1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 * 6 * The Sparx5 Chip Register Model can be browsed at this location: 7 * https://github.com/microchip-ung/sparx-5_reginfo 8 */ 9 #include <linux/module.h> 10 #include <linux/device.h> 11 #include <linux/netdevice.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_net.h> 16 #include <linux/of_mdio.h> 17 #include <net/switchdev.h> 18 #include <linux/etherdevice.h> 19 #include <linux/io.h> 20 #include <linux/printk.h> 21 #include <linux/iopoll.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 #include <linux/reset.h> 26 27 #include "sparx5_main_regs.h" 28 #include "sparx5_main.h" 29 #include "sparx5_port.h" 30 #include "sparx5_qos.h" 31 32 #define QLIM_WM(fraction) \ 33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) 34 #define IO_RANGES 3 35 36 struct initial_port_config { 37 u32 portno; 38 struct device_node *node; 39 struct sparx5_port_config conf; 40 struct phy *serdes; 41 }; 42 43 struct sparx5_ram_config { 44 void __iomem *init_reg; 45 u32 init_val; 46 }; 47 48 struct sparx5_main_io_resource { 49 enum sparx5_target id; 50 phys_addr_t offset; 51 int range; 52 }; 53 54 static const struct sparx5_main_io_resource sparx5_main_iomap[] = { 55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ 65 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */ 66 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */ 67 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */ 68 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */ 69 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */ 70 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */ 71 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */ 72 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */ 73 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */ 74 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */ 75 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */ 76 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */ 77 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */ 78 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */ 79 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */ 80 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */ 81 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */ 82 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */ 83 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */ 84 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */ 85 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */ 86 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */ 87 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */ 88 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */ 89 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */ 90 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */ 91 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */ 92 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */ 93 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */ 94 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */ 95 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */ 96 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */ 97 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */ 98 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */ 99 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */ 100 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */ 101 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */ 102 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */ 103 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */ 104 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */ 105 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */ 106 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */ 107 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */ 108 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */ 109 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */ 110 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */ 111 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */ 112 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */ 113 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */ 114 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */ 115 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */ 116 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */ 117 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */ 118 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */ 119 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */ 120 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */ 121 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */ 122 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */ 123 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */ 124 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */ 125 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */ 126 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */ 127 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */ 128 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */ 129 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */ 130 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */ 131 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */ 132 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */ 133 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */ 134 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */ 135 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */ 136 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */ 137 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */ 138 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */ 139 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */ 140 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */ 141 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */ 142 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */ 143 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */ 144 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */ 145 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */ 146 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */ 147 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */ 148 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */ 149 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */ 150 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */ 151 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */ 152 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */ 153 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */ 154 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */ 155 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */ 156 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */ 157 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */ 158 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */ 159 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */ 160 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */ 161 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */ 162 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */ 163 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */ 164 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */ 165 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */ 166 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */ 167 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */ 168 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */ 169 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */ 170 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */ 171 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */ 172 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */ 173 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */ 174 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */ 175 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */ 176 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */ 177 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */ 178 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */ 179 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */ 180 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */ 181 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */ 182 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */ 183 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */ 184 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */ 185 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */ 186 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */ 187 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */ 188 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */ 189 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */ 190 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */ 191 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */ 192 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */ 193 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */ 194 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */ 195 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */ 196 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */ 197 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */ 198 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */ 199 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */ 200 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */ 201 { TARGET_VCAP_ES2, 0x110d0000, 2 }, /* 0x6110d0000 */ 202 { TARGET_VCAP_ES0, 0x110e0000, 2 }, /* 0x6110e0000 */ 203 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */ 204 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */ 205 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */ 206 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */ 207 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */ 208 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */ 209 { TARGET_ANA_AC_SDLB, 0x11500000, 2 }, /* 0x611500000 */ 210 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */ 211 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */ 212 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */ 213 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */ 214 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ 215 }; 216 217 static int sparx5_create_targets(struct sparx5 *sparx5) 218 { 219 struct resource *iores[IO_RANGES]; 220 void __iomem *iomem[IO_RANGES]; 221 void __iomem *begin[IO_RANGES]; 222 int range_id[IO_RANGES]; 223 int idx, jdx; 224 225 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 226 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 227 228 if (idx == iomap->range) { 229 range_id[idx] = jdx; 230 idx++; 231 } 232 } 233 for (idx = 0; idx < IO_RANGES; idx++) { 234 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, 235 idx); 236 if (!iores[idx]) { 237 dev_err(sparx5->dev, "Invalid resource\n"); 238 return -EINVAL; 239 } 240 iomem[idx] = devm_ioremap(sparx5->dev, 241 iores[idx]->start, 242 resource_size(iores[idx])); 243 if (!iomem[idx]) { 244 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", 245 iores[idx]->name); 246 return -ENOMEM; 247 } 248 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; 249 } 250 for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 251 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 252 253 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; 254 } 255 return 0; 256 } 257 258 static int sparx5_create_port(struct sparx5 *sparx5, 259 struct initial_port_config *config) 260 { 261 struct sparx5_port *spx5_port; 262 struct net_device *ndev; 263 struct phylink *phylink; 264 int err; 265 266 ndev = sparx5_create_netdev(sparx5, config->portno); 267 if (IS_ERR(ndev)) { 268 dev_err(sparx5->dev, "Could not create net device: %02u\n", 269 config->portno); 270 return PTR_ERR(ndev); 271 } 272 spx5_port = netdev_priv(ndev); 273 spx5_port->of_node = config->node; 274 spx5_port->serdes = config->serdes; 275 spx5_port->pvid = NULL_VID; 276 spx5_port->signd_internal = true; 277 spx5_port->signd_active_high = true; 278 spx5_port->signd_enable = true; 279 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; 280 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; 281 spx5_port->custom_etype = 0x8880; /* Vitesse */ 282 spx5_port->phylink_pcs.poll = true; 283 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; 284 spx5_port->is_mrouter = false; 285 sparx5->ports[config->portno] = spx5_port; 286 287 err = sparx5_port_init(sparx5, spx5_port, &config->conf); 288 if (err) { 289 dev_err(sparx5->dev, "port init failed\n"); 290 return err; 291 } 292 spx5_port->conf = config->conf; 293 294 /* Setup VLAN */ 295 sparx5_vlan_port_setup(sparx5, spx5_port->portno); 296 297 /* Create a phylink for PHY management. Also handles SFPs */ 298 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; 299 spx5_port->phylink_config.type = PHYLINK_NETDEV; 300 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 301 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | 302 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; 303 304 __set_bit(PHY_INTERFACE_MODE_SGMII, 305 spx5_port->phylink_config.supported_interfaces); 306 __set_bit(PHY_INTERFACE_MODE_QSGMII, 307 spx5_port->phylink_config.supported_interfaces); 308 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 309 spx5_port->phylink_config.supported_interfaces); 310 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 311 spx5_port->phylink_config.supported_interfaces); 312 313 if (spx5_port->conf.bandwidth == SPEED_5000 || 314 spx5_port->conf.bandwidth == SPEED_10000 || 315 spx5_port->conf.bandwidth == SPEED_25000) 316 __set_bit(PHY_INTERFACE_MODE_5GBASER, 317 spx5_port->phylink_config.supported_interfaces); 318 319 if (spx5_port->conf.bandwidth == SPEED_10000 || 320 spx5_port->conf.bandwidth == SPEED_25000) 321 __set_bit(PHY_INTERFACE_MODE_10GBASER, 322 spx5_port->phylink_config.supported_interfaces); 323 324 if (spx5_port->conf.bandwidth == SPEED_25000) 325 __set_bit(PHY_INTERFACE_MODE_25GBASER, 326 spx5_port->phylink_config.supported_interfaces); 327 328 phylink = phylink_create(&spx5_port->phylink_config, 329 of_fwnode_handle(config->node), 330 config->conf.phy_mode, 331 &sparx5_phylink_mac_ops); 332 if (IS_ERR(phylink)) 333 return PTR_ERR(phylink); 334 335 spx5_port->phylink = phylink; 336 337 return 0; 338 } 339 340 static int sparx5_init_ram(struct sparx5 *s5) 341 { 342 const struct sparx5_ram_config spx5_ram_cfg[] = { 343 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET}, 344 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT}, 345 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 346 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 347 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 348 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 349 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 350 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 351 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 352 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT} 353 }; 354 const struct sparx5_ram_config *cfg; 355 u32 value, pending, jdx, idx; 356 357 for (jdx = 0; jdx < 10; jdx++) { 358 pending = ARRAY_SIZE(spx5_ram_cfg); 359 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { 360 cfg = &spx5_ram_cfg[idx]; 361 if (jdx == 0) { 362 writel(cfg->init_val, cfg->init_reg); 363 } else { 364 value = readl(cfg->init_reg); 365 if ((value & cfg->init_val) != cfg->init_val) 366 pending--; 367 } 368 } 369 if (!pending) 370 break; 371 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 372 } 373 374 if (pending > 0) { 375 /* Still initializing, should be complete in 376 * less than 1ms 377 */ 378 dev_err(s5->dev, "Memory initialization error\n"); 379 return -EINVAL; 380 } 381 return 0; 382 } 383 384 static int sparx5_init_switchcore(struct sparx5 *sparx5) 385 { 386 u32 value; 387 int err = 0; 388 389 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), 390 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 391 sparx5, 392 EACL_POL_EACL_CFG); 393 394 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), 395 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 396 sparx5, 397 EACL_POL_EACL_CFG); 398 399 /* Initialize memories, if not done already */ 400 value = spx5_rd(sparx5, HSCH_RESET_CFG); 401 if (!(value & HSCH_RESET_CFG_CORE_ENA)) { 402 err = sparx5_init_ram(sparx5); 403 if (err) 404 return err; 405 } 406 407 /* Reset counters */ 408 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); 409 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); 410 411 /* Enable switch-core and queue system */ 412 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); 413 414 return 0; 415 } 416 417 static int sparx5_init_coreclock(struct sparx5 *sparx5) 418 { 419 enum sparx5_core_clockfreq freq = sparx5->coreclock; 420 u32 clk_div, clk_period, pol_upd_int, idx; 421 422 /* Verify if core clock frequency is supported on target. 423 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported 424 * freq. is used 425 */ 426 switch (sparx5->target_ct) { 427 case SPX5_TARGET_CT_7546: 428 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 429 freq = SPX5_CORE_CLOCK_250MHZ; 430 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) 431 freq = 0; /* Not supported */ 432 break; 433 case SPX5_TARGET_CT_7549: 434 case SPX5_TARGET_CT_7552: 435 case SPX5_TARGET_CT_7556: 436 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 437 freq = SPX5_CORE_CLOCK_500MHZ; 438 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) 439 freq = 0; /* Not supported */ 440 break; 441 case SPX5_TARGET_CT_7558: 442 case SPX5_TARGET_CT_7558TSN: 443 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 444 freq = SPX5_CORE_CLOCK_625MHZ; 445 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) 446 freq = 0; /* Not supported */ 447 break; 448 case SPX5_TARGET_CT_7546TSN: 449 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 450 freq = SPX5_CORE_CLOCK_625MHZ; 451 break; 452 case SPX5_TARGET_CT_7549TSN: 453 case SPX5_TARGET_CT_7552TSN: 454 case SPX5_TARGET_CT_7556TSN: 455 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 456 freq = SPX5_CORE_CLOCK_625MHZ; 457 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) 458 freq = 0; /* Not supported */ 459 break; 460 default: 461 dev_err(sparx5->dev, "Target (%#04x) not supported\n", 462 sparx5->target_ct); 463 return -ENODEV; 464 } 465 466 switch (freq) { 467 case SPX5_CORE_CLOCK_250MHZ: 468 clk_div = 10; 469 pol_upd_int = 312; 470 break; 471 case SPX5_CORE_CLOCK_500MHZ: 472 clk_div = 5; 473 pol_upd_int = 624; 474 break; 475 case SPX5_CORE_CLOCK_625MHZ: 476 clk_div = 4; 477 pol_upd_int = 780; 478 break; 479 default: 480 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", 481 sparx5->coreclock, sparx5->target_ct); 482 return -EINVAL; 483 } 484 485 /* Update state with chosen frequency */ 486 sparx5->coreclock = freq; 487 488 /* Configure the LCPLL */ 489 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 490 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 491 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 492 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 493 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 494 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 495 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 496 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 497 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 498 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 499 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 500 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 501 sparx5, 502 CLKGEN_LCPLL1_CORE_CLK_CFG); 503 504 clk_period = sparx5_clk_period(freq); 505 506 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), 507 HSCH_SYS_CLK_PER_100PS, 508 sparx5, 509 HSCH_SYS_CLK_PER); 510 511 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 512 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, 513 sparx5, 514 ANA_AC_POL_BDLB_DLB_CTRL); 515 516 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 517 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, 518 sparx5, 519 ANA_AC_POL_SLB_DLB_CTRL); 520 521 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), 522 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, 523 sparx5, 524 LRN_AUTOAGE_CFG_1); 525 526 for (idx = 0; idx < 3; idx++) 527 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), 528 GCB_SIO_CLOCK_SYS_CLK_PERIOD, 529 sparx5, 530 GCB_SIO_CLOCK(idx)); 531 532 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET 533 ((256 * 1000) / clk_period), 534 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, 535 sparx5, 536 HSCH_TAS_STATEMACHINE_CFG); 537 538 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), 539 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, 540 sparx5, 541 ANA_AC_POL_POL_UPD_INT_CFG); 542 543 return 0; 544 } 545 546 static int sparx5_qlim_set(struct sparx5 *sparx5) 547 { 548 u32 res, dp, prio; 549 550 for (res = 0; res < 2; res++) { 551 for (prio = 0; prio < 8; prio++) 552 spx5_wr(0xFFF, sparx5, 553 QRES_RES_CFG(prio + 630 + res * 1024)); 554 555 for (dp = 0; dp < 4; dp++) 556 spx5_wr(0xFFF, sparx5, 557 QRES_RES_CFG(dp + 638 + res * 1024)); 558 } 559 560 /* Set 80,90,95,100% of memory size for top watermarks */ 561 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 562 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 563 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 564 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 565 566 return 0; 567 } 568 569 /* Some boards needs to map the SGPIO for signal detect explicitly to the 570 * port module 571 */ 572 static void sparx5_board_init(struct sparx5 *sparx5) 573 { 574 int idx; 575 576 if (!sparx5->sd_sgpio_remapping) 577 return; 578 579 /* Enable SGPIO Signal Detect remapping */ 580 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 581 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 582 sparx5, 583 GCB_HW_SGPIO_SD_CFG); 584 585 /* Refer to LOS SGPIO */ 586 for (idx = 0; idx < SPX5_PORTS; idx++) 587 if (sparx5->ports[idx]) 588 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) 589 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, 590 sparx5, 591 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx)); 592 } 593 594 static int sparx5_start(struct sparx5 *sparx5) 595 { 596 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 597 char queue_name[32]; 598 u32 idx; 599 int err; 600 601 /* Setup own UPSIDs */ 602 for (idx = 0; idx < 3; idx++) { 603 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); 604 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); 605 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); 606 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); 607 } 608 609 /* Enable CPU ports */ 610 for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) 611 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), 612 QFWD_SWITCH_PORT_MODE_PORT_ENA, 613 sparx5, 614 QFWD_SWITCH_PORT_MODE(idx)); 615 616 /* Init masks */ 617 sparx5_update_fwd(sparx5); 618 619 /* CPU copy CPU pgids */ 620 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 621 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); 622 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 623 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); 624 625 /* Recalc injected frame FCS */ 626 for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) 627 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), 628 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, 629 sparx5, ANA_CL_FILTER_CTRL(idx)); 630 631 /* Init MAC table, ageing */ 632 sparx5_mact_init(sparx5); 633 634 /* Init PGID table arbitrator */ 635 sparx5_pgid_init(sparx5); 636 637 /* Setup VLANs */ 638 sparx5_vlan_init(sparx5); 639 640 /* Add host mode BC address (points only to CPU) */ 641 sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); 642 643 /* Enable queue limitation watermarks */ 644 sparx5_qlim_set(sparx5); 645 646 err = sparx5_config_auto_calendar(sparx5); 647 if (err) 648 return err; 649 650 err = sparx5_config_dsm_calendar(sparx5); 651 if (err) 652 return err; 653 654 /* Init stats */ 655 err = sparx_stats_init(sparx5); 656 if (err) 657 return err; 658 659 /* Init mact_sw struct */ 660 mutex_init(&sparx5->mact_lock); 661 INIT_LIST_HEAD(&sparx5->mact_entries); 662 snprintf(queue_name, sizeof(queue_name), "%s-mact", 663 dev_name(sparx5->dev)); 664 sparx5->mact_queue = create_singlethread_workqueue(queue_name); 665 if (!sparx5->mact_queue) 666 return -ENOMEM; 667 668 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); 669 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, 670 SPX5_MACT_PULL_DELAY); 671 672 mutex_init(&sparx5->mdb_lock); 673 INIT_LIST_HEAD(&sparx5->mdb_entries); 674 675 err = sparx5_register_netdevs(sparx5); 676 if (err) 677 return err; 678 679 sparx5_board_init(sparx5); 680 err = sparx5_register_notifier_blocks(sparx5); 681 if (err) 682 return err; 683 684 err = sparx5_vcap_init(sparx5); 685 if (err) { 686 sparx5_unregister_notifier_blocks(sparx5); 687 return err; 688 } 689 690 /* Start Frame DMA with fallback to register based INJ/XTR */ 691 err = -ENXIO; 692 if (sparx5->fdma_irq >= 0) { 693 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) 694 err = devm_request_threaded_irq(sparx5->dev, 695 sparx5->fdma_irq, 696 NULL, 697 sparx5_fdma_handler, 698 IRQF_ONESHOT, 699 "sparx5-fdma", sparx5); 700 if (!err) 701 err = sparx5_fdma_start(sparx5); 702 if (err) 703 sparx5->fdma_irq = -ENXIO; 704 } else { 705 sparx5->fdma_irq = -ENXIO; 706 } 707 if (err && sparx5->xtr_irq >= 0) { 708 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, 709 sparx5_xtr_handler, IRQF_SHARED, 710 "sparx5-xtr", sparx5); 711 if (!err) 712 err = sparx5_manual_injection_mode(sparx5); 713 if (err) 714 sparx5->xtr_irq = -ENXIO; 715 } else { 716 sparx5->xtr_irq = -ENXIO; 717 } 718 719 if (sparx5->ptp_irq >= 0) { 720 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, 721 NULL, sparx5_ptp_irq_handler, 722 IRQF_ONESHOT, "sparx5-ptp", 723 sparx5); 724 if (err) 725 sparx5->ptp_irq = -ENXIO; 726 727 sparx5->ptp = 1; 728 } 729 730 return err; 731 } 732 733 static void sparx5_cleanup_ports(struct sparx5 *sparx5) 734 { 735 sparx5_unregister_netdevs(sparx5); 736 sparx5_destroy_netdevs(sparx5); 737 } 738 739 static int mchp_sparx5_probe(struct platform_device *pdev) 740 { 741 struct initial_port_config *configs, *config; 742 struct device_node *np = pdev->dev.of_node; 743 struct device_node *ports, *portnp; 744 struct reset_control *reset; 745 struct sparx5 *sparx5; 746 int idx = 0, err = 0; 747 748 if (!np && !pdev->dev.platform_data) 749 return -ENODEV; 750 751 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); 752 if (!sparx5) 753 return -ENOMEM; 754 755 platform_set_drvdata(pdev, sparx5); 756 sparx5->pdev = pdev; 757 sparx5->dev = &pdev->dev; 758 759 /* Do switch core reset if available */ 760 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 761 if (IS_ERR(reset)) 762 return dev_err_probe(&pdev->dev, PTR_ERR(reset), 763 "Failed to get switch reset controller.\n"); 764 reset_control_reset(reset); 765 766 /* Default values, some from DT */ 767 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; 768 769 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL); 770 771 ports = of_get_child_by_name(np, "ethernet-ports"); 772 if (!ports) { 773 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); 774 return -ENODEV; 775 } 776 sparx5->port_count = of_get_child_count(ports); 777 778 configs = kcalloc(sparx5->port_count, 779 sizeof(struct initial_port_config), GFP_KERNEL); 780 if (!configs) { 781 err = -ENOMEM; 782 goto cleanup_pnode; 783 } 784 785 for_each_available_child_of_node(ports, portnp) { 786 struct sparx5_port_config *conf; 787 struct phy *serdes; 788 u32 portno; 789 790 err = of_property_read_u32(portnp, "reg", &portno); 791 if (err) { 792 dev_err(sparx5->dev, "port reg property error\n"); 793 continue; 794 } 795 config = &configs[idx]; 796 conf = &config->conf; 797 conf->speed = SPEED_UNKNOWN; 798 conf->bandwidth = SPEED_UNKNOWN; 799 err = of_get_phy_mode(portnp, &conf->phy_mode); 800 if (err) { 801 dev_err(sparx5->dev, "port %u: missing phy-mode\n", 802 portno); 803 continue; 804 } 805 err = of_property_read_u32(portnp, "microchip,bandwidth", 806 &conf->bandwidth); 807 if (err) { 808 dev_err(sparx5->dev, "port %u: missing bandwidth\n", 809 portno); 810 continue; 811 } 812 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); 813 if (err) 814 conf->sd_sgpio = ~0; 815 else 816 sparx5->sd_sgpio_remapping = true; 817 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); 818 if (IS_ERR(serdes)) { 819 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), 820 "port %u: missing serdes\n", 821 portno); 822 of_node_put(portnp); 823 goto cleanup_config; 824 } 825 config->portno = portno; 826 config->node = portnp; 827 config->serdes = serdes; 828 829 conf->media = PHY_MEDIA_DAC; 830 conf->serdes_reset = true; 831 conf->portmode = conf->phy_mode; 832 conf->power_down = true; 833 idx++; 834 } 835 836 err = sparx5_create_targets(sparx5); 837 if (err) 838 goto cleanup_config; 839 840 if (of_get_mac_address(np, sparx5->base_mac)) { 841 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); 842 eth_random_addr(sparx5->base_mac); 843 sparx5->base_mac[5] = 0; 844 } 845 846 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); 847 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); 848 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp"); 849 850 /* Read chip ID to check CPU interface */ 851 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); 852 853 sparx5->target_ct = (enum spx5_target_chiptype) 854 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); 855 856 /* Initialize Switchcore and internal RAMs */ 857 err = sparx5_init_switchcore(sparx5); 858 if (err) { 859 dev_err(sparx5->dev, "Switchcore initialization error\n"); 860 goto cleanup_config; 861 } 862 863 /* Initialize the LC-PLL (core clock) and set affected registers */ 864 err = sparx5_init_coreclock(sparx5); 865 if (err) { 866 dev_err(sparx5->dev, "LC-PLL initialization error\n"); 867 goto cleanup_config; 868 } 869 870 for (idx = 0; idx < sparx5->port_count; ++idx) { 871 config = &configs[idx]; 872 if (!config->node) 873 continue; 874 875 err = sparx5_create_port(sparx5, config); 876 if (err) { 877 dev_err(sparx5->dev, "port create error\n"); 878 goto cleanup_ports; 879 } 880 } 881 882 err = sparx5_start(sparx5); 883 if (err) { 884 dev_err(sparx5->dev, "Start failed\n"); 885 goto cleanup_ports; 886 } 887 888 err = sparx5_qos_init(sparx5); 889 if (err) { 890 dev_err(sparx5->dev, "Failed to initialize QoS\n"); 891 goto cleanup_ports; 892 } 893 894 err = sparx5_ptp_init(sparx5); 895 if (err) { 896 dev_err(sparx5->dev, "PTP failed\n"); 897 goto cleanup_ports; 898 } 899 goto cleanup_config; 900 901 cleanup_ports: 902 sparx5_cleanup_ports(sparx5); 903 if (sparx5->mact_queue) 904 destroy_workqueue(sparx5->mact_queue); 905 cleanup_config: 906 kfree(configs); 907 cleanup_pnode: 908 of_node_put(ports); 909 return err; 910 } 911 912 static int mchp_sparx5_remove(struct platform_device *pdev) 913 { 914 struct sparx5 *sparx5 = platform_get_drvdata(pdev); 915 916 debugfs_remove_recursive(sparx5->debugfs_root); 917 if (sparx5->xtr_irq) { 918 disable_irq(sparx5->xtr_irq); 919 sparx5->xtr_irq = -ENXIO; 920 } 921 if (sparx5->fdma_irq) { 922 disable_irq(sparx5->fdma_irq); 923 sparx5->fdma_irq = -ENXIO; 924 } 925 sparx5_ptp_deinit(sparx5); 926 sparx5_fdma_stop(sparx5); 927 sparx5_cleanup_ports(sparx5); 928 sparx5_vcap_destroy(sparx5); 929 /* Unregister netdevs */ 930 sparx5_unregister_notifier_blocks(sparx5); 931 destroy_workqueue(sparx5->mact_queue); 932 933 return 0; 934 } 935 936 static const struct of_device_id mchp_sparx5_match[] = { 937 { .compatible = "microchip,sparx5-switch" }, 938 { } 939 }; 940 MODULE_DEVICE_TABLE(of, mchp_sparx5_match); 941 942 static struct platform_driver mchp_sparx5_driver = { 943 .probe = mchp_sparx5_probe, 944 .remove = mchp_sparx5_remove, 945 .driver = { 946 .name = "sparx5-switch", 947 .of_match_table = mchp_sparx5_match, 948 }, 949 }; 950 951 module_platform_driver(mchp_sparx5_driver); 952 953 MODULE_DESCRIPTION("Microchip Sparx5 switch driver"); 954 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); 955 MODULE_LICENSE("Dual MIT/GPL"); 956