1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 * 6 * The Sparx5 Chip Register Model can be browsed at this location: 7 * https://github.com/microchip-ung/sparx-5_reginfo 8 */ 9 #include <linux/module.h> 10 #include <linux/device.h> 11 #include <linux/netdevice.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_net.h> 16 #include <linux/of_mdio.h> 17 #include <net/switchdev.h> 18 #include <linux/etherdevice.h> 19 #include <linux/io.h> 20 #include <linux/printk.h> 21 #include <linux/iopoll.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 #include <linux/reset.h> 26 27 #include "sparx5_main_regs.h" 28 #include "sparx5_main.h" 29 #include "sparx5_port.h" 30 31 #define QLIM_WM(fraction) \ 32 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) 33 #define IO_RANGES 3 34 35 struct initial_port_config { 36 u32 portno; 37 struct device_node *node; 38 struct sparx5_port_config conf; 39 struct phy *serdes; 40 }; 41 42 struct sparx5_ram_config { 43 void __iomem *init_reg; 44 u32 init_val; 45 }; 46 47 struct sparx5_main_io_resource { 48 enum sparx5_target id; 49 phys_addr_t offset; 50 int range; 51 }; 52 53 static const struct sparx5_main_io_resource sparx5_main_iomap[] = { 54 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 55 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 56 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 57 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 58 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 59 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 60 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 61 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 62 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 63 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ 64 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */ 65 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */ 66 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */ 67 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */ 68 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */ 69 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */ 70 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */ 71 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */ 72 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */ 73 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */ 74 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */ 75 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */ 76 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */ 77 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */ 78 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */ 79 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */ 80 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */ 81 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */ 82 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */ 83 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */ 84 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */ 85 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */ 86 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */ 87 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */ 88 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */ 89 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */ 90 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */ 91 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */ 92 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */ 93 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */ 94 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */ 95 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */ 96 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */ 97 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */ 98 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */ 99 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */ 100 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */ 101 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */ 102 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */ 103 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */ 104 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */ 105 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */ 106 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */ 107 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */ 108 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */ 109 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */ 110 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */ 111 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */ 112 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */ 113 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */ 114 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */ 115 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */ 116 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */ 117 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */ 118 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */ 119 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */ 120 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */ 121 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */ 122 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */ 123 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */ 124 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */ 125 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */ 126 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */ 127 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */ 128 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */ 129 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */ 130 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */ 131 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */ 132 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */ 133 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */ 134 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */ 135 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */ 136 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */ 137 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */ 138 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */ 139 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */ 140 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */ 141 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */ 142 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */ 143 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */ 144 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */ 145 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */ 146 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */ 147 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */ 148 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */ 149 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */ 150 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */ 151 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */ 152 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */ 153 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */ 154 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */ 155 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */ 156 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */ 157 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */ 158 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */ 159 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */ 160 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */ 161 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */ 162 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */ 163 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */ 164 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */ 165 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */ 166 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */ 167 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */ 168 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */ 169 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */ 170 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */ 171 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */ 172 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */ 173 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */ 174 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */ 175 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */ 176 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */ 177 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */ 178 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */ 179 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */ 180 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */ 181 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */ 182 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */ 183 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */ 184 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */ 185 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */ 186 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */ 187 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */ 188 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */ 189 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */ 190 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */ 191 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */ 192 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */ 193 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */ 194 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */ 195 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */ 196 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */ 197 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */ 198 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */ 199 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */ 200 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */ 201 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */ 202 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */ 203 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */ 204 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */ 205 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */ 206 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */ 207 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */ 208 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */ 209 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ 210 }; 211 212 static int sparx5_create_targets(struct sparx5 *sparx5) 213 { 214 struct resource *iores[IO_RANGES]; 215 void __iomem *iomem[IO_RANGES]; 216 void __iomem *begin[IO_RANGES]; 217 int range_id[IO_RANGES]; 218 int idx, jdx; 219 220 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 221 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 222 223 if (idx == iomap->range) { 224 range_id[idx] = jdx; 225 idx++; 226 } 227 } 228 for (idx = 0; idx < IO_RANGES; idx++) { 229 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, 230 idx); 231 if (!iores[idx]) { 232 dev_err(sparx5->dev, "Invalid resource\n"); 233 return -EINVAL; 234 } 235 iomem[idx] = devm_ioremap(sparx5->dev, 236 iores[idx]->start, 237 resource_size(iores[idx])); 238 if (!iomem[idx]) { 239 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", 240 iores[idx]->name); 241 return -ENOMEM; 242 } 243 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; 244 } 245 for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 246 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 247 248 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; 249 } 250 return 0; 251 } 252 253 static int sparx5_create_port(struct sparx5 *sparx5, 254 struct initial_port_config *config) 255 { 256 struct sparx5_port *spx5_port; 257 struct net_device *ndev; 258 struct phylink *phylink; 259 int err; 260 261 ndev = sparx5_create_netdev(sparx5, config->portno); 262 if (IS_ERR(ndev)) { 263 dev_err(sparx5->dev, "Could not create net device: %02u\n", 264 config->portno); 265 return PTR_ERR(ndev); 266 } 267 spx5_port = netdev_priv(ndev); 268 spx5_port->of_node = config->node; 269 spx5_port->serdes = config->serdes; 270 spx5_port->pvid = NULL_VID; 271 spx5_port->signd_internal = true; 272 spx5_port->signd_active_high = true; 273 spx5_port->signd_enable = true; 274 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; 275 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; 276 spx5_port->custom_etype = 0x8880; /* Vitesse */ 277 spx5_port->phylink_pcs.poll = true; 278 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; 279 sparx5->ports[config->portno] = spx5_port; 280 281 err = sparx5_port_init(sparx5, spx5_port, &config->conf); 282 if (err) { 283 dev_err(sparx5->dev, "port init failed\n"); 284 return err; 285 } 286 spx5_port->conf = config->conf; 287 288 /* Setup VLAN */ 289 sparx5_vlan_port_setup(sparx5, spx5_port->portno); 290 291 /* Create a phylink for PHY management. Also handles SFPs */ 292 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; 293 spx5_port->phylink_config.type = PHYLINK_NETDEV; 294 spx5_port->phylink_config.pcs_poll = true; 295 296 phylink = phylink_create(&spx5_port->phylink_config, 297 of_fwnode_handle(config->node), 298 config->conf.phy_mode, 299 &sparx5_phylink_mac_ops); 300 if (IS_ERR(phylink)) 301 return PTR_ERR(phylink); 302 303 spx5_port->phylink = phylink; 304 phylink_set_pcs(phylink, &spx5_port->phylink_pcs); 305 306 return 0; 307 } 308 309 static int sparx5_init_ram(struct sparx5 *s5) 310 { 311 const struct sparx5_ram_config spx5_ram_cfg[] = { 312 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET}, 313 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT}, 314 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 315 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 316 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 317 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 318 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 319 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 320 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 321 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT} 322 }; 323 const struct sparx5_ram_config *cfg; 324 u32 value, pending, jdx, idx; 325 326 for (jdx = 0; jdx < 10; jdx++) { 327 pending = ARRAY_SIZE(spx5_ram_cfg); 328 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { 329 cfg = &spx5_ram_cfg[idx]; 330 if (jdx == 0) { 331 writel(cfg->init_val, cfg->init_reg); 332 } else { 333 value = readl(cfg->init_reg); 334 if ((value & cfg->init_val) != cfg->init_val) 335 pending--; 336 } 337 } 338 if (!pending) 339 break; 340 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 341 } 342 343 if (pending > 0) { 344 /* Still initializing, should be complete in 345 * less than 1ms 346 */ 347 dev_err(s5->dev, "Memory initialization error\n"); 348 return -EINVAL; 349 } 350 return 0; 351 } 352 353 static int sparx5_init_switchcore(struct sparx5 *sparx5) 354 { 355 u32 value; 356 int err = 0; 357 358 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), 359 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 360 sparx5, 361 EACL_POL_EACL_CFG); 362 363 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), 364 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 365 sparx5, 366 EACL_POL_EACL_CFG); 367 368 /* Initialize memories, if not done already */ 369 value = spx5_rd(sparx5, HSCH_RESET_CFG); 370 if (!(value & HSCH_RESET_CFG_CORE_ENA)) { 371 err = sparx5_init_ram(sparx5); 372 if (err) 373 return err; 374 } 375 376 /* Reset counters */ 377 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); 378 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); 379 380 /* Enable switch-core and queue system */ 381 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); 382 383 return 0; 384 } 385 386 static int sparx5_init_coreclock(struct sparx5 *sparx5) 387 { 388 enum sparx5_core_clockfreq freq = sparx5->coreclock; 389 u32 clk_div, clk_period, pol_upd_int, idx; 390 391 /* Verify if core clock frequency is supported on target. 392 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported 393 * freq. is used 394 */ 395 switch (sparx5->target_ct) { 396 case SPX5_TARGET_CT_7546: 397 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 398 freq = SPX5_CORE_CLOCK_250MHZ; 399 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) 400 freq = 0; /* Not supported */ 401 break; 402 case SPX5_TARGET_CT_7549: 403 case SPX5_TARGET_CT_7552: 404 case SPX5_TARGET_CT_7556: 405 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 406 freq = SPX5_CORE_CLOCK_500MHZ; 407 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) 408 freq = 0; /* Not supported */ 409 break; 410 case SPX5_TARGET_CT_7558: 411 case SPX5_TARGET_CT_7558TSN: 412 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 413 freq = SPX5_CORE_CLOCK_625MHZ; 414 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) 415 freq = 0; /* Not supported */ 416 break; 417 case SPX5_TARGET_CT_7546TSN: 418 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 419 freq = SPX5_CORE_CLOCK_625MHZ; 420 break; 421 case SPX5_TARGET_CT_7549TSN: 422 case SPX5_TARGET_CT_7552TSN: 423 case SPX5_TARGET_CT_7556TSN: 424 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 425 freq = SPX5_CORE_CLOCK_625MHZ; 426 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) 427 freq = 0; /* Not supported */ 428 break; 429 default: 430 dev_err(sparx5->dev, "Target (%#04x) not supported\n", 431 sparx5->target_ct); 432 return -ENODEV; 433 } 434 435 switch (freq) { 436 case SPX5_CORE_CLOCK_250MHZ: 437 clk_div = 10; 438 pol_upd_int = 312; 439 break; 440 case SPX5_CORE_CLOCK_500MHZ: 441 clk_div = 5; 442 pol_upd_int = 624; 443 break; 444 case SPX5_CORE_CLOCK_625MHZ: 445 clk_div = 4; 446 pol_upd_int = 780; 447 break; 448 default: 449 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", 450 sparx5->coreclock, sparx5->target_ct); 451 return -EINVAL; 452 } 453 454 /* Update state with chosen frequency */ 455 sparx5->coreclock = freq; 456 457 /* Configure the LCPLL */ 458 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 459 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 460 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 461 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 462 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 463 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 464 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 465 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 466 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 467 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 468 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 469 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 470 sparx5, 471 CLKGEN_LCPLL1_CORE_CLK_CFG); 472 473 clk_period = sparx5_clk_period(freq); 474 475 spx5_rmw(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(clk_period / 100), 476 HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, 477 sparx5, 478 HSCH_SYS_CLK_PER); 479 480 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 481 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, 482 sparx5, 483 ANA_AC_POL_BDLB_DLB_CTRL); 484 485 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 486 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, 487 sparx5, 488 ANA_AC_POL_SLB_DLB_CTRL); 489 490 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), 491 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, 492 sparx5, 493 LRN_AUTOAGE_CFG_1); 494 495 for (idx = 0; idx < 3; idx++) 496 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), 497 GCB_SIO_CLOCK_SYS_CLK_PERIOD, 498 sparx5, 499 GCB_SIO_CLOCK(idx)); 500 501 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET 502 ((256 * 1000) / clk_period), 503 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, 504 sparx5, 505 HSCH_TAS_STATEMACHINE_CFG); 506 507 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), 508 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, 509 sparx5, 510 ANA_AC_POL_POL_UPD_INT_CFG); 511 512 return 0; 513 } 514 515 static int sparx5_qlim_set(struct sparx5 *sparx5) 516 { 517 u32 res, dp, prio; 518 519 for (res = 0; res < 2; res++) { 520 for (prio = 0; prio < 8; prio++) 521 spx5_wr(0xFFF, sparx5, 522 QRES_RES_CFG(prio + 630 + res * 1024)); 523 524 for (dp = 0; dp < 4; dp++) 525 spx5_wr(0xFFF, sparx5, 526 QRES_RES_CFG(dp + 638 + res * 1024)); 527 } 528 529 /* Set 80,90,95,100% of memory size for top watermarks */ 530 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 531 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 532 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 533 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 534 535 return 0; 536 } 537 538 /* Some boards needs to map the SGPIO for signal detect explicitly to the 539 * port module 540 */ 541 static void sparx5_board_init(struct sparx5 *sparx5) 542 { 543 int idx; 544 545 if (!sparx5->sd_sgpio_remapping) 546 return; 547 548 /* Enable SGPIO Signal Detect remapping */ 549 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 550 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 551 sparx5, 552 GCB_HW_SGPIO_SD_CFG); 553 554 /* Refer to LOS SGPIO */ 555 for (idx = 0; idx < SPX5_PORTS; idx++) 556 if (sparx5->ports[idx]) 557 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) 558 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, 559 sparx5, 560 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx)); 561 } 562 563 static int sparx5_start(struct sparx5 *sparx5) 564 { 565 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 566 char queue_name[32]; 567 u32 idx; 568 int err; 569 570 /* Setup own UPSIDs */ 571 for (idx = 0; idx < 3; idx++) { 572 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); 573 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); 574 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); 575 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); 576 } 577 578 /* Enable CPU ports */ 579 for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) 580 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), 581 QFWD_SWITCH_PORT_MODE_PORT_ENA, 582 sparx5, 583 QFWD_SWITCH_PORT_MODE(idx)); 584 585 /* Init masks */ 586 sparx5_update_fwd(sparx5); 587 588 /* CPU copy CPU pgids */ 589 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 590 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); 591 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 592 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); 593 594 /* Recalc injected frame FCS */ 595 for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) 596 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), 597 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, 598 sparx5, ANA_CL_FILTER_CTRL(idx)); 599 600 /* Init MAC table, ageing */ 601 sparx5_mact_init(sparx5); 602 603 /* Setup VLANs */ 604 sparx5_vlan_init(sparx5); 605 606 /* Add host mode BC address (points only to CPU) */ 607 sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); 608 609 /* Enable queue limitation watermarks */ 610 sparx5_qlim_set(sparx5); 611 612 err = sparx5_config_auto_calendar(sparx5); 613 if (err) 614 return err; 615 616 err = sparx5_config_dsm_calendar(sparx5); 617 if (err) 618 return err; 619 620 /* Init stats */ 621 err = sparx_stats_init(sparx5); 622 if (err) 623 return err; 624 625 /* Init mact_sw struct */ 626 mutex_init(&sparx5->mact_lock); 627 INIT_LIST_HEAD(&sparx5->mact_entries); 628 snprintf(queue_name, sizeof(queue_name), "%s-mact", 629 dev_name(sparx5->dev)); 630 sparx5->mact_queue = create_singlethread_workqueue(queue_name); 631 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); 632 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, 633 SPX5_MACT_PULL_DELAY); 634 635 err = sparx5_register_netdevs(sparx5); 636 if (err) 637 return err; 638 639 sparx5_board_init(sparx5); 640 err = sparx5_register_notifier_blocks(sparx5); 641 642 /* Start Frame DMA with fallback to register based INJ/XTR */ 643 err = -ENXIO; 644 if (sparx5->fdma_irq >= 0) { 645 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) 646 err = devm_request_threaded_irq(sparx5->dev, 647 sparx5->fdma_irq, 648 NULL, 649 sparx5_fdma_handler, 650 IRQF_ONESHOT, 651 "sparx5-fdma", sparx5); 652 if (!err) 653 err = sparx5_fdma_start(sparx5); 654 if (err) 655 sparx5->fdma_irq = -ENXIO; 656 } else { 657 sparx5->fdma_irq = -ENXIO; 658 } 659 if (err && sparx5->xtr_irq >= 0) { 660 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, 661 sparx5_xtr_handler, IRQF_SHARED, 662 "sparx5-xtr", sparx5); 663 if (!err) 664 err = sparx5_manual_injection_mode(sparx5); 665 if (err) 666 sparx5->xtr_irq = -ENXIO; 667 } else { 668 sparx5->xtr_irq = -ENXIO; 669 } 670 return err; 671 } 672 673 static void sparx5_cleanup_ports(struct sparx5 *sparx5) 674 { 675 sparx5_unregister_netdevs(sparx5); 676 sparx5_destroy_netdevs(sparx5); 677 } 678 679 static int mchp_sparx5_probe(struct platform_device *pdev) 680 { 681 struct initial_port_config *configs, *config; 682 struct device_node *np = pdev->dev.of_node; 683 struct device_node *ports, *portnp; 684 struct reset_control *reset; 685 struct sparx5 *sparx5; 686 int idx = 0, err = 0; 687 688 if (!np && !pdev->dev.platform_data) 689 return -ENODEV; 690 691 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); 692 if (!sparx5) 693 return -ENOMEM; 694 695 platform_set_drvdata(pdev, sparx5); 696 sparx5->pdev = pdev; 697 sparx5->dev = &pdev->dev; 698 699 /* Do switch core reset if available */ 700 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 701 if (IS_ERR(reset)) 702 return dev_err_probe(&pdev->dev, PTR_ERR(reset), 703 "Failed to get switch reset controller.\n"); 704 reset_control_reset(reset); 705 706 /* Default values, some from DT */ 707 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; 708 709 ports = of_get_child_by_name(np, "ethernet-ports"); 710 if (!ports) { 711 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); 712 return -ENODEV; 713 } 714 sparx5->port_count = of_get_child_count(ports); 715 716 configs = kcalloc(sparx5->port_count, 717 sizeof(struct initial_port_config), GFP_KERNEL); 718 if (!configs) { 719 err = -ENOMEM; 720 goto cleanup_pnode; 721 } 722 723 for_each_available_child_of_node(ports, portnp) { 724 struct sparx5_port_config *conf; 725 struct phy *serdes; 726 u32 portno; 727 728 err = of_property_read_u32(portnp, "reg", &portno); 729 if (err) { 730 dev_err(sparx5->dev, "port reg property error\n"); 731 continue; 732 } 733 config = &configs[idx]; 734 conf = &config->conf; 735 conf->speed = SPEED_UNKNOWN; 736 conf->bandwidth = SPEED_UNKNOWN; 737 err = of_get_phy_mode(portnp, &conf->phy_mode); 738 if (err) { 739 dev_err(sparx5->dev, "port %u: missing phy-mode\n", 740 portno); 741 continue; 742 } 743 err = of_property_read_u32(portnp, "microchip,bandwidth", 744 &conf->bandwidth); 745 if (err) { 746 dev_err(sparx5->dev, "port %u: missing bandwidth\n", 747 portno); 748 continue; 749 } 750 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); 751 if (err) 752 conf->sd_sgpio = ~0; 753 else 754 sparx5->sd_sgpio_remapping = true; 755 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); 756 if (IS_ERR(serdes)) { 757 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), 758 "port %u: missing serdes\n", 759 portno); 760 of_node_put(portnp); 761 goto cleanup_config; 762 } 763 config->portno = portno; 764 config->node = portnp; 765 config->serdes = serdes; 766 767 conf->media = PHY_MEDIA_DAC; 768 conf->serdes_reset = true; 769 conf->portmode = conf->phy_mode; 770 conf->power_down = true; 771 idx++; 772 } 773 774 err = sparx5_create_targets(sparx5); 775 if (err) 776 goto cleanup_config; 777 778 if (!of_get_mac_address(np, sparx5->base_mac)) { 779 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); 780 eth_random_addr(sparx5->base_mac); 781 sparx5->base_mac[5] = 0; 782 } 783 784 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); 785 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); 786 787 /* Read chip ID to check CPU interface */ 788 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); 789 790 sparx5->target_ct = (enum spx5_target_chiptype) 791 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); 792 793 /* Initialize Switchcore and internal RAMs */ 794 err = sparx5_init_switchcore(sparx5); 795 if (err) { 796 dev_err(sparx5->dev, "Switchcore initialization error\n"); 797 goto cleanup_config; 798 } 799 800 /* Initialize the LC-PLL (core clock) and set affected registers */ 801 err = sparx5_init_coreclock(sparx5); 802 if (err) { 803 dev_err(sparx5->dev, "LC-PLL initialization error\n"); 804 goto cleanup_config; 805 } 806 807 for (idx = 0; idx < sparx5->port_count; ++idx) { 808 config = &configs[idx]; 809 if (!config->node) 810 continue; 811 812 err = sparx5_create_port(sparx5, config); 813 if (err) { 814 dev_err(sparx5->dev, "port create error\n"); 815 goto cleanup_ports; 816 } 817 } 818 819 err = sparx5_start(sparx5); 820 if (err) { 821 dev_err(sparx5->dev, "Start failed\n"); 822 goto cleanup_ports; 823 } 824 goto cleanup_config; 825 826 cleanup_ports: 827 sparx5_cleanup_ports(sparx5); 828 cleanup_config: 829 kfree(configs); 830 cleanup_pnode: 831 of_node_put(ports); 832 return err; 833 } 834 835 static int mchp_sparx5_remove(struct platform_device *pdev) 836 { 837 struct sparx5 *sparx5 = platform_get_drvdata(pdev); 838 839 if (sparx5->xtr_irq) { 840 disable_irq(sparx5->xtr_irq); 841 sparx5->xtr_irq = -ENXIO; 842 } 843 if (sparx5->fdma_irq) { 844 disable_irq(sparx5->fdma_irq); 845 sparx5->fdma_irq = -ENXIO; 846 } 847 sparx5_fdma_stop(sparx5); 848 sparx5_cleanup_ports(sparx5); 849 /* Unregister netdevs */ 850 sparx5_unregister_notifier_blocks(sparx5); 851 852 return 0; 853 } 854 855 static const struct of_device_id mchp_sparx5_match[] = { 856 { .compatible = "microchip,sparx5-switch" }, 857 { } 858 }; 859 MODULE_DEVICE_TABLE(of, mchp_sparx5_match); 860 861 static struct platform_driver mchp_sparx5_driver = { 862 .probe = mchp_sparx5_probe, 863 .remove = mchp_sparx5_remove, 864 .driver = { 865 .name = "sparx5-switch", 866 .of_match_table = mchp_sparx5_match, 867 }, 868 }; 869 870 module_platform_driver(mchp_sparx5_driver); 871 872 MODULE_DESCRIPTION("Microchip Sparx5 switch driver"); 873 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); 874 MODULE_LICENSE("Dual MIT/GPL"); 875