1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_FDMA = 21, 21 TARGET_GCB = 27, 22 TARGET_ORG = 36, 23 TARGET_PTP = 41, 24 TARGET_QS = 42, 25 TARGET_QSYS = 46, 26 TARGET_REW = 47, 27 TARGET_SYS = 52, 28 NUM_TARGETS = 66 29 }; 30 31 #define __REG(...) __VA_ARGS__ 32 33 /* AFI:PORT_TBL:PORT_FRM_OUT */ 34 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 35 36 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 38 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 39 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 40 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 41 42 /* AFI:PORT_TBL:PORT_CFG */ 43 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 44 45 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 47 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 48 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 49 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 50 51 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 52 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 53 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 54 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 55 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 56 57 /* ANA:ANA:ADVLEARN */ 58 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 59 60 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 61 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 62 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 63 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 64 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 65 66 /* ANA:ANA:VLANMASK */ 67 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 68 69 /* ANA:ANA:ANAINTR */ 70 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 71 72 #define ANA_ANAINTR_INTR BIT(1) 73 #define ANA_ANAINTR_INTR_SET(x)\ 74 FIELD_PREP(ANA_ANAINTR_INTR, x) 75 #define ANA_ANAINTR_INTR_GET(x)\ 76 FIELD_GET(ANA_ANAINTR_INTR, x) 77 78 #define ANA_ANAINTR_INTR_ENA BIT(0) 79 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 80 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 81 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 82 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 83 84 /* ANA:ANA:AUTOAGE */ 85 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 86 87 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 88 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 89 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 90 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 91 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 92 93 /* ANA:ANA:FLOODING */ 94 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 95 96 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 97 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 98 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 99 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 100 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 101 102 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 103 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 104 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 105 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 106 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 107 108 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 109 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 110 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 111 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 112 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 113 114 /* ANA:ANA:FLOODING_IPMC */ 115 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 116 117 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 118 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 119 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 120 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 121 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 122 123 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 124 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 125 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 126 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 127 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 128 129 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 130 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 131 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 132 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 133 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 134 135 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 136 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 137 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 138 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 139 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 140 141 /* ANA:PGID:PGID */ 142 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 143 144 #define ANA_PGID_PGID GENMASK(8, 0) 145 #define ANA_PGID_PGID_SET(x)\ 146 FIELD_PREP(ANA_PGID_PGID, x) 147 #define ANA_PGID_PGID_GET(x)\ 148 FIELD_GET(ANA_PGID_PGID, x) 149 150 /* ANA:PGID:PGID_CFG */ 151 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 152 153 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 154 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 155 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 156 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 157 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 158 159 /* ANA:ANA_TABLES:MACHDATA */ 160 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 161 162 /* ANA:ANA_TABLES:MACLDATA */ 163 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 164 165 /* ANA:ANA_TABLES:MACACCESS */ 166 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 167 168 #define ANA_MACACCESS_CHANGE2SW BIT(17) 169 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 170 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 171 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 172 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 173 174 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 175 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 176 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 177 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 178 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 179 180 #define ANA_MACACCESS_VALID BIT(12) 181 #define ANA_MACACCESS_VALID_SET(x)\ 182 FIELD_PREP(ANA_MACACCESS_VALID, x) 183 #define ANA_MACACCESS_VALID_GET(x)\ 184 FIELD_GET(ANA_MACACCESS_VALID, x) 185 186 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 187 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 188 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 189 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 190 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 191 192 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 193 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 194 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 195 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 196 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 197 198 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 199 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 200 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 201 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 202 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 203 204 /* ANA:ANA_TABLES:MACTINDX */ 205 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 206 207 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 208 #define ANA_MACTINDX_BUCKET_SET(x)\ 209 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 210 #define ANA_MACTINDX_BUCKET_GET(x)\ 211 FIELD_GET(ANA_MACTINDX_BUCKET, x) 212 213 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 214 #define ANA_MACTINDX_M_INDEX_SET(x)\ 215 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 216 #define ANA_MACTINDX_M_INDEX_GET(x)\ 217 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 218 219 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 220 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 221 222 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 223 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 224 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 225 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 226 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 227 228 /* ANA:ANA_TABLES:VLANACCESS */ 229 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 230 231 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 232 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 233 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 234 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 235 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 236 237 /* ANA:ANA_TABLES:VLANTIDX */ 238 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 239 240 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 241 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 242 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 243 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 244 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 245 246 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 247 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 248 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 249 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 250 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 251 252 /* ANA:PORT:VLAN_CFG */ 253 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 254 255 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 256 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 257 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 258 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 259 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 260 261 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 262 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 263 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 264 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 265 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 266 267 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 268 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 269 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 270 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 271 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 272 273 /* ANA:PORT:DROP_CFG */ 274 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 275 276 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 277 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 278 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 279 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 280 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 281 282 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 283 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 284 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 285 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 286 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 287 288 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 289 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 290 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 291 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 292 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 293 294 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 295 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 296 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 297 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 298 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 299 300 /* ANA:PORT:CPU_FWD_CFG */ 301 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 302 303 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6) 304 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ 305 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 306 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ 307 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 308 309 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5) 310 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ 311 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 312 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ 313 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 314 315 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4) 316 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ 317 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 318 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ 319 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 320 321 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 322 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 323 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 324 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 325 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 326 327 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 328 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 329 330 /* ANA:PORT:PORT_CFG */ 331 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 332 333 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 334 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 335 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 336 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 337 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 338 339 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 340 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 341 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 342 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 343 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 344 345 #define ANA_PORT_CFG_RECV_ENA BIT(4) 346 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 347 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 348 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 349 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 350 351 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 352 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 353 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 354 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 355 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 356 357 /* ANA:PFC:PFC_CFG */ 358 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 359 360 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 361 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 362 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 363 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 364 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 365 366 /* ANA:COMMON:AGGR_CFG */ 367 #define ANA_AGGR_CFG __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4) 368 369 #define ANA_AGGR_CFG_AC_RND_ENA BIT(6) 370 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\ 371 FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x) 372 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\ 373 FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x) 374 375 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(5) 376 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\ 377 FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x) 378 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\ 379 FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x) 380 381 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(4) 382 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\ 383 FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x) 384 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\ 385 FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x) 386 387 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(3) 388 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\ 389 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 390 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\ 391 FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 392 393 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(2) 394 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\ 395 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 396 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\ 397 FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 398 399 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(1) 400 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\ 401 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 402 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\ 403 FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 404 405 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(0) 406 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\ 407 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 408 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\ 409 FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 410 411 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 412 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 413 414 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 415 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 416 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 417 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 418 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 419 420 /* DEV:PORT_MODE:CLOCK_CFG */ 421 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 422 423 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 424 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 425 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 426 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 427 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 428 429 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 430 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 431 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 432 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 433 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 434 435 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 436 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 437 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 438 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 439 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 440 441 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 442 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 443 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 444 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 445 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 446 447 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 448 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 449 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 450 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 451 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 452 453 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 454 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 455 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 456 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 457 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 458 459 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 460 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 461 462 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 463 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 464 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 465 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 466 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 467 468 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 469 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 470 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 471 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 472 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 473 474 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 475 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 476 477 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 478 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 479 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 480 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 481 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 482 483 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 484 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 485 486 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 487 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 488 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 489 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 490 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 491 492 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 493 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 494 495 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 496 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 497 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 498 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 499 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 500 501 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 502 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 503 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 504 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 505 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 506 507 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 508 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 509 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 510 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 511 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 512 513 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 514 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 515 516 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 517 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 518 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 519 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 520 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 521 522 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 523 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 524 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 525 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 526 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 527 528 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 529 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 530 531 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 532 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 533 534 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 535 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 536 537 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 538 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 539 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 540 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 541 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 542 543 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 544 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 545 546 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 547 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 548 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 549 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 550 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 551 552 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 553 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 554 FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 555 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 556 FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 557 558 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 559 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 560 561 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 562 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 563 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 564 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 565 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 566 567 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 568 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 569 570 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 571 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 572 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 573 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 574 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 575 576 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 577 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 578 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 579 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 580 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 581 582 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 583 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 584 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 585 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 586 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 587 588 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 589 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 590 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 591 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 592 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 593 594 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 595 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 596 597 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 598 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 599 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 600 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 601 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 602 603 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 604 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 605 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 606 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 607 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 608 609 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 610 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 611 612 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 613 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 614 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 615 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 616 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 617 618 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 619 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 620 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 621 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 622 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 623 624 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 625 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 626 627 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 628 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 629 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 630 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 631 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 632 633 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 634 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 635 636 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 637 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 638 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 639 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 640 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 641 642 /* FDMA:FDMA:FDMA_CH_RELOAD */ 643 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 644 645 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 646 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 647 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 648 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 649 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 650 651 /* FDMA:FDMA:FDMA_CH_DISABLE */ 652 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 653 654 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 655 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 656 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 657 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 658 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 659 660 /* FDMA:FDMA:FDMA_CH_DB_DISCARD */ 661 #define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4) 662 663 #define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0) 664 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\ 665 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 666 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\ 667 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 668 669 /* FDMA:FDMA:FDMA_DCB_LLP */ 670 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 671 672 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 673 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 674 675 /* FDMA:FDMA:FDMA_CH_ACTIVE */ 676 #define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4) 677 678 /* FDMA:FDMA:FDMA_CH_CFG */ 679 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 680 681 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4) 682 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 683 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 684 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 685 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 686 687 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3) 688 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 689 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 690 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 691 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 692 693 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1) 694 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 695 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 696 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 697 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 698 699 #define FDMA_CH_CFG_CH_MEM BIT(0) 700 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 701 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 702 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 703 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 704 705 /* FDMA:FDMA:FDMA_PORT_CTRL */ 706 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 707 708 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 709 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 710 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 711 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 712 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 713 714 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 715 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 716 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 717 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 718 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 719 720 /* FDMA:FDMA:FDMA_INTR_DB */ 721 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 722 723 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 724 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 725 726 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 727 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 728 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 729 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 730 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 731 732 /* FDMA:FDMA:FDMA_INTR_ERR */ 733 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 734 735 /* FDMA:FDMA:FDMA_ERRORS */ 736 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 737 738 /* PTP:PTP_CFG:PTP_PIN_INTR */ 739 #define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4) 740 741 #define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0) 742 #define PTP_PIN_INTR_INTR_PTP_SET(x)\ 743 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x) 744 #define PTP_PIN_INTR_INTR_PTP_GET(x)\ 745 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x) 746 747 /* PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 748 #define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4) 749 750 #define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0) 751 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\ 752 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x) 753 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\ 754 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x) 755 756 /* PTP:PTP_CFG:PTP_DOM_CFG */ 757 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4) 758 759 #define PTP_DOM_CFG_ENA GENMASK(11, 9) 760 #define PTP_DOM_CFG_ENA_SET(x)\ 761 FIELD_PREP(PTP_DOM_CFG_ENA, x) 762 #define PTP_DOM_CFG_ENA_GET(x)\ 763 FIELD_GET(PTP_DOM_CFG_ENA, x) 764 765 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0) 766 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ 767 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x) 768 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ 769 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x) 770 771 /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 772 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4) 773 774 /* PTP:PTP_PINS:PTP_PIN_CFG */ 775 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4) 776 777 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27) 778 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ 779 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x) 780 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ 781 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x) 782 783 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25) 784 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ 785 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x) 786 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ 787 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x) 788 789 #define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21) 790 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\ 791 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x) 792 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\ 793 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x) 794 795 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16) 796 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ 797 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x) 798 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ 799 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x) 800 801 /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 802 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4) 803 804 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0) 805 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ 806 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 807 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ 808 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 809 810 /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 811 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4) 812 813 /* PTP:PTP_PINS:PTP_TOD_NSEC */ 814 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4) 815 816 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0) 817 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ 818 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x) 819 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ 820 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x) 821 822 /* PTP:PTP_PINS:WF_HIGH_PERIOD */ 823 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 824 0, 1, 0, g, 8, 64, 24, 0, 1, 4) 825 826 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) 827 #define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0) 828 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) 829 830 /* PTP:PTP_PINS:WF_LOW_PERIOD */ 831 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 832 0, 1, 0, g, 8, 64, 28, 0, 1, 4) 833 834 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) 835 #define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0) 836 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0)) 837 838 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 839 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4) 840 841 #define PTP_TWOSTEP_CTRL_NXT BIT(11) 842 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ 843 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x) 844 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ 845 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x) 846 847 #define PTP_TWOSTEP_CTRL_VLD BIT(10) 848 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ 849 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x) 850 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ 851 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x) 852 853 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 854 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 855 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 856 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 857 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 858 859 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 860 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 861 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 862 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 863 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 864 865 #define PTP_TWOSTEP_CTRL_OVFL BIT(0) 866 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ 867 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x) 868 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ 869 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x) 870 871 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ 872 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4) 873 874 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2) 875 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 876 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 877 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 878 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 879 880 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 881 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 882 883 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 884 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 885 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 886 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 887 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 888 889 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 890 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 891 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 892 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 893 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 894 895 /* DEVCPU_QS:XTR:XTR_RD */ 896 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 897 898 /* DEVCPU_QS:XTR:XTR_FLUSH */ 899 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 900 901 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 902 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 903 904 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 905 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 906 907 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 908 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 909 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 910 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 911 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 912 913 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 914 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 915 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 916 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 917 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 918 919 /* DEVCPU_QS:INJ:INJ_WR */ 920 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 921 922 /* DEVCPU_QS:INJ:INJ_CTRL */ 923 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 924 925 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 926 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 927 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 928 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 929 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 930 931 #define QS_INJ_CTRL_EOF BIT(19) 932 #define QS_INJ_CTRL_EOF_SET(x)\ 933 FIELD_PREP(QS_INJ_CTRL_EOF, x) 934 #define QS_INJ_CTRL_EOF_GET(x)\ 935 FIELD_GET(QS_INJ_CTRL_EOF, x) 936 937 #define QS_INJ_CTRL_SOF BIT(18) 938 #define QS_INJ_CTRL_SOF_SET(x)\ 939 FIELD_PREP(QS_INJ_CTRL_SOF, x) 940 #define QS_INJ_CTRL_SOF_GET(x)\ 941 FIELD_GET(QS_INJ_CTRL_SOF, x) 942 943 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 944 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 945 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 946 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 947 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 948 949 /* DEVCPU_QS:INJ:INJ_STATUS */ 950 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 951 952 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 953 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 954 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 955 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 956 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 957 958 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 959 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 960 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 961 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 962 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 963 964 /* QSYS:SYSTEM:PORT_MODE */ 965 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 966 967 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 968 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 969 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 970 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 971 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 972 973 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 974 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 975 976 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 977 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 978 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 979 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 980 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 981 982 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 983 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 984 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 985 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 986 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 987 988 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 989 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 990 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 991 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 992 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 993 994 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 995 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 996 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 997 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 998 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 999 1000 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 1001 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 1002 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 1003 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 1004 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 1005 1006 /* QSYS:SYSTEM:SW_STATUS */ 1007 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 1008 1009 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 1010 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 1011 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 1012 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 1013 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 1014 1015 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 1016 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 1017 1018 /* QSYS:RES_CTRL:RES_CFG */ 1019 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 1020 1021 /* QSYS:HSCH:CIR_CFG */ 1022 #define QSYS_CIR_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4) 1023 1024 #define QSYS_CIR_CFG_CIR_RATE GENMASK(20, 6) 1025 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\ 1026 FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x) 1027 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\ 1028 FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x) 1029 1030 #define QSYS_CIR_CFG_CIR_BURST GENMASK(5, 0) 1031 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\ 1032 FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x) 1033 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\ 1034 FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x) 1035 1036 /* QSYS:HSCH:SE_CFG */ 1037 #define QSYS_SE_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4) 1038 1039 #define QSYS_SE_CFG_SE_DWRR_CNT GENMASK(9, 6) 1040 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\ 1041 FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x) 1042 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\ 1043 FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x) 1044 1045 #define QSYS_SE_CFG_SE_RR_ENA BIT(5) 1046 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\ 1047 FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x) 1048 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\ 1049 FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x) 1050 1051 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4) 1052 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\ 1053 FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x) 1054 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\ 1055 FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x) 1056 1057 #define QSYS_SE_CFG_SE_FRM_MODE GENMASK(3, 2) 1058 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\ 1059 FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x) 1060 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\ 1061 FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x) 1062 1063 #define QSYS_SE_DWRR_CFG(g, r) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4) 1064 1065 #define QSYS_SE_DWRR_CFG_DWRR_COST GENMASK(4, 0) 1066 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\ 1067 FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1068 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\ 1069 FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1070 1071 /* QSYS:TAS_CONFIG:TAS_CFG_CTRL */ 1072 #define QSYS_TAS_CFG_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4) 1073 1074 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX GENMASK(27, 23) 1075 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\ 1076 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1077 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\ 1078 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1079 1080 #define QSYS_TAS_CFG_CTRL_LIST_NUM GENMASK(22, 18) 1081 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\ 1082 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1083 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\ 1084 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1085 1086 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q BIT(17) 1087 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\ 1088 FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1089 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\ 1090 FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1091 1092 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM GENMASK(16, 5) 1093 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\ 1094 FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1095 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\ 1096 FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1097 1098 /* QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */ 1099 #define QSYS_TAS_GS_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4) 1100 1101 #define QSYS_TAS_GS_CTRL_HSCH_POS GENMASK(2, 0) 1102 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\ 1103 FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1104 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\ 1105 FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1106 1107 /* QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 1108 #define QSYS_TAS_STM_CFG __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4) 1109 1110 #define QSYS_TAS_STM_CFG_REVISIT_DLY GENMASK(7, 0) 1111 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\ 1112 FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1113 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\ 1114 FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1115 1116 /* QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */ 1117 #define QSYS_TAS_PROFILE_CFG(g) __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4) 1118 1119 #define QSYS_TAS_PROFILE_CFG_PORT_NUM GENMASK(21, 19) 1120 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\ 1121 FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1122 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\ 1123 FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1124 1125 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED GENMASK(18, 16) 1126 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\ 1127 FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1128 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\ 1129 FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1130 1131 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */ 1132 #define QSYS_TAS_BT_NSEC __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4) 1133 1134 #define QSYS_TAS_BT_NSEC_NSEC GENMASK(29, 0) 1135 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\ 1136 FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x) 1137 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\ 1138 FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x) 1139 1140 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */ 1141 #define QSYS_TAS_BT_SEC_LSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4) 1142 1143 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */ 1144 #define QSYS_TAS_BT_SEC_MSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4) 1145 1146 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB GENMASK(15, 0) 1147 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\ 1148 FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1149 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\ 1150 FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1151 1152 /* QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */ 1153 #define QSYS_TAS_CT_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4) 1154 1155 /* QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */ 1156 #define QSYS_TAS_STARTUP_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4) 1157 1158 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX GENMASK(27, 23) 1159 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\ 1160 FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1161 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\ 1162 FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1163 1164 /* QSYS:TAS_LIST_CFG:TAS_LIST_CFG */ 1165 #define QSYS_TAS_LIST_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4) 1166 1167 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR GENMASK(11, 0) 1168 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\ 1169 FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1170 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\ 1171 FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1172 1173 /* QSYS:TAS_LIST_CFG:TAS_LIST_STATE */ 1174 #define QSYS_TAS_LST __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4) 1175 1176 #define QSYS_TAS_LST_LIST_STATE GENMASK(2, 0) 1177 #define QSYS_TAS_LST_LIST_STATE_SET(x)\ 1178 FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x) 1179 #define QSYS_TAS_LST_LIST_STATE_GET(x)\ 1180 FIELD_GET(QSYS_TAS_LST_LIST_STATE, x) 1181 1182 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */ 1183 #define QSYS_TAS_GCL_CT_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4) 1184 1185 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS GENMASK(12, 10) 1186 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\ 1187 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1188 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\ 1189 FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1190 1191 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE GENMASK(9, 2) 1192 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\ 1193 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1194 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\ 1195 FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1196 1197 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE GENMASK(1, 0) 1198 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\ 1199 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1200 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\ 1201 FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1202 1203 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */ 1204 #define QSYS_TAS_GCL_CT_CFG2 __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4) 1205 1206 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE GENMASK(15, 12) 1207 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\ 1208 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1209 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\ 1210 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1211 1212 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL GENMASK(11, 0) 1213 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\ 1214 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1215 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\ 1216 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1217 1218 /* QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */ 1219 #define QSYS_TAS_GCL_TM_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4) 1220 1221 /* QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */ 1222 #define QSYS_TAS_GATE_STATE __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4) 1223 1224 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE GENMASK(7, 0) 1225 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\ 1226 FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1227 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\ 1228 FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1229 1230 /* REW:PORT:PORT_VLAN_CFG */ 1231 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 1232 1233 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 1234 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 1235 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 1236 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 1237 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 1238 1239 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 1240 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 1241 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 1242 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 1243 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 1244 1245 /* REW:PORT:TAG_CFG */ 1246 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 1247 1248 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 1249 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 1250 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 1251 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 1252 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 1253 1254 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 1255 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 1256 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 1257 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 1258 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 1259 1260 /* REW:PORT:PORT_CFG */ 1261 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 1262 1263 #define REW_PORT_CFG_NO_REWRITE BIT(0) 1264 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 1265 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 1266 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 1267 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 1268 1269 /* SYS:SYSTEM:RESET_CFG */ 1270 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 1271 1272 #define SYS_RESET_CFG_CORE_ENA BIT(0) 1273 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 1274 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 1275 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 1276 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 1277 1278 /* SYS:SYSTEM:PORT_MODE */ 1279 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 1280 1281 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 1282 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 1283 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 1284 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 1285 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 1286 1287 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 1288 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 1289 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 1290 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 1291 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 1292 1293 /* SYS:SYSTEM:FRONT_PORT_MODE */ 1294 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 1295 1296 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 1297 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 1298 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1299 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 1300 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1301 1302 /* SYS:SYSTEM:FRM_AGING */ 1303 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 1304 1305 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 1306 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 1307 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 1308 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 1309 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 1310 1311 /* SYS:SYSTEM:STAT_CFG */ 1312 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 1313 1314 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 1315 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 1316 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 1317 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 1318 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 1319 1320 /* SYS:PAUSE_CFG:PAUSE_CFG */ 1321 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 1322 1323 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 1324 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 1325 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 1326 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 1327 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 1328 1329 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 1330 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 1331 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 1332 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 1333 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 1334 1335 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 1336 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 1337 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 1338 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 1339 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 1340 1341 /* SYS:PAUSE_CFG:ATOP */ 1342 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 1343 1344 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 1345 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 1346 1347 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 1348 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 1349 1350 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 1351 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 1352 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1353 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 1354 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1355 1356 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 1357 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 1358 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1359 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 1360 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1361 1362 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 1363 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 1364 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1365 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 1366 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1367 1368 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 1369 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 1370 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1371 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 1372 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1373 1374 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 1375 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 1376 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1377 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 1378 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1379 1380 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 1381 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 1382 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1383 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 1384 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1385 1386 /* SYS:STAT:CNT */ 1387 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 1388 1389 /* SYS:RAM_CTRL:RAM_INIT */ 1390 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 1391 1392 #define SYS_RAM_INIT_RAM_INIT BIT(1) 1393 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 1394 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 1395 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 1396 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 1397 1398 #endif /* _LAN966X_REGS_H_ */ 1399