1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_FDMA = 21, 21 TARGET_GCB = 27, 22 TARGET_ORG = 36, 23 TARGET_PTP = 41, 24 TARGET_QS = 42, 25 TARGET_QSYS = 46, 26 TARGET_REW = 47, 27 TARGET_SYS = 52, 28 TARGET_VCAP = 61, 29 NUM_TARGETS = 66 30 }; 31 32 #define __REG(...) __VA_ARGS__ 33 34 /* AFI:PORT_TBL:PORT_FRM_OUT */ 35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 36 37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 42 43 /* AFI:PORT_TBL:PORT_CFG */ 44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 45 46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 51 52 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 53 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 55 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 56 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 57 58 /* ANA:ANA:ADVLEARN */ 59 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 60 61 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 62 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 63 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 64 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 65 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 66 67 /* ANA:ANA:VLANMASK */ 68 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 69 70 /* ANA:ANA:ANAINTR */ 71 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 72 73 #define ANA_ANAINTR_INTR BIT(1) 74 #define ANA_ANAINTR_INTR_SET(x)\ 75 FIELD_PREP(ANA_ANAINTR_INTR, x) 76 #define ANA_ANAINTR_INTR_GET(x)\ 77 FIELD_GET(ANA_ANAINTR_INTR, x) 78 79 #define ANA_ANAINTR_INTR_ENA BIT(0) 80 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 81 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 82 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 83 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 84 85 /* ANA:ANA:AUTOAGE */ 86 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 87 88 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 89 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 90 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 91 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 92 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 93 94 /* ANA:ANA:MIRRORPORTS */ 95 #define ANA_MIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 60, 0, 1, 4) 96 97 #define ANA_MIRRORPORTS_MIRRORPORTS GENMASK(8, 0) 98 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\ 99 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x) 100 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\ 101 FIELD_GET(ANA_MIRRORPORTS_MIRRORPORTS, x) 102 103 /* ANA:ANA:EMIRRORPORTS */ 104 #define ANA_EMIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 64, 0, 1, 4) 105 106 #define ANA_EMIRRORPORTS_EMIRRORPORTS GENMASK(8, 0) 107 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\ 108 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 109 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\ 110 FIELD_GET(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 111 112 /* ANA:ANA:FLOODING */ 113 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 114 115 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 116 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 117 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 118 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 119 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 120 121 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 122 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 123 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 124 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 125 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 126 127 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 128 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 129 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 130 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 131 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 132 133 /* ANA:ANA:FLOODING_IPMC */ 134 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 135 136 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 137 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 138 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 139 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 140 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 141 142 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 143 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 144 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 145 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 146 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 147 148 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 149 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 150 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 151 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 152 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 153 154 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 155 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 156 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 157 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 158 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 159 160 /* ANA:PGID:PGID */ 161 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 162 163 #define ANA_PGID_PGID GENMASK(8, 0) 164 #define ANA_PGID_PGID_SET(x)\ 165 FIELD_PREP(ANA_PGID_PGID, x) 166 #define ANA_PGID_PGID_GET(x)\ 167 FIELD_GET(ANA_PGID_PGID, x) 168 169 /* ANA:PGID:PGID_CFG */ 170 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 171 172 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 173 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 174 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 175 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 176 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 177 178 /* ANA:ANA_TABLES:MACHDATA */ 179 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 180 181 /* ANA:ANA_TABLES:MACLDATA */ 182 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 183 184 /* ANA:ANA_TABLES:MACACCESS */ 185 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 186 187 #define ANA_MACACCESS_CHANGE2SW BIT(17) 188 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 189 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 190 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 191 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 192 193 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 194 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 195 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 196 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 197 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 198 199 #define ANA_MACACCESS_VALID BIT(12) 200 #define ANA_MACACCESS_VALID_SET(x)\ 201 FIELD_PREP(ANA_MACACCESS_VALID, x) 202 #define ANA_MACACCESS_VALID_GET(x)\ 203 FIELD_GET(ANA_MACACCESS_VALID, x) 204 205 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 206 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 207 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 208 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 209 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 210 211 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 212 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 213 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 214 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 215 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 216 217 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 218 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 219 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 220 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 221 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 222 223 /* ANA:ANA_TABLES:MACTINDX */ 224 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 225 226 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 227 #define ANA_MACTINDX_BUCKET_SET(x)\ 228 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 229 #define ANA_MACTINDX_BUCKET_GET(x)\ 230 FIELD_GET(ANA_MACTINDX_BUCKET, x) 231 232 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 233 #define ANA_MACTINDX_M_INDEX_SET(x)\ 234 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 235 #define ANA_MACTINDX_M_INDEX_GET(x)\ 236 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 237 238 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 239 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 240 241 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 242 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 243 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 244 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 245 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 246 247 /* ANA:ANA_TABLES:VLANACCESS */ 248 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 249 250 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 251 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 252 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 253 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 254 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 255 256 /* ANA:ANA_TABLES:VLANTIDX */ 257 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 258 259 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 260 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 261 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 262 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 263 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 264 265 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 266 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 267 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 268 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 269 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 270 271 /* ANA:PORT:VLAN_CFG */ 272 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 273 274 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 275 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 276 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 277 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 278 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 279 280 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 281 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 282 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 283 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 284 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 285 286 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 287 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 288 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 289 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 290 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 291 292 /* ANA:PORT:DROP_CFG */ 293 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 294 295 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 296 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 297 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 298 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 299 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 300 301 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 302 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 303 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 304 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 305 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 306 307 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 308 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 309 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 310 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 311 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 312 313 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 314 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 315 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 316 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 317 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 318 319 /* ANA:PORT:VCAP_CFG */ 320 #define ANA_VCAP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 12, 0, 1, 4) 321 322 #define ANA_VCAP_CFG_S1_ENA BIT(14) 323 #define ANA_VCAP_CFG_S1_ENA_SET(x)\ 324 FIELD_PREP(ANA_VCAP_CFG_S1_ENA, x) 325 #define ANA_VCAP_CFG_S1_ENA_GET(x)\ 326 FIELD_GET(ANA_VCAP_CFG_S1_ENA, x) 327 328 /* ANA:PORT:VCAP_S1_KEY_CFG */ 329 #define ANA_VCAP_S1_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 16, r, 3, 4) 330 331 #define ANA_VCAP_S1_CFG_KEY_RT_CFG GENMASK(11, 9) 332 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_SET(x)\ 333 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_RT_CFG, x) 334 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_GET(x)\ 335 FIELD_GET(ANA_VCAP_S1_CFG_KEY_RT_CFG, x) 336 337 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG GENMASK(8, 6) 338 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_SET(x)\ 339 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x) 340 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_GET(x)\ 341 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x) 342 343 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG GENMASK(5, 3) 344 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_SET(x)\ 345 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x) 346 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_GET(x)\ 347 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x) 348 349 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG GENMASK(2, 0) 350 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_SET(x)\ 351 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x) 352 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_GET(x)\ 353 FIELD_GET(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x) 354 355 /* ANA:PORT:VCAP_S2_CFG */ 356 #define ANA_VCAP_S2_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 28, 0, 1, 4) 357 358 #define ANA_VCAP_S2_CFG_ISDX_ENA GENMASK(20, 19) 359 #define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x)\ 360 FIELD_PREP(ANA_VCAP_S2_CFG_ISDX_ENA, x) 361 #define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x)\ 362 FIELD_GET(ANA_VCAP_S2_CFG_ISDX_ENA, x) 363 364 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA GENMASK(18, 17) 365 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x)\ 366 FIELD_PREP(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x) 367 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x)\ 368 FIELD_GET(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x) 369 370 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA GENMASK(16, 15) 371 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x)\ 372 FIELD_PREP(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x) 373 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x)\ 374 FIELD_GET(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x) 375 376 #define ANA_VCAP_S2_CFG_ENA BIT(14) 377 #define ANA_VCAP_S2_CFG_ENA_SET(x)\ 378 FIELD_PREP(ANA_VCAP_S2_CFG_ENA, x) 379 #define ANA_VCAP_S2_CFG_ENA_GET(x)\ 380 FIELD_GET(ANA_VCAP_S2_CFG_ENA, x) 381 382 #define ANA_VCAP_S2_CFG_SNAP_DIS GENMASK(13, 12) 383 #define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x)\ 384 FIELD_PREP(ANA_VCAP_S2_CFG_SNAP_DIS, x) 385 #define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x)\ 386 FIELD_GET(ANA_VCAP_S2_CFG_SNAP_DIS, x) 387 388 #define ANA_VCAP_S2_CFG_ARP_DIS GENMASK(11, 10) 389 #define ANA_VCAP_S2_CFG_ARP_DIS_SET(x)\ 390 FIELD_PREP(ANA_VCAP_S2_CFG_ARP_DIS, x) 391 #define ANA_VCAP_S2_CFG_ARP_DIS_GET(x)\ 392 FIELD_GET(ANA_VCAP_S2_CFG_ARP_DIS, x) 393 394 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS GENMASK(9, 8) 395 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x)\ 396 FIELD_PREP(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x) 397 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x)\ 398 FIELD_GET(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x) 399 400 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS GENMASK(7, 6) 401 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x)\ 402 FIELD_PREP(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x) 403 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x)\ 404 FIELD_GET(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x) 405 406 #define ANA_VCAP_S2_CFG_IP6_CFG GENMASK(5, 2) 407 #define ANA_VCAP_S2_CFG_IP6_CFG_SET(x)\ 408 FIELD_PREP(ANA_VCAP_S2_CFG_IP6_CFG, x) 409 #define ANA_VCAP_S2_CFG_IP6_CFG_GET(x)\ 410 FIELD_GET(ANA_VCAP_S2_CFG_IP6_CFG, x) 411 412 #define ANA_VCAP_S2_CFG_OAM_DIS GENMASK(1, 0) 413 #define ANA_VCAP_S2_CFG_OAM_DIS_SET(x)\ 414 FIELD_PREP(ANA_VCAP_S2_CFG_OAM_DIS, x) 415 #define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\ 416 FIELD_GET(ANA_VCAP_S2_CFG_OAM_DIS, x) 417 418 /* ANA:PORT:CPU_FWD_CFG */ 419 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 420 421 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6) 422 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ 423 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 424 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ 425 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 426 427 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5) 428 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ 429 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 430 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ 431 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 432 433 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4) 434 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ 435 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 436 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ 437 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 438 439 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 440 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 441 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 442 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 443 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 444 445 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 446 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 447 448 /* ANA:PORT:PORT_CFG */ 449 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 450 451 #define ANA_PORT_CFG_SRC_MIRROR_ENA BIT(13) 452 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\ 453 FIELD_PREP(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 454 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\ 455 FIELD_GET(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 456 457 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 458 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 459 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 460 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 461 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 462 463 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 464 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 465 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 466 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 467 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 468 469 #define ANA_PORT_CFG_RECV_ENA BIT(4) 470 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 471 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 472 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 473 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 474 475 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 476 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 477 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 478 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 479 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 480 481 /* ANA:PORT:POL_CFG */ 482 #define ANA_POL_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 116, 0, 1, 4) 483 484 #define ANA_POL_CFG_PORT_POL_ENA BIT(17) 485 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\ 486 FIELD_PREP(ANA_POL_CFG_PORT_POL_ENA, x) 487 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\ 488 FIELD_GET(ANA_POL_CFG_PORT_POL_ENA, x) 489 490 #define ANA_POL_CFG_POL_ORDER GENMASK(8, 0) 491 #define ANA_POL_CFG_POL_ORDER_SET(x)\ 492 FIELD_PREP(ANA_POL_CFG_POL_ORDER, x) 493 #define ANA_POL_CFG_POL_ORDER_GET(x)\ 494 FIELD_GET(ANA_POL_CFG_POL_ORDER, x) 495 496 /* ANA:PFC:PFC_CFG */ 497 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 498 499 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 500 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 501 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 502 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 503 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 504 505 /* ANA:COMMON:AGGR_CFG */ 506 #define ANA_AGGR_CFG __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4) 507 508 #define ANA_AGGR_CFG_AC_RND_ENA BIT(6) 509 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\ 510 FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x) 511 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\ 512 FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x) 513 514 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(5) 515 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\ 516 FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x) 517 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\ 518 FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x) 519 520 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(4) 521 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\ 522 FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x) 523 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\ 524 FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x) 525 526 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(3) 527 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\ 528 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 529 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\ 530 FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 531 532 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(2) 533 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\ 534 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 535 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\ 536 FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 537 538 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(1) 539 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\ 540 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 541 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\ 542 FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 543 544 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(0) 545 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\ 546 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 547 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\ 548 FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 549 550 /* ANA:POL:POL_PIR_CFG */ 551 #define ANA_POL_PIR_CFG(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 0, 0, 1, 4) 552 553 #define ANA_POL_PIR_CFG_PIR_RATE GENMASK(20, 6) 554 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\ 555 FIELD_PREP(ANA_POL_PIR_CFG_PIR_RATE, x) 556 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\ 557 FIELD_GET(ANA_POL_PIR_CFG_PIR_RATE, x) 558 559 #define ANA_POL_PIR_CFG_PIR_BURST GENMASK(5, 0) 560 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\ 561 FIELD_PREP(ANA_POL_PIR_CFG_PIR_BURST, x) 562 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\ 563 FIELD_GET(ANA_POL_PIR_CFG_PIR_BURST, x) 564 565 /* ANA:POL:POL_MODE_CFG */ 566 #define ANA_POL_MODE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 8, 0, 1, 4) 567 568 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA BIT(11) 569 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\ 570 FIELD_PREP(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 571 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\ 572 FIELD_GET(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 573 574 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA BIT(10) 575 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\ 576 FIELD_PREP(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 577 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\ 578 FIELD_GET(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 579 580 #define ANA_POL_MODE_IPG_SIZE GENMASK(9, 5) 581 #define ANA_POL_MODE_IPG_SIZE_SET(x)\ 582 FIELD_PREP(ANA_POL_MODE_IPG_SIZE, x) 583 #define ANA_POL_MODE_IPG_SIZE_GET(x)\ 584 FIELD_GET(ANA_POL_MODE_IPG_SIZE, x) 585 586 #define ANA_POL_MODE_FRM_MODE GENMASK(4, 3) 587 #define ANA_POL_MODE_FRM_MODE_SET(x)\ 588 FIELD_PREP(ANA_POL_MODE_FRM_MODE, x) 589 #define ANA_POL_MODE_FRM_MODE_GET(x)\ 590 FIELD_GET(ANA_POL_MODE_FRM_MODE, x) 591 592 #define ANA_POL_MODE_OVERSHOOT_ENA BIT(0) 593 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\ 594 FIELD_PREP(ANA_POL_MODE_OVERSHOOT_ENA, x) 595 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\ 596 FIELD_GET(ANA_POL_MODE_OVERSHOOT_ENA, x) 597 598 /* ANA:POL:POL_PIR_STATE */ 599 #define ANA_POL_PIR_STATE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 12, 0, 1, 4) 600 601 #define ANA_POL_PIR_STATE_PIR_LVL GENMASK(21, 0) 602 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\ 603 FIELD_PREP(ANA_POL_PIR_STATE_PIR_LVL, x) 604 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\ 605 FIELD_GET(ANA_POL_PIR_STATE_PIR_LVL, x) 606 607 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 608 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 609 610 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 611 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 612 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 613 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 614 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 615 616 /* DEV:PORT_MODE:CLOCK_CFG */ 617 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 618 619 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 620 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 621 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 622 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 623 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 624 625 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 626 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 627 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 628 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 629 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 630 631 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 632 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 633 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 634 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 635 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 636 637 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 638 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 639 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 640 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 641 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 642 643 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 644 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 645 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 646 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 647 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 648 649 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 650 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 651 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 652 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 653 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 654 655 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 656 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 657 658 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 659 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 660 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 661 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 662 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 663 664 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 665 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 666 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 667 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 668 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 669 670 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 671 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 672 673 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 674 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 675 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 676 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 677 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 678 679 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 680 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 681 682 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 683 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 684 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 685 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 686 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 687 688 /* DEV:MAC_CFG_STATUS:MAC_TAGS_CFG */ 689 #define DEV_MAC_TAGS_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 12, 0, 1, 4) 690 691 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1) 692 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\ 693 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 694 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\ 695 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 696 697 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 698 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 699 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 700 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 701 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 702 703 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 704 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 705 706 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 707 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 708 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 709 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 710 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 711 712 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 713 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 714 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 715 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 716 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 717 718 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 719 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 720 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 721 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 722 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 723 724 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 725 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 726 727 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 728 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 729 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 730 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 731 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 732 733 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 734 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 735 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 736 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 737 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 738 739 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 740 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 741 742 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 743 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 744 745 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 746 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 747 748 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 749 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 750 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 751 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 752 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 753 754 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 755 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 756 757 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 758 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 759 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 760 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 761 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 762 763 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 764 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 765 FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 766 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 767 FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 768 769 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 770 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 771 772 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 773 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 774 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 775 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 776 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 777 778 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 779 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 780 781 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 782 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 783 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 784 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 785 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 786 787 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 788 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 789 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 790 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 791 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 792 793 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 794 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 795 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 796 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 797 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 798 799 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 800 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 801 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 802 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 803 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 804 805 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 806 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 807 808 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 809 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 810 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 811 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 812 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 813 814 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 815 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 816 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 817 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 818 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 819 820 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 821 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 822 823 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 824 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 825 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 826 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 827 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 828 829 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 830 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 831 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 832 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 833 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 834 835 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 836 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 837 838 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 839 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 840 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 841 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 842 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 843 844 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 845 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 846 847 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 848 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 849 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 850 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 851 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 852 853 /* FDMA:FDMA:FDMA_CH_RELOAD */ 854 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 855 856 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 857 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 858 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 859 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 860 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 861 862 /* FDMA:FDMA:FDMA_CH_DISABLE */ 863 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 864 865 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 866 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 867 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 868 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 869 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 870 871 /* FDMA:FDMA:FDMA_CH_DB_DISCARD */ 872 #define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4) 873 874 #define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0) 875 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\ 876 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 877 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\ 878 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 879 880 /* FDMA:FDMA:FDMA_DCB_LLP */ 881 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 882 883 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 884 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 885 886 /* FDMA:FDMA:FDMA_CH_ACTIVE */ 887 #define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4) 888 889 /* FDMA:FDMA:FDMA_CH_CFG */ 890 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 891 892 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4) 893 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 894 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 895 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 896 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 897 898 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3) 899 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 900 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 901 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 902 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 903 904 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1) 905 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 906 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 907 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 908 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 909 910 #define FDMA_CH_CFG_CH_MEM BIT(0) 911 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 912 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 913 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 914 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 915 916 /* FDMA:FDMA:FDMA_PORT_CTRL */ 917 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 918 919 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 920 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 921 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 922 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 923 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 924 925 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 926 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 927 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 928 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 929 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 930 931 /* FDMA:FDMA:FDMA_INTR_DB */ 932 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 933 934 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 935 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 936 937 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 938 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 939 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 940 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 941 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 942 943 /* FDMA:FDMA:FDMA_INTR_ERR */ 944 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 945 946 /* FDMA:FDMA:FDMA_ERRORS */ 947 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 948 949 /* PTP:PTP_CFG:PTP_PIN_INTR */ 950 #define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4) 951 952 #define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0) 953 #define PTP_PIN_INTR_INTR_PTP_SET(x)\ 954 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x) 955 #define PTP_PIN_INTR_INTR_PTP_GET(x)\ 956 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x) 957 958 /* PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 959 #define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4) 960 961 #define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0) 962 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\ 963 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x) 964 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\ 965 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x) 966 967 /* PTP:PTP_CFG:PTP_DOM_CFG */ 968 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4) 969 970 #define PTP_DOM_CFG_ENA GENMASK(11, 9) 971 #define PTP_DOM_CFG_ENA_SET(x)\ 972 FIELD_PREP(PTP_DOM_CFG_ENA, x) 973 #define PTP_DOM_CFG_ENA_GET(x)\ 974 FIELD_GET(PTP_DOM_CFG_ENA, x) 975 976 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0) 977 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ 978 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x) 979 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ 980 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x) 981 982 /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 983 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4) 984 985 /* PTP:PTP_PINS:PTP_PIN_CFG */ 986 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4) 987 988 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27) 989 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ 990 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x) 991 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ 992 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x) 993 994 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25) 995 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ 996 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x) 997 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ 998 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x) 999 1000 #define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21) 1001 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\ 1002 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x) 1003 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\ 1004 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x) 1005 1006 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16) 1007 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ 1008 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x) 1009 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ 1010 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x) 1011 1012 /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 1013 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4) 1014 1015 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0) 1016 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ 1017 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 1018 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ 1019 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 1020 1021 /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 1022 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4) 1023 1024 /* PTP:PTP_PINS:PTP_TOD_NSEC */ 1025 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4) 1026 1027 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0) 1028 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ 1029 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x) 1030 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ 1031 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x) 1032 1033 /* PTP:PTP_PINS:WF_HIGH_PERIOD */ 1034 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 1035 0, 1, 0, g, 8, 64, 24, 0, 1, 4) 1036 1037 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) 1038 #define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0) 1039 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) 1040 1041 /* PTP:PTP_PINS:WF_LOW_PERIOD */ 1042 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 1043 0, 1, 0, g, 8, 64, 28, 0, 1, 4) 1044 1045 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) 1046 #define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0) 1047 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0)) 1048 1049 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 1050 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4) 1051 1052 #define PTP_TWOSTEP_CTRL_NXT BIT(11) 1053 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ 1054 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x) 1055 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ 1056 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x) 1057 1058 #define PTP_TWOSTEP_CTRL_VLD BIT(10) 1059 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ 1060 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x) 1061 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ 1062 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x) 1063 1064 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 1065 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 1066 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 1067 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 1068 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 1069 1070 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 1071 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 1072 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 1073 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 1074 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 1075 1076 #define PTP_TWOSTEP_CTRL_OVFL BIT(0) 1077 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ 1078 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x) 1079 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ 1080 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x) 1081 1082 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ 1083 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4) 1084 1085 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2) 1086 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 1087 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 1088 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 1089 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 1090 1091 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 1092 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 1093 1094 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 1095 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 1096 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 1097 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 1098 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 1099 1100 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 1101 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 1102 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1103 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 1104 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1105 1106 /* DEVCPU_QS:XTR:XTR_RD */ 1107 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 1108 1109 /* DEVCPU_QS:XTR:XTR_FLUSH */ 1110 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 1111 1112 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 1113 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 1114 1115 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 1116 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 1117 1118 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 1119 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 1120 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 1121 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 1122 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 1123 1124 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 1125 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 1126 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1127 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 1128 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1129 1130 /* DEVCPU_QS:INJ:INJ_WR */ 1131 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 1132 1133 /* DEVCPU_QS:INJ:INJ_CTRL */ 1134 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 1135 1136 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 1137 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 1138 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 1139 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 1140 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 1141 1142 #define QS_INJ_CTRL_EOF BIT(19) 1143 #define QS_INJ_CTRL_EOF_SET(x)\ 1144 FIELD_PREP(QS_INJ_CTRL_EOF, x) 1145 #define QS_INJ_CTRL_EOF_GET(x)\ 1146 FIELD_GET(QS_INJ_CTRL_EOF, x) 1147 1148 #define QS_INJ_CTRL_SOF BIT(18) 1149 #define QS_INJ_CTRL_SOF_SET(x)\ 1150 FIELD_PREP(QS_INJ_CTRL_SOF, x) 1151 #define QS_INJ_CTRL_SOF_GET(x)\ 1152 FIELD_GET(QS_INJ_CTRL_SOF, x) 1153 1154 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 1155 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 1156 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 1157 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 1158 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 1159 1160 /* DEVCPU_QS:INJ:INJ_STATUS */ 1161 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 1162 1163 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 1164 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 1165 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 1166 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 1167 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 1168 1169 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 1170 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 1171 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 1172 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 1173 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 1174 1175 /* QSYS:SYSTEM:PORT_MODE */ 1176 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 1177 1178 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 1179 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 1180 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1181 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 1182 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1183 1184 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 1185 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 1186 1187 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 1188 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 1189 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 1190 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 1191 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 1192 1193 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 1194 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 1195 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1196 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 1197 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1198 1199 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 1200 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 1201 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1202 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 1203 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1204 1205 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 1206 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 1207 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1208 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 1209 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1210 1211 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 1212 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 1213 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 1214 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 1215 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 1216 1217 /* QSYS:SYSTEM:SW_STATUS */ 1218 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 1219 1220 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 1221 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 1222 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 1223 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 1224 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 1225 1226 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 1227 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 1228 1229 /* QSYS:RES_CTRL:RES_CFG */ 1230 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 1231 1232 /* QSYS:HSCH:CIR_CFG */ 1233 #define QSYS_CIR_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4) 1234 1235 #define QSYS_CIR_CFG_CIR_RATE GENMASK(20, 6) 1236 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\ 1237 FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x) 1238 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\ 1239 FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x) 1240 1241 #define QSYS_CIR_CFG_CIR_BURST GENMASK(5, 0) 1242 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\ 1243 FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x) 1244 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\ 1245 FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x) 1246 1247 /* QSYS:HSCH:SE_CFG */ 1248 #define QSYS_SE_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4) 1249 1250 #define QSYS_SE_CFG_SE_DWRR_CNT GENMASK(9, 6) 1251 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\ 1252 FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x) 1253 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\ 1254 FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x) 1255 1256 #define QSYS_SE_CFG_SE_RR_ENA BIT(5) 1257 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\ 1258 FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x) 1259 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\ 1260 FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x) 1261 1262 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4) 1263 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\ 1264 FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x) 1265 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\ 1266 FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x) 1267 1268 #define QSYS_SE_CFG_SE_FRM_MODE GENMASK(3, 2) 1269 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\ 1270 FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x) 1271 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\ 1272 FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x) 1273 1274 #define QSYS_SE_DWRR_CFG(g, r) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4) 1275 1276 #define QSYS_SE_DWRR_CFG_DWRR_COST GENMASK(4, 0) 1277 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\ 1278 FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1279 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\ 1280 FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1281 1282 /* QSYS:TAS_CONFIG:TAS_CFG_CTRL */ 1283 #define QSYS_TAS_CFG_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4) 1284 1285 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX GENMASK(27, 23) 1286 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\ 1287 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1288 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\ 1289 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1290 1291 #define QSYS_TAS_CFG_CTRL_LIST_NUM GENMASK(22, 18) 1292 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\ 1293 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1294 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\ 1295 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1296 1297 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q BIT(17) 1298 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\ 1299 FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1300 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\ 1301 FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1302 1303 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM GENMASK(16, 5) 1304 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\ 1305 FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1306 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\ 1307 FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1308 1309 /* QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */ 1310 #define QSYS_TAS_GS_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4) 1311 1312 #define QSYS_TAS_GS_CTRL_HSCH_POS GENMASK(2, 0) 1313 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\ 1314 FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1315 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\ 1316 FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1317 1318 /* QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 1319 #define QSYS_TAS_STM_CFG __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4) 1320 1321 #define QSYS_TAS_STM_CFG_REVISIT_DLY GENMASK(7, 0) 1322 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\ 1323 FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1324 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\ 1325 FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1326 1327 /* QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */ 1328 #define QSYS_TAS_PROFILE_CFG(g) __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4) 1329 1330 #define QSYS_TAS_PROFILE_CFG_PORT_NUM GENMASK(21, 19) 1331 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\ 1332 FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1333 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\ 1334 FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1335 1336 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED GENMASK(18, 16) 1337 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\ 1338 FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1339 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\ 1340 FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1341 1342 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */ 1343 #define QSYS_TAS_BT_NSEC __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4) 1344 1345 #define QSYS_TAS_BT_NSEC_NSEC GENMASK(29, 0) 1346 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\ 1347 FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x) 1348 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\ 1349 FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x) 1350 1351 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */ 1352 #define QSYS_TAS_BT_SEC_LSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4) 1353 1354 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */ 1355 #define QSYS_TAS_BT_SEC_MSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4) 1356 1357 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB GENMASK(15, 0) 1358 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\ 1359 FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1360 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\ 1361 FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1362 1363 /* QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */ 1364 #define QSYS_TAS_CT_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4) 1365 1366 /* QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */ 1367 #define QSYS_TAS_STARTUP_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4) 1368 1369 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX GENMASK(27, 23) 1370 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\ 1371 FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1372 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\ 1373 FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1374 1375 /* QSYS:TAS_LIST_CFG:TAS_LIST_CFG */ 1376 #define QSYS_TAS_LIST_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4) 1377 1378 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR GENMASK(11, 0) 1379 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\ 1380 FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1381 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\ 1382 FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1383 1384 /* QSYS:TAS_LIST_CFG:TAS_LIST_STATE */ 1385 #define QSYS_TAS_LST __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4) 1386 1387 #define QSYS_TAS_LST_LIST_STATE GENMASK(2, 0) 1388 #define QSYS_TAS_LST_LIST_STATE_SET(x)\ 1389 FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x) 1390 #define QSYS_TAS_LST_LIST_STATE_GET(x)\ 1391 FIELD_GET(QSYS_TAS_LST_LIST_STATE, x) 1392 1393 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */ 1394 #define QSYS_TAS_GCL_CT_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4) 1395 1396 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS GENMASK(12, 10) 1397 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\ 1398 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1399 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\ 1400 FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1401 1402 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE GENMASK(9, 2) 1403 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\ 1404 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1405 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\ 1406 FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1407 1408 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE GENMASK(1, 0) 1409 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\ 1410 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1411 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\ 1412 FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1413 1414 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */ 1415 #define QSYS_TAS_GCL_CT_CFG2 __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4) 1416 1417 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE GENMASK(15, 12) 1418 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\ 1419 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1420 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\ 1421 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1422 1423 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL GENMASK(11, 0) 1424 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\ 1425 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1426 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\ 1427 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1428 1429 /* QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */ 1430 #define QSYS_TAS_GCL_TM_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4) 1431 1432 /* QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */ 1433 #define QSYS_TAS_GATE_STATE __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4) 1434 1435 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE GENMASK(7, 0) 1436 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\ 1437 FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1438 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\ 1439 FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1440 1441 /* REW:PORT:PORT_VLAN_CFG */ 1442 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 1443 1444 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 1445 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 1446 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 1447 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 1448 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 1449 1450 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 1451 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 1452 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 1453 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 1454 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 1455 1456 /* REW:PORT:TAG_CFG */ 1457 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 1458 1459 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 1460 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 1461 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 1462 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 1463 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 1464 1465 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 1466 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 1467 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 1468 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 1469 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 1470 1471 /* REW:PORT:PORT_CFG */ 1472 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 1473 1474 #define REW_PORT_CFG_NO_REWRITE BIT(0) 1475 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 1476 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 1477 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 1478 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 1479 1480 /* SYS:SYSTEM:RESET_CFG */ 1481 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 1482 1483 #define SYS_RESET_CFG_CORE_ENA BIT(0) 1484 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 1485 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 1486 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 1487 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 1488 1489 /* SYS:SYSTEM:PORT_MODE */ 1490 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 1491 1492 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 1493 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 1494 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 1495 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 1496 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 1497 1498 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 1499 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 1500 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 1501 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 1502 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 1503 1504 /* SYS:SYSTEM:FRONT_PORT_MODE */ 1505 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 1506 1507 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 1508 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 1509 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1510 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 1511 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1512 1513 /* SYS:SYSTEM:FRM_AGING */ 1514 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 1515 1516 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 1517 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 1518 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 1519 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 1520 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 1521 1522 /* SYS:SYSTEM:STAT_CFG */ 1523 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 1524 1525 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 1526 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 1527 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 1528 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 1529 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 1530 1531 /* SYS:PAUSE_CFG:PAUSE_CFG */ 1532 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 1533 1534 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 1535 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 1536 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 1537 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 1538 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 1539 1540 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 1541 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 1542 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 1543 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 1544 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 1545 1546 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 1547 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 1548 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 1549 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 1550 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 1551 1552 /* SYS:PAUSE_CFG:ATOP */ 1553 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 1554 1555 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 1556 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 1557 1558 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 1559 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 1560 1561 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 1562 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 1563 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1564 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 1565 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1566 1567 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 1568 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 1569 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1570 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 1571 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1572 1573 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 1574 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 1575 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1576 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 1577 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1578 1579 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 1580 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 1581 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1582 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 1583 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1584 1585 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 1586 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 1587 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1588 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 1589 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1590 1591 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 1592 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 1593 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1594 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 1595 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1596 1597 /* SYS:STAT:CNT */ 1598 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 1599 1600 /* SYS:RAM_CTRL:RAM_INIT */ 1601 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 1602 1603 #define SYS_RAM_INIT_RAM_INIT BIT(1) 1604 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 1605 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 1606 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 1607 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 1608 1609 /* VCAP:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 1610 #define VCAP_UPDATE_CTRL(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 0, 0, 1, 4) 1611 1612 #define VCAP_UPDATE_CTRL_UPDATE_CMD GENMASK(24, 22) 1613 #define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x)\ 1614 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CMD, x) 1615 #define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x)\ 1616 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CMD, x) 1617 1618 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 1619 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 1620 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x) 1621 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 1622 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x) 1623 1624 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 1625 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x)\ 1626 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x) 1627 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x)\ 1628 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x) 1629 1630 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 1631 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x)\ 1632 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x) 1633 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x)\ 1634 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x) 1635 1636 #define VCAP_UPDATE_CTRL_UPDATE_ADDR GENMASK(18, 3) 1637 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x)\ 1638 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ADDR, x) 1639 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x)\ 1640 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ADDR, x) 1641 1642 #define VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2) 1643 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x)\ 1644 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_SHOT, x) 1645 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x)\ 1646 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_SHOT, x) 1647 1648 #define VCAP_UPDATE_CTRL_CLEAR_CACHE BIT(1) 1649 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x)\ 1650 FIELD_PREP(VCAP_UPDATE_CTRL_CLEAR_CACHE, x) 1651 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x)\ 1652 FIELD_GET(VCAP_UPDATE_CTRL_CLEAR_CACHE, x) 1653 1654 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 1655 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x)\ 1656 FIELD_PREP(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x) 1657 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x)\ 1658 FIELD_GET(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x) 1659 1660 /* VCAP:VCAP_CORE_CFG:VCAP_MV_CFG */ 1661 #define VCAP_MV_CFG(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 4, 0, 1, 4) 1662 1663 #define VCAP_MV_CFG_MV_NUM_POS GENMASK(31, 16) 1664 #define VCAP_MV_CFG_MV_NUM_POS_SET(x)\ 1665 FIELD_PREP(VCAP_MV_CFG_MV_NUM_POS, x) 1666 #define VCAP_MV_CFG_MV_NUM_POS_GET(x)\ 1667 FIELD_GET(VCAP_MV_CFG_MV_NUM_POS, x) 1668 1669 #define VCAP_MV_CFG_MV_SIZE GENMASK(15, 0) 1670 #define VCAP_MV_CFG_MV_SIZE_SET(x)\ 1671 FIELD_PREP(VCAP_MV_CFG_MV_SIZE, x) 1672 #define VCAP_MV_CFG_MV_SIZE_GET(x)\ 1673 FIELD_GET(VCAP_MV_CFG_MV_SIZE, x) 1674 1675 /* VCAP:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 1676 #define VCAP_ENTRY_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 0, r, 64, 4) 1677 1678 /* VCAP:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 1679 #define VCAP_MASK_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 256, r, 64, 4) 1680 1681 /* VCAP:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 1682 #define VCAP_ACTION_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 512, r, 64, 4) 1683 1684 /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 1685 #define VCAP_CNT_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 768, r, 32, 4) 1686 1687 /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 1688 #define VCAP_CNT_FW_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 896, 0, 1, 4) 1689 1690 /* VCAP:VCAP_CORE_CACHE:VCAP_TG_DAT */ 1691 #define VCAP_TG_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 900, 0, 1, 4) 1692 1693 /* VCAP:VCAP_CORE_MAP:VCAP_CORE_IDX */ 1694 #define VCAP_CORE_IDX(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 0, 0, 1, 4) 1695 1696 #define VCAP_CORE_IDX_CORE_IDX GENMASK(3, 0) 1697 #define VCAP_CORE_IDX_CORE_IDX_SET(x)\ 1698 FIELD_PREP(VCAP_CORE_IDX_CORE_IDX, x) 1699 #define VCAP_CORE_IDX_CORE_IDX_GET(x)\ 1700 FIELD_GET(VCAP_CORE_IDX_CORE_IDX, x) 1701 1702 /* VCAP:VCAP_CORE_MAP:VCAP_CORE_MAP */ 1703 #define VCAP_CORE_MAP(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 4, 0, 1, 4) 1704 1705 #define VCAP_CORE_MAP_CORE_MAP GENMASK(2, 0) 1706 #define VCAP_CORE_MAP_CORE_MAP_SET(x)\ 1707 FIELD_PREP(VCAP_CORE_MAP_CORE_MAP, x) 1708 #define VCAP_CORE_MAP_CORE_MAP_GET(x)\ 1709 FIELD_GET(VCAP_CORE_MAP_CORE_MAP, x) 1710 1711 /* VCAP:VCAP_CONST:VCAP_VER */ 1712 #define VCAP_VER(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 0, 0, 1, 4) 1713 1714 /* VCAP:VCAP_CONST:ENTRY_WIDTH */ 1715 #define VCAP_ENTRY_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 4, 0, 1, 4) 1716 1717 /* VCAP:VCAP_CONST:ENTRY_CNT */ 1718 #define VCAP_ENTRY_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 8, 0, 1, 4) 1719 1720 /* VCAP:VCAP_CONST:ENTRY_SWCNT */ 1721 #define VCAP_ENTRY_SWCNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 12, 0, 1, 4) 1722 1723 /* VCAP:VCAP_CONST:ENTRY_TG_WIDTH */ 1724 #define VCAP_ENTRY_TG_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 16, 0, 1, 4) 1725 1726 /* VCAP:VCAP_CONST:ACTION_DEF_CNT */ 1727 #define VCAP_ACTION_DEF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 20, 0, 1, 4) 1728 1729 /* VCAP:VCAP_CONST:ACTION_WIDTH */ 1730 #define VCAP_ACTION_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 24, 0, 1, 4) 1731 1732 /* VCAP:VCAP_CONST:CNT_WIDTH */ 1733 #define VCAP_CNT_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 28, 0, 1, 4) 1734 1735 /* VCAP:VCAP_CONST:CORE_CNT */ 1736 #define VCAP_CORE_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 32, 0, 1, 4) 1737 1738 /* VCAP:VCAP_CONST:IF_CNT */ 1739 #define VCAP_IF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 36, 0, 1, 4) 1740 1741 #endif /* _LAN966X_REGS_H_ */ 1742