1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_GCB = 27, 21 TARGET_ORG = 36, 22 TARGET_PTP = 41, 23 TARGET_QS = 42, 24 TARGET_QSYS = 46, 25 TARGET_REW = 47, 26 TARGET_SYS = 52, 27 NUM_TARGETS = 66 28 }; 29 30 #define __REG(...) __VA_ARGS__ 31 32 /* AFI:PORT_TBL:PORT_FRM_OUT */ 33 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 34 35 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 36 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 37 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 39 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 40 41 /* AFI:PORT_TBL:PORT_CFG */ 42 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 43 44 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 45 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 46 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 48 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 49 50 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 51 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 52 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 53 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 54 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 55 56 /* ANA:ANA:ADVLEARN */ 57 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 58 59 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 60 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 61 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 62 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 63 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 64 65 /* ANA:ANA:VLANMASK */ 66 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 67 68 /* ANA:ANA:ANAINTR */ 69 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 70 71 #define ANA_ANAINTR_INTR BIT(1) 72 #define ANA_ANAINTR_INTR_SET(x)\ 73 FIELD_PREP(ANA_ANAINTR_INTR, x) 74 #define ANA_ANAINTR_INTR_GET(x)\ 75 FIELD_GET(ANA_ANAINTR_INTR, x) 76 77 #define ANA_ANAINTR_INTR_ENA BIT(0) 78 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 79 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 80 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 81 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 82 83 /* ANA:ANA:AUTOAGE */ 84 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 85 86 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 87 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 88 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 89 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 90 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 91 92 /* ANA:ANA:FLOODING */ 93 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 94 95 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 96 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 97 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 98 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 99 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 100 101 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 102 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 103 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 104 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 105 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 106 107 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 108 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 109 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 110 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 111 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 112 113 /* ANA:ANA:FLOODING_IPMC */ 114 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 115 116 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 117 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 118 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 119 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 120 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 121 122 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 123 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 124 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 125 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 126 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 127 128 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 129 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 130 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 131 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 132 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 133 134 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 135 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 136 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 137 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 138 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 139 140 /* ANA:PGID:PGID */ 141 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 142 143 #define ANA_PGID_PGID GENMASK(8, 0) 144 #define ANA_PGID_PGID_SET(x)\ 145 FIELD_PREP(ANA_PGID_PGID, x) 146 #define ANA_PGID_PGID_GET(x)\ 147 FIELD_GET(ANA_PGID_PGID, x) 148 149 /* ANA:PGID:PGID_CFG */ 150 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 151 152 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 153 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 154 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 155 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 156 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 157 158 /* ANA:ANA_TABLES:MACHDATA */ 159 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 160 161 /* ANA:ANA_TABLES:MACLDATA */ 162 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 163 164 /* ANA:ANA_TABLES:MACACCESS */ 165 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 166 167 #define ANA_MACACCESS_CHANGE2SW BIT(17) 168 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 169 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 170 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 171 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 172 173 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 174 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 175 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 176 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 177 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 178 179 #define ANA_MACACCESS_VALID BIT(12) 180 #define ANA_MACACCESS_VALID_SET(x)\ 181 FIELD_PREP(ANA_MACACCESS_VALID, x) 182 #define ANA_MACACCESS_VALID_GET(x)\ 183 FIELD_GET(ANA_MACACCESS_VALID, x) 184 185 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 186 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 187 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 188 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 189 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 190 191 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 192 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 193 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 194 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 195 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 196 197 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 198 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 199 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 200 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 201 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 202 203 /* ANA:ANA_TABLES:MACTINDX */ 204 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 205 206 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 207 #define ANA_MACTINDX_BUCKET_SET(x)\ 208 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 209 #define ANA_MACTINDX_BUCKET_GET(x)\ 210 FIELD_GET(ANA_MACTINDX_BUCKET, x) 211 212 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 213 #define ANA_MACTINDX_M_INDEX_SET(x)\ 214 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 215 #define ANA_MACTINDX_M_INDEX_GET(x)\ 216 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 217 218 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 219 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 220 221 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 222 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 223 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 224 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 225 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 226 227 /* ANA:ANA_TABLES:VLANACCESS */ 228 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 229 230 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 231 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 232 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 233 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 234 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 235 236 /* ANA:ANA_TABLES:VLANTIDX */ 237 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 238 239 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 240 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 241 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 242 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 243 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 244 245 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 246 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 247 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 248 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 249 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 250 251 /* ANA:PORT:VLAN_CFG */ 252 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 253 254 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 255 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 256 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 257 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 258 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 259 260 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 261 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 262 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 263 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 264 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 265 266 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 267 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 268 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 269 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 270 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 271 272 /* ANA:PORT:DROP_CFG */ 273 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 274 275 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 276 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 277 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 278 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 279 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 280 281 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 282 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 283 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 284 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 285 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 286 287 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 288 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 289 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 290 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 291 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 292 293 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 294 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 295 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 296 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 297 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 298 299 /* ANA:PORT:CPU_FWD_CFG */ 300 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 301 302 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6) 303 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ 304 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 305 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ 306 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 307 308 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5) 309 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ 310 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 311 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ 312 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 313 314 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4) 315 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ 316 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 317 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ 318 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 319 320 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 321 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 322 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 323 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 324 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 325 326 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 327 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 328 329 /* ANA:PORT:PORT_CFG */ 330 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 331 332 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 333 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 334 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 335 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 336 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 337 338 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 339 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 340 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 341 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 342 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 343 344 #define ANA_PORT_CFG_RECV_ENA BIT(4) 345 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 346 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 347 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 348 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 349 350 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 351 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 352 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 353 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 354 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 355 356 /* ANA:PFC:PFC_CFG */ 357 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 358 359 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 360 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 361 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 362 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 363 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 364 365 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 366 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 367 368 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 369 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 370 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 371 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 372 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 373 374 /* DEV:PORT_MODE:CLOCK_CFG */ 375 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 376 377 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 378 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 379 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 380 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 381 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 382 383 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 384 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 385 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 386 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 387 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 388 389 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 390 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 391 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 392 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 393 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 394 395 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 396 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 397 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 398 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 399 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 400 401 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 402 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 403 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 404 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 405 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 406 407 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 408 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 409 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 410 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 411 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 412 413 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 414 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 415 416 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 417 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 418 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 419 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 420 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 421 422 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 423 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 424 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 425 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 426 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 427 428 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 429 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 430 431 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 432 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 433 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 434 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 435 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 436 437 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 438 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 439 440 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 441 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 442 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 443 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 444 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 445 446 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 447 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 448 449 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 450 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 451 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 452 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 453 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 454 455 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 456 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 457 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 458 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 459 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 460 461 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 462 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 463 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 464 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 465 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 466 467 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 468 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 469 470 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 471 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 472 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 473 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 474 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 475 476 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 477 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 478 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 479 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 480 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 481 482 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 483 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 484 485 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 486 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 487 488 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 489 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 490 491 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 492 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 493 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 494 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 495 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 496 497 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 498 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 499 500 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 501 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 502 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 503 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 504 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 505 506 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 507 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 508 509 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 510 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 511 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 512 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 513 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 514 515 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 516 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 517 518 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 519 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 520 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 521 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 522 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 523 524 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 525 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 526 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 527 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 528 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 529 530 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 531 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 532 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 533 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 534 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 535 536 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 537 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 538 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 539 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 540 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 541 542 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 543 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 544 545 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 546 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 547 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 548 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 549 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 550 551 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 552 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 553 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 554 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 555 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 556 557 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 558 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 559 560 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 561 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 562 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 563 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 564 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 565 566 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 567 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 568 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 569 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 570 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 571 572 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 573 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 574 575 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 576 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 577 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 578 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 579 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 580 581 /* PTP:PTP_CFG:PTP_DOM_CFG */ 582 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4) 583 584 #define PTP_DOM_CFG_ENA GENMASK(11, 9) 585 #define PTP_DOM_CFG_ENA_SET(x)\ 586 FIELD_PREP(PTP_DOM_CFG_ENA, x) 587 #define PTP_DOM_CFG_ENA_GET(x)\ 588 FIELD_GET(PTP_DOM_CFG_ENA, x) 589 590 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0) 591 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ 592 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x) 593 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ 594 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x) 595 596 /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 597 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4) 598 599 /* PTP:PTP_PINS:PTP_PIN_CFG */ 600 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4) 601 602 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27) 603 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ 604 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x) 605 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ 606 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x) 607 608 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25) 609 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ 610 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x) 611 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ 612 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x) 613 614 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16) 615 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ 616 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x) 617 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ 618 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x) 619 620 /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 621 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4) 622 623 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0) 624 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ 625 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 626 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ 627 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 628 629 /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 630 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4) 631 632 /* PTP:PTP_PINS:PTP_TOD_NSEC */ 633 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4) 634 635 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0) 636 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ 637 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x) 638 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ 639 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x) 640 641 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 642 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4) 643 644 #define PTP_TWOSTEP_CTRL_NXT BIT(11) 645 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ 646 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x) 647 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ 648 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x) 649 650 #define PTP_TWOSTEP_CTRL_VLD BIT(10) 651 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ 652 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x) 653 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ 654 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x) 655 656 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 657 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 658 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 659 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 660 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 661 662 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 663 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 664 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 665 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 666 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 667 668 #define PTP_TWOSTEP_CTRL_OVFL BIT(0) 669 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ 670 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x) 671 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ 672 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x) 673 674 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ 675 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4) 676 677 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2) 678 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 679 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 680 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 681 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 682 683 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 684 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 685 686 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 687 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 688 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 689 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 690 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 691 692 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 693 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 694 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 695 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 696 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 697 698 /* DEVCPU_QS:XTR:XTR_RD */ 699 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 700 701 /* DEVCPU_QS:XTR:XTR_FLUSH */ 702 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 703 704 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 705 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 706 707 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 708 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 709 710 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 711 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 712 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 713 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 714 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 715 716 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 717 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 718 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 719 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 720 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 721 722 /* DEVCPU_QS:INJ:INJ_WR */ 723 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 724 725 /* DEVCPU_QS:INJ:INJ_CTRL */ 726 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 727 728 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 729 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 730 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 731 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 732 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 733 734 #define QS_INJ_CTRL_EOF BIT(19) 735 #define QS_INJ_CTRL_EOF_SET(x)\ 736 FIELD_PREP(QS_INJ_CTRL_EOF, x) 737 #define QS_INJ_CTRL_EOF_GET(x)\ 738 FIELD_GET(QS_INJ_CTRL_EOF, x) 739 740 #define QS_INJ_CTRL_SOF BIT(18) 741 #define QS_INJ_CTRL_SOF_SET(x)\ 742 FIELD_PREP(QS_INJ_CTRL_SOF, x) 743 #define QS_INJ_CTRL_SOF_GET(x)\ 744 FIELD_GET(QS_INJ_CTRL_SOF, x) 745 746 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 747 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 748 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 749 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 750 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 751 752 /* DEVCPU_QS:INJ:INJ_STATUS */ 753 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 754 755 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 756 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 757 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 758 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 759 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 760 761 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 762 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 763 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 764 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 765 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 766 767 /* QSYS:SYSTEM:PORT_MODE */ 768 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 769 770 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 771 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 772 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 773 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 774 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 775 776 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 777 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 778 779 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 780 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 781 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 782 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 783 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 784 785 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 786 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 787 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 788 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 789 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 790 791 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 792 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 793 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 794 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 795 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 796 797 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 798 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 799 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 800 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 801 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 802 803 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 804 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 805 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 806 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 807 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 808 809 /* QSYS:SYSTEM:SW_STATUS */ 810 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 811 812 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 813 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 814 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 815 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 816 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 817 818 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 819 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 820 821 /* QSYS:RES_CTRL:RES_CFG */ 822 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 823 824 /* REW:PORT:PORT_VLAN_CFG */ 825 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 826 827 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 828 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 829 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 830 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 831 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 832 833 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 834 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 835 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 836 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 837 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 838 839 /* REW:PORT:TAG_CFG */ 840 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 841 842 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 843 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 844 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 845 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 846 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 847 848 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 849 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 850 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 851 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 852 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 853 854 /* REW:PORT:PORT_CFG */ 855 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 856 857 #define REW_PORT_CFG_NO_REWRITE BIT(0) 858 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 859 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 860 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 861 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 862 863 /* SYS:SYSTEM:RESET_CFG */ 864 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 865 866 #define SYS_RESET_CFG_CORE_ENA BIT(0) 867 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 868 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 869 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 870 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 871 872 /* SYS:SYSTEM:PORT_MODE */ 873 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 874 875 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 876 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 877 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 878 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 879 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 880 881 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 882 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 883 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 884 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 885 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 886 887 /* SYS:SYSTEM:FRONT_PORT_MODE */ 888 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 889 890 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 891 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 892 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 893 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 894 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 895 896 /* SYS:SYSTEM:FRM_AGING */ 897 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 898 899 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 900 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 901 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 902 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 903 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 904 905 /* SYS:SYSTEM:STAT_CFG */ 906 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 907 908 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 909 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 910 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 911 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 912 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 913 914 /* SYS:PAUSE_CFG:PAUSE_CFG */ 915 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 916 917 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 918 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 919 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 920 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 921 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 922 923 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 924 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 925 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 926 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 927 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 928 929 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 930 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 931 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 932 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 933 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 934 935 /* SYS:PAUSE_CFG:ATOP */ 936 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 937 938 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 939 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 940 941 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 942 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 943 944 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 945 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 946 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 947 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 948 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 949 950 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 951 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 952 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 953 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 954 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 955 956 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 957 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 958 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 959 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 960 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 961 962 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 963 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 964 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 965 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 966 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 967 968 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 969 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 970 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 971 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 972 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 973 974 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 975 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 976 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 977 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 978 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 979 980 /* SYS:STAT:CNT */ 981 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 982 983 /* SYS:RAM_CTRL:RAM_INIT */ 984 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 985 986 #define SYS_RAM_INIT_RAM_INIT BIT(1) 987 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 988 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 989 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 990 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 991 992 #endif /* _LAN966X_REGS_H_ */ 993