1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2018 Microchip Technology Inc. */
3 
4 #ifndef _LAN743X_H
5 #define _LAN743X_H
6 
7 #include "lan743x_ptp.h"
8 
9 #define DRIVER_AUTHOR   "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
10 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
11 #define DRIVER_NAME "lan743x"
12 
13 /* Register Definitions */
14 #define ID_REV				(0x00)
15 #define ID_REV_ID_MASK_			(0xFFFF0000)
16 #define ID_REV_ID_LAN7430_		(0x74300000)
17 #define ID_REV_ID_LAN7431_		(0x74310000)
18 #define ID_REV_IS_VALID_CHIP_ID_(id_rev)	\
19 	(((id_rev) & 0xFFF00000) == 0x74300000)
20 #define ID_REV_CHIP_REV_MASK_		(0x0000FFFF)
21 #define ID_REV_CHIP_REV_A0_		(0x00000000)
22 #define ID_REV_CHIP_REV_B0_		(0x00000010)
23 
24 #define FPGA_REV			(0x04)
25 #define FPGA_REV_GET_MINOR_(fpga_rev)	(((fpga_rev) >> 8) & 0x000000FF)
26 #define FPGA_REV_GET_MAJOR_(fpga_rev)	((fpga_rev) & 0x000000FF)
27 
28 #define HW_CFG					(0x010)
29 #define HW_CFG_LRST_				BIT(1)
30 
31 #define PMT_CTL					(0x014)
32 #define PMT_CTL_ETH_PHY_D3_COLD_OVR_		BIT(27)
33 #define PMT_CTL_MAC_D3_RX_CLK_OVR_		BIT(25)
34 #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_		BIT(24)
35 #define PMT_CTL_ETH_PHY_D3_OVR_			BIT(23)
36 #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_		BIT(18)
37 #define PMT_CTL_GPIO_WAKEUP_EN_			BIT(15)
38 #define PMT_CTL_EEE_WAKEUP_EN_			BIT(13)
39 #define PMT_CTL_READY_				BIT(7)
40 #define PMT_CTL_ETH_PHY_RST_			BIT(4)
41 #define PMT_CTL_WOL_EN_				BIT(3)
42 #define PMT_CTL_ETH_PHY_WAKE_EN_		BIT(2)
43 #define PMT_CTL_WUPS_MASK_			(0x00000003)
44 
45 #define DP_SEL				(0x024)
46 #define DP_SEL_DPRDY_			BIT(31)
47 #define DP_SEL_MASK_			(0x0000001F)
48 #define DP_SEL_RFE_RAM			(0x00000001)
49 
50 #define DP_SEL_VHF_HASH_LEN		(16)
51 #define DP_SEL_VHF_VLAN_LEN		(128)
52 
53 #define DP_CMD				(0x028)
54 #define DP_CMD_WRITE_			(0x00000001)
55 
56 #define DP_ADDR				(0x02C)
57 
58 #define DP_DATA_0			(0x030)
59 
60 #define E2P_CMD				(0x040)
61 #define E2P_CMD_EPC_BUSY_		BIT(31)
62 #define E2P_CMD_EPC_CMD_WRITE_		(0x30000000)
63 #define E2P_CMD_EPC_CMD_EWEN_		(0x20000000)
64 #define E2P_CMD_EPC_CMD_READ_		(0x00000000)
65 #define E2P_CMD_EPC_TIMEOUT_		BIT(10)
66 #define E2P_CMD_EPC_ADDR_MASK_		(0x000001FF)
67 
68 #define E2P_DATA			(0x044)
69 
70 #define GPIO_CFG0			(0x050)
71 #define GPIO_CFG0_GPIO_DIR_BIT_(bit)	BIT(16 + (bit))
72 #define GPIO_CFG0_GPIO_DATA_BIT_(bit)	BIT(0 + (bit))
73 
74 #define GPIO_CFG1			(0x054)
75 #define GPIO_CFG1_GPIOEN_BIT_(bit)	BIT(16 + (bit))
76 #define GPIO_CFG1_GPIOBUF_BIT_(bit)	BIT(0 + (bit))
77 
78 #define GPIO_CFG2			(0x058)
79 #define GPIO_CFG2_1588_POL_BIT_(bit)	BIT(0 + (bit))
80 
81 #define GPIO_CFG3			(0x05C)
82 #define GPIO_CFG3_1588_CH_SEL_BIT_(bit)	BIT(16 + (bit))
83 #define GPIO_CFG3_1588_OE_BIT_(bit)	BIT(0 + (bit))
84 
85 #define FCT_RX_CTL			(0xAC)
86 #define FCT_RX_CTL_EN_(channel)		BIT(28 + (channel))
87 #define FCT_RX_CTL_DIS_(channel)	BIT(24 + (channel))
88 #define FCT_RX_CTL_RESET_(channel)	BIT(20 + (channel))
89 
90 #define FCT_TX_CTL			(0xC4)
91 #define FCT_TX_CTL_EN_(channel)		BIT(28 + (channel))
92 #define FCT_TX_CTL_DIS_(channel)	BIT(24 + (channel))
93 #define FCT_TX_CTL_RESET_(channel)	BIT(20 + (channel))
94 
95 #define FCT_FLOW(rx_channel)			(0xE0 + ((rx_channel) << 2))
96 #define FCT_FLOW_CTL_OFF_THRESHOLD_		(0x00007F00)
97 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value)	\
98 	((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
99 #define FCT_FLOW_CTL_REQ_EN_			BIT(7)
100 #define FCT_FLOW_CTL_ON_THRESHOLD_		(0x0000007F)
101 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value)	\
102 	((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
103 
104 #define MAC_CR				(0x100)
105 #define MAC_CR_EEE_EN_			BIT(17)
106 #define MAC_CR_ADD_			BIT(12)
107 #define MAC_CR_ASD_			BIT(11)
108 #define MAC_CR_CNTR_RST_		BIT(5)
109 #define MAC_CR_RST_			BIT(0)
110 
111 #define MAC_RX				(0x104)
112 #define MAC_RX_MAX_SIZE_SHIFT_		(16)
113 #define MAC_RX_MAX_SIZE_MASK_		(0x3FFF0000)
114 #define MAC_RX_RXD_			BIT(1)
115 #define MAC_RX_RXEN_			BIT(0)
116 
117 #define MAC_TX				(0x108)
118 #define MAC_TX_TXD_			BIT(1)
119 #define MAC_TX_TXEN_			BIT(0)
120 
121 #define MAC_FLOW			(0x10C)
122 #define MAC_FLOW_CR_TX_FCEN_		BIT(30)
123 #define MAC_FLOW_CR_RX_FCEN_		BIT(29)
124 #define MAC_FLOW_CR_FCPT_MASK_		(0x0000FFFF)
125 
126 #define MAC_RX_ADDRH			(0x118)
127 
128 #define MAC_RX_ADDRL			(0x11C)
129 
130 #define MAC_MII_ACC			(0x120)
131 #define MAC_MII_ACC_PHY_ADDR_SHIFT_	(11)
132 #define MAC_MII_ACC_PHY_ADDR_MASK_	(0x0000F800)
133 #define MAC_MII_ACC_MIIRINDA_SHIFT_	(6)
134 #define MAC_MII_ACC_MIIRINDA_MASK_	(0x000007C0)
135 #define MAC_MII_ACC_MII_READ_		(0x00000000)
136 #define MAC_MII_ACC_MII_WRITE_		(0x00000002)
137 #define MAC_MII_ACC_MII_BUSY_		BIT(0)
138 
139 #define MAC_MII_DATA			(0x124)
140 
141 #define MAC_EEE_TX_LPI_REQ_DLY_CNT		(0x130)
142 
143 #define MAC_WUCSR				(0x140)
144 #define MAC_WUCSR_RFE_WAKE_EN_			BIT(14)
145 #define MAC_WUCSR_PFDA_EN_			BIT(3)
146 #define MAC_WUCSR_WAKE_EN_			BIT(2)
147 #define MAC_WUCSR_MPEN_				BIT(1)
148 #define MAC_WUCSR_BCST_EN_			BIT(0)
149 
150 #define MAC_WK_SRC				(0x144)
151 
152 #define MAC_WUF_CFG0			(0x150)
153 #define MAC_NUM_OF_WUF_CFG		(32)
154 #define MAC_WUF_CFG_BEGIN		(MAC_WUF_CFG0)
155 #define MAC_WUF_CFG(index)		(MAC_WUF_CFG_BEGIN + (4 * (index)))
156 #define MAC_WUF_CFG_EN_			BIT(31)
157 #define MAC_WUF_CFG_TYPE_MCAST_		(0x02000000)
158 #define MAC_WUF_CFG_TYPE_ALL_		(0x01000000)
159 #define MAC_WUF_CFG_OFFSET_SHIFT_	(16)
160 #define MAC_WUF_CFG_CRC16_MASK_		(0x0000FFFF)
161 
162 #define MAC_WUF_MASK0_0			(0x200)
163 #define MAC_WUF_MASK0_1			(0x204)
164 #define MAC_WUF_MASK0_2			(0x208)
165 #define MAC_WUF_MASK0_3			(0x20C)
166 #define MAC_WUF_MASK0_BEGIN		(MAC_WUF_MASK0_0)
167 #define MAC_WUF_MASK1_BEGIN		(MAC_WUF_MASK0_1)
168 #define MAC_WUF_MASK2_BEGIN		(MAC_WUF_MASK0_2)
169 #define MAC_WUF_MASK3_BEGIN		(MAC_WUF_MASK0_3)
170 #define MAC_WUF_MASK0(index)		(MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
171 #define MAC_WUF_MASK1(index)		(MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
172 #define MAC_WUF_MASK2(index)		(MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
173 #define MAC_WUF_MASK3(index)		(MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
174 
175 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
176 #define RFE_ADDR_FILT_HI(x)		(0x400 + (8 * (x)))
177 #define RFE_ADDR_FILT_HI_VALID_		BIT(31)
178 
179 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
180 #define RFE_ADDR_FILT_LO(x)		(0x404 + (8 * (x)))
181 
182 #define RFE_CTL				(0x508)
183 #define RFE_CTL_AB_			BIT(10)
184 #define RFE_CTL_AM_			BIT(9)
185 #define RFE_CTL_AU_			BIT(8)
186 #define RFE_CTL_MCAST_HASH_		BIT(3)
187 #define RFE_CTL_DA_PERFECT_		BIT(1)
188 
189 #define RFE_RSS_CFG			(0x554)
190 #define RFE_RSS_CFG_UDP_IPV6_EX_	BIT(16)
191 #define RFE_RSS_CFG_TCP_IPV6_EX_	BIT(15)
192 #define RFE_RSS_CFG_IPV6_EX_		BIT(14)
193 #define RFE_RSS_CFG_UDP_IPV6_		BIT(13)
194 #define RFE_RSS_CFG_TCP_IPV6_		BIT(12)
195 #define RFE_RSS_CFG_IPV6_		BIT(11)
196 #define RFE_RSS_CFG_UDP_IPV4_		BIT(10)
197 #define RFE_RSS_CFG_TCP_IPV4_		BIT(9)
198 #define RFE_RSS_CFG_IPV4_		BIT(8)
199 #define RFE_RSS_CFG_VALID_HASH_BITS_	(0x000000E0)
200 #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_	BIT(2)
201 #define RFE_RSS_CFG_RSS_HASH_STORE_	BIT(1)
202 #define RFE_RSS_CFG_RSS_ENABLE_		BIT(0)
203 
204 #define RFE_HASH_KEY(index)		(0x558 + (index << 2))
205 
206 #define RFE_INDX(index)			(0x580 + (index << 2))
207 
208 #define MAC_WUCSR2			(0x600)
209 
210 #define INT_STS				(0x780)
211 #define INT_BIT_DMA_RX_(channel)	BIT(24 + (channel))
212 #define INT_BIT_ALL_RX_			(0x0F000000)
213 #define INT_BIT_DMA_TX_(channel)	BIT(16 + (channel))
214 #define INT_BIT_ALL_TX_			(0x000F0000)
215 #define INT_BIT_SW_GP_			BIT(9)
216 #define INT_BIT_1588_			BIT(7)
217 #define INT_BIT_ALL_OTHER_		(INT_BIT_SW_GP_ | INT_BIT_1588_)
218 #define INT_BIT_MAS_			BIT(0)
219 
220 #define INT_SET				(0x784)
221 
222 #define INT_EN_SET			(0x788)
223 
224 #define INT_EN_CLR			(0x78C)
225 
226 #define INT_STS_R2C			(0x790)
227 
228 #define INT_VEC_EN_SET			(0x794)
229 #define INT_VEC_EN_CLR			(0x798)
230 #define INT_VEC_EN_AUTO_CLR		(0x79C)
231 #define INT_VEC_EN_(vector_index)	BIT(0 + vector_index)
232 
233 #define INT_VEC_MAP0			(0x7A0)
234 #define INT_VEC_MAP0_RX_VEC_(channel, vector)	\
235 	(((u32)(vector)) << ((channel) << 2))
236 
237 #define INT_VEC_MAP1			(0x7A4)
238 #define INT_VEC_MAP1_TX_VEC_(channel, vector)	\
239 	(((u32)(vector)) << ((channel) << 2))
240 
241 #define INT_VEC_MAP2			(0x7A8)
242 
243 #define INT_MOD_MAP0			(0x7B0)
244 
245 #define INT_MOD_MAP1			(0x7B4)
246 
247 #define INT_MOD_MAP2			(0x7B8)
248 
249 #define INT_MOD_CFG0			(0x7C0)
250 #define INT_MOD_CFG1			(0x7C4)
251 #define INT_MOD_CFG2			(0x7C8)
252 #define INT_MOD_CFG3			(0x7CC)
253 #define INT_MOD_CFG4			(0x7D0)
254 #define INT_MOD_CFG5			(0x7D4)
255 #define INT_MOD_CFG6			(0x7D8)
256 #define INT_MOD_CFG7			(0x7DC)
257 
258 #define PTP_CMD_CTL					(0x0A00)
259 #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_			BIT(6)
260 #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_			BIT(5)
261 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_			BIT(4)
262 #define PTP_CMD_CTL_PTP_CLOCK_READ_			BIT(3)
263 #define PTP_CMD_CTL_PTP_ENABLE_				BIT(2)
264 #define PTP_CMD_CTL_PTP_DISABLE_			BIT(1)
265 #define PTP_CMD_CTL_PTP_RESET_				BIT(0)
266 #define PTP_GENERAL_CONFIG				(0x0A04)
267 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
268 	(0x7 << (1 + ((channel) << 2)))
269 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_	(0)
270 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_	(1)
271 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_	(2)
272 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_	(3)
273 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_	(4)
274 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_	(5)
275 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
276 	(((value) & 0x7) << (1 + ((channel) << 2)))
277 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel)	(BIT((channel) << 2))
278 
279 #define PTP_INT_STS				(0x0A08)
280 #define PTP_INT_EN_SET				(0x0A0C)
281 #define PTP_INT_EN_CLR				(0x0A10)
282 #define PTP_INT_BIT_TX_SWTS_ERR_		BIT(13)
283 #define PTP_INT_BIT_TX_TS_			BIT(12)
284 #define PTP_INT_BIT_TIMER_B_			BIT(1)
285 #define PTP_INT_BIT_TIMER_A_			BIT(0)
286 
287 #define PTP_CLOCK_SEC				(0x0A14)
288 #define PTP_CLOCK_NS				(0x0A18)
289 #define PTP_CLOCK_SUBNS				(0x0A1C)
290 #define PTP_CLOCK_RATE_ADJ			(0x0A20)
291 #define PTP_CLOCK_RATE_ADJ_DIR_			BIT(31)
292 #define PTP_CLOCK_STEP_ADJ			(0x0A2C)
293 #define PTP_CLOCK_STEP_ADJ_DIR_			BIT(31)
294 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_		(0x3FFFFFFF)
295 #define PTP_CLOCK_TARGET_SEC_X(channel)		(0x0A30 + ((channel) << 4))
296 #define PTP_CLOCK_TARGET_NS_X(channel)		(0x0A34 + ((channel) << 4))
297 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel)	(0x0A38 + ((channel) << 4))
298 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel)	(0x0A3C + ((channel) << 4))
299 #define PTP_LATENCY				(0x0A5C)
300 #define PTP_LATENCY_TX_SET_(tx_latency)		(((u32)(tx_latency)) << 16)
301 #define PTP_LATENCY_RX_SET_(rx_latency)		\
302 	(((u32)(rx_latency)) & 0x0000FFFF)
303 #define PTP_CAP_INFO				(0x0A60)
304 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)	(((reg_val) & 0x00000070) >> 4)
305 
306 #define PTP_TX_MOD				(0x0AA4)
307 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_	(0x10000000)
308 
309 #define PTP_TX_MOD2				(0x0AA8)
310 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_	(0x00000001)
311 
312 #define PTP_TX_EGRESS_SEC			(0x0AAC)
313 #define PTP_TX_EGRESS_NS			(0x0AB0)
314 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_	(0xC0000000)
315 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_	(0x00000000)
316 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_	(0x40000000)
317 #define PTP_TX_EGRESS_NS_TS_NS_MASK_		(0x3FFFFFFF)
318 
319 #define PTP_TX_MSG_HEADER			(0x0AB4)
320 #define PTP_TX_MSG_HEADER_MSG_TYPE_		(0x000F0000)
321 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_	(0x00000000)
322 
323 #define DMAC_CFG				(0xC00)
324 #define DMAC_CFG_COAL_EN_			BIT(16)
325 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_		(0x00000000)
326 #define DMAC_CFG_MAX_READ_REQ_MASK_		(0x00000070)
327 #define DMAC_CFG_MAX_READ_REQ_SET_(val)	\
328 	((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
329 #define DMAC_CFG_MAX_DSPACE_16_			(0x00000000)
330 #define DMAC_CFG_MAX_DSPACE_32_			(0x00000001)
331 #define DMAC_CFG_MAX_DSPACE_64_			BIT(1)
332 #define DMAC_CFG_MAX_DSPACE_128_		(0x00000003)
333 
334 #define DMAC_COAL_CFG				(0xC04)
335 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_		(0xFFF00000)
336 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val)	\
337 	((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
338 #define DMAC_COAL_CFG_TIMER_TX_START_		BIT(19)
339 #define DMAC_COAL_CFG_FLUSH_INTS_		BIT(18)
340 #define DMAC_COAL_CFG_INT_EXIT_COAL_		BIT(17)
341 #define DMAC_COAL_CFG_CSR_EXIT_COAL_		BIT(16)
342 #define DMAC_COAL_CFG_TX_THRES_MASK_		(0x0000FF00)
343 #define DMAC_COAL_CFG_TX_THRES_SET_(val)	\
344 	((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
345 #define DMAC_COAL_CFG_RX_THRES_MASK_		(0x000000FF)
346 #define DMAC_COAL_CFG_RX_THRES_SET_(val)	\
347 	(((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
348 
349 #define DMAC_OBFF_CFG				(0xC08)
350 #define DMAC_OBFF_TX_THRES_MASK_		(0x0000FF00)
351 #define DMAC_OBFF_TX_THRES_SET_(val)	\
352 	((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
353 #define DMAC_OBFF_RX_THRES_MASK_		(0x000000FF)
354 #define DMAC_OBFF_RX_THRES_SET_(val)	\
355 	(((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
356 
357 #define DMAC_CMD				(0xC0C)
358 #define DMAC_CMD_SWR_				BIT(31)
359 #define DMAC_CMD_TX_SWR_(channel)		BIT(24 + (channel))
360 #define DMAC_CMD_START_T_(channel)		BIT(20 + (channel))
361 #define DMAC_CMD_STOP_T_(channel)		BIT(16 + (channel))
362 #define DMAC_CMD_RX_SWR_(channel)		BIT(8 + (channel))
363 #define DMAC_CMD_START_R_(channel)		BIT(4 + (channel))
364 #define DMAC_CMD_STOP_R_(channel)		BIT(0 + (channel))
365 
366 #define DMAC_INT_STS				(0xC10)
367 #define DMAC_INT_EN_SET				(0xC14)
368 #define DMAC_INT_EN_CLR				(0xC18)
369 #define DMAC_INT_BIT_RXFRM_(channel)		BIT(16 + (channel))
370 #define DMAC_INT_BIT_TX_IOC_(channel)		BIT(0 + (channel))
371 
372 #define RX_CFG_A(channel)			(0xC40 + ((channel) << 6))
373 #define RX_CFG_A_RX_WB_ON_INT_TMR_		BIT(30)
374 #define RX_CFG_A_RX_WB_THRES_MASK_		(0x1F000000)
375 #define RX_CFG_A_RX_WB_THRES_SET_(val)	\
376 	((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
377 #define RX_CFG_A_RX_PF_THRES_MASK_		(0x001F0000)
378 #define RX_CFG_A_RX_PF_THRES_SET_(val)	\
379 	((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
380 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_		(0x00001F00)
381 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val)	\
382 	((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
383 #define RX_CFG_A_RX_HP_WB_EN_			BIT(5)
384 
385 #define RX_CFG_B(channel)			(0xC44 + ((channel) << 6))
386 #define RX_CFG_B_TS_ALL_RX_			BIT(29)
387 #define RX_CFG_B_RX_PAD_MASK_			(0x03000000)
388 #define RX_CFG_B_RX_PAD_0_			(0x00000000)
389 #define RX_CFG_B_RX_PAD_2_			(0x02000000)
390 #define RX_CFG_B_RDMABL_512_			(0x00040000)
391 #define RX_CFG_B_RX_RING_LEN_MASK_		(0x0000FFFF)
392 
393 #define RX_BASE_ADDRH(channel)			(0xC48 + ((channel) << 6))
394 
395 #define RX_BASE_ADDRL(channel)			(0xC4C + ((channel) << 6))
396 
397 #define RX_HEAD_WRITEBACK_ADDRH(channel)	(0xC50 + ((channel) << 6))
398 
399 #define RX_HEAD_WRITEBACK_ADDRL(channel)	(0xC54 + ((channel) << 6))
400 
401 #define RX_HEAD(channel)			(0xC58 + ((channel) << 6))
402 
403 #define RX_TAIL(channel)			(0xC5C + ((channel) << 6))
404 #define RX_TAIL_SET_TOP_INT_EN_			BIT(30)
405 #define RX_TAIL_SET_TOP_INT_VEC_EN_		BIT(29)
406 
407 #define RX_CFG_C(channel)			(0xC64 + ((channel) << 6))
408 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_	BIT(6)
409 #define RX_CFG_C_RX_INT_EN_R2C_			BIT(4)
410 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_	BIT(3)
411 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_	(0x00000007)
412 
413 #define TX_CFG_A(channel)			(0xD40 + ((channel) << 6))
414 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_		BIT(30)
415 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_		(0x10000000)
416 #define TX_CFG_A_TX_PF_THRES_MASK_		(0x001F0000)
417 #define TX_CFG_A_TX_PF_THRES_SET_(value)	\
418 	((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
419 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_		(0x00001F00)
420 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value)	\
421 	((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
422 #define TX_CFG_A_TX_HP_WB_EN_			BIT(5)
423 #define TX_CFG_A_TX_HP_WB_THRES_MASK_		(0x0000000F)
424 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value)	\
425 	(((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
426 
427 #define TX_CFG_B(channel)			(0xD44 + ((channel) << 6))
428 #define TX_CFG_B_TDMABL_512_			(0x00040000)
429 #define TX_CFG_B_TX_RING_LEN_MASK_		(0x0000FFFF)
430 
431 #define TX_BASE_ADDRH(channel)			(0xD48 + ((channel) << 6))
432 
433 #define TX_BASE_ADDRL(channel)			(0xD4C + ((channel) << 6))
434 
435 #define TX_HEAD_WRITEBACK_ADDRH(channel)	(0xD50 + ((channel) << 6))
436 
437 #define TX_HEAD_WRITEBACK_ADDRL(channel)	(0xD54 + ((channel) << 6))
438 
439 #define TX_HEAD(channel)			(0xD58 + ((channel) << 6))
440 
441 #define TX_TAIL(channel)			(0xD5C + ((channel) << 6))
442 #define TX_TAIL_SET_DMAC_INT_EN_		BIT(31)
443 #define TX_TAIL_SET_TOP_INT_EN_			BIT(30)
444 #define TX_TAIL_SET_TOP_INT_VEC_EN_		BIT(29)
445 
446 #define TX_CFG_C(channel)			(0xD64 + ((channel) << 6))
447 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_	BIT(6)
448 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_	BIT(5)
449 #define TX_CFG_C_TX_INT_EN_R2C_			BIT(4)
450 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_	BIT(3)
451 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_	(0x00000007)
452 
453 #define OTP_PWR_DN				(0x1000)
454 #define OTP_PWR_DN_PWRDN_N_			BIT(0)
455 
456 #define OTP_ADDR1				(0x1004)
457 #define OTP_ADDR1_15_11_MASK_			(0x1F)
458 
459 #define OTP_ADDR2				(0x1008)
460 #define OTP_ADDR2_10_3_MASK_			(0xFF)
461 
462 #define OTP_PRGM_DATA				(0x1010)
463 
464 #define OTP_PRGM_MODE				(0x1014)
465 #define OTP_PRGM_MODE_BYTE_			BIT(0)
466 
467 #define OTP_TST_CMD				(0x1024)
468 #define OTP_TST_CMD_PRGVRFY_			BIT(3)
469 
470 #define OTP_CMD_GO				(0x1028)
471 #define OTP_CMD_GO_GO_				BIT(0)
472 
473 #define OTP_STATUS				(0x1030)
474 #define OTP_STATUS_BUSY_			BIT(0)
475 
476 /* MAC statistics registers */
477 #define STAT_RX_FCS_ERRORS			(0x1200)
478 #define STAT_RX_ALIGNMENT_ERRORS		(0x1204)
479 #define STAT_RX_FRAGMENT_ERRORS			(0x1208)
480 #define STAT_RX_JABBER_ERRORS			(0x120C)
481 #define STAT_RX_UNDERSIZE_FRAME_ERRORS		(0x1210)
482 #define STAT_RX_OVERSIZE_FRAME_ERRORS		(0x1214)
483 #define STAT_RX_DROPPED_FRAMES			(0x1218)
484 #define STAT_RX_UNICAST_BYTE_COUNT		(0x121C)
485 #define STAT_RX_BROADCAST_BYTE_COUNT		(0x1220)
486 #define STAT_RX_MULTICAST_BYTE_COUNT		(0x1224)
487 #define STAT_RX_UNICAST_FRAMES			(0x1228)
488 #define STAT_RX_BROADCAST_FRAMES		(0x122C)
489 #define STAT_RX_MULTICAST_FRAMES		(0x1230)
490 #define STAT_RX_PAUSE_FRAMES			(0x1234)
491 #define STAT_RX_64_BYTE_FRAMES			(0x1238)
492 #define STAT_RX_65_127_BYTE_FRAMES		(0x123C)
493 #define STAT_RX_128_255_BYTE_FRAMES		(0x1240)
494 #define STAT_RX_256_511_BYTES_FRAMES		(0x1244)
495 #define STAT_RX_512_1023_BYTE_FRAMES		(0x1248)
496 #define STAT_RX_1024_1518_BYTE_FRAMES		(0x124C)
497 #define STAT_RX_GREATER_1518_BYTE_FRAMES	(0x1250)
498 #define STAT_RX_TOTAL_FRAMES			(0x1254)
499 #define STAT_EEE_RX_LPI_TRANSITIONS		(0x1258)
500 #define STAT_EEE_RX_LPI_TIME			(0x125C)
501 #define STAT_RX_COUNTER_ROLLOVER_STATUS		(0x127C)
502 
503 #define STAT_TX_FCS_ERRORS			(0x1280)
504 #define STAT_TX_EXCESS_DEFERRAL_ERRORS		(0x1284)
505 #define STAT_TX_CARRIER_ERRORS			(0x1288)
506 #define STAT_TX_BAD_BYTE_COUNT			(0x128C)
507 #define STAT_TX_SINGLE_COLLISIONS		(0x1290)
508 #define STAT_TX_MULTIPLE_COLLISIONS		(0x1294)
509 #define STAT_TX_EXCESSIVE_COLLISION		(0x1298)
510 #define STAT_TX_LATE_COLLISIONS			(0x129C)
511 #define STAT_TX_UNICAST_BYTE_COUNT		(0x12A0)
512 #define STAT_TX_BROADCAST_BYTE_COUNT		(0x12A4)
513 #define STAT_TX_MULTICAST_BYTE_COUNT		(0x12A8)
514 #define STAT_TX_UNICAST_FRAMES			(0x12AC)
515 #define STAT_TX_BROADCAST_FRAMES		(0x12B0)
516 #define STAT_TX_MULTICAST_FRAMES		(0x12B4)
517 #define STAT_TX_PAUSE_FRAMES			(0x12B8)
518 #define STAT_TX_64_BYTE_FRAMES			(0x12BC)
519 #define STAT_TX_65_127_BYTE_FRAMES		(0x12C0)
520 #define STAT_TX_128_255_BYTE_FRAMES		(0x12C4)
521 #define STAT_TX_256_511_BYTES_FRAMES		(0x12C8)
522 #define STAT_TX_512_1023_BYTE_FRAMES		(0x12CC)
523 #define STAT_TX_1024_1518_BYTE_FRAMES		(0x12D0)
524 #define STAT_TX_GREATER_1518_BYTE_FRAMES	(0x12D4)
525 #define STAT_TX_TOTAL_FRAMES			(0x12D8)
526 #define STAT_EEE_TX_LPI_TRANSITIONS		(0x12DC)
527 #define STAT_EEE_TX_LPI_TIME			(0x12E0)
528 #define STAT_TX_COUNTER_ROLLOVER_STATUS		(0x12FC)
529 
530 /* End of Register definitions */
531 
532 #define LAN743X_MAX_RX_CHANNELS		(4)
533 #define LAN743X_MAX_TX_CHANNELS		(1)
534 struct lan743x_adapter;
535 
536 #define LAN743X_USED_RX_CHANNELS	(4)
537 #define LAN743X_USED_TX_CHANNELS	(1)
538 #define LAN743X_INT_MOD	(400)
539 
540 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)
541 #error Invalid LAN743X_USED_RX_CHANNELS
542 #endif
543 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)
544 #error Invalid LAN743X_USED_TX_CHANNELS
545 #endif
546 
547 /* PCI */
548 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */
549 #define PCI_VENDOR_ID_SMSC		PCI_VENDOR_ID_EFAR
550 #define PCI_DEVICE_ID_SMSC_LAN7430	(0x7430)
551 #define PCI_DEVICE_ID_SMSC_LAN7431	(0x7431)
552 
553 #define PCI_CONFIG_LENGTH		(0x1000)
554 
555 /* CSR */
556 #define CSR_LENGTH					(0x2000)
557 
558 #define LAN743X_CSR_FLAG_IS_A0				BIT(0)
559 #define LAN743X_CSR_FLAG_IS_B0				BIT(1)
560 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR	BIT(8)
561 
562 struct lan743x_csr {
563 	u32 flags;
564 	u8 __iomem *csr_address;
565 	u32 id_rev;
566 	u32 fpga_rev;
567 };
568 
569 /* INTERRUPTS */
570 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);
571 
572 #define LAN743X_VECTOR_FLAG_IRQ_SHARED			BIT(0)
573 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ		BIT(1)
574 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C		BIT(2)
575 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C		BIT(3)
576 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK		BIT(4)
577 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR		BIT(5)
578 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C		BIT(6)
579 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR		BIT(7)
580 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET		BIT(8)
581 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR	BIT(9)
582 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET	BIT(10)
583 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR	BIT(11)
584 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET	BIT(12)
585 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR	BIT(13)
586 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET	BIT(14)
587 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR	BIT(15)
588 
589 struct lan743x_vector {
590 	int			irq;
591 	u32			flags;
592 	struct lan743x_adapter	*adapter;
593 	int			vector_index;
594 	u32			int_mask;
595 	lan743x_vector_handler	handler;
596 	void			*context;
597 };
598 
599 #define LAN743X_MAX_VECTOR_COUNT	(8)
600 
601 struct lan743x_intr {
602 	int			flags;
603 
604 	unsigned int		irq;
605 
606 	struct lan743x_vector	vector_list[LAN743X_MAX_VECTOR_COUNT];
607 	int			number_of_vectors;
608 	bool			using_vectors;
609 
610 	int			software_isr_flag;
611 };
612 
613 #define LAN743X_MAX_FRAME_SIZE			(9 * 1024)
614 
615 /* PHY */
616 struct lan743x_phy {
617 	bool	fc_autoneg;
618 	u8	fc_request_control;
619 };
620 
621 /* TX */
622 struct lan743x_tx_descriptor;
623 struct lan743x_tx_buffer_info;
624 
625 #define GPIO_QUEUE_STARTED		(0)
626 #define GPIO_TX_FUNCTION		(1)
627 #define GPIO_TX_COMPLETION		(2)
628 #define GPIO_TX_FRAGMENT		(3)
629 
630 #define TX_FRAME_FLAG_IN_PROGRESS	BIT(0)
631 
632 #define TX_TS_FLAG_TIMESTAMPING_ENABLED	BIT(0)
633 #define TX_TS_FLAG_ONE_STEP_SYNC	BIT(1)
634 
635 struct lan743x_tx {
636 	struct lan743x_adapter *adapter;
637 	u32	ts_flags;
638 	u32	vector_flags;
639 	int	channel_number;
640 
641 	int	ring_size;
642 	size_t	ring_allocation_size;
643 	struct lan743x_tx_descriptor *ring_cpu_ptr;
644 	dma_addr_t ring_dma_ptr;
645 	/* ring_lock: used to prevent concurrent access to tx ring */
646 	spinlock_t ring_lock;
647 	u32		frame_flags;
648 	u32		frame_first;
649 	u32		frame_data0;
650 	u32		frame_tail;
651 
652 	struct lan743x_tx_buffer_info *buffer_info;
653 
654 	u32		*head_cpu_ptr;
655 	dma_addr_t	head_dma_ptr;
656 	int		last_head;
657 	int		last_tail;
658 
659 	struct napi_struct napi;
660 
661 	struct sk_buff *overflow_skb;
662 };
663 
664 void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
665 				      bool enable_timestamping,
666 				      bool enable_onestep_sync);
667 
668 /* RX */
669 struct lan743x_rx_descriptor;
670 struct lan743x_rx_buffer_info;
671 
672 struct lan743x_rx {
673 	struct lan743x_adapter *adapter;
674 	u32	vector_flags;
675 	int	channel_number;
676 
677 	int	ring_size;
678 	size_t	ring_allocation_size;
679 	struct lan743x_rx_descriptor *ring_cpu_ptr;
680 	dma_addr_t ring_dma_ptr;
681 
682 	struct lan743x_rx_buffer_info *buffer_info;
683 
684 	u32		*head_cpu_ptr;
685 	dma_addr_t	head_dma_ptr;
686 	u32		last_head;
687 	u32		last_tail;
688 
689 	struct napi_struct napi;
690 
691 	u32		frame_count;
692 };
693 
694 struct lan743x_adapter {
695 	struct net_device       *netdev;
696 	struct mii_bus		*mdiobus;
697 	int                     msg_enable;
698 #ifdef CONFIG_PM
699 	u32			wolopts;
700 #endif
701 	struct pci_dev		*pdev;
702 	struct lan743x_csr      csr;
703 	struct lan743x_intr     intr;
704 
705 	/* lock, used to prevent concurrent access to data port */
706 	struct mutex		dp_lock;
707 
708 	struct lan743x_gpio	gpio;
709 	struct lan743x_ptp	ptp;
710 
711 	u8			mac_address[ETH_ALEN];
712 
713 	struct lan743x_phy      phy;
714 	struct lan743x_tx       tx[LAN743X_MAX_TX_CHANNELS];
715 	struct lan743x_rx       rx[LAN743X_MAX_RX_CHANNELS];
716 };
717 
718 #define LAN743X_COMPONENT_FLAG_RX(channel)  BIT(20 + (channel))
719 
720 #define INTR_FLAG_IRQ_REQUESTED(vector_index)	BIT(0 + vector_index)
721 #define INTR_FLAG_MSI_ENABLED			BIT(8)
722 #define INTR_FLAG_MSIX_ENABLED			BIT(9)
723 
724 #define MAC_MII_READ            1
725 #define MAC_MII_WRITE           0
726 
727 #define PHY_FLAG_OPENED     BIT(0)
728 #define PHY_FLAG_ATTACHED   BIT(1)
729 
730 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
731 #define DMA_ADDR_HIGH32(dma_addr)   ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
732 #else
733 #define DMA_ADDR_HIGH32(dma_addr)   ((u32)(0))
734 #endif
735 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
736 #define DMA_DESCRIPTOR_SPACING_16       (16)
737 #define DMA_DESCRIPTOR_SPACING_32       (32)
738 #define DMA_DESCRIPTOR_SPACING_64       (64)
739 #define DMA_DESCRIPTOR_SPACING_128      (128)
740 #define DEFAULT_DMA_DESCRIPTOR_SPACING  (L1_CACHE_BYTES)
741 
742 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \
743 	(((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
744 #define DMAC_CHANNEL_STATE_INITIAL      DMAC_CHANNEL_STATE_SET(0, 0)
745 #define DMAC_CHANNEL_STATE_STARTED      DMAC_CHANNEL_STATE_SET(1, 0)
746 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)
747 #define DMAC_CHANNEL_STATE_STOPPED      DMAC_CHANNEL_STATE_SET(0, 1)
748 
749 /* TX Descriptor bits */
750 #define TX_DESC_DATA0_DTYPE_MASK_		(0xC0000000)
751 #define TX_DESC_DATA0_DTYPE_DATA_		(0x00000000)
752 #define TX_DESC_DATA0_DTYPE_EXT_		(0x40000000)
753 #define TX_DESC_DATA0_FS_			(0x20000000)
754 #define TX_DESC_DATA0_LS_			(0x10000000)
755 #define TX_DESC_DATA0_EXT_			(0x08000000)
756 #define TX_DESC_DATA0_IOC_			(0x04000000)
757 #define TX_DESC_DATA0_ICE_			(0x00400000)
758 #define TX_DESC_DATA0_IPE_			(0x00200000)
759 #define TX_DESC_DATA0_TPE_			(0x00100000)
760 #define TX_DESC_DATA0_FCS_			(0x00020000)
761 #define TX_DESC_DATA0_TSE_			(0x00010000)
762 #define TX_DESC_DATA0_BUF_LENGTH_MASK_		(0x0000FFFF)
763 #define TX_DESC_DATA0_EXT_LSO_			(0x00200000)
764 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_	(0x000FFFFF)
765 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_	(0x3FFF0000)
766 
767 struct lan743x_tx_descriptor {
768 	u32     data0;
769 	u32     data1;
770 	u32     data2;
771 	u32     data3;
772 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
773 
774 #define TX_BUFFER_INFO_FLAG_ACTIVE		BIT(0)
775 #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED	BIT(1)
776 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC		BIT(2)
777 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT	BIT(3)
778 struct lan743x_tx_buffer_info {
779 	int flags;
780 	struct sk_buff *skb;
781 	dma_addr_t      dma_ptr;
782 	unsigned int    buffer_length;
783 };
784 
785 #define LAN743X_TX_RING_SIZE    (50)
786 
787 /* OWN bit is set. ie, Descs are owned by RX DMAC */
788 #define RX_DESC_DATA0_OWN_                (0x00008000)
789 /* OWN bit is clear. ie, Descs are owned by host */
790 #define RX_DESC_DATA0_FS_                 (0x80000000)
791 #define RX_DESC_DATA0_LS_                 (0x40000000)
792 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_  (0x3FFF0000)
793 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0)	\
794 	(((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)
795 #define RX_DESC_DATA0_EXT_                (0x00004000)
796 #define RX_DESC_DATA0_BUF_LENGTH_MASK_    (0x00003FFF)
797 #define RX_DESC_DATA2_TS_NS_MASK_         (0x3FFFFFFF)
798 
799 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
800 #error NET_IP_ALIGN must be 0 or 2
801 #endif
802 
803 #define RX_HEAD_PADDING		NET_IP_ALIGN
804 
805 struct lan743x_rx_descriptor {
806 	u32     data0;
807 	u32     data1;
808 	u32     data2;
809 	u32     data3;
810 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
811 
812 #define RX_BUFFER_INFO_FLAG_ACTIVE      BIT(0)
813 struct lan743x_rx_buffer_info {
814 	int flags;
815 	struct sk_buff *skb;
816 
817 	dma_addr_t      dma_ptr;
818 	unsigned int    buffer_length;
819 };
820 
821 #define LAN743X_RX_RING_SIZE        (65)
822 
823 #define RX_PROCESS_RESULT_NOTHING_TO_DO     (0)
824 #define RX_PROCESS_RESULT_PACKET_RECEIVED   (1)
825 #define RX_PROCESS_RESULT_PACKET_DROPPED    (2)
826 
827 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset);
828 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data);
829 
830 #endif /* _LAN743X_H */
831