1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2018 Microchip Technology Inc. */ 3 4 #ifndef _LAN743X_H 5 #define _LAN743X_H 6 7 #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 8 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 9 #define DRIVER_NAME "lan743x" 10 11 /* Register Definitions */ 12 #define ID_REV (0x00) 13 #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 14 (((id_rev) & 0xFFF00000) == 0x74300000) 15 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 16 #define ID_REV_CHIP_REV_A0_ (0x00000000) 17 #define ID_REV_CHIP_REV_B0_ (0x00000010) 18 19 #define FPGA_REV (0x04) 20 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 21 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 22 23 #define HW_CFG (0x010) 24 #define HW_CFG_LRST_ BIT(1) 25 26 #define PMT_CTL (0x014) 27 #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 28 #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 29 #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 30 #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 31 #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 32 #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 33 #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 34 #define PMT_CTL_READY_ BIT(7) 35 #define PMT_CTL_ETH_PHY_RST_ BIT(4) 36 #define PMT_CTL_WOL_EN_ BIT(3) 37 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 38 #define PMT_CTL_WUPS_MASK_ (0x00000003) 39 40 #define DP_SEL (0x024) 41 #define DP_SEL_DPRDY_ BIT(31) 42 #define DP_SEL_MASK_ (0x0000001F) 43 #define DP_SEL_RFE_RAM (0x00000001) 44 45 #define DP_SEL_VHF_HASH_LEN (16) 46 #define DP_SEL_VHF_VLAN_LEN (128) 47 48 #define DP_CMD (0x028) 49 #define DP_CMD_WRITE_ (0x00000001) 50 51 #define DP_ADDR (0x02C) 52 53 #define DP_DATA_0 (0x030) 54 55 #define E2P_CMD (0x040) 56 #define E2P_CMD_EPC_BUSY_ BIT(31) 57 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 58 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 59 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 60 #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 61 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 62 63 #define E2P_DATA (0x044) 64 65 #define FCT_RX_CTL (0xAC) 66 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 67 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 68 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 69 70 #define FCT_TX_CTL (0xC4) 71 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 72 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 73 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 74 75 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 76 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 77 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 78 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 79 #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 80 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 81 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 82 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 83 84 #define MAC_CR (0x100) 85 #define MAC_CR_EEE_EN_ BIT(17) 86 #define MAC_CR_ADD_ BIT(12) 87 #define MAC_CR_ASD_ BIT(11) 88 #define MAC_CR_CNTR_RST_ BIT(5) 89 #define MAC_CR_RST_ BIT(0) 90 91 #define MAC_RX (0x104) 92 #define MAC_RX_MAX_SIZE_SHIFT_ (16) 93 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 94 #define MAC_RX_RXD_ BIT(1) 95 #define MAC_RX_RXEN_ BIT(0) 96 97 #define MAC_TX (0x108) 98 #define MAC_TX_TXD_ BIT(1) 99 #define MAC_TX_TXEN_ BIT(0) 100 101 #define MAC_FLOW (0x10C) 102 #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 103 #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 104 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 105 106 #define MAC_RX_ADDRH (0x118) 107 108 #define MAC_RX_ADDRL (0x11C) 109 110 #define MAC_MII_ACC (0x120) 111 #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 112 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 113 #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 114 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 115 #define MAC_MII_ACC_MII_READ_ (0x00000000) 116 #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 117 #define MAC_MII_ACC_MII_BUSY_ BIT(0) 118 119 #define MAC_MII_DATA (0x124) 120 121 #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 122 123 #define MAC_WUCSR (0x140) 124 #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 125 #define MAC_WUCSR_PFDA_EN_ BIT(3) 126 #define MAC_WUCSR_WAKE_EN_ BIT(2) 127 #define MAC_WUCSR_MPEN_ BIT(1) 128 #define MAC_WUCSR_BCST_EN_ BIT(0) 129 130 #define MAC_WK_SRC (0x144) 131 132 #define MAC_WUF_CFG0 (0x150) 133 #define MAC_NUM_OF_WUF_CFG (32) 134 #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 135 #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 136 #define MAC_WUF_CFG_EN_ BIT(31) 137 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 138 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 139 #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 140 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 141 142 #define MAC_WUF_MASK0_0 (0x200) 143 #define MAC_WUF_MASK0_1 (0x204) 144 #define MAC_WUF_MASK0_2 (0x208) 145 #define MAC_WUF_MASK0_3 (0x20C) 146 #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 147 #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 148 #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 149 #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 150 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 151 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 152 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 153 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 154 155 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 156 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 157 #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 158 159 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 160 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 161 162 #define RFE_CTL (0x508) 163 #define RFE_CTL_AB_ BIT(10) 164 #define RFE_CTL_AM_ BIT(9) 165 #define RFE_CTL_AU_ BIT(8) 166 #define RFE_CTL_MCAST_HASH_ BIT(3) 167 #define RFE_CTL_DA_PERFECT_ BIT(1) 168 169 #define MAC_WUCSR2 (0x600) 170 171 #define INT_STS (0x780) 172 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 173 #define INT_BIT_ALL_RX_ (0x0F000000) 174 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 175 #define INT_BIT_ALL_TX_ (0x000F0000) 176 #define INT_BIT_SW_GP_ BIT(9) 177 #define INT_BIT_ALL_OTHER_ (0x00000280) 178 #define INT_BIT_MAS_ BIT(0) 179 180 #define INT_SET (0x784) 181 182 #define INT_EN_SET (0x788) 183 184 #define INT_EN_CLR (0x78C) 185 186 #define INT_STS_R2C (0x790) 187 188 #define INT_VEC_EN_SET (0x794) 189 #define INT_VEC_EN_CLR (0x798) 190 #define INT_VEC_EN_AUTO_CLR (0x79C) 191 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 192 193 #define INT_VEC_MAP0 (0x7A0) 194 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 195 (((u32)(vector)) << ((channel) << 2)) 196 197 #define INT_VEC_MAP1 (0x7A4) 198 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 199 (((u32)(vector)) << ((channel) << 2)) 200 201 #define INT_VEC_MAP2 (0x7A8) 202 203 #define INT_MOD_MAP0 (0x7B0) 204 205 #define INT_MOD_MAP1 (0x7B4) 206 207 #define INT_MOD_MAP2 (0x7B8) 208 209 #define INT_MOD_CFG0 (0x7C0) 210 #define INT_MOD_CFG1 (0x7C4) 211 #define INT_MOD_CFG2 (0x7C8) 212 #define INT_MOD_CFG3 (0x7CC) 213 #define INT_MOD_CFG4 (0x7D0) 214 #define INT_MOD_CFG5 (0x7D4) 215 #define INT_MOD_CFG6 (0x7D8) 216 #define INT_MOD_CFG7 (0x7DC) 217 218 #define DMAC_CFG (0xC00) 219 #define DMAC_CFG_COAL_EN_ BIT(16) 220 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 221 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 222 #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 223 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 224 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 225 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 226 #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 227 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 228 229 #define DMAC_COAL_CFG (0xC04) 230 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 231 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 232 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 233 #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 234 #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 235 #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 236 #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 237 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 238 #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 239 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 240 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 241 #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 242 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 243 244 #define DMAC_OBFF_CFG (0xC08) 245 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 246 #define DMAC_OBFF_TX_THRES_SET_(val) \ 247 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 248 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 249 #define DMAC_OBFF_RX_THRES_SET_(val) \ 250 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 251 252 #define DMAC_CMD (0xC0C) 253 #define DMAC_CMD_SWR_ BIT(31) 254 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 255 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 256 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 257 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 258 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 259 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 260 261 #define DMAC_INT_STS (0xC10) 262 #define DMAC_INT_EN_SET (0xC14) 263 #define DMAC_INT_EN_CLR (0xC18) 264 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 265 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 266 267 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 268 #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 269 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 270 #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 271 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 272 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 273 #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 274 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 275 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 276 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 277 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 278 #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 279 280 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 281 #define RX_CFG_B_TS_ALL_RX_ BIT(29) 282 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 283 #define RX_CFG_B_RX_PAD_0_ (0x00000000) 284 #define RX_CFG_B_RX_PAD_2_ (0x02000000) 285 #define RX_CFG_B_RDMABL_512_ (0x00040000) 286 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 287 288 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 289 290 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 291 292 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 293 294 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 295 296 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 297 298 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 299 #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 300 #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 301 302 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 303 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 304 #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 305 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 306 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 307 308 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 309 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 310 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 311 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 312 #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 313 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 314 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 315 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 316 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 317 #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 318 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 319 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 320 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 321 322 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 323 #define TX_CFG_B_TDMABL_512_ (0x00040000) 324 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 325 326 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 327 328 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 329 330 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 331 332 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 333 334 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 335 336 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 337 #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 338 #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 339 #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 340 341 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 342 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 343 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 344 #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 345 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 346 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 347 348 #define OTP_PWR_DN (0x1000) 349 #define OTP_PWR_DN_PWRDN_N_ BIT(0) 350 351 #define OTP_ADDR1 (0x1004) 352 #define OTP_ADDR1_15_11_MASK_ (0x1F) 353 354 #define OTP_ADDR2 (0x1008) 355 #define OTP_ADDR2_10_3_MASK_ (0xFF) 356 357 #define OTP_PRGM_DATA (0x1010) 358 359 #define OTP_PRGM_MODE (0x1014) 360 #define OTP_PRGM_MODE_BYTE_ BIT(0) 361 362 #define OTP_TST_CMD (0x1024) 363 #define OTP_TST_CMD_PRGVRFY_ BIT(3) 364 365 #define OTP_CMD_GO (0x1028) 366 #define OTP_CMD_GO_GO_ BIT(0) 367 368 #define OTP_STATUS (0x1030) 369 #define OTP_STATUS_BUSY_ BIT(0) 370 371 /* MAC statistics registers */ 372 #define STAT_RX_FCS_ERRORS (0x1200) 373 #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 374 #define STAT_RX_FRAGMENT_ERRORS (0x1208) 375 #define STAT_RX_JABBER_ERRORS (0x120C) 376 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 377 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 378 #define STAT_RX_DROPPED_FRAMES (0x1218) 379 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 380 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 381 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 382 #define STAT_RX_UNICAST_FRAMES (0x1228) 383 #define STAT_RX_BROADCAST_FRAMES (0x122C) 384 #define STAT_RX_MULTICAST_FRAMES (0x1230) 385 #define STAT_RX_PAUSE_FRAMES (0x1234) 386 #define STAT_RX_64_BYTE_FRAMES (0x1238) 387 #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 388 #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 389 #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 390 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 391 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 392 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 393 #define STAT_RX_TOTAL_FRAMES (0x1254) 394 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 395 #define STAT_EEE_RX_LPI_TIME (0x125C) 396 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 397 398 #define STAT_TX_FCS_ERRORS (0x1280) 399 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 400 #define STAT_TX_CARRIER_ERRORS (0x1288) 401 #define STAT_TX_BAD_BYTE_COUNT (0x128C) 402 #define STAT_TX_SINGLE_COLLISIONS (0x1290) 403 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 404 #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 405 #define STAT_TX_LATE_COLLISIONS (0x129C) 406 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 407 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 408 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 409 #define STAT_TX_UNICAST_FRAMES (0x12AC) 410 #define STAT_TX_BROADCAST_FRAMES (0x12B0) 411 #define STAT_TX_MULTICAST_FRAMES (0x12B4) 412 #define STAT_TX_PAUSE_FRAMES (0x12B8) 413 #define STAT_TX_64_BYTE_FRAMES (0x12BC) 414 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 415 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 416 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 417 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 418 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 419 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 420 #define STAT_TX_TOTAL_FRAMES (0x12D8) 421 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 422 #define STAT_EEE_TX_LPI_TIME (0x12E0) 423 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 424 425 /* End of Register definitions */ 426 427 #define LAN743X_MAX_RX_CHANNELS (4) 428 #define LAN743X_MAX_TX_CHANNELS (1) 429 struct lan743x_adapter; 430 431 #define LAN743X_USED_RX_CHANNELS (4) 432 #define LAN743X_USED_TX_CHANNELS (1) 433 #define LAN743X_INT_MOD (400) 434 435 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 436 #error Invalid LAN743X_USED_RX_CHANNELS 437 #endif 438 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 439 #error Invalid LAN743X_USED_TX_CHANNELS 440 #endif 441 442 /* PCI */ 443 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 444 #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 445 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 446 447 #define PCI_CONFIG_LENGTH (0x1000) 448 449 /* CSR */ 450 #define CSR_LENGTH (0x2000) 451 452 #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 453 #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 454 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 455 456 struct lan743x_csr { 457 u32 flags; 458 u8 __iomem *csr_address; 459 u32 id_rev; 460 u32 fpga_rev; 461 }; 462 463 /* INTERRUPTS */ 464 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 465 466 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 467 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 468 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 469 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 470 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 471 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 472 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 473 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 474 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 475 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 476 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 477 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 478 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 479 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 480 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 481 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 482 483 struct lan743x_vector { 484 int irq; 485 u32 flags; 486 struct lan743x_adapter *adapter; 487 int vector_index; 488 u32 int_mask; 489 lan743x_vector_handler handler; 490 void *context; 491 }; 492 493 #define LAN743X_MAX_VECTOR_COUNT (8) 494 495 struct lan743x_intr { 496 int flags; 497 498 unsigned int irq; 499 500 struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT]; 501 int number_of_vectors; 502 bool using_vectors; 503 504 int software_isr_flag; 505 }; 506 507 #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 508 509 /* PHY */ 510 struct lan743x_phy { 511 bool fc_autoneg; 512 u8 fc_request_control; 513 }; 514 515 /* TX */ 516 struct lan743x_tx_descriptor; 517 struct lan743x_tx_buffer_info; 518 519 #define GPIO_QUEUE_STARTED (0) 520 #define GPIO_TX_FUNCTION (1) 521 #define GPIO_TX_COMPLETION (2) 522 #define GPIO_TX_FRAGMENT (3) 523 524 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 525 526 struct lan743x_tx { 527 struct lan743x_adapter *adapter; 528 u32 vector_flags; 529 int channel_number; 530 531 int ring_size; 532 size_t ring_allocation_size; 533 struct lan743x_tx_descriptor *ring_cpu_ptr; 534 dma_addr_t ring_dma_ptr; 535 /* ring_lock: used to prevent concurrent access to tx ring */ 536 spinlock_t ring_lock; 537 u32 frame_flags; 538 u32 frame_first; 539 u32 frame_data0; 540 u32 frame_tail; 541 542 struct lan743x_tx_buffer_info *buffer_info; 543 544 u32 *head_cpu_ptr; 545 dma_addr_t head_dma_ptr; 546 int last_head; 547 int last_tail; 548 549 struct napi_struct napi; 550 551 struct sk_buff *overflow_skb; 552 }; 553 554 /* RX */ 555 struct lan743x_rx_descriptor; 556 struct lan743x_rx_buffer_info; 557 558 struct lan743x_rx { 559 struct lan743x_adapter *adapter; 560 u32 vector_flags; 561 int channel_number; 562 563 int ring_size; 564 size_t ring_allocation_size; 565 struct lan743x_rx_descriptor *ring_cpu_ptr; 566 dma_addr_t ring_dma_ptr; 567 568 struct lan743x_rx_buffer_info *buffer_info; 569 570 u32 *head_cpu_ptr; 571 dma_addr_t head_dma_ptr; 572 u32 last_head; 573 u32 last_tail; 574 575 struct napi_struct napi; 576 577 u32 frame_count; 578 }; 579 580 struct lan743x_adapter { 581 struct net_device *netdev; 582 struct mii_bus *mdiobus; 583 int msg_enable; 584 #ifdef CONFIG_PM 585 u32 wolopts; 586 #endif 587 struct pci_dev *pdev; 588 struct lan743x_csr csr; 589 struct lan743x_intr intr; 590 591 /* lock, used to prevent concurrent access to data port */ 592 struct mutex dp_lock; 593 594 u8 mac_address[ETH_ALEN]; 595 596 struct lan743x_phy phy; 597 struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS]; 598 struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS]; 599 }; 600 601 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 602 603 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 604 #define INTR_FLAG_MSI_ENABLED BIT(8) 605 #define INTR_FLAG_MSIX_ENABLED BIT(9) 606 607 #define MAC_MII_READ 1 608 #define MAC_MII_WRITE 0 609 610 #define PHY_FLAG_OPENED BIT(0) 611 #define PHY_FLAG_ATTACHED BIT(1) 612 613 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 614 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 615 #else 616 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 617 #endif 618 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 619 #define DMA_DESCRIPTOR_SPACING_16 (16) 620 #define DMA_DESCRIPTOR_SPACING_32 (32) 621 #define DMA_DESCRIPTOR_SPACING_64 (64) 622 #define DMA_DESCRIPTOR_SPACING_128 (128) 623 #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 624 625 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 626 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 627 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 628 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 629 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 630 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 631 632 /* TX Descriptor bits */ 633 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 634 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 635 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 636 #define TX_DESC_DATA0_FS_ (0x20000000) 637 #define TX_DESC_DATA0_LS_ (0x10000000) 638 #define TX_DESC_DATA0_EXT_ (0x08000000) 639 #define TX_DESC_DATA0_IOC_ (0x04000000) 640 #define TX_DESC_DATA0_ICE_ (0x00400000) 641 #define TX_DESC_DATA0_IPE_ (0x00200000) 642 #define TX_DESC_DATA0_TPE_ (0x00100000) 643 #define TX_DESC_DATA0_FCS_ (0x00020000) 644 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 645 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 646 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 647 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 648 649 struct lan743x_tx_descriptor { 650 u32 data0; 651 u32 data1; 652 u32 data2; 653 u32 data3; 654 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 655 656 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 657 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 658 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 659 struct lan743x_tx_buffer_info { 660 int flags; 661 struct sk_buff *skb; 662 dma_addr_t dma_ptr; 663 unsigned int buffer_length; 664 }; 665 666 #define LAN743X_TX_RING_SIZE (50) 667 668 /* OWN bit is set. ie, Descs are owned by RX DMAC */ 669 #define RX_DESC_DATA0_OWN_ (0x00008000) 670 /* OWN bit is clear. ie, Descs are owned by host */ 671 #define RX_DESC_DATA0_FS_ (0x80000000) 672 #define RX_DESC_DATA0_LS_ (0x40000000) 673 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 674 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 675 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 676 #define RX_DESC_DATA0_EXT_ (0x00004000) 677 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 678 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 679 680 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 681 #error NET_IP_ALIGN must be 0 or 2 682 #endif 683 684 #define RX_HEAD_PADDING NET_IP_ALIGN 685 686 struct lan743x_rx_descriptor { 687 u32 data0; 688 u32 data1; 689 u32 data2; 690 u32 data3; 691 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 692 693 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 694 struct lan743x_rx_buffer_info { 695 int flags; 696 struct sk_buff *skb; 697 698 dma_addr_t dma_ptr; 699 unsigned int buffer_length; 700 }; 701 702 #define LAN743X_RX_RING_SIZE (65) 703 704 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 705 #define RX_PROCESS_RESULT_PACKET_RECEIVED (1) 706 #define RX_PROCESS_RESULT_PACKET_DROPPED (2) 707 708 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 709 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 710 711 #endif /* _LAN743X_H */ 712