1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2018 Microchip Technology Inc. */ 3 4 #ifndef _LAN743X_H 5 #define _LAN743X_H 6 7 #include <linux/phy.h> 8 #include "lan743x_ptp.h" 9 10 #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 11 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 12 #define DRIVER_NAME "lan743x" 13 14 /* Register Definitions */ 15 #define ID_REV (0x00) 16 #define ID_REV_ID_MASK_ (0xFFFF0000) 17 #define ID_REV_ID_LAN7430_ (0x74300000) 18 #define ID_REV_ID_LAN7431_ (0x74310000) 19 #define ID_REV_ID_LAN743X_ (0x74300000) 20 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 21 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 22 #define ID_REV_ID_A0X1_ (0xA0010000) 23 #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ 25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) 26 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 27 #define ID_REV_CHIP_REV_A0_ (0x00000000) 28 #define ID_REV_CHIP_REV_B0_ (0x00000010) 29 30 #define FPGA_REV (0x04) 31 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 32 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 33 34 #define HW_CFG (0x010) 35 #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) 36 #define HW_CFG_EE_OTP_RELOAD_ BIT(4) 37 #define HW_CFG_LRST_ BIT(1) 38 39 #define PMT_CTL (0x014) 40 #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 41 #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 42 #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 43 #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 44 #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 45 #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 46 #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 47 #define PMT_CTL_READY_ BIT(7) 48 #define PMT_CTL_ETH_PHY_RST_ BIT(4) 49 #define PMT_CTL_WOL_EN_ BIT(3) 50 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 51 #define PMT_CTL_WUPS_MASK_ (0x00000003) 52 53 #define DP_SEL (0x024) 54 #define DP_SEL_DPRDY_ BIT(31) 55 #define DP_SEL_MASK_ (0x0000001F) 56 #define DP_SEL_RFE_RAM (0x00000001) 57 58 #define DP_SEL_VHF_HASH_LEN (16) 59 #define DP_SEL_VHF_VLAN_LEN (128) 60 61 #define DP_CMD (0x028) 62 #define DP_CMD_WRITE_ (0x00000001) 63 64 #define DP_ADDR (0x02C) 65 66 #define DP_DATA_0 (0x030) 67 68 #define E2P_CMD (0x040) 69 #define E2P_CMD_EPC_BUSY_ BIT(31) 70 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 71 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 72 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 73 #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 74 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 75 76 #define E2P_DATA (0x044) 77 78 #define GPIO_CFG0 (0x050) 79 #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 80 #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 81 82 #define GPIO_CFG1 (0x054) 83 #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 84 #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 85 86 #define GPIO_CFG2 (0x058) 87 #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 88 89 #define GPIO_CFG3 (0x05C) 90 #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 91 #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 92 93 #define FCT_RX_CTL (0xAC) 94 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 95 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 96 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 97 98 #define FCT_TX_CTL (0xC4) 99 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 100 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 101 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 102 103 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 104 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 105 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 106 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 107 #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 108 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 109 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 110 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 111 112 #define MAC_CR (0x100) 113 #define MAC_CR_MII_EN_ BIT(19) 114 #define MAC_CR_EEE_EN_ BIT(17) 115 #define MAC_CR_ADD_ BIT(12) 116 #define MAC_CR_ASD_ BIT(11) 117 #define MAC_CR_CNTR_RST_ BIT(5) 118 #define MAC_CR_DPX_ BIT(3) 119 #define MAC_CR_CFG_H_ BIT(2) 120 #define MAC_CR_CFG_L_ BIT(1) 121 #define MAC_CR_RST_ BIT(0) 122 123 #define MAC_RX (0x104) 124 #define MAC_RX_MAX_SIZE_SHIFT_ (16) 125 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 126 #define MAC_RX_RXD_ BIT(1) 127 #define MAC_RX_RXEN_ BIT(0) 128 129 #define MAC_TX (0x108) 130 #define MAC_TX_TXD_ BIT(1) 131 #define MAC_TX_TXEN_ BIT(0) 132 133 #define MAC_FLOW (0x10C) 134 #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 135 #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 136 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 137 138 #define MAC_RX_ADDRH (0x118) 139 140 #define MAC_RX_ADDRL (0x11C) 141 142 #define MAC_MII_ACC (0x120) 143 #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 144 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 145 #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 146 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 147 #define MAC_MII_ACC_MII_READ_ (0x00000000) 148 #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 149 #define MAC_MII_ACC_MII_BUSY_ BIT(0) 150 151 #define MAC_MII_DATA (0x124) 152 153 #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 154 155 #define MAC_WUCSR (0x140) 156 #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 157 #define MAC_WUCSR_PFDA_EN_ BIT(3) 158 #define MAC_WUCSR_WAKE_EN_ BIT(2) 159 #define MAC_WUCSR_MPEN_ BIT(1) 160 #define MAC_WUCSR_BCST_EN_ BIT(0) 161 162 #define MAC_WK_SRC (0x144) 163 164 #define MAC_WUF_CFG0 (0x150) 165 #define MAC_NUM_OF_WUF_CFG (32) 166 #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 167 #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 168 #define MAC_WUF_CFG_EN_ BIT(31) 169 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 170 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 171 #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 172 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 173 174 #define MAC_WUF_MASK0_0 (0x200) 175 #define MAC_WUF_MASK0_1 (0x204) 176 #define MAC_WUF_MASK0_2 (0x208) 177 #define MAC_WUF_MASK0_3 (0x20C) 178 #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 179 #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 180 #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 181 #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 182 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 183 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 184 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 185 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 186 187 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 188 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 189 #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 190 191 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 192 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 193 194 #define RFE_CTL (0x508) 195 #define RFE_CTL_AB_ BIT(10) 196 #define RFE_CTL_AM_ BIT(9) 197 #define RFE_CTL_AU_ BIT(8) 198 #define RFE_CTL_MCAST_HASH_ BIT(3) 199 #define RFE_CTL_DA_PERFECT_ BIT(1) 200 201 #define RFE_RSS_CFG (0x554) 202 #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 203 #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 204 #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 205 #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 206 #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 207 #define RFE_RSS_CFG_IPV6_ BIT(11) 208 #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 209 #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 210 #define RFE_RSS_CFG_IPV4_ BIT(8) 211 #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 212 #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 213 #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 214 #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 215 216 #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 217 218 #define RFE_INDX(index) (0x580 + (index << 2)) 219 220 #define MAC_WUCSR2 (0x600) 221 222 #define INT_STS (0x780) 223 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 224 #define INT_BIT_ALL_RX_ (0x0F000000) 225 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 226 #define INT_BIT_ALL_TX_ (0x000F0000) 227 #define INT_BIT_SW_GP_ BIT(9) 228 #define INT_BIT_1588_ BIT(7) 229 #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 230 #define INT_BIT_MAS_ BIT(0) 231 232 #define INT_SET (0x784) 233 234 #define INT_EN_SET (0x788) 235 236 #define INT_EN_CLR (0x78C) 237 238 #define INT_STS_R2C (0x790) 239 240 #define INT_VEC_EN_SET (0x794) 241 #define INT_VEC_EN_CLR (0x798) 242 #define INT_VEC_EN_AUTO_CLR (0x79C) 243 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 244 245 #define INT_VEC_MAP0 (0x7A0) 246 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 247 (((u32)(vector)) << ((channel) << 2)) 248 249 #define INT_VEC_MAP1 (0x7A4) 250 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 251 (((u32)(vector)) << ((channel) << 2)) 252 253 #define INT_VEC_MAP2 (0x7A8) 254 255 #define INT_MOD_MAP0 (0x7B0) 256 257 #define INT_MOD_MAP1 (0x7B4) 258 259 #define INT_MOD_MAP2 (0x7B8) 260 261 #define INT_MOD_CFG0 (0x7C0) 262 #define INT_MOD_CFG1 (0x7C4) 263 #define INT_MOD_CFG2 (0x7C8) 264 #define INT_MOD_CFG3 (0x7CC) 265 #define INT_MOD_CFG4 (0x7D0) 266 #define INT_MOD_CFG5 (0x7D4) 267 #define INT_MOD_CFG6 (0x7D8) 268 #define INT_MOD_CFG7 (0x7DC) 269 270 #define PTP_CMD_CTL (0x0A00) 271 #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 272 #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 273 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 274 #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 275 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 276 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 277 #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 278 #define PTP_GENERAL_CONFIG (0x0A04) 279 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 280 (0x7 << (1 + ((channel) << 2))) 281 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 282 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 283 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 284 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 285 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 286 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 287 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) 288 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 289 (((value) & 0x7) << (1 + ((channel) << 2))) 290 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 291 292 #define PTP_INT_STS (0x0A08) 293 #define PTP_INT_EN_SET (0x0A0C) 294 #define PTP_INT_EN_CLR (0x0A10) 295 #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 296 #define PTP_INT_BIT_TX_TS_ BIT(12) 297 #define PTP_INT_BIT_TIMER_B_ BIT(1) 298 #define PTP_INT_BIT_TIMER_A_ BIT(0) 299 300 #define PTP_CLOCK_SEC (0x0A14) 301 #define PTP_CLOCK_NS (0x0A18) 302 #define PTP_CLOCK_SUBNS (0x0A1C) 303 #define PTP_CLOCK_RATE_ADJ (0x0A20) 304 #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 305 #define PTP_CLOCK_STEP_ADJ (0x0A2C) 306 #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 307 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 308 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 309 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 310 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 311 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 312 #define PTP_LATENCY (0x0A5C) 313 #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 314 #define PTP_LATENCY_RX_SET_(rx_latency) \ 315 (((u32)(rx_latency)) & 0x0000FFFF) 316 #define PTP_CAP_INFO (0x0A60) 317 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 318 319 #define PTP_TX_MOD (0x0AA4) 320 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 321 322 #define PTP_TX_MOD2 (0x0AA8) 323 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 324 325 #define PTP_TX_EGRESS_SEC (0x0AAC) 326 #define PTP_TX_EGRESS_NS (0x0AB0) 327 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 328 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 329 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 330 #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 331 332 #define PTP_TX_MSG_HEADER (0x0AB4) 333 #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 334 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 335 336 #define DMAC_CFG (0xC00) 337 #define DMAC_CFG_COAL_EN_ BIT(16) 338 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 339 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 340 #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 341 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 342 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 343 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 344 #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 345 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 346 347 #define DMAC_COAL_CFG (0xC04) 348 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 349 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 350 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 351 #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 352 #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 353 #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 354 #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 355 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 356 #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 357 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 358 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 359 #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 360 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 361 362 #define DMAC_OBFF_CFG (0xC08) 363 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 364 #define DMAC_OBFF_TX_THRES_SET_(val) \ 365 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 366 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 367 #define DMAC_OBFF_RX_THRES_SET_(val) \ 368 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 369 370 #define DMAC_CMD (0xC0C) 371 #define DMAC_CMD_SWR_ BIT(31) 372 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 373 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 374 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 375 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 376 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 377 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 378 379 #define DMAC_INT_STS (0xC10) 380 #define DMAC_INT_EN_SET (0xC14) 381 #define DMAC_INT_EN_CLR (0xC18) 382 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 383 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 384 385 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 386 #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 387 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 388 #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 389 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 390 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 391 #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 392 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 393 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 394 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 395 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 396 #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 397 398 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 399 #define RX_CFG_B_TS_ALL_RX_ BIT(29) 400 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 401 #define RX_CFG_B_RX_PAD_0_ (0x00000000) 402 #define RX_CFG_B_RX_PAD_2_ (0x02000000) 403 #define RX_CFG_B_RDMABL_512_ (0x00040000) 404 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 405 406 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 407 408 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 409 410 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 411 412 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 413 414 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 415 416 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 417 #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 418 #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 419 420 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 421 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 422 #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 423 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 424 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 425 426 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 427 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 428 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 429 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 430 #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 431 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 432 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 433 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 434 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 435 #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 436 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 437 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 438 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 439 440 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 441 #define TX_CFG_B_TDMABL_512_ (0x00040000) 442 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 443 444 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 445 446 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 447 448 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 449 450 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 451 452 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 453 454 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 455 #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 456 #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 457 #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 458 459 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 460 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 461 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 462 #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 463 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 464 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 465 466 #define OTP_PWR_DN (0x1000) 467 #define OTP_PWR_DN_PWRDN_N_ BIT(0) 468 469 #define OTP_ADDR_HIGH (0x1004) 470 #define OTP_ADDR_LOW (0x1008) 471 472 #define OTP_PRGM_DATA (0x1010) 473 474 #define OTP_PRGM_MODE (0x1014) 475 #define OTP_PRGM_MODE_BYTE_ BIT(0) 476 477 #define OTP_READ_DATA (0x1018) 478 479 #define OTP_FUNC_CMD (0x1020) 480 #define OTP_FUNC_CMD_READ_ BIT(0) 481 482 #define OTP_TST_CMD (0x1024) 483 #define OTP_TST_CMD_PRGVRFY_ BIT(3) 484 485 #define OTP_CMD_GO (0x1028) 486 #define OTP_CMD_GO_GO_ BIT(0) 487 488 #define OTP_STATUS (0x1030) 489 #define OTP_STATUS_BUSY_ BIT(0) 490 491 /* MAC statistics registers */ 492 #define STAT_RX_FCS_ERRORS (0x1200) 493 #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 494 #define STAT_RX_FRAGMENT_ERRORS (0x1208) 495 #define STAT_RX_JABBER_ERRORS (0x120C) 496 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 497 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 498 #define STAT_RX_DROPPED_FRAMES (0x1218) 499 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 500 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 501 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 502 #define STAT_RX_UNICAST_FRAMES (0x1228) 503 #define STAT_RX_BROADCAST_FRAMES (0x122C) 504 #define STAT_RX_MULTICAST_FRAMES (0x1230) 505 #define STAT_RX_PAUSE_FRAMES (0x1234) 506 #define STAT_RX_64_BYTE_FRAMES (0x1238) 507 #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 508 #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 509 #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 510 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 511 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 512 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 513 #define STAT_RX_TOTAL_FRAMES (0x1254) 514 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 515 #define STAT_EEE_RX_LPI_TIME (0x125C) 516 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 517 518 #define STAT_TX_FCS_ERRORS (0x1280) 519 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 520 #define STAT_TX_CARRIER_ERRORS (0x1288) 521 #define STAT_TX_BAD_BYTE_COUNT (0x128C) 522 #define STAT_TX_SINGLE_COLLISIONS (0x1290) 523 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 524 #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 525 #define STAT_TX_LATE_COLLISIONS (0x129C) 526 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 527 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 528 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 529 #define STAT_TX_UNICAST_FRAMES (0x12AC) 530 #define STAT_TX_BROADCAST_FRAMES (0x12B0) 531 #define STAT_TX_MULTICAST_FRAMES (0x12B4) 532 #define STAT_TX_PAUSE_FRAMES (0x12B8) 533 #define STAT_TX_64_BYTE_FRAMES (0x12BC) 534 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 535 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 536 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 537 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 538 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 539 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 540 #define STAT_TX_TOTAL_FRAMES (0x12D8) 541 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 542 #define STAT_EEE_TX_LPI_TIME (0x12E0) 543 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 544 545 /* End of Register definitions */ 546 547 #define LAN743X_MAX_RX_CHANNELS (4) 548 #define LAN743X_MAX_TX_CHANNELS (1) 549 struct lan743x_adapter; 550 551 #define LAN743X_USED_RX_CHANNELS (4) 552 #define LAN743X_USED_TX_CHANNELS (1) 553 #define LAN743X_INT_MOD (400) 554 555 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 556 #error Invalid LAN743X_USED_RX_CHANNELS 557 #endif 558 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 559 #error Invalid LAN743X_USED_TX_CHANNELS 560 #endif 561 562 /* PCI */ 563 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 564 #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 565 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 566 #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) 567 #define PCI_DEVICE_ID_SMSC_A011 (0xA011) 568 #define PCI_DEVICE_ID_SMSC_A041 (0xA041) 569 570 #define PCI_CONFIG_LENGTH (0x1000) 571 572 /* CSR */ 573 #define CSR_LENGTH (0x2000) 574 575 #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 576 #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 577 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 578 579 struct lan743x_csr { 580 u32 flags; 581 u8 __iomem *csr_address; 582 u32 id_rev; 583 u32 fpga_rev; 584 }; 585 586 /* INTERRUPTS */ 587 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 588 589 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 590 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 591 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 592 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 593 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 594 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 595 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 596 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 597 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 598 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 599 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 600 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 601 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 602 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 603 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 604 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 605 606 struct lan743x_vector { 607 int irq; 608 u32 flags; 609 struct lan743x_adapter *adapter; 610 int vector_index; 611 u32 int_mask; 612 lan743x_vector_handler handler; 613 void *context; 614 }; 615 616 #define LAN743X_MAX_VECTOR_COUNT (8) 617 618 struct lan743x_intr { 619 int flags; 620 621 unsigned int irq; 622 623 struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT]; 624 int number_of_vectors; 625 bool using_vectors; 626 627 bool software_isr_flag; 628 wait_queue_head_t software_isr_wq; 629 }; 630 631 #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 632 633 /* PHY */ 634 struct lan743x_phy { 635 bool fc_autoneg; 636 u8 fc_request_control; 637 }; 638 639 /* TX */ 640 struct lan743x_tx_descriptor; 641 struct lan743x_tx_buffer_info; 642 643 #define GPIO_QUEUE_STARTED (0) 644 #define GPIO_TX_FUNCTION (1) 645 #define GPIO_TX_COMPLETION (2) 646 #define GPIO_TX_FRAGMENT (3) 647 648 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 649 650 #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 651 #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 652 653 struct lan743x_tx { 654 struct lan743x_adapter *adapter; 655 u32 ts_flags; 656 u32 vector_flags; 657 int channel_number; 658 659 int ring_size; 660 size_t ring_allocation_size; 661 struct lan743x_tx_descriptor *ring_cpu_ptr; 662 dma_addr_t ring_dma_ptr; 663 /* ring_lock: used to prevent concurrent access to tx ring */ 664 spinlock_t ring_lock; 665 u32 frame_flags; 666 u32 frame_first; 667 u32 frame_data0; 668 u32 frame_tail; 669 670 struct lan743x_tx_buffer_info *buffer_info; 671 672 __le32 *head_cpu_ptr; 673 dma_addr_t head_dma_ptr; 674 int last_head; 675 int last_tail; 676 677 struct napi_struct napi; 678 679 struct sk_buff *overflow_skb; 680 }; 681 682 void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 683 bool enable_timestamping, 684 bool enable_onestep_sync); 685 686 /* RX */ 687 struct lan743x_rx_descriptor; 688 struct lan743x_rx_buffer_info; 689 690 struct lan743x_rx { 691 struct lan743x_adapter *adapter; 692 u32 vector_flags; 693 int channel_number; 694 695 int ring_size; 696 size_t ring_allocation_size; 697 struct lan743x_rx_descriptor *ring_cpu_ptr; 698 dma_addr_t ring_dma_ptr; 699 700 struct lan743x_rx_buffer_info *buffer_info; 701 702 __le32 *head_cpu_ptr; 703 dma_addr_t head_dma_ptr; 704 u32 last_head; 705 u32 last_tail; 706 707 struct napi_struct napi; 708 709 u32 frame_count; 710 711 struct sk_buff *skb_head, *skb_tail; 712 }; 713 714 struct lan743x_adapter { 715 struct net_device *netdev; 716 struct mii_bus *mdiobus; 717 int msg_enable; 718 #ifdef CONFIG_PM 719 u32 wolopts; 720 #endif 721 struct pci_dev *pdev; 722 struct lan743x_csr csr; 723 struct lan743x_intr intr; 724 725 struct lan743x_gpio gpio; 726 struct lan743x_ptp ptp; 727 728 u8 mac_address[ETH_ALEN]; 729 730 struct lan743x_phy phy; 731 struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS]; 732 struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS]; 733 734 #define LAN743X_ADAPTER_FLAG_OTP BIT(0) 735 u32 flags; 736 }; 737 738 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 739 740 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 741 #define INTR_FLAG_MSI_ENABLED BIT(8) 742 #define INTR_FLAG_MSIX_ENABLED BIT(9) 743 744 #define MAC_MII_READ 1 745 #define MAC_MII_WRITE 0 746 747 #define PHY_FLAG_OPENED BIT(0) 748 #define PHY_FLAG_ATTACHED BIT(1) 749 750 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 751 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 752 #else 753 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 754 #endif 755 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 756 #define DMA_DESCRIPTOR_SPACING_16 (16) 757 #define DMA_DESCRIPTOR_SPACING_32 (32) 758 #define DMA_DESCRIPTOR_SPACING_64 (64) 759 #define DMA_DESCRIPTOR_SPACING_128 (128) 760 #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 761 762 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 763 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 764 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 765 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 766 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 767 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 768 769 /* TX Descriptor bits */ 770 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 771 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 772 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 773 #define TX_DESC_DATA0_FS_ (0x20000000) 774 #define TX_DESC_DATA0_LS_ (0x10000000) 775 #define TX_DESC_DATA0_EXT_ (0x08000000) 776 #define TX_DESC_DATA0_IOC_ (0x04000000) 777 #define TX_DESC_DATA0_ICE_ (0x00400000) 778 #define TX_DESC_DATA0_IPE_ (0x00200000) 779 #define TX_DESC_DATA0_TPE_ (0x00100000) 780 #define TX_DESC_DATA0_FCS_ (0x00020000) 781 #define TX_DESC_DATA0_TSE_ (0x00010000) 782 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 783 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 784 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 785 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 786 787 struct lan743x_tx_descriptor { 788 __le32 data0; 789 __le32 data1; 790 __le32 data2; 791 __le32 data3; 792 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 793 794 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 795 #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 796 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 797 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 798 struct lan743x_tx_buffer_info { 799 int flags; 800 struct sk_buff *skb; 801 dma_addr_t dma_ptr; 802 unsigned int buffer_length; 803 }; 804 805 #define LAN743X_TX_RING_SIZE (50) 806 807 /* OWN bit is set. ie, Descs are owned by RX DMAC */ 808 #define RX_DESC_DATA0_OWN_ (0x00008000) 809 /* OWN bit is clear. ie, Descs are owned by host */ 810 #define RX_DESC_DATA0_FS_ (0x80000000) 811 #define RX_DESC_DATA0_LS_ (0x40000000) 812 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 813 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 814 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 815 #define RX_DESC_DATA0_EXT_ (0x00004000) 816 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 817 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 818 819 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 820 #error NET_IP_ALIGN must be 0 or 2 821 #endif 822 823 #define RX_HEAD_PADDING NET_IP_ALIGN 824 825 struct lan743x_rx_descriptor { 826 __le32 data0; 827 __le32 data1; 828 __le32 data2; 829 __le32 data3; 830 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 831 832 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 833 struct lan743x_rx_buffer_info { 834 int flags; 835 struct sk_buff *skb; 836 837 dma_addr_t dma_ptr; 838 unsigned int buffer_length; 839 }; 840 841 #define LAN743X_RX_RING_SIZE (128) 842 843 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 844 #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) 845 846 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 847 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 848 849 #endif /* _LAN743X_H */ 850