1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2018 Microchip Technology Inc. */ 3 4 #ifndef _LAN743X_H 5 #define _LAN743X_H 6 7 #include <linux/phy.h> 8 #include "lan743x_ptp.h" 9 10 #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 11 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 12 #define DRIVER_NAME "lan743x" 13 14 /* Register Definitions */ 15 #define ID_REV (0x00) 16 #define ID_REV_ID_MASK_ (0xFFFF0000) 17 #define ID_REV_ID_LAN7430_ (0x74300000) 18 #define ID_REV_ID_LAN7431_ (0x74310000) 19 #define ID_REV_ID_LAN743X_ (0x74300000) 20 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 21 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 22 #define ID_REV_ID_A0X1_ (0xA0010000) 23 #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ 25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) 26 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 27 #define ID_REV_CHIP_REV_A0_ (0x00000000) 28 #define ID_REV_CHIP_REV_B0_ (0x00000010) 29 30 #define FPGA_REV (0x04) 31 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 32 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 33 #define FPGA_SGMII_OP BIT(24) 34 35 #define STRAP_READ (0x0C) 36 #define STRAP_READ_USE_SGMII_EN_ BIT(22) 37 #define STRAP_READ_SGMII_EN_ BIT(6) 38 #define STRAP_READ_SGMII_REFCLK_ BIT(5) 39 #define STRAP_READ_SGMII_2_5G_ BIT(4) 40 #define STRAP_READ_BASE_X_ BIT(3) 41 #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2) 42 #define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1) 43 #define STRAP_READ_ADV_PM_DISABLE_ BIT(0) 44 45 #define HW_CFG (0x010) 46 #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) 47 #define HW_CFG_EE_OTP_RELOAD_ BIT(4) 48 #define HW_CFG_LRST_ BIT(1) 49 50 #define PMT_CTL (0x014) 51 #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 52 #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 53 #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 54 #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 55 #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 56 #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 57 #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 58 #define PMT_CTL_READY_ BIT(7) 59 #define PMT_CTL_ETH_PHY_RST_ BIT(4) 60 #define PMT_CTL_WOL_EN_ BIT(3) 61 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 62 #define PMT_CTL_WUPS_MASK_ (0x00000003) 63 64 #define DP_SEL (0x024) 65 #define DP_SEL_DPRDY_ BIT(31) 66 #define DP_SEL_MASK_ (0x0000001F) 67 #define DP_SEL_RFE_RAM (0x00000001) 68 69 #define DP_SEL_VHF_HASH_LEN (16) 70 #define DP_SEL_VHF_VLAN_LEN (128) 71 72 #define DP_CMD (0x028) 73 #define DP_CMD_WRITE_ (0x00000001) 74 75 #define DP_ADDR (0x02C) 76 77 #define DP_DATA_0 (0x030) 78 79 #define E2P_CMD (0x040) 80 #define E2P_CMD_EPC_BUSY_ BIT(31) 81 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 82 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 83 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 84 #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 85 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 86 87 #define E2P_DATA (0x044) 88 89 #define GPIO_CFG0 (0x050) 90 #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 91 #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 92 93 #define GPIO_CFG1 (0x054) 94 #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 95 #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 96 97 #define GPIO_CFG2 (0x058) 98 #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 99 100 #define GPIO_CFG3 (0x05C) 101 #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 102 #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 103 104 #define FCT_RX_CTL (0xAC) 105 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 106 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 107 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 108 109 #define FCT_TX_CTL (0xC4) 110 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 111 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 112 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 113 114 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 115 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 116 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 117 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 118 #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 119 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 120 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 121 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 122 123 #define MAC_CR (0x100) 124 #define MAC_CR_MII_EN_ BIT(19) 125 #define MAC_CR_EEE_EN_ BIT(17) 126 #define MAC_CR_ADD_ BIT(12) 127 #define MAC_CR_ASD_ BIT(11) 128 #define MAC_CR_CNTR_RST_ BIT(5) 129 #define MAC_CR_DPX_ BIT(3) 130 #define MAC_CR_CFG_H_ BIT(2) 131 #define MAC_CR_CFG_L_ BIT(1) 132 #define MAC_CR_RST_ BIT(0) 133 134 #define MAC_RX (0x104) 135 #define MAC_RX_MAX_SIZE_SHIFT_ (16) 136 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 137 #define MAC_RX_RXD_ BIT(1) 138 #define MAC_RX_RXEN_ BIT(0) 139 140 #define MAC_TX (0x108) 141 #define MAC_TX_TXD_ BIT(1) 142 #define MAC_TX_TXEN_ BIT(0) 143 144 #define MAC_FLOW (0x10C) 145 #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 146 #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 147 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 148 149 #define MAC_RX_ADDRH (0x118) 150 151 #define MAC_RX_ADDRL (0x11C) 152 153 #define MAC_MII_ACC (0x120) 154 #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 155 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 156 #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 157 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 158 #define MAC_MII_ACC_MII_READ_ (0x00000000) 159 #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 160 #define MAC_MII_ACC_MII_BUSY_ BIT(0) 161 162 #define MAC_MII_DATA (0x124) 163 164 #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 165 166 #define MAC_WUCSR (0x140) 167 #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 168 #define MAC_WUCSR_PFDA_EN_ BIT(3) 169 #define MAC_WUCSR_WAKE_EN_ BIT(2) 170 #define MAC_WUCSR_MPEN_ BIT(1) 171 #define MAC_WUCSR_BCST_EN_ BIT(0) 172 173 #define MAC_WK_SRC (0x144) 174 175 #define MAC_WUF_CFG0 (0x150) 176 #define MAC_NUM_OF_WUF_CFG (32) 177 #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 178 #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 179 #define MAC_WUF_CFG_EN_ BIT(31) 180 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 181 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 182 #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 183 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 184 185 #define MAC_WUF_MASK0_0 (0x200) 186 #define MAC_WUF_MASK0_1 (0x204) 187 #define MAC_WUF_MASK0_2 (0x208) 188 #define MAC_WUF_MASK0_3 (0x20C) 189 #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 190 #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 191 #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 192 #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 193 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 194 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 195 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 196 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 197 198 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 199 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 200 #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 201 202 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 203 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 204 205 #define RFE_CTL (0x508) 206 #define RFE_CTL_AB_ BIT(10) 207 #define RFE_CTL_AM_ BIT(9) 208 #define RFE_CTL_AU_ BIT(8) 209 #define RFE_CTL_MCAST_HASH_ BIT(3) 210 #define RFE_CTL_DA_PERFECT_ BIT(1) 211 212 #define RFE_RSS_CFG (0x554) 213 #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 214 #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 215 #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 216 #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 217 #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 218 #define RFE_RSS_CFG_IPV6_ BIT(11) 219 #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 220 #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 221 #define RFE_RSS_CFG_IPV4_ BIT(8) 222 #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 223 #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 224 #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 225 #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 226 227 #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 228 229 #define RFE_INDX(index) (0x580 + (index << 2)) 230 231 #define MAC_WUCSR2 (0x600) 232 233 #define SGMII_CTL (0x728) 234 #define SGMII_CTL_SGMII_ENABLE_ BIT(31) 235 #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8) 236 #define SGMII_CTL_SGMII_POWER_DN_ BIT(1) 237 238 #define INT_STS (0x780) 239 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 240 #define INT_BIT_ALL_RX_ (0x0F000000) 241 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 242 #define INT_BIT_ALL_TX_ (0x000F0000) 243 #define INT_BIT_SW_GP_ BIT(9) 244 #define INT_BIT_1588_ BIT(7) 245 #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 246 #define INT_BIT_MAS_ BIT(0) 247 248 #define INT_SET (0x784) 249 250 #define INT_EN_SET (0x788) 251 252 #define INT_EN_CLR (0x78C) 253 254 #define INT_STS_R2C (0x790) 255 256 #define INT_VEC_EN_SET (0x794) 257 #define INT_VEC_EN_CLR (0x798) 258 #define INT_VEC_EN_AUTO_CLR (0x79C) 259 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 260 261 #define INT_VEC_MAP0 (0x7A0) 262 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 263 (((u32)(vector)) << ((channel) << 2)) 264 265 #define INT_VEC_MAP1 (0x7A4) 266 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 267 (((u32)(vector)) << ((channel) << 2)) 268 269 #define INT_VEC_MAP2 (0x7A8) 270 271 #define INT_MOD_MAP0 (0x7B0) 272 273 #define INT_MOD_MAP1 (0x7B4) 274 275 #define INT_MOD_MAP2 (0x7B8) 276 277 #define INT_MOD_CFG0 (0x7C0) 278 #define INT_MOD_CFG1 (0x7C4) 279 #define INT_MOD_CFG2 (0x7C8) 280 #define INT_MOD_CFG3 (0x7CC) 281 #define INT_MOD_CFG4 (0x7D0) 282 #define INT_MOD_CFG5 (0x7D4) 283 #define INT_MOD_CFG6 (0x7D8) 284 #define INT_MOD_CFG7 (0x7DC) 285 #define INT_MOD_CFG8 (0x7E0) 286 #define INT_MOD_CFG9 (0x7E4) 287 288 #define PTP_CMD_CTL (0x0A00) 289 #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 290 #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 291 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 292 #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 293 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 294 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 295 #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 296 #define PTP_GENERAL_CONFIG (0x0A04) 297 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 298 (0x7 << (1 + ((channel) << 2))) 299 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 300 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 301 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 302 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 303 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 304 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 305 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) 306 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 307 (((value) & 0x7) << (1 + ((channel) << 2))) 308 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 309 310 #define PTP_INT_STS (0x0A08) 311 #define PTP_INT_EN_SET (0x0A0C) 312 #define PTP_INT_EN_CLR (0x0A10) 313 #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 314 #define PTP_INT_BIT_TX_TS_ BIT(12) 315 #define PTP_INT_BIT_TIMER_B_ BIT(1) 316 #define PTP_INT_BIT_TIMER_A_ BIT(0) 317 318 #define PTP_CLOCK_SEC (0x0A14) 319 #define PTP_CLOCK_NS (0x0A18) 320 #define PTP_CLOCK_SUBNS (0x0A1C) 321 #define PTP_CLOCK_RATE_ADJ (0x0A20) 322 #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 323 #define PTP_CLOCK_STEP_ADJ (0x0A2C) 324 #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 325 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 326 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 327 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 328 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 329 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 330 #define PTP_LATENCY (0x0A5C) 331 #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 332 #define PTP_LATENCY_RX_SET_(rx_latency) \ 333 (((u32)(rx_latency)) & 0x0000FFFF) 334 #define PTP_CAP_INFO (0x0A60) 335 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 336 337 #define PTP_TX_MOD (0x0AA4) 338 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 339 340 #define PTP_TX_MOD2 (0x0AA8) 341 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 342 343 #define PTP_TX_EGRESS_SEC (0x0AAC) 344 #define PTP_TX_EGRESS_NS (0x0AB0) 345 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 346 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 347 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 348 #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 349 350 #define PTP_TX_MSG_HEADER (0x0AB4) 351 #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 352 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 353 354 #define DMAC_CFG (0xC00) 355 #define DMAC_CFG_COAL_EN_ BIT(16) 356 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 357 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 358 #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 359 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 360 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 361 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 362 #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 363 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 364 365 #define DMAC_COAL_CFG (0xC04) 366 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 367 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 368 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 369 #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 370 #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 371 #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 372 #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 373 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 374 #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 375 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 376 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 377 #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 378 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 379 380 #define DMAC_OBFF_CFG (0xC08) 381 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 382 #define DMAC_OBFF_TX_THRES_SET_(val) \ 383 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 384 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 385 #define DMAC_OBFF_RX_THRES_SET_(val) \ 386 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 387 388 #define DMAC_CMD (0xC0C) 389 #define DMAC_CMD_SWR_ BIT(31) 390 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 391 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 392 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 393 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 394 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 395 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 396 397 #define DMAC_INT_STS (0xC10) 398 #define DMAC_INT_EN_SET (0xC14) 399 #define DMAC_INT_EN_CLR (0xC18) 400 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 401 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 402 403 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 404 #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 405 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 406 #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 407 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 408 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 409 #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 410 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 411 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 412 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 413 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 414 #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 415 416 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 417 #define RX_CFG_B_TS_ALL_RX_ BIT(29) 418 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 419 #define RX_CFG_B_RX_PAD_0_ (0x00000000) 420 #define RX_CFG_B_RX_PAD_2_ (0x02000000) 421 #define RX_CFG_B_RDMABL_512_ (0x00040000) 422 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 423 424 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 425 426 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 427 428 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 429 430 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 431 432 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 433 434 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 435 #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 436 #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 437 438 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 439 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 440 #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 441 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 442 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 443 444 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 445 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 446 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 447 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 448 #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 449 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 450 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 451 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 452 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 453 #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 454 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 455 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 456 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 457 458 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 459 #define TX_CFG_B_TDMABL_512_ (0x00040000) 460 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 461 462 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 463 464 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 465 466 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 467 468 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 469 470 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 471 472 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 473 #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 474 #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 475 #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 476 477 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 478 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 479 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 480 #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 481 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 482 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 483 484 #define OTP_PWR_DN (0x1000) 485 #define OTP_PWR_DN_PWRDN_N_ BIT(0) 486 487 #define OTP_ADDR_HIGH (0x1004) 488 #define OTP_ADDR_LOW (0x1008) 489 490 #define OTP_PRGM_DATA (0x1010) 491 492 #define OTP_PRGM_MODE (0x1014) 493 #define OTP_PRGM_MODE_BYTE_ BIT(0) 494 495 #define OTP_READ_DATA (0x1018) 496 497 #define OTP_FUNC_CMD (0x1020) 498 #define OTP_FUNC_CMD_READ_ BIT(0) 499 500 #define OTP_TST_CMD (0x1024) 501 #define OTP_TST_CMD_PRGVRFY_ BIT(3) 502 503 #define OTP_CMD_GO (0x1028) 504 #define OTP_CMD_GO_GO_ BIT(0) 505 506 #define OTP_STATUS (0x1030) 507 #define OTP_STATUS_BUSY_ BIT(0) 508 509 /* MAC statistics registers */ 510 #define STAT_RX_FCS_ERRORS (0x1200) 511 #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 512 #define STAT_RX_FRAGMENT_ERRORS (0x1208) 513 #define STAT_RX_JABBER_ERRORS (0x120C) 514 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 515 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 516 #define STAT_RX_DROPPED_FRAMES (0x1218) 517 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 518 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 519 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 520 #define STAT_RX_UNICAST_FRAMES (0x1228) 521 #define STAT_RX_BROADCAST_FRAMES (0x122C) 522 #define STAT_RX_MULTICAST_FRAMES (0x1230) 523 #define STAT_RX_PAUSE_FRAMES (0x1234) 524 #define STAT_RX_64_BYTE_FRAMES (0x1238) 525 #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 526 #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 527 #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 528 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 529 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 530 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 531 #define STAT_RX_TOTAL_FRAMES (0x1254) 532 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 533 #define STAT_EEE_RX_LPI_TIME (0x125C) 534 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 535 536 #define STAT_TX_FCS_ERRORS (0x1280) 537 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 538 #define STAT_TX_CARRIER_ERRORS (0x1288) 539 #define STAT_TX_BAD_BYTE_COUNT (0x128C) 540 #define STAT_TX_SINGLE_COLLISIONS (0x1290) 541 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 542 #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 543 #define STAT_TX_LATE_COLLISIONS (0x129C) 544 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 545 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 546 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 547 #define STAT_TX_UNICAST_FRAMES (0x12AC) 548 #define STAT_TX_BROADCAST_FRAMES (0x12B0) 549 #define STAT_TX_MULTICAST_FRAMES (0x12B4) 550 #define STAT_TX_PAUSE_FRAMES (0x12B8) 551 #define STAT_TX_64_BYTE_FRAMES (0x12BC) 552 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 553 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 554 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 555 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 556 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 557 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 558 #define STAT_TX_TOTAL_FRAMES (0x12D8) 559 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 560 #define STAT_EEE_TX_LPI_TIME (0x12E0) 561 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 562 563 /* End of Register definitions */ 564 565 #define LAN743X_MAX_RX_CHANNELS (4) 566 #define LAN743X_MAX_TX_CHANNELS (1) 567 #define PCI11X1X_MAX_TX_CHANNELS (4) 568 struct lan743x_adapter; 569 570 #define LAN743X_USED_RX_CHANNELS (4) 571 #define LAN743X_USED_TX_CHANNELS (1) 572 #define PCI11X1X_USED_TX_CHANNELS (4) 573 #define LAN743X_INT_MOD (400) 574 575 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 576 #error Invalid LAN743X_USED_RX_CHANNELS 577 #endif 578 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 579 #error Invalid LAN743X_USED_TX_CHANNELS 580 #endif 581 #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS) 582 #error Invalid PCI11X1X_USED_TX_CHANNELS 583 #endif 584 585 /* PCI */ 586 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 587 #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 588 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 589 #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) 590 #define PCI_DEVICE_ID_SMSC_A011 (0xA011) 591 #define PCI_DEVICE_ID_SMSC_A041 (0xA041) 592 593 #define PCI_CONFIG_LENGTH (0x1000) 594 595 /* CSR */ 596 #define CSR_LENGTH (0x2000) 597 598 #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 599 #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 600 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 601 602 struct lan743x_csr { 603 u32 flags; 604 u8 __iomem *csr_address; 605 u32 id_rev; 606 u32 fpga_rev; 607 }; 608 609 /* INTERRUPTS */ 610 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 611 612 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 613 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 614 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 615 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 616 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 617 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 618 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 619 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 620 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 621 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 622 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 623 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 624 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 625 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 626 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 627 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 628 629 struct lan743x_vector { 630 int irq; 631 u32 flags; 632 struct lan743x_adapter *adapter; 633 int vector_index; 634 u32 int_mask; 635 lan743x_vector_handler handler; 636 void *context; 637 }; 638 639 #define LAN743X_MAX_VECTOR_COUNT (8) 640 #define PCI11X1X_MAX_VECTOR_COUNT (16) 641 642 struct lan743x_intr { 643 int flags; 644 645 unsigned int irq; 646 647 struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT]; 648 int number_of_vectors; 649 bool using_vectors; 650 651 bool software_isr_flag; 652 wait_queue_head_t software_isr_wq; 653 }; 654 655 #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 656 657 /* PHY */ 658 struct lan743x_phy { 659 bool fc_autoneg; 660 u8 fc_request_control; 661 }; 662 663 /* TX */ 664 struct lan743x_tx_descriptor; 665 struct lan743x_tx_buffer_info; 666 667 #define GPIO_QUEUE_STARTED (0) 668 #define GPIO_TX_FUNCTION (1) 669 #define GPIO_TX_COMPLETION (2) 670 #define GPIO_TX_FRAGMENT (3) 671 672 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 673 674 #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 675 #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 676 677 struct lan743x_tx { 678 struct lan743x_adapter *adapter; 679 u32 ts_flags; 680 u32 vector_flags; 681 int channel_number; 682 683 int ring_size; 684 size_t ring_allocation_size; 685 struct lan743x_tx_descriptor *ring_cpu_ptr; 686 dma_addr_t ring_dma_ptr; 687 /* ring_lock: used to prevent concurrent access to tx ring */ 688 spinlock_t ring_lock; 689 u32 frame_flags; 690 u32 frame_first; 691 u32 frame_data0; 692 u32 frame_tail; 693 694 struct lan743x_tx_buffer_info *buffer_info; 695 696 __le32 *head_cpu_ptr; 697 dma_addr_t head_dma_ptr; 698 int last_head; 699 int last_tail; 700 701 struct napi_struct napi; 702 703 struct sk_buff *overflow_skb; 704 }; 705 706 void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 707 bool enable_timestamping, 708 bool enable_onestep_sync); 709 710 /* RX */ 711 struct lan743x_rx_descriptor; 712 struct lan743x_rx_buffer_info; 713 714 struct lan743x_rx { 715 struct lan743x_adapter *adapter; 716 u32 vector_flags; 717 int channel_number; 718 719 int ring_size; 720 size_t ring_allocation_size; 721 struct lan743x_rx_descriptor *ring_cpu_ptr; 722 dma_addr_t ring_dma_ptr; 723 724 struct lan743x_rx_buffer_info *buffer_info; 725 726 __le32 *head_cpu_ptr; 727 dma_addr_t head_dma_ptr; 728 u32 last_head; 729 u32 last_tail; 730 731 struct napi_struct napi; 732 733 u32 frame_count; 734 735 struct sk_buff *skb_head, *skb_tail; 736 }; 737 738 struct lan743x_adapter { 739 struct net_device *netdev; 740 struct mii_bus *mdiobus; 741 int msg_enable; 742 #ifdef CONFIG_PM 743 u32 wolopts; 744 #endif 745 struct pci_dev *pdev; 746 struct lan743x_csr csr; 747 struct lan743x_intr intr; 748 749 struct lan743x_gpio gpio; 750 struct lan743x_ptp ptp; 751 752 u8 mac_address[ETH_ALEN]; 753 754 struct lan743x_phy phy; 755 struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS]; 756 struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; 757 bool is_pci11x1x; 758 bool is_sgmii_en; 759 u8 max_tx_channels; 760 u8 used_tx_channels; 761 u8 max_vector_count; 762 763 #define LAN743X_ADAPTER_FLAG_OTP BIT(0) 764 u32 flags; 765 }; 766 767 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 768 769 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 770 #define INTR_FLAG_MSI_ENABLED BIT(8) 771 #define INTR_FLAG_MSIX_ENABLED BIT(9) 772 773 #define MAC_MII_READ 1 774 #define MAC_MII_WRITE 0 775 776 #define PHY_FLAG_OPENED BIT(0) 777 #define PHY_FLAG_ATTACHED BIT(1) 778 779 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 780 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 781 #else 782 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 783 #endif 784 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 785 #define DMA_DESCRIPTOR_SPACING_16 (16) 786 #define DMA_DESCRIPTOR_SPACING_32 (32) 787 #define DMA_DESCRIPTOR_SPACING_64 (64) 788 #define DMA_DESCRIPTOR_SPACING_128 (128) 789 #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 790 791 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 792 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 793 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 794 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 795 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 796 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 797 798 /* TX Descriptor bits */ 799 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 800 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 801 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 802 #define TX_DESC_DATA0_FS_ (0x20000000) 803 #define TX_DESC_DATA0_LS_ (0x10000000) 804 #define TX_DESC_DATA0_EXT_ (0x08000000) 805 #define TX_DESC_DATA0_IOC_ (0x04000000) 806 #define TX_DESC_DATA0_ICE_ (0x00400000) 807 #define TX_DESC_DATA0_IPE_ (0x00200000) 808 #define TX_DESC_DATA0_TPE_ (0x00100000) 809 #define TX_DESC_DATA0_FCS_ (0x00020000) 810 #define TX_DESC_DATA0_TSE_ (0x00010000) 811 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 812 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 813 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 814 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 815 816 struct lan743x_tx_descriptor { 817 __le32 data0; 818 __le32 data1; 819 __le32 data2; 820 __le32 data3; 821 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 822 823 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 824 #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 825 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 826 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 827 struct lan743x_tx_buffer_info { 828 int flags; 829 struct sk_buff *skb; 830 dma_addr_t dma_ptr; 831 unsigned int buffer_length; 832 }; 833 834 #define LAN743X_TX_RING_SIZE (50) 835 836 /* OWN bit is set. ie, Descs are owned by RX DMAC */ 837 #define RX_DESC_DATA0_OWN_ (0x00008000) 838 /* OWN bit is clear. ie, Descs are owned by host */ 839 #define RX_DESC_DATA0_FS_ (0x80000000) 840 #define RX_DESC_DATA0_LS_ (0x40000000) 841 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 842 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 843 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 844 #define RX_DESC_DATA0_EXT_ (0x00004000) 845 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 846 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 847 848 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 849 #error NET_IP_ALIGN must be 0 or 2 850 #endif 851 852 #define RX_HEAD_PADDING NET_IP_ALIGN 853 854 struct lan743x_rx_descriptor { 855 __le32 data0; 856 __le32 data1; 857 __le32 data2; 858 __le32 data3; 859 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 860 861 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 862 struct lan743x_rx_buffer_info { 863 int flags; 864 struct sk_buff *skb; 865 866 dma_addr_t dma_ptr; 867 unsigned int buffer_length; 868 }; 869 870 #define LAN743X_RX_RING_SIZE (128) 871 872 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 873 #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) 874 875 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 876 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 877 878 #endif /* _LAN743X_H */ 879