1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2018 Microchip Technology Inc. */ 3 4 #ifndef _LAN743X_H 5 #define _LAN743X_H 6 7 #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 8 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 9 #define DRIVER_NAME "lan743x" 10 11 /* Register Definitions */ 12 #define ID_REV (0x00) 13 #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 14 (((id_rev) & 0xFFF00000) == 0x74300000) 15 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 16 #define ID_REV_CHIP_REV_A0_ (0x00000000) 17 #define ID_REV_CHIP_REV_B0_ (0x00000010) 18 19 #define FPGA_REV (0x04) 20 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 21 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 22 23 #define HW_CFG (0x010) 24 #define HW_CFG_LRST_ BIT(1) 25 26 #define PMT_CTL (0x014) 27 #define PMT_CTL_READY_ BIT(7) 28 #define PMT_CTL_ETH_PHY_RST_ BIT(4) 29 30 #define DP_SEL (0x024) 31 #define DP_SEL_DPRDY_ BIT(31) 32 #define DP_SEL_MASK_ (0x0000001F) 33 #define DP_SEL_RFE_RAM (0x00000001) 34 35 #define DP_SEL_VHF_HASH_LEN (16) 36 #define DP_SEL_VHF_VLAN_LEN (128) 37 38 #define DP_CMD (0x028) 39 #define DP_CMD_WRITE_ (0x00000001) 40 41 #define DP_ADDR (0x02C) 42 43 #define DP_DATA_0 (0x030) 44 45 #define E2P_CMD (0x040) 46 #define E2P_CMD_EPC_BUSY_ BIT(31) 47 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 48 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 49 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 50 #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 51 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 52 53 #define E2P_DATA (0x044) 54 55 #define FCT_RX_CTL (0xAC) 56 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 57 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 58 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 59 60 #define FCT_TX_CTL (0xC4) 61 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 62 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 63 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 64 65 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 66 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 67 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 68 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 69 #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 70 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 71 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 72 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 73 74 #define MAC_CR (0x100) 75 #define MAC_CR_ADD_ BIT(12) 76 #define MAC_CR_ASD_ BIT(11) 77 #define MAC_CR_CNTR_RST_ BIT(5) 78 #define MAC_CR_RST_ BIT(0) 79 80 #define MAC_RX (0x104) 81 #define MAC_RX_MAX_SIZE_SHIFT_ (16) 82 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 83 #define MAC_RX_RXD_ BIT(1) 84 #define MAC_RX_RXEN_ BIT(0) 85 86 #define MAC_TX (0x108) 87 #define MAC_TX_TXD_ BIT(1) 88 #define MAC_TX_TXEN_ BIT(0) 89 90 #define MAC_FLOW (0x10C) 91 #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 92 #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 93 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 94 95 #define MAC_RX_ADDRH (0x118) 96 97 #define MAC_RX_ADDRL (0x11C) 98 99 #define MAC_MII_ACC (0x120) 100 #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 101 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 102 #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 103 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 104 #define MAC_MII_ACC_MII_READ_ (0x00000000) 105 #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 106 #define MAC_MII_ACC_MII_BUSY_ BIT(0) 107 108 #define MAC_MII_DATA (0x124) 109 110 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 111 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 112 #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 113 114 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 115 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 116 117 #define RFE_CTL (0x508) 118 #define RFE_CTL_AB_ BIT(10) 119 #define RFE_CTL_AM_ BIT(9) 120 #define RFE_CTL_AU_ BIT(8) 121 #define RFE_CTL_MCAST_HASH_ BIT(3) 122 #define RFE_CTL_DA_PERFECT_ BIT(1) 123 124 #define INT_STS (0x780) 125 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 126 #define INT_BIT_ALL_RX_ (0x0F000000) 127 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 128 #define INT_BIT_ALL_TX_ (0x000F0000) 129 #define INT_BIT_SW_GP_ BIT(9) 130 #define INT_BIT_ALL_OTHER_ (0x00000280) 131 #define INT_BIT_MAS_ BIT(0) 132 133 #define INT_SET (0x784) 134 135 #define INT_EN_SET (0x788) 136 137 #define INT_EN_CLR (0x78C) 138 139 #define INT_STS_R2C (0x790) 140 141 #define INT_VEC_EN_SET (0x794) 142 #define INT_VEC_EN_CLR (0x798) 143 #define INT_VEC_EN_AUTO_CLR (0x79C) 144 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 145 146 #define INT_VEC_MAP0 (0x7A0) 147 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 148 (((u32)(vector)) << ((channel) << 2)) 149 150 #define INT_VEC_MAP1 (0x7A4) 151 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 152 (((u32)(vector)) << ((channel) << 2)) 153 154 #define INT_VEC_MAP2 (0x7A8) 155 156 #define INT_MOD_MAP0 (0x7B0) 157 158 #define INT_MOD_MAP1 (0x7B4) 159 160 #define INT_MOD_MAP2 (0x7B8) 161 162 #define INT_MOD_CFG0 (0x7C0) 163 #define INT_MOD_CFG1 (0x7C4) 164 #define INT_MOD_CFG2 (0x7C8) 165 #define INT_MOD_CFG3 (0x7CC) 166 #define INT_MOD_CFG4 (0x7D0) 167 #define INT_MOD_CFG5 (0x7D4) 168 #define INT_MOD_CFG6 (0x7D8) 169 #define INT_MOD_CFG7 (0x7DC) 170 171 #define DMAC_CFG (0xC00) 172 #define DMAC_CFG_COAL_EN_ BIT(16) 173 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 174 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 175 #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 176 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 177 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 178 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 179 #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 180 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 181 182 #define DMAC_COAL_CFG (0xC04) 183 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 184 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 185 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 186 #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 187 #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 188 #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 189 #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 190 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 191 #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 192 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 193 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 194 #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 195 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 196 197 #define DMAC_OBFF_CFG (0xC08) 198 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 199 #define DMAC_OBFF_TX_THRES_SET_(val) \ 200 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 201 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 202 #define DMAC_OBFF_RX_THRES_SET_(val) \ 203 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 204 205 #define DMAC_CMD (0xC0C) 206 #define DMAC_CMD_SWR_ BIT(31) 207 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 208 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 209 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 210 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 211 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 212 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 213 214 #define DMAC_INT_STS (0xC10) 215 #define DMAC_INT_EN_SET (0xC14) 216 #define DMAC_INT_EN_CLR (0xC18) 217 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 218 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 219 220 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 221 #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 222 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 223 #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 224 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 225 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 226 #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 227 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 228 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 229 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 230 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 231 #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 232 233 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 234 #define RX_CFG_B_TS_ALL_RX_ BIT(29) 235 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 236 #define RX_CFG_B_RX_PAD_0_ (0x00000000) 237 #define RX_CFG_B_RX_PAD_2_ (0x02000000) 238 #define RX_CFG_B_RDMABL_512_ (0x00040000) 239 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 240 241 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 242 243 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 244 245 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 246 247 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 248 249 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 250 251 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 252 #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 253 #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 254 255 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 256 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 257 #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 258 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 259 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 260 261 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 262 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 263 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 264 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 265 #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 266 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 267 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 268 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 269 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 270 #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 271 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 272 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 273 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 274 275 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 276 #define TX_CFG_B_TDMABL_512_ (0x00040000) 277 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 278 279 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 280 281 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 282 283 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 284 285 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 286 287 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 288 289 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 290 #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 291 #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 292 #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 293 294 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 295 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 296 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 297 #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 298 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 299 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 300 301 #define OTP_PWR_DN (0x1000) 302 #define OTP_PWR_DN_PWRDN_N_ BIT(0) 303 304 #define OTP_ADDR1 (0x1004) 305 #define OTP_ADDR1_15_11_MASK_ (0x1F) 306 307 #define OTP_ADDR2 (0x1008) 308 #define OTP_ADDR2_10_3_MASK_ (0xFF) 309 310 #define OTP_PRGM_DATA (0x1010) 311 312 #define OTP_PRGM_MODE (0x1014) 313 #define OTP_PRGM_MODE_BYTE_ BIT(0) 314 315 #define OTP_TST_CMD (0x1024) 316 #define OTP_TST_CMD_PRGVRFY_ BIT(3) 317 318 #define OTP_CMD_GO (0x1028) 319 #define OTP_CMD_GO_GO_ BIT(0) 320 321 #define OTP_STATUS (0x1030) 322 #define OTP_STATUS_BUSY_ BIT(0) 323 324 /* MAC statistics registers */ 325 #define STAT_RX_FCS_ERRORS (0x1200) 326 #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 327 #define STAT_RX_FRAGMENT_ERRORS (0x1208) 328 #define STAT_RX_JABBER_ERRORS (0x120C) 329 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 330 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 331 #define STAT_RX_DROPPED_FRAMES (0x1218) 332 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 333 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 334 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 335 #define STAT_RX_UNICAST_FRAMES (0x1228) 336 #define STAT_RX_BROADCAST_FRAMES (0x122C) 337 #define STAT_RX_MULTICAST_FRAMES (0x1230) 338 #define STAT_RX_PAUSE_FRAMES (0x1234) 339 #define STAT_RX_64_BYTE_FRAMES (0x1238) 340 #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 341 #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 342 #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 343 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 344 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 345 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 346 #define STAT_RX_TOTAL_FRAMES (0x1254) 347 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 348 #define STAT_EEE_RX_LPI_TIME (0x125C) 349 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 350 351 #define STAT_TX_FCS_ERRORS (0x1280) 352 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 353 #define STAT_TX_CARRIER_ERRORS (0x1288) 354 #define STAT_TX_BAD_BYTE_COUNT (0x128C) 355 #define STAT_TX_SINGLE_COLLISIONS (0x1290) 356 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 357 #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 358 #define STAT_TX_LATE_COLLISIONS (0x129C) 359 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 360 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 361 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 362 #define STAT_TX_UNICAST_FRAMES (0x12AC) 363 #define STAT_TX_BROADCAST_FRAMES (0x12B0) 364 #define STAT_TX_MULTICAST_FRAMES (0x12B4) 365 #define STAT_TX_PAUSE_FRAMES (0x12B8) 366 #define STAT_TX_64_BYTE_FRAMES (0x12BC) 367 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 368 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 369 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 370 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 371 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 372 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 373 #define STAT_TX_TOTAL_FRAMES (0x12D8) 374 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 375 #define STAT_EEE_TX_LPI_TIME (0x12E0) 376 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 377 378 /* End of Register definitions */ 379 380 #define LAN743X_MAX_RX_CHANNELS (4) 381 #define LAN743X_MAX_TX_CHANNELS (1) 382 struct lan743x_adapter; 383 384 #define LAN743X_USED_RX_CHANNELS (4) 385 #define LAN743X_USED_TX_CHANNELS (1) 386 #define LAN743X_INT_MOD (400) 387 388 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 389 #error Invalid LAN743X_USED_RX_CHANNELS 390 #endif 391 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 392 #error Invalid LAN743X_USED_TX_CHANNELS 393 #endif 394 395 /* PCI */ 396 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 397 #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 398 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 399 400 #define PCI_CONFIG_LENGTH (0x1000) 401 402 /* CSR */ 403 #define CSR_LENGTH (0x2000) 404 405 #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 406 #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 407 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 408 409 struct lan743x_csr { 410 u32 flags; 411 u8 __iomem *csr_address; 412 u32 id_rev; 413 u32 fpga_rev; 414 }; 415 416 /* INTERRUPTS */ 417 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 418 419 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 420 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 421 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 422 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 423 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 424 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 425 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 426 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 427 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 428 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 429 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 430 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 431 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 432 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 433 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 434 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 435 436 struct lan743x_vector { 437 int irq; 438 u32 flags; 439 struct lan743x_adapter *adapter; 440 int vector_index; 441 u32 int_mask; 442 lan743x_vector_handler handler; 443 void *context; 444 }; 445 446 #define LAN743X_MAX_VECTOR_COUNT (8) 447 448 struct lan743x_intr { 449 int flags; 450 451 unsigned int irq; 452 453 struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT]; 454 int number_of_vectors; 455 bool using_vectors; 456 457 int software_isr_flag; 458 }; 459 460 #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 461 462 /* PHY */ 463 struct lan743x_phy { 464 bool fc_autoneg; 465 u8 fc_request_control; 466 }; 467 468 /* TX */ 469 struct lan743x_tx_descriptor; 470 struct lan743x_tx_buffer_info; 471 472 #define GPIO_QUEUE_STARTED (0) 473 #define GPIO_TX_FUNCTION (1) 474 #define GPIO_TX_COMPLETION (2) 475 #define GPIO_TX_FRAGMENT (3) 476 477 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 478 479 struct lan743x_tx { 480 struct lan743x_adapter *adapter; 481 u32 vector_flags; 482 int channel_number; 483 484 int ring_size; 485 size_t ring_allocation_size; 486 struct lan743x_tx_descriptor *ring_cpu_ptr; 487 dma_addr_t ring_dma_ptr; 488 /* ring_lock: used to prevent concurrent access to tx ring */ 489 spinlock_t ring_lock; 490 u32 frame_flags; 491 u32 frame_first; 492 u32 frame_data0; 493 u32 frame_tail; 494 495 struct lan743x_tx_buffer_info *buffer_info; 496 497 u32 *head_cpu_ptr; 498 dma_addr_t head_dma_ptr; 499 int last_head; 500 int last_tail; 501 502 struct napi_struct napi; 503 504 struct sk_buff *overflow_skb; 505 }; 506 507 /* RX */ 508 struct lan743x_rx_descriptor; 509 struct lan743x_rx_buffer_info; 510 511 struct lan743x_rx { 512 struct lan743x_adapter *adapter; 513 u32 vector_flags; 514 int channel_number; 515 516 int ring_size; 517 size_t ring_allocation_size; 518 struct lan743x_rx_descriptor *ring_cpu_ptr; 519 dma_addr_t ring_dma_ptr; 520 521 struct lan743x_rx_buffer_info *buffer_info; 522 523 u32 *head_cpu_ptr; 524 dma_addr_t head_dma_ptr; 525 u32 last_head; 526 u32 last_tail; 527 528 struct napi_struct napi; 529 530 u32 frame_count; 531 }; 532 533 struct lan743x_adapter { 534 struct net_device *netdev; 535 struct mii_bus *mdiobus; 536 int msg_enable; 537 struct pci_dev *pdev; 538 struct lan743x_csr csr; 539 struct lan743x_intr intr; 540 541 /* lock, used to prevent concurrent access to data port */ 542 struct mutex dp_lock; 543 544 u8 mac_address[ETH_ALEN]; 545 546 struct lan743x_phy phy; 547 struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS]; 548 struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS]; 549 }; 550 551 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 552 553 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 554 #define INTR_FLAG_MSI_ENABLED BIT(8) 555 #define INTR_FLAG_MSIX_ENABLED BIT(9) 556 557 #define MAC_MII_READ 1 558 #define MAC_MII_WRITE 0 559 560 #define PHY_FLAG_OPENED BIT(0) 561 #define PHY_FLAG_ATTACHED BIT(1) 562 563 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 564 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 565 #else 566 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 567 #endif 568 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 569 #define DMA_DESCRIPTOR_SPACING_16 (16) 570 #define DMA_DESCRIPTOR_SPACING_32 (32) 571 #define DMA_DESCRIPTOR_SPACING_64 (64) 572 #define DMA_DESCRIPTOR_SPACING_128 (128) 573 #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 574 575 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 576 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 577 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 578 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 579 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 580 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 581 582 /* TX Descriptor bits */ 583 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 584 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 585 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 586 #define TX_DESC_DATA0_FS_ (0x20000000) 587 #define TX_DESC_DATA0_LS_ (0x10000000) 588 #define TX_DESC_DATA0_EXT_ (0x08000000) 589 #define TX_DESC_DATA0_IOC_ (0x04000000) 590 #define TX_DESC_DATA0_ICE_ (0x00400000) 591 #define TX_DESC_DATA0_IPE_ (0x00200000) 592 #define TX_DESC_DATA0_TPE_ (0x00100000) 593 #define TX_DESC_DATA0_FCS_ (0x00020000) 594 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 595 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 596 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 597 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 598 599 struct lan743x_tx_descriptor { 600 u32 data0; 601 u32 data1; 602 u32 data2; 603 u32 data3; 604 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 605 606 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 607 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 608 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 609 struct lan743x_tx_buffer_info { 610 int flags; 611 struct sk_buff *skb; 612 dma_addr_t dma_ptr; 613 unsigned int buffer_length; 614 }; 615 616 #define LAN743X_TX_RING_SIZE (50) 617 618 /* OWN bit is set. ie, Descs are owned by RX DMAC */ 619 #define RX_DESC_DATA0_OWN_ (0x00008000) 620 /* OWN bit is clear. ie, Descs are owned by host */ 621 #define RX_DESC_DATA0_FS_ (0x80000000) 622 #define RX_DESC_DATA0_LS_ (0x40000000) 623 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 624 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 625 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 626 #define RX_DESC_DATA0_EXT_ (0x00004000) 627 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 628 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 629 630 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 631 #error NET_IP_ALIGN must be 0 or 2 632 #endif 633 634 #define RX_HEAD_PADDING NET_IP_ALIGN 635 636 struct lan743x_rx_descriptor { 637 u32 data0; 638 u32 data1; 639 u32 data2; 640 u32 data3; 641 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 642 643 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 644 struct lan743x_rx_buffer_info { 645 int flags; 646 struct sk_buff *skb; 647 648 dma_addr_t dma_ptr; 649 unsigned int buffer_length; 650 }; 651 652 #define LAN743X_RX_RING_SIZE (65) 653 654 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 655 #define RX_PROCESS_RESULT_PACKET_RECEIVED (1) 656 #define RX_PROCESS_RESULT_PACKET_DROPPED (2) 657 658 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 659 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 660 661 #endif /* _LAN743X_H */ 662