1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (C) 2018 Microchip Technology Inc. */ 3 4 #ifndef _LAN743X_H 5 #define _LAN743X_H 6 7 #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 8 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 9 #define DRIVER_NAME "lan743x" 10 11 /* Register Definitions */ 12 #define ID_REV (0x00) 13 #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 14 (((id_rev) & 0xFFF00000) == 0x74300000) 15 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 16 #define ID_REV_CHIP_REV_A0_ (0x00000000) 17 #define ID_REV_CHIP_REV_B0_ (0x00000010) 18 19 #define FPGA_REV (0x04) 20 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 21 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 22 23 #define HW_CFG (0x010) 24 #define HW_CFG_LRST_ BIT(1) 25 26 #define PMT_CTL (0x014) 27 #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 28 #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 29 #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 30 #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 31 #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 32 #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 33 #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 34 #define PMT_CTL_READY_ BIT(7) 35 #define PMT_CTL_ETH_PHY_RST_ BIT(4) 36 #define PMT_CTL_WOL_EN_ BIT(3) 37 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 38 #define PMT_CTL_WUPS_MASK_ (0x00000003) 39 40 #define DP_SEL (0x024) 41 #define DP_SEL_DPRDY_ BIT(31) 42 #define DP_SEL_MASK_ (0x0000001F) 43 #define DP_SEL_RFE_RAM (0x00000001) 44 45 #define DP_SEL_VHF_HASH_LEN (16) 46 #define DP_SEL_VHF_VLAN_LEN (128) 47 48 #define DP_CMD (0x028) 49 #define DP_CMD_WRITE_ (0x00000001) 50 51 #define DP_ADDR (0x02C) 52 53 #define DP_DATA_0 (0x030) 54 55 #define E2P_CMD (0x040) 56 #define E2P_CMD_EPC_BUSY_ BIT(31) 57 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 58 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 59 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 60 #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 61 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 62 63 #define E2P_DATA (0x044) 64 65 #define FCT_RX_CTL (0xAC) 66 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 67 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 68 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 69 70 #define FCT_TX_CTL (0xC4) 71 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 72 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 73 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 74 75 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 76 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 77 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 78 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 79 #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 80 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 81 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 82 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 83 84 #define MAC_CR (0x100) 85 #define MAC_CR_ADD_ BIT(12) 86 #define MAC_CR_ASD_ BIT(11) 87 #define MAC_CR_CNTR_RST_ BIT(5) 88 #define MAC_CR_RST_ BIT(0) 89 90 #define MAC_RX (0x104) 91 #define MAC_RX_MAX_SIZE_SHIFT_ (16) 92 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 93 #define MAC_RX_RXD_ BIT(1) 94 #define MAC_RX_RXEN_ BIT(0) 95 96 #define MAC_TX (0x108) 97 #define MAC_TX_TXD_ BIT(1) 98 #define MAC_TX_TXEN_ BIT(0) 99 100 #define MAC_FLOW (0x10C) 101 #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 102 #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 103 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 104 105 #define MAC_RX_ADDRH (0x118) 106 107 #define MAC_RX_ADDRL (0x11C) 108 109 #define MAC_MII_ACC (0x120) 110 #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 111 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 112 #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 113 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 114 #define MAC_MII_ACC_MII_READ_ (0x00000000) 115 #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 116 #define MAC_MII_ACC_MII_BUSY_ BIT(0) 117 118 #define MAC_MII_DATA (0x124) 119 120 #define MAC_WUCSR (0x140) 121 #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 122 #define MAC_WUCSR_PFDA_EN_ BIT(3) 123 #define MAC_WUCSR_WAKE_EN_ BIT(2) 124 #define MAC_WUCSR_MPEN_ BIT(1) 125 #define MAC_WUCSR_BCST_EN_ BIT(0) 126 127 #define MAC_WK_SRC (0x144) 128 129 #define MAC_WUF_CFG0 (0x150) 130 #define MAC_NUM_OF_WUF_CFG (32) 131 #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 132 #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 133 #define MAC_WUF_CFG_EN_ BIT(31) 134 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 135 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 136 #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 137 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 138 139 #define MAC_WUF_MASK0_0 (0x200) 140 #define MAC_WUF_MASK0_1 (0x204) 141 #define MAC_WUF_MASK0_2 (0x208) 142 #define MAC_WUF_MASK0_3 (0x20C) 143 #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 144 #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 145 #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 146 #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 147 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 148 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 149 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 150 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 151 152 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 153 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 154 #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 155 156 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 157 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 158 159 #define RFE_CTL (0x508) 160 #define RFE_CTL_AB_ BIT(10) 161 #define RFE_CTL_AM_ BIT(9) 162 #define RFE_CTL_AU_ BIT(8) 163 #define RFE_CTL_MCAST_HASH_ BIT(3) 164 #define RFE_CTL_DA_PERFECT_ BIT(1) 165 166 #define MAC_WUCSR2 (0x600) 167 168 #define INT_STS (0x780) 169 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 170 #define INT_BIT_ALL_RX_ (0x0F000000) 171 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 172 #define INT_BIT_ALL_TX_ (0x000F0000) 173 #define INT_BIT_SW_GP_ BIT(9) 174 #define INT_BIT_ALL_OTHER_ (0x00000280) 175 #define INT_BIT_MAS_ BIT(0) 176 177 #define INT_SET (0x784) 178 179 #define INT_EN_SET (0x788) 180 181 #define INT_EN_CLR (0x78C) 182 183 #define INT_STS_R2C (0x790) 184 185 #define INT_VEC_EN_SET (0x794) 186 #define INT_VEC_EN_CLR (0x798) 187 #define INT_VEC_EN_AUTO_CLR (0x79C) 188 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 189 190 #define INT_VEC_MAP0 (0x7A0) 191 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 192 (((u32)(vector)) << ((channel) << 2)) 193 194 #define INT_VEC_MAP1 (0x7A4) 195 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 196 (((u32)(vector)) << ((channel) << 2)) 197 198 #define INT_VEC_MAP2 (0x7A8) 199 200 #define INT_MOD_MAP0 (0x7B0) 201 202 #define INT_MOD_MAP1 (0x7B4) 203 204 #define INT_MOD_MAP2 (0x7B8) 205 206 #define INT_MOD_CFG0 (0x7C0) 207 #define INT_MOD_CFG1 (0x7C4) 208 #define INT_MOD_CFG2 (0x7C8) 209 #define INT_MOD_CFG3 (0x7CC) 210 #define INT_MOD_CFG4 (0x7D0) 211 #define INT_MOD_CFG5 (0x7D4) 212 #define INT_MOD_CFG6 (0x7D8) 213 #define INT_MOD_CFG7 (0x7DC) 214 215 #define DMAC_CFG (0xC00) 216 #define DMAC_CFG_COAL_EN_ BIT(16) 217 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 218 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 219 #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 220 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 221 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 222 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 223 #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 224 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 225 226 #define DMAC_COAL_CFG (0xC04) 227 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 228 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 229 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 230 #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 231 #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 232 #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 233 #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 234 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 235 #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 236 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 237 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 238 #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 239 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 240 241 #define DMAC_OBFF_CFG (0xC08) 242 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 243 #define DMAC_OBFF_TX_THRES_SET_(val) \ 244 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 245 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 246 #define DMAC_OBFF_RX_THRES_SET_(val) \ 247 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 248 249 #define DMAC_CMD (0xC0C) 250 #define DMAC_CMD_SWR_ BIT(31) 251 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 252 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 253 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 254 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 255 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 256 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 257 258 #define DMAC_INT_STS (0xC10) 259 #define DMAC_INT_EN_SET (0xC14) 260 #define DMAC_INT_EN_CLR (0xC18) 261 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 262 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 263 264 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 265 #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 266 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 267 #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 268 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 269 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 270 #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 271 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 272 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 273 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 274 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 275 #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 276 277 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 278 #define RX_CFG_B_TS_ALL_RX_ BIT(29) 279 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 280 #define RX_CFG_B_RX_PAD_0_ (0x00000000) 281 #define RX_CFG_B_RX_PAD_2_ (0x02000000) 282 #define RX_CFG_B_RDMABL_512_ (0x00040000) 283 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 284 285 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 286 287 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 288 289 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 290 291 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 292 293 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 294 295 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 296 #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 297 #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 298 299 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 300 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 301 #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 302 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 303 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 304 305 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 306 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 307 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 308 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 309 #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 310 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 311 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 312 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 313 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 314 #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 315 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 316 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 317 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 318 319 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 320 #define TX_CFG_B_TDMABL_512_ (0x00040000) 321 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 322 323 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 324 325 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 326 327 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 328 329 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 330 331 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 332 333 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 334 #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 335 #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 336 #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 337 338 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 339 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 340 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 341 #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 342 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 343 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 344 345 #define OTP_PWR_DN (0x1000) 346 #define OTP_PWR_DN_PWRDN_N_ BIT(0) 347 348 #define OTP_ADDR1 (0x1004) 349 #define OTP_ADDR1_15_11_MASK_ (0x1F) 350 351 #define OTP_ADDR2 (0x1008) 352 #define OTP_ADDR2_10_3_MASK_ (0xFF) 353 354 #define OTP_PRGM_DATA (0x1010) 355 356 #define OTP_PRGM_MODE (0x1014) 357 #define OTP_PRGM_MODE_BYTE_ BIT(0) 358 359 #define OTP_TST_CMD (0x1024) 360 #define OTP_TST_CMD_PRGVRFY_ BIT(3) 361 362 #define OTP_CMD_GO (0x1028) 363 #define OTP_CMD_GO_GO_ BIT(0) 364 365 #define OTP_STATUS (0x1030) 366 #define OTP_STATUS_BUSY_ BIT(0) 367 368 /* MAC statistics registers */ 369 #define STAT_RX_FCS_ERRORS (0x1200) 370 #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 371 #define STAT_RX_FRAGMENT_ERRORS (0x1208) 372 #define STAT_RX_JABBER_ERRORS (0x120C) 373 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 374 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 375 #define STAT_RX_DROPPED_FRAMES (0x1218) 376 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 377 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 378 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 379 #define STAT_RX_UNICAST_FRAMES (0x1228) 380 #define STAT_RX_BROADCAST_FRAMES (0x122C) 381 #define STAT_RX_MULTICAST_FRAMES (0x1230) 382 #define STAT_RX_PAUSE_FRAMES (0x1234) 383 #define STAT_RX_64_BYTE_FRAMES (0x1238) 384 #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 385 #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 386 #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 387 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 388 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 389 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 390 #define STAT_RX_TOTAL_FRAMES (0x1254) 391 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 392 #define STAT_EEE_RX_LPI_TIME (0x125C) 393 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 394 395 #define STAT_TX_FCS_ERRORS (0x1280) 396 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 397 #define STAT_TX_CARRIER_ERRORS (0x1288) 398 #define STAT_TX_BAD_BYTE_COUNT (0x128C) 399 #define STAT_TX_SINGLE_COLLISIONS (0x1290) 400 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 401 #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 402 #define STAT_TX_LATE_COLLISIONS (0x129C) 403 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 404 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 405 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 406 #define STAT_TX_UNICAST_FRAMES (0x12AC) 407 #define STAT_TX_BROADCAST_FRAMES (0x12B0) 408 #define STAT_TX_MULTICAST_FRAMES (0x12B4) 409 #define STAT_TX_PAUSE_FRAMES (0x12B8) 410 #define STAT_TX_64_BYTE_FRAMES (0x12BC) 411 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 412 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 413 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 414 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 415 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 416 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 417 #define STAT_TX_TOTAL_FRAMES (0x12D8) 418 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 419 #define STAT_EEE_TX_LPI_TIME (0x12E0) 420 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 421 422 /* End of Register definitions */ 423 424 #define LAN743X_MAX_RX_CHANNELS (4) 425 #define LAN743X_MAX_TX_CHANNELS (1) 426 struct lan743x_adapter; 427 428 #define LAN743X_USED_RX_CHANNELS (4) 429 #define LAN743X_USED_TX_CHANNELS (1) 430 #define LAN743X_INT_MOD (400) 431 432 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 433 #error Invalid LAN743X_USED_RX_CHANNELS 434 #endif 435 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 436 #error Invalid LAN743X_USED_TX_CHANNELS 437 #endif 438 439 /* PCI */ 440 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 441 #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 442 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 443 444 #define PCI_CONFIG_LENGTH (0x1000) 445 446 /* CSR */ 447 #define CSR_LENGTH (0x2000) 448 449 #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 450 #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 451 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 452 453 struct lan743x_csr { 454 u32 flags; 455 u8 __iomem *csr_address; 456 u32 id_rev; 457 u32 fpga_rev; 458 }; 459 460 /* INTERRUPTS */ 461 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 462 463 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 464 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 465 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 466 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 467 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 468 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 469 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 470 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 471 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 472 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 473 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 474 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 475 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 476 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 477 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 478 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 479 480 struct lan743x_vector { 481 int irq; 482 u32 flags; 483 struct lan743x_adapter *adapter; 484 int vector_index; 485 u32 int_mask; 486 lan743x_vector_handler handler; 487 void *context; 488 }; 489 490 #define LAN743X_MAX_VECTOR_COUNT (8) 491 492 struct lan743x_intr { 493 int flags; 494 495 unsigned int irq; 496 497 struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT]; 498 int number_of_vectors; 499 bool using_vectors; 500 501 int software_isr_flag; 502 }; 503 504 #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 505 506 /* PHY */ 507 struct lan743x_phy { 508 bool fc_autoneg; 509 u8 fc_request_control; 510 }; 511 512 /* TX */ 513 struct lan743x_tx_descriptor; 514 struct lan743x_tx_buffer_info; 515 516 #define GPIO_QUEUE_STARTED (0) 517 #define GPIO_TX_FUNCTION (1) 518 #define GPIO_TX_COMPLETION (2) 519 #define GPIO_TX_FRAGMENT (3) 520 521 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 522 523 struct lan743x_tx { 524 struct lan743x_adapter *adapter; 525 u32 vector_flags; 526 int channel_number; 527 528 int ring_size; 529 size_t ring_allocation_size; 530 struct lan743x_tx_descriptor *ring_cpu_ptr; 531 dma_addr_t ring_dma_ptr; 532 /* ring_lock: used to prevent concurrent access to tx ring */ 533 spinlock_t ring_lock; 534 u32 frame_flags; 535 u32 frame_first; 536 u32 frame_data0; 537 u32 frame_tail; 538 539 struct lan743x_tx_buffer_info *buffer_info; 540 541 u32 *head_cpu_ptr; 542 dma_addr_t head_dma_ptr; 543 int last_head; 544 int last_tail; 545 546 struct napi_struct napi; 547 548 struct sk_buff *overflow_skb; 549 }; 550 551 /* RX */ 552 struct lan743x_rx_descriptor; 553 struct lan743x_rx_buffer_info; 554 555 struct lan743x_rx { 556 struct lan743x_adapter *adapter; 557 u32 vector_flags; 558 int channel_number; 559 560 int ring_size; 561 size_t ring_allocation_size; 562 struct lan743x_rx_descriptor *ring_cpu_ptr; 563 dma_addr_t ring_dma_ptr; 564 565 struct lan743x_rx_buffer_info *buffer_info; 566 567 u32 *head_cpu_ptr; 568 dma_addr_t head_dma_ptr; 569 u32 last_head; 570 u32 last_tail; 571 572 struct napi_struct napi; 573 574 u32 frame_count; 575 }; 576 577 struct lan743x_adapter { 578 struct net_device *netdev; 579 struct mii_bus *mdiobus; 580 int msg_enable; 581 #ifdef CONFIG_PM 582 u32 wolopts; 583 #endif 584 struct pci_dev *pdev; 585 struct lan743x_csr csr; 586 struct lan743x_intr intr; 587 588 /* lock, used to prevent concurrent access to data port */ 589 struct mutex dp_lock; 590 591 u8 mac_address[ETH_ALEN]; 592 593 struct lan743x_phy phy; 594 struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS]; 595 struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS]; 596 }; 597 598 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 599 600 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 601 #define INTR_FLAG_MSI_ENABLED BIT(8) 602 #define INTR_FLAG_MSIX_ENABLED BIT(9) 603 604 #define MAC_MII_READ 1 605 #define MAC_MII_WRITE 0 606 607 #define PHY_FLAG_OPENED BIT(0) 608 #define PHY_FLAG_ATTACHED BIT(1) 609 610 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 611 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 612 #else 613 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 614 #endif 615 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 616 #define DMA_DESCRIPTOR_SPACING_16 (16) 617 #define DMA_DESCRIPTOR_SPACING_32 (32) 618 #define DMA_DESCRIPTOR_SPACING_64 (64) 619 #define DMA_DESCRIPTOR_SPACING_128 (128) 620 #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 621 622 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 623 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 624 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 625 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 626 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 627 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 628 629 /* TX Descriptor bits */ 630 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 631 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 632 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 633 #define TX_DESC_DATA0_FS_ (0x20000000) 634 #define TX_DESC_DATA0_LS_ (0x10000000) 635 #define TX_DESC_DATA0_EXT_ (0x08000000) 636 #define TX_DESC_DATA0_IOC_ (0x04000000) 637 #define TX_DESC_DATA0_ICE_ (0x00400000) 638 #define TX_DESC_DATA0_IPE_ (0x00200000) 639 #define TX_DESC_DATA0_TPE_ (0x00100000) 640 #define TX_DESC_DATA0_FCS_ (0x00020000) 641 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 642 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 643 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 644 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 645 646 struct lan743x_tx_descriptor { 647 u32 data0; 648 u32 data1; 649 u32 data2; 650 u32 data3; 651 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 652 653 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 654 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 655 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 656 struct lan743x_tx_buffer_info { 657 int flags; 658 struct sk_buff *skb; 659 dma_addr_t dma_ptr; 660 unsigned int buffer_length; 661 }; 662 663 #define LAN743X_TX_RING_SIZE (50) 664 665 /* OWN bit is set. ie, Descs are owned by RX DMAC */ 666 #define RX_DESC_DATA0_OWN_ (0x00008000) 667 /* OWN bit is clear. ie, Descs are owned by host */ 668 #define RX_DESC_DATA0_FS_ (0x80000000) 669 #define RX_DESC_DATA0_LS_ (0x40000000) 670 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 671 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 672 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 673 #define RX_DESC_DATA0_EXT_ (0x00004000) 674 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 675 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 676 677 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 678 #error NET_IP_ALIGN must be 0 or 2 679 #endif 680 681 #define RX_HEAD_PADDING NET_IP_ALIGN 682 683 struct lan743x_rx_descriptor { 684 u32 data0; 685 u32 data1; 686 u32 data2; 687 u32 data3; 688 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 689 690 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 691 struct lan743x_rx_buffer_info { 692 int flags; 693 struct sk_buff *skb; 694 695 dma_addr_t dma_ptr; 696 unsigned int buffer_length; 697 }; 698 699 #define LAN743X_RX_RING_SIZE (65) 700 701 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 702 #define RX_PROCESS_RESULT_PACKET_RECEIVED (1) 703 #define RX_PROCESS_RESULT_PACKET_DROPPED (2) 704 705 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 706 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 707 708 #endif /* _LAN743X_H */ 709