123f0703cSBryan Whitehead /* SPDX-License-Identifier: GPL-2.0+ */ 223f0703cSBryan Whitehead /* Copyright (C) 2018 Microchip Technology Inc. */ 323f0703cSBryan Whitehead 423f0703cSBryan Whitehead #ifndef _LAN743X_H 523f0703cSBryan Whitehead #define _LAN743X_H 623f0703cSBryan Whitehead 76f197fb6SRoelof Berg #include <linux/phy.h> 807624df1SBryan Whitehead #include "lan743x_ptp.h" 907624df1SBryan Whitehead 1023f0703cSBryan Whitehead #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 1123f0703cSBryan Whitehead #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 1223f0703cSBryan Whitehead #define DRIVER_NAME "lan743x" 1323f0703cSBryan Whitehead 1423f0703cSBryan Whitehead /* Register Definitions */ 1523f0703cSBryan Whitehead #define ID_REV (0x00) 1607624df1SBryan Whitehead #define ID_REV_ID_MASK_ (0xFFFF0000) 1707624df1SBryan Whitehead #define ID_REV_ID_LAN7430_ (0x74300000) 1807624df1SBryan Whitehead #define ID_REV_ID_LAN7431_ (0x74310000) 19bb4f6bffSRaju Lakkaraju #define ID_REV_ID_LAN743X_ (0x74300000) 20bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 21bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 22bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A0X1_ (0xA0010000) 2323f0703cSBryan Whitehead #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 24bb4f6bffSRaju Lakkaraju ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ 25bb4f6bffSRaju Lakkaraju (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) 2623f0703cSBryan Whitehead #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 2723f0703cSBryan Whitehead #define ID_REV_CHIP_REV_A0_ (0x00000000) 2823f0703cSBryan Whitehead #define ID_REV_CHIP_REV_B0_ (0x00000010) 2923f0703cSBryan Whitehead 3023f0703cSBryan Whitehead #define FPGA_REV (0x04) 3123f0703cSBryan Whitehead #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 3223f0703cSBryan Whitehead #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 33a46d9d37SRaju Lakkaraju #define FPGA_SGMII_OP BIT(24) 34a46d9d37SRaju Lakkaraju 35a46d9d37SRaju Lakkaraju #define STRAP_READ (0x0C) 36a46d9d37SRaju Lakkaraju #define STRAP_READ_USE_SGMII_EN_ BIT(22) 37a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_EN_ BIT(6) 38a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_REFCLK_ BIT(5) 39a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_2_5G_ BIT(4) 40a46d9d37SRaju Lakkaraju #define STRAP_READ_BASE_X_ BIT(3) 41a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2) 42a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1) 43a46d9d37SRaju Lakkaraju #define STRAP_READ_ADV_PM_DISABLE_ BIT(0) 4423f0703cSBryan Whitehead 4523f0703cSBryan Whitehead #define HW_CFG (0x010) 46662a14d0SBryan Whitehead #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) 47662a14d0SBryan Whitehead #define HW_CFG_EE_OTP_RELOAD_ BIT(4) 4823f0703cSBryan Whitehead #define HW_CFG_LRST_ BIT(1) 4923f0703cSBryan Whitehead 5023f0703cSBryan Whitehead #define PMT_CTL (0x014) 514d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 524d94282aSBryan Whitehead #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 534d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 544d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 554d94282aSBryan Whitehead #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 564d94282aSBryan Whitehead #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 574d94282aSBryan Whitehead #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 5823f0703cSBryan Whitehead #define PMT_CTL_READY_ BIT(7) 5923f0703cSBryan Whitehead #define PMT_CTL_ETH_PHY_RST_ BIT(4) 604d94282aSBryan Whitehead #define PMT_CTL_WOL_EN_ BIT(3) 614d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 624d94282aSBryan Whitehead #define PMT_CTL_WUPS_MASK_ (0x00000003) 6323f0703cSBryan Whitehead 6423f0703cSBryan Whitehead #define DP_SEL (0x024) 6523f0703cSBryan Whitehead #define DP_SEL_DPRDY_ BIT(31) 6623f0703cSBryan Whitehead #define DP_SEL_MASK_ (0x0000001F) 6723f0703cSBryan Whitehead #define DP_SEL_RFE_RAM (0x00000001) 6823f0703cSBryan Whitehead 6923f0703cSBryan Whitehead #define DP_SEL_VHF_HASH_LEN (16) 7023f0703cSBryan Whitehead #define DP_SEL_VHF_VLAN_LEN (128) 7123f0703cSBryan Whitehead 7223f0703cSBryan Whitehead #define DP_CMD (0x028) 7323f0703cSBryan Whitehead #define DP_CMD_WRITE_ (0x00000001) 7423f0703cSBryan Whitehead 7523f0703cSBryan Whitehead #define DP_ADDR (0x02C) 7623f0703cSBryan Whitehead 7723f0703cSBryan Whitehead #define DP_DATA_0 (0x030) 7823f0703cSBryan Whitehead 7969584604SBryan Whitehead #define E2P_CMD (0x040) 8069584604SBryan Whitehead #define E2P_CMD_EPC_BUSY_ BIT(31) 8169584604SBryan Whitehead #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 8269584604SBryan Whitehead #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 8369584604SBryan Whitehead #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 8469584604SBryan Whitehead #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 8569584604SBryan Whitehead #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 8669584604SBryan Whitehead 8769584604SBryan Whitehead #define E2P_DATA (0x044) 8869584604SBryan Whitehead 89cdea83ccSRaju Lakkaraju /* Hearthstone top level & System Reg Addresses */ 90cdea83ccSRaju Lakkaraju #define ETH_CTRL_REG_ADDR_BASE (0x0000) 91cdea83ccSRaju Lakkaraju #define ETH_SYS_REG_ADDR_BASE (0x4000) 92cdea83ccSRaju Lakkaraju #define CONFIG_REG_ADDR_BASE (0x0000) 93cdea83ccSRaju Lakkaraju #define ETH_EEPROM_REG_ADDR_BASE (0x0E00) 94cdea83ccSRaju Lakkaraju #define ETH_OTP_REG_ADDR_BASE (0x1000) 95cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG (0x00A0) 96cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_MAIN_LOCK_ BIT(7) 97cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5) 98cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4) 99cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3) 100cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2) 101cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1) 102cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0) 103cdea83ccSRaju Lakkaraju #define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \ 104cdea83ccSRaju Lakkaraju CONFIG_REG_ADDR_BASE + \ 105cdea83ccSRaju Lakkaraju SYS_LOCK_REG) 106cdea83ccSRaju Lakkaraju #define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \ 107cdea83ccSRaju Lakkaraju ETH_EEPROM_REG_ADDR_BASE) 108cdea83ccSRaju Lakkaraju #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000) 109cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_BUSY_ BIT(31) 110cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28) 111cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_CMD_READ_ (0x0) 112cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17) 113cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0) 114cdea83ccSRaju Lakkaraju #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004) 115cdea83ccSRaju Lakkaraju #define HS_E2P_DATA_MASK_ GENMASK(7, 0) 116cdea83ccSRaju Lakkaraju #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008) 117cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16) 118cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12) 119cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8) 120cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0) 121cdea83ccSRaju Lakkaraju #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C) 122cdea83ccSRaju Lakkaraju 12307624df1SBryan Whitehead #define GPIO_CFG0 (0x050) 12407624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 12507624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 12607624df1SBryan Whitehead 12707624df1SBryan Whitehead #define GPIO_CFG1 (0x054) 12807624df1SBryan Whitehead #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 12907624df1SBryan Whitehead #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 13007624df1SBryan Whitehead 13107624df1SBryan Whitehead #define GPIO_CFG2 (0x058) 13207624df1SBryan Whitehead #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 13307624df1SBryan Whitehead 13407624df1SBryan Whitehead #define GPIO_CFG3 (0x05C) 13507624df1SBryan Whitehead #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 13607624df1SBryan Whitehead #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 13707624df1SBryan Whitehead 13823f0703cSBryan Whitehead #define FCT_RX_CTL (0xAC) 13923f0703cSBryan Whitehead #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 14023f0703cSBryan Whitehead #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 14123f0703cSBryan Whitehead #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 14223f0703cSBryan Whitehead 14323f0703cSBryan Whitehead #define FCT_TX_CTL (0xC4) 14423f0703cSBryan Whitehead #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 14523f0703cSBryan Whitehead #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 14623f0703cSBryan Whitehead #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 14723f0703cSBryan Whitehead 14823f0703cSBryan Whitehead #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 14923f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 15023f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 15123f0703cSBryan Whitehead ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 15223f0703cSBryan Whitehead #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 15323f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 15423f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 15523f0703cSBryan Whitehead ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 15623f0703cSBryan Whitehead 15723f0703cSBryan Whitehead #define MAC_CR (0x100) 1586f197fb6SRoelof Berg #define MAC_CR_MII_EN_ BIT(19) 159c9cf96bbSBryan Whitehead #define MAC_CR_EEE_EN_ BIT(17) 16023f0703cSBryan Whitehead #define MAC_CR_ADD_ BIT(12) 16123f0703cSBryan Whitehead #define MAC_CR_ASD_ BIT(11) 16223f0703cSBryan Whitehead #define MAC_CR_CNTR_RST_ BIT(5) 1636f197fb6SRoelof Berg #define MAC_CR_DPX_ BIT(3) 1646f197fb6SRoelof Berg #define MAC_CR_CFG_H_ BIT(2) 1656f197fb6SRoelof Berg #define MAC_CR_CFG_L_ BIT(1) 16623f0703cSBryan Whitehead #define MAC_CR_RST_ BIT(0) 16723f0703cSBryan Whitehead 16823f0703cSBryan Whitehead #define MAC_RX (0x104) 16923f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_SHIFT_ (16) 17023f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 17123f0703cSBryan Whitehead #define MAC_RX_RXD_ BIT(1) 17223f0703cSBryan Whitehead #define MAC_RX_RXEN_ BIT(0) 17323f0703cSBryan Whitehead 17423f0703cSBryan Whitehead #define MAC_TX (0x108) 17523f0703cSBryan Whitehead #define MAC_TX_TXD_ BIT(1) 17623f0703cSBryan Whitehead #define MAC_TX_TXEN_ BIT(0) 17723f0703cSBryan Whitehead 17823f0703cSBryan Whitehead #define MAC_FLOW (0x10C) 17923f0703cSBryan Whitehead #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 18023f0703cSBryan Whitehead #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 18123f0703cSBryan Whitehead #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 18223f0703cSBryan Whitehead 18323f0703cSBryan Whitehead #define MAC_RX_ADDRH (0x118) 18423f0703cSBryan Whitehead 18523f0703cSBryan Whitehead #define MAC_RX_ADDRL (0x11C) 18623f0703cSBryan Whitehead 18723f0703cSBryan Whitehead #define MAC_MII_ACC (0x120) 188a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16) 189a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000) 190a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0) 191a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1) 192a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2) 193a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3) 194a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4) 19523f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 19623f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 19723f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 19823f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 19923f0703cSBryan Whitehead #define MAC_MII_ACC_MII_READ_ (0x00000000) 20023f0703cSBryan Whitehead #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 20123f0703cSBryan Whitehead #define MAC_MII_ACC_MII_BUSY_ BIT(0) 20223f0703cSBryan Whitehead 203a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIIMMD_SHIFT_ (6) 204a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0) 205a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICL45_ BIT(3) 206a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_MASK_ (0x00000006) 207a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000) 208a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002) 209a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_READ_ (0x00000004) 210a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006) 211a2ab95a3SRaju Lakkaraju 21223f0703cSBryan Whitehead #define MAC_MII_DATA (0x124) 21323f0703cSBryan Whitehead 214c9cf96bbSBryan Whitehead #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 215c9cf96bbSBryan Whitehead 2164d94282aSBryan Whitehead #define MAC_WUCSR (0x140) 2174d94282aSBryan Whitehead #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 2184d94282aSBryan Whitehead #define MAC_WUCSR_PFDA_EN_ BIT(3) 2194d94282aSBryan Whitehead #define MAC_WUCSR_WAKE_EN_ BIT(2) 2204d94282aSBryan Whitehead #define MAC_WUCSR_MPEN_ BIT(1) 2214d94282aSBryan Whitehead #define MAC_WUCSR_BCST_EN_ BIT(0) 2224d94282aSBryan Whitehead 2234d94282aSBryan Whitehead #define MAC_WK_SRC (0x144) 2244d94282aSBryan Whitehead 2254d94282aSBryan Whitehead #define MAC_WUF_CFG0 (0x150) 2264d94282aSBryan Whitehead #define MAC_NUM_OF_WUF_CFG (32) 2274d94282aSBryan Whitehead #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 2284d94282aSBryan Whitehead #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 2294d94282aSBryan Whitehead #define MAC_WUF_CFG_EN_ BIT(31) 2304d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 2314d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 2324d94282aSBryan Whitehead #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 2334d94282aSBryan Whitehead #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 2344d94282aSBryan Whitehead 2354d94282aSBryan Whitehead #define MAC_WUF_MASK0_0 (0x200) 2364d94282aSBryan Whitehead #define MAC_WUF_MASK0_1 (0x204) 2374d94282aSBryan Whitehead #define MAC_WUF_MASK0_2 (0x208) 2384d94282aSBryan Whitehead #define MAC_WUF_MASK0_3 (0x20C) 2394d94282aSBryan Whitehead #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 2404d94282aSBryan Whitehead #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 2414d94282aSBryan Whitehead #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 2424d94282aSBryan Whitehead #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 2434d94282aSBryan Whitehead #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 2444d94282aSBryan Whitehead #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 2454d94282aSBryan Whitehead #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 2464d94282aSBryan Whitehead #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 2474d94282aSBryan Whitehead 24823f0703cSBryan Whitehead /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 24923f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 25023f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 25123f0703cSBryan Whitehead 25223f0703cSBryan Whitehead /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 25323f0703cSBryan Whitehead #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 25423f0703cSBryan Whitehead 25523f0703cSBryan Whitehead #define RFE_CTL (0x508) 25623f0703cSBryan Whitehead #define RFE_CTL_AB_ BIT(10) 25723f0703cSBryan Whitehead #define RFE_CTL_AM_ BIT(9) 25823f0703cSBryan Whitehead #define RFE_CTL_AU_ BIT(8) 25923f0703cSBryan Whitehead #define RFE_CTL_MCAST_HASH_ BIT(3) 26023f0703cSBryan Whitehead #define RFE_CTL_DA_PERFECT_ BIT(1) 26123f0703cSBryan Whitehead 26243e8fe9bSBryan Whitehead #define RFE_RSS_CFG (0x554) 26343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 26443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 26543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 26643e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 26743e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 26843e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_ BIT(11) 26943e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 27043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 27143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV4_ BIT(8) 27243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 27343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 27443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 27543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 27643e8fe9bSBryan Whitehead 27743e8fe9bSBryan Whitehead #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 27843e8fe9bSBryan Whitehead 27943e8fe9bSBryan Whitehead #define RFE_INDX(index) (0x580 + (index << 2)) 28043e8fe9bSBryan Whitehead 2814d94282aSBryan Whitehead #define MAC_WUCSR2 (0x600) 2824d94282aSBryan Whitehead 283a46d9d37SRaju Lakkaraju #define SGMII_CTL (0x728) 284a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_ENABLE_ BIT(31) 285a46d9d37SRaju Lakkaraju #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8) 286a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_POWER_DN_ BIT(1) 287a46d9d37SRaju Lakkaraju 28823f0703cSBryan Whitehead #define INT_STS (0x780) 28923f0703cSBryan Whitehead #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 29023f0703cSBryan Whitehead #define INT_BIT_ALL_RX_ (0x0F000000) 29123f0703cSBryan Whitehead #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 29223f0703cSBryan Whitehead #define INT_BIT_ALL_TX_ (0x000F0000) 29323f0703cSBryan Whitehead #define INT_BIT_SW_GP_ BIT(9) 29407624df1SBryan Whitehead #define INT_BIT_1588_ BIT(7) 29507624df1SBryan Whitehead #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 29623f0703cSBryan Whitehead #define INT_BIT_MAS_ BIT(0) 29723f0703cSBryan Whitehead 29823f0703cSBryan Whitehead #define INT_SET (0x784) 29923f0703cSBryan Whitehead 30023f0703cSBryan Whitehead #define INT_EN_SET (0x788) 30123f0703cSBryan Whitehead 30223f0703cSBryan Whitehead #define INT_EN_CLR (0x78C) 30323f0703cSBryan Whitehead 30423f0703cSBryan Whitehead #define INT_STS_R2C (0x790) 30523f0703cSBryan Whitehead 30623f0703cSBryan Whitehead #define INT_VEC_EN_SET (0x794) 30723f0703cSBryan Whitehead #define INT_VEC_EN_CLR (0x798) 30823f0703cSBryan Whitehead #define INT_VEC_EN_AUTO_CLR (0x79C) 30923f0703cSBryan Whitehead #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 31023f0703cSBryan Whitehead 31123f0703cSBryan Whitehead #define INT_VEC_MAP0 (0x7A0) 31223f0703cSBryan Whitehead #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 31323f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 31423f0703cSBryan Whitehead 31523f0703cSBryan Whitehead #define INT_VEC_MAP1 (0x7A4) 31623f0703cSBryan Whitehead #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 31723f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 31823f0703cSBryan Whitehead 31923f0703cSBryan Whitehead #define INT_VEC_MAP2 (0x7A8) 32023f0703cSBryan Whitehead 32123f0703cSBryan Whitehead #define INT_MOD_MAP0 (0x7B0) 32223f0703cSBryan Whitehead 32323f0703cSBryan Whitehead #define INT_MOD_MAP1 (0x7B4) 32423f0703cSBryan Whitehead 32523f0703cSBryan Whitehead #define INT_MOD_MAP2 (0x7B8) 32623f0703cSBryan Whitehead 32723f0703cSBryan Whitehead #define INT_MOD_CFG0 (0x7C0) 32823f0703cSBryan Whitehead #define INT_MOD_CFG1 (0x7C4) 32923f0703cSBryan Whitehead #define INT_MOD_CFG2 (0x7C8) 33023f0703cSBryan Whitehead #define INT_MOD_CFG3 (0x7CC) 33123f0703cSBryan Whitehead #define INT_MOD_CFG4 (0x7D0) 33223f0703cSBryan Whitehead #define INT_MOD_CFG5 (0x7D4) 33323f0703cSBryan Whitehead #define INT_MOD_CFG6 (0x7D8) 33423f0703cSBryan Whitehead #define INT_MOD_CFG7 (0x7DC) 335ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG8 (0x7E0) 336ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG9 (0x7E4) 33723f0703cSBryan Whitehead 33807624df1SBryan Whitehead #define PTP_CMD_CTL (0x0A00) 33907624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 34007624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 34107624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 34207624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 34307624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 34407624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 34507624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 34607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG (0x0A04) 34707624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 34807624df1SBryan Whitehead (0x7 << (1 + ((channel) << 2))) 34907624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 35007624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 35107624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 35207624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 35307624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 35407624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 3554ece1ae4SYuiko Oshino #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) 35607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 35707624df1SBryan Whitehead (((value) & 0x7) << (1 + ((channel) << 2))) 35807624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 35907624df1SBryan Whitehead 36007624df1SBryan Whitehead #define PTP_INT_STS (0x0A08) 36107624df1SBryan Whitehead #define PTP_INT_EN_SET (0x0A0C) 36207624df1SBryan Whitehead #define PTP_INT_EN_CLR (0x0A10) 36307624df1SBryan Whitehead #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 36407624df1SBryan Whitehead #define PTP_INT_BIT_TX_TS_ BIT(12) 36507624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_B_ BIT(1) 36607624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_A_ BIT(0) 36707624df1SBryan Whitehead 36807624df1SBryan Whitehead #define PTP_CLOCK_SEC (0x0A14) 36907624df1SBryan Whitehead #define PTP_CLOCK_NS (0x0A18) 37007624df1SBryan Whitehead #define PTP_CLOCK_SUBNS (0x0A1C) 37107624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ (0x0A20) 37207624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 37307624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ (0x0A2C) 37407624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 37507624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 37607624df1SBryan Whitehead #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 37707624df1SBryan Whitehead #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 37807624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 37907624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 38007624df1SBryan Whitehead #define PTP_LATENCY (0x0A5C) 38107624df1SBryan Whitehead #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 38207624df1SBryan Whitehead #define PTP_LATENCY_RX_SET_(rx_latency) \ 38307624df1SBryan Whitehead (((u32)(rx_latency)) & 0x0000FFFF) 38407624df1SBryan Whitehead #define PTP_CAP_INFO (0x0A60) 38507624df1SBryan Whitehead #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 38607624df1SBryan Whitehead 38707624df1SBryan Whitehead #define PTP_TX_MOD (0x0AA4) 38807624df1SBryan Whitehead #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 38907624df1SBryan Whitehead 39007624df1SBryan Whitehead #define PTP_TX_MOD2 (0x0AA8) 39107624df1SBryan Whitehead #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 39207624df1SBryan Whitehead 39307624df1SBryan Whitehead #define PTP_TX_EGRESS_SEC (0x0AAC) 39407624df1SBryan Whitehead #define PTP_TX_EGRESS_NS (0x0AB0) 39507624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 39607624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 39707624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 39807624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 39907624df1SBryan Whitehead 40007624df1SBryan Whitehead #define PTP_TX_MSG_HEADER (0x0AB4) 40107624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 40207624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 40307624df1SBryan Whitehead 40423f0703cSBryan Whitehead #define DMAC_CFG (0xC00) 40523f0703cSBryan Whitehead #define DMAC_CFG_COAL_EN_ BIT(16) 40623f0703cSBryan Whitehead #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 40723f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 40823f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 40923f0703cSBryan Whitehead ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 41023f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 41123f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 41223f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 41323f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 41423f0703cSBryan Whitehead 41523f0703cSBryan Whitehead #define DMAC_COAL_CFG (0xC04) 41623f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 41723f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 41823f0703cSBryan Whitehead ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 41923f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 42023f0703cSBryan Whitehead #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 42123f0703cSBryan Whitehead #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 42223f0703cSBryan Whitehead #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 42323f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 42423f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 42523f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 42623f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 42723f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 42823f0703cSBryan Whitehead (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 42923f0703cSBryan Whitehead 43023f0703cSBryan Whitehead #define DMAC_OBFF_CFG (0xC08) 43123f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 43223f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_SET_(val) \ 43323f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 43423f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 43523f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_SET_(val) \ 43623f0703cSBryan Whitehead (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 43723f0703cSBryan Whitehead 43823f0703cSBryan Whitehead #define DMAC_CMD (0xC0C) 43923f0703cSBryan Whitehead #define DMAC_CMD_SWR_ BIT(31) 44023f0703cSBryan Whitehead #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 44123f0703cSBryan Whitehead #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 44223f0703cSBryan Whitehead #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 44323f0703cSBryan Whitehead #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 44423f0703cSBryan Whitehead #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 44523f0703cSBryan Whitehead #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 44623f0703cSBryan Whitehead 44723f0703cSBryan Whitehead #define DMAC_INT_STS (0xC10) 44823f0703cSBryan Whitehead #define DMAC_INT_EN_SET (0xC14) 44923f0703cSBryan Whitehead #define DMAC_INT_EN_CLR (0xC18) 45023f0703cSBryan Whitehead #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 45123f0703cSBryan Whitehead #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 45223f0703cSBryan Whitehead 45323f0703cSBryan Whitehead #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 45423f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 45523f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 45623f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 45723f0703cSBryan Whitehead ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 45823f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 45923f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 46023f0703cSBryan Whitehead ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 46123f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 46223f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 46323f0703cSBryan Whitehead ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 46423f0703cSBryan Whitehead #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 46523f0703cSBryan Whitehead 46623f0703cSBryan Whitehead #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 46723f0703cSBryan Whitehead #define RX_CFG_B_TS_ALL_RX_ BIT(29) 46823f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 46923f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_0_ (0x00000000) 47023f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_2_ (0x02000000) 47123f0703cSBryan Whitehead #define RX_CFG_B_RDMABL_512_ (0x00040000) 47223f0703cSBryan Whitehead #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 47323f0703cSBryan Whitehead 47423f0703cSBryan Whitehead #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 47523f0703cSBryan Whitehead 47623f0703cSBryan Whitehead #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 47723f0703cSBryan Whitehead 47823f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 47923f0703cSBryan Whitehead 48023f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 48123f0703cSBryan Whitehead 48223f0703cSBryan Whitehead #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 48323f0703cSBryan Whitehead 48423f0703cSBryan Whitehead #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 48523f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 48623f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 48723f0703cSBryan Whitehead 48823f0703cSBryan Whitehead #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 48923f0703cSBryan Whitehead #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 49023f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 49123f0703cSBryan Whitehead #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 49223f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 49323f0703cSBryan Whitehead 49423f0703cSBryan Whitehead #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 49523f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 49623f0703cSBryan Whitehead #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 49723f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 49823f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 49923f0703cSBryan Whitehead ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 50023f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 50123f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 50223f0703cSBryan Whitehead ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 50323f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 50423f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 50523f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 50623f0703cSBryan Whitehead (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 50723f0703cSBryan Whitehead 50823f0703cSBryan Whitehead #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 50923f0703cSBryan Whitehead #define TX_CFG_B_TDMABL_512_ (0x00040000) 51023f0703cSBryan Whitehead #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 51123f0703cSBryan Whitehead 51223f0703cSBryan Whitehead #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 51323f0703cSBryan Whitehead 51423f0703cSBryan Whitehead #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 51523f0703cSBryan Whitehead 51623f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 51723f0703cSBryan Whitehead 51823f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 51923f0703cSBryan Whitehead 52023f0703cSBryan Whitehead #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 52123f0703cSBryan Whitehead 52223f0703cSBryan Whitehead #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 52323f0703cSBryan Whitehead #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 52423f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 52523f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 52623f0703cSBryan Whitehead 52723f0703cSBryan Whitehead #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 52823f0703cSBryan Whitehead #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 52923f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 53023f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 53123f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 53223f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 53323f0703cSBryan Whitehead 53469584604SBryan Whitehead #define OTP_PWR_DN (0x1000) 53569584604SBryan Whitehead #define OTP_PWR_DN_PWRDN_N_ BIT(0) 53669584604SBryan Whitehead 537662a14d0SBryan Whitehead #define OTP_ADDR_HIGH (0x1004) 538662a14d0SBryan Whitehead #define OTP_ADDR_LOW (0x1008) 53969584604SBryan Whitehead 54069584604SBryan Whitehead #define OTP_PRGM_DATA (0x1010) 54169584604SBryan Whitehead 54269584604SBryan Whitehead #define OTP_PRGM_MODE (0x1014) 54369584604SBryan Whitehead #define OTP_PRGM_MODE_BYTE_ BIT(0) 54469584604SBryan Whitehead 545662a14d0SBryan Whitehead #define OTP_READ_DATA (0x1018) 546662a14d0SBryan Whitehead 547662a14d0SBryan Whitehead #define OTP_FUNC_CMD (0x1020) 548662a14d0SBryan Whitehead #define OTP_FUNC_CMD_READ_ BIT(0) 549662a14d0SBryan Whitehead 55069584604SBryan Whitehead #define OTP_TST_CMD (0x1024) 55169584604SBryan Whitehead #define OTP_TST_CMD_PRGVRFY_ BIT(3) 55269584604SBryan Whitehead 55369584604SBryan Whitehead #define OTP_CMD_GO (0x1028) 55469584604SBryan Whitehead #define OTP_CMD_GO_GO_ BIT(0) 55569584604SBryan Whitehead 55669584604SBryan Whitehead #define OTP_STATUS (0x1030) 55769584604SBryan Whitehead #define OTP_STATUS_BUSY_ BIT(0) 55869584604SBryan Whitehead 559*d808f7caSRaju Lakkaraju /* Hearthstone OTP block registers */ 560*d808f7caSRaju Lakkaraju #define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \ 561*d808f7caSRaju Lakkaraju ETH_OTP_REG_ADDR_BASE) 562*d808f7caSRaju Lakkaraju #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0) 563*d808f7caSRaju Lakkaraju #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4) 564*d808f7caSRaju Lakkaraju #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8) 565*d808f7caSRaju Lakkaraju #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10) 566*d808f7caSRaju Lakkaraju #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14) 567*d808f7caSRaju Lakkaraju #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18) 568*d808f7caSRaju Lakkaraju #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20) 569*d808f7caSRaju Lakkaraju #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24) 570*d808f7caSRaju Lakkaraju #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28) 571*d808f7caSRaju Lakkaraju #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30) 572*d808f7caSRaju Lakkaraju 57323f0703cSBryan Whitehead /* MAC statistics registers */ 57423f0703cSBryan Whitehead #define STAT_RX_FCS_ERRORS (0x1200) 57523f0703cSBryan Whitehead #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 5768114e8a2SBryan Whitehead #define STAT_RX_FRAGMENT_ERRORS (0x1208) 57723f0703cSBryan Whitehead #define STAT_RX_JABBER_ERRORS (0x120C) 57823f0703cSBryan Whitehead #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 57923f0703cSBryan Whitehead #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 58023f0703cSBryan Whitehead #define STAT_RX_DROPPED_FRAMES (0x1218) 58123f0703cSBryan Whitehead #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 58223f0703cSBryan Whitehead #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 58323f0703cSBryan Whitehead #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 5848114e8a2SBryan Whitehead #define STAT_RX_UNICAST_FRAMES (0x1228) 5858114e8a2SBryan Whitehead #define STAT_RX_BROADCAST_FRAMES (0x122C) 58623f0703cSBryan Whitehead #define STAT_RX_MULTICAST_FRAMES (0x1230) 5878114e8a2SBryan Whitehead #define STAT_RX_PAUSE_FRAMES (0x1234) 5888114e8a2SBryan Whitehead #define STAT_RX_64_BYTE_FRAMES (0x1238) 5898114e8a2SBryan Whitehead #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 5908114e8a2SBryan Whitehead #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 5918114e8a2SBryan Whitehead #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 5928114e8a2SBryan Whitehead #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 5938114e8a2SBryan Whitehead #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 5948114e8a2SBryan Whitehead #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 59523f0703cSBryan Whitehead #define STAT_RX_TOTAL_FRAMES (0x1254) 5968114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 5978114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TIME (0x125C) 5988114e8a2SBryan Whitehead #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 59923f0703cSBryan Whitehead 60023f0703cSBryan Whitehead #define STAT_TX_FCS_ERRORS (0x1280) 60123f0703cSBryan Whitehead #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 60223f0703cSBryan Whitehead #define STAT_TX_CARRIER_ERRORS (0x1288) 6038114e8a2SBryan Whitehead #define STAT_TX_BAD_BYTE_COUNT (0x128C) 60423f0703cSBryan Whitehead #define STAT_TX_SINGLE_COLLISIONS (0x1290) 60523f0703cSBryan Whitehead #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 60623f0703cSBryan Whitehead #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 60723f0703cSBryan Whitehead #define STAT_TX_LATE_COLLISIONS (0x129C) 60823f0703cSBryan Whitehead #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 60923f0703cSBryan Whitehead #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 61023f0703cSBryan Whitehead #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 6118114e8a2SBryan Whitehead #define STAT_TX_UNICAST_FRAMES (0x12AC) 6128114e8a2SBryan Whitehead #define STAT_TX_BROADCAST_FRAMES (0x12B0) 61323f0703cSBryan Whitehead #define STAT_TX_MULTICAST_FRAMES (0x12B4) 6148114e8a2SBryan Whitehead #define STAT_TX_PAUSE_FRAMES (0x12B8) 6158114e8a2SBryan Whitehead #define STAT_TX_64_BYTE_FRAMES (0x12BC) 6168114e8a2SBryan Whitehead #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 6178114e8a2SBryan Whitehead #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 6188114e8a2SBryan Whitehead #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 6198114e8a2SBryan Whitehead #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 6208114e8a2SBryan Whitehead #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 6218114e8a2SBryan Whitehead #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 62223f0703cSBryan Whitehead #define STAT_TX_TOTAL_FRAMES (0x12D8) 6238114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 6248114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TIME (0x12E0) 6258114e8a2SBryan Whitehead #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 62623f0703cSBryan Whitehead 62723f0703cSBryan Whitehead /* End of Register definitions */ 62823f0703cSBryan Whitehead 62923f0703cSBryan Whitehead #define LAN743X_MAX_RX_CHANNELS (4) 63023f0703cSBryan Whitehead #define LAN743X_MAX_TX_CHANNELS (1) 631cf9aaea8SRaju Lakkaraju #define PCI11X1X_MAX_TX_CHANNELS (4) 63223f0703cSBryan Whitehead struct lan743x_adapter; 63323f0703cSBryan Whitehead 63423f0703cSBryan Whitehead #define LAN743X_USED_RX_CHANNELS (4) 63523f0703cSBryan Whitehead #define LAN743X_USED_TX_CHANNELS (1) 636cf9aaea8SRaju Lakkaraju #define PCI11X1X_USED_TX_CHANNELS (4) 63723f0703cSBryan Whitehead #define LAN743X_INT_MOD (400) 63823f0703cSBryan Whitehead 63923f0703cSBryan Whitehead #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 64023f0703cSBryan Whitehead #error Invalid LAN743X_USED_RX_CHANNELS 64123f0703cSBryan Whitehead #endif 64223f0703cSBryan Whitehead #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 64323f0703cSBryan Whitehead #error Invalid LAN743X_USED_TX_CHANNELS 64423f0703cSBryan Whitehead #endif 645cf9aaea8SRaju Lakkaraju #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS) 646cf9aaea8SRaju Lakkaraju #error Invalid PCI11X1X_USED_TX_CHANNELS 647cf9aaea8SRaju Lakkaraju #endif 64823f0703cSBryan Whitehead 64923f0703cSBryan Whitehead /* PCI */ 65023f0703cSBryan Whitehead /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 65123f0703cSBryan Whitehead #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 65223f0703cSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 6534df5ce9bSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) 654bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A011 (0xA011) 655bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A041 (0xA041) 65623f0703cSBryan Whitehead 65723f0703cSBryan Whitehead #define PCI_CONFIG_LENGTH (0x1000) 65823f0703cSBryan Whitehead 65923f0703cSBryan Whitehead /* CSR */ 66023f0703cSBryan Whitehead #define CSR_LENGTH (0x2000) 66123f0703cSBryan Whitehead 66223f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 66323f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 66423f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 66523f0703cSBryan Whitehead 66623f0703cSBryan Whitehead struct lan743x_csr { 66723f0703cSBryan Whitehead u32 flags; 66823f0703cSBryan Whitehead u8 __iomem *csr_address; 66923f0703cSBryan Whitehead u32 id_rev; 67023f0703cSBryan Whitehead u32 fpga_rev; 67123f0703cSBryan Whitehead }; 67223f0703cSBryan Whitehead 67323f0703cSBryan Whitehead /* INTERRUPTS */ 67423f0703cSBryan Whitehead typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 67523f0703cSBryan Whitehead 67623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 67723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 67823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 67923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 68023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 68123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 68223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 68323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 68423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 68523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 68623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 68723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 68823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 68923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 69023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 69123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 69223f0703cSBryan Whitehead 69323f0703cSBryan Whitehead struct lan743x_vector { 69423f0703cSBryan Whitehead int irq; 69523f0703cSBryan Whitehead u32 flags; 69623f0703cSBryan Whitehead struct lan743x_adapter *adapter; 69723f0703cSBryan Whitehead int vector_index; 69823f0703cSBryan Whitehead u32 int_mask; 69923f0703cSBryan Whitehead lan743x_vector_handler handler; 70023f0703cSBryan Whitehead void *context; 70123f0703cSBryan Whitehead }; 70223f0703cSBryan Whitehead 70323f0703cSBryan Whitehead #define LAN743X_MAX_VECTOR_COUNT (8) 704ac16b6ebSRaju Lakkaraju #define PCI11X1X_MAX_VECTOR_COUNT (16) 70523f0703cSBryan Whitehead 70623f0703cSBryan Whitehead struct lan743x_intr { 70723f0703cSBryan Whitehead int flags; 70823f0703cSBryan Whitehead 70923f0703cSBryan Whitehead unsigned int irq; 71023f0703cSBryan Whitehead 711ac16b6ebSRaju Lakkaraju struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT]; 71223f0703cSBryan Whitehead int number_of_vectors; 71323f0703cSBryan Whitehead bool using_vectors; 71423f0703cSBryan Whitehead 715470dfd80SSven Van Asbroeck bool software_isr_flag; 716470dfd80SSven Van Asbroeck wait_queue_head_t software_isr_wq; 71723f0703cSBryan Whitehead }; 71823f0703cSBryan Whitehead 71923f0703cSBryan Whitehead #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 72023f0703cSBryan Whitehead 72123f0703cSBryan Whitehead /* PHY */ 72223f0703cSBryan Whitehead struct lan743x_phy { 72323f0703cSBryan Whitehead bool fc_autoneg; 72423f0703cSBryan Whitehead u8 fc_request_control; 72523f0703cSBryan Whitehead }; 72623f0703cSBryan Whitehead 72723f0703cSBryan Whitehead /* TX */ 72823f0703cSBryan Whitehead struct lan743x_tx_descriptor; 72923f0703cSBryan Whitehead struct lan743x_tx_buffer_info; 73023f0703cSBryan Whitehead 73123f0703cSBryan Whitehead #define GPIO_QUEUE_STARTED (0) 73223f0703cSBryan Whitehead #define GPIO_TX_FUNCTION (1) 73323f0703cSBryan Whitehead #define GPIO_TX_COMPLETION (2) 73423f0703cSBryan Whitehead #define GPIO_TX_FRAGMENT (3) 73523f0703cSBryan Whitehead 73623f0703cSBryan Whitehead #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 73723f0703cSBryan Whitehead 73807624df1SBryan Whitehead #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 73907624df1SBryan Whitehead #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 74007624df1SBryan Whitehead 74123f0703cSBryan Whitehead struct lan743x_tx { 74223f0703cSBryan Whitehead struct lan743x_adapter *adapter; 74307624df1SBryan Whitehead u32 ts_flags; 74423f0703cSBryan Whitehead u32 vector_flags; 74523f0703cSBryan Whitehead int channel_number; 74623f0703cSBryan Whitehead 74723f0703cSBryan Whitehead int ring_size; 74823f0703cSBryan Whitehead size_t ring_allocation_size; 74923f0703cSBryan Whitehead struct lan743x_tx_descriptor *ring_cpu_ptr; 75023f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 75123f0703cSBryan Whitehead /* ring_lock: used to prevent concurrent access to tx ring */ 75223f0703cSBryan Whitehead spinlock_t ring_lock; 75323f0703cSBryan Whitehead u32 frame_flags; 75423f0703cSBryan Whitehead u32 frame_first; 75523f0703cSBryan Whitehead u32 frame_data0; 75623f0703cSBryan Whitehead u32 frame_tail; 75723f0703cSBryan Whitehead 75823f0703cSBryan Whitehead struct lan743x_tx_buffer_info *buffer_info; 75923f0703cSBryan Whitehead 76046251282SAlexey Denisov __le32 *head_cpu_ptr; 76123f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 76223f0703cSBryan Whitehead int last_head; 76323f0703cSBryan Whitehead int last_tail; 76423f0703cSBryan Whitehead 76523f0703cSBryan Whitehead struct napi_struct napi; 766bc1962e5SRaju Lakkaraju u32 frame_count; 76723f0703cSBryan Whitehead 76823f0703cSBryan Whitehead struct sk_buff *overflow_skb; 76923f0703cSBryan Whitehead }; 77023f0703cSBryan Whitehead 77107624df1SBryan Whitehead void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 77207624df1SBryan Whitehead bool enable_timestamping, 77307624df1SBryan Whitehead bool enable_onestep_sync); 77407624df1SBryan Whitehead 77523f0703cSBryan Whitehead /* RX */ 77623f0703cSBryan Whitehead struct lan743x_rx_descriptor; 77723f0703cSBryan Whitehead struct lan743x_rx_buffer_info; 77823f0703cSBryan Whitehead 77923f0703cSBryan Whitehead struct lan743x_rx { 78023f0703cSBryan Whitehead struct lan743x_adapter *adapter; 78123f0703cSBryan Whitehead u32 vector_flags; 78223f0703cSBryan Whitehead int channel_number; 78323f0703cSBryan Whitehead 78423f0703cSBryan Whitehead int ring_size; 78523f0703cSBryan Whitehead size_t ring_allocation_size; 78623f0703cSBryan Whitehead struct lan743x_rx_descriptor *ring_cpu_ptr; 78723f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 78823f0703cSBryan Whitehead 78923f0703cSBryan Whitehead struct lan743x_rx_buffer_info *buffer_info; 79023f0703cSBryan Whitehead 79146251282SAlexey Denisov __le32 *head_cpu_ptr; 79223f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 79323f0703cSBryan Whitehead u32 last_head; 79423f0703cSBryan Whitehead u32 last_tail; 79523f0703cSBryan Whitehead 79623f0703cSBryan Whitehead struct napi_struct napi; 79723f0703cSBryan Whitehead 79823f0703cSBryan Whitehead u32 frame_count; 799a8db76d4SSven Van Asbroeck 800a8db76d4SSven Van Asbroeck struct sk_buff *skb_head, *skb_tail; 80123f0703cSBryan Whitehead }; 80223f0703cSBryan Whitehead 80323f0703cSBryan Whitehead struct lan743x_adapter { 80423f0703cSBryan Whitehead struct net_device *netdev; 80523f0703cSBryan Whitehead struct mii_bus *mdiobus; 80623f0703cSBryan Whitehead int msg_enable; 8074d94282aSBryan Whitehead #ifdef CONFIG_PM 8084d94282aSBryan Whitehead u32 wolopts; 8094d94282aSBryan Whitehead #endif 81023f0703cSBryan Whitehead struct pci_dev *pdev; 81123f0703cSBryan Whitehead struct lan743x_csr csr; 81223f0703cSBryan Whitehead struct lan743x_intr intr; 81323f0703cSBryan Whitehead 81407624df1SBryan Whitehead struct lan743x_gpio gpio; 81507624df1SBryan Whitehead struct lan743x_ptp ptp; 81607624df1SBryan Whitehead 81723f0703cSBryan Whitehead u8 mac_address[ETH_ALEN]; 81823f0703cSBryan Whitehead 81923f0703cSBryan Whitehead struct lan743x_phy phy; 820cf9aaea8SRaju Lakkaraju struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS]; 821cf9aaea8SRaju Lakkaraju struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; 822cf9aaea8SRaju Lakkaraju bool is_pci11x1x; 823a46d9d37SRaju Lakkaraju bool is_sgmii_en; 824cdea83ccSRaju Lakkaraju /* protect ethernet syslock */ 825cdea83ccSRaju Lakkaraju spinlock_t eth_syslock_spinlock; 826cdea83ccSRaju Lakkaraju bool eth_syslock_en; 827cdea83ccSRaju Lakkaraju u32 eth_syslock_acquire_cnt; 828cf9aaea8SRaju Lakkaraju u8 max_tx_channels; 829cf9aaea8SRaju Lakkaraju u8 used_tx_channels; 830ac16b6ebSRaju Lakkaraju u8 max_vector_count; 831662a14d0SBryan Whitehead 832662a14d0SBryan Whitehead #define LAN743X_ADAPTER_FLAG_OTP BIT(0) 833662a14d0SBryan Whitehead u32 flags; 83423f0703cSBryan Whitehead }; 83523f0703cSBryan Whitehead 83623f0703cSBryan Whitehead #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 83723f0703cSBryan Whitehead 83823f0703cSBryan Whitehead #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 83923f0703cSBryan Whitehead #define INTR_FLAG_MSI_ENABLED BIT(8) 84023f0703cSBryan Whitehead #define INTR_FLAG_MSIX_ENABLED BIT(9) 84123f0703cSBryan Whitehead 84223f0703cSBryan Whitehead #define MAC_MII_READ 1 84323f0703cSBryan Whitehead #define MAC_MII_WRITE 0 84423f0703cSBryan Whitehead 84523f0703cSBryan Whitehead #define PHY_FLAG_OPENED BIT(0) 84623f0703cSBryan Whitehead #define PHY_FLAG_ATTACHED BIT(1) 84723f0703cSBryan Whitehead 84823f0703cSBryan Whitehead #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 84923f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 85023f0703cSBryan Whitehead #else 85123f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 85223f0703cSBryan Whitehead #endif 85323f0703cSBryan Whitehead #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 85423f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_16 (16) 85523f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_32 (32) 85623f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_64 (64) 85723f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_128 (128) 85823f0703cSBryan Whitehead #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 85923f0703cSBryan Whitehead 86023f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 86123f0703cSBryan Whitehead (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 86223f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 86323f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 86423f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 86523f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 86623f0703cSBryan Whitehead 86723f0703cSBryan Whitehead /* TX Descriptor bits */ 86823f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 86923f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 87023f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 87123f0703cSBryan Whitehead #define TX_DESC_DATA0_FS_ (0x20000000) 87223f0703cSBryan Whitehead #define TX_DESC_DATA0_LS_ (0x10000000) 87323f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_ (0x08000000) 87423f0703cSBryan Whitehead #define TX_DESC_DATA0_IOC_ (0x04000000) 87523f0703cSBryan Whitehead #define TX_DESC_DATA0_ICE_ (0x00400000) 87623f0703cSBryan Whitehead #define TX_DESC_DATA0_IPE_ (0x00200000) 87723f0703cSBryan Whitehead #define TX_DESC_DATA0_TPE_ (0x00100000) 87823f0703cSBryan Whitehead #define TX_DESC_DATA0_FCS_ (0x00020000) 87907624df1SBryan Whitehead #define TX_DESC_DATA0_TSE_ (0x00010000) 88023f0703cSBryan Whitehead #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 88123f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 88223f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 88323f0703cSBryan Whitehead #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 88423f0703cSBryan Whitehead 88523f0703cSBryan Whitehead struct lan743x_tx_descriptor { 88646251282SAlexey Denisov __le32 data0; 88746251282SAlexey Denisov __le32 data1; 88846251282SAlexey Denisov __le32 data2; 88946251282SAlexey Denisov __le32 data3; 89023f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 89123f0703cSBryan Whitehead 89223f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 89307624df1SBryan Whitehead #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 89423f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 89523f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 89623f0703cSBryan Whitehead struct lan743x_tx_buffer_info { 89723f0703cSBryan Whitehead int flags; 89823f0703cSBryan Whitehead struct sk_buff *skb; 89923f0703cSBryan Whitehead dma_addr_t dma_ptr; 90023f0703cSBryan Whitehead unsigned int buffer_length; 90123f0703cSBryan Whitehead }; 90223f0703cSBryan Whitehead 90323f0703cSBryan Whitehead #define LAN743X_TX_RING_SIZE (50) 90423f0703cSBryan Whitehead 90523f0703cSBryan Whitehead /* OWN bit is set. ie, Descs are owned by RX DMAC */ 90623f0703cSBryan Whitehead #define RX_DESC_DATA0_OWN_ (0x00008000) 90723f0703cSBryan Whitehead /* OWN bit is clear. ie, Descs are owned by host */ 90823f0703cSBryan Whitehead #define RX_DESC_DATA0_FS_ (0x80000000) 90923f0703cSBryan Whitehead #define RX_DESC_DATA0_LS_ (0x40000000) 91023f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 91123f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 91223f0703cSBryan Whitehead (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 91323f0703cSBryan Whitehead #define RX_DESC_DATA0_EXT_ (0x00004000) 91423f0703cSBryan Whitehead #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 91523f0703cSBryan Whitehead #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 91623f0703cSBryan Whitehead 91723f0703cSBryan Whitehead #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 91823f0703cSBryan Whitehead #error NET_IP_ALIGN must be 0 or 2 91923f0703cSBryan Whitehead #endif 92023f0703cSBryan Whitehead 92123f0703cSBryan Whitehead #define RX_HEAD_PADDING NET_IP_ALIGN 92223f0703cSBryan Whitehead 92323f0703cSBryan Whitehead struct lan743x_rx_descriptor { 92446251282SAlexey Denisov __le32 data0; 92546251282SAlexey Denisov __le32 data1; 92646251282SAlexey Denisov __le32 data2; 92746251282SAlexey Denisov __le32 data3; 92823f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 92923f0703cSBryan Whitehead 93023f0703cSBryan Whitehead #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 93123f0703cSBryan Whitehead struct lan743x_rx_buffer_info { 93223f0703cSBryan Whitehead int flags; 93323f0703cSBryan Whitehead struct sk_buff *skb; 93423f0703cSBryan Whitehead 93523f0703cSBryan Whitehead dma_addr_t dma_ptr; 93623f0703cSBryan Whitehead unsigned int buffer_length; 93723f0703cSBryan Whitehead }; 93823f0703cSBryan Whitehead 939a1f16275SYuiko Oshino #define LAN743X_RX_RING_SIZE (128) 94023f0703cSBryan Whitehead 94123f0703cSBryan Whitehead #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 942a8db76d4SSven Van Asbroeck #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) 94323f0703cSBryan Whitehead 9448114e8a2SBryan Whitehead u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 9458114e8a2SBryan Whitehead void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 9468114e8a2SBryan Whitehead 94723f0703cSBryan Whitehead #endif /* _LAN743X_H */ 948