123f0703cSBryan Whitehead /* SPDX-License-Identifier: GPL-2.0+ */ 223f0703cSBryan Whitehead /* Copyright (C) 2018 Microchip Technology Inc. */ 323f0703cSBryan Whitehead 423f0703cSBryan Whitehead #ifndef _LAN743X_H 523f0703cSBryan Whitehead #define _LAN743X_H 623f0703cSBryan Whitehead 76f197fb6SRoelof Berg #include <linux/phy.h> 807624df1SBryan Whitehead #include "lan743x_ptp.h" 907624df1SBryan Whitehead 1023f0703cSBryan Whitehead #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 1123f0703cSBryan Whitehead #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 1223f0703cSBryan Whitehead #define DRIVER_NAME "lan743x" 1323f0703cSBryan Whitehead 1423f0703cSBryan Whitehead /* Register Definitions */ 1523f0703cSBryan Whitehead #define ID_REV (0x00) 1607624df1SBryan Whitehead #define ID_REV_ID_MASK_ (0xFFFF0000) 1707624df1SBryan Whitehead #define ID_REV_ID_LAN7430_ (0x74300000) 1807624df1SBryan Whitehead #define ID_REV_ID_LAN7431_ (0x74310000) 19bb4f6bffSRaju Lakkaraju #define ID_REV_ID_LAN743X_ (0x74300000) 20bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 21bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 22bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A0X1_ (0xA0010000) 2323f0703cSBryan Whitehead #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 24bb4f6bffSRaju Lakkaraju ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ 25bb4f6bffSRaju Lakkaraju (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) 2623f0703cSBryan Whitehead #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 2723f0703cSBryan Whitehead #define ID_REV_CHIP_REV_A0_ (0x00000000) 2823f0703cSBryan Whitehead #define ID_REV_CHIP_REV_B0_ (0x00000010) 2923f0703cSBryan Whitehead 3023f0703cSBryan Whitehead #define FPGA_REV (0x04) 3123f0703cSBryan Whitehead #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 3223f0703cSBryan Whitehead #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 3323f0703cSBryan Whitehead 3423f0703cSBryan Whitehead #define HW_CFG (0x010) 35662a14d0SBryan Whitehead #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) 36662a14d0SBryan Whitehead #define HW_CFG_EE_OTP_RELOAD_ BIT(4) 3723f0703cSBryan Whitehead #define HW_CFG_LRST_ BIT(1) 3823f0703cSBryan Whitehead 3923f0703cSBryan Whitehead #define PMT_CTL (0x014) 404d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 414d94282aSBryan Whitehead #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 424d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 434d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 444d94282aSBryan Whitehead #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 454d94282aSBryan Whitehead #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 464d94282aSBryan Whitehead #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 4723f0703cSBryan Whitehead #define PMT_CTL_READY_ BIT(7) 4823f0703cSBryan Whitehead #define PMT_CTL_ETH_PHY_RST_ BIT(4) 494d94282aSBryan Whitehead #define PMT_CTL_WOL_EN_ BIT(3) 504d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 514d94282aSBryan Whitehead #define PMT_CTL_WUPS_MASK_ (0x00000003) 5223f0703cSBryan Whitehead 5323f0703cSBryan Whitehead #define DP_SEL (0x024) 5423f0703cSBryan Whitehead #define DP_SEL_DPRDY_ BIT(31) 5523f0703cSBryan Whitehead #define DP_SEL_MASK_ (0x0000001F) 5623f0703cSBryan Whitehead #define DP_SEL_RFE_RAM (0x00000001) 5723f0703cSBryan Whitehead 5823f0703cSBryan Whitehead #define DP_SEL_VHF_HASH_LEN (16) 5923f0703cSBryan Whitehead #define DP_SEL_VHF_VLAN_LEN (128) 6023f0703cSBryan Whitehead 6123f0703cSBryan Whitehead #define DP_CMD (0x028) 6223f0703cSBryan Whitehead #define DP_CMD_WRITE_ (0x00000001) 6323f0703cSBryan Whitehead 6423f0703cSBryan Whitehead #define DP_ADDR (0x02C) 6523f0703cSBryan Whitehead 6623f0703cSBryan Whitehead #define DP_DATA_0 (0x030) 6723f0703cSBryan Whitehead 6869584604SBryan Whitehead #define E2P_CMD (0x040) 6969584604SBryan Whitehead #define E2P_CMD_EPC_BUSY_ BIT(31) 7069584604SBryan Whitehead #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 7169584604SBryan Whitehead #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 7269584604SBryan Whitehead #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 7369584604SBryan Whitehead #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 7469584604SBryan Whitehead #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 7569584604SBryan Whitehead 7669584604SBryan Whitehead #define E2P_DATA (0x044) 7769584604SBryan Whitehead 7807624df1SBryan Whitehead #define GPIO_CFG0 (0x050) 7907624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 8007624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 8107624df1SBryan Whitehead 8207624df1SBryan Whitehead #define GPIO_CFG1 (0x054) 8307624df1SBryan Whitehead #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 8407624df1SBryan Whitehead #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 8507624df1SBryan Whitehead 8607624df1SBryan Whitehead #define GPIO_CFG2 (0x058) 8707624df1SBryan Whitehead #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 8807624df1SBryan Whitehead 8907624df1SBryan Whitehead #define GPIO_CFG3 (0x05C) 9007624df1SBryan Whitehead #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 9107624df1SBryan Whitehead #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 9207624df1SBryan Whitehead 9323f0703cSBryan Whitehead #define FCT_RX_CTL (0xAC) 9423f0703cSBryan Whitehead #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 9523f0703cSBryan Whitehead #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 9623f0703cSBryan Whitehead #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 9723f0703cSBryan Whitehead 9823f0703cSBryan Whitehead #define FCT_TX_CTL (0xC4) 9923f0703cSBryan Whitehead #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 10023f0703cSBryan Whitehead #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 10123f0703cSBryan Whitehead #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 10223f0703cSBryan Whitehead 10323f0703cSBryan Whitehead #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 10423f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 10523f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 10623f0703cSBryan Whitehead ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 10723f0703cSBryan Whitehead #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 10823f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 10923f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 11023f0703cSBryan Whitehead ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 11123f0703cSBryan Whitehead 11223f0703cSBryan Whitehead #define MAC_CR (0x100) 1136f197fb6SRoelof Berg #define MAC_CR_MII_EN_ BIT(19) 114c9cf96bbSBryan Whitehead #define MAC_CR_EEE_EN_ BIT(17) 11523f0703cSBryan Whitehead #define MAC_CR_ADD_ BIT(12) 11623f0703cSBryan Whitehead #define MAC_CR_ASD_ BIT(11) 11723f0703cSBryan Whitehead #define MAC_CR_CNTR_RST_ BIT(5) 1186f197fb6SRoelof Berg #define MAC_CR_DPX_ BIT(3) 1196f197fb6SRoelof Berg #define MAC_CR_CFG_H_ BIT(2) 1206f197fb6SRoelof Berg #define MAC_CR_CFG_L_ BIT(1) 12123f0703cSBryan Whitehead #define MAC_CR_RST_ BIT(0) 12223f0703cSBryan Whitehead 12323f0703cSBryan Whitehead #define MAC_RX (0x104) 12423f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_SHIFT_ (16) 12523f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 12623f0703cSBryan Whitehead #define MAC_RX_RXD_ BIT(1) 12723f0703cSBryan Whitehead #define MAC_RX_RXEN_ BIT(0) 12823f0703cSBryan Whitehead 12923f0703cSBryan Whitehead #define MAC_TX (0x108) 13023f0703cSBryan Whitehead #define MAC_TX_TXD_ BIT(1) 13123f0703cSBryan Whitehead #define MAC_TX_TXEN_ BIT(0) 13223f0703cSBryan Whitehead 13323f0703cSBryan Whitehead #define MAC_FLOW (0x10C) 13423f0703cSBryan Whitehead #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 13523f0703cSBryan Whitehead #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 13623f0703cSBryan Whitehead #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 13723f0703cSBryan Whitehead 13823f0703cSBryan Whitehead #define MAC_RX_ADDRH (0x118) 13923f0703cSBryan Whitehead 14023f0703cSBryan Whitehead #define MAC_RX_ADDRL (0x11C) 14123f0703cSBryan Whitehead 14223f0703cSBryan Whitehead #define MAC_MII_ACC (0x120) 14323f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 14423f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 14523f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 14623f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 14723f0703cSBryan Whitehead #define MAC_MII_ACC_MII_READ_ (0x00000000) 14823f0703cSBryan Whitehead #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 14923f0703cSBryan Whitehead #define MAC_MII_ACC_MII_BUSY_ BIT(0) 15023f0703cSBryan Whitehead 15123f0703cSBryan Whitehead #define MAC_MII_DATA (0x124) 15223f0703cSBryan Whitehead 153c9cf96bbSBryan Whitehead #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 154c9cf96bbSBryan Whitehead 1554d94282aSBryan Whitehead #define MAC_WUCSR (0x140) 1564d94282aSBryan Whitehead #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 1574d94282aSBryan Whitehead #define MAC_WUCSR_PFDA_EN_ BIT(3) 1584d94282aSBryan Whitehead #define MAC_WUCSR_WAKE_EN_ BIT(2) 1594d94282aSBryan Whitehead #define MAC_WUCSR_MPEN_ BIT(1) 1604d94282aSBryan Whitehead #define MAC_WUCSR_BCST_EN_ BIT(0) 1614d94282aSBryan Whitehead 1624d94282aSBryan Whitehead #define MAC_WK_SRC (0x144) 1634d94282aSBryan Whitehead 1644d94282aSBryan Whitehead #define MAC_WUF_CFG0 (0x150) 1654d94282aSBryan Whitehead #define MAC_NUM_OF_WUF_CFG (32) 1664d94282aSBryan Whitehead #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 1674d94282aSBryan Whitehead #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 1684d94282aSBryan Whitehead #define MAC_WUF_CFG_EN_ BIT(31) 1694d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 1704d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 1714d94282aSBryan Whitehead #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 1724d94282aSBryan Whitehead #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 1734d94282aSBryan Whitehead 1744d94282aSBryan Whitehead #define MAC_WUF_MASK0_0 (0x200) 1754d94282aSBryan Whitehead #define MAC_WUF_MASK0_1 (0x204) 1764d94282aSBryan Whitehead #define MAC_WUF_MASK0_2 (0x208) 1774d94282aSBryan Whitehead #define MAC_WUF_MASK0_3 (0x20C) 1784d94282aSBryan Whitehead #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 1794d94282aSBryan Whitehead #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 1804d94282aSBryan Whitehead #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 1814d94282aSBryan Whitehead #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 1824d94282aSBryan Whitehead #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 1834d94282aSBryan Whitehead #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 1844d94282aSBryan Whitehead #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 1854d94282aSBryan Whitehead #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 1864d94282aSBryan Whitehead 18723f0703cSBryan Whitehead /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 18823f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 18923f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 19023f0703cSBryan Whitehead 19123f0703cSBryan Whitehead /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 19223f0703cSBryan Whitehead #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 19323f0703cSBryan Whitehead 19423f0703cSBryan Whitehead #define RFE_CTL (0x508) 19523f0703cSBryan Whitehead #define RFE_CTL_AB_ BIT(10) 19623f0703cSBryan Whitehead #define RFE_CTL_AM_ BIT(9) 19723f0703cSBryan Whitehead #define RFE_CTL_AU_ BIT(8) 19823f0703cSBryan Whitehead #define RFE_CTL_MCAST_HASH_ BIT(3) 19923f0703cSBryan Whitehead #define RFE_CTL_DA_PERFECT_ BIT(1) 20023f0703cSBryan Whitehead 20143e8fe9bSBryan Whitehead #define RFE_RSS_CFG (0x554) 20243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 20343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 20443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 20543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 20643e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 20743e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_ BIT(11) 20843e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 20943e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 21043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV4_ BIT(8) 21143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 21243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 21343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 21443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 21543e8fe9bSBryan Whitehead 21643e8fe9bSBryan Whitehead #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 21743e8fe9bSBryan Whitehead 21843e8fe9bSBryan Whitehead #define RFE_INDX(index) (0x580 + (index << 2)) 21943e8fe9bSBryan Whitehead 2204d94282aSBryan Whitehead #define MAC_WUCSR2 (0x600) 2214d94282aSBryan Whitehead 22223f0703cSBryan Whitehead #define INT_STS (0x780) 22323f0703cSBryan Whitehead #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 22423f0703cSBryan Whitehead #define INT_BIT_ALL_RX_ (0x0F000000) 22523f0703cSBryan Whitehead #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 22623f0703cSBryan Whitehead #define INT_BIT_ALL_TX_ (0x000F0000) 22723f0703cSBryan Whitehead #define INT_BIT_SW_GP_ BIT(9) 22807624df1SBryan Whitehead #define INT_BIT_1588_ BIT(7) 22907624df1SBryan Whitehead #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 23023f0703cSBryan Whitehead #define INT_BIT_MAS_ BIT(0) 23123f0703cSBryan Whitehead 23223f0703cSBryan Whitehead #define INT_SET (0x784) 23323f0703cSBryan Whitehead 23423f0703cSBryan Whitehead #define INT_EN_SET (0x788) 23523f0703cSBryan Whitehead 23623f0703cSBryan Whitehead #define INT_EN_CLR (0x78C) 23723f0703cSBryan Whitehead 23823f0703cSBryan Whitehead #define INT_STS_R2C (0x790) 23923f0703cSBryan Whitehead 24023f0703cSBryan Whitehead #define INT_VEC_EN_SET (0x794) 24123f0703cSBryan Whitehead #define INT_VEC_EN_CLR (0x798) 24223f0703cSBryan Whitehead #define INT_VEC_EN_AUTO_CLR (0x79C) 24323f0703cSBryan Whitehead #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 24423f0703cSBryan Whitehead 24523f0703cSBryan Whitehead #define INT_VEC_MAP0 (0x7A0) 24623f0703cSBryan Whitehead #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 24723f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 24823f0703cSBryan Whitehead 24923f0703cSBryan Whitehead #define INT_VEC_MAP1 (0x7A4) 25023f0703cSBryan Whitehead #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 25123f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 25223f0703cSBryan Whitehead 25323f0703cSBryan Whitehead #define INT_VEC_MAP2 (0x7A8) 25423f0703cSBryan Whitehead 25523f0703cSBryan Whitehead #define INT_MOD_MAP0 (0x7B0) 25623f0703cSBryan Whitehead 25723f0703cSBryan Whitehead #define INT_MOD_MAP1 (0x7B4) 25823f0703cSBryan Whitehead 25923f0703cSBryan Whitehead #define INT_MOD_MAP2 (0x7B8) 26023f0703cSBryan Whitehead 26123f0703cSBryan Whitehead #define INT_MOD_CFG0 (0x7C0) 26223f0703cSBryan Whitehead #define INT_MOD_CFG1 (0x7C4) 26323f0703cSBryan Whitehead #define INT_MOD_CFG2 (0x7C8) 26423f0703cSBryan Whitehead #define INT_MOD_CFG3 (0x7CC) 26523f0703cSBryan Whitehead #define INT_MOD_CFG4 (0x7D0) 26623f0703cSBryan Whitehead #define INT_MOD_CFG5 (0x7D4) 26723f0703cSBryan Whitehead #define INT_MOD_CFG6 (0x7D8) 26823f0703cSBryan Whitehead #define INT_MOD_CFG7 (0x7DC) 26923f0703cSBryan Whitehead 27007624df1SBryan Whitehead #define PTP_CMD_CTL (0x0A00) 27107624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 27207624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 27307624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 27407624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 27507624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 27607624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 27707624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 27807624df1SBryan Whitehead #define PTP_GENERAL_CONFIG (0x0A04) 27907624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 28007624df1SBryan Whitehead (0x7 << (1 + ((channel) << 2))) 28107624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 28207624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 28307624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 28407624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 28507624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 28607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 2874ece1ae4SYuiko Oshino #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) 28807624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 28907624df1SBryan Whitehead (((value) & 0x7) << (1 + ((channel) << 2))) 29007624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 29107624df1SBryan Whitehead 29207624df1SBryan Whitehead #define PTP_INT_STS (0x0A08) 29307624df1SBryan Whitehead #define PTP_INT_EN_SET (0x0A0C) 29407624df1SBryan Whitehead #define PTP_INT_EN_CLR (0x0A10) 29507624df1SBryan Whitehead #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 29607624df1SBryan Whitehead #define PTP_INT_BIT_TX_TS_ BIT(12) 29707624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_B_ BIT(1) 29807624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_A_ BIT(0) 29907624df1SBryan Whitehead 30007624df1SBryan Whitehead #define PTP_CLOCK_SEC (0x0A14) 30107624df1SBryan Whitehead #define PTP_CLOCK_NS (0x0A18) 30207624df1SBryan Whitehead #define PTP_CLOCK_SUBNS (0x0A1C) 30307624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ (0x0A20) 30407624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 30507624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ (0x0A2C) 30607624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 30707624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 30807624df1SBryan Whitehead #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 30907624df1SBryan Whitehead #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 31007624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 31107624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 31207624df1SBryan Whitehead #define PTP_LATENCY (0x0A5C) 31307624df1SBryan Whitehead #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 31407624df1SBryan Whitehead #define PTP_LATENCY_RX_SET_(rx_latency) \ 31507624df1SBryan Whitehead (((u32)(rx_latency)) & 0x0000FFFF) 31607624df1SBryan Whitehead #define PTP_CAP_INFO (0x0A60) 31707624df1SBryan Whitehead #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 31807624df1SBryan Whitehead 31907624df1SBryan Whitehead #define PTP_TX_MOD (0x0AA4) 32007624df1SBryan Whitehead #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 32107624df1SBryan Whitehead 32207624df1SBryan Whitehead #define PTP_TX_MOD2 (0x0AA8) 32307624df1SBryan Whitehead #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 32407624df1SBryan Whitehead 32507624df1SBryan Whitehead #define PTP_TX_EGRESS_SEC (0x0AAC) 32607624df1SBryan Whitehead #define PTP_TX_EGRESS_NS (0x0AB0) 32707624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 32807624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 32907624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 33007624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 33107624df1SBryan Whitehead 33207624df1SBryan Whitehead #define PTP_TX_MSG_HEADER (0x0AB4) 33307624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 33407624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 33507624df1SBryan Whitehead 33623f0703cSBryan Whitehead #define DMAC_CFG (0xC00) 33723f0703cSBryan Whitehead #define DMAC_CFG_COAL_EN_ BIT(16) 33823f0703cSBryan Whitehead #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 33923f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 34023f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 34123f0703cSBryan Whitehead ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 34223f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 34323f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 34423f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 34523f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 34623f0703cSBryan Whitehead 34723f0703cSBryan Whitehead #define DMAC_COAL_CFG (0xC04) 34823f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 34923f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 35023f0703cSBryan Whitehead ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 35123f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 35223f0703cSBryan Whitehead #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 35323f0703cSBryan Whitehead #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 35423f0703cSBryan Whitehead #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 35523f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 35623f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 35723f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 35823f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 35923f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 36023f0703cSBryan Whitehead (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 36123f0703cSBryan Whitehead 36223f0703cSBryan Whitehead #define DMAC_OBFF_CFG (0xC08) 36323f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 36423f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_SET_(val) \ 36523f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 36623f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 36723f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_SET_(val) \ 36823f0703cSBryan Whitehead (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 36923f0703cSBryan Whitehead 37023f0703cSBryan Whitehead #define DMAC_CMD (0xC0C) 37123f0703cSBryan Whitehead #define DMAC_CMD_SWR_ BIT(31) 37223f0703cSBryan Whitehead #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 37323f0703cSBryan Whitehead #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 37423f0703cSBryan Whitehead #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 37523f0703cSBryan Whitehead #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 37623f0703cSBryan Whitehead #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 37723f0703cSBryan Whitehead #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 37823f0703cSBryan Whitehead 37923f0703cSBryan Whitehead #define DMAC_INT_STS (0xC10) 38023f0703cSBryan Whitehead #define DMAC_INT_EN_SET (0xC14) 38123f0703cSBryan Whitehead #define DMAC_INT_EN_CLR (0xC18) 38223f0703cSBryan Whitehead #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 38323f0703cSBryan Whitehead #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 38423f0703cSBryan Whitehead 38523f0703cSBryan Whitehead #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 38623f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 38723f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 38823f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 38923f0703cSBryan Whitehead ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 39023f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 39123f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 39223f0703cSBryan Whitehead ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 39323f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 39423f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 39523f0703cSBryan Whitehead ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 39623f0703cSBryan Whitehead #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 39723f0703cSBryan Whitehead 39823f0703cSBryan Whitehead #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 39923f0703cSBryan Whitehead #define RX_CFG_B_TS_ALL_RX_ BIT(29) 40023f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 40123f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_0_ (0x00000000) 40223f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_2_ (0x02000000) 40323f0703cSBryan Whitehead #define RX_CFG_B_RDMABL_512_ (0x00040000) 40423f0703cSBryan Whitehead #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 40523f0703cSBryan Whitehead 40623f0703cSBryan Whitehead #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 40723f0703cSBryan Whitehead 40823f0703cSBryan Whitehead #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 40923f0703cSBryan Whitehead 41023f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 41123f0703cSBryan Whitehead 41223f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 41323f0703cSBryan Whitehead 41423f0703cSBryan Whitehead #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 41523f0703cSBryan Whitehead 41623f0703cSBryan Whitehead #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 41723f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 41823f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 41923f0703cSBryan Whitehead 42023f0703cSBryan Whitehead #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 42123f0703cSBryan Whitehead #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 42223f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 42323f0703cSBryan Whitehead #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 42423f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 42523f0703cSBryan Whitehead 42623f0703cSBryan Whitehead #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 42723f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 42823f0703cSBryan Whitehead #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 42923f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 43023f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 43123f0703cSBryan Whitehead ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 43223f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 43323f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 43423f0703cSBryan Whitehead ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 43523f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 43623f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 43723f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 43823f0703cSBryan Whitehead (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 43923f0703cSBryan Whitehead 44023f0703cSBryan Whitehead #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 44123f0703cSBryan Whitehead #define TX_CFG_B_TDMABL_512_ (0x00040000) 44223f0703cSBryan Whitehead #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 44323f0703cSBryan Whitehead 44423f0703cSBryan Whitehead #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 44523f0703cSBryan Whitehead 44623f0703cSBryan Whitehead #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 44723f0703cSBryan Whitehead 44823f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 44923f0703cSBryan Whitehead 45023f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 45123f0703cSBryan Whitehead 45223f0703cSBryan Whitehead #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 45323f0703cSBryan Whitehead 45423f0703cSBryan Whitehead #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 45523f0703cSBryan Whitehead #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 45623f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 45723f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 45823f0703cSBryan Whitehead 45923f0703cSBryan Whitehead #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 46023f0703cSBryan Whitehead #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 46123f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 46223f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 46323f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 46423f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 46523f0703cSBryan Whitehead 46669584604SBryan Whitehead #define OTP_PWR_DN (0x1000) 46769584604SBryan Whitehead #define OTP_PWR_DN_PWRDN_N_ BIT(0) 46869584604SBryan Whitehead 469662a14d0SBryan Whitehead #define OTP_ADDR_HIGH (0x1004) 470662a14d0SBryan Whitehead #define OTP_ADDR_LOW (0x1008) 47169584604SBryan Whitehead 47269584604SBryan Whitehead #define OTP_PRGM_DATA (0x1010) 47369584604SBryan Whitehead 47469584604SBryan Whitehead #define OTP_PRGM_MODE (0x1014) 47569584604SBryan Whitehead #define OTP_PRGM_MODE_BYTE_ BIT(0) 47669584604SBryan Whitehead 477662a14d0SBryan Whitehead #define OTP_READ_DATA (0x1018) 478662a14d0SBryan Whitehead 479662a14d0SBryan Whitehead #define OTP_FUNC_CMD (0x1020) 480662a14d0SBryan Whitehead #define OTP_FUNC_CMD_READ_ BIT(0) 481662a14d0SBryan Whitehead 48269584604SBryan Whitehead #define OTP_TST_CMD (0x1024) 48369584604SBryan Whitehead #define OTP_TST_CMD_PRGVRFY_ BIT(3) 48469584604SBryan Whitehead 48569584604SBryan Whitehead #define OTP_CMD_GO (0x1028) 48669584604SBryan Whitehead #define OTP_CMD_GO_GO_ BIT(0) 48769584604SBryan Whitehead 48869584604SBryan Whitehead #define OTP_STATUS (0x1030) 48969584604SBryan Whitehead #define OTP_STATUS_BUSY_ BIT(0) 49069584604SBryan Whitehead 49123f0703cSBryan Whitehead /* MAC statistics registers */ 49223f0703cSBryan Whitehead #define STAT_RX_FCS_ERRORS (0x1200) 49323f0703cSBryan Whitehead #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 4948114e8a2SBryan Whitehead #define STAT_RX_FRAGMENT_ERRORS (0x1208) 49523f0703cSBryan Whitehead #define STAT_RX_JABBER_ERRORS (0x120C) 49623f0703cSBryan Whitehead #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 49723f0703cSBryan Whitehead #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 49823f0703cSBryan Whitehead #define STAT_RX_DROPPED_FRAMES (0x1218) 49923f0703cSBryan Whitehead #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 50023f0703cSBryan Whitehead #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 50123f0703cSBryan Whitehead #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 5028114e8a2SBryan Whitehead #define STAT_RX_UNICAST_FRAMES (0x1228) 5038114e8a2SBryan Whitehead #define STAT_RX_BROADCAST_FRAMES (0x122C) 50423f0703cSBryan Whitehead #define STAT_RX_MULTICAST_FRAMES (0x1230) 5058114e8a2SBryan Whitehead #define STAT_RX_PAUSE_FRAMES (0x1234) 5068114e8a2SBryan Whitehead #define STAT_RX_64_BYTE_FRAMES (0x1238) 5078114e8a2SBryan Whitehead #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 5088114e8a2SBryan Whitehead #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 5098114e8a2SBryan Whitehead #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 5108114e8a2SBryan Whitehead #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 5118114e8a2SBryan Whitehead #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 5128114e8a2SBryan Whitehead #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 51323f0703cSBryan Whitehead #define STAT_RX_TOTAL_FRAMES (0x1254) 5148114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 5158114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TIME (0x125C) 5168114e8a2SBryan Whitehead #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 51723f0703cSBryan Whitehead 51823f0703cSBryan Whitehead #define STAT_TX_FCS_ERRORS (0x1280) 51923f0703cSBryan Whitehead #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 52023f0703cSBryan Whitehead #define STAT_TX_CARRIER_ERRORS (0x1288) 5218114e8a2SBryan Whitehead #define STAT_TX_BAD_BYTE_COUNT (0x128C) 52223f0703cSBryan Whitehead #define STAT_TX_SINGLE_COLLISIONS (0x1290) 52323f0703cSBryan Whitehead #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 52423f0703cSBryan Whitehead #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 52523f0703cSBryan Whitehead #define STAT_TX_LATE_COLLISIONS (0x129C) 52623f0703cSBryan Whitehead #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 52723f0703cSBryan Whitehead #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 52823f0703cSBryan Whitehead #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 5298114e8a2SBryan Whitehead #define STAT_TX_UNICAST_FRAMES (0x12AC) 5308114e8a2SBryan Whitehead #define STAT_TX_BROADCAST_FRAMES (0x12B0) 53123f0703cSBryan Whitehead #define STAT_TX_MULTICAST_FRAMES (0x12B4) 5328114e8a2SBryan Whitehead #define STAT_TX_PAUSE_FRAMES (0x12B8) 5338114e8a2SBryan Whitehead #define STAT_TX_64_BYTE_FRAMES (0x12BC) 5348114e8a2SBryan Whitehead #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 5358114e8a2SBryan Whitehead #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 5368114e8a2SBryan Whitehead #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 5378114e8a2SBryan Whitehead #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 5388114e8a2SBryan Whitehead #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 5398114e8a2SBryan Whitehead #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 54023f0703cSBryan Whitehead #define STAT_TX_TOTAL_FRAMES (0x12D8) 5418114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 5428114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TIME (0x12E0) 5438114e8a2SBryan Whitehead #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 54423f0703cSBryan Whitehead 54523f0703cSBryan Whitehead /* End of Register definitions */ 54623f0703cSBryan Whitehead 54723f0703cSBryan Whitehead #define LAN743X_MAX_RX_CHANNELS (4) 54823f0703cSBryan Whitehead #define LAN743X_MAX_TX_CHANNELS (1) 549*cf9aaea8SRaju Lakkaraju #define PCI11X1X_MAX_TX_CHANNELS (4) 55023f0703cSBryan Whitehead struct lan743x_adapter; 55123f0703cSBryan Whitehead 55223f0703cSBryan Whitehead #define LAN743X_USED_RX_CHANNELS (4) 55323f0703cSBryan Whitehead #define LAN743X_USED_TX_CHANNELS (1) 554*cf9aaea8SRaju Lakkaraju #define PCI11X1X_USED_TX_CHANNELS (4) 55523f0703cSBryan Whitehead #define LAN743X_INT_MOD (400) 55623f0703cSBryan Whitehead 55723f0703cSBryan Whitehead #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 55823f0703cSBryan Whitehead #error Invalid LAN743X_USED_RX_CHANNELS 55923f0703cSBryan Whitehead #endif 56023f0703cSBryan Whitehead #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 56123f0703cSBryan Whitehead #error Invalid LAN743X_USED_TX_CHANNELS 56223f0703cSBryan Whitehead #endif 563*cf9aaea8SRaju Lakkaraju #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS) 564*cf9aaea8SRaju Lakkaraju #error Invalid PCI11X1X_USED_TX_CHANNELS 565*cf9aaea8SRaju Lakkaraju #endif 56623f0703cSBryan Whitehead 56723f0703cSBryan Whitehead /* PCI */ 56823f0703cSBryan Whitehead /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 56923f0703cSBryan Whitehead #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 57023f0703cSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 5714df5ce9bSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) 572bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A011 (0xA011) 573bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A041 (0xA041) 57423f0703cSBryan Whitehead 57523f0703cSBryan Whitehead #define PCI_CONFIG_LENGTH (0x1000) 57623f0703cSBryan Whitehead 57723f0703cSBryan Whitehead /* CSR */ 57823f0703cSBryan Whitehead #define CSR_LENGTH (0x2000) 57923f0703cSBryan Whitehead 58023f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 58123f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 58223f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 58323f0703cSBryan Whitehead 58423f0703cSBryan Whitehead struct lan743x_csr { 58523f0703cSBryan Whitehead u32 flags; 58623f0703cSBryan Whitehead u8 __iomem *csr_address; 58723f0703cSBryan Whitehead u32 id_rev; 58823f0703cSBryan Whitehead u32 fpga_rev; 58923f0703cSBryan Whitehead }; 59023f0703cSBryan Whitehead 59123f0703cSBryan Whitehead /* INTERRUPTS */ 59223f0703cSBryan Whitehead typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 59323f0703cSBryan Whitehead 59423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 59523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 59623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 59723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 59823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 59923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 60023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 60123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 60223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 60323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 60423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 60523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 60623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 60723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 60823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 60923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 61023f0703cSBryan Whitehead 61123f0703cSBryan Whitehead struct lan743x_vector { 61223f0703cSBryan Whitehead int irq; 61323f0703cSBryan Whitehead u32 flags; 61423f0703cSBryan Whitehead struct lan743x_adapter *adapter; 61523f0703cSBryan Whitehead int vector_index; 61623f0703cSBryan Whitehead u32 int_mask; 61723f0703cSBryan Whitehead lan743x_vector_handler handler; 61823f0703cSBryan Whitehead void *context; 61923f0703cSBryan Whitehead }; 62023f0703cSBryan Whitehead 62123f0703cSBryan Whitehead #define LAN743X_MAX_VECTOR_COUNT (8) 62223f0703cSBryan Whitehead 62323f0703cSBryan Whitehead struct lan743x_intr { 62423f0703cSBryan Whitehead int flags; 62523f0703cSBryan Whitehead 62623f0703cSBryan Whitehead unsigned int irq; 62723f0703cSBryan Whitehead 62823f0703cSBryan Whitehead struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT]; 62923f0703cSBryan Whitehead int number_of_vectors; 63023f0703cSBryan Whitehead bool using_vectors; 63123f0703cSBryan Whitehead 632470dfd80SSven Van Asbroeck bool software_isr_flag; 633470dfd80SSven Van Asbroeck wait_queue_head_t software_isr_wq; 63423f0703cSBryan Whitehead }; 63523f0703cSBryan Whitehead 63623f0703cSBryan Whitehead #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 63723f0703cSBryan Whitehead 63823f0703cSBryan Whitehead /* PHY */ 63923f0703cSBryan Whitehead struct lan743x_phy { 64023f0703cSBryan Whitehead bool fc_autoneg; 64123f0703cSBryan Whitehead u8 fc_request_control; 64223f0703cSBryan Whitehead }; 64323f0703cSBryan Whitehead 64423f0703cSBryan Whitehead /* TX */ 64523f0703cSBryan Whitehead struct lan743x_tx_descriptor; 64623f0703cSBryan Whitehead struct lan743x_tx_buffer_info; 64723f0703cSBryan Whitehead 64823f0703cSBryan Whitehead #define GPIO_QUEUE_STARTED (0) 64923f0703cSBryan Whitehead #define GPIO_TX_FUNCTION (1) 65023f0703cSBryan Whitehead #define GPIO_TX_COMPLETION (2) 65123f0703cSBryan Whitehead #define GPIO_TX_FRAGMENT (3) 65223f0703cSBryan Whitehead 65323f0703cSBryan Whitehead #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 65423f0703cSBryan Whitehead 65507624df1SBryan Whitehead #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 65607624df1SBryan Whitehead #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 65707624df1SBryan Whitehead 65823f0703cSBryan Whitehead struct lan743x_tx { 65923f0703cSBryan Whitehead struct lan743x_adapter *adapter; 66007624df1SBryan Whitehead u32 ts_flags; 66123f0703cSBryan Whitehead u32 vector_flags; 66223f0703cSBryan Whitehead int channel_number; 66323f0703cSBryan Whitehead 66423f0703cSBryan Whitehead int ring_size; 66523f0703cSBryan Whitehead size_t ring_allocation_size; 66623f0703cSBryan Whitehead struct lan743x_tx_descriptor *ring_cpu_ptr; 66723f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 66823f0703cSBryan Whitehead /* ring_lock: used to prevent concurrent access to tx ring */ 66923f0703cSBryan Whitehead spinlock_t ring_lock; 67023f0703cSBryan Whitehead u32 frame_flags; 67123f0703cSBryan Whitehead u32 frame_first; 67223f0703cSBryan Whitehead u32 frame_data0; 67323f0703cSBryan Whitehead u32 frame_tail; 67423f0703cSBryan Whitehead 67523f0703cSBryan Whitehead struct lan743x_tx_buffer_info *buffer_info; 67623f0703cSBryan Whitehead 67746251282SAlexey Denisov __le32 *head_cpu_ptr; 67823f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 67923f0703cSBryan Whitehead int last_head; 68023f0703cSBryan Whitehead int last_tail; 68123f0703cSBryan Whitehead 68223f0703cSBryan Whitehead struct napi_struct napi; 68323f0703cSBryan Whitehead 68423f0703cSBryan Whitehead struct sk_buff *overflow_skb; 68523f0703cSBryan Whitehead }; 68623f0703cSBryan Whitehead 68707624df1SBryan Whitehead void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 68807624df1SBryan Whitehead bool enable_timestamping, 68907624df1SBryan Whitehead bool enable_onestep_sync); 69007624df1SBryan Whitehead 69123f0703cSBryan Whitehead /* RX */ 69223f0703cSBryan Whitehead struct lan743x_rx_descriptor; 69323f0703cSBryan Whitehead struct lan743x_rx_buffer_info; 69423f0703cSBryan Whitehead 69523f0703cSBryan Whitehead struct lan743x_rx { 69623f0703cSBryan Whitehead struct lan743x_adapter *adapter; 69723f0703cSBryan Whitehead u32 vector_flags; 69823f0703cSBryan Whitehead int channel_number; 69923f0703cSBryan Whitehead 70023f0703cSBryan Whitehead int ring_size; 70123f0703cSBryan Whitehead size_t ring_allocation_size; 70223f0703cSBryan Whitehead struct lan743x_rx_descriptor *ring_cpu_ptr; 70323f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 70423f0703cSBryan Whitehead 70523f0703cSBryan Whitehead struct lan743x_rx_buffer_info *buffer_info; 70623f0703cSBryan Whitehead 70746251282SAlexey Denisov __le32 *head_cpu_ptr; 70823f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 70923f0703cSBryan Whitehead u32 last_head; 71023f0703cSBryan Whitehead u32 last_tail; 71123f0703cSBryan Whitehead 71223f0703cSBryan Whitehead struct napi_struct napi; 71323f0703cSBryan Whitehead 71423f0703cSBryan Whitehead u32 frame_count; 715a8db76d4SSven Van Asbroeck 716a8db76d4SSven Van Asbroeck struct sk_buff *skb_head, *skb_tail; 71723f0703cSBryan Whitehead }; 71823f0703cSBryan Whitehead 71923f0703cSBryan Whitehead struct lan743x_adapter { 72023f0703cSBryan Whitehead struct net_device *netdev; 72123f0703cSBryan Whitehead struct mii_bus *mdiobus; 72223f0703cSBryan Whitehead int msg_enable; 7234d94282aSBryan Whitehead #ifdef CONFIG_PM 7244d94282aSBryan Whitehead u32 wolopts; 7254d94282aSBryan Whitehead #endif 72623f0703cSBryan Whitehead struct pci_dev *pdev; 72723f0703cSBryan Whitehead struct lan743x_csr csr; 72823f0703cSBryan Whitehead struct lan743x_intr intr; 72923f0703cSBryan Whitehead 73007624df1SBryan Whitehead struct lan743x_gpio gpio; 73107624df1SBryan Whitehead struct lan743x_ptp ptp; 73207624df1SBryan Whitehead 73323f0703cSBryan Whitehead u8 mac_address[ETH_ALEN]; 73423f0703cSBryan Whitehead 73523f0703cSBryan Whitehead struct lan743x_phy phy; 736*cf9aaea8SRaju Lakkaraju struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS]; 737*cf9aaea8SRaju Lakkaraju struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; 738*cf9aaea8SRaju Lakkaraju bool is_pci11x1x; 739*cf9aaea8SRaju Lakkaraju u8 max_tx_channels; 740*cf9aaea8SRaju Lakkaraju u8 used_tx_channels; 741662a14d0SBryan Whitehead 742662a14d0SBryan Whitehead #define LAN743X_ADAPTER_FLAG_OTP BIT(0) 743662a14d0SBryan Whitehead u32 flags; 74423f0703cSBryan Whitehead }; 74523f0703cSBryan Whitehead 74623f0703cSBryan Whitehead #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 74723f0703cSBryan Whitehead 74823f0703cSBryan Whitehead #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 74923f0703cSBryan Whitehead #define INTR_FLAG_MSI_ENABLED BIT(8) 75023f0703cSBryan Whitehead #define INTR_FLAG_MSIX_ENABLED BIT(9) 75123f0703cSBryan Whitehead 75223f0703cSBryan Whitehead #define MAC_MII_READ 1 75323f0703cSBryan Whitehead #define MAC_MII_WRITE 0 75423f0703cSBryan Whitehead 75523f0703cSBryan Whitehead #define PHY_FLAG_OPENED BIT(0) 75623f0703cSBryan Whitehead #define PHY_FLAG_ATTACHED BIT(1) 75723f0703cSBryan Whitehead 75823f0703cSBryan Whitehead #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 75923f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 76023f0703cSBryan Whitehead #else 76123f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 76223f0703cSBryan Whitehead #endif 76323f0703cSBryan Whitehead #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 76423f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_16 (16) 76523f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_32 (32) 76623f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_64 (64) 76723f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_128 (128) 76823f0703cSBryan Whitehead #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 76923f0703cSBryan Whitehead 77023f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 77123f0703cSBryan Whitehead (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 77223f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 77323f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 77423f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 77523f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 77623f0703cSBryan Whitehead 77723f0703cSBryan Whitehead /* TX Descriptor bits */ 77823f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 77923f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 78023f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 78123f0703cSBryan Whitehead #define TX_DESC_DATA0_FS_ (0x20000000) 78223f0703cSBryan Whitehead #define TX_DESC_DATA0_LS_ (0x10000000) 78323f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_ (0x08000000) 78423f0703cSBryan Whitehead #define TX_DESC_DATA0_IOC_ (0x04000000) 78523f0703cSBryan Whitehead #define TX_DESC_DATA0_ICE_ (0x00400000) 78623f0703cSBryan Whitehead #define TX_DESC_DATA0_IPE_ (0x00200000) 78723f0703cSBryan Whitehead #define TX_DESC_DATA0_TPE_ (0x00100000) 78823f0703cSBryan Whitehead #define TX_DESC_DATA0_FCS_ (0x00020000) 78907624df1SBryan Whitehead #define TX_DESC_DATA0_TSE_ (0x00010000) 79023f0703cSBryan Whitehead #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 79123f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 79223f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 79323f0703cSBryan Whitehead #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 79423f0703cSBryan Whitehead 79523f0703cSBryan Whitehead struct lan743x_tx_descriptor { 79646251282SAlexey Denisov __le32 data0; 79746251282SAlexey Denisov __le32 data1; 79846251282SAlexey Denisov __le32 data2; 79946251282SAlexey Denisov __le32 data3; 80023f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 80123f0703cSBryan Whitehead 80223f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 80307624df1SBryan Whitehead #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 80423f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 80523f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 80623f0703cSBryan Whitehead struct lan743x_tx_buffer_info { 80723f0703cSBryan Whitehead int flags; 80823f0703cSBryan Whitehead struct sk_buff *skb; 80923f0703cSBryan Whitehead dma_addr_t dma_ptr; 81023f0703cSBryan Whitehead unsigned int buffer_length; 81123f0703cSBryan Whitehead }; 81223f0703cSBryan Whitehead 81323f0703cSBryan Whitehead #define LAN743X_TX_RING_SIZE (50) 81423f0703cSBryan Whitehead 81523f0703cSBryan Whitehead /* OWN bit is set. ie, Descs are owned by RX DMAC */ 81623f0703cSBryan Whitehead #define RX_DESC_DATA0_OWN_ (0x00008000) 81723f0703cSBryan Whitehead /* OWN bit is clear. ie, Descs are owned by host */ 81823f0703cSBryan Whitehead #define RX_DESC_DATA0_FS_ (0x80000000) 81923f0703cSBryan Whitehead #define RX_DESC_DATA0_LS_ (0x40000000) 82023f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 82123f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 82223f0703cSBryan Whitehead (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 82323f0703cSBryan Whitehead #define RX_DESC_DATA0_EXT_ (0x00004000) 82423f0703cSBryan Whitehead #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 82523f0703cSBryan Whitehead #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 82623f0703cSBryan Whitehead 82723f0703cSBryan Whitehead #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 82823f0703cSBryan Whitehead #error NET_IP_ALIGN must be 0 or 2 82923f0703cSBryan Whitehead #endif 83023f0703cSBryan Whitehead 83123f0703cSBryan Whitehead #define RX_HEAD_PADDING NET_IP_ALIGN 83223f0703cSBryan Whitehead 83323f0703cSBryan Whitehead struct lan743x_rx_descriptor { 83446251282SAlexey Denisov __le32 data0; 83546251282SAlexey Denisov __le32 data1; 83646251282SAlexey Denisov __le32 data2; 83746251282SAlexey Denisov __le32 data3; 83823f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 83923f0703cSBryan Whitehead 84023f0703cSBryan Whitehead #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 84123f0703cSBryan Whitehead struct lan743x_rx_buffer_info { 84223f0703cSBryan Whitehead int flags; 84323f0703cSBryan Whitehead struct sk_buff *skb; 84423f0703cSBryan Whitehead 84523f0703cSBryan Whitehead dma_addr_t dma_ptr; 84623f0703cSBryan Whitehead unsigned int buffer_length; 84723f0703cSBryan Whitehead }; 84823f0703cSBryan Whitehead 849a1f16275SYuiko Oshino #define LAN743X_RX_RING_SIZE (128) 85023f0703cSBryan Whitehead 85123f0703cSBryan Whitehead #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 852a8db76d4SSven Van Asbroeck #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) 85323f0703cSBryan Whitehead 8548114e8a2SBryan Whitehead u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 8558114e8a2SBryan Whitehead void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 8568114e8a2SBryan Whitehead 85723f0703cSBryan Whitehead #endif /* _LAN743X_H */ 858