123f0703cSBryan Whitehead /* SPDX-License-Identifier: GPL-2.0+ */ 223f0703cSBryan Whitehead /* Copyright (C) 2018 Microchip Technology Inc. */ 323f0703cSBryan Whitehead 423f0703cSBryan Whitehead #ifndef _LAN743X_H 523f0703cSBryan Whitehead #define _LAN743X_H 623f0703cSBryan Whitehead 76f197fb6SRoelof Berg #include <linux/phy.h> 807624df1SBryan Whitehead #include "lan743x_ptp.h" 907624df1SBryan Whitehead 1023f0703cSBryan Whitehead #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 1123f0703cSBryan Whitehead #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 1223f0703cSBryan Whitehead #define DRIVER_NAME "lan743x" 1323f0703cSBryan Whitehead 1423f0703cSBryan Whitehead /* Register Definitions */ 1523f0703cSBryan Whitehead #define ID_REV (0x00) 1607624df1SBryan Whitehead #define ID_REV_ID_MASK_ (0xFFFF0000) 1707624df1SBryan Whitehead #define ID_REV_ID_LAN7430_ (0x74300000) 1807624df1SBryan Whitehead #define ID_REV_ID_LAN7431_ (0x74310000) 19bb4f6bffSRaju Lakkaraju #define ID_REV_ID_LAN743X_ (0x74300000) 20bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 21bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 22bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A0X1_ (0xA0010000) 2323f0703cSBryan Whitehead #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 24bb4f6bffSRaju Lakkaraju ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ 25bb4f6bffSRaju Lakkaraju (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) 2623f0703cSBryan Whitehead #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 2723f0703cSBryan Whitehead #define ID_REV_CHIP_REV_A0_ (0x00000000) 2823f0703cSBryan Whitehead #define ID_REV_CHIP_REV_B0_ (0x00000010) 2923f0703cSBryan Whitehead 3023f0703cSBryan Whitehead #define FPGA_REV (0x04) 3123f0703cSBryan Whitehead #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 3223f0703cSBryan Whitehead #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 33*a46d9d37SRaju Lakkaraju #define FPGA_SGMII_OP BIT(24) 34*a46d9d37SRaju Lakkaraju 35*a46d9d37SRaju Lakkaraju #define STRAP_READ (0x0C) 36*a46d9d37SRaju Lakkaraju #define STRAP_READ_USE_SGMII_EN_ BIT(22) 37*a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_EN_ BIT(6) 38*a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_REFCLK_ BIT(5) 39*a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_2_5G_ BIT(4) 40*a46d9d37SRaju Lakkaraju #define STRAP_READ_BASE_X_ BIT(3) 41*a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2) 42*a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1) 43*a46d9d37SRaju Lakkaraju #define STRAP_READ_ADV_PM_DISABLE_ BIT(0) 4423f0703cSBryan Whitehead 4523f0703cSBryan Whitehead #define HW_CFG (0x010) 46662a14d0SBryan Whitehead #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) 47662a14d0SBryan Whitehead #define HW_CFG_EE_OTP_RELOAD_ BIT(4) 4823f0703cSBryan Whitehead #define HW_CFG_LRST_ BIT(1) 4923f0703cSBryan Whitehead 5023f0703cSBryan Whitehead #define PMT_CTL (0x014) 514d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 524d94282aSBryan Whitehead #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 534d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 544d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 554d94282aSBryan Whitehead #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 564d94282aSBryan Whitehead #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 574d94282aSBryan Whitehead #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 5823f0703cSBryan Whitehead #define PMT_CTL_READY_ BIT(7) 5923f0703cSBryan Whitehead #define PMT_CTL_ETH_PHY_RST_ BIT(4) 604d94282aSBryan Whitehead #define PMT_CTL_WOL_EN_ BIT(3) 614d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 624d94282aSBryan Whitehead #define PMT_CTL_WUPS_MASK_ (0x00000003) 6323f0703cSBryan Whitehead 6423f0703cSBryan Whitehead #define DP_SEL (0x024) 6523f0703cSBryan Whitehead #define DP_SEL_DPRDY_ BIT(31) 6623f0703cSBryan Whitehead #define DP_SEL_MASK_ (0x0000001F) 6723f0703cSBryan Whitehead #define DP_SEL_RFE_RAM (0x00000001) 6823f0703cSBryan Whitehead 6923f0703cSBryan Whitehead #define DP_SEL_VHF_HASH_LEN (16) 7023f0703cSBryan Whitehead #define DP_SEL_VHF_VLAN_LEN (128) 7123f0703cSBryan Whitehead 7223f0703cSBryan Whitehead #define DP_CMD (0x028) 7323f0703cSBryan Whitehead #define DP_CMD_WRITE_ (0x00000001) 7423f0703cSBryan Whitehead 7523f0703cSBryan Whitehead #define DP_ADDR (0x02C) 7623f0703cSBryan Whitehead 7723f0703cSBryan Whitehead #define DP_DATA_0 (0x030) 7823f0703cSBryan Whitehead 7969584604SBryan Whitehead #define E2P_CMD (0x040) 8069584604SBryan Whitehead #define E2P_CMD_EPC_BUSY_ BIT(31) 8169584604SBryan Whitehead #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 8269584604SBryan Whitehead #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 8369584604SBryan Whitehead #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 8469584604SBryan Whitehead #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 8569584604SBryan Whitehead #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 8669584604SBryan Whitehead 8769584604SBryan Whitehead #define E2P_DATA (0x044) 8869584604SBryan Whitehead 8907624df1SBryan Whitehead #define GPIO_CFG0 (0x050) 9007624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 9107624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 9207624df1SBryan Whitehead 9307624df1SBryan Whitehead #define GPIO_CFG1 (0x054) 9407624df1SBryan Whitehead #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 9507624df1SBryan Whitehead #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 9607624df1SBryan Whitehead 9707624df1SBryan Whitehead #define GPIO_CFG2 (0x058) 9807624df1SBryan Whitehead #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 9907624df1SBryan Whitehead 10007624df1SBryan Whitehead #define GPIO_CFG3 (0x05C) 10107624df1SBryan Whitehead #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 10207624df1SBryan Whitehead #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 10307624df1SBryan Whitehead 10423f0703cSBryan Whitehead #define FCT_RX_CTL (0xAC) 10523f0703cSBryan Whitehead #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 10623f0703cSBryan Whitehead #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 10723f0703cSBryan Whitehead #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 10823f0703cSBryan Whitehead 10923f0703cSBryan Whitehead #define FCT_TX_CTL (0xC4) 11023f0703cSBryan Whitehead #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 11123f0703cSBryan Whitehead #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 11223f0703cSBryan Whitehead #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 11323f0703cSBryan Whitehead 11423f0703cSBryan Whitehead #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 11523f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 11623f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 11723f0703cSBryan Whitehead ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 11823f0703cSBryan Whitehead #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 11923f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 12023f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 12123f0703cSBryan Whitehead ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 12223f0703cSBryan Whitehead 12323f0703cSBryan Whitehead #define MAC_CR (0x100) 1246f197fb6SRoelof Berg #define MAC_CR_MII_EN_ BIT(19) 125c9cf96bbSBryan Whitehead #define MAC_CR_EEE_EN_ BIT(17) 12623f0703cSBryan Whitehead #define MAC_CR_ADD_ BIT(12) 12723f0703cSBryan Whitehead #define MAC_CR_ASD_ BIT(11) 12823f0703cSBryan Whitehead #define MAC_CR_CNTR_RST_ BIT(5) 1296f197fb6SRoelof Berg #define MAC_CR_DPX_ BIT(3) 1306f197fb6SRoelof Berg #define MAC_CR_CFG_H_ BIT(2) 1316f197fb6SRoelof Berg #define MAC_CR_CFG_L_ BIT(1) 13223f0703cSBryan Whitehead #define MAC_CR_RST_ BIT(0) 13323f0703cSBryan Whitehead 13423f0703cSBryan Whitehead #define MAC_RX (0x104) 13523f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_SHIFT_ (16) 13623f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 13723f0703cSBryan Whitehead #define MAC_RX_RXD_ BIT(1) 13823f0703cSBryan Whitehead #define MAC_RX_RXEN_ BIT(0) 13923f0703cSBryan Whitehead 14023f0703cSBryan Whitehead #define MAC_TX (0x108) 14123f0703cSBryan Whitehead #define MAC_TX_TXD_ BIT(1) 14223f0703cSBryan Whitehead #define MAC_TX_TXEN_ BIT(0) 14323f0703cSBryan Whitehead 14423f0703cSBryan Whitehead #define MAC_FLOW (0x10C) 14523f0703cSBryan Whitehead #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 14623f0703cSBryan Whitehead #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 14723f0703cSBryan Whitehead #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 14823f0703cSBryan Whitehead 14923f0703cSBryan Whitehead #define MAC_RX_ADDRH (0x118) 15023f0703cSBryan Whitehead 15123f0703cSBryan Whitehead #define MAC_RX_ADDRL (0x11C) 15223f0703cSBryan Whitehead 15323f0703cSBryan Whitehead #define MAC_MII_ACC (0x120) 15423f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 15523f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 15623f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 15723f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 15823f0703cSBryan Whitehead #define MAC_MII_ACC_MII_READ_ (0x00000000) 15923f0703cSBryan Whitehead #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 16023f0703cSBryan Whitehead #define MAC_MII_ACC_MII_BUSY_ BIT(0) 16123f0703cSBryan Whitehead 16223f0703cSBryan Whitehead #define MAC_MII_DATA (0x124) 16323f0703cSBryan Whitehead 164c9cf96bbSBryan Whitehead #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 165c9cf96bbSBryan Whitehead 1664d94282aSBryan Whitehead #define MAC_WUCSR (0x140) 1674d94282aSBryan Whitehead #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 1684d94282aSBryan Whitehead #define MAC_WUCSR_PFDA_EN_ BIT(3) 1694d94282aSBryan Whitehead #define MAC_WUCSR_WAKE_EN_ BIT(2) 1704d94282aSBryan Whitehead #define MAC_WUCSR_MPEN_ BIT(1) 1714d94282aSBryan Whitehead #define MAC_WUCSR_BCST_EN_ BIT(0) 1724d94282aSBryan Whitehead 1734d94282aSBryan Whitehead #define MAC_WK_SRC (0x144) 1744d94282aSBryan Whitehead 1754d94282aSBryan Whitehead #define MAC_WUF_CFG0 (0x150) 1764d94282aSBryan Whitehead #define MAC_NUM_OF_WUF_CFG (32) 1774d94282aSBryan Whitehead #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 1784d94282aSBryan Whitehead #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 1794d94282aSBryan Whitehead #define MAC_WUF_CFG_EN_ BIT(31) 1804d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 1814d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 1824d94282aSBryan Whitehead #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 1834d94282aSBryan Whitehead #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 1844d94282aSBryan Whitehead 1854d94282aSBryan Whitehead #define MAC_WUF_MASK0_0 (0x200) 1864d94282aSBryan Whitehead #define MAC_WUF_MASK0_1 (0x204) 1874d94282aSBryan Whitehead #define MAC_WUF_MASK0_2 (0x208) 1884d94282aSBryan Whitehead #define MAC_WUF_MASK0_3 (0x20C) 1894d94282aSBryan Whitehead #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 1904d94282aSBryan Whitehead #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 1914d94282aSBryan Whitehead #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 1924d94282aSBryan Whitehead #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 1934d94282aSBryan Whitehead #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 1944d94282aSBryan Whitehead #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 1954d94282aSBryan Whitehead #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 1964d94282aSBryan Whitehead #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 1974d94282aSBryan Whitehead 19823f0703cSBryan Whitehead /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 19923f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 20023f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 20123f0703cSBryan Whitehead 20223f0703cSBryan Whitehead /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 20323f0703cSBryan Whitehead #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 20423f0703cSBryan Whitehead 20523f0703cSBryan Whitehead #define RFE_CTL (0x508) 20623f0703cSBryan Whitehead #define RFE_CTL_AB_ BIT(10) 20723f0703cSBryan Whitehead #define RFE_CTL_AM_ BIT(9) 20823f0703cSBryan Whitehead #define RFE_CTL_AU_ BIT(8) 20923f0703cSBryan Whitehead #define RFE_CTL_MCAST_HASH_ BIT(3) 21023f0703cSBryan Whitehead #define RFE_CTL_DA_PERFECT_ BIT(1) 21123f0703cSBryan Whitehead 21243e8fe9bSBryan Whitehead #define RFE_RSS_CFG (0x554) 21343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 21443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 21543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 21643e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 21743e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 21843e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_ BIT(11) 21943e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 22043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 22143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV4_ BIT(8) 22243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 22343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 22443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 22543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 22643e8fe9bSBryan Whitehead 22743e8fe9bSBryan Whitehead #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 22843e8fe9bSBryan Whitehead 22943e8fe9bSBryan Whitehead #define RFE_INDX(index) (0x580 + (index << 2)) 23043e8fe9bSBryan Whitehead 2314d94282aSBryan Whitehead #define MAC_WUCSR2 (0x600) 2324d94282aSBryan Whitehead 233*a46d9d37SRaju Lakkaraju #define SGMII_CTL (0x728) 234*a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_ENABLE_ BIT(31) 235*a46d9d37SRaju Lakkaraju #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8) 236*a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_POWER_DN_ BIT(1) 237*a46d9d37SRaju Lakkaraju 23823f0703cSBryan Whitehead #define INT_STS (0x780) 23923f0703cSBryan Whitehead #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 24023f0703cSBryan Whitehead #define INT_BIT_ALL_RX_ (0x0F000000) 24123f0703cSBryan Whitehead #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 24223f0703cSBryan Whitehead #define INT_BIT_ALL_TX_ (0x000F0000) 24323f0703cSBryan Whitehead #define INT_BIT_SW_GP_ BIT(9) 24407624df1SBryan Whitehead #define INT_BIT_1588_ BIT(7) 24507624df1SBryan Whitehead #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 24623f0703cSBryan Whitehead #define INT_BIT_MAS_ BIT(0) 24723f0703cSBryan Whitehead 24823f0703cSBryan Whitehead #define INT_SET (0x784) 24923f0703cSBryan Whitehead 25023f0703cSBryan Whitehead #define INT_EN_SET (0x788) 25123f0703cSBryan Whitehead 25223f0703cSBryan Whitehead #define INT_EN_CLR (0x78C) 25323f0703cSBryan Whitehead 25423f0703cSBryan Whitehead #define INT_STS_R2C (0x790) 25523f0703cSBryan Whitehead 25623f0703cSBryan Whitehead #define INT_VEC_EN_SET (0x794) 25723f0703cSBryan Whitehead #define INT_VEC_EN_CLR (0x798) 25823f0703cSBryan Whitehead #define INT_VEC_EN_AUTO_CLR (0x79C) 25923f0703cSBryan Whitehead #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 26023f0703cSBryan Whitehead 26123f0703cSBryan Whitehead #define INT_VEC_MAP0 (0x7A0) 26223f0703cSBryan Whitehead #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 26323f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 26423f0703cSBryan Whitehead 26523f0703cSBryan Whitehead #define INT_VEC_MAP1 (0x7A4) 26623f0703cSBryan Whitehead #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 26723f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 26823f0703cSBryan Whitehead 26923f0703cSBryan Whitehead #define INT_VEC_MAP2 (0x7A8) 27023f0703cSBryan Whitehead 27123f0703cSBryan Whitehead #define INT_MOD_MAP0 (0x7B0) 27223f0703cSBryan Whitehead 27323f0703cSBryan Whitehead #define INT_MOD_MAP1 (0x7B4) 27423f0703cSBryan Whitehead 27523f0703cSBryan Whitehead #define INT_MOD_MAP2 (0x7B8) 27623f0703cSBryan Whitehead 27723f0703cSBryan Whitehead #define INT_MOD_CFG0 (0x7C0) 27823f0703cSBryan Whitehead #define INT_MOD_CFG1 (0x7C4) 27923f0703cSBryan Whitehead #define INT_MOD_CFG2 (0x7C8) 28023f0703cSBryan Whitehead #define INT_MOD_CFG3 (0x7CC) 28123f0703cSBryan Whitehead #define INT_MOD_CFG4 (0x7D0) 28223f0703cSBryan Whitehead #define INT_MOD_CFG5 (0x7D4) 28323f0703cSBryan Whitehead #define INT_MOD_CFG6 (0x7D8) 28423f0703cSBryan Whitehead #define INT_MOD_CFG7 (0x7DC) 285ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG8 (0x7E0) 286ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG9 (0x7E4) 28723f0703cSBryan Whitehead 28807624df1SBryan Whitehead #define PTP_CMD_CTL (0x0A00) 28907624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 29007624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 29107624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 29207624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 29307624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 29407624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 29507624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 29607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG (0x0A04) 29707624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 29807624df1SBryan Whitehead (0x7 << (1 + ((channel) << 2))) 29907624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 30007624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 30107624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 30207624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 30307624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 30407624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 3054ece1ae4SYuiko Oshino #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) 30607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 30707624df1SBryan Whitehead (((value) & 0x7) << (1 + ((channel) << 2))) 30807624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 30907624df1SBryan Whitehead 31007624df1SBryan Whitehead #define PTP_INT_STS (0x0A08) 31107624df1SBryan Whitehead #define PTP_INT_EN_SET (0x0A0C) 31207624df1SBryan Whitehead #define PTP_INT_EN_CLR (0x0A10) 31307624df1SBryan Whitehead #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 31407624df1SBryan Whitehead #define PTP_INT_BIT_TX_TS_ BIT(12) 31507624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_B_ BIT(1) 31607624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_A_ BIT(0) 31707624df1SBryan Whitehead 31807624df1SBryan Whitehead #define PTP_CLOCK_SEC (0x0A14) 31907624df1SBryan Whitehead #define PTP_CLOCK_NS (0x0A18) 32007624df1SBryan Whitehead #define PTP_CLOCK_SUBNS (0x0A1C) 32107624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ (0x0A20) 32207624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 32307624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ (0x0A2C) 32407624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 32507624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 32607624df1SBryan Whitehead #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 32707624df1SBryan Whitehead #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 32807624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 32907624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 33007624df1SBryan Whitehead #define PTP_LATENCY (0x0A5C) 33107624df1SBryan Whitehead #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 33207624df1SBryan Whitehead #define PTP_LATENCY_RX_SET_(rx_latency) \ 33307624df1SBryan Whitehead (((u32)(rx_latency)) & 0x0000FFFF) 33407624df1SBryan Whitehead #define PTP_CAP_INFO (0x0A60) 33507624df1SBryan Whitehead #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 33607624df1SBryan Whitehead 33707624df1SBryan Whitehead #define PTP_TX_MOD (0x0AA4) 33807624df1SBryan Whitehead #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 33907624df1SBryan Whitehead 34007624df1SBryan Whitehead #define PTP_TX_MOD2 (0x0AA8) 34107624df1SBryan Whitehead #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 34207624df1SBryan Whitehead 34307624df1SBryan Whitehead #define PTP_TX_EGRESS_SEC (0x0AAC) 34407624df1SBryan Whitehead #define PTP_TX_EGRESS_NS (0x0AB0) 34507624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 34607624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 34707624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 34807624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 34907624df1SBryan Whitehead 35007624df1SBryan Whitehead #define PTP_TX_MSG_HEADER (0x0AB4) 35107624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 35207624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 35307624df1SBryan Whitehead 35423f0703cSBryan Whitehead #define DMAC_CFG (0xC00) 35523f0703cSBryan Whitehead #define DMAC_CFG_COAL_EN_ BIT(16) 35623f0703cSBryan Whitehead #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 35723f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 35823f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 35923f0703cSBryan Whitehead ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 36023f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 36123f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 36223f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 36323f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 36423f0703cSBryan Whitehead 36523f0703cSBryan Whitehead #define DMAC_COAL_CFG (0xC04) 36623f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 36723f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 36823f0703cSBryan Whitehead ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 36923f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 37023f0703cSBryan Whitehead #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 37123f0703cSBryan Whitehead #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 37223f0703cSBryan Whitehead #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 37323f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 37423f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 37523f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 37623f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 37723f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 37823f0703cSBryan Whitehead (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 37923f0703cSBryan Whitehead 38023f0703cSBryan Whitehead #define DMAC_OBFF_CFG (0xC08) 38123f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 38223f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_SET_(val) \ 38323f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 38423f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 38523f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_SET_(val) \ 38623f0703cSBryan Whitehead (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 38723f0703cSBryan Whitehead 38823f0703cSBryan Whitehead #define DMAC_CMD (0xC0C) 38923f0703cSBryan Whitehead #define DMAC_CMD_SWR_ BIT(31) 39023f0703cSBryan Whitehead #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 39123f0703cSBryan Whitehead #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 39223f0703cSBryan Whitehead #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 39323f0703cSBryan Whitehead #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 39423f0703cSBryan Whitehead #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 39523f0703cSBryan Whitehead #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 39623f0703cSBryan Whitehead 39723f0703cSBryan Whitehead #define DMAC_INT_STS (0xC10) 39823f0703cSBryan Whitehead #define DMAC_INT_EN_SET (0xC14) 39923f0703cSBryan Whitehead #define DMAC_INT_EN_CLR (0xC18) 40023f0703cSBryan Whitehead #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 40123f0703cSBryan Whitehead #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 40223f0703cSBryan Whitehead 40323f0703cSBryan Whitehead #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 40423f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 40523f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 40623f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 40723f0703cSBryan Whitehead ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 40823f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 40923f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 41023f0703cSBryan Whitehead ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 41123f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 41223f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 41323f0703cSBryan Whitehead ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 41423f0703cSBryan Whitehead #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 41523f0703cSBryan Whitehead 41623f0703cSBryan Whitehead #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 41723f0703cSBryan Whitehead #define RX_CFG_B_TS_ALL_RX_ BIT(29) 41823f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 41923f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_0_ (0x00000000) 42023f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_2_ (0x02000000) 42123f0703cSBryan Whitehead #define RX_CFG_B_RDMABL_512_ (0x00040000) 42223f0703cSBryan Whitehead #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 42323f0703cSBryan Whitehead 42423f0703cSBryan Whitehead #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 42523f0703cSBryan Whitehead 42623f0703cSBryan Whitehead #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 42723f0703cSBryan Whitehead 42823f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 42923f0703cSBryan Whitehead 43023f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 43123f0703cSBryan Whitehead 43223f0703cSBryan Whitehead #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 43323f0703cSBryan Whitehead 43423f0703cSBryan Whitehead #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 43523f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 43623f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 43723f0703cSBryan Whitehead 43823f0703cSBryan Whitehead #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 43923f0703cSBryan Whitehead #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 44023f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 44123f0703cSBryan Whitehead #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 44223f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 44323f0703cSBryan Whitehead 44423f0703cSBryan Whitehead #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 44523f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 44623f0703cSBryan Whitehead #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 44723f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 44823f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 44923f0703cSBryan Whitehead ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 45023f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 45123f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 45223f0703cSBryan Whitehead ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 45323f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 45423f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 45523f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 45623f0703cSBryan Whitehead (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 45723f0703cSBryan Whitehead 45823f0703cSBryan Whitehead #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 45923f0703cSBryan Whitehead #define TX_CFG_B_TDMABL_512_ (0x00040000) 46023f0703cSBryan Whitehead #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 46123f0703cSBryan Whitehead 46223f0703cSBryan Whitehead #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 46323f0703cSBryan Whitehead 46423f0703cSBryan Whitehead #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 46523f0703cSBryan Whitehead 46623f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 46723f0703cSBryan Whitehead 46823f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 46923f0703cSBryan Whitehead 47023f0703cSBryan Whitehead #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 47123f0703cSBryan Whitehead 47223f0703cSBryan Whitehead #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 47323f0703cSBryan Whitehead #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 47423f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 47523f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 47623f0703cSBryan Whitehead 47723f0703cSBryan Whitehead #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 47823f0703cSBryan Whitehead #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 47923f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 48023f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 48123f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 48223f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 48323f0703cSBryan Whitehead 48469584604SBryan Whitehead #define OTP_PWR_DN (0x1000) 48569584604SBryan Whitehead #define OTP_PWR_DN_PWRDN_N_ BIT(0) 48669584604SBryan Whitehead 487662a14d0SBryan Whitehead #define OTP_ADDR_HIGH (0x1004) 488662a14d0SBryan Whitehead #define OTP_ADDR_LOW (0x1008) 48969584604SBryan Whitehead 49069584604SBryan Whitehead #define OTP_PRGM_DATA (0x1010) 49169584604SBryan Whitehead 49269584604SBryan Whitehead #define OTP_PRGM_MODE (0x1014) 49369584604SBryan Whitehead #define OTP_PRGM_MODE_BYTE_ BIT(0) 49469584604SBryan Whitehead 495662a14d0SBryan Whitehead #define OTP_READ_DATA (0x1018) 496662a14d0SBryan Whitehead 497662a14d0SBryan Whitehead #define OTP_FUNC_CMD (0x1020) 498662a14d0SBryan Whitehead #define OTP_FUNC_CMD_READ_ BIT(0) 499662a14d0SBryan Whitehead 50069584604SBryan Whitehead #define OTP_TST_CMD (0x1024) 50169584604SBryan Whitehead #define OTP_TST_CMD_PRGVRFY_ BIT(3) 50269584604SBryan Whitehead 50369584604SBryan Whitehead #define OTP_CMD_GO (0x1028) 50469584604SBryan Whitehead #define OTP_CMD_GO_GO_ BIT(0) 50569584604SBryan Whitehead 50669584604SBryan Whitehead #define OTP_STATUS (0x1030) 50769584604SBryan Whitehead #define OTP_STATUS_BUSY_ BIT(0) 50869584604SBryan Whitehead 50923f0703cSBryan Whitehead /* MAC statistics registers */ 51023f0703cSBryan Whitehead #define STAT_RX_FCS_ERRORS (0x1200) 51123f0703cSBryan Whitehead #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 5128114e8a2SBryan Whitehead #define STAT_RX_FRAGMENT_ERRORS (0x1208) 51323f0703cSBryan Whitehead #define STAT_RX_JABBER_ERRORS (0x120C) 51423f0703cSBryan Whitehead #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 51523f0703cSBryan Whitehead #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 51623f0703cSBryan Whitehead #define STAT_RX_DROPPED_FRAMES (0x1218) 51723f0703cSBryan Whitehead #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 51823f0703cSBryan Whitehead #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 51923f0703cSBryan Whitehead #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 5208114e8a2SBryan Whitehead #define STAT_RX_UNICAST_FRAMES (0x1228) 5218114e8a2SBryan Whitehead #define STAT_RX_BROADCAST_FRAMES (0x122C) 52223f0703cSBryan Whitehead #define STAT_RX_MULTICAST_FRAMES (0x1230) 5238114e8a2SBryan Whitehead #define STAT_RX_PAUSE_FRAMES (0x1234) 5248114e8a2SBryan Whitehead #define STAT_RX_64_BYTE_FRAMES (0x1238) 5258114e8a2SBryan Whitehead #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 5268114e8a2SBryan Whitehead #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 5278114e8a2SBryan Whitehead #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 5288114e8a2SBryan Whitehead #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 5298114e8a2SBryan Whitehead #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 5308114e8a2SBryan Whitehead #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 53123f0703cSBryan Whitehead #define STAT_RX_TOTAL_FRAMES (0x1254) 5328114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 5338114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TIME (0x125C) 5348114e8a2SBryan Whitehead #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 53523f0703cSBryan Whitehead 53623f0703cSBryan Whitehead #define STAT_TX_FCS_ERRORS (0x1280) 53723f0703cSBryan Whitehead #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 53823f0703cSBryan Whitehead #define STAT_TX_CARRIER_ERRORS (0x1288) 5398114e8a2SBryan Whitehead #define STAT_TX_BAD_BYTE_COUNT (0x128C) 54023f0703cSBryan Whitehead #define STAT_TX_SINGLE_COLLISIONS (0x1290) 54123f0703cSBryan Whitehead #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 54223f0703cSBryan Whitehead #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 54323f0703cSBryan Whitehead #define STAT_TX_LATE_COLLISIONS (0x129C) 54423f0703cSBryan Whitehead #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 54523f0703cSBryan Whitehead #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 54623f0703cSBryan Whitehead #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 5478114e8a2SBryan Whitehead #define STAT_TX_UNICAST_FRAMES (0x12AC) 5488114e8a2SBryan Whitehead #define STAT_TX_BROADCAST_FRAMES (0x12B0) 54923f0703cSBryan Whitehead #define STAT_TX_MULTICAST_FRAMES (0x12B4) 5508114e8a2SBryan Whitehead #define STAT_TX_PAUSE_FRAMES (0x12B8) 5518114e8a2SBryan Whitehead #define STAT_TX_64_BYTE_FRAMES (0x12BC) 5528114e8a2SBryan Whitehead #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 5538114e8a2SBryan Whitehead #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 5548114e8a2SBryan Whitehead #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 5558114e8a2SBryan Whitehead #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 5568114e8a2SBryan Whitehead #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 5578114e8a2SBryan Whitehead #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 55823f0703cSBryan Whitehead #define STAT_TX_TOTAL_FRAMES (0x12D8) 5598114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 5608114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TIME (0x12E0) 5618114e8a2SBryan Whitehead #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 56223f0703cSBryan Whitehead 56323f0703cSBryan Whitehead /* End of Register definitions */ 56423f0703cSBryan Whitehead 56523f0703cSBryan Whitehead #define LAN743X_MAX_RX_CHANNELS (4) 56623f0703cSBryan Whitehead #define LAN743X_MAX_TX_CHANNELS (1) 567cf9aaea8SRaju Lakkaraju #define PCI11X1X_MAX_TX_CHANNELS (4) 56823f0703cSBryan Whitehead struct lan743x_adapter; 56923f0703cSBryan Whitehead 57023f0703cSBryan Whitehead #define LAN743X_USED_RX_CHANNELS (4) 57123f0703cSBryan Whitehead #define LAN743X_USED_TX_CHANNELS (1) 572cf9aaea8SRaju Lakkaraju #define PCI11X1X_USED_TX_CHANNELS (4) 57323f0703cSBryan Whitehead #define LAN743X_INT_MOD (400) 57423f0703cSBryan Whitehead 57523f0703cSBryan Whitehead #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 57623f0703cSBryan Whitehead #error Invalid LAN743X_USED_RX_CHANNELS 57723f0703cSBryan Whitehead #endif 57823f0703cSBryan Whitehead #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 57923f0703cSBryan Whitehead #error Invalid LAN743X_USED_TX_CHANNELS 58023f0703cSBryan Whitehead #endif 581cf9aaea8SRaju Lakkaraju #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS) 582cf9aaea8SRaju Lakkaraju #error Invalid PCI11X1X_USED_TX_CHANNELS 583cf9aaea8SRaju Lakkaraju #endif 58423f0703cSBryan Whitehead 58523f0703cSBryan Whitehead /* PCI */ 58623f0703cSBryan Whitehead /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 58723f0703cSBryan Whitehead #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 58823f0703cSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 5894df5ce9bSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) 590bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A011 (0xA011) 591bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A041 (0xA041) 59223f0703cSBryan Whitehead 59323f0703cSBryan Whitehead #define PCI_CONFIG_LENGTH (0x1000) 59423f0703cSBryan Whitehead 59523f0703cSBryan Whitehead /* CSR */ 59623f0703cSBryan Whitehead #define CSR_LENGTH (0x2000) 59723f0703cSBryan Whitehead 59823f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 59923f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 60023f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 60123f0703cSBryan Whitehead 60223f0703cSBryan Whitehead struct lan743x_csr { 60323f0703cSBryan Whitehead u32 flags; 60423f0703cSBryan Whitehead u8 __iomem *csr_address; 60523f0703cSBryan Whitehead u32 id_rev; 60623f0703cSBryan Whitehead u32 fpga_rev; 60723f0703cSBryan Whitehead }; 60823f0703cSBryan Whitehead 60923f0703cSBryan Whitehead /* INTERRUPTS */ 61023f0703cSBryan Whitehead typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 61123f0703cSBryan Whitehead 61223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 61323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 61423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 61523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 61623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 61723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 61823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 61923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 62023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 62123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 62223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 62323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 62423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 62523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 62623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 62723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 62823f0703cSBryan Whitehead 62923f0703cSBryan Whitehead struct lan743x_vector { 63023f0703cSBryan Whitehead int irq; 63123f0703cSBryan Whitehead u32 flags; 63223f0703cSBryan Whitehead struct lan743x_adapter *adapter; 63323f0703cSBryan Whitehead int vector_index; 63423f0703cSBryan Whitehead u32 int_mask; 63523f0703cSBryan Whitehead lan743x_vector_handler handler; 63623f0703cSBryan Whitehead void *context; 63723f0703cSBryan Whitehead }; 63823f0703cSBryan Whitehead 63923f0703cSBryan Whitehead #define LAN743X_MAX_VECTOR_COUNT (8) 640ac16b6ebSRaju Lakkaraju #define PCI11X1X_MAX_VECTOR_COUNT (16) 64123f0703cSBryan Whitehead 64223f0703cSBryan Whitehead struct lan743x_intr { 64323f0703cSBryan Whitehead int flags; 64423f0703cSBryan Whitehead 64523f0703cSBryan Whitehead unsigned int irq; 64623f0703cSBryan Whitehead 647ac16b6ebSRaju Lakkaraju struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT]; 64823f0703cSBryan Whitehead int number_of_vectors; 64923f0703cSBryan Whitehead bool using_vectors; 65023f0703cSBryan Whitehead 651470dfd80SSven Van Asbroeck bool software_isr_flag; 652470dfd80SSven Van Asbroeck wait_queue_head_t software_isr_wq; 65323f0703cSBryan Whitehead }; 65423f0703cSBryan Whitehead 65523f0703cSBryan Whitehead #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 65623f0703cSBryan Whitehead 65723f0703cSBryan Whitehead /* PHY */ 65823f0703cSBryan Whitehead struct lan743x_phy { 65923f0703cSBryan Whitehead bool fc_autoneg; 66023f0703cSBryan Whitehead u8 fc_request_control; 66123f0703cSBryan Whitehead }; 66223f0703cSBryan Whitehead 66323f0703cSBryan Whitehead /* TX */ 66423f0703cSBryan Whitehead struct lan743x_tx_descriptor; 66523f0703cSBryan Whitehead struct lan743x_tx_buffer_info; 66623f0703cSBryan Whitehead 66723f0703cSBryan Whitehead #define GPIO_QUEUE_STARTED (0) 66823f0703cSBryan Whitehead #define GPIO_TX_FUNCTION (1) 66923f0703cSBryan Whitehead #define GPIO_TX_COMPLETION (2) 67023f0703cSBryan Whitehead #define GPIO_TX_FRAGMENT (3) 67123f0703cSBryan Whitehead 67223f0703cSBryan Whitehead #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 67323f0703cSBryan Whitehead 67407624df1SBryan Whitehead #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 67507624df1SBryan Whitehead #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 67607624df1SBryan Whitehead 67723f0703cSBryan Whitehead struct lan743x_tx { 67823f0703cSBryan Whitehead struct lan743x_adapter *adapter; 67907624df1SBryan Whitehead u32 ts_flags; 68023f0703cSBryan Whitehead u32 vector_flags; 68123f0703cSBryan Whitehead int channel_number; 68223f0703cSBryan Whitehead 68323f0703cSBryan Whitehead int ring_size; 68423f0703cSBryan Whitehead size_t ring_allocation_size; 68523f0703cSBryan Whitehead struct lan743x_tx_descriptor *ring_cpu_ptr; 68623f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 68723f0703cSBryan Whitehead /* ring_lock: used to prevent concurrent access to tx ring */ 68823f0703cSBryan Whitehead spinlock_t ring_lock; 68923f0703cSBryan Whitehead u32 frame_flags; 69023f0703cSBryan Whitehead u32 frame_first; 69123f0703cSBryan Whitehead u32 frame_data0; 69223f0703cSBryan Whitehead u32 frame_tail; 69323f0703cSBryan Whitehead 69423f0703cSBryan Whitehead struct lan743x_tx_buffer_info *buffer_info; 69523f0703cSBryan Whitehead 69646251282SAlexey Denisov __le32 *head_cpu_ptr; 69723f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 69823f0703cSBryan Whitehead int last_head; 69923f0703cSBryan Whitehead int last_tail; 70023f0703cSBryan Whitehead 70123f0703cSBryan Whitehead struct napi_struct napi; 70223f0703cSBryan Whitehead 70323f0703cSBryan Whitehead struct sk_buff *overflow_skb; 70423f0703cSBryan Whitehead }; 70523f0703cSBryan Whitehead 70607624df1SBryan Whitehead void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 70707624df1SBryan Whitehead bool enable_timestamping, 70807624df1SBryan Whitehead bool enable_onestep_sync); 70907624df1SBryan Whitehead 71023f0703cSBryan Whitehead /* RX */ 71123f0703cSBryan Whitehead struct lan743x_rx_descriptor; 71223f0703cSBryan Whitehead struct lan743x_rx_buffer_info; 71323f0703cSBryan Whitehead 71423f0703cSBryan Whitehead struct lan743x_rx { 71523f0703cSBryan Whitehead struct lan743x_adapter *adapter; 71623f0703cSBryan Whitehead u32 vector_flags; 71723f0703cSBryan Whitehead int channel_number; 71823f0703cSBryan Whitehead 71923f0703cSBryan Whitehead int ring_size; 72023f0703cSBryan Whitehead size_t ring_allocation_size; 72123f0703cSBryan Whitehead struct lan743x_rx_descriptor *ring_cpu_ptr; 72223f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 72323f0703cSBryan Whitehead 72423f0703cSBryan Whitehead struct lan743x_rx_buffer_info *buffer_info; 72523f0703cSBryan Whitehead 72646251282SAlexey Denisov __le32 *head_cpu_ptr; 72723f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 72823f0703cSBryan Whitehead u32 last_head; 72923f0703cSBryan Whitehead u32 last_tail; 73023f0703cSBryan Whitehead 73123f0703cSBryan Whitehead struct napi_struct napi; 73223f0703cSBryan Whitehead 73323f0703cSBryan Whitehead u32 frame_count; 734a8db76d4SSven Van Asbroeck 735a8db76d4SSven Van Asbroeck struct sk_buff *skb_head, *skb_tail; 73623f0703cSBryan Whitehead }; 73723f0703cSBryan Whitehead 73823f0703cSBryan Whitehead struct lan743x_adapter { 73923f0703cSBryan Whitehead struct net_device *netdev; 74023f0703cSBryan Whitehead struct mii_bus *mdiobus; 74123f0703cSBryan Whitehead int msg_enable; 7424d94282aSBryan Whitehead #ifdef CONFIG_PM 7434d94282aSBryan Whitehead u32 wolopts; 7444d94282aSBryan Whitehead #endif 74523f0703cSBryan Whitehead struct pci_dev *pdev; 74623f0703cSBryan Whitehead struct lan743x_csr csr; 74723f0703cSBryan Whitehead struct lan743x_intr intr; 74823f0703cSBryan Whitehead 74907624df1SBryan Whitehead struct lan743x_gpio gpio; 75007624df1SBryan Whitehead struct lan743x_ptp ptp; 75107624df1SBryan Whitehead 75223f0703cSBryan Whitehead u8 mac_address[ETH_ALEN]; 75323f0703cSBryan Whitehead 75423f0703cSBryan Whitehead struct lan743x_phy phy; 755cf9aaea8SRaju Lakkaraju struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS]; 756cf9aaea8SRaju Lakkaraju struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; 757cf9aaea8SRaju Lakkaraju bool is_pci11x1x; 758*a46d9d37SRaju Lakkaraju bool is_sgmii_en; 759cf9aaea8SRaju Lakkaraju u8 max_tx_channels; 760cf9aaea8SRaju Lakkaraju u8 used_tx_channels; 761ac16b6ebSRaju Lakkaraju u8 max_vector_count; 762662a14d0SBryan Whitehead 763662a14d0SBryan Whitehead #define LAN743X_ADAPTER_FLAG_OTP BIT(0) 764662a14d0SBryan Whitehead u32 flags; 76523f0703cSBryan Whitehead }; 76623f0703cSBryan Whitehead 76723f0703cSBryan Whitehead #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 76823f0703cSBryan Whitehead 76923f0703cSBryan Whitehead #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 77023f0703cSBryan Whitehead #define INTR_FLAG_MSI_ENABLED BIT(8) 77123f0703cSBryan Whitehead #define INTR_FLAG_MSIX_ENABLED BIT(9) 77223f0703cSBryan Whitehead 77323f0703cSBryan Whitehead #define MAC_MII_READ 1 77423f0703cSBryan Whitehead #define MAC_MII_WRITE 0 77523f0703cSBryan Whitehead 77623f0703cSBryan Whitehead #define PHY_FLAG_OPENED BIT(0) 77723f0703cSBryan Whitehead #define PHY_FLAG_ATTACHED BIT(1) 77823f0703cSBryan Whitehead 77923f0703cSBryan Whitehead #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 78023f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 78123f0703cSBryan Whitehead #else 78223f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 78323f0703cSBryan Whitehead #endif 78423f0703cSBryan Whitehead #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 78523f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_16 (16) 78623f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_32 (32) 78723f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_64 (64) 78823f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_128 (128) 78923f0703cSBryan Whitehead #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 79023f0703cSBryan Whitehead 79123f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 79223f0703cSBryan Whitehead (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 79323f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 79423f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 79523f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 79623f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 79723f0703cSBryan Whitehead 79823f0703cSBryan Whitehead /* TX Descriptor bits */ 79923f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 80023f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 80123f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 80223f0703cSBryan Whitehead #define TX_DESC_DATA0_FS_ (0x20000000) 80323f0703cSBryan Whitehead #define TX_DESC_DATA0_LS_ (0x10000000) 80423f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_ (0x08000000) 80523f0703cSBryan Whitehead #define TX_DESC_DATA0_IOC_ (0x04000000) 80623f0703cSBryan Whitehead #define TX_DESC_DATA0_ICE_ (0x00400000) 80723f0703cSBryan Whitehead #define TX_DESC_DATA0_IPE_ (0x00200000) 80823f0703cSBryan Whitehead #define TX_DESC_DATA0_TPE_ (0x00100000) 80923f0703cSBryan Whitehead #define TX_DESC_DATA0_FCS_ (0x00020000) 81007624df1SBryan Whitehead #define TX_DESC_DATA0_TSE_ (0x00010000) 81123f0703cSBryan Whitehead #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 81223f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 81323f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 81423f0703cSBryan Whitehead #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 81523f0703cSBryan Whitehead 81623f0703cSBryan Whitehead struct lan743x_tx_descriptor { 81746251282SAlexey Denisov __le32 data0; 81846251282SAlexey Denisov __le32 data1; 81946251282SAlexey Denisov __le32 data2; 82046251282SAlexey Denisov __le32 data3; 82123f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 82223f0703cSBryan Whitehead 82323f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 82407624df1SBryan Whitehead #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 82523f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 82623f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 82723f0703cSBryan Whitehead struct lan743x_tx_buffer_info { 82823f0703cSBryan Whitehead int flags; 82923f0703cSBryan Whitehead struct sk_buff *skb; 83023f0703cSBryan Whitehead dma_addr_t dma_ptr; 83123f0703cSBryan Whitehead unsigned int buffer_length; 83223f0703cSBryan Whitehead }; 83323f0703cSBryan Whitehead 83423f0703cSBryan Whitehead #define LAN743X_TX_RING_SIZE (50) 83523f0703cSBryan Whitehead 83623f0703cSBryan Whitehead /* OWN bit is set. ie, Descs are owned by RX DMAC */ 83723f0703cSBryan Whitehead #define RX_DESC_DATA0_OWN_ (0x00008000) 83823f0703cSBryan Whitehead /* OWN bit is clear. ie, Descs are owned by host */ 83923f0703cSBryan Whitehead #define RX_DESC_DATA0_FS_ (0x80000000) 84023f0703cSBryan Whitehead #define RX_DESC_DATA0_LS_ (0x40000000) 84123f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 84223f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 84323f0703cSBryan Whitehead (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 84423f0703cSBryan Whitehead #define RX_DESC_DATA0_EXT_ (0x00004000) 84523f0703cSBryan Whitehead #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 84623f0703cSBryan Whitehead #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 84723f0703cSBryan Whitehead 84823f0703cSBryan Whitehead #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 84923f0703cSBryan Whitehead #error NET_IP_ALIGN must be 0 or 2 85023f0703cSBryan Whitehead #endif 85123f0703cSBryan Whitehead 85223f0703cSBryan Whitehead #define RX_HEAD_PADDING NET_IP_ALIGN 85323f0703cSBryan Whitehead 85423f0703cSBryan Whitehead struct lan743x_rx_descriptor { 85546251282SAlexey Denisov __le32 data0; 85646251282SAlexey Denisov __le32 data1; 85746251282SAlexey Denisov __le32 data2; 85846251282SAlexey Denisov __le32 data3; 85923f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 86023f0703cSBryan Whitehead 86123f0703cSBryan Whitehead #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 86223f0703cSBryan Whitehead struct lan743x_rx_buffer_info { 86323f0703cSBryan Whitehead int flags; 86423f0703cSBryan Whitehead struct sk_buff *skb; 86523f0703cSBryan Whitehead 86623f0703cSBryan Whitehead dma_addr_t dma_ptr; 86723f0703cSBryan Whitehead unsigned int buffer_length; 86823f0703cSBryan Whitehead }; 86923f0703cSBryan Whitehead 870a1f16275SYuiko Oshino #define LAN743X_RX_RING_SIZE (128) 87123f0703cSBryan Whitehead 87223f0703cSBryan Whitehead #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 873a8db76d4SSven Van Asbroeck #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) 87423f0703cSBryan Whitehead 8758114e8a2SBryan Whitehead u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 8768114e8a2SBryan Whitehead void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 8778114e8a2SBryan Whitehead 87823f0703cSBryan Whitehead #endif /* _LAN743X_H */ 879