123f0703cSBryan Whitehead /* SPDX-License-Identifier: GPL-2.0+ */ 223f0703cSBryan Whitehead /* Copyright (C) 2018 Microchip Technology Inc. */ 323f0703cSBryan Whitehead 423f0703cSBryan Whitehead #ifndef _LAN743X_H 523f0703cSBryan Whitehead #define _LAN743X_H 623f0703cSBryan Whitehead 76f197fb6SRoelof Berg #include <linux/phy.h> 807624df1SBryan Whitehead #include "lan743x_ptp.h" 907624df1SBryan Whitehead 1023f0703cSBryan Whitehead #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 1123f0703cSBryan Whitehead #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 1223f0703cSBryan Whitehead #define DRIVER_NAME "lan743x" 1323f0703cSBryan Whitehead 1423f0703cSBryan Whitehead /* Register Definitions */ 1523f0703cSBryan Whitehead #define ID_REV (0x00) 1607624df1SBryan Whitehead #define ID_REV_ID_MASK_ (0xFFFF0000) 1707624df1SBryan Whitehead #define ID_REV_ID_LAN7430_ (0x74300000) 1807624df1SBryan Whitehead #define ID_REV_ID_LAN7431_ (0x74310000) 19bb4f6bffSRaju Lakkaraju #define ID_REV_ID_LAN743X_ (0x74300000) 20bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 21bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 22bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A0X1_ (0xA0010000) 2323f0703cSBryan Whitehead #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 24bb4f6bffSRaju Lakkaraju ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ 25bb4f6bffSRaju Lakkaraju (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) 2623f0703cSBryan Whitehead #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 2723f0703cSBryan Whitehead #define ID_REV_CHIP_REV_A0_ (0x00000000) 2823f0703cSBryan Whitehead #define ID_REV_CHIP_REV_B0_ (0x00000010) 2923f0703cSBryan Whitehead 3023f0703cSBryan Whitehead #define FPGA_REV (0x04) 3123f0703cSBryan Whitehead #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 3223f0703cSBryan Whitehead #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 33a46d9d37SRaju Lakkaraju #define FPGA_SGMII_OP BIT(24) 34a46d9d37SRaju Lakkaraju 35a46d9d37SRaju Lakkaraju #define STRAP_READ (0x0C) 36a46d9d37SRaju Lakkaraju #define STRAP_READ_USE_SGMII_EN_ BIT(22) 37a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_EN_ BIT(6) 38a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_REFCLK_ BIT(5) 39a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_2_5G_ BIT(4) 40a46d9d37SRaju Lakkaraju #define STRAP_READ_BASE_X_ BIT(3) 41a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2) 42a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1) 43a46d9d37SRaju Lakkaraju #define STRAP_READ_ADV_PM_DISABLE_ BIT(0) 4423f0703cSBryan Whitehead 4523f0703cSBryan Whitehead #define HW_CFG (0x010) 46*6b3768acSRaju Lakkaraju #define HW_CFG_RST_PROTECT_PCIE_ BIT(19) 47*6b3768acSRaju Lakkaraju #define HW_CFG_HOT_RESET_DIS_ BIT(15) 48*6b3768acSRaju Lakkaraju #define HW_CFG_D3_VAUX_OVR_ BIT(14) 49*6b3768acSRaju Lakkaraju #define HW_CFG_D3_RESET_DIS_ BIT(13) 50*6b3768acSRaju Lakkaraju #define HW_CFG_RST_PROTECT_ BIT(12) 51662a14d0SBryan Whitehead #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) 52662a14d0SBryan Whitehead #define HW_CFG_EE_OTP_RELOAD_ BIT(4) 5323f0703cSBryan Whitehead #define HW_CFG_LRST_ BIT(1) 5423f0703cSBryan Whitehead 5523f0703cSBryan Whitehead #define PMT_CTL (0x014) 564d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 574d94282aSBryan Whitehead #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 584d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 594d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 604d94282aSBryan Whitehead #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 614d94282aSBryan Whitehead #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 624d94282aSBryan Whitehead #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 6323f0703cSBryan Whitehead #define PMT_CTL_READY_ BIT(7) 6423f0703cSBryan Whitehead #define PMT_CTL_ETH_PHY_RST_ BIT(4) 654d94282aSBryan Whitehead #define PMT_CTL_WOL_EN_ BIT(3) 664d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 674d94282aSBryan Whitehead #define PMT_CTL_WUPS_MASK_ (0x00000003) 6823f0703cSBryan Whitehead 6923f0703cSBryan Whitehead #define DP_SEL (0x024) 7023f0703cSBryan Whitehead #define DP_SEL_DPRDY_ BIT(31) 7123f0703cSBryan Whitehead #define DP_SEL_MASK_ (0x0000001F) 7223f0703cSBryan Whitehead #define DP_SEL_RFE_RAM (0x00000001) 7323f0703cSBryan Whitehead 7423f0703cSBryan Whitehead #define DP_SEL_VHF_HASH_LEN (16) 7523f0703cSBryan Whitehead #define DP_SEL_VHF_VLAN_LEN (128) 7623f0703cSBryan Whitehead 7723f0703cSBryan Whitehead #define DP_CMD (0x028) 7823f0703cSBryan Whitehead #define DP_CMD_WRITE_ (0x00000001) 7923f0703cSBryan Whitehead 8023f0703cSBryan Whitehead #define DP_ADDR (0x02C) 8123f0703cSBryan Whitehead 8223f0703cSBryan Whitehead #define DP_DATA_0 (0x030) 8323f0703cSBryan Whitehead 8469584604SBryan Whitehead #define E2P_CMD (0x040) 8569584604SBryan Whitehead #define E2P_CMD_EPC_BUSY_ BIT(31) 8669584604SBryan Whitehead #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 8769584604SBryan Whitehead #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 8869584604SBryan Whitehead #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 8969584604SBryan Whitehead #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 9069584604SBryan Whitehead #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 9169584604SBryan Whitehead 9269584604SBryan Whitehead #define E2P_DATA (0x044) 9369584604SBryan Whitehead 94cdea83ccSRaju Lakkaraju /* Hearthstone top level & System Reg Addresses */ 95cdea83ccSRaju Lakkaraju #define ETH_CTRL_REG_ADDR_BASE (0x0000) 96cdea83ccSRaju Lakkaraju #define ETH_SYS_REG_ADDR_BASE (0x4000) 97cdea83ccSRaju Lakkaraju #define CONFIG_REG_ADDR_BASE (0x0000) 98cdea83ccSRaju Lakkaraju #define ETH_EEPROM_REG_ADDR_BASE (0x0E00) 99cdea83ccSRaju Lakkaraju #define ETH_OTP_REG_ADDR_BASE (0x1000) 100cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG (0x00A0) 101cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_MAIN_LOCK_ BIT(7) 102cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5) 103cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4) 104cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3) 105cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2) 106cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1) 107cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0) 108cdea83ccSRaju Lakkaraju #define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \ 109cdea83ccSRaju Lakkaraju CONFIG_REG_ADDR_BASE + \ 110cdea83ccSRaju Lakkaraju SYS_LOCK_REG) 111cdea83ccSRaju Lakkaraju #define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \ 112cdea83ccSRaju Lakkaraju ETH_EEPROM_REG_ADDR_BASE) 113cdea83ccSRaju Lakkaraju #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000) 114cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_BUSY_ BIT(31) 115cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28) 116cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_CMD_READ_ (0x0) 117cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17) 118cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0) 119cdea83ccSRaju Lakkaraju #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004) 120cdea83ccSRaju Lakkaraju #define HS_E2P_DATA_MASK_ GENMASK(7, 0) 121cdea83ccSRaju Lakkaraju #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008) 122cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16) 123cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12) 124cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8) 125cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0) 126cdea83ccSRaju Lakkaraju #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C) 127cdea83ccSRaju Lakkaraju 12807624df1SBryan Whitehead #define GPIO_CFG0 (0x050) 12907624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 13007624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 13107624df1SBryan Whitehead 13207624df1SBryan Whitehead #define GPIO_CFG1 (0x054) 13307624df1SBryan Whitehead #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 13407624df1SBryan Whitehead #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 13507624df1SBryan Whitehead 13607624df1SBryan Whitehead #define GPIO_CFG2 (0x058) 13707624df1SBryan Whitehead #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 13807624df1SBryan Whitehead 13907624df1SBryan Whitehead #define GPIO_CFG3 (0x05C) 14007624df1SBryan Whitehead #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 14107624df1SBryan Whitehead #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 14207624df1SBryan Whitehead 14323f0703cSBryan Whitehead #define FCT_RX_CTL (0xAC) 14423f0703cSBryan Whitehead #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 14523f0703cSBryan Whitehead #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 14623f0703cSBryan Whitehead #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 14723f0703cSBryan Whitehead 14823f0703cSBryan Whitehead #define FCT_TX_CTL (0xC4) 14923f0703cSBryan Whitehead #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 15023f0703cSBryan Whitehead #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 15123f0703cSBryan Whitehead #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 15223f0703cSBryan Whitehead 15323f0703cSBryan Whitehead #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 15423f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 15523f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 15623f0703cSBryan Whitehead ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 15723f0703cSBryan Whitehead #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 15823f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 15923f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 16023f0703cSBryan Whitehead ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 16123f0703cSBryan Whitehead 16223f0703cSBryan Whitehead #define MAC_CR (0x100) 1636f197fb6SRoelof Berg #define MAC_CR_MII_EN_ BIT(19) 164c9cf96bbSBryan Whitehead #define MAC_CR_EEE_EN_ BIT(17) 16523f0703cSBryan Whitehead #define MAC_CR_ADD_ BIT(12) 16623f0703cSBryan Whitehead #define MAC_CR_ASD_ BIT(11) 16723f0703cSBryan Whitehead #define MAC_CR_CNTR_RST_ BIT(5) 1686f197fb6SRoelof Berg #define MAC_CR_DPX_ BIT(3) 1696f197fb6SRoelof Berg #define MAC_CR_CFG_H_ BIT(2) 1706f197fb6SRoelof Berg #define MAC_CR_CFG_L_ BIT(1) 17123f0703cSBryan Whitehead #define MAC_CR_RST_ BIT(0) 17223f0703cSBryan Whitehead 17323f0703cSBryan Whitehead #define MAC_RX (0x104) 17423f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_SHIFT_ (16) 17523f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 17623f0703cSBryan Whitehead #define MAC_RX_RXD_ BIT(1) 17723f0703cSBryan Whitehead #define MAC_RX_RXEN_ BIT(0) 17823f0703cSBryan Whitehead 17923f0703cSBryan Whitehead #define MAC_TX (0x108) 18023f0703cSBryan Whitehead #define MAC_TX_TXD_ BIT(1) 18123f0703cSBryan Whitehead #define MAC_TX_TXEN_ BIT(0) 18223f0703cSBryan Whitehead 18323f0703cSBryan Whitehead #define MAC_FLOW (0x10C) 18423f0703cSBryan Whitehead #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 18523f0703cSBryan Whitehead #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 18623f0703cSBryan Whitehead #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 18723f0703cSBryan Whitehead 18823f0703cSBryan Whitehead #define MAC_RX_ADDRH (0x118) 18923f0703cSBryan Whitehead 19023f0703cSBryan Whitehead #define MAC_RX_ADDRL (0x11C) 19123f0703cSBryan Whitehead 19223f0703cSBryan Whitehead #define MAC_MII_ACC (0x120) 193a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16) 194a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000) 195a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0) 196a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1) 197a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2) 198a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3) 199a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4) 20023f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 20123f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 20223f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 20323f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 20423f0703cSBryan Whitehead #define MAC_MII_ACC_MII_READ_ (0x00000000) 20523f0703cSBryan Whitehead #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 20623f0703cSBryan Whitehead #define MAC_MII_ACC_MII_BUSY_ BIT(0) 20723f0703cSBryan Whitehead 208a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIIMMD_SHIFT_ (6) 209a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0) 210a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICL45_ BIT(3) 211a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_MASK_ (0x00000006) 212a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000) 213a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002) 214a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_READ_ (0x00000004) 215a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006) 216a2ab95a3SRaju Lakkaraju 21723f0703cSBryan Whitehead #define MAC_MII_DATA (0x124) 21823f0703cSBryan Whitehead 219c9cf96bbSBryan Whitehead #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 220c9cf96bbSBryan Whitehead 2214d94282aSBryan Whitehead #define MAC_WUCSR (0x140) 222*6b3768acSRaju Lakkaraju #define MAC_MP_SO_EN_ BIT(21) 2234d94282aSBryan Whitehead #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 2244d94282aSBryan Whitehead #define MAC_WUCSR_PFDA_EN_ BIT(3) 2254d94282aSBryan Whitehead #define MAC_WUCSR_WAKE_EN_ BIT(2) 2264d94282aSBryan Whitehead #define MAC_WUCSR_MPEN_ BIT(1) 2274d94282aSBryan Whitehead #define MAC_WUCSR_BCST_EN_ BIT(0) 2284d94282aSBryan Whitehead 2294d94282aSBryan Whitehead #define MAC_WK_SRC (0x144) 230*6b3768acSRaju Lakkaraju #define MAC_MP_SO_HI (0x148) 231*6b3768acSRaju Lakkaraju #define MAC_MP_SO_LO (0x14C) 2324d94282aSBryan Whitehead 2334d94282aSBryan Whitehead #define MAC_WUF_CFG0 (0x150) 2344d94282aSBryan Whitehead #define MAC_NUM_OF_WUF_CFG (32) 2354d94282aSBryan Whitehead #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 2364d94282aSBryan Whitehead #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 2374d94282aSBryan Whitehead #define MAC_WUF_CFG_EN_ BIT(31) 2384d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 2394d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 2404d94282aSBryan Whitehead #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 2414d94282aSBryan Whitehead #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 2424d94282aSBryan Whitehead 2434d94282aSBryan Whitehead #define MAC_WUF_MASK0_0 (0x200) 2444d94282aSBryan Whitehead #define MAC_WUF_MASK0_1 (0x204) 2454d94282aSBryan Whitehead #define MAC_WUF_MASK0_2 (0x208) 2464d94282aSBryan Whitehead #define MAC_WUF_MASK0_3 (0x20C) 2474d94282aSBryan Whitehead #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 2484d94282aSBryan Whitehead #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 2494d94282aSBryan Whitehead #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 2504d94282aSBryan Whitehead #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 2514d94282aSBryan Whitehead #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 2524d94282aSBryan Whitehead #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 2534d94282aSBryan Whitehead #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 2544d94282aSBryan Whitehead #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 2554d94282aSBryan Whitehead 25623f0703cSBryan Whitehead /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 25723f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 25823f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 25923f0703cSBryan Whitehead 26023f0703cSBryan Whitehead /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 26123f0703cSBryan Whitehead #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 26223f0703cSBryan Whitehead 26323f0703cSBryan Whitehead #define RFE_CTL (0x508) 26423f0703cSBryan Whitehead #define RFE_CTL_AB_ BIT(10) 26523f0703cSBryan Whitehead #define RFE_CTL_AM_ BIT(9) 26623f0703cSBryan Whitehead #define RFE_CTL_AU_ BIT(8) 26723f0703cSBryan Whitehead #define RFE_CTL_MCAST_HASH_ BIT(3) 26823f0703cSBryan Whitehead #define RFE_CTL_DA_PERFECT_ BIT(1) 26923f0703cSBryan Whitehead 27043e8fe9bSBryan Whitehead #define RFE_RSS_CFG (0x554) 27143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 27243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 27343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 27443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 27543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 27643e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_ BIT(11) 27743e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 27843e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 27943e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV4_ BIT(8) 28043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 28143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 28243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 28343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 28443e8fe9bSBryan Whitehead 28543e8fe9bSBryan Whitehead #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 28643e8fe9bSBryan Whitehead 28743e8fe9bSBryan Whitehead #define RFE_INDX(index) (0x580 + (index << 2)) 28843e8fe9bSBryan Whitehead 2894d94282aSBryan Whitehead #define MAC_WUCSR2 (0x600) 2904d94282aSBryan Whitehead 291a46d9d37SRaju Lakkaraju #define SGMII_CTL (0x728) 292a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_ENABLE_ BIT(31) 293a46d9d37SRaju Lakkaraju #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8) 294a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_POWER_DN_ BIT(1) 295a46d9d37SRaju Lakkaraju 29623f0703cSBryan Whitehead #define INT_STS (0x780) 29723f0703cSBryan Whitehead #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 29823f0703cSBryan Whitehead #define INT_BIT_ALL_RX_ (0x0F000000) 29923f0703cSBryan Whitehead #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 30023f0703cSBryan Whitehead #define INT_BIT_ALL_TX_ (0x000F0000) 30123f0703cSBryan Whitehead #define INT_BIT_SW_GP_ BIT(9) 30207624df1SBryan Whitehead #define INT_BIT_1588_ BIT(7) 30307624df1SBryan Whitehead #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 30423f0703cSBryan Whitehead #define INT_BIT_MAS_ BIT(0) 30523f0703cSBryan Whitehead 30623f0703cSBryan Whitehead #define INT_SET (0x784) 30723f0703cSBryan Whitehead 30823f0703cSBryan Whitehead #define INT_EN_SET (0x788) 30923f0703cSBryan Whitehead 31023f0703cSBryan Whitehead #define INT_EN_CLR (0x78C) 31123f0703cSBryan Whitehead 31223f0703cSBryan Whitehead #define INT_STS_R2C (0x790) 31323f0703cSBryan Whitehead 31423f0703cSBryan Whitehead #define INT_VEC_EN_SET (0x794) 31523f0703cSBryan Whitehead #define INT_VEC_EN_CLR (0x798) 31623f0703cSBryan Whitehead #define INT_VEC_EN_AUTO_CLR (0x79C) 31723f0703cSBryan Whitehead #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 31823f0703cSBryan Whitehead 31923f0703cSBryan Whitehead #define INT_VEC_MAP0 (0x7A0) 32023f0703cSBryan Whitehead #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 32123f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 32223f0703cSBryan Whitehead 32323f0703cSBryan Whitehead #define INT_VEC_MAP1 (0x7A4) 32423f0703cSBryan Whitehead #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 32523f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 32623f0703cSBryan Whitehead 32723f0703cSBryan Whitehead #define INT_VEC_MAP2 (0x7A8) 32823f0703cSBryan Whitehead 32923f0703cSBryan Whitehead #define INT_MOD_MAP0 (0x7B0) 33023f0703cSBryan Whitehead 33123f0703cSBryan Whitehead #define INT_MOD_MAP1 (0x7B4) 33223f0703cSBryan Whitehead 33323f0703cSBryan Whitehead #define INT_MOD_MAP2 (0x7B8) 33423f0703cSBryan Whitehead 33523f0703cSBryan Whitehead #define INT_MOD_CFG0 (0x7C0) 33623f0703cSBryan Whitehead #define INT_MOD_CFG1 (0x7C4) 33723f0703cSBryan Whitehead #define INT_MOD_CFG2 (0x7C8) 33823f0703cSBryan Whitehead #define INT_MOD_CFG3 (0x7CC) 33923f0703cSBryan Whitehead #define INT_MOD_CFG4 (0x7D0) 34023f0703cSBryan Whitehead #define INT_MOD_CFG5 (0x7D4) 34123f0703cSBryan Whitehead #define INT_MOD_CFG6 (0x7D8) 34223f0703cSBryan Whitehead #define INT_MOD_CFG7 (0x7DC) 343ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG8 (0x7E0) 344ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG9 (0x7E4) 34523f0703cSBryan Whitehead 34607624df1SBryan Whitehead #define PTP_CMD_CTL (0x0A00) 347e432dd3bSRaju Lakkaraju #define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13) 34807624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 34907624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 35007624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 35107624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 35207624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 35307624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 35407624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 35507624df1SBryan Whitehead #define PTP_GENERAL_CONFIG (0x0A04) 35607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 35707624df1SBryan Whitehead (0x7 << (1 + ((channel) << 2))) 35807624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 35907624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 36007624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 36107624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 36207624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 36307624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 3644ece1ae4SYuiko Oshino #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) 36507624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 36607624df1SBryan Whitehead (((value) & 0x7) << (1 + ((channel) << 2))) 36707624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 36807624df1SBryan Whitehead 369e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG (0x0A04) 370e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 371e432dd3bSRaju Lakkaraju (0xf << (4 + ((channel) << 2))) 372e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 373e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1) 374e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2) 375e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3) 376e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4) 377e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5) 378e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6) 379e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7) 380e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8) 381e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9) 382e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10) 383e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11) 384e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12) 385e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13) 386e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14) 387e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15) 388e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 389e432dd3bSRaju Lakkaraju (((value) & 0xf) << (4 + ((channel) << 2))) 390e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2))) 391e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2)) 392e432dd3bSRaju Lakkaraju 39307624df1SBryan Whitehead #define PTP_INT_STS (0x0A08) 39460942c39SRaju Lakkaraju #define PTP_INT_IO_FE_MASK_ GENMASK(31, 24) 39560942c39SRaju Lakkaraju #define PTP_INT_IO_FE_SHIFT_ (24) 39660942c39SRaju Lakkaraju #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel)) 39760942c39SRaju Lakkaraju #define PTP_INT_IO_RE_MASK_ GENMASK(23, 16) 39860942c39SRaju Lakkaraju #define PTP_INT_IO_RE_SHIFT_ (16) 39960942c39SRaju Lakkaraju #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel)) 400e432dd3bSRaju Lakkaraju #define PTP_INT_TX_TS_OVRFL_INT_ BIT(14) 401e432dd3bSRaju Lakkaraju #define PTP_INT_TX_SWTS_ERR_INT_ BIT(13) 402e432dd3bSRaju Lakkaraju #define PTP_INT_TX_TS_INT_ BIT(12) 403e432dd3bSRaju Lakkaraju #define PTP_INT_RX_TS_OVRFL_INT_ BIT(9) 404e432dd3bSRaju Lakkaraju #define PTP_INT_RX_TS_INT_ BIT(8) 405e432dd3bSRaju Lakkaraju #define PTP_INT_TIMER_INT_B_ BIT(1) 406e432dd3bSRaju Lakkaraju #define PTP_INT_TIMER_INT_A_ BIT(0) 40707624df1SBryan Whitehead #define PTP_INT_EN_SET (0x0A0C) 40860942c39SRaju Lakkaraju #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel)) 40960942c39SRaju Lakkaraju #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel)) 410e432dd3bSRaju Lakkaraju #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel) 41107624df1SBryan Whitehead #define PTP_INT_EN_CLR (0x0A10) 41260942c39SRaju Lakkaraju #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel)) 41360942c39SRaju Lakkaraju #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel)) 41407624df1SBryan Whitehead #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 41507624df1SBryan Whitehead #define PTP_INT_BIT_TX_TS_ BIT(12) 41607624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_B_ BIT(1) 41707624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_A_ BIT(0) 41807624df1SBryan Whitehead 41907624df1SBryan Whitehead #define PTP_CLOCK_SEC (0x0A14) 42007624df1SBryan Whitehead #define PTP_CLOCK_NS (0x0A18) 42107624df1SBryan Whitehead #define PTP_CLOCK_SUBNS (0x0A1C) 42207624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ (0x0A20) 42307624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 42407624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ (0x0A2C) 42507624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 42607624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 42707624df1SBryan Whitehead #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 42807624df1SBryan Whitehead #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 42907624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 43007624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 43160942c39SRaju Lakkaraju #define PTP_LTC_SET_SEC_HI (0x0A50) 43260942c39SRaju Lakkaraju #define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) 43360942c39SRaju Lakkaraju #define PTP_VERSION (0x0A54) 43460942c39SRaju Lakkaraju #define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24) 43560942c39SRaju Lakkaraju #define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16) 43660942c39SRaju Lakkaraju #define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8) 43760942c39SRaju Lakkaraju #define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0) 43860942c39SRaju Lakkaraju #define PTP_IO_SEL (0x0A58) 43960942c39SRaju Lakkaraju #define PTP_IO_SEL_MASK_ GENMASK(10, 8) 44060942c39SRaju Lakkaraju #define PTP_IO_SEL_SHIFT_ (8) 44107624df1SBryan Whitehead #define PTP_LATENCY (0x0A5C) 44207624df1SBryan Whitehead #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 44307624df1SBryan Whitehead #define PTP_LATENCY_RX_SET_(rx_latency) \ 44407624df1SBryan Whitehead (((u32)(rx_latency)) & 0x0000FFFF) 44507624df1SBryan Whitehead #define PTP_CAP_INFO (0x0A60) 44607624df1SBryan Whitehead #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 44707624df1SBryan Whitehead 44807624df1SBryan Whitehead #define PTP_TX_MOD (0x0AA4) 44907624df1SBryan Whitehead #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 45007624df1SBryan Whitehead 45107624df1SBryan Whitehead #define PTP_TX_MOD2 (0x0AA8) 45207624df1SBryan Whitehead #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 45307624df1SBryan Whitehead 45407624df1SBryan Whitehead #define PTP_TX_EGRESS_SEC (0x0AAC) 45507624df1SBryan Whitehead #define PTP_TX_EGRESS_NS (0x0AB0) 45607624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 45707624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 45807624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 45907624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 46007624df1SBryan Whitehead 46107624df1SBryan Whitehead #define PTP_TX_MSG_HEADER (0x0AB4) 46207624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 46307624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 46407624df1SBryan Whitehead 46560942c39SRaju Lakkaraju #define PTP_TX_CAP_INFO (0x0AB8) 46660942c39SRaju Lakkaraju #define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0) 46760942c39SRaju Lakkaraju #define PTP_TX_DOMAIN (0x0ABC) 46860942c39SRaju Lakkaraju #define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16) 46960942c39SRaju Lakkaraju #define PTP_TX_DOMAIN_RANGE_EN_ BIT(15) 47060942c39SRaju Lakkaraju #define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0) 47160942c39SRaju Lakkaraju #define PTP_TX_SDOID (0x0AC0) 47260942c39SRaju Lakkaraju #define PTP_TX_SDOID_MASK_ GENMASK(23, 16) 47360942c39SRaju Lakkaraju #define PTP_TX_SDOID_RANGE_EN_ BIT(15) 47460942c39SRaju Lakkaraju #define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0) 47560942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG (0x0AC4) 47660942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel)) 47760942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel)) 47860942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel)) 47960942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel)) 48060942c39SRaju Lakkaraju #define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8) 48160942c39SRaju Lakkaraju #define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC) 48260942c39SRaju Lakkaraju #define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0) 48360942c39SRaju Lakkaraju #define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4) 48460942c39SRaju Lakkaraju #define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8) 48560942c39SRaju Lakkaraju #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel)) 48660942c39SRaju Lakkaraju #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel)) 48760942c39SRaju Lakkaraju #define PTP_IO_PIN_CFG (0x0ADC) 48860942c39SRaju Lakkaraju #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel)) 48960942c39SRaju Lakkaraju #define PTP_LTC_RD_SEC_HI (0x0AF0) 49060942c39SRaju Lakkaraju #define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) 49160942c39SRaju Lakkaraju #define PTP_LTC_RD_SEC_LO (0x0AF4) 49260942c39SRaju Lakkaraju #define PTP_LTC_RD_NS (0x0AF8) 49360942c39SRaju Lakkaraju #define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0) 49460942c39SRaju Lakkaraju #define PTP_LTC_RD_SUBNS (0x0AFC) 49560942c39SRaju Lakkaraju #define PTP_RX_USER_MAC_HI (0x0B00) 49660942c39SRaju Lakkaraju #define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) 49760942c39SRaju Lakkaraju #define PTP_RX_USER_MAC_LO (0x0B04) 49860942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_0 (0x0B20) 49960942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_1 (0x0B24) 50060942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_2 (0x0B28) 50160942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_3 (0x0B2C) 50260942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_0 (0x0B30) 50360942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_1 (0x0B34) 50460942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_2 (0x0B38) 50560942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_3 (0x0B3C) 50660942c39SRaju Lakkaraju #define PTP_TX_USER_MAC_HI (0x0B40) 50760942c39SRaju Lakkaraju #define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) 50860942c39SRaju Lakkaraju #define PTP_TX_USER_MAC_LO (0x0B44) 50960942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_0 (0x0B60) 51060942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_1 (0x0B64) 51160942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_2 (0x0B68) 51260942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_3 (0x0B6C) 51360942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_0 (0x0B70) 51460942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_1 (0x0B74) 51560942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_2 (0x0B78) 51660942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_3 (0x0B7C) 51760942c39SRaju Lakkaraju 51823f0703cSBryan Whitehead #define DMAC_CFG (0xC00) 51923f0703cSBryan Whitehead #define DMAC_CFG_COAL_EN_ BIT(16) 52023f0703cSBryan Whitehead #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 52123f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 52223f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 52323f0703cSBryan Whitehead ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 52423f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 52523f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 52623f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 52723f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 52823f0703cSBryan Whitehead 52923f0703cSBryan Whitehead #define DMAC_COAL_CFG (0xC04) 53023f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 53123f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 53223f0703cSBryan Whitehead ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 53323f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 53423f0703cSBryan Whitehead #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 53523f0703cSBryan Whitehead #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 53623f0703cSBryan Whitehead #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 53723f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 53823f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 53923f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 54023f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 54123f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 54223f0703cSBryan Whitehead (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 54323f0703cSBryan Whitehead 54423f0703cSBryan Whitehead #define DMAC_OBFF_CFG (0xC08) 54523f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 54623f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_SET_(val) \ 54723f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 54823f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 54923f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_SET_(val) \ 55023f0703cSBryan Whitehead (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 55123f0703cSBryan Whitehead 55223f0703cSBryan Whitehead #define DMAC_CMD (0xC0C) 55323f0703cSBryan Whitehead #define DMAC_CMD_SWR_ BIT(31) 55423f0703cSBryan Whitehead #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 55523f0703cSBryan Whitehead #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 55623f0703cSBryan Whitehead #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 55723f0703cSBryan Whitehead #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 55823f0703cSBryan Whitehead #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 55923f0703cSBryan Whitehead #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 56023f0703cSBryan Whitehead 56123f0703cSBryan Whitehead #define DMAC_INT_STS (0xC10) 56223f0703cSBryan Whitehead #define DMAC_INT_EN_SET (0xC14) 56323f0703cSBryan Whitehead #define DMAC_INT_EN_CLR (0xC18) 56423f0703cSBryan Whitehead #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 56523f0703cSBryan Whitehead #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 56623f0703cSBryan Whitehead 56723f0703cSBryan Whitehead #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 56823f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 56923f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 57023f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 57123f0703cSBryan Whitehead ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 57223f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 57323f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 57423f0703cSBryan Whitehead ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 57523f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 57623f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 57723f0703cSBryan Whitehead ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 57823f0703cSBryan Whitehead #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 57923f0703cSBryan Whitehead 58023f0703cSBryan Whitehead #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 58123f0703cSBryan Whitehead #define RX_CFG_B_TS_ALL_RX_ BIT(29) 58223f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 58323f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_0_ (0x00000000) 58423f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_2_ (0x02000000) 58523f0703cSBryan Whitehead #define RX_CFG_B_RDMABL_512_ (0x00040000) 58623f0703cSBryan Whitehead #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 58723f0703cSBryan Whitehead 58823f0703cSBryan Whitehead #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 58923f0703cSBryan Whitehead 59023f0703cSBryan Whitehead #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 59123f0703cSBryan Whitehead 59223f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 59323f0703cSBryan Whitehead 59423f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 59523f0703cSBryan Whitehead 59623f0703cSBryan Whitehead #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 59723f0703cSBryan Whitehead 59823f0703cSBryan Whitehead #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 59923f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 60023f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 60123f0703cSBryan Whitehead 60223f0703cSBryan Whitehead #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 60323f0703cSBryan Whitehead #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 60423f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 60523f0703cSBryan Whitehead #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 60623f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 60723f0703cSBryan Whitehead 60823f0703cSBryan Whitehead #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 60923f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 61023f0703cSBryan Whitehead #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 61123f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 61223f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 61323f0703cSBryan Whitehead ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 61423f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 61523f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 61623f0703cSBryan Whitehead ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 61723f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 61823f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 61923f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 62023f0703cSBryan Whitehead (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 62123f0703cSBryan Whitehead 62223f0703cSBryan Whitehead #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 62323f0703cSBryan Whitehead #define TX_CFG_B_TDMABL_512_ (0x00040000) 62423f0703cSBryan Whitehead #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 62523f0703cSBryan Whitehead 62623f0703cSBryan Whitehead #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 62723f0703cSBryan Whitehead 62823f0703cSBryan Whitehead #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 62923f0703cSBryan Whitehead 63023f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 63123f0703cSBryan Whitehead 63223f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 63323f0703cSBryan Whitehead 63423f0703cSBryan Whitehead #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 63523f0703cSBryan Whitehead 63623f0703cSBryan Whitehead #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 63723f0703cSBryan Whitehead #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 63823f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 63923f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 64023f0703cSBryan Whitehead 64123f0703cSBryan Whitehead #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 64223f0703cSBryan Whitehead #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 64323f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 64423f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 64523f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 64623f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 64723f0703cSBryan Whitehead 64869584604SBryan Whitehead #define OTP_PWR_DN (0x1000) 64969584604SBryan Whitehead #define OTP_PWR_DN_PWRDN_N_ BIT(0) 65069584604SBryan Whitehead 651662a14d0SBryan Whitehead #define OTP_ADDR_HIGH (0x1004) 652662a14d0SBryan Whitehead #define OTP_ADDR_LOW (0x1008) 65369584604SBryan Whitehead 65469584604SBryan Whitehead #define OTP_PRGM_DATA (0x1010) 65569584604SBryan Whitehead 65669584604SBryan Whitehead #define OTP_PRGM_MODE (0x1014) 65769584604SBryan Whitehead #define OTP_PRGM_MODE_BYTE_ BIT(0) 65869584604SBryan Whitehead 659662a14d0SBryan Whitehead #define OTP_READ_DATA (0x1018) 660662a14d0SBryan Whitehead 661662a14d0SBryan Whitehead #define OTP_FUNC_CMD (0x1020) 662662a14d0SBryan Whitehead #define OTP_FUNC_CMD_READ_ BIT(0) 663662a14d0SBryan Whitehead 66469584604SBryan Whitehead #define OTP_TST_CMD (0x1024) 66569584604SBryan Whitehead #define OTP_TST_CMD_PRGVRFY_ BIT(3) 66669584604SBryan Whitehead 66769584604SBryan Whitehead #define OTP_CMD_GO (0x1028) 66869584604SBryan Whitehead #define OTP_CMD_GO_GO_ BIT(0) 66969584604SBryan Whitehead 67069584604SBryan Whitehead #define OTP_STATUS (0x1030) 67169584604SBryan Whitehead #define OTP_STATUS_BUSY_ BIT(0) 67269584604SBryan Whitehead 673d808f7caSRaju Lakkaraju /* Hearthstone OTP block registers */ 674d808f7caSRaju Lakkaraju #define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \ 675d808f7caSRaju Lakkaraju ETH_OTP_REG_ADDR_BASE) 676d808f7caSRaju Lakkaraju #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0) 677d808f7caSRaju Lakkaraju #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4) 678d808f7caSRaju Lakkaraju #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8) 679d808f7caSRaju Lakkaraju #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10) 680d808f7caSRaju Lakkaraju #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14) 681d808f7caSRaju Lakkaraju #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18) 682d808f7caSRaju Lakkaraju #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20) 683d808f7caSRaju Lakkaraju #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24) 684d808f7caSRaju Lakkaraju #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28) 685d808f7caSRaju Lakkaraju #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30) 686d808f7caSRaju Lakkaraju 68723f0703cSBryan Whitehead /* MAC statistics registers */ 68823f0703cSBryan Whitehead #define STAT_RX_FCS_ERRORS (0x1200) 68923f0703cSBryan Whitehead #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 6908114e8a2SBryan Whitehead #define STAT_RX_FRAGMENT_ERRORS (0x1208) 69123f0703cSBryan Whitehead #define STAT_RX_JABBER_ERRORS (0x120C) 69223f0703cSBryan Whitehead #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 69323f0703cSBryan Whitehead #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 69423f0703cSBryan Whitehead #define STAT_RX_DROPPED_FRAMES (0x1218) 69523f0703cSBryan Whitehead #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 69623f0703cSBryan Whitehead #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 69723f0703cSBryan Whitehead #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 6988114e8a2SBryan Whitehead #define STAT_RX_UNICAST_FRAMES (0x1228) 6998114e8a2SBryan Whitehead #define STAT_RX_BROADCAST_FRAMES (0x122C) 70023f0703cSBryan Whitehead #define STAT_RX_MULTICAST_FRAMES (0x1230) 7018114e8a2SBryan Whitehead #define STAT_RX_PAUSE_FRAMES (0x1234) 7028114e8a2SBryan Whitehead #define STAT_RX_64_BYTE_FRAMES (0x1238) 7038114e8a2SBryan Whitehead #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 7048114e8a2SBryan Whitehead #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 7058114e8a2SBryan Whitehead #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 7068114e8a2SBryan Whitehead #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 7078114e8a2SBryan Whitehead #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 7088114e8a2SBryan Whitehead #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 70923f0703cSBryan Whitehead #define STAT_RX_TOTAL_FRAMES (0x1254) 7108114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 7118114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TIME (0x125C) 7128114e8a2SBryan Whitehead #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 71323f0703cSBryan Whitehead 71423f0703cSBryan Whitehead #define STAT_TX_FCS_ERRORS (0x1280) 71523f0703cSBryan Whitehead #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 71623f0703cSBryan Whitehead #define STAT_TX_CARRIER_ERRORS (0x1288) 7178114e8a2SBryan Whitehead #define STAT_TX_BAD_BYTE_COUNT (0x128C) 71823f0703cSBryan Whitehead #define STAT_TX_SINGLE_COLLISIONS (0x1290) 71923f0703cSBryan Whitehead #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 72023f0703cSBryan Whitehead #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 72123f0703cSBryan Whitehead #define STAT_TX_LATE_COLLISIONS (0x129C) 72223f0703cSBryan Whitehead #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 72323f0703cSBryan Whitehead #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 72423f0703cSBryan Whitehead #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 7258114e8a2SBryan Whitehead #define STAT_TX_UNICAST_FRAMES (0x12AC) 7268114e8a2SBryan Whitehead #define STAT_TX_BROADCAST_FRAMES (0x12B0) 72723f0703cSBryan Whitehead #define STAT_TX_MULTICAST_FRAMES (0x12B4) 7288114e8a2SBryan Whitehead #define STAT_TX_PAUSE_FRAMES (0x12B8) 7298114e8a2SBryan Whitehead #define STAT_TX_64_BYTE_FRAMES (0x12BC) 7308114e8a2SBryan Whitehead #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 7318114e8a2SBryan Whitehead #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 7328114e8a2SBryan Whitehead #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 7338114e8a2SBryan Whitehead #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 7348114e8a2SBryan Whitehead #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 7358114e8a2SBryan Whitehead #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 73623f0703cSBryan Whitehead #define STAT_TX_TOTAL_FRAMES (0x12D8) 7378114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 7388114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TIME (0x12E0) 7398114e8a2SBryan Whitehead #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 74023f0703cSBryan Whitehead 74123f0703cSBryan Whitehead /* End of Register definitions */ 74223f0703cSBryan Whitehead 74323f0703cSBryan Whitehead #define LAN743X_MAX_RX_CHANNELS (4) 74423f0703cSBryan Whitehead #define LAN743X_MAX_TX_CHANNELS (1) 745cf9aaea8SRaju Lakkaraju #define PCI11X1X_MAX_TX_CHANNELS (4) 74623f0703cSBryan Whitehead struct lan743x_adapter; 74723f0703cSBryan Whitehead 74823f0703cSBryan Whitehead #define LAN743X_USED_RX_CHANNELS (4) 74923f0703cSBryan Whitehead #define LAN743X_USED_TX_CHANNELS (1) 750cf9aaea8SRaju Lakkaraju #define PCI11X1X_USED_TX_CHANNELS (4) 75123f0703cSBryan Whitehead #define LAN743X_INT_MOD (400) 75223f0703cSBryan Whitehead 75323f0703cSBryan Whitehead #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 75423f0703cSBryan Whitehead #error Invalid LAN743X_USED_RX_CHANNELS 75523f0703cSBryan Whitehead #endif 75623f0703cSBryan Whitehead #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 75723f0703cSBryan Whitehead #error Invalid LAN743X_USED_TX_CHANNELS 75823f0703cSBryan Whitehead #endif 759cf9aaea8SRaju Lakkaraju #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS) 760cf9aaea8SRaju Lakkaraju #error Invalid PCI11X1X_USED_TX_CHANNELS 761cf9aaea8SRaju Lakkaraju #endif 76223f0703cSBryan Whitehead 76323f0703cSBryan Whitehead /* PCI */ 76423f0703cSBryan Whitehead /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 76523f0703cSBryan Whitehead #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 76623f0703cSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 7674df5ce9bSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) 768bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A011 (0xA011) 769bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A041 (0xA041) 77023f0703cSBryan Whitehead 77123f0703cSBryan Whitehead #define PCI_CONFIG_LENGTH (0x1000) 77223f0703cSBryan Whitehead 77323f0703cSBryan Whitehead /* CSR */ 77423f0703cSBryan Whitehead #define CSR_LENGTH (0x2000) 77523f0703cSBryan Whitehead 77623f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 77723f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 77823f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 77923f0703cSBryan Whitehead 78023f0703cSBryan Whitehead struct lan743x_csr { 78123f0703cSBryan Whitehead u32 flags; 78223f0703cSBryan Whitehead u8 __iomem *csr_address; 78323f0703cSBryan Whitehead u32 id_rev; 78423f0703cSBryan Whitehead u32 fpga_rev; 78523f0703cSBryan Whitehead }; 78623f0703cSBryan Whitehead 78723f0703cSBryan Whitehead /* INTERRUPTS */ 78823f0703cSBryan Whitehead typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 78923f0703cSBryan Whitehead 79023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 79123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 79223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 79323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 79423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 79523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 79623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 79723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 79823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 79923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 80023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 80123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 80223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 80323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 80423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 80523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 80623f0703cSBryan Whitehead 80723f0703cSBryan Whitehead struct lan743x_vector { 80823f0703cSBryan Whitehead int irq; 80923f0703cSBryan Whitehead u32 flags; 81023f0703cSBryan Whitehead struct lan743x_adapter *adapter; 81123f0703cSBryan Whitehead int vector_index; 81223f0703cSBryan Whitehead u32 int_mask; 81323f0703cSBryan Whitehead lan743x_vector_handler handler; 81423f0703cSBryan Whitehead void *context; 81523f0703cSBryan Whitehead }; 81623f0703cSBryan Whitehead 81723f0703cSBryan Whitehead #define LAN743X_MAX_VECTOR_COUNT (8) 818ac16b6ebSRaju Lakkaraju #define PCI11X1X_MAX_VECTOR_COUNT (16) 81923f0703cSBryan Whitehead 82023f0703cSBryan Whitehead struct lan743x_intr { 82123f0703cSBryan Whitehead int flags; 82223f0703cSBryan Whitehead 82323f0703cSBryan Whitehead unsigned int irq; 82423f0703cSBryan Whitehead 825ac16b6ebSRaju Lakkaraju struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT]; 82623f0703cSBryan Whitehead int number_of_vectors; 82723f0703cSBryan Whitehead bool using_vectors; 82823f0703cSBryan Whitehead 829470dfd80SSven Van Asbroeck bool software_isr_flag; 830470dfd80SSven Van Asbroeck wait_queue_head_t software_isr_wq; 83123f0703cSBryan Whitehead }; 83223f0703cSBryan Whitehead 83323f0703cSBryan Whitehead #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 83423f0703cSBryan Whitehead 83523f0703cSBryan Whitehead /* PHY */ 83623f0703cSBryan Whitehead struct lan743x_phy { 83723f0703cSBryan Whitehead bool fc_autoneg; 83823f0703cSBryan Whitehead u8 fc_request_control; 83923f0703cSBryan Whitehead }; 84023f0703cSBryan Whitehead 84123f0703cSBryan Whitehead /* TX */ 84223f0703cSBryan Whitehead struct lan743x_tx_descriptor; 84323f0703cSBryan Whitehead struct lan743x_tx_buffer_info; 84423f0703cSBryan Whitehead 84523f0703cSBryan Whitehead #define GPIO_QUEUE_STARTED (0) 84623f0703cSBryan Whitehead #define GPIO_TX_FUNCTION (1) 84723f0703cSBryan Whitehead #define GPIO_TX_COMPLETION (2) 84823f0703cSBryan Whitehead #define GPIO_TX_FRAGMENT (3) 84923f0703cSBryan Whitehead 85023f0703cSBryan Whitehead #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 85123f0703cSBryan Whitehead 85207624df1SBryan Whitehead #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 85307624df1SBryan Whitehead #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 85407624df1SBryan Whitehead 85523f0703cSBryan Whitehead struct lan743x_tx { 85623f0703cSBryan Whitehead struct lan743x_adapter *adapter; 85707624df1SBryan Whitehead u32 ts_flags; 85823f0703cSBryan Whitehead u32 vector_flags; 85923f0703cSBryan Whitehead int channel_number; 86023f0703cSBryan Whitehead 86123f0703cSBryan Whitehead int ring_size; 86223f0703cSBryan Whitehead size_t ring_allocation_size; 86323f0703cSBryan Whitehead struct lan743x_tx_descriptor *ring_cpu_ptr; 86423f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 86523f0703cSBryan Whitehead /* ring_lock: used to prevent concurrent access to tx ring */ 86623f0703cSBryan Whitehead spinlock_t ring_lock; 86723f0703cSBryan Whitehead u32 frame_flags; 86823f0703cSBryan Whitehead u32 frame_first; 86923f0703cSBryan Whitehead u32 frame_data0; 87023f0703cSBryan Whitehead u32 frame_tail; 87123f0703cSBryan Whitehead 87223f0703cSBryan Whitehead struct lan743x_tx_buffer_info *buffer_info; 87323f0703cSBryan Whitehead 87446251282SAlexey Denisov __le32 *head_cpu_ptr; 87523f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 87623f0703cSBryan Whitehead int last_head; 87723f0703cSBryan Whitehead int last_tail; 87823f0703cSBryan Whitehead 87923f0703cSBryan Whitehead struct napi_struct napi; 880bc1962e5SRaju Lakkaraju u32 frame_count; 88123f0703cSBryan Whitehead 88223f0703cSBryan Whitehead struct sk_buff *overflow_skb; 88323f0703cSBryan Whitehead }; 88423f0703cSBryan Whitehead 88507624df1SBryan Whitehead void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 88607624df1SBryan Whitehead bool enable_timestamping, 88707624df1SBryan Whitehead bool enable_onestep_sync); 88807624df1SBryan Whitehead 88923f0703cSBryan Whitehead /* RX */ 89023f0703cSBryan Whitehead struct lan743x_rx_descriptor; 89123f0703cSBryan Whitehead struct lan743x_rx_buffer_info; 89223f0703cSBryan Whitehead 89323f0703cSBryan Whitehead struct lan743x_rx { 89423f0703cSBryan Whitehead struct lan743x_adapter *adapter; 89523f0703cSBryan Whitehead u32 vector_flags; 89623f0703cSBryan Whitehead int channel_number; 89723f0703cSBryan Whitehead 89823f0703cSBryan Whitehead int ring_size; 89923f0703cSBryan Whitehead size_t ring_allocation_size; 90023f0703cSBryan Whitehead struct lan743x_rx_descriptor *ring_cpu_ptr; 90123f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 90223f0703cSBryan Whitehead 90323f0703cSBryan Whitehead struct lan743x_rx_buffer_info *buffer_info; 90423f0703cSBryan Whitehead 90546251282SAlexey Denisov __le32 *head_cpu_ptr; 90623f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 90723f0703cSBryan Whitehead u32 last_head; 90823f0703cSBryan Whitehead u32 last_tail; 90923f0703cSBryan Whitehead 91023f0703cSBryan Whitehead struct napi_struct napi; 91123f0703cSBryan Whitehead 91223f0703cSBryan Whitehead u32 frame_count; 913a8db76d4SSven Van Asbroeck 914a8db76d4SSven Van Asbroeck struct sk_buff *skb_head, *skb_tail; 91523f0703cSBryan Whitehead }; 91623f0703cSBryan Whitehead 91723f0703cSBryan Whitehead struct lan743x_adapter { 91823f0703cSBryan Whitehead struct net_device *netdev; 91923f0703cSBryan Whitehead struct mii_bus *mdiobus; 92023f0703cSBryan Whitehead int msg_enable; 9214d94282aSBryan Whitehead #ifdef CONFIG_PM 9224d94282aSBryan Whitehead u32 wolopts; 923*6b3768acSRaju Lakkaraju u8 sopass[SOPASS_MAX]; 9244d94282aSBryan Whitehead #endif 92523f0703cSBryan Whitehead struct pci_dev *pdev; 92623f0703cSBryan Whitehead struct lan743x_csr csr; 92723f0703cSBryan Whitehead struct lan743x_intr intr; 92823f0703cSBryan Whitehead 92907624df1SBryan Whitehead struct lan743x_gpio gpio; 93007624df1SBryan Whitehead struct lan743x_ptp ptp; 93107624df1SBryan Whitehead 93223f0703cSBryan Whitehead u8 mac_address[ETH_ALEN]; 93323f0703cSBryan Whitehead 93423f0703cSBryan Whitehead struct lan743x_phy phy; 935cf9aaea8SRaju Lakkaraju struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS]; 936cf9aaea8SRaju Lakkaraju struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; 937cf9aaea8SRaju Lakkaraju bool is_pci11x1x; 938a46d9d37SRaju Lakkaraju bool is_sgmii_en; 939cdea83ccSRaju Lakkaraju /* protect ethernet syslock */ 940cdea83ccSRaju Lakkaraju spinlock_t eth_syslock_spinlock; 941cdea83ccSRaju Lakkaraju bool eth_syslock_en; 942cdea83ccSRaju Lakkaraju u32 eth_syslock_acquire_cnt; 943cf9aaea8SRaju Lakkaraju u8 max_tx_channels; 944cf9aaea8SRaju Lakkaraju u8 used_tx_channels; 945ac16b6ebSRaju Lakkaraju u8 max_vector_count; 946662a14d0SBryan Whitehead 947662a14d0SBryan Whitehead #define LAN743X_ADAPTER_FLAG_OTP BIT(0) 948662a14d0SBryan Whitehead u32 flags; 949*6b3768acSRaju Lakkaraju u32 hw_cfg; 95023f0703cSBryan Whitehead }; 95123f0703cSBryan Whitehead 95223f0703cSBryan Whitehead #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 95323f0703cSBryan Whitehead 95423f0703cSBryan Whitehead #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 95523f0703cSBryan Whitehead #define INTR_FLAG_MSI_ENABLED BIT(8) 95623f0703cSBryan Whitehead #define INTR_FLAG_MSIX_ENABLED BIT(9) 95723f0703cSBryan Whitehead 95823f0703cSBryan Whitehead #define MAC_MII_READ 1 95923f0703cSBryan Whitehead #define MAC_MII_WRITE 0 96023f0703cSBryan Whitehead 96123f0703cSBryan Whitehead #define PHY_FLAG_OPENED BIT(0) 96223f0703cSBryan Whitehead #define PHY_FLAG_ATTACHED BIT(1) 96323f0703cSBryan Whitehead 96423f0703cSBryan Whitehead #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 96523f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 96623f0703cSBryan Whitehead #else 96723f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 96823f0703cSBryan Whitehead #endif 96923f0703cSBryan Whitehead #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 97023f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_16 (16) 97123f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_32 (32) 97223f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_64 (64) 97323f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_128 (128) 97423f0703cSBryan Whitehead #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 97523f0703cSBryan Whitehead 97623f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 97723f0703cSBryan Whitehead (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 97823f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 97923f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 98023f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 98123f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 98223f0703cSBryan Whitehead 98323f0703cSBryan Whitehead /* TX Descriptor bits */ 98423f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 98523f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 98623f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 98723f0703cSBryan Whitehead #define TX_DESC_DATA0_FS_ (0x20000000) 98823f0703cSBryan Whitehead #define TX_DESC_DATA0_LS_ (0x10000000) 98923f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_ (0x08000000) 99023f0703cSBryan Whitehead #define TX_DESC_DATA0_IOC_ (0x04000000) 99123f0703cSBryan Whitehead #define TX_DESC_DATA0_ICE_ (0x00400000) 99223f0703cSBryan Whitehead #define TX_DESC_DATA0_IPE_ (0x00200000) 99323f0703cSBryan Whitehead #define TX_DESC_DATA0_TPE_ (0x00100000) 99423f0703cSBryan Whitehead #define TX_DESC_DATA0_FCS_ (0x00020000) 99507624df1SBryan Whitehead #define TX_DESC_DATA0_TSE_ (0x00010000) 99623f0703cSBryan Whitehead #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 99723f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 99823f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 99923f0703cSBryan Whitehead #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 100023f0703cSBryan Whitehead 100123f0703cSBryan Whitehead struct lan743x_tx_descriptor { 100246251282SAlexey Denisov __le32 data0; 100346251282SAlexey Denisov __le32 data1; 100446251282SAlexey Denisov __le32 data2; 100546251282SAlexey Denisov __le32 data3; 100623f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 100723f0703cSBryan Whitehead 100823f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 100907624df1SBryan Whitehead #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 101023f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 101123f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 101223f0703cSBryan Whitehead struct lan743x_tx_buffer_info { 101323f0703cSBryan Whitehead int flags; 101423f0703cSBryan Whitehead struct sk_buff *skb; 101523f0703cSBryan Whitehead dma_addr_t dma_ptr; 101623f0703cSBryan Whitehead unsigned int buffer_length; 101723f0703cSBryan Whitehead }; 101823f0703cSBryan Whitehead 101923f0703cSBryan Whitehead #define LAN743X_TX_RING_SIZE (50) 102023f0703cSBryan Whitehead 102123f0703cSBryan Whitehead /* OWN bit is set. ie, Descs are owned by RX DMAC */ 102223f0703cSBryan Whitehead #define RX_DESC_DATA0_OWN_ (0x00008000) 102323f0703cSBryan Whitehead /* OWN bit is clear. ie, Descs are owned by host */ 102423f0703cSBryan Whitehead #define RX_DESC_DATA0_FS_ (0x80000000) 102523f0703cSBryan Whitehead #define RX_DESC_DATA0_LS_ (0x40000000) 102623f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 102723f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 102823f0703cSBryan Whitehead (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 102923f0703cSBryan Whitehead #define RX_DESC_DATA0_EXT_ (0x00004000) 103023f0703cSBryan Whitehead #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 103123f0703cSBryan Whitehead #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 103223f0703cSBryan Whitehead 103323f0703cSBryan Whitehead #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 103423f0703cSBryan Whitehead #error NET_IP_ALIGN must be 0 or 2 103523f0703cSBryan Whitehead #endif 103623f0703cSBryan Whitehead 103723f0703cSBryan Whitehead #define RX_HEAD_PADDING NET_IP_ALIGN 103823f0703cSBryan Whitehead 103923f0703cSBryan Whitehead struct lan743x_rx_descriptor { 104046251282SAlexey Denisov __le32 data0; 104146251282SAlexey Denisov __le32 data1; 104246251282SAlexey Denisov __le32 data2; 104346251282SAlexey Denisov __le32 data3; 104423f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 104523f0703cSBryan Whitehead 104623f0703cSBryan Whitehead #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 104723f0703cSBryan Whitehead struct lan743x_rx_buffer_info { 104823f0703cSBryan Whitehead int flags; 104923f0703cSBryan Whitehead struct sk_buff *skb; 105023f0703cSBryan Whitehead 105123f0703cSBryan Whitehead dma_addr_t dma_ptr; 105223f0703cSBryan Whitehead unsigned int buffer_length; 105323f0703cSBryan Whitehead }; 105423f0703cSBryan Whitehead 1055a1f16275SYuiko Oshino #define LAN743X_RX_RING_SIZE (128) 105623f0703cSBryan Whitehead 105723f0703cSBryan Whitehead #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 1058a8db76d4SSven Van Asbroeck #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) 105923f0703cSBryan Whitehead 10608114e8a2SBryan Whitehead u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 10618114e8a2SBryan Whitehead void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 10628114e8a2SBryan Whitehead 106323f0703cSBryan Whitehead #endif /* _LAN743X_H */ 1064