123f0703cSBryan Whitehead /* SPDX-License-Identifier: GPL-2.0+ */ 223f0703cSBryan Whitehead /* Copyright (C) 2018 Microchip Technology Inc. */ 323f0703cSBryan Whitehead 423f0703cSBryan Whitehead #ifndef _LAN743X_H 523f0703cSBryan Whitehead #define _LAN743X_H 623f0703cSBryan Whitehead 723f0703cSBryan Whitehead #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 823f0703cSBryan Whitehead #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 923f0703cSBryan Whitehead #define DRIVER_NAME "lan743x" 1023f0703cSBryan Whitehead 1123f0703cSBryan Whitehead /* Register Definitions */ 1223f0703cSBryan Whitehead #define ID_REV (0x00) 1323f0703cSBryan Whitehead #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 1423f0703cSBryan Whitehead (((id_rev) & 0xFFF00000) == 0x74300000) 1523f0703cSBryan Whitehead #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 1623f0703cSBryan Whitehead #define ID_REV_CHIP_REV_A0_ (0x00000000) 1723f0703cSBryan Whitehead #define ID_REV_CHIP_REV_B0_ (0x00000010) 1823f0703cSBryan Whitehead 1923f0703cSBryan Whitehead #define FPGA_REV (0x04) 2023f0703cSBryan Whitehead #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 2123f0703cSBryan Whitehead #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 2223f0703cSBryan Whitehead 2323f0703cSBryan Whitehead #define HW_CFG (0x010) 2423f0703cSBryan Whitehead #define HW_CFG_LRST_ BIT(1) 2523f0703cSBryan Whitehead 2623f0703cSBryan Whitehead #define PMT_CTL (0x014) 2723f0703cSBryan Whitehead #define PMT_CTL_READY_ BIT(7) 2823f0703cSBryan Whitehead #define PMT_CTL_ETH_PHY_RST_ BIT(4) 2923f0703cSBryan Whitehead 3023f0703cSBryan Whitehead #define DP_SEL (0x024) 3123f0703cSBryan Whitehead #define DP_SEL_DPRDY_ BIT(31) 3223f0703cSBryan Whitehead #define DP_SEL_MASK_ (0x0000001F) 3323f0703cSBryan Whitehead #define DP_SEL_RFE_RAM (0x00000001) 3423f0703cSBryan Whitehead 3523f0703cSBryan Whitehead #define DP_SEL_VHF_HASH_LEN (16) 3623f0703cSBryan Whitehead #define DP_SEL_VHF_VLAN_LEN (128) 3723f0703cSBryan Whitehead 3823f0703cSBryan Whitehead #define DP_CMD (0x028) 3923f0703cSBryan Whitehead #define DP_CMD_WRITE_ (0x00000001) 4023f0703cSBryan Whitehead 4123f0703cSBryan Whitehead #define DP_ADDR (0x02C) 4223f0703cSBryan Whitehead 4323f0703cSBryan Whitehead #define DP_DATA_0 (0x030) 4423f0703cSBryan Whitehead 4523f0703cSBryan Whitehead #define FCT_RX_CTL (0xAC) 4623f0703cSBryan Whitehead #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 4723f0703cSBryan Whitehead #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 4823f0703cSBryan Whitehead #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 4923f0703cSBryan Whitehead 5023f0703cSBryan Whitehead #define FCT_TX_CTL (0xC4) 5123f0703cSBryan Whitehead #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 5223f0703cSBryan Whitehead #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 5323f0703cSBryan Whitehead #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 5423f0703cSBryan Whitehead 5523f0703cSBryan Whitehead #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 5623f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 5723f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 5823f0703cSBryan Whitehead ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 5923f0703cSBryan Whitehead #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 6023f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 6123f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 6223f0703cSBryan Whitehead ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 6323f0703cSBryan Whitehead 6423f0703cSBryan Whitehead #define MAC_CR (0x100) 6523f0703cSBryan Whitehead #define MAC_CR_ADD_ BIT(12) 6623f0703cSBryan Whitehead #define MAC_CR_ASD_ BIT(11) 6723f0703cSBryan Whitehead #define MAC_CR_CNTR_RST_ BIT(5) 6823f0703cSBryan Whitehead #define MAC_CR_RST_ BIT(0) 6923f0703cSBryan Whitehead 7023f0703cSBryan Whitehead #define MAC_RX (0x104) 7123f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_SHIFT_ (16) 7223f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 7323f0703cSBryan Whitehead #define MAC_RX_RXD_ BIT(1) 7423f0703cSBryan Whitehead #define MAC_RX_RXEN_ BIT(0) 7523f0703cSBryan Whitehead 7623f0703cSBryan Whitehead #define MAC_TX (0x108) 7723f0703cSBryan Whitehead #define MAC_TX_TXD_ BIT(1) 7823f0703cSBryan Whitehead #define MAC_TX_TXEN_ BIT(0) 7923f0703cSBryan Whitehead 8023f0703cSBryan Whitehead #define MAC_FLOW (0x10C) 8123f0703cSBryan Whitehead #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 8223f0703cSBryan Whitehead #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 8323f0703cSBryan Whitehead #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 8423f0703cSBryan Whitehead 8523f0703cSBryan Whitehead #define MAC_RX_ADDRH (0x118) 8623f0703cSBryan Whitehead 8723f0703cSBryan Whitehead #define MAC_RX_ADDRL (0x11C) 8823f0703cSBryan Whitehead 8923f0703cSBryan Whitehead #define MAC_MII_ACC (0x120) 9023f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 9123f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 9223f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 9323f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 9423f0703cSBryan Whitehead #define MAC_MII_ACC_MII_READ_ (0x00000000) 9523f0703cSBryan Whitehead #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 9623f0703cSBryan Whitehead #define MAC_MII_ACC_MII_BUSY_ BIT(0) 9723f0703cSBryan Whitehead 9823f0703cSBryan Whitehead #define MAC_MII_DATA (0x124) 9923f0703cSBryan Whitehead 10023f0703cSBryan Whitehead /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 10123f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 10223f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 10323f0703cSBryan Whitehead 10423f0703cSBryan Whitehead /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 10523f0703cSBryan Whitehead #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 10623f0703cSBryan Whitehead 10723f0703cSBryan Whitehead #define RFE_CTL (0x508) 10823f0703cSBryan Whitehead #define RFE_CTL_AB_ BIT(10) 10923f0703cSBryan Whitehead #define RFE_CTL_AM_ BIT(9) 11023f0703cSBryan Whitehead #define RFE_CTL_AU_ BIT(8) 11123f0703cSBryan Whitehead #define RFE_CTL_MCAST_HASH_ BIT(3) 11223f0703cSBryan Whitehead #define RFE_CTL_DA_PERFECT_ BIT(1) 11323f0703cSBryan Whitehead 11423f0703cSBryan Whitehead #define INT_STS (0x780) 11523f0703cSBryan Whitehead #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 11623f0703cSBryan Whitehead #define INT_BIT_ALL_RX_ (0x0F000000) 11723f0703cSBryan Whitehead #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 11823f0703cSBryan Whitehead #define INT_BIT_ALL_TX_ (0x000F0000) 11923f0703cSBryan Whitehead #define INT_BIT_SW_GP_ BIT(9) 12023f0703cSBryan Whitehead #define INT_BIT_ALL_OTHER_ (0x00000280) 12123f0703cSBryan Whitehead #define INT_BIT_MAS_ BIT(0) 12223f0703cSBryan Whitehead 12323f0703cSBryan Whitehead #define INT_SET (0x784) 12423f0703cSBryan Whitehead 12523f0703cSBryan Whitehead #define INT_EN_SET (0x788) 12623f0703cSBryan Whitehead 12723f0703cSBryan Whitehead #define INT_EN_CLR (0x78C) 12823f0703cSBryan Whitehead 12923f0703cSBryan Whitehead #define INT_STS_R2C (0x790) 13023f0703cSBryan Whitehead 13123f0703cSBryan Whitehead #define INT_VEC_EN_SET (0x794) 13223f0703cSBryan Whitehead #define INT_VEC_EN_CLR (0x798) 13323f0703cSBryan Whitehead #define INT_VEC_EN_AUTO_CLR (0x79C) 13423f0703cSBryan Whitehead #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 13523f0703cSBryan Whitehead 13623f0703cSBryan Whitehead #define INT_VEC_MAP0 (0x7A0) 13723f0703cSBryan Whitehead #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 13823f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 13923f0703cSBryan Whitehead 14023f0703cSBryan Whitehead #define INT_VEC_MAP1 (0x7A4) 14123f0703cSBryan Whitehead #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 14223f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 14323f0703cSBryan Whitehead 14423f0703cSBryan Whitehead #define INT_VEC_MAP2 (0x7A8) 14523f0703cSBryan Whitehead 14623f0703cSBryan Whitehead #define INT_MOD_MAP0 (0x7B0) 14723f0703cSBryan Whitehead 14823f0703cSBryan Whitehead #define INT_MOD_MAP1 (0x7B4) 14923f0703cSBryan Whitehead 15023f0703cSBryan Whitehead #define INT_MOD_MAP2 (0x7B8) 15123f0703cSBryan Whitehead 15223f0703cSBryan Whitehead #define INT_MOD_CFG0 (0x7C0) 15323f0703cSBryan Whitehead #define INT_MOD_CFG1 (0x7C4) 15423f0703cSBryan Whitehead #define INT_MOD_CFG2 (0x7C8) 15523f0703cSBryan Whitehead #define INT_MOD_CFG3 (0x7CC) 15623f0703cSBryan Whitehead #define INT_MOD_CFG4 (0x7D0) 15723f0703cSBryan Whitehead #define INT_MOD_CFG5 (0x7D4) 15823f0703cSBryan Whitehead #define INT_MOD_CFG6 (0x7D8) 15923f0703cSBryan Whitehead #define INT_MOD_CFG7 (0x7DC) 16023f0703cSBryan Whitehead 16123f0703cSBryan Whitehead #define DMAC_CFG (0xC00) 16223f0703cSBryan Whitehead #define DMAC_CFG_COAL_EN_ BIT(16) 16323f0703cSBryan Whitehead #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 16423f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 16523f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 16623f0703cSBryan Whitehead ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 16723f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 16823f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 16923f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 17023f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 17123f0703cSBryan Whitehead 17223f0703cSBryan Whitehead #define DMAC_COAL_CFG (0xC04) 17323f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 17423f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 17523f0703cSBryan Whitehead ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 17623f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 17723f0703cSBryan Whitehead #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 17823f0703cSBryan Whitehead #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 17923f0703cSBryan Whitehead #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 18023f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 18123f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 18223f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 18323f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 18423f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 18523f0703cSBryan Whitehead (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 18623f0703cSBryan Whitehead 18723f0703cSBryan Whitehead #define DMAC_OBFF_CFG (0xC08) 18823f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 18923f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_SET_(val) \ 19023f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 19123f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 19223f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_SET_(val) \ 19323f0703cSBryan Whitehead (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 19423f0703cSBryan Whitehead 19523f0703cSBryan Whitehead #define DMAC_CMD (0xC0C) 19623f0703cSBryan Whitehead #define DMAC_CMD_SWR_ BIT(31) 19723f0703cSBryan Whitehead #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 19823f0703cSBryan Whitehead #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 19923f0703cSBryan Whitehead #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 20023f0703cSBryan Whitehead #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 20123f0703cSBryan Whitehead #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 20223f0703cSBryan Whitehead #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 20323f0703cSBryan Whitehead 20423f0703cSBryan Whitehead #define DMAC_INT_STS (0xC10) 20523f0703cSBryan Whitehead #define DMAC_INT_EN_SET (0xC14) 20623f0703cSBryan Whitehead #define DMAC_INT_EN_CLR (0xC18) 20723f0703cSBryan Whitehead #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 20823f0703cSBryan Whitehead #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 20923f0703cSBryan Whitehead 21023f0703cSBryan Whitehead #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 21123f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 21223f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 21323f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 21423f0703cSBryan Whitehead ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 21523f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 21623f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 21723f0703cSBryan Whitehead ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 21823f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 21923f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 22023f0703cSBryan Whitehead ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 22123f0703cSBryan Whitehead #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 22223f0703cSBryan Whitehead 22323f0703cSBryan Whitehead #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 22423f0703cSBryan Whitehead #define RX_CFG_B_TS_ALL_RX_ BIT(29) 22523f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 22623f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_0_ (0x00000000) 22723f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_2_ (0x02000000) 22823f0703cSBryan Whitehead #define RX_CFG_B_RDMABL_512_ (0x00040000) 22923f0703cSBryan Whitehead #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 23023f0703cSBryan Whitehead 23123f0703cSBryan Whitehead #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 23223f0703cSBryan Whitehead 23323f0703cSBryan Whitehead #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 23423f0703cSBryan Whitehead 23523f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 23623f0703cSBryan Whitehead 23723f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 23823f0703cSBryan Whitehead 23923f0703cSBryan Whitehead #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 24023f0703cSBryan Whitehead 24123f0703cSBryan Whitehead #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 24223f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 24323f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 24423f0703cSBryan Whitehead 24523f0703cSBryan Whitehead #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 24623f0703cSBryan Whitehead #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 24723f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 24823f0703cSBryan Whitehead #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 24923f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 25023f0703cSBryan Whitehead 25123f0703cSBryan Whitehead #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 25223f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 25323f0703cSBryan Whitehead #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 25423f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 25523f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 25623f0703cSBryan Whitehead ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 25723f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 25823f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 25923f0703cSBryan Whitehead ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 26023f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 26123f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 26223f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 26323f0703cSBryan Whitehead (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 26423f0703cSBryan Whitehead 26523f0703cSBryan Whitehead #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 26623f0703cSBryan Whitehead #define TX_CFG_B_TDMABL_512_ (0x00040000) 26723f0703cSBryan Whitehead #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 26823f0703cSBryan Whitehead 26923f0703cSBryan Whitehead #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 27023f0703cSBryan Whitehead 27123f0703cSBryan Whitehead #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 27223f0703cSBryan Whitehead 27323f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 27423f0703cSBryan Whitehead 27523f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 27623f0703cSBryan Whitehead 27723f0703cSBryan Whitehead #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 27823f0703cSBryan Whitehead 27923f0703cSBryan Whitehead #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 28023f0703cSBryan Whitehead #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 28123f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 28223f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 28323f0703cSBryan Whitehead 28423f0703cSBryan Whitehead #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 28523f0703cSBryan Whitehead #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 28623f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 28723f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 28823f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 28923f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 29023f0703cSBryan Whitehead 29123f0703cSBryan Whitehead /* MAC statistics registers */ 29223f0703cSBryan Whitehead #define STAT_RX_FCS_ERRORS (0x1200) 29323f0703cSBryan Whitehead #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 29423f0703cSBryan Whitehead #define STAT_RX_JABBER_ERRORS (0x120C) 29523f0703cSBryan Whitehead #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 29623f0703cSBryan Whitehead #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 29723f0703cSBryan Whitehead #define STAT_RX_DROPPED_FRAMES (0x1218) 29823f0703cSBryan Whitehead #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 29923f0703cSBryan Whitehead #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 30023f0703cSBryan Whitehead #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 30123f0703cSBryan Whitehead #define STAT_RX_MULTICAST_FRAMES (0x1230) 30223f0703cSBryan Whitehead #define STAT_RX_TOTAL_FRAMES (0x1254) 30323f0703cSBryan Whitehead 30423f0703cSBryan Whitehead #define STAT_TX_FCS_ERRORS (0x1280) 30523f0703cSBryan Whitehead #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 30623f0703cSBryan Whitehead #define STAT_TX_CARRIER_ERRORS (0x1288) 30723f0703cSBryan Whitehead #define STAT_TX_SINGLE_COLLISIONS (0x1290) 30823f0703cSBryan Whitehead #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 30923f0703cSBryan Whitehead #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 31023f0703cSBryan Whitehead #define STAT_TX_LATE_COLLISIONS (0x129C) 31123f0703cSBryan Whitehead #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 31223f0703cSBryan Whitehead #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 31323f0703cSBryan Whitehead #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 31423f0703cSBryan Whitehead #define STAT_TX_MULTICAST_FRAMES (0x12B4) 31523f0703cSBryan Whitehead #define STAT_TX_TOTAL_FRAMES (0x12D8) 31623f0703cSBryan Whitehead 31723f0703cSBryan Whitehead /* End of Register definitions */ 31823f0703cSBryan Whitehead 31923f0703cSBryan Whitehead #define LAN743X_MAX_RX_CHANNELS (4) 32023f0703cSBryan Whitehead #define LAN743X_MAX_TX_CHANNELS (1) 32123f0703cSBryan Whitehead struct lan743x_adapter; 32223f0703cSBryan Whitehead 32323f0703cSBryan Whitehead #define LAN743X_USED_RX_CHANNELS (4) 32423f0703cSBryan Whitehead #define LAN743X_USED_TX_CHANNELS (1) 32523f0703cSBryan Whitehead #define LAN743X_INT_MOD (400) 32623f0703cSBryan Whitehead 32723f0703cSBryan Whitehead #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 32823f0703cSBryan Whitehead #error Invalid LAN743X_USED_RX_CHANNELS 32923f0703cSBryan Whitehead #endif 33023f0703cSBryan Whitehead #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 33123f0703cSBryan Whitehead #error Invalid LAN743X_USED_TX_CHANNELS 33223f0703cSBryan Whitehead #endif 33323f0703cSBryan Whitehead 33423f0703cSBryan Whitehead /* PCI */ 33523f0703cSBryan Whitehead /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 33623f0703cSBryan Whitehead #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 33723f0703cSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 33823f0703cSBryan Whitehead 33923f0703cSBryan Whitehead #define PCI_CONFIG_LENGTH (0x1000) 34023f0703cSBryan Whitehead 34123f0703cSBryan Whitehead /* CSR */ 34223f0703cSBryan Whitehead #define CSR_LENGTH (0x2000) 34323f0703cSBryan Whitehead 34423f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 34523f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 34623f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 34723f0703cSBryan Whitehead 34823f0703cSBryan Whitehead struct lan743x_csr { 34923f0703cSBryan Whitehead u32 flags; 35023f0703cSBryan Whitehead u8 __iomem *csr_address; 35123f0703cSBryan Whitehead u32 id_rev; 35223f0703cSBryan Whitehead u32 fpga_rev; 35323f0703cSBryan Whitehead }; 35423f0703cSBryan Whitehead 35523f0703cSBryan Whitehead /* INTERRUPTS */ 35623f0703cSBryan Whitehead typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 35723f0703cSBryan Whitehead 35823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 35923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 36023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 36123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 36223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 36323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 36423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 36523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 36623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 36723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 36823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 36923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 37023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 37123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 37223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 37323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 37423f0703cSBryan Whitehead 37523f0703cSBryan Whitehead struct lan743x_vector { 37623f0703cSBryan Whitehead int irq; 37723f0703cSBryan Whitehead u32 flags; 37823f0703cSBryan Whitehead struct lan743x_adapter *adapter; 37923f0703cSBryan Whitehead int vector_index; 38023f0703cSBryan Whitehead u32 int_mask; 38123f0703cSBryan Whitehead lan743x_vector_handler handler; 38223f0703cSBryan Whitehead void *context; 38323f0703cSBryan Whitehead }; 38423f0703cSBryan Whitehead 38523f0703cSBryan Whitehead #define LAN743X_MAX_VECTOR_COUNT (8) 38623f0703cSBryan Whitehead 38723f0703cSBryan Whitehead struct lan743x_intr { 38823f0703cSBryan Whitehead int flags; 38923f0703cSBryan Whitehead 39023f0703cSBryan Whitehead unsigned int irq; 39123f0703cSBryan Whitehead 39223f0703cSBryan Whitehead struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT]; 39323f0703cSBryan Whitehead int number_of_vectors; 39423f0703cSBryan Whitehead bool using_vectors; 39523f0703cSBryan Whitehead 39623f0703cSBryan Whitehead int software_isr_flag; 39723f0703cSBryan Whitehead }; 39823f0703cSBryan Whitehead 39923f0703cSBryan Whitehead #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 40023f0703cSBryan Whitehead 40123f0703cSBryan Whitehead /* PHY */ 40223f0703cSBryan Whitehead struct lan743x_phy { 40323f0703cSBryan Whitehead bool fc_autoneg; 40423f0703cSBryan Whitehead u8 fc_request_control; 40523f0703cSBryan Whitehead }; 40623f0703cSBryan Whitehead 40723f0703cSBryan Whitehead /* TX */ 40823f0703cSBryan Whitehead struct lan743x_tx_descriptor; 40923f0703cSBryan Whitehead struct lan743x_tx_buffer_info; 41023f0703cSBryan Whitehead 41123f0703cSBryan Whitehead #define GPIO_QUEUE_STARTED (0) 41223f0703cSBryan Whitehead #define GPIO_TX_FUNCTION (1) 41323f0703cSBryan Whitehead #define GPIO_TX_COMPLETION (2) 41423f0703cSBryan Whitehead #define GPIO_TX_FRAGMENT (3) 41523f0703cSBryan Whitehead 41623f0703cSBryan Whitehead #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 41723f0703cSBryan Whitehead 41823f0703cSBryan Whitehead struct lan743x_tx { 41923f0703cSBryan Whitehead struct lan743x_adapter *adapter; 42023f0703cSBryan Whitehead u32 vector_flags; 42123f0703cSBryan Whitehead int channel_number; 42223f0703cSBryan Whitehead 42323f0703cSBryan Whitehead int ring_size; 42423f0703cSBryan Whitehead size_t ring_allocation_size; 42523f0703cSBryan Whitehead struct lan743x_tx_descriptor *ring_cpu_ptr; 42623f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 42723f0703cSBryan Whitehead /* ring_lock: used to prevent concurrent access to tx ring */ 42823f0703cSBryan Whitehead spinlock_t ring_lock; 42923f0703cSBryan Whitehead u32 frame_flags; 43023f0703cSBryan Whitehead u32 frame_first; 43123f0703cSBryan Whitehead u32 frame_data0; 43223f0703cSBryan Whitehead u32 frame_tail; 43323f0703cSBryan Whitehead 43423f0703cSBryan Whitehead struct lan743x_tx_buffer_info *buffer_info; 43523f0703cSBryan Whitehead 43623f0703cSBryan Whitehead u32 *head_cpu_ptr; 43723f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 43823f0703cSBryan Whitehead int last_head; 43923f0703cSBryan Whitehead int last_tail; 44023f0703cSBryan Whitehead 44123f0703cSBryan Whitehead struct napi_struct napi; 44223f0703cSBryan Whitehead 44323f0703cSBryan Whitehead struct sk_buff *overflow_skb; 44423f0703cSBryan Whitehead }; 44523f0703cSBryan Whitehead 44623f0703cSBryan Whitehead /* RX */ 44723f0703cSBryan Whitehead struct lan743x_rx_descriptor; 44823f0703cSBryan Whitehead struct lan743x_rx_buffer_info; 44923f0703cSBryan Whitehead 45023f0703cSBryan Whitehead struct lan743x_rx { 45123f0703cSBryan Whitehead struct lan743x_adapter *adapter; 45223f0703cSBryan Whitehead u32 vector_flags; 45323f0703cSBryan Whitehead int channel_number; 45423f0703cSBryan Whitehead 45523f0703cSBryan Whitehead int ring_size; 45623f0703cSBryan Whitehead size_t ring_allocation_size; 45723f0703cSBryan Whitehead struct lan743x_rx_descriptor *ring_cpu_ptr; 45823f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 45923f0703cSBryan Whitehead 46023f0703cSBryan Whitehead struct lan743x_rx_buffer_info *buffer_info; 46123f0703cSBryan Whitehead 46223f0703cSBryan Whitehead u32 *head_cpu_ptr; 46323f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 46423f0703cSBryan Whitehead u32 last_head; 46523f0703cSBryan Whitehead u32 last_tail; 46623f0703cSBryan Whitehead 46723f0703cSBryan Whitehead struct napi_struct napi; 46823f0703cSBryan Whitehead 46923f0703cSBryan Whitehead u32 frame_count; 47023f0703cSBryan Whitehead }; 47123f0703cSBryan Whitehead 47223f0703cSBryan Whitehead struct lan743x_adapter { 47323f0703cSBryan Whitehead struct net_device *netdev; 47423f0703cSBryan Whitehead struct mii_bus *mdiobus; 47523f0703cSBryan Whitehead int msg_enable; 47623f0703cSBryan Whitehead struct pci_dev *pdev; 47723f0703cSBryan Whitehead struct lan743x_csr csr; 47823f0703cSBryan Whitehead struct lan743x_intr intr; 47923f0703cSBryan Whitehead 48023f0703cSBryan Whitehead /* lock, used to prevent concurrent access to data port */ 48123f0703cSBryan Whitehead struct mutex dp_lock; 48223f0703cSBryan Whitehead 48323f0703cSBryan Whitehead u8 mac_address[ETH_ALEN]; 48423f0703cSBryan Whitehead 48523f0703cSBryan Whitehead struct lan743x_phy phy; 48623f0703cSBryan Whitehead struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS]; 48723f0703cSBryan Whitehead struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS]; 48823f0703cSBryan Whitehead }; 48923f0703cSBryan Whitehead 49023f0703cSBryan Whitehead #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 49123f0703cSBryan Whitehead 49223f0703cSBryan Whitehead #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 49323f0703cSBryan Whitehead #define INTR_FLAG_MSI_ENABLED BIT(8) 49423f0703cSBryan Whitehead #define INTR_FLAG_MSIX_ENABLED BIT(9) 49523f0703cSBryan Whitehead 49623f0703cSBryan Whitehead #define MAC_MII_READ 1 49723f0703cSBryan Whitehead #define MAC_MII_WRITE 0 49823f0703cSBryan Whitehead 49923f0703cSBryan Whitehead #define PHY_FLAG_OPENED BIT(0) 50023f0703cSBryan Whitehead #define PHY_FLAG_ATTACHED BIT(1) 50123f0703cSBryan Whitehead 50223f0703cSBryan Whitehead #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 50323f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 50423f0703cSBryan Whitehead #else 50523f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 50623f0703cSBryan Whitehead #endif 50723f0703cSBryan Whitehead #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 50823f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_16 (16) 50923f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_32 (32) 51023f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_64 (64) 51123f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_128 (128) 51223f0703cSBryan Whitehead #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 51323f0703cSBryan Whitehead 51423f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 51523f0703cSBryan Whitehead (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 51623f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 51723f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 51823f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 51923f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 52023f0703cSBryan Whitehead 52123f0703cSBryan Whitehead /* TX Descriptor bits */ 52223f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 52323f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 52423f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 52523f0703cSBryan Whitehead #define TX_DESC_DATA0_FS_ (0x20000000) 52623f0703cSBryan Whitehead #define TX_DESC_DATA0_LS_ (0x10000000) 52723f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_ (0x08000000) 52823f0703cSBryan Whitehead #define TX_DESC_DATA0_IOC_ (0x04000000) 52923f0703cSBryan Whitehead #define TX_DESC_DATA0_ICE_ (0x00400000) 53023f0703cSBryan Whitehead #define TX_DESC_DATA0_IPE_ (0x00200000) 53123f0703cSBryan Whitehead #define TX_DESC_DATA0_TPE_ (0x00100000) 53223f0703cSBryan Whitehead #define TX_DESC_DATA0_FCS_ (0x00020000) 53323f0703cSBryan Whitehead #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 53423f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 53523f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 53623f0703cSBryan Whitehead #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 53723f0703cSBryan Whitehead 53823f0703cSBryan Whitehead struct lan743x_tx_descriptor { 53923f0703cSBryan Whitehead u32 data0; 54023f0703cSBryan Whitehead u32 data1; 54123f0703cSBryan Whitehead u32 data2; 54223f0703cSBryan Whitehead u32 data3; 54323f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 54423f0703cSBryan Whitehead 54523f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 54623f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 54723f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 54823f0703cSBryan Whitehead struct lan743x_tx_buffer_info { 54923f0703cSBryan Whitehead int flags; 55023f0703cSBryan Whitehead struct sk_buff *skb; 55123f0703cSBryan Whitehead dma_addr_t dma_ptr; 55223f0703cSBryan Whitehead unsigned int buffer_length; 55323f0703cSBryan Whitehead }; 55423f0703cSBryan Whitehead 55523f0703cSBryan Whitehead #define LAN743X_TX_RING_SIZE (50) 55623f0703cSBryan Whitehead 55723f0703cSBryan Whitehead /* OWN bit is set. ie, Descs are owned by RX DMAC */ 55823f0703cSBryan Whitehead #define RX_DESC_DATA0_OWN_ (0x00008000) 55923f0703cSBryan Whitehead /* OWN bit is clear. ie, Descs are owned by host */ 56023f0703cSBryan Whitehead #define RX_DESC_DATA0_FS_ (0x80000000) 56123f0703cSBryan Whitehead #define RX_DESC_DATA0_LS_ (0x40000000) 56223f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 56323f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 56423f0703cSBryan Whitehead (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 56523f0703cSBryan Whitehead #define RX_DESC_DATA0_EXT_ (0x00004000) 56623f0703cSBryan Whitehead #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 56723f0703cSBryan Whitehead #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 56823f0703cSBryan Whitehead 56923f0703cSBryan Whitehead #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 57023f0703cSBryan Whitehead #error NET_IP_ALIGN must be 0 or 2 57123f0703cSBryan Whitehead #endif 57223f0703cSBryan Whitehead 57323f0703cSBryan Whitehead #define RX_HEAD_PADDING NET_IP_ALIGN 57423f0703cSBryan Whitehead 57523f0703cSBryan Whitehead struct lan743x_rx_descriptor { 57623f0703cSBryan Whitehead u32 data0; 57723f0703cSBryan Whitehead u32 data1; 57823f0703cSBryan Whitehead u32 data2; 57923f0703cSBryan Whitehead u32 data3; 58023f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 58123f0703cSBryan Whitehead 58223f0703cSBryan Whitehead #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 58323f0703cSBryan Whitehead struct lan743x_rx_buffer_info { 58423f0703cSBryan Whitehead int flags; 58523f0703cSBryan Whitehead struct sk_buff *skb; 58623f0703cSBryan Whitehead 58723f0703cSBryan Whitehead dma_addr_t dma_ptr; 58823f0703cSBryan Whitehead unsigned int buffer_length; 58923f0703cSBryan Whitehead }; 59023f0703cSBryan Whitehead 59123f0703cSBryan Whitehead #define LAN743X_RX_RING_SIZE (65) 59223f0703cSBryan Whitehead 59323f0703cSBryan Whitehead #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 59423f0703cSBryan Whitehead #define RX_PROCESS_RESULT_PACKET_RECEIVED (1) 59523f0703cSBryan Whitehead #define RX_PROCESS_RESULT_PACKET_DROPPED (2) 59623f0703cSBryan Whitehead 59723f0703cSBryan Whitehead #endif /* _LAN743X_H */ 598