123f0703cSBryan Whitehead /* SPDX-License-Identifier: GPL-2.0+ */ 223f0703cSBryan Whitehead /* Copyright (C) 2018 Microchip Technology Inc. */ 323f0703cSBryan Whitehead 423f0703cSBryan Whitehead #ifndef _LAN743X_H 523f0703cSBryan Whitehead #define _LAN743X_H 623f0703cSBryan Whitehead 707624df1SBryan Whitehead #include "lan743x_ptp.h" 807624df1SBryan Whitehead 923f0703cSBryan Whitehead #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 1023f0703cSBryan Whitehead #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 1123f0703cSBryan Whitehead #define DRIVER_NAME "lan743x" 1223f0703cSBryan Whitehead 1323f0703cSBryan Whitehead /* Register Definitions */ 1423f0703cSBryan Whitehead #define ID_REV (0x00) 1507624df1SBryan Whitehead #define ID_REV_ID_MASK_ (0xFFFF0000) 1607624df1SBryan Whitehead #define ID_REV_ID_LAN7430_ (0x74300000) 1707624df1SBryan Whitehead #define ID_REV_ID_LAN7431_ (0x74310000) 1823f0703cSBryan Whitehead #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 1923f0703cSBryan Whitehead (((id_rev) & 0xFFF00000) == 0x74300000) 2023f0703cSBryan Whitehead #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 2123f0703cSBryan Whitehead #define ID_REV_CHIP_REV_A0_ (0x00000000) 2223f0703cSBryan Whitehead #define ID_REV_CHIP_REV_B0_ (0x00000010) 2323f0703cSBryan Whitehead 2423f0703cSBryan Whitehead #define FPGA_REV (0x04) 2523f0703cSBryan Whitehead #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 2623f0703cSBryan Whitehead #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 2723f0703cSBryan Whitehead 2823f0703cSBryan Whitehead #define HW_CFG (0x010) 2923f0703cSBryan Whitehead #define HW_CFG_LRST_ BIT(1) 3023f0703cSBryan Whitehead 3123f0703cSBryan Whitehead #define PMT_CTL (0x014) 324d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 334d94282aSBryan Whitehead #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 344d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 354d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 364d94282aSBryan Whitehead #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 374d94282aSBryan Whitehead #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 384d94282aSBryan Whitehead #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 3923f0703cSBryan Whitehead #define PMT_CTL_READY_ BIT(7) 4023f0703cSBryan Whitehead #define PMT_CTL_ETH_PHY_RST_ BIT(4) 414d94282aSBryan Whitehead #define PMT_CTL_WOL_EN_ BIT(3) 424d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 434d94282aSBryan Whitehead #define PMT_CTL_WUPS_MASK_ (0x00000003) 4423f0703cSBryan Whitehead 4523f0703cSBryan Whitehead #define DP_SEL (0x024) 4623f0703cSBryan Whitehead #define DP_SEL_DPRDY_ BIT(31) 4723f0703cSBryan Whitehead #define DP_SEL_MASK_ (0x0000001F) 4823f0703cSBryan Whitehead #define DP_SEL_RFE_RAM (0x00000001) 4923f0703cSBryan Whitehead 5023f0703cSBryan Whitehead #define DP_SEL_VHF_HASH_LEN (16) 5123f0703cSBryan Whitehead #define DP_SEL_VHF_VLAN_LEN (128) 5223f0703cSBryan Whitehead 5323f0703cSBryan Whitehead #define DP_CMD (0x028) 5423f0703cSBryan Whitehead #define DP_CMD_WRITE_ (0x00000001) 5523f0703cSBryan Whitehead 5623f0703cSBryan Whitehead #define DP_ADDR (0x02C) 5723f0703cSBryan Whitehead 5823f0703cSBryan Whitehead #define DP_DATA_0 (0x030) 5923f0703cSBryan Whitehead 6069584604SBryan Whitehead #define E2P_CMD (0x040) 6169584604SBryan Whitehead #define E2P_CMD_EPC_BUSY_ BIT(31) 6269584604SBryan Whitehead #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 6369584604SBryan Whitehead #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 6469584604SBryan Whitehead #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 6569584604SBryan Whitehead #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 6669584604SBryan Whitehead #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 6769584604SBryan Whitehead 6869584604SBryan Whitehead #define E2P_DATA (0x044) 6969584604SBryan Whitehead 7007624df1SBryan Whitehead #define GPIO_CFG0 (0x050) 7107624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 7207624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 7307624df1SBryan Whitehead 7407624df1SBryan Whitehead #define GPIO_CFG1 (0x054) 7507624df1SBryan Whitehead #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 7607624df1SBryan Whitehead #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 7707624df1SBryan Whitehead 7807624df1SBryan Whitehead #define GPIO_CFG2 (0x058) 7907624df1SBryan Whitehead #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 8007624df1SBryan Whitehead 8107624df1SBryan Whitehead #define GPIO_CFG3 (0x05C) 8207624df1SBryan Whitehead #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 8307624df1SBryan Whitehead #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 8407624df1SBryan Whitehead 8523f0703cSBryan Whitehead #define FCT_RX_CTL (0xAC) 8623f0703cSBryan Whitehead #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 8723f0703cSBryan Whitehead #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 8823f0703cSBryan Whitehead #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 8923f0703cSBryan Whitehead 9023f0703cSBryan Whitehead #define FCT_TX_CTL (0xC4) 9123f0703cSBryan Whitehead #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 9223f0703cSBryan Whitehead #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 9323f0703cSBryan Whitehead #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 9423f0703cSBryan Whitehead 9523f0703cSBryan Whitehead #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 9623f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 9723f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 9823f0703cSBryan Whitehead ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 9923f0703cSBryan Whitehead #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 10023f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 10123f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 10223f0703cSBryan Whitehead ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 10323f0703cSBryan Whitehead 10423f0703cSBryan Whitehead #define MAC_CR (0x100) 105c9cf96bbSBryan Whitehead #define MAC_CR_EEE_EN_ BIT(17) 10623f0703cSBryan Whitehead #define MAC_CR_ADD_ BIT(12) 10723f0703cSBryan Whitehead #define MAC_CR_ASD_ BIT(11) 10823f0703cSBryan Whitehead #define MAC_CR_CNTR_RST_ BIT(5) 10923f0703cSBryan Whitehead #define MAC_CR_RST_ BIT(0) 11023f0703cSBryan Whitehead 11123f0703cSBryan Whitehead #define MAC_RX (0x104) 11223f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_SHIFT_ (16) 11323f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 11423f0703cSBryan Whitehead #define MAC_RX_RXD_ BIT(1) 11523f0703cSBryan Whitehead #define MAC_RX_RXEN_ BIT(0) 11623f0703cSBryan Whitehead 11723f0703cSBryan Whitehead #define MAC_TX (0x108) 11823f0703cSBryan Whitehead #define MAC_TX_TXD_ BIT(1) 11923f0703cSBryan Whitehead #define MAC_TX_TXEN_ BIT(0) 12023f0703cSBryan Whitehead 12123f0703cSBryan Whitehead #define MAC_FLOW (0x10C) 12223f0703cSBryan Whitehead #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 12323f0703cSBryan Whitehead #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 12423f0703cSBryan Whitehead #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 12523f0703cSBryan Whitehead 12623f0703cSBryan Whitehead #define MAC_RX_ADDRH (0x118) 12723f0703cSBryan Whitehead 12823f0703cSBryan Whitehead #define MAC_RX_ADDRL (0x11C) 12923f0703cSBryan Whitehead 13023f0703cSBryan Whitehead #define MAC_MII_ACC (0x120) 13123f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 13223f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 13323f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 13423f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 13523f0703cSBryan Whitehead #define MAC_MII_ACC_MII_READ_ (0x00000000) 13623f0703cSBryan Whitehead #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 13723f0703cSBryan Whitehead #define MAC_MII_ACC_MII_BUSY_ BIT(0) 13823f0703cSBryan Whitehead 13923f0703cSBryan Whitehead #define MAC_MII_DATA (0x124) 14023f0703cSBryan Whitehead 141c9cf96bbSBryan Whitehead #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 142c9cf96bbSBryan Whitehead 1434d94282aSBryan Whitehead #define MAC_WUCSR (0x140) 1444d94282aSBryan Whitehead #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 1454d94282aSBryan Whitehead #define MAC_WUCSR_PFDA_EN_ BIT(3) 1464d94282aSBryan Whitehead #define MAC_WUCSR_WAKE_EN_ BIT(2) 1474d94282aSBryan Whitehead #define MAC_WUCSR_MPEN_ BIT(1) 1484d94282aSBryan Whitehead #define MAC_WUCSR_BCST_EN_ BIT(0) 1494d94282aSBryan Whitehead 1504d94282aSBryan Whitehead #define MAC_WK_SRC (0x144) 1514d94282aSBryan Whitehead 1524d94282aSBryan Whitehead #define MAC_WUF_CFG0 (0x150) 1534d94282aSBryan Whitehead #define MAC_NUM_OF_WUF_CFG (32) 1544d94282aSBryan Whitehead #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 1554d94282aSBryan Whitehead #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 1564d94282aSBryan Whitehead #define MAC_WUF_CFG_EN_ BIT(31) 1574d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 1584d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 1594d94282aSBryan Whitehead #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 1604d94282aSBryan Whitehead #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 1614d94282aSBryan Whitehead 1624d94282aSBryan Whitehead #define MAC_WUF_MASK0_0 (0x200) 1634d94282aSBryan Whitehead #define MAC_WUF_MASK0_1 (0x204) 1644d94282aSBryan Whitehead #define MAC_WUF_MASK0_2 (0x208) 1654d94282aSBryan Whitehead #define MAC_WUF_MASK0_3 (0x20C) 1664d94282aSBryan Whitehead #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 1674d94282aSBryan Whitehead #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 1684d94282aSBryan Whitehead #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 1694d94282aSBryan Whitehead #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 1704d94282aSBryan Whitehead #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 1714d94282aSBryan Whitehead #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 1724d94282aSBryan Whitehead #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 1734d94282aSBryan Whitehead #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 1744d94282aSBryan Whitehead 17523f0703cSBryan Whitehead /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 17623f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 17723f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 17823f0703cSBryan Whitehead 17923f0703cSBryan Whitehead /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 18023f0703cSBryan Whitehead #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 18123f0703cSBryan Whitehead 18223f0703cSBryan Whitehead #define RFE_CTL (0x508) 18323f0703cSBryan Whitehead #define RFE_CTL_AB_ BIT(10) 18423f0703cSBryan Whitehead #define RFE_CTL_AM_ BIT(9) 18523f0703cSBryan Whitehead #define RFE_CTL_AU_ BIT(8) 18623f0703cSBryan Whitehead #define RFE_CTL_MCAST_HASH_ BIT(3) 18723f0703cSBryan Whitehead #define RFE_CTL_DA_PERFECT_ BIT(1) 18823f0703cSBryan Whitehead 18943e8fe9bSBryan Whitehead #define RFE_RSS_CFG (0x554) 19043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 19143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 19243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 19343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 19443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 19543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_ BIT(11) 19643e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 19743e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 19843e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV4_ BIT(8) 19943e8fe9bSBryan Whitehead #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 20043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 20143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 20243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 20343e8fe9bSBryan Whitehead 20443e8fe9bSBryan Whitehead #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 20543e8fe9bSBryan Whitehead 20643e8fe9bSBryan Whitehead #define RFE_INDX(index) (0x580 + (index << 2)) 20743e8fe9bSBryan Whitehead 2084d94282aSBryan Whitehead #define MAC_WUCSR2 (0x600) 2094d94282aSBryan Whitehead 21023f0703cSBryan Whitehead #define INT_STS (0x780) 21123f0703cSBryan Whitehead #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 21223f0703cSBryan Whitehead #define INT_BIT_ALL_RX_ (0x0F000000) 21323f0703cSBryan Whitehead #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 21423f0703cSBryan Whitehead #define INT_BIT_ALL_TX_ (0x000F0000) 21523f0703cSBryan Whitehead #define INT_BIT_SW_GP_ BIT(9) 21607624df1SBryan Whitehead #define INT_BIT_1588_ BIT(7) 21707624df1SBryan Whitehead #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 21823f0703cSBryan Whitehead #define INT_BIT_MAS_ BIT(0) 21923f0703cSBryan Whitehead 22023f0703cSBryan Whitehead #define INT_SET (0x784) 22123f0703cSBryan Whitehead 22223f0703cSBryan Whitehead #define INT_EN_SET (0x788) 22323f0703cSBryan Whitehead 22423f0703cSBryan Whitehead #define INT_EN_CLR (0x78C) 22523f0703cSBryan Whitehead 22623f0703cSBryan Whitehead #define INT_STS_R2C (0x790) 22723f0703cSBryan Whitehead 22823f0703cSBryan Whitehead #define INT_VEC_EN_SET (0x794) 22923f0703cSBryan Whitehead #define INT_VEC_EN_CLR (0x798) 23023f0703cSBryan Whitehead #define INT_VEC_EN_AUTO_CLR (0x79C) 23123f0703cSBryan Whitehead #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 23223f0703cSBryan Whitehead 23323f0703cSBryan Whitehead #define INT_VEC_MAP0 (0x7A0) 23423f0703cSBryan Whitehead #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 23523f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 23623f0703cSBryan Whitehead 23723f0703cSBryan Whitehead #define INT_VEC_MAP1 (0x7A4) 23823f0703cSBryan Whitehead #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 23923f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 24023f0703cSBryan Whitehead 24123f0703cSBryan Whitehead #define INT_VEC_MAP2 (0x7A8) 24223f0703cSBryan Whitehead 24323f0703cSBryan Whitehead #define INT_MOD_MAP0 (0x7B0) 24423f0703cSBryan Whitehead 24523f0703cSBryan Whitehead #define INT_MOD_MAP1 (0x7B4) 24623f0703cSBryan Whitehead 24723f0703cSBryan Whitehead #define INT_MOD_MAP2 (0x7B8) 24823f0703cSBryan Whitehead 24923f0703cSBryan Whitehead #define INT_MOD_CFG0 (0x7C0) 25023f0703cSBryan Whitehead #define INT_MOD_CFG1 (0x7C4) 25123f0703cSBryan Whitehead #define INT_MOD_CFG2 (0x7C8) 25223f0703cSBryan Whitehead #define INT_MOD_CFG3 (0x7CC) 25323f0703cSBryan Whitehead #define INT_MOD_CFG4 (0x7D0) 25423f0703cSBryan Whitehead #define INT_MOD_CFG5 (0x7D4) 25523f0703cSBryan Whitehead #define INT_MOD_CFG6 (0x7D8) 25623f0703cSBryan Whitehead #define INT_MOD_CFG7 (0x7DC) 25723f0703cSBryan Whitehead 25807624df1SBryan Whitehead #define PTP_CMD_CTL (0x0A00) 25907624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 26007624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 26107624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 26207624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 26307624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 26407624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 26507624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 26607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG (0x0A04) 26707624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 26807624df1SBryan Whitehead (0x7 << (1 + ((channel) << 2))) 26907624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 27007624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 27107624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 27207624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 27307624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 27407624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 27507624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 27607624df1SBryan Whitehead (((value) & 0x7) << (1 + ((channel) << 2))) 27707624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 27807624df1SBryan Whitehead 27907624df1SBryan Whitehead #define PTP_INT_STS (0x0A08) 28007624df1SBryan Whitehead #define PTP_INT_EN_SET (0x0A0C) 28107624df1SBryan Whitehead #define PTP_INT_EN_CLR (0x0A10) 28207624df1SBryan Whitehead #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 28307624df1SBryan Whitehead #define PTP_INT_BIT_TX_TS_ BIT(12) 28407624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_B_ BIT(1) 28507624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_A_ BIT(0) 28607624df1SBryan Whitehead 28707624df1SBryan Whitehead #define PTP_CLOCK_SEC (0x0A14) 28807624df1SBryan Whitehead #define PTP_CLOCK_NS (0x0A18) 28907624df1SBryan Whitehead #define PTP_CLOCK_SUBNS (0x0A1C) 29007624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ (0x0A20) 29107624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 29207624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ (0x0A2C) 29307624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 29407624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 29507624df1SBryan Whitehead #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 29607624df1SBryan Whitehead #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 29707624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 29807624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 29907624df1SBryan Whitehead #define PTP_LATENCY (0x0A5C) 30007624df1SBryan Whitehead #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 30107624df1SBryan Whitehead #define PTP_LATENCY_RX_SET_(rx_latency) \ 30207624df1SBryan Whitehead (((u32)(rx_latency)) & 0x0000FFFF) 30307624df1SBryan Whitehead #define PTP_CAP_INFO (0x0A60) 30407624df1SBryan Whitehead #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 30507624df1SBryan Whitehead 30607624df1SBryan Whitehead #define PTP_TX_MOD (0x0AA4) 30707624df1SBryan Whitehead #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 30807624df1SBryan Whitehead 30907624df1SBryan Whitehead #define PTP_TX_MOD2 (0x0AA8) 31007624df1SBryan Whitehead #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 31107624df1SBryan Whitehead 31207624df1SBryan Whitehead #define PTP_TX_EGRESS_SEC (0x0AAC) 31307624df1SBryan Whitehead #define PTP_TX_EGRESS_NS (0x0AB0) 31407624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 31507624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 31607624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 31707624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 31807624df1SBryan Whitehead 31907624df1SBryan Whitehead #define PTP_TX_MSG_HEADER (0x0AB4) 32007624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 32107624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 32207624df1SBryan Whitehead 32323f0703cSBryan Whitehead #define DMAC_CFG (0xC00) 32423f0703cSBryan Whitehead #define DMAC_CFG_COAL_EN_ BIT(16) 32523f0703cSBryan Whitehead #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 32623f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 32723f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 32823f0703cSBryan Whitehead ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 32923f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 33023f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 33123f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 33223f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 33323f0703cSBryan Whitehead 33423f0703cSBryan Whitehead #define DMAC_COAL_CFG (0xC04) 33523f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 33623f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 33723f0703cSBryan Whitehead ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 33823f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 33923f0703cSBryan Whitehead #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 34023f0703cSBryan Whitehead #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 34123f0703cSBryan Whitehead #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 34223f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 34323f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 34423f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 34523f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 34623f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 34723f0703cSBryan Whitehead (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 34823f0703cSBryan Whitehead 34923f0703cSBryan Whitehead #define DMAC_OBFF_CFG (0xC08) 35023f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 35123f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_SET_(val) \ 35223f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 35323f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 35423f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_SET_(val) \ 35523f0703cSBryan Whitehead (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 35623f0703cSBryan Whitehead 35723f0703cSBryan Whitehead #define DMAC_CMD (0xC0C) 35823f0703cSBryan Whitehead #define DMAC_CMD_SWR_ BIT(31) 35923f0703cSBryan Whitehead #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 36023f0703cSBryan Whitehead #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 36123f0703cSBryan Whitehead #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 36223f0703cSBryan Whitehead #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 36323f0703cSBryan Whitehead #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 36423f0703cSBryan Whitehead #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 36523f0703cSBryan Whitehead 36623f0703cSBryan Whitehead #define DMAC_INT_STS (0xC10) 36723f0703cSBryan Whitehead #define DMAC_INT_EN_SET (0xC14) 36823f0703cSBryan Whitehead #define DMAC_INT_EN_CLR (0xC18) 36923f0703cSBryan Whitehead #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 37023f0703cSBryan Whitehead #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 37123f0703cSBryan Whitehead 37223f0703cSBryan Whitehead #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 37323f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 37423f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 37523f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 37623f0703cSBryan Whitehead ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 37723f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 37823f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 37923f0703cSBryan Whitehead ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 38023f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 38123f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 38223f0703cSBryan Whitehead ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 38323f0703cSBryan Whitehead #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 38423f0703cSBryan Whitehead 38523f0703cSBryan Whitehead #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 38623f0703cSBryan Whitehead #define RX_CFG_B_TS_ALL_RX_ BIT(29) 38723f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 38823f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_0_ (0x00000000) 38923f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_2_ (0x02000000) 39023f0703cSBryan Whitehead #define RX_CFG_B_RDMABL_512_ (0x00040000) 39123f0703cSBryan Whitehead #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 39223f0703cSBryan Whitehead 39323f0703cSBryan Whitehead #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 39423f0703cSBryan Whitehead 39523f0703cSBryan Whitehead #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 39623f0703cSBryan Whitehead 39723f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 39823f0703cSBryan Whitehead 39923f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 40023f0703cSBryan Whitehead 40123f0703cSBryan Whitehead #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 40223f0703cSBryan Whitehead 40323f0703cSBryan Whitehead #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 40423f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 40523f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 40623f0703cSBryan Whitehead 40723f0703cSBryan Whitehead #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 40823f0703cSBryan Whitehead #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 40923f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 41023f0703cSBryan Whitehead #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 41123f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 41223f0703cSBryan Whitehead 41323f0703cSBryan Whitehead #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 41423f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 41523f0703cSBryan Whitehead #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 41623f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 41723f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 41823f0703cSBryan Whitehead ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 41923f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 42023f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 42123f0703cSBryan Whitehead ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 42223f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 42323f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 42423f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 42523f0703cSBryan Whitehead (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 42623f0703cSBryan Whitehead 42723f0703cSBryan Whitehead #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 42823f0703cSBryan Whitehead #define TX_CFG_B_TDMABL_512_ (0x00040000) 42923f0703cSBryan Whitehead #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 43023f0703cSBryan Whitehead 43123f0703cSBryan Whitehead #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 43223f0703cSBryan Whitehead 43323f0703cSBryan Whitehead #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 43423f0703cSBryan Whitehead 43523f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 43623f0703cSBryan Whitehead 43723f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 43823f0703cSBryan Whitehead 43923f0703cSBryan Whitehead #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 44023f0703cSBryan Whitehead 44123f0703cSBryan Whitehead #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 44223f0703cSBryan Whitehead #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 44323f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 44423f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 44523f0703cSBryan Whitehead 44623f0703cSBryan Whitehead #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 44723f0703cSBryan Whitehead #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 44823f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 44923f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 45023f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 45123f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 45223f0703cSBryan Whitehead 45369584604SBryan Whitehead #define OTP_PWR_DN (0x1000) 45469584604SBryan Whitehead #define OTP_PWR_DN_PWRDN_N_ BIT(0) 45569584604SBryan Whitehead 45669584604SBryan Whitehead #define OTP_ADDR1 (0x1004) 45769584604SBryan Whitehead #define OTP_ADDR1_15_11_MASK_ (0x1F) 45869584604SBryan Whitehead 45969584604SBryan Whitehead #define OTP_ADDR2 (0x1008) 46069584604SBryan Whitehead #define OTP_ADDR2_10_3_MASK_ (0xFF) 46169584604SBryan Whitehead 46269584604SBryan Whitehead #define OTP_PRGM_DATA (0x1010) 46369584604SBryan Whitehead 46469584604SBryan Whitehead #define OTP_PRGM_MODE (0x1014) 46569584604SBryan Whitehead #define OTP_PRGM_MODE_BYTE_ BIT(0) 46669584604SBryan Whitehead 46769584604SBryan Whitehead #define OTP_TST_CMD (0x1024) 46869584604SBryan Whitehead #define OTP_TST_CMD_PRGVRFY_ BIT(3) 46969584604SBryan Whitehead 47069584604SBryan Whitehead #define OTP_CMD_GO (0x1028) 47169584604SBryan Whitehead #define OTP_CMD_GO_GO_ BIT(0) 47269584604SBryan Whitehead 47369584604SBryan Whitehead #define OTP_STATUS (0x1030) 47469584604SBryan Whitehead #define OTP_STATUS_BUSY_ BIT(0) 47569584604SBryan Whitehead 47623f0703cSBryan Whitehead /* MAC statistics registers */ 47723f0703cSBryan Whitehead #define STAT_RX_FCS_ERRORS (0x1200) 47823f0703cSBryan Whitehead #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 4798114e8a2SBryan Whitehead #define STAT_RX_FRAGMENT_ERRORS (0x1208) 48023f0703cSBryan Whitehead #define STAT_RX_JABBER_ERRORS (0x120C) 48123f0703cSBryan Whitehead #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 48223f0703cSBryan Whitehead #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 48323f0703cSBryan Whitehead #define STAT_RX_DROPPED_FRAMES (0x1218) 48423f0703cSBryan Whitehead #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 48523f0703cSBryan Whitehead #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 48623f0703cSBryan Whitehead #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 4878114e8a2SBryan Whitehead #define STAT_RX_UNICAST_FRAMES (0x1228) 4888114e8a2SBryan Whitehead #define STAT_RX_BROADCAST_FRAMES (0x122C) 48923f0703cSBryan Whitehead #define STAT_RX_MULTICAST_FRAMES (0x1230) 4908114e8a2SBryan Whitehead #define STAT_RX_PAUSE_FRAMES (0x1234) 4918114e8a2SBryan Whitehead #define STAT_RX_64_BYTE_FRAMES (0x1238) 4928114e8a2SBryan Whitehead #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 4938114e8a2SBryan Whitehead #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 4948114e8a2SBryan Whitehead #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 4958114e8a2SBryan Whitehead #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 4968114e8a2SBryan Whitehead #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 4978114e8a2SBryan Whitehead #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 49823f0703cSBryan Whitehead #define STAT_RX_TOTAL_FRAMES (0x1254) 4998114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 5008114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TIME (0x125C) 5018114e8a2SBryan Whitehead #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 50223f0703cSBryan Whitehead 50323f0703cSBryan Whitehead #define STAT_TX_FCS_ERRORS (0x1280) 50423f0703cSBryan Whitehead #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 50523f0703cSBryan Whitehead #define STAT_TX_CARRIER_ERRORS (0x1288) 5068114e8a2SBryan Whitehead #define STAT_TX_BAD_BYTE_COUNT (0x128C) 50723f0703cSBryan Whitehead #define STAT_TX_SINGLE_COLLISIONS (0x1290) 50823f0703cSBryan Whitehead #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 50923f0703cSBryan Whitehead #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 51023f0703cSBryan Whitehead #define STAT_TX_LATE_COLLISIONS (0x129C) 51123f0703cSBryan Whitehead #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 51223f0703cSBryan Whitehead #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 51323f0703cSBryan Whitehead #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 5148114e8a2SBryan Whitehead #define STAT_TX_UNICAST_FRAMES (0x12AC) 5158114e8a2SBryan Whitehead #define STAT_TX_BROADCAST_FRAMES (0x12B0) 51623f0703cSBryan Whitehead #define STAT_TX_MULTICAST_FRAMES (0x12B4) 5178114e8a2SBryan Whitehead #define STAT_TX_PAUSE_FRAMES (0x12B8) 5188114e8a2SBryan Whitehead #define STAT_TX_64_BYTE_FRAMES (0x12BC) 5198114e8a2SBryan Whitehead #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 5208114e8a2SBryan Whitehead #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 5218114e8a2SBryan Whitehead #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 5228114e8a2SBryan Whitehead #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 5238114e8a2SBryan Whitehead #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 5248114e8a2SBryan Whitehead #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 52523f0703cSBryan Whitehead #define STAT_TX_TOTAL_FRAMES (0x12D8) 5268114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 5278114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TIME (0x12E0) 5288114e8a2SBryan Whitehead #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 52923f0703cSBryan Whitehead 53023f0703cSBryan Whitehead /* End of Register definitions */ 53123f0703cSBryan Whitehead 53223f0703cSBryan Whitehead #define LAN743X_MAX_RX_CHANNELS (4) 53323f0703cSBryan Whitehead #define LAN743X_MAX_TX_CHANNELS (1) 53423f0703cSBryan Whitehead struct lan743x_adapter; 53523f0703cSBryan Whitehead 53623f0703cSBryan Whitehead #define LAN743X_USED_RX_CHANNELS (4) 53723f0703cSBryan Whitehead #define LAN743X_USED_TX_CHANNELS (1) 53823f0703cSBryan Whitehead #define LAN743X_INT_MOD (400) 53923f0703cSBryan Whitehead 54023f0703cSBryan Whitehead #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 54123f0703cSBryan Whitehead #error Invalid LAN743X_USED_RX_CHANNELS 54223f0703cSBryan Whitehead #endif 54323f0703cSBryan Whitehead #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 54423f0703cSBryan Whitehead #error Invalid LAN743X_USED_TX_CHANNELS 54523f0703cSBryan Whitehead #endif 54623f0703cSBryan Whitehead 54723f0703cSBryan Whitehead /* PCI */ 54823f0703cSBryan Whitehead /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 54923f0703cSBryan Whitehead #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 55023f0703cSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 55123f0703cSBryan Whitehead 55223f0703cSBryan Whitehead #define PCI_CONFIG_LENGTH (0x1000) 55323f0703cSBryan Whitehead 55423f0703cSBryan Whitehead /* CSR */ 55523f0703cSBryan Whitehead #define CSR_LENGTH (0x2000) 55623f0703cSBryan Whitehead 55723f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 55823f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 55923f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 56023f0703cSBryan Whitehead 56123f0703cSBryan Whitehead struct lan743x_csr { 56223f0703cSBryan Whitehead u32 flags; 56323f0703cSBryan Whitehead u8 __iomem *csr_address; 56423f0703cSBryan Whitehead u32 id_rev; 56523f0703cSBryan Whitehead u32 fpga_rev; 56623f0703cSBryan Whitehead }; 56723f0703cSBryan Whitehead 56823f0703cSBryan Whitehead /* INTERRUPTS */ 56923f0703cSBryan Whitehead typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 57023f0703cSBryan Whitehead 57123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 57223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 57323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 57423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 57523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 57623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 57723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 57823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 57923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 58023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 58123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 58223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 58323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 58423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 58523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 58623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 58723f0703cSBryan Whitehead 58823f0703cSBryan Whitehead struct lan743x_vector { 58923f0703cSBryan Whitehead int irq; 59023f0703cSBryan Whitehead u32 flags; 59123f0703cSBryan Whitehead struct lan743x_adapter *adapter; 59223f0703cSBryan Whitehead int vector_index; 59323f0703cSBryan Whitehead u32 int_mask; 59423f0703cSBryan Whitehead lan743x_vector_handler handler; 59523f0703cSBryan Whitehead void *context; 59623f0703cSBryan Whitehead }; 59723f0703cSBryan Whitehead 59823f0703cSBryan Whitehead #define LAN743X_MAX_VECTOR_COUNT (8) 59923f0703cSBryan Whitehead 60023f0703cSBryan Whitehead struct lan743x_intr { 60123f0703cSBryan Whitehead int flags; 60223f0703cSBryan Whitehead 60323f0703cSBryan Whitehead unsigned int irq; 60423f0703cSBryan Whitehead 60523f0703cSBryan Whitehead struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT]; 60623f0703cSBryan Whitehead int number_of_vectors; 60723f0703cSBryan Whitehead bool using_vectors; 60823f0703cSBryan Whitehead 60923f0703cSBryan Whitehead int software_isr_flag; 61023f0703cSBryan Whitehead }; 61123f0703cSBryan Whitehead 61223f0703cSBryan Whitehead #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 61323f0703cSBryan Whitehead 61423f0703cSBryan Whitehead /* PHY */ 61523f0703cSBryan Whitehead struct lan743x_phy { 61623f0703cSBryan Whitehead bool fc_autoneg; 61723f0703cSBryan Whitehead u8 fc_request_control; 61823f0703cSBryan Whitehead }; 61923f0703cSBryan Whitehead 62023f0703cSBryan Whitehead /* TX */ 62123f0703cSBryan Whitehead struct lan743x_tx_descriptor; 62223f0703cSBryan Whitehead struct lan743x_tx_buffer_info; 62323f0703cSBryan Whitehead 62423f0703cSBryan Whitehead #define GPIO_QUEUE_STARTED (0) 62523f0703cSBryan Whitehead #define GPIO_TX_FUNCTION (1) 62623f0703cSBryan Whitehead #define GPIO_TX_COMPLETION (2) 62723f0703cSBryan Whitehead #define GPIO_TX_FRAGMENT (3) 62823f0703cSBryan Whitehead 62923f0703cSBryan Whitehead #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 63023f0703cSBryan Whitehead 63107624df1SBryan Whitehead #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 63207624df1SBryan Whitehead #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 63307624df1SBryan Whitehead 63423f0703cSBryan Whitehead struct lan743x_tx { 63523f0703cSBryan Whitehead struct lan743x_adapter *adapter; 63607624df1SBryan Whitehead u32 ts_flags; 63723f0703cSBryan Whitehead u32 vector_flags; 63823f0703cSBryan Whitehead int channel_number; 63923f0703cSBryan Whitehead 64023f0703cSBryan Whitehead int ring_size; 64123f0703cSBryan Whitehead size_t ring_allocation_size; 64223f0703cSBryan Whitehead struct lan743x_tx_descriptor *ring_cpu_ptr; 64323f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 64423f0703cSBryan Whitehead /* ring_lock: used to prevent concurrent access to tx ring */ 64523f0703cSBryan Whitehead spinlock_t ring_lock; 64623f0703cSBryan Whitehead u32 frame_flags; 64723f0703cSBryan Whitehead u32 frame_first; 64823f0703cSBryan Whitehead u32 frame_data0; 64923f0703cSBryan Whitehead u32 frame_tail; 65023f0703cSBryan Whitehead 65123f0703cSBryan Whitehead struct lan743x_tx_buffer_info *buffer_info; 65223f0703cSBryan Whitehead 65323f0703cSBryan Whitehead u32 *head_cpu_ptr; 65423f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 65523f0703cSBryan Whitehead int last_head; 65623f0703cSBryan Whitehead int last_tail; 65723f0703cSBryan Whitehead 65823f0703cSBryan Whitehead struct napi_struct napi; 65923f0703cSBryan Whitehead 66023f0703cSBryan Whitehead struct sk_buff *overflow_skb; 66123f0703cSBryan Whitehead }; 66223f0703cSBryan Whitehead 66307624df1SBryan Whitehead void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 66407624df1SBryan Whitehead bool enable_timestamping, 66507624df1SBryan Whitehead bool enable_onestep_sync); 66607624df1SBryan Whitehead 66723f0703cSBryan Whitehead /* RX */ 66823f0703cSBryan Whitehead struct lan743x_rx_descriptor; 66923f0703cSBryan Whitehead struct lan743x_rx_buffer_info; 67023f0703cSBryan Whitehead 67123f0703cSBryan Whitehead struct lan743x_rx { 67223f0703cSBryan Whitehead struct lan743x_adapter *adapter; 67323f0703cSBryan Whitehead u32 vector_flags; 67423f0703cSBryan Whitehead int channel_number; 67523f0703cSBryan Whitehead 67623f0703cSBryan Whitehead int ring_size; 67723f0703cSBryan Whitehead size_t ring_allocation_size; 67823f0703cSBryan Whitehead struct lan743x_rx_descriptor *ring_cpu_ptr; 67923f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 68023f0703cSBryan Whitehead 68123f0703cSBryan Whitehead struct lan743x_rx_buffer_info *buffer_info; 68223f0703cSBryan Whitehead 68323f0703cSBryan Whitehead u32 *head_cpu_ptr; 68423f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 68523f0703cSBryan Whitehead u32 last_head; 68623f0703cSBryan Whitehead u32 last_tail; 68723f0703cSBryan Whitehead 68823f0703cSBryan Whitehead struct napi_struct napi; 68923f0703cSBryan Whitehead 69023f0703cSBryan Whitehead u32 frame_count; 69123f0703cSBryan Whitehead }; 69223f0703cSBryan Whitehead 69323f0703cSBryan Whitehead struct lan743x_adapter { 69423f0703cSBryan Whitehead struct net_device *netdev; 69523f0703cSBryan Whitehead struct mii_bus *mdiobus; 69623f0703cSBryan Whitehead int msg_enable; 6974d94282aSBryan Whitehead #ifdef CONFIG_PM 6984d94282aSBryan Whitehead u32 wolopts; 6994d94282aSBryan Whitehead #endif 70023f0703cSBryan Whitehead struct pci_dev *pdev; 70123f0703cSBryan Whitehead struct lan743x_csr csr; 70223f0703cSBryan Whitehead struct lan743x_intr intr; 70323f0703cSBryan Whitehead 70423f0703cSBryan Whitehead /* lock, used to prevent concurrent access to data port */ 70523f0703cSBryan Whitehead struct mutex dp_lock; 70623f0703cSBryan Whitehead 70707624df1SBryan Whitehead struct lan743x_gpio gpio; 70807624df1SBryan Whitehead struct lan743x_ptp ptp; 70907624df1SBryan Whitehead 71023f0703cSBryan Whitehead u8 mac_address[ETH_ALEN]; 71123f0703cSBryan Whitehead 71223f0703cSBryan Whitehead struct lan743x_phy phy; 71323f0703cSBryan Whitehead struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS]; 71423f0703cSBryan Whitehead struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS]; 71523f0703cSBryan Whitehead }; 71623f0703cSBryan Whitehead 71723f0703cSBryan Whitehead #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 71823f0703cSBryan Whitehead 71923f0703cSBryan Whitehead #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 72023f0703cSBryan Whitehead #define INTR_FLAG_MSI_ENABLED BIT(8) 72123f0703cSBryan Whitehead #define INTR_FLAG_MSIX_ENABLED BIT(9) 72223f0703cSBryan Whitehead 72323f0703cSBryan Whitehead #define MAC_MII_READ 1 72423f0703cSBryan Whitehead #define MAC_MII_WRITE 0 72523f0703cSBryan Whitehead 72623f0703cSBryan Whitehead #define PHY_FLAG_OPENED BIT(0) 72723f0703cSBryan Whitehead #define PHY_FLAG_ATTACHED BIT(1) 72823f0703cSBryan Whitehead 72923f0703cSBryan Whitehead #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 73023f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 73123f0703cSBryan Whitehead #else 73223f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 73323f0703cSBryan Whitehead #endif 73423f0703cSBryan Whitehead #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 73523f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_16 (16) 73623f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_32 (32) 73723f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_64 (64) 73823f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_128 (128) 73923f0703cSBryan Whitehead #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 74023f0703cSBryan Whitehead 74123f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 74223f0703cSBryan Whitehead (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 74323f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 74423f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 74523f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 74623f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 74723f0703cSBryan Whitehead 74823f0703cSBryan Whitehead /* TX Descriptor bits */ 74923f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 75023f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 75123f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 75223f0703cSBryan Whitehead #define TX_DESC_DATA0_FS_ (0x20000000) 75323f0703cSBryan Whitehead #define TX_DESC_DATA0_LS_ (0x10000000) 75423f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_ (0x08000000) 75523f0703cSBryan Whitehead #define TX_DESC_DATA0_IOC_ (0x04000000) 75623f0703cSBryan Whitehead #define TX_DESC_DATA0_ICE_ (0x00400000) 75723f0703cSBryan Whitehead #define TX_DESC_DATA0_IPE_ (0x00200000) 75823f0703cSBryan Whitehead #define TX_DESC_DATA0_TPE_ (0x00100000) 75923f0703cSBryan Whitehead #define TX_DESC_DATA0_FCS_ (0x00020000) 76007624df1SBryan Whitehead #define TX_DESC_DATA0_TSE_ (0x00010000) 76123f0703cSBryan Whitehead #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 76223f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 76323f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 76423f0703cSBryan Whitehead #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 76523f0703cSBryan Whitehead 76623f0703cSBryan Whitehead struct lan743x_tx_descriptor { 76723f0703cSBryan Whitehead u32 data0; 76823f0703cSBryan Whitehead u32 data1; 76923f0703cSBryan Whitehead u32 data2; 77023f0703cSBryan Whitehead u32 data3; 77123f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 77223f0703cSBryan Whitehead 77323f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 77407624df1SBryan Whitehead #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 77523f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 77623f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 77723f0703cSBryan Whitehead struct lan743x_tx_buffer_info { 77823f0703cSBryan Whitehead int flags; 77923f0703cSBryan Whitehead struct sk_buff *skb; 78023f0703cSBryan Whitehead dma_addr_t dma_ptr; 78123f0703cSBryan Whitehead unsigned int buffer_length; 78223f0703cSBryan Whitehead }; 78323f0703cSBryan Whitehead 78423f0703cSBryan Whitehead #define LAN743X_TX_RING_SIZE (50) 78523f0703cSBryan Whitehead 78623f0703cSBryan Whitehead /* OWN bit is set. ie, Descs are owned by RX DMAC */ 78723f0703cSBryan Whitehead #define RX_DESC_DATA0_OWN_ (0x00008000) 78823f0703cSBryan Whitehead /* OWN bit is clear. ie, Descs are owned by host */ 78923f0703cSBryan Whitehead #define RX_DESC_DATA0_FS_ (0x80000000) 79023f0703cSBryan Whitehead #define RX_DESC_DATA0_LS_ (0x40000000) 79123f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 79223f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 79323f0703cSBryan Whitehead (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 79423f0703cSBryan Whitehead #define RX_DESC_DATA0_EXT_ (0x00004000) 79523f0703cSBryan Whitehead #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 79623f0703cSBryan Whitehead #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 79723f0703cSBryan Whitehead 79823f0703cSBryan Whitehead #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 79923f0703cSBryan Whitehead #error NET_IP_ALIGN must be 0 or 2 80023f0703cSBryan Whitehead #endif 80123f0703cSBryan Whitehead 80223f0703cSBryan Whitehead #define RX_HEAD_PADDING NET_IP_ALIGN 80323f0703cSBryan Whitehead 80423f0703cSBryan Whitehead struct lan743x_rx_descriptor { 80523f0703cSBryan Whitehead u32 data0; 80623f0703cSBryan Whitehead u32 data1; 80723f0703cSBryan Whitehead u32 data2; 80823f0703cSBryan Whitehead u32 data3; 80923f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 81023f0703cSBryan Whitehead 81123f0703cSBryan Whitehead #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 81223f0703cSBryan Whitehead struct lan743x_rx_buffer_info { 81323f0703cSBryan Whitehead int flags; 81423f0703cSBryan Whitehead struct sk_buff *skb; 81523f0703cSBryan Whitehead 81623f0703cSBryan Whitehead dma_addr_t dma_ptr; 81723f0703cSBryan Whitehead unsigned int buffer_length; 81823f0703cSBryan Whitehead }; 81923f0703cSBryan Whitehead 82023f0703cSBryan Whitehead #define LAN743X_RX_RING_SIZE (65) 82123f0703cSBryan Whitehead 82223f0703cSBryan Whitehead #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 82323f0703cSBryan Whitehead #define RX_PROCESS_RESULT_PACKET_RECEIVED (1) 82423f0703cSBryan Whitehead #define RX_PROCESS_RESULT_PACKET_DROPPED (2) 82523f0703cSBryan Whitehead 8268114e8a2SBryan Whitehead u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 8278114e8a2SBryan Whitehead void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 8288114e8a2SBryan Whitehead 82923f0703cSBryan Whitehead #endif /* _LAN743X_H */ 830