1 /** 2 * Microchip ENCX24J600 ethernet driver 3 * 4 * Copyright (C) 2015 Gridpoint 5 * Author: Jon Ringle <jringle@gridpoint.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/interrupt.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/netdevice.h> 22 #include <linux/regmap.h> 23 #include <linux/skbuff.h> 24 #include <linux/spi/spi.h> 25 26 #include "encx24j600_hw.h" 27 28 #define DRV_NAME "encx24j600" 29 #define DRV_VERSION "1.0" 30 31 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 32 static int debug = -1; 33 module_param(debug, int, 0); 34 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 35 36 /* SRAM memory layout: 37 * 38 * 0x0000-0x05ff TX buffers 1.5KB (1*1536) reside in the GP area in SRAM 39 * 0x0600-0x5fff RX buffers 22.5KB (15*1536) reside in the RX area in SRAM 40 */ 41 #define ENC_TX_BUF_START 0x0000U 42 #define ENC_RX_BUF_START 0x0600U 43 #define ENC_RX_BUF_END 0x5fffU 44 #define ENC_SRAM_SIZE 0x6000U 45 46 enum { 47 RXFILTER_NORMAL, 48 RXFILTER_MULTI, 49 RXFILTER_PROMISC 50 }; 51 52 struct encx24j600_priv { 53 struct net_device *ndev; 54 struct mutex lock; /* device access lock */ 55 struct encx24j600_context ctx; 56 struct sk_buff *tx_skb; 57 struct task_struct *kworker_task; 58 struct kthread_worker kworker; 59 struct kthread_work tx_work; 60 struct kthread_work setrx_work; 61 u16 next_packet; 62 bool hw_enabled; 63 bool full_duplex; 64 bool autoneg; 65 u16 speed; 66 int rxfilter; 67 u32 msg_enable; 68 }; 69 70 static void dump_packet(const char *msg, int len, const char *data) 71 { 72 pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len); 73 print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len); 74 } 75 76 static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg, 77 struct rsv *rsv) 78 { 79 struct net_device *dev = priv->ndev; 80 81 netdev_info(dev, "RX packet Len:%d\n", rsv->len); 82 netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg, 83 rsv->next_packet); 84 netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n", 85 RSV_GETBIT(rsv->rxstat, RSV_RXOK), 86 RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE)); 87 netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n", 88 RSV_GETBIT(rsv->rxstat, RSV_CRCERROR), 89 RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR), 90 RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE)); 91 netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n", 92 RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST), 93 RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST), 94 RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV), 95 RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV)); 96 netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n", 97 RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME), 98 RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME), 99 RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE), 100 RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN)); 101 } 102 103 static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg) 104 { 105 struct net_device *dev = priv->ndev; 106 unsigned int val = 0; 107 int ret = regmap_read(priv->ctx.regmap, reg, &val); 108 if (unlikely(ret)) 109 netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n", 110 __func__, ret, reg); 111 return val; 112 } 113 114 static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val) 115 { 116 struct net_device *dev = priv->ndev; 117 int ret = regmap_write(priv->ctx.regmap, reg, val); 118 if (unlikely(ret)) 119 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n", 120 __func__, ret, reg, val); 121 } 122 123 static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg, 124 u16 mask, u16 val) 125 { 126 struct net_device *dev = priv->ndev; 127 int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val); 128 if (unlikely(ret)) 129 netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n", 130 __func__, ret, reg, val, mask); 131 } 132 133 static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg) 134 { 135 struct net_device *dev = priv->ndev; 136 unsigned int val = 0; 137 int ret = regmap_read(priv->ctx.phymap, reg, &val); 138 if (unlikely(ret)) 139 netif_err(priv, drv, dev, "%s: error %d reading %02x\n", 140 __func__, ret, reg); 141 return val; 142 } 143 144 static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val) 145 { 146 struct net_device *dev = priv->ndev; 147 int ret = regmap_write(priv->ctx.phymap, reg, val); 148 if (unlikely(ret)) 149 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n", 150 __func__, ret, reg, val); 151 } 152 153 static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask) 154 { 155 encx24j600_update_reg(priv, reg, mask, 0); 156 } 157 158 static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask) 159 { 160 encx24j600_update_reg(priv, reg, mask, mask); 161 } 162 163 static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd) 164 { 165 struct net_device *dev = priv->ndev; 166 int ret = regmap_write(priv->ctx.regmap, cmd, 0); 167 if (unlikely(ret)) 168 netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n", 169 __func__, ret, cmd); 170 } 171 172 static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data, 173 size_t count) 174 { 175 int ret; 176 mutex_lock(&priv->ctx.mutex); 177 ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count); 178 mutex_unlock(&priv->ctx.mutex); 179 180 return ret; 181 } 182 183 static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg, 184 const u8 *data, size_t count) 185 { 186 int ret; 187 mutex_lock(&priv->ctx.mutex); 188 ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count); 189 mutex_unlock(&priv->ctx.mutex); 190 191 return ret; 192 } 193 194 static void encx24j600_update_phcon1(struct encx24j600_priv *priv) 195 { 196 u16 phcon1 = encx24j600_read_phy(priv, PHCON1); 197 if (priv->autoneg == AUTONEG_ENABLE) { 198 phcon1 |= ANEN | RENEG; 199 } else { 200 phcon1 &= ~ANEN; 201 if (priv->speed == SPEED_100) 202 phcon1 |= SPD100; 203 else 204 phcon1 &= ~SPD100; 205 206 if (priv->full_duplex) 207 phcon1 |= PFULDPX; 208 else 209 phcon1 &= ~PFULDPX; 210 } 211 encx24j600_write_phy(priv, PHCON1, phcon1); 212 } 213 214 /* Waits for autonegotiation to complete. */ 215 static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv) 216 { 217 struct net_device *dev = priv->ndev; 218 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 219 u16 phstat1; 220 u16 estat; 221 int ret = 0; 222 223 phstat1 = encx24j600_read_phy(priv, PHSTAT1); 224 while ((phstat1 & ANDONE) == 0) { 225 if (time_after(jiffies, timeout)) { 226 u16 phstat3; 227 228 netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n"); 229 230 priv->autoneg = AUTONEG_DISABLE; 231 phstat3 = encx24j600_read_phy(priv, PHSTAT3); 232 priv->speed = (phstat3 & PHY3SPD100) 233 ? SPEED_100 : SPEED_10; 234 priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0; 235 encx24j600_update_phcon1(priv); 236 netif_notice(priv, drv, dev, "Using parallel detection: %s/%s", 237 priv->speed == SPEED_100 ? "100" : "10", 238 priv->full_duplex ? "Full" : "Half"); 239 240 return -ETIMEDOUT; 241 } 242 cpu_relax(); 243 phstat1 = encx24j600_read_phy(priv, PHSTAT1); 244 } 245 246 estat = encx24j600_read_reg(priv, ESTAT); 247 if (estat & PHYDPX) { 248 encx24j600_set_bits(priv, MACON2, FULDPX); 249 encx24j600_write_reg(priv, MABBIPG, 0x15); 250 } else { 251 encx24j600_clr_bits(priv, MACON2, FULDPX); 252 encx24j600_write_reg(priv, MABBIPG, 0x12); 253 /* Max retransmittions attempt */ 254 encx24j600_write_reg(priv, MACLCON, 0x370f); 255 } 256 257 return ret; 258 } 259 260 /* Access the PHY to determine link status */ 261 static void encx24j600_check_link_status(struct encx24j600_priv *priv) 262 { 263 struct net_device *dev = priv->ndev; 264 u16 estat; 265 266 estat = encx24j600_read_reg(priv, ESTAT); 267 268 if (estat & PHYLNK) { 269 if (priv->autoneg == AUTONEG_ENABLE) 270 encx24j600_wait_for_autoneg(priv); 271 272 netif_carrier_on(dev); 273 netif_info(priv, ifup, dev, "link up\n"); 274 } else { 275 netif_info(priv, ifdown, dev, "link down\n"); 276 277 /* Re-enable autoneg since we won't know what we might be 278 * connected to when the link is brought back up again. 279 */ 280 priv->autoneg = AUTONEG_ENABLE; 281 priv->full_duplex = true; 282 priv->speed = SPEED_100; 283 netif_carrier_off(dev); 284 } 285 } 286 287 static void encx24j600_int_link_handler(struct encx24j600_priv *priv) 288 { 289 struct net_device *dev = priv->ndev; 290 291 netif_dbg(priv, intr, dev, "%s", __func__); 292 encx24j600_check_link_status(priv); 293 encx24j600_clr_bits(priv, EIR, LINKIF); 294 } 295 296 static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err) 297 { 298 struct net_device *dev = priv->ndev; 299 300 if (!priv->tx_skb) { 301 BUG(); 302 return; 303 } 304 305 mutex_lock(&priv->lock); 306 307 if (err) 308 dev->stats.tx_errors++; 309 else 310 dev->stats.tx_packets++; 311 312 dev->stats.tx_bytes += priv->tx_skb->len; 313 314 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF); 315 316 netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : ""); 317 318 dev_kfree_skb(priv->tx_skb); 319 priv->tx_skb = NULL; 320 321 netif_wake_queue(dev); 322 323 mutex_unlock(&priv->lock); 324 } 325 326 static int encx24j600_receive_packet(struct encx24j600_priv *priv, 327 struct rsv *rsv) 328 { 329 struct net_device *dev = priv->ndev; 330 struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN); 331 if (!skb) { 332 pr_err_ratelimited("RX: OOM: packet dropped\n"); 333 dev->stats.rx_dropped++; 334 return -ENOMEM; 335 } 336 skb_reserve(skb, NET_IP_ALIGN); 337 encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len); 338 339 if (netif_msg_pktdata(priv)) 340 dump_packet("RX", skb->len, skb->data); 341 342 skb->dev = dev; 343 skb->protocol = eth_type_trans(skb, dev); 344 skb->ip_summed = CHECKSUM_COMPLETE; 345 346 /* Maintain stats */ 347 dev->stats.rx_packets++; 348 dev->stats.rx_bytes += rsv->len; 349 priv->next_packet = rsv->next_packet; 350 351 netif_rx(skb); 352 353 return 0; 354 } 355 356 static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count) 357 { 358 struct net_device *dev = priv->ndev; 359 360 while (packet_count--) { 361 struct rsv rsv; 362 u16 newrxtail; 363 364 encx24j600_write_reg(priv, ERXRDPT, priv->next_packet); 365 encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv)); 366 367 if (netif_msg_rx_status(priv)) 368 encx24j600_dump_rsv(priv, __func__, &rsv); 369 370 if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) || 371 (rsv.len > MAX_FRAMELEN)) { 372 netif_err(priv, rx_err, dev, "RX Error %04x\n", 373 rsv.rxstat); 374 dev->stats.rx_errors++; 375 376 if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR)) 377 dev->stats.rx_crc_errors++; 378 if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR)) 379 dev->stats.rx_frame_errors++; 380 if (rsv.len > MAX_FRAMELEN) 381 dev->stats.rx_over_errors++; 382 } else { 383 encx24j600_receive_packet(priv, &rsv); 384 } 385 386 newrxtail = priv->next_packet - 2; 387 if (newrxtail == ENC_RX_BUF_START) 388 newrxtail = SRAM_SIZE - 2; 389 390 encx24j600_cmd(priv, SETPKTDEC); 391 encx24j600_write_reg(priv, ERXTAIL, newrxtail); 392 } 393 } 394 395 static irqreturn_t encx24j600_isr(int irq, void *dev_id) 396 { 397 struct encx24j600_priv *priv = dev_id; 398 struct net_device *dev = priv->ndev; 399 int eir; 400 401 /* Clear interrupts */ 402 encx24j600_cmd(priv, CLREIE); 403 404 eir = encx24j600_read_reg(priv, EIR); 405 406 if (eir & LINKIF) 407 encx24j600_int_link_handler(priv); 408 409 if (eir & TXIF) 410 encx24j600_tx_complete(priv, false); 411 412 if (eir & TXABTIF) 413 encx24j600_tx_complete(priv, true); 414 415 if (eir & RXABTIF) { 416 if (eir & PCFULIF) { 417 /* Packet counter is full */ 418 netif_err(priv, rx_err, dev, "Packet counter full\n"); 419 } 420 dev->stats.rx_dropped++; 421 encx24j600_clr_bits(priv, EIR, RXABTIF); 422 } 423 424 if (eir & PKTIF) { 425 u8 packet_count; 426 427 mutex_lock(&priv->lock); 428 429 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff; 430 while (packet_count) { 431 encx24j600_rx_packets(priv, packet_count); 432 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff; 433 } 434 435 mutex_unlock(&priv->lock); 436 } 437 438 /* Enable interrupts */ 439 encx24j600_cmd(priv, SETEIE); 440 441 return IRQ_HANDLED; 442 } 443 444 static int encx24j600_soft_reset(struct encx24j600_priv *priv) 445 { 446 int ret = 0; 447 int timeout; 448 u16 eudast; 449 450 /* Write and verify a test value to EUDAST */ 451 regcache_cache_bypass(priv->ctx.regmap, true); 452 timeout = 10; 453 do { 454 encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL); 455 eudast = encx24j600_read_reg(priv, EUDAST); 456 usleep_range(25, 100); 457 } while ((eudast != EUDAST_TEST_VAL) && --timeout); 458 regcache_cache_bypass(priv->ctx.regmap, false); 459 460 if (timeout == 0) { 461 ret = -ETIMEDOUT; 462 goto err_out; 463 } 464 465 /* Wait for CLKRDY to become set */ 466 timeout = 10; 467 while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout) 468 usleep_range(25, 100); 469 470 if (timeout == 0) { 471 ret = -ETIMEDOUT; 472 goto err_out; 473 } 474 475 /* Issue a System Reset command */ 476 encx24j600_cmd(priv, SETETHRST); 477 usleep_range(25, 100); 478 479 /* Confirm that EUDAST has 0000h after system reset */ 480 if (encx24j600_read_reg(priv, EUDAST) != 0) { 481 ret = -EINVAL; 482 goto err_out; 483 } 484 485 /* Wait for PHY register and status bits to become available */ 486 usleep_range(256, 1000); 487 488 err_out: 489 return ret; 490 } 491 492 static int encx24j600_hw_reset(struct encx24j600_priv *priv) 493 { 494 int ret; 495 496 mutex_lock(&priv->lock); 497 ret = encx24j600_soft_reset(priv); 498 mutex_unlock(&priv->lock); 499 500 return ret; 501 } 502 503 static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv) 504 { 505 encx24j600_set_bits(priv, ECON2, TXRST); 506 encx24j600_clr_bits(priv, ECON2, TXRST); 507 } 508 509 static void encx24j600_hw_init_tx(struct encx24j600_priv *priv) 510 { 511 /* Reset TX */ 512 encx24j600_reset_hw_tx(priv); 513 514 /* Clear the TXIF flag if were previously set */ 515 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF); 516 517 /* Write the Tx Buffer pointer */ 518 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START); 519 } 520 521 static void encx24j600_hw_init_rx(struct encx24j600_priv *priv) 522 { 523 encx24j600_cmd(priv, DISABLERX); 524 525 /* Set up RX packet start address in the SRAM */ 526 encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START); 527 528 /* Preload the RX Data pointer to the beginning of the RX area */ 529 encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START); 530 531 priv->next_packet = ENC_RX_BUF_START; 532 533 /* Set up RX end address in the SRAM */ 534 encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2); 535 536 /* Reset the user data pointers */ 537 encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE); 538 encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1); 539 540 /* Set Max Frame length */ 541 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN); 542 } 543 544 static void encx24j600_dump_config(struct encx24j600_priv *priv, 545 const char *msg) 546 { 547 pr_info(DRV_NAME ": %s\n", msg); 548 549 /* CHIP configuration */ 550 pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1)); 551 pr_info(DRV_NAME " ECON2: %04X\n", encx24j600_read_reg(priv, ECON2)); 552 pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv, 553 ERXFCON)); 554 pr_info(DRV_NAME " ESTAT: %04X\n", encx24j600_read_reg(priv, ESTAT)); 555 pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR)); 556 pr_info(DRV_NAME " EIDLED: %04X\n", encx24j600_read_reg(priv, EIDLED)); 557 558 /* MAC layer configuration */ 559 pr_info(DRV_NAME " MACON1: %04X\n", encx24j600_read_reg(priv, MACON1)); 560 pr_info(DRV_NAME " MACON2: %04X\n", encx24j600_read_reg(priv, MACON2)); 561 pr_info(DRV_NAME " MAIPG: %04X\n", encx24j600_read_reg(priv, MAIPG)); 562 pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv, 563 MACLCON)); 564 pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv, 565 MABBIPG)); 566 567 /* PHY configuation */ 568 pr_info(DRV_NAME " PHCON1: %04X\n", encx24j600_read_phy(priv, PHCON1)); 569 pr_info(DRV_NAME " PHCON2: %04X\n", encx24j600_read_phy(priv, PHCON2)); 570 pr_info(DRV_NAME " PHANA: %04X\n", encx24j600_read_phy(priv, PHANA)); 571 pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv, 572 PHANLPA)); 573 pr_info(DRV_NAME " PHANE: %04X\n", encx24j600_read_phy(priv, PHANE)); 574 pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv, 575 PHSTAT1)); 576 pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv, 577 PHSTAT2)); 578 pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv, 579 PHSTAT3)); 580 } 581 582 static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv) 583 { 584 switch (priv->rxfilter) { 585 case RXFILTER_PROMISC: 586 encx24j600_set_bits(priv, MACON1, PASSALL); 587 encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN); 588 break; 589 case RXFILTER_MULTI: 590 encx24j600_clr_bits(priv, MACON1, PASSALL); 591 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN); 592 break; 593 case RXFILTER_NORMAL: 594 default: 595 encx24j600_clr_bits(priv, MACON1, PASSALL); 596 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN); 597 break; 598 } 599 } 600 601 static int encx24j600_hw_init(struct encx24j600_priv *priv) 602 { 603 struct net_device *dev = priv->ndev; 604 int ret = 0; 605 u16 eidled; 606 u16 macon2; 607 608 priv->hw_enabled = false; 609 610 eidled = encx24j600_read_reg(priv, EIDLED); 611 if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) { 612 ret = -EINVAL; 613 goto err_out; 614 } 615 616 netif_info(priv, drv, dev, "Silicon rev ID: 0x%02x\n", 617 (eidled & REVID_MASK) >> REVID_SHIFT); 618 619 /* PHY Leds: link status, 620 * LEDA: Link State + collision events 621 * LEDB: Link State + transmit/receive events 622 */ 623 encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00); 624 625 /* Loopback disabled */ 626 encx24j600_write_reg(priv, MACON1, 0x9); 627 628 /* interpacket gap value */ 629 encx24j600_write_reg(priv, MAIPG, 0x0c12); 630 631 /* Write the auto negotiation pattern */ 632 encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT); 633 634 encx24j600_update_phcon1(priv); 635 encx24j600_check_link_status(priv); 636 637 macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER; 638 if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex) 639 macon2 |= FULDPX; 640 641 encx24j600_set_bits(priv, MACON2, macon2); 642 643 priv->rxfilter = RXFILTER_NORMAL; 644 encx24j600_set_rxfilter_mode(priv); 645 646 /* Program the Maximum frame length */ 647 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN); 648 649 /* Init Tx pointers */ 650 encx24j600_hw_init_tx(priv); 651 652 /* Init Rx pointers */ 653 encx24j600_hw_init_rx(priv); 654 655 if (netif_msg_hw(priv)) 656 encx24j600_dump_config(priv, "Hw is initialized"); 657 658 err_out: 659 return ret; 660 } 661 662 static void encx24j600_hw_enable(struct encx24j600_priv *priv) 663 { 664 /* Clear the interrupt flags in case was set */ 665 encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF | 666 PKTIF | LINKIF)); 667 668 /* Enable the interrupts */ 669 encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE | 670 PKTIE | LINKIE | INTIE)); 671 672 /* Enable RX */ 673 encx24j600_cmd(priv, ENABLERX); 674 675 priv->hw_enabled = true; 676 } 677 678 static void encx24j600_hw_disable(struct encx24j600_priv *priv) 679 { 680 /* Disable all interrupts */ 681 encx24j600_write_reg(priv, EIE, 0); 682 683 /* Disable RX */ 684 encx24j600_cmd(priv, DISABLERX); 685 686 priv->hw_enabled = false; 687 } 688 689 static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed, 690 u8 duplex) 691 { 692 struct encx24j600_priv *priv = netdev_priv(dev); 693 int ret = 0; 694 695 if (!priv->hw_enabled) { 696 /* link is in low power mode now; duplex setting 697 * will take effect on next encx24j600_hw_init() 698 */ 699 if (speed == SPEED_10 || speed == SPEED_100) { 700 priv->autoneg = (autoneg == AUTONEG_ENABLE); 701 priv->full_duplex = (duplex == DUPLEX_FULL); 702 priv->speed = (speed == SPEED_100); 703 } else { 704 netif_warn(priv, link, dev, "unsupported link speed setting\n"); 705 /*speeds other than SPEED_10 and SPEED_100 */ 706 /*are not supported by chip */ 707 ret = -EOPNOTSUPP; 708 } 709 } else { 710 netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n"); 711 ret = -EBUSY; 712 } 713 return ret; 714 } 715 716 static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv, 717 unsigned char *ethaddr) 718 { 719 unsigned short val; 720 721 val = encx24j600_read_reg(priv, MAADR1); 722 723 ethaddr[0] = val & 0x00ff; 724 ethaddr[1] = (val & 0xff00) >> 8; 725 726 val = encx24j600_read_reg(priv, MAADR2); 727 728 ethaddr[2] = val & 0x00ffU; 729 ethaddr[3] = (val & 0xff00U) >> 8; 730 731 val = encx24j600_read_reg(priv, MAADR3); 732 733 ethaddr[4] = val & 0x00ffU; 734 ethaddr[5] = (val & 0xff00U) >> 8; 735 } 736 737 /* Program the hardware MAC address from dev->dev_addr.*/ 738 static int encx24j600_set_hw_macaddr(struct net_device *dev) 739 { 740 struct encx24j600_priv *priv = netdev_priv(dev); 741 742 if (priv->hw_enabled) { 743 netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n"); 744 return -EBUSY; 745 } 746 747 mutex_lock(&priv->lock); 748 749 netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n", 750 dev->name, dev->dev_addr); 751 752 encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] | 753 dev->dev_addr[5] << 8)); 754 encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] | 755 dev->dev_addr[3] << 8)); 756 encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] | 757 dev->dev_addr[1] << 8)); 758 759 mutex_unlock(&priv->lock); 760 761 return 0; 762 } 763 764 /* Store the new hardware address in dev->dev_addr, and update the MAC.*/ 765 static int encx24j600_set_mac_address(struct net_device *dev, void *addr) 766 { 767 struct sockaddr *address = addr; 768 769 if (netif_running(dev)) 770 return -EBUSY; 771 if (!is_valid_ether_addr(address->sa_data)) 772 return -EADDRNOTAVAIL; 773 774 memcpy(dev->dev_addr, address->sa_data, dev->addr_len); 775 return encx24j600_set_hw_macaddr(dev); 776 } 777 778 static int encx24j600_open(struct net_device *dev) 779 { 780 struct encx24j600_priv *priv = netdev_priv(dev); 781 782 int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr, 783 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 784 DRV_NAME, priv); 785 if (unlikely(ret < 0)) { 786 netdev_err(dev, "request irq %d failed (ret = %d)\n", 787 priv->ctx.spi->irq, ret); 788 return ret; 789 } 790 791 encx24j600_hw_disable(priv); 792 encx24j600_hw_init(priv); 793 encx24j600_hw_enable(priv); 794 netif_start_queue(dev); 795 796 return 0; 797 } 798 799 static int encx24j600_stop(struct net_device *dev) 800 { 801 struct encx24j600_priv *priv = netdev_priv(dev); 802 803 netif_stop_queue(dev); 804 free_irq(priv->ctx.spi->irq, priv); 805 return 0; 806 } 807 808 static void encx24j600_setrx_proc(struct kthread_work *ws) 809 { 810 struct encx24j600_priv *priv = 811 container_of(ws, struct encx24j600_priv, setrx_work); 812 813 mutex_lock(&priv->lock); 814 encx24j600_set_rxfilter_mode(priv); 815 mutex_unlock(&priv->lock); 816 } 817 818 static void encx24j600_set_multicast_list(struct net_device *dev) 819 { 820 struct encx24j600_priv *priv = netdev_priv(dev); 821 int oldfilter = priv->rxfilter; 822 823 if (dev->flags & IFF_PROMISC) { 824 netif_dbg(priv, link, dev, "promiscuous mode\n"); 825 priv->rxfilter = RXFILTER_PROMISC; 826 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) { 827 netif_dbg(priv, link, dev, "%smulticast mode\n", 828 (dev->flags & IFF_ALLMULTI) ? "all-" : ""); 829 priv->rxfilter = RXFILTER_MULTI; 830 } else { 831 netif_dbg(priv, link, dev, "normal mode\n"); 832 priv->rxfilter = RXFILTER_NORMAL; 833 } 834 835 if (oldfilter != priv->rxfilter) 836 queue_kthread_work(&priv->kworker, &priv->setrx_work); 837 } 838 839 static void encx24j600_hw_tx(struct encx24j600_priv *priv) 840 { 841 struct net_device *dev = priv->ndev; 842 netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n", 843 priv->tx_skb->len); 844 845 if (netif_msg_pktdata(priv)) 846 dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data); 847 848 if (encx24j600_read_reg(priv, EIR) & TXABTIF) 849 /* Last transmition aborted due to error. Reset TX interface */ 850 encx24j600_reset_hw_tx(priv); 851 852 /* Clear the TXIF flag if were previously set */ 853 encx24j600_clr_bits(priv, EIR, TXIF); 854 855 /* Set the data pointer to the TX buffer address in the SRAM */ 856 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START); 857 858 /* Copy the packet into the SRAM */ 859 encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data, 860 priv->tx_skb->len); 861 862 /* Program the Tx buffer start pointer */ 863 encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START); 864 865 /* Program the packet length */ 866 encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len); 867 868 /* Start the transmission */ 869 encx24j600_cmd(priv, SETTXRTS); 870 } 871 872 static void encx24j600_tx_proc(struct kthread_work *ws) 873 { 874 struct encx24j600_priv *priv = 875 container_of(ws, struct encx24j600_priv, tx_work); 876 877 mutex_lock(&priv->lock); 878 encx24j600_hw_tx(priv); 879 mutex_unlock(&priv->lock); 880 } 881 882 static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev) 883 { 884 struct encx24j600_priv *priv = netdev_priv(dev); 885 886 netif_stop_queue(dev); 887 888 /* save the timestamp */ 889 dev->trans_start = jiffies; 890 891 /* Remember the skb for deferred processing */ 892 priv->tx_skb = skb; 893 894 queue_kthread_work(&priv->kworker, &priv->tx_work); 895 896 return NETDEV_TX_OK; 897 } 898 899 /* Deal with a transmit timeout */ 900 static void encx24j600_tx_timeout(struct net_device *dev) 901 { 902 struct encx24j600_priv *priv = netdev_priv(dev); 903 904 netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n", 905 jiffies, jiffies - dev->trans_start); 906 907 dev->stats.tx_errors++; 908 netif_wake_queue(dev); 909 return; 910 } 911 912 static int encx24j600_get_regs_len(struct net_device *dev) 913 { 914 return SFR_REG_COUNT; 915 } 916 917 static void encx24j600_get_regs(struct net_device *dev, 918 struct ethtool_regs *regs, void *p) 919 { 920 struct encx24j600_priv *priv = netdev_priv(dev); 921 u16 *buff = p; 922 u8 reg; 923 924 regs->version = 1; 925 mutex_lock(&priv->lock); 926 for (reg = 0; reg < SFR_REG_COUNT; reg += 2) { 927 unsigned int val = 0; 928 /* ignore errors for unreadable registers */ 929 regmap_read(priv->ctx.regmap, reg, &val); 930 buff[reg] = val & 0xffff; 931 } 932 mutex_unlock(&priv->lock); 933 } 934 935 static void encx24j600_get_drvinfo(struct net_device *dev, 936 struct ethtool_drvinfo *info) 937 { 938 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 939 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 940 strlcpy(info->bus_info, dev_name(dev->dev.parent), 941 sizeof(info->bus_info)); 942 } 943 944 static int encx24j600_get_settings(struct net_device *dev, 945 struct ethtool_cmd *cmd) 946 { 947 struct encx24j600_priv *priv = netdev_priv(dev); 948 949 cmd->transceiver = XCVR_INTERNAL; 950 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 951 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 952 SUPPORTED_Autoneg | SUPPORTED_TP; 953 954 ethtool_cmd_speed_set(cmd, priv->speed); 955 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 956 cmd->port = PORT_TP; 957 cmd->autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 958 959 return 0; 960 } 961 962 static int encx24j600_set_settings(struct net_device *dev, 963 struct ethtool_cmd *cmd) 964 { 965 return encx24j600_setlink(dev, cmd->autoneg, 966 ethtool_cmd_speed(cmd), cmd->duplex); 967 } 968 969 static u32 encx24j600_get_msglevel(struct net_device *dev) 970 { 971 struct encx24j600_priv *priv = netdev_priv(dev); 972 return priv->msg_enable; 973 } 974 975 static void encx24j600_set_msglevel(struct net_device *dev, u32 val) 976 { 977 struct encx24j600_priv *priv = netdev_priv(dev); 978 priv->msg_enable = val; 979 } 980 981 static const struct ethtool_ops encx24j600_ethtool_ops = { 982 .get_settings = encx24j600_get_settings, 983 .set_settings = encx24j600_set_settings, 984 .get_drvinfo = encx24j600_get_drvinfo, 985 .get_msglevel = encx24j600_get_msglevel, 986 .set_msglevel = encx24j600_set_msglevel, 987 .get_regs_len = encx24j600_get_regs_len, 988 .get_regs = encx24j600_get_regs, 989 }; 990 991 static const struct net_device_ops encx24j600_netdev_ops = { 992 .ndo_open = encx24j600_open, 993 .ndo_stop = encx24j600_stop, 994 .ndo_start_xmit = encx24j600_tx, 995 .ndo_set_rx_mode = encx24j600_set_multicast_list, 996 .ndo_set_mac_address = encx24j600_set_mac_address, 997 .ndo_tx_timeout = encx24j600_tx_timeout, 998 .ndo_validate_addr = eth_validate_addr, 999 }; 1000 1001 static int encx24j600_spi_probe(struct spi_device *spi) 1002 { 1003 int ret; 1004 1005 struct net_device *ndev; 1006 struct encx24j600_priv *priv; 1007 1008 ndev = alloc_etherdev(sizeof(struct encx24j600_priv)); 1009 1010 if (!ndev) { 1011 ret = -ENOMEM; 1012 goto error_out; 1013 } 1014 1015 priv = netdev_priv(ndev); 1016 spi_set_drvdata(spi, priv); 1017 dev_set_drvdata(&spi->dev, priv); 1018 SET_NETDEV_DEV(ndev, &spi->dev); 1019 1020 priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1021 priv->ndev = ndev; 1022 1023 /* Default configuration PHY configuration */ 1024 priv->full_duplex = true; 1025 priv->autoneg = AUTONEG_ENABLE; 1026 priv->speed = SPEED_100; 1027 1028 priv->ctx.spi = spi; 1029 devm_regmap_init_encx24j600(&spi->dev, &priv->ctx); 1030 ndev->irq = spi->irq; 1031 ndev->netdev_ops = &encx24j600_netdev_ops; 1032 1033 mutex_init(&priv->lock); 1034 1035 /* Reset device and check if it is connected */ 1036 if (encx24j600_hw_reset(priv)) { 1037 netif_err(priv, probe, ndev, 1038 DRV_NAME ": Chip is not detected\n"); 1039 ret = -EIO; 1040 goto out_free; 1041 } 1042 1043 /* Initialize the device HW to the consistent state */ 1044 if (encx24j600_hw_init(priv)) { 1045 netif_err(priv, probe, ndev, 1046 DRV_NAME ": HW initialization error\n"); 1047 ret = -EIO; 1048 goto out_free; 1049 } 1050 1051 init_kthread_worker(&priv->kworker); 1052 init_kthread_work(&priv->tx_work, encx24j600_tx_proc); 1053 init_kthread_work(&priv->setrx_work, encx24j600_setrx_proc); 1054 1055 priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker, 1056 "encx24j600"); 1057 1058 if (IS_ERR(priv->kworker_task)) { 1059 ret = PTR_ERR(priv->kworker_task); 1060 goto out_free; 1061 } 1062 1063 /* Get the MAC address from the chip */ 1064 encx24j600_hw_get_macaddr(priv, ndev->dev_addr); 1065 1066 ndev->ethtool_ops = &encx24j600_ethtool_ops; 1067 1068 ret = register_netdev(ndev); 1069 if (unlikely(ret)) { 1070 netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n", 1071 ret); 1072 goto out_free; 1073 } 1074 1075 netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr); 1076 1077 return ret; 1078 1079 out_free: 1080 free_netdev(ndev); 1081 1082 error_out: 1083 return ret; 1084 } 1085 1086 static int encx24j600_spi_remove(struct spi_device *spi) 1087 { 1088 struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev); 1089 1090 unregister_netdev(priv->ndev); 1091 1092 free_netdev(priv->ndev); 1093 1094 return 0; 1095 } 1096 1097 static const struct spi_device_id encx24j600_spi_id_table[] = { 1098 { .name = "encx24j600" }, 1099 { /* sentinel */ } 1100 }; 1101 MODULE_DEVICE_TABLE(spi, encx24j600_spi_id_table); 1102 1103 static struct spi_driver encx24j600_spi_net_driver = { 1104 .driver = { 1105 .name = DRV_NAME, 1106 .owner = THIS_MODULE, 1107 .bus = &spi_bus_type, 1108 }, 1109 .probe = encx24j600_spi_probe, 1110 .remove = encx24j600_spi_remove, 1111 .id_table = encx24j600_spi_id_table, 1112 }; 1113 1114 static int __init encx24j600_init(void) 1115 { 1116 return spi_register_driver(&encx24j600_spi_net_driver); 1117 } 1118 module_init(encx24j600_init); 1119 1120 static void encx24j600_exit(void) 1121 { 1122 spi_unregister_driver(&encx24j600_spi_net_driver); 1123 } 1124 module_exit(encx24j600_exit); 1125 1126 MODULE_DESCRIPTION(DRV_NAME " ethernet driver"); 1127 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1128 MODULE_LICENSE("GPL"); 1129 MODULE_ALIAS("spi:" DRV_NAME); 1130