1 /** 2 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver 3 * 4 * Copyright (c) 2009-2010 Micrel, Inc. 5 * Tristram Ha <Tristram.Ha@micrel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/ioport.h> 24 #include <linux/pci.h> 25 #include <linux/proc_fs.h> 26 #include <linux/mii.h> 27 #include <linux/platform_device.h> 28 #include <linux/ethtool.h> 29 #include <linux/etherdevice.h> 30 #include <linux/in.h> 31 #include <linux/ip.h> 32 #include <linux/if_vlan.h> 33 #include <linux/crc32.h> 34 #include <linux/sched.h> 35 #include <linux/slab.h> 36 37 38 /* DMA Registers */ 39 40 #define KS_DMA_TX_CTRL 0x0000 41 #define DMA_TX_ENABLE 0x00000001 42 #define DMA_TX_CRC_ENABLE 0x00000002 43 #define DMA_TX_PAD_ENABLE 0x00000004 44 #define DMA_TX_LOOPBACK 0x00000100 45 #define DMA_TX_FLOW_ENABLE 0x00000200 46 #define DMA_TX_CSUM_IP 0x00010000 47 #define DMA_TX_CSUM_TCP 0x00020000 48 #define DMA_TX_CSUM_UDP 0x00040000 49 #define DMA_TX_BURST_SIZE 0x3F000000 50 51 #define KS_DMA_RX_CTRL 0x0004 52 #define DMA_RX_ENABLE 0x00000001 53 #define KS884X_DMA_RX_MULTICAST 0x00000002 54 #define DMA_RX_PROMISCUOUS 0x00000004 55 #define DMA_RX_ERROR 0x00000008 56 #define DMA_RX_UNICAST 0x00000010 57 #define DMA_RX_ALL_MULTICAST 0x00000020 58 #define DMA_RX_BROADCAST 0x00000040 59 #define DMA_RX_FLOW_ENABLE 0x00000200 60 #define DMA_RX_CSUM_IP 0x00010000 61 #define DMA_RX_CSUM_TCP 0x00020000 62 #define DMA_RX_CSUM_UDP 0x00040000 63 #define DMA_RX_BURST_SIZE 0x3F000000 64 65 #define DMA_BURST_SHIFT 24 66 #define DMA_BURST_DEFAULT 8 67 68 #define KS_DMA_TX_START 0x0008 69 #define KS_DMA_RX_START 0x000C 70 #define DMA_START 0x00000001 71 72 #define KS_DMA_TX_ADDR 0x0010 73 #define KS_DMA_RX_ADDR 0x0014 74 75 #define DMA_ADDR_LIST_MASK 0xFFFFFFFC 76 #define DMA_ADDR_LIST_SHIFT 2 77 78 /* MTR0 */ 79 #define KS884X_MULTICAST_0_OFFSET 0x0020 80 #define KS884X_MULTICAST_1_OFFSET 0x0021 81 #define KS884X_MULTICAST_2_OFFSET 0x0022 82 #define KS884x_MULTICAST_3_OFFSET 0x0023 83 /* MTR1 */ 84 #define KS884X_MULTICAST_4_OFFSET 0x0024 85 #define KS884X_MULTICAST_5_OFFSET 0x0025 86 #define KS884X_MULTICAST_6_OFFSET 0x0026 87 #define KS884X_MULTICAST_7_OFFSET 0x0027 88 89 /* Interrupt Registers */ 90 91 /* INTEN */ 92 #define KS884X_INTERRUPTS_ENABLE 0x0028 93 /* INTST */ 94 #define KS884X_INTERRUPTS_STATUS 0x002C 95 96 #define KS884X_INT_RX_STOPPED 0x02000000 97 #define KS884X_INT_TX_STOPPED 0x04000000 98 #define KS884X_INT_RX_OVERRUN 0x08000000 99 #define KS884X_INT_TX_EMPTY 0x10000000 100 #define KS884X_INT_RX 0x20000000 101 #define KS884X_INT_TX 0x40000000 102 #define KS884X_INT_PHY 0x80000000 103 104 #define KS884X_INT_RX_MASK \ 105 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN) 106 #define KS884X_INT_TX_MASK \ 107 (KS884X_INT_TX | KS884X_INT_TX_EMPTY) 108 #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY) 109 110 /* MAC Additional Station Address */ 111 112 /* MAAL0 */ 113 #define KS_ADD_ADDR_0_LO 0x0080 114 /* MAAH0 */ 115 #define KS_ADD_ADDR_0_HI 0x0084 116 /* MAAL1 */ 117 #define KS_ADD_ADDR_1_LO 0x0088 118 /* MAAH1 */ 119 #define KS_ADD_ADDR_1_HI 0x008C 120 /* MAAL2 */ 121 #define KS_ADD_ADDR_2_LO 0x0090 122 /* MAAH2 */ 123 #define KS_ADD_ADDR_2_HI 0x0094 124 /* MAAL3 */ 125 #define KS_ADD_ADDR_3_LO 0x0098 126 /* MAAH3 */ 127 #define KS_ADD_ADDR_3_HI 0x009C 128 /* MAAL4 */ 129 #define KS_ADD_ADDR_4_LO 0x00A0 130 /* MAAH4 */ 131 #define KS_ADD_ADDR_4_HI 0x00A4 132 /* MAAL5 */ 133 #define KS_ADD_ADDR_5_LO 0x00A8 134 /* MAAH5 */ 135 #define KS_ADD_ADDR_5_HI 0x00AC 136 /* MAAL6 */ 137 #define KS_ADD_ADDR_6_LO 0x00B0 138 /* MAAH6 */ 139 #define KS_ADD_ADDR_6_HI 0x00B4 140 /* MAAL7 */ 141 #define KS_ADD_ADDR_7_LO 0x00B8 142 /* MAAH7 */ 143 #define KS_ADD_ADDR_7_HI 0x00BC 144 /* MAAL8 */ 145 #define KS_ADD_ADDR_8_LO 0x00C0 146 /* MAAH8 */ 147 #define KS_ADD_ADDR_8_HI 0x00C4 148 /* MAAL9 */ 149 #define KS_ADD_ADDR_9_LO 0x00C8 150 /* MAAH9 */ 151 #define KS_ADD_ADDR_9_HI 0x00CC 152 /* MAAL10 */ 153 #define KS_ADD_ADDR_A_LO 0x00D0 154 /* MAAH10 */ 155 #define KS_ADD_ADDR_A_HI 0x00D4 156 /* MAAL11 */ 157 #define KS_ADD_ADDR_B_LO 0x00D8 158 /* MAAH11 */ 159 #define KS_ADD_ADDR_B_HI 0x00DC 160 /* MAAL12 */ 161 #define KS_ADD_ADDR_C_LO 0x00E0 162 /* MAAH12 */ 163 #define KS_ADD_ADDR_C_HI 0x00E4 164 /* MAAL13 */ 165 #define KS_ADD_ADDR_D_LO 0x00E8 166 /* MAAH13 */ 167 #define KS_ADD_ADDR_D_HI 0x00EC 168 /* MAAL14 */ 169 #define KS_ADD_ADDR_E_LO 0x00F0 170 /* MAAH14 */ 171 #define KS_ADD_ADDR_E_HI 0x00F4 172 /* MAAL15 */ 173 #define KS_ADD_ADDR_F_LO 0x00F8 174 /* MAAH15 */ 175 #define KS_ADD_ADDR_F_HI 0x00FC 176 177 #define ADD_ADDR_HI_MASK 0x0000FFFF 178 #define ADD_ADDR_ENABLE 0x80000000 179 #define ADD_ADDR_INCR 8 180 181 /* Miscellaneous Registers */ 182 183 /* MARL */ 184 #define KS884X_ADDR_0_OFFSET 0x0200 185 #define KS884X_ADDR_1_OFFSET 0x0201 186 /* MARM */ 187 #define KS884X_ADDR_2_OFFSET 0x0202 188 #define KS884X_ADDR_3_OFFSET 0x0203 189 /* MARH */ 190 #define KS884X_ADDR_4_OFFSET 0x0204 191 #define KS884X_ADDR_5_OFFSET 0x0205 192 193 /* OBCR */ 194 #define KS884X_BUS_CTRL_OFFSET 0x0210 195 196 #define BUS_SPEED_125_MHZ 0x0000 197 #define BUS_SPEED_62_5_MHZ 0x0001 198 #define BUS_SPEED_41_66_MHZ 0x0002 199 #define BUS_SPEED_25_MHZ 0x0003 200 201 /* EEPCR */ 202 #define KS884X_EEPROM_CTRL_OFFSET 0x0212 203 204 #define EEPROM_CHIP_SELECT 0x0001 205 #define EEPROM_SERIAL_CLOCK 0x0002 206 #define EEPROM_DATA_OUT 0x0004 207 #define EEPROM_DATA_IN 0x0008 208 #define EEPROM_ACCESS_ENABLE 0x0010 209 210 /* MBIR */ 211 #define KS884X_MEM_INFO_OFFSET 0x0214 212 213 #define RX_MEM_TEST_FAILED 0x0008 214 #define RX_MEM_TEST_FINISHED 0x0010 215 #define TX_MEM_TEST_FAILED 0x0800 216 #define TX_MEM_TEST_FINISHED 0x1000 217 218 /* GCR */ 219 #define KS884X_GLOBAL_CTRL_OFFSET 0x0216 220 #define GLOBAL_SOFTWARE_RESET 0x0001 221 222 #define KS8841_POWER_MANAGE_OFFSET 0x0218 223 224 /* WFCR */ 225 #define KS8841_WOL_CTRL_OFFSET 0x021A 226 #define KS8841_WOL_MAGIC_ENABLE 0x0080 227 #define KS8841_WOL_FRAME3_ENABLE 0x0008 228 #define KS8841_WOL_FRAME2_ENABLE 0x0004 229 #define KS8841_WOL_FRAME1_ENABLE 0x0002 230 #define KS8841_WOL_FRAME0_ENABLE 0x0001 231 232 /* WF0 */ 233 #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220 234 #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224 235 #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228 236 237 /* IACR */ 238 #define KS884X_IACR_P 0x04A0 239 #define KS884X_IACR_OFFSET KS884X_IACR_P 240 241 /* IADR1 */ 242 #define KS884X_IADR1_P 0x04A2 243 #define KS884X_IADR2_P 0x04A4 244 #define KS884X_IADR3_P 0x04A6 245 #define KS884X_IADR4_P 0x04A8 246 #define KS884X_IADR5_P 0x04AA 247 248 #define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P 249 #define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1) 250 251 #define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P 252 #define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1) 253 #define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P 254 #define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1) 255 #define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P 256 #define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1) 257 #define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P 258 #define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1) 259 #define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P 260 261 /* P1MBCR */ 262 #define KS884X_P1MBCR_P 0x04D0 263 #define KS884X_P1MBSR_P 0x04D2 264 #define KS884X_PHY1ILR_P 0x04D4 265 #define KS884X_PHY1IHR_P 0x04D6 266 #define KS884X_P1ANAR_P 0x04D8 267 #define KS884X_P1ANLPR_P 0x04DA 268 269 /* P2MBCR */ 270 #define KS884X_P2MBCR_P 0x04E0 271 #define KS884X_P2MBSR_P 0x04E2 272 #define KS884X_PHY2ILR_P 0x04E4 273 #define KS884X_PHY2IHR_P 0x04E6 274 #define KS884X_P2ANAR_P 0x04E8 275 #define KS884X_P2ANLPR_P 0x04EA 276 277 #define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P 278 #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P) 279 280 #define KS884X_PHY_CTRL_OFFSET 0x00 281 282 /* Mode Control Register */ 283 #define PHY_REG_CTRL 0 284 285 #define PHY_RESET 0x8000 286 #define PHY_LOOPBACK 0x4000 287 #define PHY_SPEED_100MBIT 0x2000 288 #define PHY_AUTO_NEG_ENABLE 0x1000 289 #define PHY_POWER_DOWN 0x0800 290 #define PHY_MII_DISABLE 0x0400 291 #define PHY_AUTO_NEG_RESTART 0x0200 292 #define PHY_FULL_DUPLEX 0x0100 293 #define PHY_COLLISION_TEST 0x0080 294 #define PHY_HP_MDIX 0x0020 295 #define PHY_FORCE_MDIX 0x0010 296 #define PHY_AUTO_MDIX_DISABLE 0x0008 297 #define PHY_REMOTE_FAULT_DISABLE 0x0004 298 #define PHY_TRANSMIT_DISABLE 0x0002 299 #define PHY_LED_DISABLE 0x0001 300 301 #define KS884X_PHY_STATUS_OFFSET 0x02 302 303 /* Mode Status Register */ 304 #define PHY_REG_STATUS 1 305 306 #define PHY_100BT4_CAPABLE 0x8000 307 #define PHY_100BTX_FD_CAPABLE 0x4000 308 #define PHY_100BTX_CAPABLE 0x2000 309 #define PHY_10BT_FD_CAPABLE 0x1000 310 #define PHY_10BT_CAPABLE 0x0800 311 #define PHY_MII_SUPPRESS_CAPABLE 0x0040 312 #define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020 313 #define PHY_REMOTE_FAULT 0x0010 314 #define PHY_AUTO_NEG_CAPABLE 0x0008 315 #define PHY_LINK_STATUS 0x0004 316 #define PHY_JABBER_DETECT 0x0002 317 #define PHY_EXTENDED_CAPABILITY 0x0001 318 319 #define KS884X_PHY_ID_1_OFFSET 0x04 320 #define KS884X_PHY_ID_2_OFFSET 0x06 321 322 /* PHY Identifier Registers */ 323 #define PHY_REG_ID_1 2 324 #define PHY_REG_ID_2 3 325 326 #define KS884X_PHY_AUTO_NEG_OFFSET 0x08 327 328 /* Auto-Negotiation Advertisement Register */ 329 #define PHY_REG_AUTO_NEGOTIATION 4 330 331 #define PHY_AUTO_NEG_NEXT_PAGE 0x8000 332 #define PHY_AUTO_NEG_REMOTE_FAULT 0x2000 333 /* Not supported. */ 334 #define PHY_AUTO_NEG_ASYM_PAUSE 0x0800 335 #define PHY_AUTO_NEG_SYM_PAUSE 0x0400 336 #define PHY_AUTO_NEG_100BT4 0x0200 337 #define PHY_AUTO_NEG_100BTX_FD 0x0100 338 #define PHY_AUTO_NEG_100BTX 0x0080 339 #define PHY_AUTO_NEG_10BT_FD 0x0040 340 #define PHY_AUTO_NEG_10BT 0x0020 341 #define PHY_AUTO_NEG_SELECTOR 0x001F 342 #define PHY_AUTO_NEG_802_3 0x0001 343 344 #define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE) 345 346 #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A 347 348 /* Auto-Negotiation Link Partner Ability Register */ 349 #define PHY_REG_REMOTE_CAPABILITY 5 350 351 #define PHY_REMOTE_NEXT_PAGE 0x8000 352 #define PHY_REMOTE_ACKNOWLEDGE 0x4000 353 #define PHY_REMOTE_REMOTE_FAULT 0x2000 354 #define PHY_REMOTE_SYM_PAUSE 0x0400 355 #define PHY_REMOTE_100BTX_FD 0x0100 356 #define PHY_REMOTE_100BTX 0x0080 357 #define PHY_REMOTE_10BT_FD 0x0040 358 #define PHY_REMOTE_10BT 0x0020 359 360 /* P1VCT */ 361 #define KS884X_P1VCT_P 0x04F0 362 #define KS884X_P1PHYCTRL_P 0x04F2 363 364 /* P2VCT */ 365 #define KS884X_P2VCT_P 0x04F4 366 #define KS884X_P2PHYCTRL_P 0x04F6 367 368 #define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P 369 #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P) 370 371 #define KS884X_PHY_LINK_MD_OFFSET 0x00 372 373 #define PHY_START_CABLE_DIAG 0x8000 374 #define PHY_CABLE_DIAG_RESULT 0x6000 375 #define PHY_CABLE_STAT_NORMAL 0x0000 376 #define PHY_CABLE_STAT_OPEN 0x2000 377 #define PHY_CABLE_STAT_SHORT 0x4000 378 #define PHY_CABLE_STAT_FAILED 0x6000 379 #define PHY_CABLE_10M_SHORT 0x1000 380 #define PHY_CABLE_FAULT_COUNTER 0x01FF 381 382 #define KS884X_PHY_PHY_CTRL_OFFSET 0x02 383 384 #define PHY_STAT_REVERSED_POLARITY 0x0020 385 #define PHY_STAT_MDIX 0x0010 386 #define PHY_FORCE_LINK 0x0008 387 #define PHY_POWER_SAVING_DISABLE 0x0004 388 #define PHY_REMOTE_LOOPBACK 0x0002 389 390 /* SIDER */ 391 #define KS884X_SIDER_P 0x0400 392 #define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P 393 #define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1) 394 395 #define REG_FAMILY_ID 0x88 396 397 #define REG_CHIP_ID_41 0x8810 398 #define REG_CHIP_ID_42 0x8800 399 400 #define KS884X_CHIP_ID_MASK_41 0xFF10 401 #define KS884X_CHIP_ID_MASK 0xFFF0 402 #define KS884X_CHIP_ID_SHIFT 4 403 #define KS884X_REVISION_MASK 0x000E 404 #define KS884X_REVISION_SHIFT 1 405 #define KS8842_START 0x0001 406 407 #define CHIP_IP_41_M 0x8810 408 #define CHIP_IP_42_M 0x8800 409 #define CHIP_IP_61_M 0x8890 410 #define CHIP_IP_62_M 0x8880 411 412 #define CHIP_IP_41_P 0x8850 413 #define CHIP_IP_42_P 0x8840 414 #define CHIP_IP_61_P 0x88D0 415 #define CHIP_IP_62_P 0x88C0 416 417 /* SGCR1 */ 418 #define KS8842_SGCR1_P 0x0402 419 #define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P 420 421 #define SWITCH_PASS_ALL 0x8000 422 #define SWITCH_TX_FLOW_CTRL 0x2000 423 #define SWITCH_RX_FLOW_CTRL 0x1000 424 #define SWITCH_CHECK_LENGTH 0x0800 425 #define SWITCH_AGING_ENABLE 0x0400 426 #define SWITCH_FAST_AGING 0x0200 427 #define SWITCH_AGGR_BACKOFF 0x0100 428 #define SWITCH_PASS_PAUSE 0x0008 429 #define SWITCH_LINK_AUTO_AGING 0x0001 430 431 /* SGCR2 */ 432 #define KS8842_SGCR2_P 0x0404 433 #define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P 434 435 #define SWITCH_VLAN_ENABLE 0x8000 436 #define SWITCH_IGMP_SNOOP 0x4000 437 #define IPV6_MLD_SNOOP_ENABLE 0x2000 438 #define IPV6_MLD_SNOOP_OPTION 0x1000 439 #define PRIORITY_SCHEME_SELECT 0x0800 440 #define SWITCH_MIRROR_RX_TX 0x0100 441 #define UNICAST_VLAN_BOUNDARY 0x0080 442 #define MULTICAST_STORM_DISABLE 0x0040 443 #define SWITCH_BACK_PRESSURE 0x0020 444 #define FAIR_FLOW_CTRL 0x0010 445 #define NO_EXC_COLLISION_DROP 0x0008 446 #define SWITCH_HUGE_PACKET 0x0004 447 #define SWITCH_LEGAL_PACKET 0x0002 448 #define SWITCH_BUF_RESERVE 0x0001 449 450 /* SGCR3 */ 451 #define KS8842_SGCR3_P 0x0406 452 #define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P 453 454 #define BROADCAST_STORM_RATE_LO 0xFF00 455 #define SWITCH_REPEATER 0x0080 456 #define SWITCH_HALF_DUPLEX 0x0040 457 #define SWITCH_FLOW_CTRL 0x0020 458 #define SWITCH_10_MBIT 0x0010 459 #define SWITCH_REPLACE_NULL_VID 0x0008 460 #define BROADCAST_STORM_RATE_HI 0x0007 461 462 #define BROADCAST_STORM_RATE 0x07FF 463 464 /* SGCR4 */ 465 #define KS8842_SGCR4_P 0x0408 466 467 /* SGCR5 */ 468 #define KS8842_SGCR5_P 0x040A 469 #define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P 470 471 #define LED_MODE 0x8200 472 #define LED_SPEED_DUPLEX_ACT 0x0000 473 #define LED_SPEED_DUPLEX_LINK_ACT 0x8000 474 #define LED_DUPLEX_10_100 0x0200 475 476 /* SGCR6 */ 477 #define KS8842_SGCR6_P 0x0410 478 #define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P 479 480 #define KS8842_PRIORITY_MASK 3 481 #define KS8842_PRIORITY_SHIFT 2 482 483 /* SGCR7 */ 484 #define KS8842_SGCR7_P 0x0412 485 #define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P 486 487 #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008 488 #define SWITCH_UNK_DEF_PORT_3 0x0004 489 #define SWITCH_UNK_DEF_PORT_2 0x0002 490 #define SWITCH_UNK_DEF_PORT_1 0x0001 491 492 /* MACAR1 */ 493 #define KS8842_MACAR1_P 0x0470 494 #define KS8842_MACAR2_P 0x0472 495 #define KS8842_MACAR3_P 0x0474 496 #define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P 497 #define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1) 498 #define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P 499 #define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1) 500 #define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P 501 #define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1) 502 503 /* TOSR1 */ 504 #define KS8842_TOSR1_P 0x0480 505 #define KS8842_TOSR2_P 0x0482 506 #define KS8842_TOSR3_P 0x0484 507 #define KS8842_TOSR4_P 0x0486 508 #define KS8842_TOSR5_P 0x0488 509 #define KS8842_TOSR6_P 0x048A 510 #define KS8842_TOSR7_P 0x0490 511 #define KS8842_TOSR8_P 0x0492 512 #define KS8842_TOS_1_OFFSET KS8842_TOSR1_P 513 #define KS8842_TOS_2_OFFSET KS8842_TOSR2_P 514 #define KS8842_TOS_3_OFFSET KS8842_TOSR3_P 515 #define KS8842_TOS_4_OFFSET KS8842_TOSR4_P 516 #define KS8842_TOS_5_OFFSET KS8842_TOSR5_P 517 #define KS8842_TOS_6_OFFSET KS8842_TOSR6_P 518 519 #define KS8842_TOS_7_OFFSET KS8842_TOSR7_P 520 #define KS8842_TOS_8_OFFSET KS8842_TOSR8_P 521 522 /* P1CR1 */ 523 #define KS8842_P1CR1_P 0x0500 524 #define KS8842_P1CR2_P 0x0502 525 #define KS8842_P1VIDR_P 0x0504 526 #define KS8842_P1CR3_P 0x0506 527 #define KS8842_P1IRCR_P 0x0508 528 #define KS8842_P1ERCR_P 0x050A 529 #define KS884X_P1SCSLMD_P 0x0510 530 #define KS884X_P1CR4_P 0x0512 531 #define KS884X_P1SR_P 0x0514 532 533 /* P2CR1 */ 534 #define KS8842_P2CR1_P 0x0520 535 #define KS8842_P2CR2_P 0x0522 536 #define KS8842_P2VIDR_P 0x0524 537 #define KS8842_P2CR3_P 0x0526 538 #define KS8842_P2IRCR_P 0x0528 539 #define KS8842_P2ERCR_P 0x052A 540 #define KS884X_P2SCSLMD_P 0x0530 541 #define KS884X_P2CR4_P 0x0532 542 #define KS884X_P2SR_P 0x0534 543 544 /* P3CR1 */ 545 #define KS8842_P3CR1_P 0x0540 546 #define KS8842_P3CR2_P 0x0542 547 #define KS8842_P3VIDR_P 0x0544 548 #define KS8842_P3CR3_P 0x0546 549 #define KS8842_P3IRCR_P 0x0548 550 #define KS8842_P3ERCR_P 0x054A 551 552 #define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P 553 #define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P 554 #define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P 555 556 #define PORT_CTRL_ADDR(port, addr) \ 557 (addr = KS8842_PORT_1_CTRL_1 + (port) * \ 558 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1)) 559 560 #define KS8842_PORT_CTRL_1_OFFSET 0x00 561 562 #define PORT_BROADCAST_STORM 0x0080 563 #define PORT_DIFFSERV_ENABLE 0x0040 564 #define PORT_802_1P_ENABLE 0x0020 565 #define PORT_BASED_PRIORITY_MASK 0x0018 566 #define PORT_BASED_PRIORITY_BASE 0x0003 567 #define PORT_BASED_PRIORITY_SHIFT 3 568 #define PORT_BASED_PRIORITY_0 0x0000 569 #define PORT_BASED_PRIORITY_1 0x0008 570 #define PORT_BASED_PRIORITY_2 0x0010 571 #define PORT_BASED_PRIORITY_3 0x0018 572 #define PORT_INSERT_TAG 0x0004 573 #define PORT_REMOVE_TAG 0x0002 574 #define PORT_PRIO_QUEUE_ENABLE 0x0001 575 576 #define KS8842_PORT_CTRL_2_OFFSET 0x02 577 578 #define PORT_INGRESS_VLAN_FILTER 0x4000 579 #define PORT_DISCARD_NON_VID 0x2000 580 #define PORT_FORCE_FLOW_CTRL 0x1000 581 #define PORT_BACK_PRESSURE 0x0800 582 #define PORT_TX_ENABLE 0x0400 583 #define PORT_RX_ENABLE 0x0200 584 #define PORT_LEARN_DISABLE 0x0100 585 #define PORT_MIRROR_SNIFFER 0x0080 586 #define PORT_MIRROR_RX 0x0040 587 #define PORT_MIRROR_TX 0x0020 588 #define PORT_USER_PRIORITY_CEILING 0x0008 589 #define PORT_VLAN_MEMBERSHIP 0x0007 590 591 #define KS8842_PORT_CTRL_VID_OFFSET 0x04 592 593 #define PORT_DEFAULT_VID 0x0001 594 595 #define KS8842_PORT_CTRL_3_OFFSET 0x06 596 597 #define PORT_INGRESS_LIMIT_MODE 0x000C 598 #define PORT_INGRESS_ALL 0x0000 599 #define PORT_INGRESS_UNICAST 0x0004 600 #define PORT_INGRESS_MULTICAST 0x0008 601 #define PORT_INGRESS_BROADCAST 0x000C 602 #define PORT_COUNT_IFG 0x0002 603 #define PORT_COUNT_PREAMBLE 0x0001 604 605 #define KS8842_PORT_IN_RATE_OFFSET 0x08 606 #define KS8842_PORT_OUT_RATE_OFFSET 0x0A 607 608 #define PORT_PRIORITY_RATE 0x0F 609 #define PORT_PRIORITY_RATE_SHIFT 4 610 611 #define KS884X_PORT_LINK_MD 0x10 612 613 #define PORT_CABLE_10M_SHORT 0x8000 614 #define PORT_CABLE_DIAG_RESULT 0x6000 615 #define PORT_CABLE_STAT_NORMAL 0x0000 616 #define PORT_CABLE_STAT_OPEN 0x2000 617 #define PORT_CABLE_STAT_SHORT 0x4000 618 #define PORT_CABLE_STAT_FAILED 0x6000 619 #define PORT_START_CABLE_DIAG 0x1000 620 #define PORT_FORCE_LINK 0x0800 621 #define PORT_POWER_SAVING_DISABLE 0x0400 622 #define PORT_PHY_REMOTE_LOOPBACK 0x0200 623 #define PORT_CABLE_FAULT_COUNTER 0x01FF 624 625 #define KS884X_PORT_CTRL_4_OFFSET 0x12 626 627 #define PORT_LED_OFF 0x8000 628 #define PORT_TX_DISABLE 0x4000 629 #define PORT_AUTO_NEG_RESTART 0x2000 630 #define PORT_REMOTE_FAULT_DISABLE 0x1000 631 #define PORT_POWER_DOWN 0x0800 632 #define PORT_AUTO_MDIX_DISABLE 0x0400 633 #define PORT_FORCE_MDIX 0x0200 634 #define PORT_LOOPBACK 0x0100 635 #define PORT_AUTO_NEG_ENABLE 0x0080 636 #define PORT_FORCE_100_MBIT 0x0040 637 #define PORT_FORCE_FULL_DUPLEX 0x0020 638 #define PORT_AUTO_NEG_SYM_PAUSE 0x0010 639 #define PORT_AUTO_NEG_100BTX_FD 0x0008 640 #define PORT_AUTO_NEG_100BTX 0x0004 641 #define PORT_AUTO_NEG_10BT_FD 0x0002 642 #define PORT_AUTO_NEG_10BT 0x0001 643 644 #define KS884X_PORT_STATUS_OFFSET 0x14 645 646 #define PORT_HP_MDIX 0x8000 647 #define PORT_REVERSED_POLARITY 0x2000 648 #define PORT_RX_FLOW_CTRL 0x0800 649 #define PORT_TX_FLOW_CTRL 0x1000 650 #define PORT_STATUS_SPEED_100MBIT 0x0400 651 #define PORT_STATUS_FULL_DUPLEX 0x0200 652 #define PORT_REMOTE_FAULT 0x0100 653 #define PORT_MDIX_STATUS 0x0080 654 #define PORT_AUTO_NEG_COMPLETE 0x0040 655 #define PORT_STATUS_LINK_GOOD 0x0020 656 #define PORT_REMOTE_SYM_PAUSE 0x0010 657 #define PORT_REMOTE_100BTX_FD 0x0008 658 #define PORT_REMOTE_100BTX 0x0004 659 #define PORT_REMOTE_10BT_FD 0x0002 660 #define PORT_REMOTE_10BT 0x0001 661 662 /* 663 #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF 664 #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000 665 #define STATIC_MAC_TABLE_VALID 00-00080000-00000000 666 #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000 667 #define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000 668 #define STATIC_MAC_TABLE_FID 00-03C00000-00000000 669 */ 670 671 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF 672 #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000 673 #define STATIC_MAC_TABLE_VALID 0x00080000 674 #define STATIC_MAC_TABLE_OVERRIDE 0x00100000 675 #define STATIC_MAC_TABLE_USE_FID 0x00200000 676 #define STATIC_MAC_TABLE_FID 0x03C00000 677 678 #define STATIC_MAC_FWD_PORTS_SHIFT 16 679 #define STATIC_MAC_FID_SHIFT 22 680 681 /* 682 #define VLAN_TABLE_VID 00-00000000-00000FFF 683 #define VLAN_TABLE_FID 00-00000000-0000F000 684 #define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000 685 #define VLAN_TABLE_VALID 00-00000000-00080000 686 */ 687 688 #define VLAN_TABLE_VID 0x00000FFF 689 #define VLAN_TABLE_FID 0x0000F000 690 #define VLAN_TABLE_MEMBERSHIP 0x00070000 691 #define VLAN_TABLE_VALID 0x00080000 692 693 #define VLAN_TABLE_FID_SHIFT 12 694 #define VLAN_TABLE_MEMBERSHIP_SHIFT 16 695 696 /* 697 #define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF 698 #define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000 699 #define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000 700 #define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000 701 #define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000 702 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000 703 #define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000 704 #define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000 705 */ 706 707 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF 708 #define DYNAMIC_MAC_TABLE_FID 0x000F0000 709 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000 710 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000 711 #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000 712 713 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03 714 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04 715 #define DYNAMIC_MAC_TABLE_RESERVED 0x78 716 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80 717 718 #define DYNAMIC_MAC_FID_SHIFT 16 719 #define DYNAMIC_MAC_SRC_PORT_SHIFT 20 720 #define DYNAMIC_MAC_TIMESTAMP_SHIFT 22 721 #define DYNAMIC_MAC_ENTRIES_SHIFT 24 722 #define DYNAMIC_MAC_ENTRIES_H_SHIFT 8 723 724 /* 725 #define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF 726 #define MIB_COUNTER_VALID 00-00000000-40000000 727 #define MIB_COUNTER_OVERFLOW 00-00000000-80000000 728 */ 729 730 #define MIB_COUNTER_VALUE 0x3FFFFFFF 731 #define MIB_COUNTER_VALID 0x40000000 732 #define MIB_COUNTER_OVERFLOW 0x80000000 733 734 #define MIB_PACKET_DROPPED 0x0000FFFF 735 736 #define KS_MIB_PACKET_DROPPED_TX_0 0x100 737 #define KS_MIB_PACKET_DROPPED_TX_1 0x101 738 #define KS_MIB_PACKET_DROPPED_TX 0x102 739 #define KS_MIB_PACKET_DROPPED_RX_0 0x103 740 #define KS_MIB_PACKET_DROPPED_RX_1 0x104 741 #define KS_MIB_PACKET_DROPPED_RX 0x105 742 743 /* Change default LED mode. */ 744 #define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT 745 746 #define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i)) 747 748 #define MAX_ETHERNET_BODY_SIZE 1500 749 #define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN) 750 751 #define MAX_ETHERNET_PACKET_SIZE \ 752 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE) 753 754 #define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4) 755 #define MAX_RX_BUF_SIZE (1912 + 4) 756 757 #define ADDITIONAL_ENTRIES 16 758 #define MAX_MULTICAST_LIST 32 759 760 #define HW_MULTICAST_SIZE 8 761 762 #define HW_TO_DEV_PORT(port) (port - 1) 763 764 enum { 765 media_connected, 766 media_disconnected 767 }; 768 769 enum { 770 OID_COUNTER_UNKOWN, 771 772 OID_COUNTER_FIRST, 773 774 /* total transmit errors */ 775 OID_COUNTER_XMIT_ERROR, 776 777 /* total receive errors */ 778 OID_COUNTER_RCV_ERROR, 779 780 OID_COUNTER_LAST 781 }; 782 783 /* 784 * Hardware descriptor definitions 785 */ 786 787 #define DESC_ALIGNMENT 16 788 #define BUFFER_ALIGNMENT 8 789 790 #define NUM_OF_RX_DESC 64 791 #define NUM_OF_TX_DESC 64 792 793 #define KS_DESC_RX_FRAME_LEN 0x000007FF 794 #define KS_DESC_RX_FRAME_TYPE 0x00008000 795 #define KS_DESC_RX_ERROR_CRC 0x00010000 796 #define KS_DESC_RX_ERROR_RUNT 0x00020000 797 #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000 798 #define KS_DESC_RX_ERROR_PHY 0x00080000 799 #define KS884X_DESC_RX_PORT_MASK 0x00300000 800 #define KS_DESC_RX_MULTICAST 0x01000000 801 #define KS_DESC_RX_ERROR 0x02000000 802 #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000 803 #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000 804 #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000 805 #define KS_DESC_RX_LAST 0x20000000 806 #define KS_DESC_RX_FIRST 0x40000000 807 #define KS_DESC_RX_ERROR_COND \ 808 (KS_DESC_RX_ERROR_CRC | \ 809 KS_DESC_RX_ERROR_RUNT | \ 810 KS_DESC_RX_ERROR_PHY | \ 811 KS_DESC_RX_ERROR_TOO_LONG) 812 813 #define KS_DESC_HW_OWNED 0x80000000 814 815 #define KS_DESC_BUF_SIZE 0x000007FF 816 #define KS884X_DESC_TX_PORT_MASK 0x00300000 817 #define KS_DESC_END_OF_RING 0x02000000 818 #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000 819 #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000 820 #define KS_DESC_TX_CSUM_GEN_IP 0x10000000 821 #define KS_DESC_TX_LAST 0x20000000 822 #define KS_DESC_TX_FIRST 0x40000000 823 #define KS_DESC_TX_INTERRUPT 0x80000000 824 825 #define KS_DESC_PORT_SHIFT 20 826 827 #define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE) 828 829 #define KS_DESC_TX_MASK \ 830 (KS_DESC_TX_INTERRUPT | \ 831 KS_DESC_TX_FIRST | \ 832 KS_DESC_TX_LAST | \ 833 KS_DESC_TX_CSUM_GEN_IP | \ 834 KS_DESC_TX_CSUM_GEN_TCP | \ 835 KS_DESC_TX_CSUM_GEN_UDP | \ 836 KS_DESC_BUF_SIZE) 837 838 struct ksz_desc_rx_stat { 839 #ifdef __BIG_ENDIAN_BITFIELD 840 u32 hw_owned:1; 841 u32 first_desc:1; 842 u32 last_desc:1; 843 u32 csum_err_ip:1; 844 u32 csum_err_tcp:1; 845 u32 csum_err_udp:1; 846 u32 error:1; 847 u32 multicast:1; 848 u32 src_port:4; 849 u32 err_phy:1; 850 u32 err_too_long:1; 851 u32 err_runt:1; 852 u32 err_crc:1; 853 u32 frame_type:1; 854 u32 reserved1:4; 855 u32 frame_len:11; 856 #else 857 u32 frame_len:11; 858 u32 reserved1:4; 859 u32 frame_type:1; 860 u32 err_crc:1; 861 u32 err_runt:1; 862 u32 err_too_long:1; 863 u32 err_phy:1; 864 u32 src_port:4; 865 u32 multicast:1; 866 u32 error:1; 867 u32 csum_err_udp:1; 868 u32 csum_err_tcp:1; 869 u32 csum_err_ip:1; 870 u32 last_desc:1; 871 u32 first_desc:1; 872 u32 hw_owned:1; 873 #endif 874 }; 875 876 struct ksz_desc_tx_stat { 877 #ifdef __BIG_ENDIAN_BITFIELD 878 u32 hw_owned:1; 879 u32 reserved1:31; 880 #else 881 u32 reserved1:31; 882 u32 hw_owned:1; 883 #endif 884 }; 885 886 struct ksz_desc_rx_buf { 887 #ifdef __BIG_ENDIAN_BITFIELD 888 u32 reserved4:6; 889 u32 end_of_ring:1; 890 u32 reserved3:14; 891 u32 buf_size:11; 892 #else 893 u32 buf_size:11; 894 u32 reserved3:14; 895 u32 end_of_ring:1; 896 u32 reserved4:6; 897 #endif 898 }; 899 900 struct ksz_desc_tx_buf { 901 #ifdef __BIG_ENDIAN_BITFIELD 902 u32 intr:1; 903 u32 first_seg:1; 904 u32 last_seg:1; 905 u32 csum_gen_ip:1; 906 u32 csum_gen_tcp:1; 907 u32 csum_gen_udp:1; 908 u32 end_of_ring:1; 909 u32 reserved4:1; 910 u32 dest_port:4; 911 u32 reserved3:9; 912 u32 buf_size:11; 913 #else 914 u32 buf_size:11; 915 u32 reserved3:9; 916 u32 dest_port:4; 917 u32 reserved4:1; 918 u32 end_of_ring:1; 919 u32 csum_gen_udp:1; 920 u32 csum_gen_tcp:1; 921 u32 csum_gen_ip:1; 922 u32 last_seg:1; 923 u32 first_seg:1; 924 u32 intr:1; 925 #endif 926 }; 927 928 union desc_stat { 929 struct ksz_desc_rx_stat rx; 930 struct ksz_desc_tx_stat tx; 931 u32 data; 932 }; 933 934 union desc_buf { 935 struct ksz_desc_rx_buf rx; 936 struct ksz_desc_tx_buf tx; 937 u32 data; 938 }; 939 940 /** 941 * struct ksz_hw_desc - Hardware descriptor data structure 942 * @ctrl: Descriptor control value. 943 * @buf: Descriptor buffer value. 944 * @addr: Physical address of memory buffer. 945 * @next: Pointer to next hardware descriptor. 946 */ 947 struct ksz_hw_desc { 948 union desc_stat ctrl; 949 union desc_buf buf; 950 u32 addr; 951 u32 next; 952 }; 953 954 /** 955 * struct ksz_sw_desc - Software descriptor data structure 956 * @ctrl: Descriptor control value. 957 * @buf: Descriptor buffer value. 958 * @buf_size: Current buffers size value in hardware descriptor. 959 */ 960 struct ksz_sw_desc { 961 union desc_stat ctrl; 962 union desc_buf buf; 963 u32 buf_size; 964 }; 965 966 /** 967 * struct ksz_dma_buf - OS dependent DMA buffer data structure 968 * @skb: Associated socket buffer. 969 * @dma: Associated physical DMA address. 970 * len: Actual len used. 971 */ 972 struct ksz_dma_buf { 973 struct sk_buff *skb; 974 dma_addr_t dma; 975 int len; 976 }; 977 978 /** 979 * struct ksz_desc - Descriptor structure 980 * @phw: Hardware descriptor pointer to uncached physical memory. 981 * @sw: Cached memory to hold hardware descriptor values for 982 * manipulation. 983 * @dma_buf: Operating system dependent data structure to hold physical 984 * memory buffer allocation information. 985 */ 986 struct ksz_desc { 987 struct ksz_hw_desc *phw; 988 struct ksz_sw_desc sw; 989 struct ksz_dma_buf dma_buf; 990 }; 991 992 #define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf)) 993 994 /** 995 * struct ksz_desc_info - Descriptor information data structure 996 * @ring: First descriptor in the ring. 997 * @cur: Current descriptor being manipulated. 998 * @ring_virt: First hardware descriptor in the ring. 999 * @ring_phys: The physical address of the first descriptor of the ring. 1000 * @size: Size of hardware descriptor. 1001 * @alloc: Number of descriptors allocated. 1002 * @avail: Number of descriptors available for use. 1003 * @last: Index for last descriptor released to hardware. 1004 * @next: Index for next descriptor available for use. 1005 * @mask: Mask for index wrapping. 1006 */ 1007 struct ksz_desc_info { 1008 struct ksz_desc *ring; 1009 struct ksz_desc *cur; 1010 struct ksz_hw_desc *ring_virt; 1011 u32 ring_phys; 1012 int size; 1013 int alloc; 1014 int avail; 1015 int last; 1016 int next; 1017 int mask; 1018 }; 1019 1020 /* 1021 * KSZ8842 switch definitions 1022 */ 1023 1024 enum { 1025 TABLE_STATIC_MAC = 0, 1026 TABLE_VLAN, 1027 TABLE_DYNAMIC_MAC, 1028 TABLE_MIB 1029 }; 1030 1031 #define LEARNED_MAC_TABLE_ENTRIES 1024 1032 #define STATIC_MAC_TABLE_ENTRIES 8 1033 1034 /** 1035 * struct ksz_mac_table - Static MAC table data structure 1036 * @mac_addr: MAC address to filter. 1037 * @vid: VID value. 1038 * @fid: FID value. 1039 * @ports: Port membership. 1040 * @override: Override setting. 1041 * @use_fid: FID use setting. 1042 * @valid: Valid setting indicating the entry is being used. 1043 */ 1044 struct ksz_mac_table { 1045 u8 mac_addr[ETH_ALEN]; 1046 u16 vid; 1047 u8 fid; 1048 u8 ports; 1049 u8 override:1; 1050 u8 use_fid:1; 1051 u8 valid:1; 1052 }; 1053 1054 #define VLAN_TABLE_ENTRIES 16 1055 1056 /** 1057 * struct ksz_vlan_table - VLAN table data structure 1058 * @vid: VID value. 1059 * @fid: FID value. 1060 * @member: Port membership. 1061 */ 1062 struct ksz_vlan_table { 1063 u16 vid; 1064 u8 fid; 1065 u8 member; 1066 }; 1067 1068 #define DIFFSERV_ENTRIES 64 1069 #define PRIO_802_1P_ENTRIES 8 1070 #define PRIO_QUEUES 4 1071 1072 #define SWITCH_PORT_NUM 2 1073 #define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1) 1074 #define HOST_MASK (1 << SWITCH_PORT_NUM) 1075 #define PORT_MASK 7 1076 1077 #define MAIN_PORT 0 1078 #define OTHER_PORT 1 1079 #define HOST_PORT SWITCH_PORT_NUM 1080 1081 #define PORT_COUNTER_NUM 0x20 1082 #define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2) 1083 1084 #define MIB_COUNTER_RX_LO_PRIORITY 0x00 1085 #define MIB_COUNTER_RX_HI_PRIORITY 0x01 1086 #define MIB_COUNTER_RX_UNDERSIZE 0x02 1087 #define MIB_COUNTER_RX_FRAGMENT 0x03 1088 #define MIB_COUNTER_RX_OVERSIZE 0x04 1089 #define MIB_COUNTER_RX_JABBER 0x05 1090 #define MIB_COUNTER_RX_SYMBOL_ERR 0x06 1091 #define MIB_COUNTER_RX_CRC_ERR 0x07 1092 #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08 1093 #define MIB_COUNTER_RX_CTRL_8808 0x09 1094 #define MIB_COUNTER_RX_PAUSE 0x0A 1095 #define MIB_COUNTER_RX_BROADCAST 0x0B 1096 #define MIB_COUNTER_RX_MULTICAST 0x0C 1097 #define MIB_COUNTER_RX_UNICAST 0x0D 1098 #define MIB_COUNTER_RX_OCTET_64 0x0E 1099 #define MIB_COUNTER_RX_OCTET_65_127 0x0F 1100 #define MIB_COUNTER_RX_OCTET_128_255 0x10 1101 #define MIB_COUNTER_RX_OCTET_256_511 0x11 1102 #define MIB_COUNTER_RX_OCTET_512_1023 0x12 1103 #define MIB_COUNTER_RX_OCTET_1024_1522 0x13 1104 #define MIB_COUNTER_TX_LO_PRIORITY 0x14 1105 #define MIB_COUNTER_TX_HI_PRIORITY 0x15 1106 #define MIB_COUNTER_TX_LATE_COLLISION 0x16 1107 #define MIB_COUNTER_TX_PAUSE 0x17 1108 #define MIB_COUNTER_TX_BROADCAST 0x18 1109 #define MIB_COUNTER_TX_MULTICAST 0x19 1110 #define MIB_COUNTER_TX_UNICAST 0x1A 1111 #define MIB_COUNTER_TX_DEFERRED 0x1B 1112 #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C 1113 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D 1114 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E 1115 #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F 1116 1117 #define MIB_COUNTER_RX_DROPPED_PACKET 0x20 1118 #define MIB_COUNTER_TX_DROPPED_PACKET 0x21 1119 1120 /** 1121 * struct ksz_port_mib - Port MIB data structure 1122 * @cnt_ptr: Current pointer to MIB counter index. 1123 * @link_down: Indication the link has just gone down. 1124 * @state: Connection status of the port. 1125 * @mib_start: The starting counter index. Some ports do not start at 0. 1126 * @counter: 64-bit MIB counter value. 1127 * @dropped: Temporary buffer to remember last read packet dropped values. 1128 * 1129 * MIB counters needs to be read periodically so that counters do not get 1130 * overflowed and give incorrect values. A right balance is needed to 1131 * satisfy this condition and not waste too much CPU time. 1132 * 1133 * It is pointless to read MIB counters when the port is disconnected. The 1134 * @state provides the connection status so that MIB counters are read only 1135 * when the port is connected. The @link_down indicates the port is just 1136 * disconnected so that all MIB counters are read one last time to update the 1137 * information. 1138 */ 1139 struct ksz_port_mib { 1140 u8 cnt_ptr; 1141 u8 link_down; 1142 u8 state; 1143 u8 mib_start; 1144 1145 u64 counter[TOTAL_PORT_COUNTER_NUM]; 1146 u32 dropped[2]; 1147 }; 1148 1149 /** 1150 * struct ksz_port_cfg - Port configuration data structure 1151 * @vid: VID value. 1152 * @member: Port membership. 1153 * @port_prio: Port priority. 1154 * @rx_rate: Receive priority rate. 1155 * @tx_rate: Transmit priority rate. 1156 * @stp_state: Current Spanning Tree Protocol state. 1157 */ 1158 struct ksz_port_cfg { 1159 u16 vid; 1160 u8 member; 1161 u8 port_prio; 1162 u32 rx_rate[PRIO_QUEUES]; 1163 u32 tx_rate[PRIO_QUEUES]; 1164 int stp_state; 1165 }; 1166 1167 /** 1168 * struct ksz_switch - KSZ8842 switch data structure 1169 * @mac_table: MAC table entries information. 1170 * @vlan_table: VLAN table entries information. 1171 * @port_cfg: Port configuration information. 1172 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS 1173 * (bit7 ~ bit2) field. 1174 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p 1175 * Tag priority field. 1176 * @br_addr: Bridge address. Used for STP. 1177 * @other_addr: Other MAC address. Used for multiple network device mode. 1178 * @broad_per: Broadcast storm percentage. 1179 * @member: Current port membership. Used for STP. 1180 */ 1181 struct ksz_switch { 1182 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES]; 1183 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES]; 1184 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM]; 1185 1186 u8 diffserv[DIFFSERV_ENTRIES]; 1187 u8 p_802_1p[PRIO_802_1P_ENTRIES]; 1188 1189 u8 br_addr[ETH_ALEN]; 1190 u8 other_addr[ETH_ALEN]; 1191 1192 u8 broad_per; 1193 u8 member; 1194 }; 1195 1196 #define TX_RATE_UNIT 10000 1197 1198 /** 1199 * struct ksz_port_info - Port information data structure 1200 * @state: Connection status of the port. 1201 * @tx_rate: Transmit rate divided by 10000 to get Mbit. 1202 * @duplex: Duplex mode. 1203 * @advertised: Advertised auto-negotiation setting. Used to determine link. 1204 * @partner: Auto-negotiation partner setting. Used to determine link. 1205 * @port_id: Port index to access actual hardware register. 1206 * @pdev: Pointer to OS dependent network device. 1207 */ 1208 struct ksz_port_info { 1209 uint state; 1210 uint tx_rate; 1211 u8 duplex; 1212 u8 advertised; 1213 u8 partner; 1214 u8 port_id; 1215 void *pdev; 1216 }; 1217 1218 #define MAX_TX_HELD_SIZE 52000 1219 1220 /* Hardware features and bug fixes. */ 1221 #define LINK_INT_WORKING (1 << 0) 1222 #define SMALL_PACKET_TX_BUG (1 << 1) 1223 #define HALF_DUPLEX_SIGNAL_BUG (1 << 2) 1224 #define RX_HUGE_FRAME (1 << 4) 1225 #define STP_SUPPORT (1 << 8) 1226 1227 /* Software overrides. */ 1228 #define PAUSE_FLOW_CTRL (1 << 0) 1229 #define FAST_AGING (1 << 1) 1230 1231 /** 1232 * struct ksz_hw - KSZ884X hardware data structure 1233 * @io: Virtual address assigned. 1234 * @ksz_switch: Pointer to KSZ8842 switch. 1235 * @port_info: Port information. 1236 * @port_mib: Port MIB information. 1237 * @dev_count: Number of network devices this hardware supports. 1238 * @dst_ports: Destination ports in switch for transmission. 1239 * @id: Hardware ID. Used for display only. 1240 * @mib_cnt: Number of MIB counters this hardware has. 1241 * @mib_port_cnt: Number of ports with MIB counters. 1242 * @tx_cfg: Cached transmit control settings. 1243 * @rx_cfg: Cached receive control settings. 1244 * @intr_mask: Current interrupt mask. 1245 * @intr_set: Current interrup set. 1246 * @intr_blocked: Interrupt blocked. 1247 * @rx_desc_info: Receive descriptor information. 1248 * @tx_desc_info: Transmit descriptor information. 1249 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization. 1250 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization. 1251 * @tx_size: Transmit data size. Used for TX optimization. 1252 * The maximum is defined by MAX_TX_HELD_SIZE. 1253 * @perm_addr: Permanent MAC address. 1254 * @override_addr: Overrided MAC address. 1255 * @address: Additional MAC address entries. 1256 * @addr_list_size: Additional MAC address list size. 1257 * @mac_override: Indication of MAC address overrided. 1258 * @promiscuous: Counter to keep track of promiscuous mode set. 1259 * @all_multi: Counter to keep track of all multicast mode set. 1260 * @multi_list: Multicast address entries. 1261 * @multi_bits: Cached multicast hash table settings. 1262 * @multi_list_size: Multicast address list size. 1263 * @enabled: Indication of hardware enabled. 1264 * @rx_stop: Indication of receive process stop. 1265 * @features: Hardware features to enable. 1266 * @overrides: Hardware features to override. 1267 * @parent: Pointer to parent, network device private structure. 1268 */ 1269 struct ksz_hw { 1270 void __iomem *io; 1271 1272 struct ksz_switch *ksz_switch; 1273 struct ksz_port_info port_info[SWITCH_PORT_NUM]; 1274 struct ksz_port_mib port_mib[TOTAL_PORT_NUM]; 1275 int dev_count; 1276 int dst_ports; 1277 int id; 1278 int mib_cnt; 1279 int mib_port_cnt; 1280 1281 u32 tx_cfg; 1282 u32 rx_cfg; 1283 u32 intr_mask; 1284 u32 intr_set; 1285 uint intr_blocked; 1286 1287 struct ksz_desc_info rx_desc_info; 1288 struct ksz_desc_info tx_desc_info; 1289 1290 int tx_int_cnt; 1291 int tx_int_mask; 1292 int tx_size; 1293 1294 u8 perm_addr[ETH_ALEN]; 1295 u8 override_addr[ETH_ALEN]; 1296 u8 address[ADDITIONAL_ENTRIES][ETH_ALEN]; 1297 u8 addr_list_size; 1298 u8 mac_override; 1299 u8 promiscuous; 1300 u8 all_multi; 1301 u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN]; 1302 u8 multi_bits[HW_MULTICAST_SIZE]; 1303 u8 multi_list_size; 1304 1305 u8 enabled; 1306 u8 rx_stop; 1307 u8 reserved2[1]; 1308 1309 uint features; 1310 uint overrides; 1311 1312 void *parent; 1313 }; 1314 1315 enum { 1316 PHY_NO_FLOW_CTRL, 1317 PHY_FLOW_CTRL, 1318 PHY_TX_ONLY, 1319 PHY_RX_ONLY 1320 }; 1321 1322 /** 1323 * struct ksz_port - Virtual port data structure 1324 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full 1325 * duplex, and 0 for auto, which normally results in full 1326 * duplex. 1327 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and 1328 * 0 for auto, which normally results in 100 Mbit. 1329 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for 1330 * force. 1331 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow 1332 * control, and PHY_FLOW_CTRL for flow control. 1333 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100 1334 * Mbit PHY. 1335 * @first_port: Index of first port this port supports. 1336 * @mib_port_cnt: Number of ports with MIB counters. 1337 * @port_cnt: Number of ports this port supports. 1338 * @counter: Port statistics counter. 1339 * @hw: Pointer to hardware structure. 1340 * @linked: Pointer to port information linked to this port. 1341 */ 1342 struct ksz_port { 1343 u8 duplex; 1344 u8 speed; 1345 u8 force_link; 1346 u8 flow_ctrl; 1347 1348 int first_port; 1349 int mib_port_cnt; 1350 int port_cnt; 1351 u64 counter[OID_COUNTER_LAST]; 1352 1353 struct ksz_hw *hw; 1354 struct ksz_port_info *linked; 1355 }; 1356 1357 /** 1358 * struct ksz_timer_info - Timer information data structure 1359 * @timer: Kernel timer. 1360 * @cnt: Running timer counter. 1361 * @max: Number of times to run timer; -1 for infinity. 1362 * @period: Timer period in jiffies. 1363 */ 1364 struct ksz_timer_info { 1365 struct timer_list timer; 1366 int cnt; 1367 int max; 1368 int period; 1369 }; 1370 1371 /** 1372 * struct ksz_shared_mem - OS dependent shared memory data structure 1373 * @dma_addr: Physical DMA address allocated. 1374 * @alloc_size: Allocation size. 1375 * @phys: Actual physical address used. 1376 * @alloc_virt: Virtual address allocated. 1377 * @virt: Actual virtual address used. 1378 */ 1379 struct ksz_shared_mem { 1380 dma_addr_t dma_addr; 1381 uint alloc_size; 1382 uint phys; 1383 u8 *alloc_virt; 1384 u8 *virt; 1385 }; 1386 1387 /** 1388 * struct ksz_counter_info - OS dependent counter information data structure 1389 * @counter: Wait queue to wakeup after counters are read. 1390 * @time: Next time in jiffies to read counter. 1391 * @read: Indication of counters read in full or not. 1392 */ 1393 struct ksz_counter_info { 1394 wait_queue_head_t counter; 1395 unsigned long time; 1396 int read; 1397 }; 1398 1399 /** 1400 * struct dev_info - Network device information data structure 1401 * @dev: Pointer to network device. 1402 * @pdev: Pointer to PCI device. 1403 * @hw: Hardware structure. 1404 * @desc_pool: Physical memory used for descriptor pool. 1405 * @hwlock: Spinlock to prevent hardware from accessing. 1406 * @lock: Mutex lock to prevent device from accessing. 1407 * @dev_rcv: Receive process function used. 1408 * @last_skb: Socket buffer allocated for descriptor rx fragments. 1409 * @skb_index: Buffer index for receiving fragments. 1410 * @skb_len: Buffer length for receiving fragments. 1411 * @mib_read: Workqueue to read MIB counters. 1412 * @mib_timer_info: Timer to read MIB counters. 1413 * @counter: Used for MIB reading. 1414 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE; 1415 * the maximum is MAX_RX_BUF_SIZE. 1416 * @opened: Counter to keep track of device open. 1417 * @rx_tasklet: Receive processing tasklet. 1418 * @tx_tasklet: Transmit processing tasklet. 1419 * @wol_enable: Wake-on-LAN enable set by ethtool. 1420 * @wol_support: Wake-on-LAN support used by ethtool. 1421 * @pme_wait: Used for KSZ8841 power management. 1422 */ 1423 struct dev_info { 1424 struct net_device *dev; 1425 struct pci_dev *pdev; 1426 1427 struct ksz_hw hw; 1428 struct ksz_shared_mem desc_pool; 1429 1430 spinlock_t hwlock; 1431 struct mutex lock; 1432 1433 int (*dev_rcv)(struct dev_info *); 1434 1435 struct sk_buff *last_skb; 1436 int skb_index; 1437 int skb_len; 1438 1439 struct work_struct mib_read; 1440 struct ksz_timer_info mib_timer_info; 1441 struct ksz_counter_info counter[TOTAL_PORT_NUM]; 1442 1443 int mtu; 1444 int opened; 1445 1446 struct tasklet_struct rx_tasklet; 1447 struct tasklet_struct tx_tasklet; 1448 1449 int wol_enable; 1450 int wol_support; 1451 unsigned long pme_wait; 1452 }; 1453 1454 /** 1455 * struct dev_priv - Network device private data structure 1456 * @adapter: Adapter device information. 1457 * @port: Port information. 1458 * @monitor_time_info: Timer to monitor ports. 1459 * @proc_sem: Semaphore for proc accessing. 1460 * @id: Device ID. 1461 * @mii_if: MII interface information. 1462 * @advertising: Temporary variable to store advertised settings. 1463 * @msg_enable: The message flags controlling driver output. 1464 * @media_state: The connection status of the device. 1465 * @multicast: The all multicast state of the device. 1466 * @promiscuous: The promiscuous state of the device. 1467 */ 1468 struct dev_priv { 1469 struct dev_info *adapter; 1470 struct ksz_port port; 1471 struct ksz_timer_info monitor_timer_info; 1472 1473 struct semaphore proc_sem; 1474 int id; 1475 1476 struct mii_if_info mii_if; 1477 u32 advertising; 1478 1479 u32 msg_enable; 1480 int media_state; 1481 int multicast; 1482 int promiscuous; 1483 }; 1484 1485 #define DRV_NAME "KSZ884X PCI" 1486 #define DEVICE_NAME "KSZ884x PCI" 1487 #define DRV_VERSION "1.0.0" 1488 #define DRV_RELDATE "Feb 8, 2010" 1489 1490 static char version[] = 1491 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")"; 1492 1493 static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 }; 1494 1495 /* 1496 * Interrupt processing primary routines 1497 */ 1498 1499 static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt) 1500 { 1501 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS); 1502 } 1503 1504 static inline void hw_dis_intr(struct ksz_hw *hw) 1505 { 1506 hw->intr_blocked = hw->intr_mask; 1507 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE); 1508 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE); 1509 } 1510 1511 static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt) 1512 { 1513 hw->intr_set = interrupt; 1514 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE); 1515 } 1516 1517 static inline void hw_ena_intr(struct ksz_hw *hw) 1518 { 1519 hw->intr_blocked = 0; 1520 hw_set_intr(hw, hw->intr_mask); 1521 } 1522 1523 static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit) 1524 { 1525 hw->intr_mask &= ~(bit); 1526 } 1527 1528 static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt) 1529 { 1530 u32 read_intr; 1531 1532 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); 1533 hw->intr_set = read_intr & ~interrupt; 1534 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); 1535 hw_dis_intr_bit(hw, interrupt); 1536 } 1537 1538 /** 1539 * hw_turn_on_intr - turn on specified interrupts 1540 * @hw: The hardware instance. 1541 * @bit: The interrupt bits to be on. 1542 * 1543 * This routine turns on the specified interrupts in the interrupt mask so that 1544 * those interrupts will be enabled. 1545 */ 1546 static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit) 1547 { 1548 hw->intr_mask |= bit; 1549 1550 if (!hw->intr_blocked) 1551 hw_set_intr(hw, hw->intr_mask); 1552 } 1553 1554 static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt) 1555 { 1556 u32 read_intr; 1557 1558 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); 1559 hw->intr_set = read_intr | interrupt; 1560 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); 1561 } 1562 1563 static inline void hw_read_intr(struct ksz_hw *hw, uint *status) 1564 { 1565 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS); 1566 *status = *status & hw->intr_set; 1567 } 1568 1569 static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt) 1570 { 1571 if (interrupt) 1572 hw_ena_intr(hw); 1573 } 1574 1575 /** 1576 * hw_block_intr - block hardware interrupts 1577 * 1578 * This function blocks all interrupts of the hardware and returns the current 1579 * interrupt enable mask so that interrupts can be restored later. 1580 * 1581 * Return the current interrupt enable mask. 1582 */ 1583 static uint hw_block_intr(struct ksz_hw *hw) 1584 { 1585 uint interrupt = 0; 1586 1587 if (!hw->intr_blocked) { 1588 hw_dis_intr(hw); 1589 interrupt = hw->intr_blocked; 1590 } 1591 return interrupt; 1592 } 1593 1594 /* 1595 * Hardware descriptor routines 1596 */ 1597 1598 static inline void reset_desc(struct ksz_desc *desc, union desc_stat status) 1599 { 1600 status.rx.hw_owned = 0; 1601 desc->phw->ctrl.data = cpu_to_le32(status.data); 1602 } 1603 1604 static inline void release_desc(struct ksz_desc *desc) 1605 { 1606 desc->sw.ctrl.tx.hw_owned = 1; 1607 if (desc->sw.buf_size != desc->sw.buf.data) { 1608 desc->sw.buf_size = desc->sw.buf.data; 1609 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data); 1610 } 1611 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data); 1612 } 1613 1614 static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc) 1615 { 1616 *desc = &info->ring[info->last]; 1617 info->last++; 1618 info->last &= info->mask; 1619 info->avail--; 1620 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK; 1621 } 1622 1623 static inline void set_rx_buf(struct ksz_desc *desc, u32 addr) 1624 { 1625 desc->phw->addr = cpu_to_le32(addr); 1626 } 1627 1628 static inline void set_rx_len(struct ksz_desc *desc, u32 len) 1629 { 1630 desc->sw.buf.rx.buf_size = len; 1631 } 1632 1633 static inline void get_tx_pkt(struct ksz_desc_info *info, 1634 struct ksz_desc **desc) 1635 { 1636 *desc = &info->ring[info->next]; 1637 info->next++; 1638 info->next &= info->mask; 1639 info->avail--; 1640 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK; 1641 } 1642 1643 static inline void set_tx_buf(struct ksz_desc *desc, u32 addr) 1644 { 1645 desc->phw->addr = cpu_to_le32(addr); 1646 } 1647 1648 static inline void set_tx_len(struct ksz_desc *desc, u32 len) 1649 { 1650 desc->sw.buf.tx.buf_size = len; 1651 } 1652 1653 /* Switch functions */ 1654 1655 #define TABLE_READ 0x10 1656 #define TABLE_SEL_SHIFT 2 1657 1658 #define HW_DELAY(hw, reg) \ 1659 do { \ 1660 u16 dummy; \ 1661 dummy = readw(hw->io + reg); \ 1662 } while (0) 1663 1664 /** 1665 * sw_r_table - read 4 bytes of data from switch table 1666 * @hw: The hardware instance. 1667 * @table: The table selector. 1668 * @addr: The address of the table entry. 1669 * @data: Buffer to store the read data. 1670 * 1671 * This routine reads 4 bytes of data from the table of the switch. 1672 * Hardware interrupts are disabled to minimize corruption of read data. 1673 */ 1674 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data) 1675 { 1676 u16 ctrl_addr; 1677 uint interrupt; 1678 1679 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr; 1680 1681 interrupt = hw_block_intr(hw); 1682 1683 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); 1684 HW_DELAY(hw, KS884X_IACR_OFFSET); 1685 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); 1686 1687 hw_restore_intr(hw, interrupt); 1688 } 1689 1690 /** 1691 * sw_w_table_64 - write 8 bytes of data to the switch table 1692 * @hw: The hardware instance. 1693 * @table: The table selector. 1694 * @addr: The address of the table entry. 1695 * @data_hi: The high part of data to be written (bit63 ~ bit32). 1696 * @data_lo: The low part of data to be written (bit31 ~ bit0). 1697 * 1698 * This routine writes 8 bytes of data to the table of the switch. 1699 * Hardware interrupts are disabled to minimize corruption of written data. 1700 */ 1701 static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi, 1702 u32 data_lo) 1703 { 1704 u16 ctrl_addr; 1705 uint interrupt; 1706 1707 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr; 1708 1709 interrupt = hw_block_intr(hw); 1710 1711 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET); 1712 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET); 1713 1714 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); 1715 HW_DELAY(hw, KS884X_IACR_OFFSET); 1716 1717 hw_restore_intr(hw, interrupt); 1718 } 1719 1720 /** 1721 * sw_w_sta_mac_table - write to the static MAC table 1722 * @hw: The hardware instance. 1723 * @addr: The address of the table entry. 1724 * @mac_addr: The MAC address. 1725 * @ports: The port members. 1726 * @override: The flag to override the port receive/transmit settings. 1727 * @valid: The flag to indicate entry is valid. 1728 * @use_fid: The flag to indicate the FID is valid. 1729 * @fid: The FID value. 1730 * 1731 * This routine writes an entry of the static MAC table of the switch. It 1732 * calls sw_w_table_64() to write the data. 1733 */ 1734 static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr, 1735 u8 ports, int override, int valid, int use_fid, u8 fid) 1736 { 1737 u32 data_hi; 1738 u32 data_lo; 1739 1740 data_lo = ((u32) mac_addr[2] << 24) | 1741 ((u32) mac_addr[3] << 16) | 1742 ((u32) mac_addr[4] << 8) | mac_addr[5]; 1743 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1]; 1744 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT; 1745 1746 if (override) 1747 data_hi |= STATIC_MAC_TABLE_OVERRIDE; 1748 if (use_fid) { 1749 data_hi |= STATIC_MAC_TABLE_USE_FID; 1750 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT; 1751 } 1752 if (valid) 1753 data_hi |= STATIC_MAC_TABLE_VALID; 1754 1755 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo); 1756 } 1757 1758 /** 1759 * sw_r_vlan_table - read from the VLAN table 1760 * @hw: The hardware instance. 1761 * @addr: The address of the table entry. 1762 * @vid: Buffer to store the VID. 1763 * @fid: Buffer to store the VID. 1764 * @member: Buffer to store the port membership. 1765 * 1766 * This function reads an entry of the VLAN table of the switch. It calls 1767 * sw_r_table() to get the data. 1768 * 1769 * Return 0 if the entry is valid; otherwise -1. 1770 */ 1771 static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid, 1772 u8 *member) 1773 { 1774 u32 data; 1775 1776 sw_r_table(hw, TABLE_VLAN, addr, &data); 1777 if (data & VLAN_TABLE_VALID) { 1778 *vid = (u16)(data & VLAN_TABLE_VID); 1779 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT); 1780 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >> 1781 VLAN_TABLE_MEMBERSHIP_SHIFT); 1782 return 0; 1783 } 1784 return -1; 1785 } 1786 1787 /** 1788 * port_r_mib_cnt - read MIB counter 1789 * @hw: The hardware instance. 1790 * @port: The port index. 1791 * @addr: The address of the counter. 1792 * @cnt: Buffer to store the counter. 1793 * 1794 * This routine reads a MIB counter of the port. 1795 * Hardware interrupts are disabled to minimize corruption of read data. 1796 */ 1797 static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt) 1798 { 1799 u32 data; 1800 u16 ctrl_addr; 1801 uint interrupt; 1802 int timeout; 1803 1804 ctrl_addr = addr + PORT_COUNTER_NUM * port; 1805 1806 interrupt = hw_block_intr(hw); 1807 1808 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8); 1809 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); 1810 HW_DELAY(hw, KS884X_IACR_OFFSET); 1811 1812 for (timeout = 100; timeout > 0; timeout--) { 1813 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); 1814 1815 if (data & MIB_COUNTER_VALID) { 1816 if (data & MIB_COUNTER_OVERFLOW) 1817 *cnt += MIB_COUNTER_VALUE + 1; 1818 *cnt += data & MIB_COUNTER_VALUE; 1819 break; 1820 } 1821 } 1822 1823 hw_restore_intr(hw, interrupt); 1824 } 1825 1826 /** 1827 * port_r_mib_pkt - read dropped packet counts 1828 * @hw: The hardware instance. 1829 * @port: The port index. 1830 * @cnt: Buffer to store the receive and transmit dropped packet counts. 1831 * 1832 * This routine reads the dropped packet counts of the port. 1833 * Hardware interrupts are disabled to minimize corruption of read data. 1834 */ 1835 static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt) 1836 { 1837 u32 cur; 1838 u32 data; 1839 u16 ctrl_addr; 1840 uint interrupt; 1841 int index; 1842 1843 index = KS_MIB_PACKET_DROPPED_RX_0 + port; 1844 do { 1845 interrupt = hw_block_intr(hw); 1846 1847 ctrl_addr = (u16) index; 1848 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) 1849 << 8); 1850 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); 1851 HW_DELAY(hw, KS884X_IACR_OFFSET); 1852 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); 1853 1854 hw_restore_intr(hw, interrupt); 1855 1856 data &= MIB_PACKET_DROPPED; 1857 cur = *last; 1858 if (data != cur) { 1859 *last = data; 1860 if (data < cur) 1861 data += MIB_PACKET_DROPPED + 1; 1862 data -= cur; 1863 *cnt += data; 1864 } 1865 ++last; 1866 ++cnt; 1867 index -= KS_MIB_PACKET_DROPPED_TX - 1868 KS_MIB_PACKET_DROPPED_TX_0 + 1; 1869 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port); 1870 } 1871 1872 /** 1873 * port_r_cnt - read MIB counters periodically 1874 * @hw: The hardware instance. 1875 * @port: The port index. 1876 * 1877 * This routine is used to read the counters of the port periodically to avoid 1878 * counter overflow. The hardware should be acquired first before calling this 1879 * routine. 1880 * 1881 * Return non-zero when not all counters not read. 1882 */ 1883 static int port_r_cnt(struct ksz_hw *hw, int port) 1884 { 1885 struct ksz_port_mib *mib = &hw->port_mib[port]; 1886 1887 if (mib->mib_start < PORT_COUNTER_NUM) 1888 while (mib->cnt_ptr < PORT_COUNTER_NUM) { 1889 port_r_mib_cnt(hw, port, mib->cnt_ptr, 1890 &mib->counter[mib->cnt_ptr]); 1891 ++mib->cnt_ptr; 1892 } 1893 if (hw->mib_cnt > PORT_COUNTER_NUM) 1894 port_r_mib_pkt(hw, port, mib->dropped, 1895 &mib->counter[PORT_COUNTER_NUM]); 1896 mib->cnt_ptr = 0; 1897 return 0; 1898 } 1899 1900 /** 1901 * port_init_cnt - initialize MIB counter values 1902 * @hw: The hardware instance. 1903 * @port: The port index. 1904 * 1905 * This routine is used to initialize all counters to zero if the hardware 1906 * cannot do it after reset. 1907 */ 1908 static void port_init_cnt(struct ksz_hw *hw, int port) 1909 { 1910 struct ksz_port_mib *mib = &hw->port_mib[port]; 1911 1912 mib->cnt_ptr = 0; 1913 if (mib->mib_start < PORT_COUNTER_NUM) 1914 do { 1915 port_r_mib_cnt(hw, port, mib->cnt_ptr, 1916 &mib->counter[mib->cnt_ptr]); 1917 ++mib->cnt_ptr; 1918 } while (mib->cnt_ptr < PORT_COUNTER_NUM); 1919 if (hw->mib_cnt > PORT_COUNTER_NUM) 1920 port_r_mib_pkt(hw, port, mib->dropped, 1921 &mib->counter[PORT_COUNTER_NUM]); 1922 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); 1923 mib->cnt_ptr = 0; 1924 } 1925 1926 /* 1927 * Port functions 1928 */ 1929 1930 /** 1931 * port_chk - check port register bits 1932 * @hw: The hardware instance. 1933 * @port: The port index. 1934 * @offset: The offset of the port register. 1935 * @bits: The data bits to check. 1936 * 1937 * This function checks whether the specified bits of the port register are set 1938 * or not. 1939 * 1940 * Return 0 if the bits are not set. 1941 */ 1942 static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits) 1943 { 1944 u32 addr; 1945 u16 data; 1946 1947 PORT_CTRL_ADDR(port, addr); 1948 addr += offset; 1949 data = readw(hw->io + addr); 1950 return (data & bits) == bits; 1951 } 1952 1953 /** 1954 * port_cfg - set port register bits 1955 * @hw: The hardware instance. 1956 * @port: The port index. 1957 * @offset: The offset of the port register. 1958 * @bits: The data bits to set. 1959 * @set: The flag indicating whether the bits are to be set or not. 1960 * 1961 * This routine sets or resets the specified bits of the port register. 1962 */ 1963 static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits, 1964 int set) 1965 { 1966 u32 addr; 1967 u16 data; 1968 1969 PORT_CTRL_ADDR(port, addr); 1970 addr += offset; 1971 data = readw(hw->io + addr); 1972 if (set) 1973 data |= bits; 1974 else 1975 data &= ~bits; 1976 writew(data, hw->io + addr); 1977 } 1978 1979 /** 1980 * port_chk_shift - check port bit 1981 * @hw: The hardware instance. 1982 * @port: The port index. 1983 * @offset: The offset of the register. 1984 * @shift: Number of bits to shift. 1985 * 1986 * This function checks whether the specified port is set in the register or 1987 * not. 1988 * 1989 * Return 0 if the port is not set. 1990 */ 1991 static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift) 1992 { 1993 u16 data; 1994 u16 bit = 1 << port; 1995 1996 data = readw(hw->io + addr); 1997 data >>= shift; 1998 return (data & bit) == bit; 1999 } 2000 2001 /** 2002 * port_cfg_shift - set port bit 2003 * @hw: The hardware instance. 2004 * @port: The port index. 2005 * @offset: The offset of the register. 2006 * @shift: Number of bits to shift. 2007 * @set: The flag indicating whether the port is to be set or not. 2008 * 2009 * This routine sets or resets the specified port in the register. 2010 */ 2011 static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift, 2012 int set) 2013 { 2014 u16 data; 2015 u16 bits = 1 << port; 2016 2017 data = readw(hw->io + addr); 2018 bits <<= shift; 2019 if (set) 2020 data |= bits; 2021 else 2022 data &= ~bits; 2023 writew(data, hw->io + addr); 2024 } 2025 2026 /** 2027 * port_r8 - read byte from port register 2028 * @hw: The hardware instance. 2029 * @port: The port index. 2030 * @offset: The offset of the port register. 2031 * @data: Buffer to store the data. 2032 * 2033 * This routine reads a byte from the port register. 2034 */ 2035 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data) 2036 { 2037 u32 addr; 2038 2039 PORT_CTRL_ADDR(port, addr); 2040 addr += offset; 2041 *data = readb(hw->io + addr); 2042 } 2043 2044 /** 2045 * port_r16 - read word from port register. 2046 * @hw: The hardware instance. 2047 * @port: The port index. 2048 * @offset: The offset of the port register. 2049 * @data: Buffer to store the data. 2050 * 2051 * This routine reads a word from the port register. 2052 */ 2053 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data) 2054 { 2055 u32 addr; 2056 2057 PORT_CTRL_ADDR(port, addr); 2058 addr += offset; 2059 *data = readw(hw->io + addr); 2060 } 2061 2062 /** 2063 * port_w16 - write word to port register. 2064 * @hw: The hardware instance. 2065 * @port: The port index. 2066 * @offset: The offset of the port register. 2067 * @data: Data to write. 2068 * 2069 * This routine writes a word to the port register. 2070 */ 2071 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data) 2072 { 2073 u32 addr; 2074 2075 PORT_CTRL_ADDR(port, addr); 2076 addr += offset; 2077 writew(data, hw->io + addr); 2078 } 2079 2080 /** 2081 * sw_chk - check switch register bits 2082 * @hw: The hardware instance. 2083 * @addr: The address of the switch register. 2084 * @bits: The data bits to check. 2085 * 2086 * This function checks whether the specified bits of the switch register are 2087 * set or not. 2088 * 2089 * Return 0 if the bits are not set. 2090 */ 2091 static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits) 2092 { 2093 u16 data; 2094 2095 data = readw(hw->io + addr); 2096 return (data & bits) == bits; 2097 } 2098 2099 /** 2100 * sw_cfg - set switch register bits 2101 * @hw: The hardware instance. 2102 * @addr: The address of the switch register. 2103 * @bits: The data bits to set. 2104 * @set: The flag indicating whether the bits are to be set or not. 2105 * 2106 * This function sets or resets the specified bits of the switch register. 2107 */ 2108 static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set) 2109 { 2110 u16 data; 2111 2112 data = readw(hw->io + addr); 2113 if (set) 2114 data |= bits; 2115 else 2116 data &= ~bits; 2117 writew(data, hw->io + addr); 2118 } 2119 2120 /* Bandwidth */ 2121 2122 static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set) 2123 { 2124 port_cfg(hw, p, 2125 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set); 2126 } 2127 2128 static inline int port_chk_broad_storm(struct ksz_hw *hw, int p) 2129 { 2130 return port_chk(hw, p, 2131 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM); 2132 } 2133 2134 /* Driver set switch broadcast storm protection at 10% rate. */ 2135 #define BROADCAST_STORM_PROTECTION_RATE 10 2136 2137 /* 148,800 frames * 67 ms / 100 */ 2138 #define BROADCAST_STORM_VALUE 9969 2139 2140 /** 2141 * sw_cfg_broad_storm - configure broadcast storm threshold 2142 * @hw: The hardware instance. 2143 * @percent: Broadcast storm threshold in percent of transmit rate. 2144 * 2145 * This routine configures the broadcast storm threshold of the switch. 2146 */ 2147 static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) 2148 { 2149 u16 data; 2150 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100); 2151 2152 if (value > BROADCAST_STORM_RATE) 2153 value = BROADCAST_STORM_RATE; 2154 2155 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); 2156 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI); 2157 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8); 2158 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); 2159 } 2160 2161 /** 2162 * sw_get_board_storm - get broadcast storm threshold 2163 * @hw: The hardware instance. 2164 * @percent: Buffer to store the broadcast storm threshold percentage. 2165 * 2166 * This routine retrieves the broadcast storm threshold of the switch. 2167 */ 2168 static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent) 2169 { 2170 int num; 2171 u16 data; 2172 2173 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); 2174 num = (data & BROADCAST_STORM_RATE_HI); 2175 num <<= 8; 2176 num |= (data & BROADCAST_STORM_RATE_LO) >> 8; 2177 num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE; 2178 *percent = (u8) num; 2179 } 2180 2181 /** 2182 * sw_dis_broad_storm - disable broadstorm 2183 * @hw: The hardware instance. 2184 * @port: The port index. 2185 * 2186 * This routine disables the broadcast storm limit function of the switch. 2187 */ 2188 static void sw_dis_broad_storm(struct ksz_hw *hw, int port) 2189 { 2190 port_cfg_broad_storm(hw, port, 0); 2191 } 2192 2193 /** 2194 * sw_ena_broad_storm - enable broadcast storm 2195 * @hw: The hardware instance. 2196 * @port: The port index. 2197 * 2198 * This routine enables the broadcast storm limit function of the switch. 2199 */ 2200 static void sw_ena_broad_storm(struct ksz_hw *hw, int port) 2201 { 2202 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); 2203 port_cfg_broad_storm(hw, port, 1); 2204 } 2205 2206 /** 2207 * sw_init_broad_storm - initialize broadcast storm 2208 * @hw: The hardware instance. 2209 * 2210 * This routine initializes the broadcast storm limit function of the switch. 2211 */ 2212 static void sw_init_broad_storm(struct ksz_hw *hw) 2213 { 2214 int port; 2215 2216 hw->ksz_switch->broad_per = 1; 2217 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); 2218 for (port = 0; port < TOTAL_PORT_NUM; port++) 2219 sw_dis_broad_storm(hw, port); 2220 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1); 2221 } 2222 2223 /** 2224 * hw_cfg_broad_storm - configure broadcast storm 2225 * @hw: The hardware instance. 2226 * @percent: Broadcast storm threshold in percent of transmit rate. 2227 * 2228 * This routine configures the broadcast storm threshold of the switch. 2229 * It is called by user functions. The hardware should be acquired first. 2230 */ 2231 static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) 2232 { 2233 if (percent > 100) 2234 percent = 100; 2235 2236 sw_cfg_broad_storm(hw, percent); 2237 sw_get_broad_storm(hw, &percent); 2238 hw->ksz_switch->broad_per = percent; 2239 } 2240 2241 /** 2242 * sw_dis_prio_rate - disable switch priority rate 2243 * @hw: The hardware instance. 2244 * @port: The port index. 2245 * 2246 * This routine disables the priority rate function of the switch. 2247 */ 2248 static void sw_dis_prio_rate(struct ksz_hw *hw, int port) 2249 { 2250 u32 addr; 2251 2252 PORT_CTRL_ADDR(port, addr); 2253 addr += KS8842_PORT_IN_RATE_OFFSET; 2254 writel(0, hw->io + addr); 2255 } 2256 2257 /** 2258 * sw_init_prio_rate - initialize switch prioirty rate 2259 * @hw: The hardware instance. 2260 * 2261 * This routine initializes the priority rate function of the switch. 2262 */ 2263 static void sw_init_prio_rate(struct ksz_hw *hw) 2264 { 2265 int port; 2266 int prio; 2267 struct ksz_switch *sw = hw->ksz_switch; 2268 2269 for (port = 0; port < TOTAL_PORT_NUM; port++) { 2270 for (prio = 0; prio < PRIO_QUEUES; prio++) { 2271 sw->port_cfg[port].rx_rate[prio] = 2272 sw->port_cfg[port].tx_rate[prio] = 0; 2273 } 2274 sw_dis_prio_rate(hw, port); 2275 } 2276 } 2277 2278 /* Communication */ 2279 2280 static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set) 2281 { 2282 port_cfg(hw, p, 2283 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set); 2284 } 2285 2286 static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set) 2287 { 2288 port_cfg(hw, p, 2289 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set); 2290 } 2291 2292 static inline int port_chk_back_pressure(struct ksz_hw *hw, int p) 2293 { 2294 return port_chk(hw, p, 2295 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE); 2296 } 2297 2298 static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p) 2299 { 2300 return port_chk(hw, p, 2301 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL); 2302 } 2303 2304 /* Spanning Tree */ 2305 2306 static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set) 2307 { 2308 port_cfg(hw, p, 2309 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set); 2310 } 2311 2312 static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set) 2313 { 2314 port_cfg(hw, p, 2315 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set); 2316 } 2317 2318 static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set) 2319 { 2320 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set); 2321 } 2322 2323 static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw) 2324 { 2325 if (!(hw->overrides & FAST_AGING)) { 2326 sw_cfg_fast_aging(hw, 1); 2327 mdelay(1); 2328 sw_cfg_fast_aging(hw, 0); 2329 } 2330 } 2331 2332 /* VLAN */ 2333 2334 static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert) 2335 { 2336 port_cfg(hw, p, 2337 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert); 2338 } 2339 2340 static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove) 2341 { 2342 port_cfg(hw, p, 2343 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove); 2344 } 2345 2346 static inline int port_chk_ins_tag(struct ksz_hw *hw, int p) 2347 { 2348 return port_chk(hw, p, 2349 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG); 2350 } 2351 2352 static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p) 2353 { 2354 return port_chk(hw, p, 2355 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG); 2356 } 2357 2358 static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set) 2359 { 2360 port_cfg(hw, p, 2361 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set); 2362 } 2363 2364 static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set) 2365 { 2366 port_cfg(hw, p, 2367 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set); 2368 } 2369 2370 static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p) 2371 { 2372 return port_chk(hw, p, 2373 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID); 2374 } 2375 2376 static inline int port_chk_in_filter(struct ksz_hw *hw, int p) 2377 { 2378 return port_chk(hw, p, 2379 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER); 2380 } 2381 2382 /* Mirroring */ 2383 2384 static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set) 2385 { 2386 port_cfg(hw, p, 2387 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set); 2388 } 2389 2390 static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set) 2391 { 2392 port_cfg(hw, p, 2393 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set); 2394 } 2395 2396 static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set) 2397 { 2398 port_cfg(hw, p, 2399 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set); 2400 } 2401 2402 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set) 2403 { 2404 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set); 2405 } 2406 2407 static void sw_init_mirror(struct ksz_hw *hw) 2408 { 2409 int port; 2410 2411 for (port = 0; port < TOTAL_PORT_NUM; port++) { 2412 port_cfg_mirror_sniffer(hw, port, 0); 2413 port_cfg_mirror_rx(hw, port, 0); 2414 port_cfg_mirror_tx(hw, port, 0); 2415 } 2416 sw_cfg_mirror_rx_tx(hw, 0); 2417 } 2418 2419 static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set) 2420 { 2421 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET, 2422 SWITCH_UNK_DEF_PORT_ENABLE, set); 2423 } 2424 2425 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw) 2426 { 2427 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET, 2428 SWITCH_UNK_DEF_PORT_ENABLE); 2429 } 2430 2431 static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set) 2432 { 2433 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set); 2434 } 2435 2436 static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port) 2437 { 2438 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0); 2439 } 2440 2441 /* Priority */ 2442 2443 static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set) 2444 { 2445 port_cfg(hw, p, 2446 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set); 2447 } 2448 2449 static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set) 2450 { 2451 port_cfg(hw, p, 2452 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set); 2453 } 2454 2455 static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set) 2456 { 2457 port_cfg(hw, p, 2458 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set); 2459 } 2460 2461 static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set) 2462 { 2463 port_cfg(hw, p, 2464 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set); 2465 } 2466 2467 static inline int port_chk_diffserv(struct ksz_hw *hw, int p) 2468 { 2469 return port_chk(hw, p, 2470 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE); 2471 } 2472 2473 static inline int port_chk_802_1p(struct ksz_hw *hw, int p) 2474 { 2475 return port_chk(hw, p, 2476 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE); 2477 } 2478 2479 static inline int port_chk_replace_vid(struct ksz_hw *hw, int p) 2480 { 2481 return port_chk(hw, p, 2482 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING); 2483 } 2484 2485 static inline int port_chk_prio(struct ksz_hw *hw, int p) 2486 { 2487 return port_chk(hw, p, 2488 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE); 2489 } 2490 2491 /** 2492 * sw_dis_diffserv - disable switch DiffServ priority 2493 * @hw: The hardware instance. 2494 * @port: The port index. 2495 * 2496 * This routine disables the DiffServ priority function of the switch. 2497 */ 2498 static void sw_dis_diffserv(struct ksz_hw *hw, int port) 2499 { 2500 port_cfg_diffserv(hw, port, 0); 2501 } 2502 2503 /** 2504 * sw_dis_802_1p - disable switch 802.1p priority 2505 * @hw: The hardware instance. 2506 * @port: The port index. 2507 * 2508 * This routine disables the 802.1p priority function of the switch. 2509 */ 2510 static void sw_dis_802_1p(struct ksz_hw *hw, int port) 2511 { 2512 port_cfg_802_1p(hw, port, 0); 2513 } 2514 2515 /** 2516 * sw_cfg_replace_null_vid - 2517 * @hw: The hardware instance. 2518 * @set: The flag to disable or enable. 2519 * 2520 */ 2521 static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set) 2522 { 2523 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set); 2524 } 2525 2526 /** 2527 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping 2528 * @hw: The hardware instance. 2529 * @port: The port index. 2530 * @set: The flag to disable or enable. 2531 * 2532 * This routine enables the 802.1p priority re-mapping function of the switch. 2533 * That allows 802.1p priority field to be replaced with the port's default 2534 * tag's priority value if the ingress packet's 802.1p priority has a higher 2535 * priority than port's default tag's priority. 2536 */ 2537 static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set) 2538 { 2539 port_cfg_replace_vid(hw, port, set); 2540 } 2541 2542 /** 2543 * sw_cfg_port_based - configure switch port based priority 2544 * @hw: The hardware instance. 2545 * @port: The port index. 2546 * @prio: The priority to set. 2547 * 2548 * This routine configures the port based priority of the switch. 2549 */ 2550 static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio) 2551 { 2552 u16 data; 2553 2554 if (prio > PORT_BASED_PRIORITY_BASE) 2555 prio = PORT_BASED_PRIORITY_BASE; 2556 2557 hw->ksz_switch->port_cfg[port].port_prio = prio; 2558 2559 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data); 2560 data &= ~PORT_BASED_PRIORITY_MASK; 2561 data |= prio << PORT_BASED_PRIORITY_SHIFT; 2562 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data); 2563 } 2564 2565 /** 2566 * sw_dis_multi_queue - disable transmit multiple queues 2567 * @hw: The hardware instance. 2568 * @port: The port index. 2569 * 2570 * This routine disables the transmit multiple queues selection of the switch 2571 * port. Only single transmit queue on the port. 2572 */ 2573 static void sw_dis_multi_queue(struct ksz_hw *hw, int port) 2574 { 2575 port_cfg_prio(hw, port, 0); 2576 } 2577 2578 /** 2579 * sw_init_prio - initialize switch priority 2580 * @hw: The hardware instance. 2581 * 2582 * This routine initializes the switch QoS priority functions. 2583 */ 2584 static void sw_init_prio(struct ksz_hw *hw) 2585 { 2586 int port; 2587 int tos; 2588 struct ksz_switch *sw = hw->ksz_switch; 2589 2590 /* 2591 * Init all the 802.1p tag priority value to be assigned to different 2592 * priority queue. 2593 */ 2594 sw->p_802_1p[0] = 0; 2595 sw->p_802_1p[1] = 0; 2596 sw->p_802_1p[2] = 1; 2597 sw->p_802_1p[3] = 1; 2598 sw->p_802_1p[4] = 2; 2599 sw->p_802_1p[5] = 2; 2600 sw->p_802_1p[6] = 3; 2601 sw->p_802_1p[7] = 3; 2602 2603 /* 2604 * Init all the DiffServ priority value to be assigned to priority 2605 * queue 0. 2606 */ 2607 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++) 2608 sw->diffserv[tos] = 0; 2609 2610 /* All QoS functions disabled. */ 2611 for (port = 0; port < TOTAL_PORT_NUM; port++) { 2612 sw_dis_multi_queue(hw, port); 2613 sw_dis_diffserv(hw, port); 2614 sw_dis_802_1p(hw, port); 2615 sw_cfg_replace_vid(hw, port, 0); 2616 2617 sw->port_cfg[port].port_prio = 0; 2618 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio); 2619 } 2620 sw_cfg_replace_null_vid(hw, 0); 2621 } 2622 2623 /** 2624 * port_get_def_vid - get port default VID. 2625 * @hw: The hardware instance. 2626 * @port: The port index. 2627 * @vid: Buffer to store the VID. 2628 * 2629 * This routine retrieves the default VID of the port. 2630 */ 2631 static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid) 2632 { 2633 u32 addr; 2634 2635 PORT_CTRL_ADDR(port, addr); 2636 addr += KS8842_PORT_CTRL_VID_OFFSET; 2637 *vid = readw(hw->io + addr); 2638 } 2639 2640 /** 2641 * sw_init_vlan - initialize switch VLAN 2642 * @hw: The hardware instance. 2643 * 2644 * This routine initializes the VLAN function of the switch. 2645 */ 2646 static void sw_init_vlan(struct ksz_hw *hw) 2647 { 2648 int port; 2649 int entry; 2650 struct ksz_switch *sw = hw->ksz_switch; 2651 2652 /* Read 16 VLAN entries from device's VLAN table. */ 2653 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) { 2654 sw_r_vlan_table(hw, entry, 2655 &sw->vlan_table[entry].vid, 2656 &sw->vlan_table[entry].fid, 2657 &sw->vlan_table[entry].member); 2658 } 2659 2660 for (port = 0; port < TOTAL_PORT_NUM; port++) { 2661 port_get_def_vid(hw, port, &sw->port_cfg[port].vid); 2662 sw->port_cfg[port].member = PORT_MASK; 2663 } 2664 } 2665 2666 /** 2667 * sw_cfg_port_base_vlan - configure port-based VLAN membership 2668 * @hw: The hardware instance. 2669 * @port: The port index. 2670 * @member: The port-based VLAN membership. 2671 * 2672 * This routine configures the port-based VLAN membership of the port. 2673 */ 2674 static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member) 2675 { 2676 u32 addr; 2677 u8 data; 2678 2679 PORT_CTRL_ADDR(port, addr); 2680 addr += KS8842_PORT_CTRL_2_OFFSET; 2681 2682 data = readb(hw->io + addr); 2683 data &= ~PORT_VLAN_MEMBERSHIP; 2684 data |= (member & PORT_MASK); 2685 writeb(data, hw->io + addr); 2686 2687 hw->ksz_switch->port_cfg[port].member = member; 2688 } 2689 2690 /** 2691 * sw_get_addr - get the switch MAC address. 2692 * @hw: The hardware instance. 2693 * @mac_addr: Buffer to store the MAC address. 2694 * 2695 * This function retrieves the MAC address of the switch. 2696 */ 2697 static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr) 2698 { 2699 int i; 2700 2701 for (i = 0; i < 6; i += 2) { 2702 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i); 2703 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i); 2704 } 2705 } 2706 2707 /** 2708 * sw_set_addr - configure switch MAC address 2709 * @hw: The hardware instance. 2710 * @mac_addr: The MAC address. 2711 * 2712 * This function configures the MAC address of the switch. 2713 */ 2714 static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr) 2715 { 2716 int i; 2717 2718 for (i = 0; i < 6; i += 2) { 2719 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i); 2720 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i); 2721 } 2722 } 2723 2724 /** 2725 * sw_set_global_ctrl - set switch global control 2726 * @hw: The hardware instance. 2727 * 2728 * This routine sets the global control of the switch function. 2729 */ 2730 static void sw_set_global_ctrl(struct ksz_hw *hw) 2731 { 2732 u16 data; 2733 2734 /* Enable switch MII flow control. */ 2735 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); 2736 data |= SWITCH_FLOW_CTRL; 2737 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); 2738 2739 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET); 2740 2741 /* Enable aggressive back off algorithm in half duplex mode. */ 2742 data |= SWITCH_AGGR_BACKOFF; 2743 2744 /* Enable automatic fast aging when link changed detected. */ 2745 data |= SWITCH_AGING_ENABLE; 2746 data |= SWITCH_LINK_AUTO_AGING; 2747 2748 if (hw->overrides & FAST_AGING) 2749 data |= SWITCH_FAST_AGING; 2750 else 2751 data &= ~SWITCH_FAST_AGING; 2752 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET); 2753 2754 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); 2755 2756 /* Enable no excessive collision drop. */ 2757 data |= NO_EXC_COLLISION_DROP; 2758 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); 2759 } 2760 2761 enum { 2762 STP_STATE_DISABLED = 0, 2763 STP_STATE_LISTENING, 2764 STP_STATE_LEARNING, 2765 STP_STATE_FORWARDING, 2766 STP_STATE_BLOCKED, 2767 STP_STATE_SIMPLE 2768 }; 2769 2770 /** 2771 * port_set_stp_state - configure port spanning tree state 2772 * @hw: The hardware instance. 2773 * @port: The port index. 2774 * @state: The spanning tree state. 2775 * 2776 * This routine configures the spanning tree state of the port. 2777 */ 2778 static void port_set_stp_state(struct ksz_hw *hw, int port, int state) 2779 { 2780 u16 data; 2781 2782 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data); 2783 switch (state) { 2784 case STP_STATE_DISABLED: 2785 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE); 2786 data |= PORT_LEARN_DISABLE; 2787 break; 2788 case STP_STATE_LISTENING: 2789 /* 2790 * No need to turn on transmit because of port direct mode. 2791 * Turning on receive is required if static MAC table is not setup. 2792 */ 2793 data &= ~PORT_TX_ENABLE; 2794 data |= PORT_RX_ENABLE; 2795 data |= PORT_LEARN_DISABLE; 2796 break; 2797 case STP_STATE_LEARNING: 2798 data &= ~PORT_TX_ENABLE; 2799 data |= PORT_RX_ENABLE; 2800 data &= ~PORT_LEARN_DISABLE; 2801 break; 2802 case STP_STATE_FORWARDING: 2803 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2804 data &= ~PORT_LEARN_DISABLE; 2805 break; 2806 case STP_STATE_BLOCKED: 2807 /* 2808 * Need to setup static MAC table with override to keep receiving BPDU 2809 * messages. See sw_init_stp routine. 2810 */ 2811 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE); 2812 data |= PORT_LEARN_DISABLE; 2813 break; 2814 case STP_STATE_SIMPLE: 2815 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2816 data |= PORT_LEARN_DISABLE; 2817 break; 2818 } 2819 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data); 2820 hw->ksz_switch->port_cfg[port].stp_state = state; 2821 } 2822 2823 #define STP_ENTRY 0 2824 #define BROADCAST_ENTRY 1 2825 #define BRIDGE_ADDR_ENTRY 2 2826 #define IPV6_ADDR_ENTRY 3 2827 2828 /** 2829 * sw_clr_sta_mac_table - clear static MAC table 2830 * @hw: The hardware instance. 2831 * 2832 * This routine clears the static MAC table. 2833 */ 2834 static void sw_clr_sta_mac_table(struct ksz_hw *hw) 2835 { 2836 struct ksz_mac_table *entry; 2837 int i; 2838 2839 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) { 2840 entry = &hw->ksz_switch->mac_table[i]; 2841 sw_w_sta_mac_table(hw, i, 2842 entry->mac_addr, entry->ports, 2843 entry->override, 0, 2844 entry->use_fid, entry->fid); 2845 } 2846 } 2847 2848 /** 2849 * sw_init_stp - initialize switch spanning tree support 2850 * @hw: The hardware instance. 2851 * 2852 * This routine initializes the spanning tree support of the switch. 2853 */ 2854 static void sw_init_stp(struct ksz_hw *hw) 2855 { 2856 struct ksz_mac_table *entry; 2857 2858 entry = &hw->ksz_switch->mac_table[STP_ENTRY]; 2859 entry->mac_addr[0] = 0x01; 2860 entry->mac_addr[1] = 0x80; 2861 entry->mac_addr[2] = 0xC2; 2862 entry->mac_addr[3] = 0x00; 2863 entry->mac_addr[4] = 0x00; 2864 entry->mac_addr[5] = 0x00; 2865 entry->ports = HOST_MASK; 2866 entry->override = 1; 2867 entry->valid = 1; 2868 sw_w_sta_mac_table(hw, STP_ENTRY, 2869 entry->mac_addr, entry->ports, 2870 entry->override, entry->valid, 2871 entry->use_fid, entry->fid); 2872 } 2873 2874 /** 2875 * sw_block_addr - block certain packets from the host port 2876 * @hw: The hardware instance. 2877 * 2878 * This routine blocks certain packets from reaching to the host port. 2879 */ 2880 static void sw_block_addr(struct ksz_hw *hw) 2881 { 2882 struct ksz_mac_table *entry; 2883 int i; 2884 2885 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) { 2886 entry = &hw->ksz_switch->mac_table[i]; 2887 entry->valid = 0; 2888 sw_w_sta_mac_table(hw, i, 2889 entry->mac_addr, entry->ports, 2890 entry->override, entry->valid, 2891 entry->use_fid, entry->fid); 2892 } 2893 } 2894 2895 #define PHY_LINK_SUPPORT \ 2896 (PHY_AUTO_NEG_ASYM_PAUSE | \ 2897 PHY_AUTO_NEG_SYM_PAUSE | \ 2898 PHY_AUTO_NEG_100BT4 | \ 2899 PHY_AUTO_NEG_100BTX_FD | \ 2900 PHY_AUTO_NEG_100BTX | \ 2901 PHY_AUTO_NEG_10BT_FD | \ 2902 PHY_AUTO_NEG_10BT) 2903 2904 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data) 2905 { 2906 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); 2907 } 2908 2909 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data) 2910 { 2911 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); 2912 } 2913 2914 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data) 2915 { 2916 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET); 2917 } 2918 2919 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data) 2920 { 2921 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); 2922 } 2923 2924 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data) 2925 { 2926 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); 2927 } 2928 2929 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data) 2930 { 2931 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET); 2932 } 2933 2934 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data) 2935 { 2936 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); 2937 } 2938 2939 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data) 2940 { 2941 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); 2942 } 2943 2944 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data) 2945 { 2946 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); 2947 } 2948 2949 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data) 2950 { 2951 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); 2952 } 2953 2954 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data) 2955 { 2956 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); 2957 } 2958 2959 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data) 2960 { 2961 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); 2962 } 2963 2964 /** 2965 * hw_r_phy - read data from PHY register 2966 * @hw: The hardware instance. 2967 * @port: Port to read. 2968 * @reg: PHY register to read. 2969 * @val: Buffer to store the read data. 2970 * 2971 * This routine reads data from the PHY register. 2972 */ 2973 static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val) 2974 { 2975 int phy; 2976 2977 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; 2978 *val = readw(hw->io + phy); 2979 } 2980 2981 /** 2982 * port_w_phy - write data to PHY register 2983 * @hw: The hardware instance. 2984 * @port: Port to write. 2985 * @reg: PHY register to write. 2986 * @val: Word data to write. 2987 * 2988 * This routine writes data to the PHY register. 2989 */ 2990 static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val) 2991 { 2992 int phy; 2993 2994 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; 2995 writew(val, hw->io + phy); 2996 } 2997 2998 /* 2999 * EEPROM access functions 3000 */ 3001 3002 #define AT93C_CODE 0 3003 #define AT93C_WR_OFF 0x00 3004 #define AT93C_WR_ALL 0x10 3005 #define AT93C_ER_ALL 0x20 3006 #define AT93C_WR_ON 0x30 3007 3008 #define AT93C_WRITE 1 3009 #define AT93C_READ 2 3010 #define AT93C_ERASE 3 3011 3012 #define EEPROM_DELAY 4 3013 3014 static inline void drop_gpio(struct ksz_hw *hw, u8 gpio) 3015 { 3016 u16 data; 3017 3018 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); 3019 data &= ~gpio; 3020 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); 3021 } 3022 3023 static inline void raise_gpio(struct ksz_hw *hw, u8 gpio) 3024 { 3025 u16 data; 3026 3027 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); 3028 data |= gpio; 3029 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); 3030 } 3031 3032 static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio) 3033 { 3034 u16 data; 3035 3036 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); 3037 return (u8)(data & gpio); 3038 } 3039 3040 static void eeprom_clk(struct ksz_hw *hw) 3041 { 3042 raise_gpio(hw, EEPROM_SERIAL_CLOCK); 3043 udelay(EEPROM_DELAY); 3044 drop_gpio(hw, EEPROM_SERIAL_CLOCK); 3045 udelay(EEPROM_DELAY); 3046 } 3047 3048 static u16 spi_r(struct ksz_hw *hw) 3049 { 3050 int i; 3051 u16 temp = 0; 3052 3053 for (i = 15; i >= 0; i--) { 3054 raise_gpio(hw, EEPROM_SERIAL_CLOCK); 3055 udelay(EEPROM_DELAY); 3056 3057 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0; 3058 3059 drop_gpio(hw, EEPROM_SERIAL_CLOCK); 3060 udelay(EEPROM_DELAY); 3061 } 3062 return temp; 3063 } 3064 3065 static void spi_w(struct ksz_hw *hw, u16 data) 3066 { 3067 int i; 3068 3069 for (i = 15; i >= 0; i--) { 3070 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : 3071 drop_gpio(hw, EEPROM_DATA_OUT); 3072 eeprom_clk(hw); 3073 } 3074 } 3075 3076 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg) 3077 { 3078 int i; 3079 3080 /* Initial start bit */ 3081 raise_gpio(hw, EEPROM_DATA_OUT); 3082 eeprom_clk(hw); 3083 3084 /* AT93C operation */ 3085 for (i = 1; i >= 0; i--) { 3086 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : 3087 drop_gpio(hw, EEPROM_DATA_OUT); 3088 eeprom_clk(hw); 3089 } 3090 3091 /* Address location */ 3092 for (i = 5; i >= 0; i--) { 3093 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : 3094 drop_gpio(hw, EEPROM_DATA_OUT); 3095 eeprom_clk(hw); 3096 } 3097 } 3098 3099 #define EEPROM_DATA_RESERVED 0 3100 #define EEPROM_DATA_MAC_ADDR_0 1 3101 #define EEPROM_DATA_MAC_ADDR_1 2 3102 #define EEPROM_DATA_MAC_ADDR_2 3 3103 #define EEPROM_DATA_SUBSYS_ID 4 3104 #define EEPROM_DATA_SUBSYS_VEN_ID 5 3105 #define EEPROM_DATA_PM_CAP 6 3106 3107 /* User defined EEPROM data */ 3108 #define EEPROM_DATA_OTHER_MAC_ADDR 9 3109 3110 /** 3111 * eeprom_read - read from AT93C46 EEPROM 3112 * @hw: The hardware instance. 3113 * @reg: The register offset. 3114 * 3115 * This function reads a word from the AT93C46 EEPROM. 3116 * 3117 * Return the data value. 3118 */ 3119 static u16 eeprom_read(struct ksz_hw *hw, u8 reg) 3120 { 3121 u16 data; 3122 3123 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); 3124 3125 spi_reg(hw, AT93C_READ, reg); 3126 data = spi_r(hw); 3127 3128 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); 3129 3130 return data; 3131 } 3132 3133 /** 3134 * eeprom_write - write to AT93C46 EEPROM 3135 * @hw: The hardware instance. 3136 * @reg: The register offset. 3137 * @data: The data value. 3138 * 3139 * This procedure writes a word to the AT93C46 EEPROM. 3140 */ 3141 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data) 3142 { 3143 int timeout; 3144 3145 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); 3146 3147 /* Enable write. */ 3148 spi_reg(hw, AT93C_CODE, AT93C_WR_ON); 3149 drop_gpio(hw, EEPROM_CHIP_SELECT); 3150 udelay(1); 3151 3152 /* Erase the register. */ 3153 raise_gpio(hw, EEPROM_CHIP_SELECT); 3154 spi_reg(hw, AT93C_ERASE, reg); 3155 drop_gpio(hw, EEPROM_CHIP_SELECT); 3156 udelay(1); 3157 3158 /* Check operation complete. */ 3159 raise_gpio(hw, EEPROM_CHIP_SELECT); 3160 timeout = 8; 3161 mdelay(2); 3162 do { 3163 mdelay(1); 3164 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); 3165 drop_gpio(hw, EEPROM_CHIP_SELECT); 3166 udelay(1); 3167 3168 /* Write the register. */ 3169 raise_gpio(hw, EEPROM_CHIP_SELECT); 3170 spi_reg(hw, AT93C_WRITE, reg); 3171 spi_w(hw, data); 3172 drop_gpio(hw, EEPROM_CHIP_SELECT); 3173 udelay(1); 3174 3175 /* Check operation complete. */ 3176 raise_gpio(hw, EEPROM_CHIP_SELECT); 3177 timeout = 8; 3178 mdelay(2); 3179 do { 3180 mdelay(1); 3181 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); 3182 drop_gpio(hw, EEPROM_CHIP_SELECT); 3183 udelay(1); 3184 3185 /* Disable write. */ 3186 raise_gpio(hw, EEPROM_CHIP_SELECT); 3187 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF); 3188 3189 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); 3190 } 3191 3192 /* 3193 * Link detection routines 3194 */ 3195 3196 static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl) 3197 { 3198 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE; 3199 switch (port->flow_ctrl) { 3200 case PHY_FLOW_CTRL: 3201 ctrl |= PORT_AUTO_NEG_SYM_PAUSE; 3202 break; 3203 /* Not supported. */ 3204 case PHY_TX_ONLY: 3205 case PHY_RX_ONLY: 3206 default: 3207 break; 3208 } 3209 return ctrl; 3210 } 3211 3212 static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx) 3213 { 3214 u32 rx_cfg; 3215 u32 tx_cfg; 3216 3217 rx_cfg = hw->rx_cfg; 3218 tx_cfg = hw->tx_cfg; 3219 if (rx) 3220 hw->rx_cfg |= DMA_RX_FLOW_ENABLE; 3221 else 3222 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE; 3223 if (tx) 3224 hw->tx_cfg |= DMA_TX_FLOW_ENABLE; 3225 else 3226 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; 3227 if (hw->enabled) { 3228 if (rx_cfg != hw->rx_cfg) 3229 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); 3230 if (tx_cfg != hw->tx_cfg) 3231 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); 3232 } 3233 } 3234 3235 static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port, 3236 u16 local, u16 remote) 3237 { 3238 int rx; 3239 int tx; 3240 3241 if (hw->overrides & PAUSE_FLOW_CTRL) 3242 return; 3243 3244 rx = tx = 0; 3245 if (port->force_link) 3246 rx = tx = 1; 3247 if (remote & PHY_AUTO_NEG_SYM_PAUSE) { 3248 if (local & PHY_AUTO_NEG_SYM_PAUSE) { 3249 rx = tx = 1; 3250 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) && 3251 (local & PHY_AUTO_NEG_PAUSE) == 3252 PHY_AUTO_NEG_ASYM_PAUSE) { 3253 tx = 1; 3254 } 3255 } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) { 3256 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE) 3257 rx = 1; 3258 } 3259 if (!hw->ksz_switch) 3260 set_flow_ctrl(hw, rx, tx); 3261 } 3262 3263 static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port, 3264 struct ksz_port_info *info, u16 link_status) 3265 { 3266 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) && 3267 !(hw->overrides & PAUSE_FLOW_CTRL)) { 3268 u32 cfg = hw->tx_cfg; 3269 3270 /* Disable flow control in the half duplex mode. */ 3271 if (1 == info->duplex) 3272 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; 3273 if (hw->enabled && cfg != hw->tx_cfg) 3274 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); 3275 } 3276 } 3277 3278 /** 3279 * port_get_link_speed - get current link status 3280 * @port: The port instance. 3281 * 3282 * This routine reads PHY registers to determine the current link status of the 3283 * switch ports. 3284 */ 3285 static void port_get_link_speed(struct ksz_port *port) 3286 { 3287 uint interrupt; 3288 struct ksz_port_info *info; 3289 struct ksz_port_info *linked = NULL; 3290 struct ksz_hw *hw = port->hw; 3291 u16 data; 3292 u16 status; 3293 u8 local; 3294 u8 remote; 3295 int i; 3296 int p; 3297 int change = 0; 3298 3299 interrupt = hw_block_intr(hw); 3300 3301 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { 3302 info = &hw->port_info[p]; 3303 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); 3304 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status); 3305 3306 /* 3307 * Link status is changing all the time even when there is no 3308 * cable connection! 3309 */ 3310 remote = status & (PORT_AUTO_NEG_COMPLETE | 3311 PORT_STATUS_LINK_GOOD); 3312 local = (u8) data; 3313 3314 /* No change to status. */ 3315 if (local == info->advertised && remote == info->partner) 3316 continue; 3317 3318 info->advertised = local; 3319 info->partner = remote; 3320 if (status & PORT_STATUS_LINK_GOOD) { 3321 3322 /* Remember the first linked port. */ 3323 if (!linked) 3324 linked = info; 3325 3326 info->tx_rate = 10 * TX_RATE_UNIT; 3327 if (status & PORT_STATUS_SPEED_100MBIT) 3328 info->tx_rate = 100 * TX_RATE_UNIT; 3329 3330 info->duplex = 1; 3331 if (status & PORT_STATUS_FULL_DUPLEX) 3332 info->duplex = 2; 3333 3334 if (media_connected != info->state) { 3335 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET, 3336 &data); 3337 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET, 3338 &status); 3339 determine_flow_ctrl(hw, port, data, status); 3340 if (hw->ksz_switch) { 3341 port_cfg_back_pressure(hw, p, 3342 (1 == info->duplex)); 3343 } 3344 change |= 1 << i; 3345 port_cfg_change(hw, port, info, status); 3346 } 3347 info->state = media_connected; 3348 } else { 3349 if (media_disconnected != info->state) { 3350 change |= 1 << i; 3351 3352 /* Indicate the link just goes down. */ 3353 hw->port_mib[p].link_down = 1; 3354 } 3355 info->state = media_disconnected; 3356 } 3357 hw->port_mib[p].state = (u8) info->state; 3358 } 3359 3360 if (linked && media_disconnected == port->linked->state) 3361 port->linked = linked; 3362 3363 hw_restore_intr(hw, interrupt); 3364 } 3365 3366 #define PHY_RESET_TIMEOUT 10 3367 3368 /** 3369 * port_set_link_speed - set port speed 3370 * @port: The port instance. 3371 * 3372 * This routine sets the link speed of the switch ports. 3373 */ 3374 static void port_set_link_speed(struct ksz_port *port) 3375 { 3376 struct ksz_port_info *info; 3377 struct ksz_hw *hw = port->hw; 3378 u16 data; 3379 u16 cfg; 3380 u8 status; 3381 int i; 3382 int p; 3383 3384 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { 3385 info = &hw->port_info[p]; 3386 3387 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); 3388 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status); 3389 3390 cfg = 0; 3391 if (status & PORT_STATUS_LINK_GOOD) 3392 cfg = data; 3393 3394 data |= PORT_AUTO_NEG_ENABLE; 3395 data = advertised_flow_ctrl(port, data); 3396 3397 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX | 3398 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT; 3399 3400 /* Check if manual configuration is specified by the user. */ 3401 if (port->speed || port->duplex) { 3402 if (10 == port->speed) 3403 data &= ~(PORT_AUTO_NEG_100BTX_FD | 3404 PORT_AUTO_NEG_100BTX); 3405 else if (100 == port->speed) 3406 data &= ~(PORT_AUTO_NEG_10BT_FD | 3407 PORT_AUTO_NEG_10BT); 3408 if (1 == port->duplex) 3409 data &= ~(PORT_AUTO_NEG_100BTX_FD | 3410 PORT_AUTO_NEG_10BT_FD); 3411 else if (2 == port->duplex) 3412 data &= ~(PORT_AUTO_NEG_100BTX | 3413 PORT_AUTO_NEG_10BT); 3414 } 3415 if (data != cfg) { 3416 data |= PORT_AUTO_NEG_RESTART; 3417 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data); 3418 } 3419 } 3420 } 3421 3422 /** 3423 * port_force_link_speed - force port speed 3424 * @port: The port instance. 3425 * 3426 * This routine forces the link speed of the switch ports. 3427 */ 3428 static void port_force_link_speed(struct ksz_port *port) 3429 { 3430 struct ksz_hw *hw = port->hw; 3431 u16 data; 3432 int i; 3433 int phy; 3434 int p; 3435 3436 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { 3437 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL; 3438 hw_r_phy_ctrl(hw, phy, &data); 3439 3440 data &= ~PHY_AUTO_NEG_ENABLE; 3441 3442 if (10 == port->speed) 3443 data &= ~PHY_SPEED_100MBIT; 3444 else if (100 == port->speed) 3445 data |= PHY_SPEED_100MBIT; 3446 if (1 == port->duplex) 3447 data &= ~PHY_FULL_DUPLEX; 3448 else if (2 == port->duplex) 3449 data |= PHY_FULL_DUPLEX; 3450 hw_w_phy_ctrl(hw, phy, data); 3451 } 3452 } 3453 3454 static void port_set_power_saving(struct ksz_port *port, int enable) 3455 { 3456 struct ksz_hw *hw = port->hw; 3457 int i; 3458 int p; 3459 3460 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) 3461 port_cfg(hw, p, 3462 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable); 3463 } 3464 3465 /* 3466 * KSZ8841 power management functions 3467 */ 3468 3469 /** 3470 * hw_chk_wol_pme_status - check PMEN pin 3471 * @hw: The hardware instance. 3472 * 3473 * This function is used to check PMEN pin is asserted. 3474 * 3475 * Return 1 if PMEN pin is asserted; otherwise, 0. 3476 */ 3477 static int hw_chk_wol_pme_status(struct ksz_hw *hw) 3478 { 3479 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); 3480 struct pci_dev *pdev = hw_priv->pdev; 3481 u16 data; 3482 3483 if (!pdev->pm_cap) 3484 return 0; 3485 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); 3486 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS; 3487 } 3488 3489 /** 3490 * hw_clr_wol_pme_status - clear PMEN pin 3491 * @hw: The hardware instance. 3492 * 3493 * This routine is used to clear PME_Status to deassert PMEN pin. 3494 */ 3495 static void hw_clr_wol_pme_status(struct ksz_hw *hw) 3496 { 3497 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); 3498 struct pci_dev *pdev = hw_priv->pdev; 3499 u16 data; 3500 3501 if (!pdev->pm_cap) 3502 return; 3503 3504 /* Clear PME_Status to deassert PMEN pin. */ 3505 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); 3506 data |= PCI_PM_CTRL_PME_STATUS; 3507 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data); 3508 } 3509 3510 /** 3511 * hw_cfg_wol_pme - enable or disable Wake-on-LAN 3512 * @hw: The hardware instance. 3513 * @set: The flag indicating whether to enable or disable. 3514 * 3515 * This routine is used to enable or disable Wake-on-LAN. 3516 */ 3517 static void hw_cfg_wol_pme(struct ksz_hw *hw, int set) 3518 { 3519 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); 3520 struct pci_dev *pdev = hw_priv->pdev; 3521 u16 data; 3522 3523 if (!pdev->pm_cap) 3524 return; 3525 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); 3526 data &= ~PCI_PM_CTRL_STATE_MASK; 3527 if (set) 3528 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot; 3529 else 3530 data &= ~PCI_PM_CTRL_PME_ENABLE; 3531 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data); 3532 } 3533 3534 /** 3535 * hw_cfg_wol - configure Wake-on-LAN features 3536 * @hw: The hardware instance. 3537 * @frame: The pattern frame bit. 3538 * @set: The flag indicating whether to enable or disable. 3539 * 3540 * This routine is used to enable or disable certain Wake-on-LAN features. 3541 */ 3542 static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set) 3543 { 3544 u16 data; 3545 3546 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET); 3547 if (set) 3548 data |= frame; 3549 else 3550 data &= ~frame; 3551 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET); 3552 } 3553 3554 /** 3555 * hw_set_wol_frame - program Wake-on-LAN pattern 3556 * @hw: The hardware instance. 3557 * @i: The frame index. 3558 * @mask_size: The size of the mask. 3559 * @mask: Mask to ignore certain bytes in the pattern. 3560 * @frame_size: The size of the frame. 3561 * @pattern: The frame data. 3562 * 3563 * This routine is used to program Wake-on-LAN pattern. 3564 */ 3565 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size, 3566 const u8 *mask, uint frame_size, const u8 *pattern) 3567 { 3568 int bits; 3569 int from; 3570 int len; 3571 int to; 3572 u32 crc; 3573 u8 data[64]; 3574 u8 val = 0; 3575 3576 if (frame_size > mask_size * 8) 3577 frame_size = mask_size * 8; 3578 if (frame_size > 64) 3579 frame_size = 64; 3580 3581 i *= 0x10; 3582 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i); 3583 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i); 3584 3585 bits = len = from = to = 0; 3586 do { 3587 if (bits) { 3588 if ((val & 1)) 3589 data[to++] = pattern[from]; 3590 val >>= 1; 3591 ++from; 3592 --bits; 3593 } else { 3594 val = mask[len]; 3595 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i 3596 + len); 3597 ++len; 3598 if (val) 3599 bits = 8; 3600 else 3601 from += 8; 3602 } 3603 } while (from < (int) frame_size); 3604 if (val) { 3605 bits = mask[len - 1]; 3606 val <<= (from % 8); 3607 bits &= ~val; 3608 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len - 3609 1); 3610 } 3611 crc = ether_crc(to, data); 3612 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i); 3613 } 3614 3615 /** 3616 * hw_add_wol_arp - add ARP pattern 3617 * @hw: The hardware instance. 3618 * @ip_addr: The IPv4 address assigned to the device. 3619 * 3620 * This routine is used to add ARP pattern for waking up the host. 3621 */ 3622 static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr) 3623 { 3624 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 }; 3625 u8 pattern[42] = { 3626 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 3627 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 3628 0x08, 0x06, 3629 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 3630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 3631 0x00, 0x00, 0x00, 0x00, 3632 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 3633 0x00, 0x00, 0x00, 0x00 }; 3634 3635 memcpy(&pattern[38], ip_addr, 4); 3636 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern); 3637 } 3638 3639 /** 3640 * hw_add_wol_bcast - add broadcast pattern 3641 * @hw: The hardware instance. 3642 * 3643 * This routine is used to add broadcast pattern for waking up the host. 3644 */ 3645 static void hw_add_wol_bcast(struct ksz_hw *hw) 3646 { 3647 static const u8 mask[] = { 0x3F }; 3648 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3649 3650 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern); 3651 } 3652 3653 /** 3654 * hw_add_wol_mcast - add multicast pattern 3655 * @hw: The hardware instance. 3656 * 3657 * This routine is used to add multicast pattern for waking up the host. 3658 * 3659 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used 3660 * by IPv6 ping command. Note that multicast packets are filtred through the 3661 * multicast hash table, so not all multicast packets can wake up the host. 3662 */ 3663 static void hw_add_wol_mcast(struct ksz_hw *hw) 3664 { 3665 static const u8 mask[] = { 0x3F }; 3666 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 }; 3667 3668 memcpy(&pattern[3], &hw->override_addr[3], 3); 3669 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern); 3670 } 3671 3672 /** 3673 * hw_add_wol_ucast - add unicast pattern 3674 * @hw: The hardware instance. 3675 * 3676 * This routine is used to add unicast pattern to wakeup the host. 3677 * 3678 * It is assumed the unicast packet is directed to the device, as the hardware 3679 * can only receive them in normal case. 3680 */ 3681 static void hw_add_wol_ucast(struct ksz_hw *hw) 3682 { 3683 static const u8 mask[] = { 0x3F }; 3684 3685 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr); 3686 } 3687 3688 /** 3689 * hw_enable_wol - enable Wake-on-LAN 3690 * @hw: The hardware instance. 3691 * @wol_enable: The Wake-on-LAN settings. 3692 * @net_addr: The IPv4 address assigned to the device. 3693 * 3694 * This routine is used to enable Wake-on-LAN depending on driver settings. 3695 */ 3696 static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr) 3697 { 3698 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC)); 3699 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST)); 3700 hw_add_wol_ucast(hw); 3701 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST)); 3702 hw_add_wol_mcast(hw); 3703 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST)); 3704 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP)); 3705 hw_add_wol_arp(hw, net_addr); 3706 } 3707 3708 /** 3709 * hw_init - check driver is correct for the hardware 3710 * @hw: The hardware instance. 3711 * 3712 * This function checks the hardware is correct for this driver and sets the 3713 * hardware up for proper initialization. 3714 * 3715 * Return number of ports or 0 if not right. 3716 */ 3717 static int hw_init(struct ksz_hw *hw) 3718 { 3719 int rc = 0; 3720 u16 data; 3721 u16 revision; 3722 3723 /* Set bus speed to 125MHz. */ 3724 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET); 3725 3726 /* Check KSZ884x chip ID. */ 3727 data = readw(hw->io + KS884X_CHIP_ID_OFFSET); 3728 3729 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT; 3730 data &= KS884X_CHIP_ID_MASK_41; 3731 if (REG_CHIP_ID_41 == data) 3732 rc = 1; 3733 else if (REG_CHIP_ID_42 == data) 3734 rc = 2; 3735 else 3736 return 0; 3737 3738 /* Setup hardware features or bug workarounds. */ 3739 if (revision <= 1) { 3740 hw->features |= SMALL_PACKET_TX_BUG; 3741 if (1 == rc) 3742 hw->features |= HALF_DUPLEX_SIGNAL_BUG; 3743 } 3744 return rc; 3745 } 3746 3747 /** 3748 * hw_reset - reset the hardware 3749 * @hw: The hardware instance. 3750 * 3751 * This routine resets the hardware. 3752 */ 3753 static void hw_reset(struct ksz_hw *hw) 3754 { 3755 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET); 3756 3757 /* Wait for device to reset. */ 3758 mdelay(10); 3759 3760 /* Write 0 to clear device reset. */ 3761 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET); 3762 } 3763 3764 /** 3765 * hw_setup - setup the hardware 3766 * @hw: The hardware instance. 3767 * 3768 * This routine setup the hardware for proper operation. 3769 */ 3770 static void hw_setup(struct ksz_hw *hw) 3771 { 3772 #if SET_DEFAULT_LED 3773 u16 data; 3774 3775 /* Change default LED mode. */ 3776 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET); 3777 data &= ~LED_MODE; 3778 data |= SET_DEFAULT_LED; 3779 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET); 3780 #endif 3781 3782 /* Setup transmit control. */ 3783 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE | 3784 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE); 3785 3786 /* Setup receive control. */ 3787 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST | 3788 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE); 3789 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST; 3790 3791 /* Hardware cannot handle UDP packet in IP fragments. */ 3792 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP); 3793 3794 if (hw->all_multi) 3795 hw->rx_cfg |= DMA_RX_ALL_MULTICAST; 3796 if (hw->promiscuous) 3797 hw->rx_cfg |= DMA_RX_PROMISCUOUS; 3798 } 3799 3800 /** 3801 * hw_setup_intr - setup interrupt mask 3802 * @hw: The hardware instance. 3803 * 3804 * This routine setup the interrupt mask for proper operation. 3805 */ 3806 static void hw_setup_intr(struct ksz_hw *hw) 3807 { 3808 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN; 3809 } 3810 3811 static void ksz_check_desc_num(struct ksz_desc_info *info) 3812 { 3813 #define MIN_DESC_SHIFT 2 3814 3815 int alloc = info->alloc; 3816 int shift; 3817 3818 shift = 0; 3819 while (!(alloc & 1)) { 3820 shift++; 3821 alloc >>= 1; 3822 } 3823 if (alloc != 1 || shift < MIN_DESC_SHIFT) { 3824 pr_alert("Hardware descriptor numbers not right!\n"); 3825 while (alloc) { 3826 shift++; 3827 alloc >>= 1; 3828 } 3829 if (shift < MIN_DESC_SHIFT) 3830 shift = MIN_DESC_SHIFT; 3831 alloc = 1 << shift; 3832 info->alloc = alloc; 3833 } 3834 info->mask = info->alloc - 1; 3835 } 3836 3837 static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit) 3838 { 3839 int i; 3840 u32 phys = desc_info->ring_phys; 3841 struct ksz_hw_desc *desc = desc_info->ring_virt; 3842 struct ksz_desc *cur = desc_info->ring; 3843 struct ksz_desc *previous = NULL; 3844 3845 for (i = 0; i < desc_info->alloc; i++) { 3846 cur->phw = desc++; 3847 phys += desc_info->size; 3848 previous = cur++; 3849 previous->phw->next = cpu_to_le32(phys); 3850 } 3851 previous->phw->next = cpu_to_le32(desc_info->ring_phys); 3852 previous->sw.buf.rx.end_of_ring = 1; 3853 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data); 3854 3855 desc_info->avail = desc_info->alloc; 3856 desc_info->last = desc_info->next = 0; 3857 3858 desc_info->cur = desc_info->ring; 3859 } 3860 3861 /** 3862 * hw_set_desc_base - set descriptor base addresses 3863 * @hw: The hardware instance. 3864 * @tx_addr: The transmit descriptor base. 3865 * @rx_addr: The receive descriptor base. 3866 * 3867 * This routine programs the descriptor base addresses after reset. 3868 */ 3869 static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr) 3870 { 3871 /* Set base address of Tx/Rx descriptors. */ 3872 writel(tx_addr, hw->io + KS_DMA_TX_ADDR); 3873 writel(rx_addr, hw->io + KS_DMA_RX_ADDR); 3874 } 3875 3876 static void hw_reset_pkts(struct ksz_desc_info *info) 3877 { 3878 info->cur = info->ring; 3879 info->avail = info->alloc; 3880 info->last = info->next = 0; 3881 } 3882 3883 static inline void hw_resume_rx(struct ksz_hw *hw) 3884 { 3885 writel(DMA_START, hw->io + KS_DMA_RX_START); 3886 } 3887 3888 /** 3889 * hw_start_rx - start receiving 3890 * @hw: The hardware instance. 3891 * 3892 * This routine starts the receive function of the hardware. 3893 */ 3894 static void hw_start_rx(struct ksz_hw *hw) 3895 { 3896 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); 3897 3898 /* Notify when the receive stops. */ 3899 hw->intr_mask |= KS884X_INT_RX_STOPPED; 3900 3901 writel(DMA_START, hw->io + KS_DMA_RX_START); 3902 hw_ack_intr(hw, KS884X_INT_RX_STOPPED); 3903 hw->rx_stop++; 3904 3905 /* Variable overflows. */ 3906 if (0 == hw->rx_stop) 3907 hw->rx_stop = 2; 3908 } 3909 3910 /** 3911 * hw_stop_rx - stop receiving 3912 * @hw: The hardware instance. 3913 * 3914 * This routine stops the receive function of the hardware. 3915 */ 3916 static void hw_stop_rx(struct ksz_hw *hw) 3917 { 3918 hw->rx_stop = 0; 3919 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED); 3920 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL); 3921 } 3922 3923 /** 3924 * hw_start_tx - start transmitting 3925 * @hw: The hardware instance. 3926 * 3927 * This routine starts the transmit function of the hardware. 3928 */ 3929 static void hw_start_tx(struct ksz_hw *hw) 3930 { 3931 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); 3932 } 3933 3934 /** 3935 * hw_stop_tx - stop transmitting 3936 * @hw: The hardware instance. 3937 * 3938 * This routine stops the transmit function of the hardware. 3939 */ 3940 static void hw_stop_tx(struct ksz_hw *hw) 3941 { 3942 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL); 3943 } 3944 3945 /** 3946 * hw_disable - disable hardware 3947 * @hw: The hardware instance. 3948 * 3949 * This routine disables the hardware. 3950 */ 3951 static void hw_disable(struct ksz_hw *hw) 3952 { 3953 hw_stop_rx(hw); 3954 hw_stop_tx(hw); 3955 hw->enabled = 0; 3956 } 3957 3958 /** 3959 * hw_enable - enable hardware 3960 * @hw: The hardware instance. 3961 * 3962 * This routine enables the hardware. 3963 */ 3964 static void hw_enable(struct ksz_hw *hw) 3965 { 3966 hw_start_tx(hw); 3967 hw_start_rx(hw); 3968 hw->enabled = 1; 3969 } 3970 3971 /** 3972 * hw_alloc_pkt - allocate enough descriptors for transmission 3973 * @hw: The hardware instance. 3974 * @length: The length of the packet. 3975 * @physical: Number of descriptors required. 3976 * 3977 * This function allocates descriptors for transmission. 3978 * 3979 * Return 0 if not successful; 1 for buffer copy; or number of descriptors. 3980 */ 3981 static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical) 3982 { 3983 /* Always leave one descriptor free. */ 3984 if (hw->tx_desc_info.avail <= 1) 3985 return 0; 3986 3987 /* Allocate a descriptor for transmission and mark it current. */ 3988 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur); 3989 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1; 3990 3991 /* Keep track of number of transmit descriptors used so far. */ 3992 ++hw->tx_int_cnt; 3993 hw->tx_size += length; 3994 3995 /* Cannot hold on too much data. */ 3996 if (hw->tx_size >= MAX_TX_HELD_SIZE) 3997 hw->tx_int_cnt = hw->tx_int_mask + 1; 3998 3999 if (physical > hw->tx_desc_info.avail) 4000 return 1; 4001 4002 return hw->tx_desc_info.avail; 4003 } 4004 4005 /** 4006 * hw_send_pkt - mark packet for transmission 4007 * @hw: The hardware instance. 4008 * 4009 * This routine marks the packet for transmission in PCI version. 4010 */ 4011 static void hw_send_pkt(struct ksz_hw *hw) 4012 { 4013 struct ksz_desc *cur = hw->tx_desc_info.cur; 4014 4015 cur->sw.buf.tx.last_seg = 1; 4016 4017 /* Interrupt only after specified number of descriptors used. */ 4018 if (hw->tx_int_cnt > hw->tx_int_mask) { 4019 cur->sw.buf.tx.intr = 1; 4020 hw->tx_int_cnt = 0; 4021 hw->tx_size = 0; 4022 } 4023 4024 /* KSZ8842 supports port directed transmission. */ 4025 cur->sw.buf.tx.dest_port = hw->dst_ports; 4026 4027 release_desc(cur); 4028 4029 writel(0, hw->io + KS_DMA_TX_START); 4030 } 4031 4032 static int empty_addr(u8 *addr) 4033 { 4034 u32 *addr1 = (u32 *) addr; 4035 u16 *addr2 = (u16 *) &addr[4]; 4036 4037 return 0 == *addr1 && 0 == *addr2; 4038 } 4039 4040 /** 4041 * hw_set_addr - set MAC address 4042 * @hw: The hardware instance. 4043 * 4044 * This routine programs the MAC address of the hardware when the address is 4045 * overrided. 4046 */ 4047 static void hw_set_addr(struct ksz_hw *hw) 4048 { 4049 int i; 4050 4051 for (i = 0; i < ETH_ALEN; i++) 4052 writeb(hw->override_addr[MAC_ADDR_ORDER(i)], 4053 hw->io + KS884X_ADDR_0_OFFSET + i); 4054 4055 sw_set_addr(hw, hw->override_addr); 4056 } 4057 4058 /** 4059 * hw_read_addr - read MAC address 4060 * @hw: The hardware instance. 4061 * 4062 * This routine retrieves the MAC address of the hardware. 4063 */ 4064 static void hw_read_addr(struct ksz_hw *hw) 4065 { 4066 int i; 4067 4068 for (i = 0; i < ETH_ALEN; i++) 4069 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io + 4070 KS884X_ADDR_0_OFFSET + i); 4071 4072 if (!hw->mac_override) { 4073 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN); 4074 if (empty_addr(hw->override_addr)) { 4075 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN); 4076 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS, 4077 ETH_ALEN); 4078 hw->override_addr[5] += hw->id; 4079 hw_set_addr(hw); 4080 } 4081 } 4082 } 4083 4084 static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr) 4085 { 4086 int i; 4087 u32 mac_addr_lo; 4088 u32 mac_addr_hi; 4089 4090 mac_addr_hi = 0; 4091 for (i = 0; i < 2; i++) { 4092 mac_addr_hi <<= 8; 4093 mac_addr_hi |= mac_addr[i]; 4094 } 4095 mac_addr_hi |= ADD_ADDR_ENABLE; 4096 mac_addr_lo = 0; 4097 for (i = 2; i < 6; i++) { 4098 mac_addr_lo <<= 8; 4099 mac_addr_lo |= mac_addr[i]; 4100 } 4101 index *= ADD_ADDR_INCR; 4102 4103 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO); 4104 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI); 4105 } 4106 4107 static void hw_set_add_addr(struct ksz_hw *hw) 4108 { 4109 int i; 4110 4111 for (i = 0; i < ADDITIONAL_ENTRIES; i++) { 4112 if (empty_addr(hw->address[i])) 4113 writel(0, hw->io + ADD_ADDR_INCR * i + 4114 KS_ADD_ADDR_0_HI); 4115 else 4116 hw_ena_add_addr(hw, i, hw->address[i]); 4117 } 4118 } 4119 4120 static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr) 4121 { 4122 int i; 4123 int j = ADDITIONAL_ENTRIES; 4124 4125 if (ether_addr_equal(hw->override_addr, mac_addr)) 4126 return 0; 4127 for (i = 0; i < hw->addr_list_size; i++) { 4128 if (ether_addr_equal(hw->address[i], mac_addr)) 4129 return 0; 4130 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i])) 4131 j = i; 4132 } 4133 if (j < ADDITIONAL_ENTRIES) { 4134 memcpy(hw->address[j], mac_addr, ETH_ALEN); 4135 hw_ena_add_addr(hw, j, hw->address[j]); 4136 return 0; 4137 } 4138 return -1; 4139 } 4140 4141 static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr) 4142 { 4143 int i; 4144 4145 for (i = 0; i < hw->addr_list_size; i++) { 4146 if (ether_addr_equal(hw->address[i], mac_addr)) { 4147 memset(hw->address[i], 0, ETH_ALEN); 4148 writel(0, hw->io + ADD_ADDR_INCR * i + 4149 KS_ADD_ADDR_0_HI); 4150 return 0; 4151 } 4152 } 4153 return -1; 4154 } 4155 4156 /** 4157 * hw_clr_multicast - clear multicast addresses 4158 * @hw: The hardware instance. 4159 * 4160 * This routine removes all multicast addresses set in the hardware. 4161 */ 4162 static void hw_clr_multicast(struct ksz_hw *hw) 4163 { 4164 int i; 4165 4166 for (i = 0; i < HW_MULTICAST_SIZE; i++) { 4167 hw->multi_bits[i] = 0; 4168 4169 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i); 4170 } 4171 } 4172 4173 /** 4174 * hw_set_grp_addr - set multicast addresses 4175 * @hw: The hardware instance. 4176 * 4177 * This routine programs multicast addresses for the hardware to accept those 4178 * addresses. 4179 */ 4180 static void hw_set_grp_addr(struct ksz_hw *hw) 4181 { 4182 int i; 4183 int index; 4184 int position; 4185 int value; 4186 4187 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE); 4188 4189 for (i = 0; i < hw->multi_list_size; i++) { 4190 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f; 4191 index = position >> 3; 4192 value = 1 << (position & 7); 4193 hw->multi_bits[index] |= (u8) value; 4194 } 4195 4196 for (i = 0; i < HW_MULTICAST_SIZE; i++) 4197 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET + 4198 i); 4199 } 4200 4201 /** 4202 * hw_set_multicast - enable or disable all multicast receiving 4203 * @hw: The hardware instance. 4204 * @multicast: To turn on or off the all multicast feature. 4205 * 4206 * This routine enables/disables the hardware to accept all multicast packets. 4207 */ 4208 static void hw_set_multicast(struct ksz_hw *hw, u8 multicast) 4209 { 4210 /* Stop receiving for reconfiguration. */ 4211 hw_stop_rx(hw); 4212 4213 if (multicast) 4214 hw->rx_cfg |= DMA_RX_ALL_MULTICAST; 4215 else 4216 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST; 4217 4218 if (hw->enabled) 4219 hw_start_rx(hw); 4220 } 4221 4222 /** 4223 * hw_set_promiscuous - enable or disable promiscuous receiving 4224 * @hw: The hardware instance. 4225 * @prom: To turn on or off the promiscuous feature. 4226 * 4227 * This routine enables/disables the hardware to accept all packets. 4228 */ 4229 static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom) 4230 { 4231 /* Stop receiving for reconfiguration. */ 4232 hw_stop_rx(hw); 4233 4234 if (prom) 4235 hw->rx_cfg |= DMA_RX_PROMISCUOUS; 4236 else 4237 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS; 4238 4239 if (hw->enabled) 4240 hw_start_rx(hw); 4241 } 4242 4243 /** 4244 * sw_enable - enable the switch 4245 * @hw: The hardware instance. 4246 * @enable: The flag to enable or disable the switch 4247 * 4248 * This routine is used to enable/disable the switch in KSZ8842. 4249 */ 4250 static void sw_enable(struct ksz_hw *hw, int enable) 4251 { 4252 int port; 4253 4254 for (port = 0; port < SWITCH_PORT_NUM; port++) { 4255 if (hw->dev_count > 1) { 4256 /* Set port-base vlan membership with host port. */ 4257 sw_cfg_port_base_vlan(hw, port, 4258 HOST_MASK | (1 << port)); 4259 port_set_stp_state(hw, port, STP_STATE_DISABLED); 4260 } else { 4261 sw_cfg_port_base_vlan(hw, port, PORT_MASK); 4262 port_set_stp_state(hw, port, STP_STATE_FORWARDING); 4263 } 4264 } 4265 if (hw->dev_count > 1) 4266 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); 4267 else 4268 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING); 4269 4270 if (enable) 4271 enable = KS8842_START; 4272 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET); 4273 } 4274 4275 /** 4276 * sw_setup - setup the switch 4277 * @hw: The hardware instance. 4278 * 4279 * This routine setup the hardware switch engine for default operation. 4280 */ 4281 static void sw_setup(struct ksz_hw *hw) 4282 { 4283 int port; 4284 4285 sw_set_global_ctrl(hw); 4286 4287 /* Enable switch broadcast storm protection at 10% percent rate. */ 4288 sw_init_broad_storm(hw); 4289 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE); 4290 for (port = 0; port < SWITCH_PORT_NUM; port++) 4291 sw_ena_broad_storm(hw, port); 4292 4293 sw_init_prio(hw); 4294 4295 sw_init_mirror(hw); 4296 4297 sw_init_prio_rate(hw); 4298 4299 sw_init_vlan(hw); 4300 4301 if (hw->features & STP_SUPPORT) 4302 sw_init_stp(hw); 4303 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, 4304 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL)) 4305 hw->overrides |= PAUSE_FLOW_CTRL; 4306 sw_enable(hw, 1); 4307 } 4308 4309 /** 4310 * ksz_start_timer - start kernel timer 4311 * @info: Kernel timer information. 4312 * @time: The time tick. 4313 * 4314 * This routine starts the kernel timer after the specified time tick. 4315 */ 4316 static void ksz_start_timer(struct ksz_timer_info *info, int time) 4317 { 4318 info->cnt = 0; 4319 info->timer.expires = jiffies + time; 4320 add_timer(&info->timer); 4321 4322 /* infinity */ 4323 info->max = -1; 4324 } 4325 4326 /** 4327 * ksz_stop_timer - stop kernel timer 4328 * @info: Kernel timer information. 4329 * 4330 * This routine stops the kernel timer. 4331 */ 4332 static void ksz_stop_timer(struct ksz_timer_info *info) 4333 { 4334 if (info->max) { 4335 info->max = 0; 4336 del_timer_sync(&info->timer); 4337 } 4338 } 4339 4340 static void ksz_init_timer(struct ksz_timer_info *info, int period, 4341 void (*function)(unsigned long), void *data) 4342 { 4343 info->max = 0; 4344 info->period = period; 4345 init_timer(&info->timer); 4346 info->timer.function = function; 4347 info->timer.data = (unsigned long) data; 4348 } 4349 4350 static void ksz_update_timer(struct ksz_timer_info *info) 4351 { 4352 ++info->cnt; 4353 if (info->max > 0) { 4354 if (info->cnt < info->max) { 4355 info->timer.expires = jiffies + info->period; 4356 add_timer(&info->timer); 4357 } else 4358 info->max = 0; 4359 } else if (info->max < 0) { 4360 info->timer.expires = jiffies + info->period; 4361 add_timer(&info->timer); 4362 } 4363 } 4364 4365 /** 4366 * ksz_alloc_soft_desc - allocate software descriptors 4367 * @desc_info: Descriptor information structure. 4368 * @transmit: Indication that descriptors are for transmit. 4369 * 4370 * This local function allocates software descriptors for manipulation in 4371 * memory. 4372 * 4373 * Return 0 if successful. 4374 */ 4375 static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit) 4376 { 4377 desc_info->ring = kzalloc(sizeof(struct ksz_desc) * desc_info->alloc, 4378 GFP_KERNEL); 4379 if (!desc_info->ring) 4380 return 1; 4381 hw_init_desc(desc_info, transmit); 4382 return 0; 4383 } 4384 4385 /** 4386 * ksz_alloc_desc - allocate hardware descriptors 4387 * @adapter: Adapter information structure. 4388 * 4389 * This local function allocates hardware descriptors for receiving and 4390 * transmitting. 4391 * 4392 * Return 0 if successful. 4393 */ 4394 static int ksz_alloc_desc(struct dev_info *adapter) 4395 { 4396 struct ksz_hw *hw = &adapter->hw; 4397 int offset; 4398 4399 /* Allocate memory for RX & TX descriptors. */ 4400 adapter->desc_pool.alloc_size = 4401 hw->rx_desc_info.size * hw->rx_desc_info.alloc + 4402 hw->tx_desc_info.size * hw->tx_desc_info.alloc + 4403 DESC_ALIGNMENT; 4404 4405 adapter->desc_pool.alloc_virt = 4406 pci_zalloc_consistent(adapter->pdev, 4407 adapter->desc_pool.alloc_size, 4408 &adapter->desc_pool.dma_addr); 4409 if (adapter->desc_pool.alloc_virt == NULL) { 4410 adapter->desc_pool.alloc_size = 0; 4411 return 1; 4412 } 4413 4414 /* Align to the next cache line boundary. */ 4415 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ? 4416 (DESC_ALIGNMENT - 4417 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0); 4418 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset; 4419 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset; 4420 4421 /* Allocate receive/transmit descriptors. */ 4422 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *) 4423 adapter->desc_pool.virt; 4424 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys; 4425 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size; 4426 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *) 4427 (adapter->desc_pool.virt + offset); 4428 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset; 4429 4430 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0)) 4431 return 1; 4432 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1)) 4433 return 1; 4434 4435 return 0; 4436 } 4437 4438 /** 4439 * free_dma_buf - release DMA buffer resources 4440 * @adapter: Adapter information structure. 4441 * 4442 * This routine is just a helper function to release the DMA buffer resources. 4443 */ 4444 static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf, 4445 int direction) 4446 { 4447 pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction); 4448 dev_kfree_skb(dma_buf->skb); 4449 dma_buf->skb = NULL; 4450 dma_buf->dma = 0; 4451 } 4452 4453 /** 4454 * ksz_init_rx_buffers - initialize receive descriptors 4455 * @adapter: Adapter information structure. 4456 * 4457 * This routine initializes DMA buffers for receiving. 4458 */ 4459 static void ksz_init_rx_buffers(struct dev_info *adapter) 4460 { 4461 int i; 4462 struct ksz_desc *desc; 4463 struct ksz_dma_buf *dma_buf; 4464 struct ksz_hw *hw = &adapter->hw; 4465 struct ksz_desc_info *info = &hw->rx_desc_info; 4466 4467 for (i = 0; i < hw->rx_desc_info.alloc; i++) { 4468 get_rx_pkt(info, &desc); 4469 4470 dma_buf = DMA_BUFFER(desc); 4471 if (dma_buf->skb && dma_buf->len != adapter->mtu) 4472 free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE); 4473 dma_buf->len = adapter->mtu; 4474 if (!dma_buf->skb) 4475 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC); 4476 if (dma_buf->skb && !dma_buf->dma) 4477 dma_buf->dma = pci_map_single( 4478 adapter->pdev, 4479 skb_tail_pointer(dma_buf->skb), 4480 dma_buf->len, 4481 PCI_DMA_FROMDEVICE); 4482 4483 /* Set descriptor. */ 4484 set_rx_buf(desc, dma_buf->dma); 4485 set_rx_len(desc, dma_buf->len); 4486 release_desc(desc); 4487 } 4488 } 4489 4490 /** 4491 * ksz_alloc_mem - allocate memory for hardware descriptors 4492 * @adapter: Adapter information structure. 4493 * 4494 * This function allocates memory for use by hardware descriptors for receiving 4495 * and transmitting. 4496 * 4497 * Return 0 if successful. 4498 */ 4499 static int ksz_alloc_mem(struct dev_info *adapter) 4500 { 4501 struct ksz_hw *hw = &adapter->hw; 4502 4503 /* Determine the number of receive and transmit descriptors. */ 4504 hw->rx_desc_info.alloc = NUM_OF_RX_DESC; 4505 hw->tx_desc_info.alloc = NUM_OF_TX_DESC; 4506 4507 /* Determine how many descriptors to skip transmit interrupt. */ 4508 hw->tx_int_cnt = 0; 4509 hw->tx_int_mask = NUM_OF_TX_DESC / 4; 4510 if (hw->tx_int_mask > 8) 4511 hw->tx_int_mask = 8; 4512 while (hw->tx_int_mask) { 4513 hw->tx_int_cnt++; 4514 hw->tx_int_mask >>= 1; 4515 } 4516 if (hw->tx_int_cnt) { 4517 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1; 4518 hw->tx_int_cnt = 0; 4519 } 4520 4521 /* Determine the descriptor size. */ 4522 hw->rx_desc_info.size = 4523 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) / 4524 DESC_ALIGNMENT) * DESC_ALIGNMENT); 4525 hw->tx_desc_info.size = 4526 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) / 4527 DESC_ALIGNMENT) * DESC_ALIGNMENT); 4528 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc)) 4529 pr_alert("Hardware descriptor size not right!\n"); 4530 ksz_check_desc_num(&hw->rx_desc_info); 4531 ksz_check_desc_num(&hw->tx_desc_info); 4532 4533 /* Allocate descriptors. */ 4534 if (ksz_alloc_desc(adapter)) 4535 return 1; 4536 4537 return 0; 4538 } 4539 4540 /** 4541 * ksz_free_desc - free software and hardware descriptors 4542 * @adapter: Adapter information structure. 4543 * 4544 * This local routine frees the software and hardware descriptors allocated by 4545 * ksz_alloc_desc(). 4546 */ 4547 static void ksz_free_desc(struct dev_info *adapter) 4548 { 4549 struct ksz_hw *hw = &adapter->hw; 4550 4551 /* Reset descriptor. */ 4552 hw->rx_desc_info.ring_virt = NULL; 4553 hw->tx_desc_info.ring_virt = NULL; 4554 hw->rx_desc_info.ring_phys = 0; 4555 hw->tx_desc_info.ring_phys = 0; 4556 4557 /* Free memory. */ 4558 if (adapter->desc_pool.alloc_virt) 4559 pci_free_consistent( 4560 adapter->pdev, 4561 adapter->desc_pool.alloc_size, 4562 adapter->desc_pool.alloc_virt, 4563 adapter->desc_pool.dma_addr); 4564 4565 /* Reset resource pool. */ 4566 adapter->desc_pool.alloc_size = 0; 4567 adapter->desc_pool.alloc_virt = NULL; 4568 4569 kfree(hw->rx_desc_info.ring); 4570 hw->rx_desc_info.ring = NULL; 4571 kfree(hw->tx_desc_info.ring); 4572 hw->tx_desc_info.ring = NULL; 4573 } 4574 4575 /** 4576 * ksz_free_buffers - free buffers used in the descriptors 4577 * @adapter: Adapter information structure. 4578 * @desc_info: Descriptor information structure. 4579 * 4580 * This local routine frees buffers used in the DMA buffers. 4581 */ 4582 static void ksz_free_buffers(struct dev_info *adapter, 4583 struct ksz_desc_info *desc_info, int direction) 4584 { 4585 int i; 4586 struct ksz_dma_buf *dma_buf; 4587 struct ksz_desc *desc = desc_info->ring; 4588 4589 for (i = 0; i < desc_info->alloc; i++) { 4590 dma_buf = DMA_BUFFER(desc); 4591 if (dma_buf->skb) 4592 free_dma_buf(adapter, dma_buf, direction); 4593 desc++; 4594 } 4595 } 4596 4597 /** 4598 * ksz_free_mem - free all resources used by descriptors 4599 * @adapter: Adapter information structure. 4600 * 4601 * This local routine frees all the resources allocated by ksz_alloc_mem(). 4602 */ 4603 static void ksz_free_mem(struct dev_info *adapter) 4604 { 4605 /* Free transmit buffers. */ 4606 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info, 4607 PCI_DMA_TODEVICE); 4608 4609 /* Free receive buffers. */ 4610 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info, 4611 PCI_DMA_FROMDEVICE); 4612 4613 /* Free descriptors. */ 4614 ksz_free_desc(adapter); 4615 } 4616 4617 static void get_mib_counters(struct ksz_hw *hw, int first, int cnt, 4618 u64 *counter) 4619 { 4620 int i; 4621 int mib; 4622 int port; 4623 struct ksz_port_mib *port_mib; 4624 4625 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); 4626 for (i = 0, port = first; i < cnt; i++, port++) { 4627 port_mib = &hw->port_mib[port]; 4628 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++) 4629 counter[mib] += port_mib->counter[mib]; 4630 } 4631 } 4632 4633 /** 4634 * send_packet - send packet 4635 * @skb: Socket buffer. 4636 * @dev: Network device. 4637 * 4638 * This routine is used to send a packet out to the network. 4639 */ 4640 static void send_packet(struct sk_buff *skb, struct net_device *dev) 4641 { 4642 struct ksz_desc *desc; 4643 struct ksz_desc *first; 4644 struct dev_priv *priv = netdev_priv(dev); 4645 struct dev_info *hw_priv = priv->adapter; 4646 struct ksz_hw *hw = &hw_priv->hw; 4647 struct ksz_desc_info *info = &hw->tx_desc_info; 4648 struct ksz_dma_buf *dma_buf; 4649 int len; 4650 int last_frag = skb_shinfo(skb)->nr_frags; 4651 4652 /* 4653 * KSZ8842 with multiple device interfaces needs to be told which port 4654 * to send. 4655 */ 4656 if (hw->dev_count > 1) 4657 hw->dst_ports = 1 << priv->port.first_port; 4658 4659 /* Hardware will pad the length to 60. */ 4660 len = skb->len; 4661 4662 /* Remember the very first descriptor. */ 4663 first = info->cur; 4664 desc = first; 4665 4666 dma_buf = DMA_BUFFER(desc); 4667 if (last_frag) { 4668 int frag; 4669 skb_frag_t *this_frag; 4670 4671 dma_buf->len = skb_headlen(skb); 4672 4673 dma_buf->dma = pci_map_single( 4674 hw_priv->pdev, skb->data, dma_buf->len, 4675 PCI_DMA_TODEVICE); 4676 set_tx_buf(desc, dma_buf->dma); 4677 set_tx_len(desc, dma_buf->len); 4678 4679 frag = 0; 4680 do { 4681 this_frag = &skb_shinfo(skb)->frags[frag]; 4682 4683 /* Get a new descriptor. */ 4684 get_tx_pkt(info, &desc); 4685 4686 /* Keep track of descriptors used so far. */ 4687 ++hw->tx_int_cnt; 4688 4689 dma_buf = DMA_BUFFER(desc); 4690 dma_buf->len = skb_frag_size(this_frag); 4691 4692 dma_buf->dma = pci_map_single( 4693 hw_priv->pdev, 4694 skb_frag_address(this_frag), 4695 dma_buf->len, 4696 PCI_DMA_TODEVICE); 4697 set_tx_buf(desc, dma_buf->dma); 4698 set_tx_len(desc, dma_buf->len); 4699 4700 frag++; 4701 if (frag == last_frag) 4702 break; 4703 4704 /* Do not release the last descriptor here. */ 4705 release_desc(desc); 4706 } while (1); 4707 4708 /* current points to the last descriptor. */ 4709 info->cur = desc; 4710 4711 /* Release the first descriptor. */ 4712 release_desc(first); 4713 } else { 4714 dma_buf->len = len; 4715 4716 dma_buf->dma = pci_map_single( 4717 hw_priv->pdev, skb->data, dma_buf->len, 4718 PCI_DMA_TODEVICE); 4719 set_tx_buf(desc, dma_buf->dma); 4720 set_tx_len(desc, dma_buf->len); 4721 } 4722 4723 if (skb->ip_summed == CHECKSUM_PARTIAL) { 4724 (desc)->sw.buf.tx.csum_gen_tcp = 1; 4725 (desc)->sw.buf.tx.csum_gen_udp = 1; 4726 } 4727 4728 /* 4729 * The last descriptor holds the packet so that it can be returned to 4730 * network subsystem after all descriptors are transmitted. 4731 */ 4732 dma_buf->skb = skb; 4733 4734 hw_send_pkt(hw); 4735 4736 /* Update transmit statistics. */ 4737 dev->stats.tx_packets++; 4738 dev->stats.tx_bytes += len; 4739 } 4740 4741 /** 4742 * transmit_cleanup - clean up transmit descriptors 4743 * @dev: Network device. 4744 * 4745 * This routine is called to clean up the transmitted buffers. 4746 */ 4747 static void transmit_cleanup(struct dev_info *hw_priv, int normal) 4748 { 4749 int last; 4750 union desc_stat status; 4751 struct ksz_hw *hw = &hw_priv->hw; 4752 struct ksz_desc_info *info = &hw->tx_desc_info; 4753 struct ksz_desc *desc; 4754 struct ksz_dma_buf *dma_buf; 4755 struct net_device *dev = NULL; 4756 4757 spin_lock_irq(&hw_priv->hwlock); 4758 last = info->last; 4759 4760 while (info->avail < info->alloc) { 4761 /* Get next descriptor which is not hardware owned. */ 4762 desc = &info->ring[last]; 4763 status.data = le32_to_cpu(desc->phw->ctrl.data); 4764 if (status.tx.hw_owned) { 4765 if (normal) 4766 break; 4767 else 4768 reset_desc(desc, status); 4769 } 4770 4771 dma_buf = DMA_BUFFER(desc); 4772 pci_unmap_single( 4773 hw_priv->pdev, dma_buf->dma, dma_buf->len, 4774 PCI_DMA_TODEVICE); 4775 4776 /* This descriptor contains the last buffer in the packet. */ 4777 if (dma_buf->skb) { 4778 dev = dma_buf->skb->dev; 4779 4780 /* Release the packet back to network subsystem. */ 4781 dev_kfree_skb_irq(dma_buf->skb); 4782 dma_buf->skb = NULL; 4783 } 4784 4785 /* Free the transmitted descriptor. */ 4786 last++; 4787 last &= info->mask; 4788 info->avail++; 4789 } 4790 info->last = last; 4791 spin_unlock_irq(&hw_priv->hwlock); 4792 4793 /* Notify the network subsystem that the packet has been sent. */ 4794 if (dev) 4795 dev->trans_start = jiffies; 4796 } 4797 4798 /** 4799 * transmit_done - transmit done processing 4800 * @dev: Network device. 4801 * 4802 * This routine is called when the transmit interrupt is triggered, indicating 4803 * either a packet is sent successfully or there are transmit errors. 4804 */ 4805 static void tx_done(struct dev_info *hw_priv) 4806 { 4807 struct ksz_hw *hw = &hw_priv->hw; 4808 int port; 4809 4810 transmit_cleanup(hw_priv, 1); 4811 4812 for (port = 0; port < hw->dev_count; port++) { 4813 struct net_device *dev = hw->port_info[port].pdev; 4814 4815 if (netif_running(dev) && netif_queue_stopped(dev)) 4816 netif_wake_queue(dev); 4817 } 4818 } 4819 4820 static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb) 4821 { 4822 skb->dev = old->dev; 4823 skb->protocol = old->protocol; 4824 skb->ip_summed = old->ip_summed; 4825 skb->csum = old->csum; 4826 skb_set_network_header(skb, ETH_HLEN); 4827 4828 dev_consume_skb_any(old); 4829 } 4830 4831 /** 4832 * netdev_tx - send out packet 4833 * @skb: Socket buffer. 4834 * @dev: Network device. 4835 * 4836 * This function is used by the upper network layer to send out a packet. 4837 * 4838 * Return 0 if successful; otherwise an error code indicating failure. 4839 */ 4840 static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev) 4841 { 4842 struct dev_priv *priv = netdev_priv(dev); 4843 struct dev_info *hw_priv = priv->adapter; 4844 struct ksz_hw *hw = &hw_priv->hw; 4845 int left; 4846 int num = 1; 4847 int rc = 0; 4848 4849 if (hw->features & SMALL_PACKET_TX_BUG) { 4850 struct sk_buff *org_skb = skb; 4851 4852 if (skb->len <= 48) { 4853 if (skb_end_pointer(skb) - skb->data >= 50) { 4854 memset(&skb->data[skb->len], 0, 50 - skb->len); 4855 skb->len = 50; 4856 } else { 4857 skb = netdev_alloc_skb(dev, 50); 4858 if (!skb) 4859 return NETDEV_TX_BUSY; 4860 memcpy(skb->data, org_skb->data, org_skb->len); 4861 memset(&skb->data[org_skb->len], 0, 4862 50 - org_skb->len); 4863 skb->len = 50; 4864 copy_old_skb(org_skb, skb); 4865 } 4866 } 4867 } 4868 4869 spin_lock_irq(&hw_priv->hwlock); 4870 4871 num = skb_shinfo(skb)->nr_frags + 1; 4872 left = hw_alloc_pkt(hw, skb->len, num); 4873 if (left) { 4874 if (left < num || 4875 (CHECKSUM_PARTIAL == skb->ip_summed && 4876 skb->protocol == htons(ETH_P_IPV6))) { 4877 struct sk_buff *org_skb = skb; 4878 4879 skb = netdev_alloc_skb(dev, org_skb->len); 4880 if (!skb) { 4881 rc = NETDEV_TX_BUSY; 4882 goto unlock; 4883 } 4884 skb_copy_and_csum_dev(org_skb, skb->data); 4885 org_skb->ip_summed = CHECKSUM_NONE; 4886 skb->len = org_skb->len; 4887 copy_old_skb(org_skb, skb); 4888 } 4889 send_packet(skb, dev); 4890 if (left <= num) 4891 netif_stop_queue(dev); 4892 } else { 4893 /* Stop the transmit queue until packet is allocated. */ 4894 netif_stop_queue(dev); 4895 rc = NETDEV_TX_BUSY; 4896 } 4897 unlock: 4898 spin_unlock_irq(&hw_priv->hwlock); 4899 4900 return rc; 4901 } 4902 4903 /** 4904 * netdev_tx_timeout - transmit timeout processing 4905 * @dev: Network device. 4906 * 4907 * This routine is called when the transmit timer expires. That indicates the 4908 * hardware is not running correctly because transmit interrupts are not 4909 * triggered to free up resources so that the transmit routine can continue 4910 * sending out packets. The hardware is reset to correct the problem. 4911 */ 4912 static void netdev_tx_timeout(struct net_device *dev) 4913 { 4914 static unsigned long last_reset; 4915 4916 struct dev_priv *priv = netdev_priv(dev); 4917 struct dev_info *hw_priv = priv->adapter; 4918 struct ksz_hw *hw = &hw_priv->hw; 4919 int port; 4920 4921 if (hw->dev_count > 1) { 4922 /* 4923 * Only reset the hardware if time between calls is long 4924 * enough. 4925 */ 4926 if (time_before_eq(jiffies, last_reset + dev->watchdog_timeo)) 4927 hw_priv = NULL; 4928 } 4929 4930 last_reset = jiffies; 4931 if (hw_priv) { 4932 hw_dis_intr(hw); 4933 hw_disable(hw); 4934 4935 transmit_cleanup(hw_priv, 0); 4936 hw_reset_pkts(&hw->rx_desc_info); 4937 hw_reset_pkts(&hw->tx_desc_info); 4938 ksz_init_rx_buffers(hw_priv); 4939 4940 hw_reset(hw); 4941 4942 hw_set_desc_base(hw, 4943 hw->tx_desc_info.ring_phys, 4944 hw->rx_desc_info.ring_phys); 4945 hw_set_addr(hw); 4946 if (hw->all_multi) 4947 hw_set_multicast(hw, hw->all_multi); 4948 else if (hw->multi_list_size) 4949 hw_set_grp_addr(hw); 4950 4951 if (hw->dev_count > 1) { 4952 hw_set_add_addr(hw); 4953 for (port = 0; port < SWITCH_PORT_NUM; port++) { 4954 struct net_device *port_dev; 4955 4956 port_set_stp_state(hw, port, 4957 STP_STATE_DISABLED); 4958 4959 port_dev = hw->port_info[port].pdev; 4960 if (netif_running(port_dev)) 4961 port_set_stp_state(hw, port, 4962 STP_STATE_SIMPLE); 4963 } 4964 } 4965 4966 hw_enable(hw); 4967 hw_ena_intr(hw); 4968 } 4969 4970 dev->trans_start = jiffies; 4971 netif_wake_queue(dev); 4972 } 4973 4974 static inline void csum_verified(struct sk_buff *skb) 4975 { 4976 unsigned short protocol; 4977 struct iphdr *iph; 4978 4979 protocol = skb->protocol; 4980 skb_reset_network_header(skb); 4981 iph = (struct iphdr *) skb_network_header(skb); 4982 if (protocol == htons(ETH_P_8021Q)) { 4983 protocol = iph->tot_len; 4984 skb_set_network_header(skb, VLAN_HLEN); 4985 iph = (struct iphdr *) skb_network_header(skb); 4986 } 4987 if (protocol == htons(ETH_P_IP)) { 4988 if (iph->protocol == IPPROTO_TCP) 4989 skb->ip_summed = CHECKSUM_UNNECESSARY; 4990 } 4991 } 4992 4993 static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw, 4994 struct ksz_desc *desc, union desc_stat status) 4995 { 4996 int packet_len; 4997 struct dev_priv *priv = netdev_priv(dev); 4998 struct dev_info *hw_priv = priv->adapter; 4999 struct ksz_dma_buf *dma_buf; 5000 struct sk_buff *skb; 5001 int rx_status; 5002 5003 /* Received length includes 4-byte CRC. */ 5004 packet_len = status.rx.frame_len - 4; 5005 5006 dma_buf = DMA_BUFFER(desc); 5007 pci_dma_sync_single_for_cpu( 5008 hw_priv->pdev, dma_buf->dma, packet_len + 4, 5009 PCI_DMA_FROMDEVICE); 5010 5011 do { 5012 /* skb->data != skb->head */ 5013 skb = netdev_alloc_skb(dev, packet_len + 2); 5014 if (!skb) { 5015 dev->stats.rx_dropped++; 5016 return -ENOMEM; 5017 } 5018 5019 /* 5020 * Align socket buffer in 4-byte boundary for better 5021 * performance. 5022 */ 5023 skb_reserve(skb, 2); 5024 5025 memcpy(skb_put(skb, packet_len), 5026 dma_buf->skb->data, packet_len); 5027 } while (0); 5028 5029 skb->protocol = eth_type_trans(skb, dev); 5030 5031 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP)) 5032 csum_verified(skb); 5033 5034 /* Update receive statistics. */ 5035 dev->stats.rx_packets++; 5036 dev->stats.rx_bytes += packet_len; 5037 5038 /* Notify upper layer for received packet. */ 5039 rx_status = netif_rx(skb); 5040 5041 return 0; 5042 } 5043 5044 static int dev_rcv_packets(struct dev_info *hw_priv) 5045 { 5046 int next; 5047 union desc_stat status; 5048 struct ksz_hw *hw = &hw_priv->hw; 5049 struct net_device *dev = hw->port_info[0].pdev; 5050 struct ksz_desc_info *info = &hw->rx_desc_info; 5051 int left = info->alloc; 5052 struct ksz_desc *desc; 5053 int received = 0; 5054 5055 next = info->next; 5056 while (left--) { 5057 /* Get next descriptor which is not hardware owned. */ 5058 desc = &info->ring[next]; 5059 status.data = le32_to_cpu(desc->phw->ctrl.data); 5060 if (status.rx.hw_owned) 5061 break; 5062 5063 /* Status valid only when last descriptor bit is set. */ 5064 if (status.rx.last_desc && status.rx.first_desc) { 5065 if (rx_proc(dev, hw, desc, status)) 5066 goto release_packet; 5067 received++; 5068 } 5069 5070 release_packet: 5071 release_desc(desc); 5072 next++; 5073 next &= info->mask; 5074 } 5075 info->next = next; 5076 5077 return received; 5078 } 5079 5080 static int port_rcv_packets(struct dev_info *hw_priv) 5081 { 5082 int next; 5083 union desc_stat status; 5084 struct ksz_hw *hw = &hw_priv->hw; 5085 struct net_device *dev = hw->port_info[0].pdev; 5086 struct ksz_desc_info *info = &hw->rx_desc_info; 5087 int left = info->alloc; 5088 struct ksz_desc *desc; 5089 int received = 0; 5090 5091 next = info->next; 5092 while (left--) { 5093 /* Get next descriptor which is not hardware owned. */ 5094 desc = &info->ring[next]; 5095 status.data = le32_to_cpu(desc->phw->ctrl.data); 5096 if (status.rx.hw_owned) 5097 break; 5098 5099 if (hw->dev_count > 1) { 5100 /* Get received port number. */ 5101 int p = HW_TO_DEV_PORT(status.rx.src_port); 5102 5103 dev = hw->port_info[p].pdev; 5104 if (!netif_running(dev)) 5105 goto release_packet; 5106 } 5107 5108 /* Status valid only when last descriptor bit is set. */ 5109 if (status.rx.last_desc && status.rx.first_desc) { 5110 if (rx_proc(dev, hw, desc, status)) 5111 goto release_packet; 5112 received++; 5113 } 5114 5115 release_packet: 5116 release_desc(desc); 5117 next++; 5118 next &= info->mask; 5119 } 5120 info->next = next; 5121 5122 return received; 5123 } 5124 5125 static int dev_rcv_special(struct dev_info *hw_priv) 5126 { 5127 int next; 5128 union desc_stat status; 5129 struct ksz_hw *hw = &hw_priv->hw; 5130 struct net_device *dev = hw->port_info[0].pdev; 5131 struct ksz_desc_info *info = &hw->rx_desc_info; 5132 int left = info->alloc; 5133 struct ksz_desc *desc; 5134 int received = 0; 5135 5136 next = info->next; 5137 while (left--) { 5138 /* Get next descriptor which is not hardware owned. */ 5139 desc = &info->ring[next]; 5140 status.data = le32_to_cpu(desc->phw->ctrl.data); 5141 if (status.rx.hw_owned) 5142 break; 5143 5144 if (hw->dev_count > 1) { 5145 /* Get received port number. */ 5146 int p = HW_TO_DEV_PORT(status.rx.src_port); 5147 5148 dev = hw->port_info[p].pdev; 5149 if (!netif_running(dev)) 5150 goto release_packet; 5151 } 5152 5153 /* Status valid only when last descriptor bit is set. */ 5154 if (status.rx.last_desc && status.rx.first_desc) { 5155 /* 5156 * Receive without error. With receive errors 5157 * disabled, packets with receive errors will be 5158 * dropped, so no need to check the error bit. 5159 */ 5160 if (!status.rx.error || (status.data & 5161 KS_DESC_RX_ERROR_COND) == 5162 KS_DESC_RX_ERROR_TOO_LONG) { 5163 if (rx_proc(dev, hw, desc, status)) 5164 goto release_packet; 5165 received++; 5166 } else { 5167 struct dev_priv *priv = netdev_priv(dev); 5168 5169 /* Update receive error statistics. */ 5170 priv->port.counter[OID_COUNTER_RCV_ERROR]++; 5171 } 5172 } 5173 5174 release_packet: 5175 release_desc(desc); 5176 next++; 5177 next &= info->mask; 5178 } 5179 info->next = next; 5180 5181 return received; 5182 } 5183 5184 static void rx_proc_task(unsigned long data) 5185 { 5186 struct dev_info *hw_priv = (struct dev_info *) data; 5187 struct ksz_hw *hw = &hw_priv->hw; 5188 5189 if (!hw->enabled) 5190 return; 5191 if (unlikely(!hw_priv->dev_rcv(hw_priv))) { 5192 5193 /* In case receive process is suspended because of overrun. */ 5194 hw_resume_rx(hw); 5195 5196 /* tasklets are interruptible. */ 5197 spin_lock_irq(&hw_priv->hwlock); 5198 hw_turn_on_intr(hw, KS884X_INT_RX_MASK); 5199 spin_unlock_irq(&hw_priv->hwlock); 5200 } else { 5201 hw_ack_intr(hw, KS884X_INT_RX); 5202 tasklet_schedule(&hw_priv->rx_tasklet); 5203 } 5204 } 5205 5206 static void tx_proc_task(unsigned long data) 5207 { 5208 struct dev_info *hw_priv = (struct dev_info *) data; 5209 struct ksz_hw *hw = &hw_priv->hw; 5210 5211 hw_ack_intr(hw, KS884X_INT_TX_MASK); 5212 5213 tx_done(hw_priv); 5214 5215 /* tasklets are interruptible. */ 5216 spin_lock_irq(&hw_priv->hwlock); 5217 hw_turn_on_intr(hw, KS884X_INT_TX); 5218 spin_unlock_irq(&hw_priv->hwlock); 5219 } 5220 5221 static inline void handle_rx_stop(struct ksz_hw *hw) 5222 { 5223 /* Receive just has been stopped. */ 5224 if (0 == hw->rx_stop) 5225 hw->intr_mask &= ~KS884X_INT_RX_STOPPED; 5226 else if (hw->rx_stop > 1) { 5227 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) { 5228 hw_start_rx(hw); 5229 } else { 5230 hw->intr_mask &= ~KS884X_INT_RX_STOPPED; 5231 hw->rx_stop = 0; 5232 } 5233 } else 5234 /* Receive just has been started. */ 5235 hw->rx_stop++; 5236 } 5237 5238 /** 5239 * netdev_intr - interrupt handling 5240 * @irq: Interrupt number. 5241 * @dev_id: Network device. 5242 * 5243 * This function is called by upper network layer to signal interrupt. 5244 * 5245 * Return IRQ_HANDLED if interrupt is handled. 5246 */ 5247 static irqreturn_t netdev_intr(int irq, void *dev_id) 5248 { 5249 uint int_enable = 0; 5250 struct net_device *dev = (struct net_device *) dev_id; 5251 struct dev_priv *priv = netdev_priv(dev); 5252 struct dev_info *hw_priv = priv->adapter; 5253 struct ksz_hw *hw = &hw_priv->hw; 5254 5255 spin_lock(&hw_priv->hwlock); 5256 5257 hw_read_intr(hw, &int_enable); 5258 5259 /* Not our interrupt! */ 5260 if (!int_enable) { 5261 spin_unlock(&hw_priv->hwlock); 5262 return IRQ_NONE; 5263 } 5264 5265 do { 5266 hw_ack_intr(hw, int_enable); 5267 int_enable &= hw->intr_mask; 5268 5269 if (unlikely(int_enable & KS884X_INT_TX_MASK)) { 5270 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK); 5271 tasklet_schedule(&hw_priv->tx_tasklet); 5272 } 5273 5274 if (likely(int_enable & KS884X_INT_RX)) { 5275 hw_dis_intr_bit(hw, KS884X_INT_RX); 5276 tasklet_schedule(&hw_priv->rx_tasklet); 5277 } 5278 5279 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) { 5280 dev->stats.rx_fifo_errors++; 5281 hw_resume_rx(hw); 5282 } 5283 5284 if (unlikely(int_enable & KS884X_INT_PHY)) { 5285 struct ksz_port *port = &priv->port; 5286 5287 hw->features |= LINK_INT_WORKING; 5288 port_get_link_speed(port); 5289 } 5290 5291 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) { 5292 handle_rx_stop(hw); 5293 break; 5294 } 5295 5296 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) { 5297 u32 data; 5298 5299 hw->intr_mask &= ~KS884X_INT_TX_STOPPED; 5300 pr_info("Tx stopped\n"); 5301 data = readl(hw->io + KS_DMA_TX_CTRL); 5302 if (!(data & DMA_TX_ENABLE)) 5303 pr_info("Tx disabled\n"); 5304 break; 5305 } 5306 } while (0); 5307 5308 hw_ena_intr(hw); 5309 5310 spin_unlock(&hw_priv->hwlock); 5311 5312 return IRQ_HANDLED; 5313 } 5314 5315 /* 5316 * Linux network device functions 5317 */ 5318 5319 static unsigned long next_jiffies; 5320 5321 #ifdef CONFIG_NET_POLL_CONTROLLER 5322 static void netdev_netpoll(struct net_device *dev) 5323 { 5324 struct dev_priv *priv = netdev_priv(dev); 5325 struct dev_info *hw_priv = priv->adapter; 5326 5327 hw_dis_intr(&hw_priv->hw); 5328 netdev_intr(dev->irq, dev); 5329 } 5330 #endif 5331 5332 static void bridge_change(struct ksz_hw *hw) 5333 { 5334 int port; 5335 u8 member; 5336 struct ksz_switch *sw = hw->ksz_switch; 5337 5338 /* No ports in forwarding state. */ 5339 if (!sw->member) { 5340 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); 5341 sw_block_addr(hw); 5342 } 5343 for (port = 0; port < SWITCH_PORT_NUM; port++) { 5344 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state) 5345 member = HOST_MASK | sw->member; 5346 else 5347 member = HOST_MASK | (1 << port); 5348 if (member != sw->port_cfg[port].member) 5349 sw_cfg_port_base_vlan(hw, port, member); 5350 } 5351 } 5352 5353 /** 5354 * netdev_close - close network device 5355 * @dev: Network device. 5356 * 5357 * This function process the close operation of network device. This is caused 5358 * by the user command "ifconfig ethX down." 5359 * 5360 * Return 0 if successful; otherwise an error code indicating failure. 5361 */ 5362 static int netdev_close(struct net_device *dev) 5363 { 5364 struct dev_priv *priv = netdev_priv(dev); 5365 struct dev_info *hw_priv = priv->adapter; 5366 struct ksz_port *port = &priv->port; 5367 struct ksz_hw *hw = &hw_priv->hw; 5368 int pi; 5369 5370 netif_stop_queue(dev); 5371 5372 ksz_stop_timer(&priv->monitor_timer_info); 5373 5374 /* Need to shut the port manually in multiple device interfaces mode. */ 5375 if (hw->dev_count > 1) { 5376 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED); 5377 5378 /* Port is closed. Need to change bridge setting. */ 5379 if (hw->features & STP_SUPPORT) { 5380 pi = 1 << port->first_port; 5381 if (hw->ksz_switch->member & pi) { 5382 hw->ksz_switch->member &= ~pi; 5383 bridge_change(hw); 5384 } 5385 } 5386 } 5387 if (port->first_port > 0) 5388 hw_del_addr(hw, dev->dev_addr); 5389 if (!hw_priv->wol_enable) 5390 port_set_power_saving(port, true); 5391 5392 if (priv->multicast) 5393 --hw->all_multi; 5394 if (priv->promiscuous) 5395 --hw->promiscuous; 5396 5397 hw_priv->opened--; 5398 if (!(hw_priv->opened)) { 5399 ksz_stop_timer(&hw_priv->mib_timer_info); 5400 flush_work(&hw_priv->mib_read); 5401 5402 hw_dis_intr(hw); 5403 hw_disable(hw); 5404 hw_clr_multicast(hw); 5405 5406 /* Delay for receive task to stop scheduling itself. */ 5407 msleep(2000 / HZ); 5408 5409 tasklet_kill(&hw_priv->rx_tasklet); 5410 tasklet_kill(&hw_priv->tx_tasklet); 5411 free_irq(dev->irq, hw_priv->dev); 5412 5413 transmit_cleanup(hw_priv, 0); 5414 hw_reset_pkts(&hw->rx_desc_info); 5415 hw_reset_pkts(&hw->tx_desc_info); 5416 5417 /* Clean out static MAC table when the switch is shutdown. */ 5418 if (hw->features & STP_SUPPORT) 5419 sw_clr_sta_mac_table(hw); 5420 } 5421 5422 return 0; 5423 } 5424 5425 static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw) 5426 { 5427 if (hw->ksz_switch) { 5428 u32 data; 5429 5430 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); 5431 if (hw->features & RX_HUGE_FRAME) 5432 data |= SWITCH_HUGE_PACKET; 5433 else 5434 data &= ~SWITCH_HUGE_PACKET; 5435 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); 5436 } 5437 if (hw->features & RX_HUGE_FRAME) { 5438 hw->rx_cfg |= DMA_RX_ERROR; 5439 hw_priv->dev_rcv = dev_rcv_special; 5440 } else { 5441 hw->rx_cfg &= ~DMA_RX_ERROR; 5442 if (hw->dev_count > 1) 5443 hw_priv->dev_rcv = port_rcv_packets; 5444 else 5445 hw_priv->dev_rcv = dev_rcv_packets; 5446 } 5447 } 5448 5449 static int prepare_hardware(struct net_device *dev) 5450 { 5451 struct dev_priv *priv = netdev_priv(dev); 5452 struct dev_info *hw_priv = priv->adapter; 5453 struct ksz_hw *hw = &hw_priv->hw; 5454 int rc = 0; 5455 5456 /* Remember the network device that requests interrupts. */ 5457 hw_priv->dev = dev; 5458 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev); 5459 if (rc) 5460 return rc; 5461 tasklet_init(&hw_priv->rx_tasklet, rx_proc_task, 5462 (unsigned long) hw_priv); 5463 tasklet_init(&hw_priv->tx_tasklet, tx_proc_task, 5464 (unsigned long) hw_priv); 5465 5466 hw->promiscuous = 0; 5467 hw->all_multi = 0; 5468 hw->multi_list_size = 0; 5469 5470 hw_reset(hw); 5471 5472 hw_set_desc_base(hw, 5473 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys); 5474 hw_set_addr(hw); 5475 hw_cfg_huge_frame(hw_priv, hw); 5476 ksz_init_rx_buffers(hw_priv); 5477 return 0; 5478 } 5479 5480 static void set_media_state(struct net_device *dev, int media_state) 5481 { 5482 struct dev_priv *priv = netdev_priv(dev); 5483 5484 if (media_state == priv->media_state) 5485 netif_carrier_on(dev); 5486 else 5487 netif_carrier_off(dev); 5488 netif_info(priv, link, dev, "link %s\n", 5489 media_state == priv->media_state ? "on" : "off"); 5490 } 5491 5492 /** 5493 * netdev_open - open network device 5494 * @dev: Network device. 5495 * 5496 * This function process the open operation of network device. This is caused 5497 * by the user command "ifconfig ethX up." 5498 * 5499 * Return 0 if successful; otherwise an error code indicating failure. 5500 */ 5501 static int netdev_open(struct net_device *dev) 5502 { 5503 struct dev_priv *priv = netdev_priv(dev); 5504 struct dev_info *hw_priv = priv->adapter; 5505 struct ksz_hw *hw = &hw_priv->hw; 5506 struct ksz_port *port = &priv->port; 5507 int i; 5508 int p; 5509 int rc = 0; 5510 5511 priv->multicast = 0; 5512 priv->promiscuous = 0; 5513 5514 /* Reset device statistics. */ 5515 memset(&dev->stats, 0, sizeof(struct net_device_stats)); 5516 memset((void *) port->counter, 0, 5517 (sizeof(u64) * OID_COUNTER_LAST)); 5518 5519 if (!(hw_priv->opened)) { 5520 rc = prepare_hardware(dev); 5521 if (rc) 5522 return rc; 5523 for (i = 0; i < hw->mib_port_cnt; i++) { 5524 if (next_jiffies < jiffies) 5525 next_jiffies = jiffies + HZ * 2; 5526 else 5527 next_jiffies += HZ * 1; 5528 hw_priv->counter[i].time = next_jiffies; 5529 hw->port_mib[i].state = media_disconnected; 5530 port_init_cnt(hw, i); 5531 } 5532 if (hw->ksz_switch) 5533 hw->port_mib[HOST_PORT].state = media_connected; 5534 else { 5535 hw_add_wol_bcast(hw); 5536 hw_cfg_wol_pme(hw, 0); 5537 hw_clr_wol_pme_status(&hw_priv->hw); 5538 } 5539 } 5540 port_set_power_saving(port, false); 5541 5542 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { 5543 /* 5544 * Initialize to invalid value so that link detection 5545 * is done. 5546 */ 5547 hw->port_info[p].partner = 0xFF; 5548 hw->port_info[p].state = media_disconnected; 5549 } 5550 5551 /* Need to open the port in multiple device interfaces mode. */ 5552 if (hw->dev_count > 1) { 5553 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE); 5554 if (port->first_port > 0) 5555 hw_add_addr(hw, dev->dev_addr); 5556 } 5557 5558 port_get_link_speed(port); 5559 if (port->force_link) 5560 port_force_link_speed(port); 5561 else 5562 port_set_link_speed(port); 5563 5564 if (!(hw_priv->opened)) { 5565 hw_setup_intr(hw); 5566 hw_enable(hw); 5567 hw_ena_intr(hw); 5568 5569 if (hw->mib_port_cnt) 5570 ksz_start_timer(&hw_priv->mib_timer_info, 5571 hw_priv->mib_timer_info.period); 5572 } 5573 5574 hw_priv->opened++; 5575 5576 ksz_start_timer(&priv->monitor_timer_info, 5577 priv->monitor_timer_info.period); 5578 5579 priv->media_state = port->linked->state; 5580 5581 set_media_state(dev, media_connected); 5582 netif_start_queue(dev); 5583 5584 return 0; 5585 } 5586 5587 /* RX errors = rx_errors */ 5588 /* RX dropped = rx_dropped */ 5589 /* RX overruns = rx_fifo_errors */ 5590 /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */ 5591 /* TX errors = tx_errors */ 5592 /* TX dropped = tx_dropped */ 5593 /* TX overruns = tx_fifo_errors */ 5594 /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */ 5595 /* collisions = collisions */ 5596 5597 /** 5598 * netdev_query_statistics - query network device statistics 5599 * @dev: Network device. 5600 * 5601 * This function returns the statistics of the network device. The device 5602 * needs not be opened. 5603 * 5604 * Return network device statistics. 5605 */ 5606 static struct net_device_stats *netdev_query_statistics(struct net_device *dev) 5607 { 5608 struct dev_priv *priv = netdev_priv(dev); 5609 struct ksz_port *port = &priv->port; 5610 struct ksz_hw *hw = &priv->adapter->hw; 5611 struct ksz_port_mib *mib; 5612 int i; 5613 int p; 5614 5615 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR]; 5616 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR]; 5617 5618 /* Reset to zero to add count later. */ 5619 dev->stats.multicast = 0; 5620 dev->stats.collisions = 0; 5621 dev->stats.rx_length_errors = 0; 5622 dev->stats.rx_crc_errors = 0; 5623 dev->stats.rx_frame_errors = 0; 5624 dev->stats.tx_window_errors = 0; 5625 5626 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { 5627 mib = &hw->port_mib[p]; 5628 5629 dev->stats.multicast += (unsigned long) 5630 mib->counter[MIB_COUNTER_RX_MULTICAST]; 5631 5632 dev->stats.collisions += (unsigned long) 5633 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION]; 5634 5635 dev->stats.rx_length_errors += (unsigned long)( 5636 mib->counter[MIB_COUNTER_RX_UNDERSIZE] + 5637 mib->counter[MIB_COUNTER_RX_FRAGMENT] + 5638 mib->counter[MIB_COUNTER_RX_OVERSIZE] + 5639 mib->counter[MIB_COUNTER_RX_JABBER]); 5640 dev->stats.rx_crc_errors += (unsigned long) 5641 mib->counter[MIB_COUNTER_RX_CRC_ERR]; 5642 dev->stats.rx_frame_errors += (unsigned long)( 5643 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] + 5644 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]); 5645 5646 dev->stats.tx_window_errors += (unsigned long) 5647 mib->counter[MIB_COUNTER_TX_LATE_COLLISION]; 5648 } 5649 5650 return &dev->stats; 5651 } 5652 5653 /** 5654 * netdev_set_mac_address - set network device MAC address 5655 * @dev: Network device. 5656 * @addr: Buffer of MAC address. 5657 * 5658 * This function is used to set the MAC address of the network device. 5659 * 5660 * Return 0 to indicate success. 5661 */ 5662 static int netdev_set_mac_address(struct net_device *dev, void *addr) 5663 { 5664 struct dev_priv *priv = netdev_priv(dev); 5665 struct dev_info *hw_priv = priv->adapter; 5666 struct ksz_hw *hw = &hw_priv->hw; 5667 struct sockaddr *mac = addr; 5668 uint interrupt; 5669 5670 if (priv->port.first_port > 0) 5671 hw_del_addr(hw, dev->dev_addr); 5672 else { 5673 hw->mac_override = 1; 5674 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN); 5675 } 5676 5677 memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN); 5678 5679 interrupt = hw_block_intr(hw); 5680 5681 if (priv->port.first_port > 0) 5682 hw_add_addr(hw, dev->dev_addr); 5683 else 5684 hw_set_addr(hw); 5685 hw_restore_intr(hw, interrupt); 5686 5687 return 0; 5688 } 5689 5690 static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv, 5691 struct ksz_hw *hw, int promiscuous) 5692 { 5693 if (promiscuous != priv->promiscuous) { 5694 u8 prev_state = hw->promiscuous; 5695 5696 if (promiscuous) 5697 ++hw->promiscuous; 5698 else 5699 --hw->promiscuous; 5700 priv->promiscuous = promiscuous; 5701 5702 /* Turn on/off promiscuous mode. */ 5703 if (hw->promiscuous <= 1 && prev_state <= 1) 5704 hw_set_promiscuous(hw, hw->promiscuous); 5705 5706 /* 5707 * Port is not in promiscuous mode, meaning it is released 5708 * from the bridge. 5709 */ 5710 if ((hw->features & STP_SUPPORT) && !promiscuous && 5711 (dev->priv_flags & IFF_BRIDGE_PORT)) { 5712 struct ksz_switch *sw = hw->ksz_switch; 5713 int port = priv->port.first_port; 5714 5715 port_set_stp_state(hw, port, STP_STATE_DISABLED); 5716 port = 1 << port; 5717 if (sw->member & port) { 5718 sw->member &= ~port; 5719 bridge_change(hw); 5720 } 5721 } 5722 } 5723 } 5724 5725 static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw, 5726 int multicast) 5727 { 5728 if (multicast != priv->multicast) { 5729 u8 all_multi = hw->all_multi; 5730 5731 if (multicast) 5732 ++hw->all_multi; 5733 else 5734 --hw->all_multi; 5735 priv->multicast = multicast; 5736 5737 /* Turn on/off all multicast mode. */ 5738 if (hw->all_multi <= 1 && all_multi <= 1) 5739 hw_set_multicast(hw, hw->all_multi); 5740 } 5741 } 5742 5743 /** 5744 * netdev_set_rx_mode 5745 * @dev: Network device. 5746 * 5747 * This routine is used to set multicast addresses or put the network device 5748 * into promiscuous mode. 5749 */ 5750 static void netdev_set_rx_mode(struct net_device *dev) 5751 { 5752 struct dev_priv *priv = netdev_priv(dev); 5753 struct dev_info *hw_priv = priv->adapter; 5754 struct ksz_hw *hw = &hw_priv->hw; 5755 struct netdev_hw_addr *ha; 5756 int multicast = (dev->flags & IFF_ALLMULTI); 5757 5758 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC)); 5759 5760 if (hw_priv->hw.dev_count > 1) 5761 multicast |= (dev->flags & IFF_MULTICAST); 5762 dev_set_multicast(priv, hw, multicast); 5763 5764 /* Cannot use different hashes in multiple device interfaces mode. */ 5765 if (hw_priv->hw.dev_count > 1) 5766 return; 5767 5768 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) { 5769 int i = 0; 5770 5771 /* List too big to support so turn on all multicast mode. */ 5772 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) { 5773 if (MAX_MULTICAST_LIST != hw->multi_list_size) { 5774 hw->multi_list_size = MAX_MULTICAST_LIST; 5775 ++hw->all_multi; 5776 hw_set_multicast(hw, hw->all_multi); 5777 } 5778 return; 5779 } 5780 5781 netdev_for_each_mc_addr(ha, dev) { 5782 if (i >= MAX_MULTICAST_LIST) 5783 break; 5784 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN); 5785 } 5786 hw->multi_list_size = (u8) i; 5787 hw_set_grp_addr(hw); 5788 } else { 5789 if (MAX_MULTICAST_LIST == hw->multi_list_size) { 5790 --hw->all_multi; 5791 hw_set_multicast(hw, hw->all_multi); 5792 } 5793 hw->multi_list_size = 0; 5794 hw_clr_multicast(hw); 5795 } 5796 } 5797 5798 static int netdev_change_mtu(struct net_device *dev, int new_mtu) 5799 { 5800 struct dev_priv *priv = netdev_priv(dev); 5801 struct dev_info *hw_priv = priv->adapter; 5802 struct ksz_hw *hw = &hw_priv->hw; 5803 int hw_mtu; 5804 5805 if (netif_running(dev)) 5806 return -EBUSY; 5807 5808 /* Cannot use different MTU in multiple device interfaces mode. */ 5809 if (hw->dev_count > 1) 5810 if (dev != hw_priv->dev) 5811 return 0; 5812 if (new_mtu < 60) 5813 return -EINVAL; 5814 5815 if (dev->mtu != new_mtu) { 5816 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4; 5817 if (hw_mtu > MAX_RX_BUF_SIZE) 5818 return -EINVAL; 5819 if (hw_mtu > REGULAR_RX_BUF_SIZE) { 5820 hw->features |= RX_HUGE_FRAME; 5821 hw_mtu = MAX_RX_BUF_SIZE; 5822 } else { 5823 hw->features &= ~RX_HUGE_FRAME; 5824 hw_mtu = REGULAR_RX_BUF_SIZE; 5825 } 5826 hw_mtu = (hw_mtu + 3) & ~3; 5827 hw_priv->mtu = hw_mtu; 5828 dev->mtu = new_mtu; 5829 } 5830 return 0; 5831 } 5832 5833 /** 5834 * netdev_ioctl - I/O control processing 5835 * @dev: Network device. 5836 * @ifr: Interface request structure. 5837 * @cmd: I/O control code. 5838 * 5839 * This function is used to process I/O control calls. 5840 * 5841 * Return 0 to indicate success. 5842 */ 5843 static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 5844 { 5845 struct dev_priv *priv = netdev_priv(dev); 5846 struct dev_info *hw_priv = priv->adapter; 5847 struct ksz_hw *hw = &hw_priv->hw; 5848 struct ksz_port *port = &priv->port; 5849 int result = 0; 5850 struct mii_ioctl_data *data = if_mii(ifr); 5851 5852 if (down_interruptible(&priv->proc_sem)) 5853 return -ERESTARTSYS; 5854 5855 switch (cmd) { 5856 /* Get address of MII PHY in use. */ 5857 case SIOCGMIIPHY: 5858 data->phy_id = priv->id; 5859 5860 /* Fallthrough... */ 5861 5862 /* Read MII PHY register. */ 5863 case SIOCGMIIREG: 5864 if (data->phy_id != priv->id || data->reg_num >= 6) 5865 result = -EIO; 5866 else 5867 hw_r_phy(hw, port->linked->port_id, data->reg_num, 5868 &data->val_out); 5869 break; 5870 5871 /* Write MII PHY register. */ 5872 case SIOCSMIIREG: 5873 if (!capable(CAP_NET_ADMIN)) 5874 result = -EPERM; 5875 else if (data->phy_id != priv->id || data->reg_num >= 6) 5876 result = -EIO; 5877 else 5878 hw_w_phy(hw, port->linked->port_id, data->reg_num, 5879 data->val_in); 5880 break; 5881 5882 default: 5883 result = -EOPNOTSUPP; 5884 } 5885 5886 up(&priv->proc_sem); 5887 5888 return result; 5889 } 5890 5891 /* 5892 * MII support 5893 */ 5894 5895 /** 5896 * mdio_read - read PHY register 5897 * @dev: Network device. 5898 * @phy_id: The PHY id. 5899 * @reg_num: The register number. 5900 * 5901 * This function returns the PHY register value. 5902 * 5903 * Return the register value. 5904 */ 5905 static int mdio_read(struct net_device *dev, int phy_id, int reg_num) 5906 { 5907 struct dev_priv *priv = netdev_priv(dev); 5908 struct ksz_port *port = &priv->port; 5909 struct ksz_hw *hw = port->hw; 5910 u16 val_out; 5911 5912 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out); 5913 return val_out; 5914 } 5915 5916 /** 5917 * mdio_write - set PHY register 5918 * @dev: Network device. 5919 * @phy_id: The PHY id. 5920 * @reg_num: The register number. 5921 * @val: The register value. 5922 * 5923 * This procedure sets the PHY register value. 5924 */ 5925 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) 5926 { 5927 struct dev_priv *priv = netdev_priv(dev); 5928 struct ksz_port *port = &priv->port; 5929 struct ksz_hw *hw = port->hw; 5930 int i; 5931 int pi; 5932 5933 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++) 5934 hw_w_phy(hw, pi, reg_num << 1, val); 5935 } 5936 5937 /* 5938 * ethtool support 5939 */ 5940 5941 #define EEPROM_SIZE 0x40 5942 5943 static u16 eeprom_data[EEPROM_SIZE] = { 0 }; 5944 5945 #define ADVERTISED_ALL \ 5946 (ADVERTISED_10baseT_Half | \ 5947 ADVERTISED_10baseT_Full | \ 5948 ADVERTISED_100baseT_Half | \ 5949 ADVERTISED_100baseT_Full) 5950 5951 /* These functions use the MII functions in mii.c. */ 5952 5953 /** 5954 * netdev_get_settings - get network device settings 5955 * @dev: Network device. 5956 * @cmd: Ethtool command. 5957 * 5958 * This function queries the PHY and returns its state in the ethtool command. 5959 * 5960 * Return 0 if successful; otherwise an error code. 5961 */ 5962 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 5963 { 5964 struct dev_priv *priv = netdev_priv(dev); 5965 struct dev_info *hw_priv = priv->adapter; 5966 5967 mutex_lock(&hw_priv->lock); 5968 mii_ethtool_gset(&priv->mii_if, cmd); 5969 cmd->advertising |= SUPPORTED_TP; 5970 mutex_unlock(&hw_priv->lock); 5971 5972 /* Save advertised settings for workaround in next function. */ 5973 priv->advertising = cmd->advertising; 5974 return 0; 5975 } 5976 5977 /** 5978 * netdev_set_settings - set network device settings 5979 * @dev: Network device. 5980 * @cmd: Ethtool command. 5981 * 5982 * This function sets the PHY according to the ethtool command. 5983 * 5984 * Return 0 if successful; otherwise an error code. 5985 */ 5986 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 5987 { 5988 struct dev_priv *priv = netdev_priv(dev); 5989 struct dev_info *hw_priv = priv->adapter; 5990 struct ksz_port *port = &priv->port; 5991 u32 speed = ethtool_cmd_speed(cmd); 5992 int rc; 5993 5994 /* 5995 * ethtool utility does not change advertised setting if auto 5996 * negotiation is not specified explicitly. 5997 */ 5998 if (cmd->autoneg && priv->advertising == cmd->advertising) { 5999 cmd->advertising |= ADVERTISED_ALL; 6000 if (10 == speed) 6001 cmd->advertising &= 6002 ~(ADVERTISED_100baseT_Full | 6003 ADVERTISED_100baseT_Half); 6004 else if (100 == speed) 6005 cmd->advertising &= 6006 ~(ADVERTISED_10baseT_Full | 6007 ADVERTISED_10baseT_Half); 6008 if (0 == cmd->duplex) 6009 cmd->advertising &= 6010 ~(ADVERTISED_100baseT_Full | 6011 ADVERTISED_10baseT_Full); 6012 else if (1 == cmd->duplex) 6013 cmd->advertising &= 6014 ~(ADVERTISED_100baseT_Half | 6015 ADVERTISED_10baseT_Half); 6016 } 6017 mutex_lock(&hw_priv->lock); 6018 if (cmd->autoneg && 6019 (cmd->advertising & ADVERTISED_ALL) == 6020 ADVERTISED_ALL) { 6021 port->duplex = 0; 6022 port->speed = 0; 6023 port->force_link = 0; 6024 } else { 6025 port->duplex = cmd->duplex + 1; 6026 if (1000 != speed) 6027 port->speed = speed; 6028 if (cmd->autoneg) 6029 port->force_link = 0; 6030 else 6031 port->force_link = 1; 6032 } 6033 rc = mii_ethtool_sset(&priv->mii_if, cmd); 6034 mutex_unlock(&hw_priv->lock); 6035 return rc; 6036 } 6037 6038 /** 6039 * netdev_nway_reset - restart auto-negotiation 6040 * @dev: Network device. 6041 * 6042 * This function restarts the PHY for auto-negotiation. 6043 * 6044 * Return 0 if successful; otherwise an error code. 6045 */ 6046 static int netdev_nway_reset(struct net_device *dev) 6047 { 6048 struct dev_priv *priv = netdev_priv(dev); 6049 struct dev_info *hw_priv = priv->adapter; 6050 int rc; 6051 6052 mutex_lock(&hw_priv->lock); 6053 rc = mii_nway_restart(&priv->mii_if); 6054 mutex_unlock(&hw_priv->lock); 6055 return rc; 6056 } 6057 6058 /** 6059 * netdev_get_link - get network device link status 6060 * @dev: Network device. 6061 * 6062 * This function gets the link status from the PHY. 6063 * 6064 * Return true if PHY is linked and false otherwise. 6065 */ 6066 static u32 netdev_get_link(struct net_device *dev) 6067 { 6068 struct dev_priv *priv = netdev_priv(dev); 6069 int rc; 6070 6071 rc = mii_link_ok(&priv->mii_if); 6072 return rc; 6073 } 6074 6075 /** 6076 * netdev_get_drvinfo - get network driver information 6077 * @dev: Network device. 6078 * @info: Ethtool driver info data structure. 6079 * 6080 * This procedure returns the driver information. 6081 */ 6082 static void netdev_get_drvinfo(struct net_device *dev, 6083 struct ethtool_drvinfo *info) 6084 { 6085 struct dev_priv *priv = netdev_priv(dev); 6086 struct dev_info *hw_priv = priv->adapter; 6087 6088 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 6089 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 6090 strlcpy(info->bus_info, pci_name(hw_priv->pdev), 6091 sizeof(info->bus_info)); 6092 } 6093 6094 /** 6095 * netdev_get_regs_len - get length of register dump 6096 * @dev: Network device. 6097 * 6098 * This function returns the length of the register dump. 6099 * 6100 * Return length of the register dump. 6101 */ 6102 static struct hw_regs { 6103 int start; 6104 int end; 6105 } hw_regs_range[] = { 6106 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS }, 6107 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI }, 6108 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET }, 6109 { KS884X_SIDER_P, KS8842_SGCR7_P }, 6110 { KS8842_MACAR1_P, KS8842_TOSR8_P }, 6111 { KS884X_P1MBCR_P, KS8842_P3ERCR_P }, 6112 { 0, 0 } 6113 }; 6114 6115 static int netdev_get_regs_len(struct net_device *dev) 6116 { 6117 struct hw_regs *range = hw_regs_range; 6118 int regs_len = 0x10 * sizeof(u32); 6119 6120 while (range->end > range->start) { 6121 regs_len += (range->end - range->start + 3) / 4 * 4; 6122 range++; 6123 } 6124 return regs_len; 6125 } 6126 6127 /** 6128 * netdev_get_regs - get register dump 6129 * @dev: Network device. 6130 * @regs: Ethtool registers data structure. 6131 * @ptr: Buffer to store the register values. 6132 * 6133 * This procedure dumps the register values in the provided buffer. 6134 */ 6135 static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs, 6136 void *ptr) 6137 { 6138 struct dev_priv *priv = netdev_priv(dev); 6139 struct dev_info *hw_priv = priv->adapter; 6140 struct ksz_hw *hw = &hw_priv->hw; 6141 int *buf = (int *) ptr; 6142 struct hw_regs *range = hw_regs_range; 6143 int len; 6144 6145 mutex_lock(&hw_priv->lock); 6146 regs->version = 0; 6147 for (len = 0; len < 0x40; len += 4) { 6148 pci_read_config_dword(hw_priv->pdev, len, buf); 6149 buf++; 6150 } 6151 while (range->end > range->start) { 6152 for (len = range->start; len < range->end; len += 4) { 6153 *buf = readl(hw->io + len); 6154 buf++; 6155 } 6156 range++; 6157 } 6158 mutex_unlock(&hw_priv->lock); 6159 } 6160 6161 #define WOL_SUPPORT \ 6162 (WAKE_PHY | WAKE_MAGIC | \ 6163 WAKE_UCAST | WAKE_MCAST | \ 6164 WAKE_BCAST | WAKE_ARP) 6165 6166 /** 6167 * netdev_get_wol - get Wake-on-LAN support 6168 * @dev: Network device. 6169 * @wol: Ethtool Wake-on-LAN data structure. 6170 * 6171 * This procedure returns Wake-on-LAN support. 6172 */ 6173 static void netdev_get_wol(struct net_device *dev, 6174 struct ethtool_wolinfo *wol) 6175 { 6176 struct dev_priv *priv = netdev_priv(dev); 6177 struct dev_info *hw_priv = priv->adapter; 6178 6179 wol->supported = hw_priv->wol_support; 6180 wol->wolopts = hw_priv->wol_enable; 6181 memset(&wol->sopass, 0, sizeof(wol->sopass)); 6182 } 6183 6184 /** 6185 * netdev_set_wol - set Wake-on-LAN support 6186 * @dev: Network device. 6187 * @wol: Ethtool Wake-on-LAN data structure. 6188 * 6189 * This function sets Wake-on-LAN support. 6190 * 6191 * Return 0 if successful; otherwise an error code. 6192 */ 6193 static int netdev_set_wol(struct net_device *dev, 6194 struct ethtool_wolinfo *wol) 6195 { 6196 struct dev_priv *priv = netdev_priv(dev); 6197 struct dev_info *hw_priv = priv->adapter; 6198 6199 /* Need to find a way to retrieve the device IP address. */ 6200 static const u8 net_addr[] = { 192, 168, 1, 1 }; 6201 6202 if (wol->wolopts & ~hw_priv->wol_support) 6203 return -EINVAL; 6204 6205 hw_priv->wol_enable = wol->wolopts; 6206 6207 /* Link wakeup cannot really be disabled. */ 6208 if (wol->wolopts) 6209 hw_priv->wol_enable |= WAKE_PHY; 6210 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr); 6211 return 0; 6212 } 6213 6214 /** 6215 * netdev_get_msglevel - get debug message level 6216 * @dev: Network device. 6217 * 6218 * This function returns current debug message level. 6219 * 6220 * Return current debug message flags. 6221 */ 6222 static u32 netdev_get_msglevel(struct net_device *dev) 6223 { 6224 struct dev_priv *priv = netdev_priv(dev); 6225 6226 return priv->msg_enable; 6227 } 6228 6229 /** 6230 * netdev_set_msglevel - set debug message level 6231 * @dev: Network device. 6232 * @value: Debug message flags. 6233 * 6234 * This procedure sets debug message level. 6235 */ 6236 static void netdev_set_msglevel(struct net_device *dev, u32 value) 6237 { 6238 struct dev_priv *priv = netdev_priv(dev); 6239 6240 priv->msg_enable = value; 6241 } 6242 6243 /** 6244 * netdev_get_eeprom_len - get EEPROM length 6245 * @dev: Network device. 6246 * 6247 * This function returns the length of the EEPROM. 6248 * 6249 * Return length of the EEPROM. 6250 */ 6251 static int netdev_get_eeprom_len(struct net_device *dev) 6252 { 6253 return EEPROM_SIZE * 2; 6254 } 6255 6256 /** 6257 * netdev_get_eeprom - get EEPROM data 6258 * @dev: Network device. 6259 * @eeprom: Ethtool EEPROM data structure. 6260 * @data: Buffer to store the EEPROM data. 6261 * 6262 * This function dumps the EEPROM data in the provided buffer. 6263 * 6264 * Return 0 if successful; otherwise an error code. 6265 */ 6266 #define EEPROM_MAGIC 0x10A18842 6267 6268 static int netdev_get_eeprom(struct net_device *dev, 6269 struct ethtool_eeprom *eeprom, u8 *data) 6270 { 6271 struct dev_priv *priv = netdev_priv(dev); 6272 struct dev_info *hw_priv = priv->adapter; 6273 u8 *eeprom_byte = (u8 *) eeprom_data; 6274 int i; 6275 int len; 6276 6277 len = (eeprom->offset + eeprom->len + 1) / 2; 6278 for (i = eeprom->offset / 2; i < len; i++) 6279 eeprom_data[i] = eeprom_read(&hw_priv->hw, i); 6280 eeprom->magic = EEPROM_MAGIC; 6281 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len); 6282 6283 return 0; 6284 } 6285 6286 /** 6287 * netdev_set_eeprom - write EEPROM data 6288 * @dev: Network device. 6289 * @eeprom: Ethtool EEPROM data structure. 6290 * @data: Data buffer. 6291 * 6292 * This function modifies the EEPROM data one byte at a time. 6293 * 6294 * Return 0 if successful; otherwise an error code. 6295 */ 6296 static int netdev_set_eeprom(struct net_device *dev, 6297 struct ethtool_eeprom *eeprom, u8 *data) 6298 { 6299 struct dev_priv *priv = netdev_priv(dev); 6300 struct dev_info *hw_priv = priv->adapter; 6301 u16 eeprom_word[EEPROM_SIZE]; 6302 u8 *eeprom_byte = (u8 *) eeprom_word; 6303 int i; 6304 int len; 6305 6306 if (eeprom->magic != EEPROM_MAGIC) 6307 return -EINVAL; 6308 6309 len = (eeprom->offset + eeprom->len + 1) / 2; 6310 for (i = eeprom->offset / 2; i < len; i++) 6311 eeprom_data[i] = eeprom_read(&hw_priv->hw, i); 6312 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2); 6313 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len); 6314 for (i = 0; i < EEPROM_SIZE; i++) 6315 if (eeprom_word[i] != eeprom_data[i]) { 6316 eeprom_data[i] = eeprom_word[i]; 6317 eeprom_write(&hw_priv->hw, i, eeprom_data[i]); 6318 } 6319 6320 return 0; 6321 } 6322 6323 /** 6324 * netdev_get_pauseparam - get flow control parameters 6325 * @dev: Network device. 6326 * @pause: Ethtool PAUSE settings data structure. 6327 * 6328 * This procedure returns the PAUSE control flow settings. 6329 */ 6330 static void netdev_get_pauseparam(struct net_device *dev, 6331 struct ethtool_pauseparam *pause) 6332 { 6333 struct dev_priv *priv = netdev_priv(dev); 6334 struct dev_info *hw_priv = priv->adapter; 6335 struct ksz_hw *hw = &hw_priv->hw; 6336 6337 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1; 6338 if (!hw->ksz_switch) { 6339 pause->rx_pause = 6340 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0; 6341 pause->tx_pause = 6342 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0; 6343 } else { 6344 pause->rx_pause = 6345 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, 6346 SWITCH_RX_FLOW_CTRL)) ? 1 : 0; 6347 pause->tx_pause = 6348 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, 6349 SWITCH_TX_FLOW_CTRL)) ? 1 : 0; 6350 } 6351 } 6352 6353 /** 6354 * netdev_set_pauseparam - set flow control parameters 6355 * @dev: Network device. 6356 * @pause: Ethtool PAUSE settings data structure. 6357 * 6358 * This function sets the PAUSE control flow settings. 6359 * Not implemented yet. 6360 * 6361 * Return 0 if successful; otherwise an error code. 6362 */ 6363 static int netdev_set_pauseparam(struct net_device *dev, 6364 struct ethtool_pauseparam *pause) 6365 { 6366 struct dev_priv *priv = netdev_priv(dev); 6367 struct dev_info *hw_priv = priv->adapter; 6368 struct ksz_hw *hw = &hw_priv->hw; 6369 struct ksz_port *port = &priv->port; 6370 6371 mutex_lock(&hw_priv->lock); 6372 if (pause->autoneg) { 6373 if (!pause->rx_pause && !pause->tx_pause) 6374 port->flow_ctrl = PHY_NO_FLOW_CTRL; 6375 else 6376 port->flow_ctrl = PHY_FLOW_CTRL; 6377 hw->overrides &= ~PAUSE_FLOW_CTRL; 6378 port->force_link = 0; 6379 if (hw->ksz_switch) { 6380 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, 6381 SWITCH_RX_FLOW_CTRL, 1); 6382 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, 6383 SWITCH_TX_FLOW_CTRL, 1); 6384 } 6385 port_set_link_speed(port); 6386 } else { 6387 hw->overrides |= PAUSE_FLOW_CTRL; 6388 if (hw->ksz_switch) { 6389 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, 6390 SWITCH_RX_FLOW_CTRL, pause->rx_pause); 6391 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, 6392 SWITCH_TX_FLOW_CTRL, pause->tx_pause); 6393 } else 6394 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause); 6395 } 6396 mutex_unlock(&hw_priv->lock); 6397 6398 return 0; 6399 } 6400 6401 /** 6402 * netdev_get_ringparam - get tx/rx ring parameters 6403 * @dev: Network device. 6404 * @pause: Ethtool RING settings data structure. 6405 * 6406 * This procedure returns the TX/RX ring settings. 6407 */ 6408 static void netdev_get_ringparam(struct net_device *dev, 6409 struct ethtool_ringparam *ring) 6410 { 6411 struct dev_priv *priv = netdev_priv(dev); 6412 struct dev_info *hw_priv = priv->adapter; 6413 struct ksz_hw *hw = &hw_priv->hw; 6414 6415 ring->tx_max_pending = (1 << 9); 6416 ring->tx_pending = hw->tx_desc_info.alloc; 6417 ring->rx_max_pending = (1 << 9); 6418 ring->rx_pending = hw->rx_desc_info.alloc; 6419 } 6420 6421 #define STATS_LEN (TOTAL_PORT_COUNTER_NUM) 6422 6423 static struct { 6424 char string[ETH_GSTRING_LEN]; 6425 } ethtool_stats_keys[STATS_LEN] = { 6426 { "rx_lo_priority_octets" }, 6427 { "rx_hi_priority_octets" }, 6428 { "rx_undersize_packets" }, 6429 { "rx_fragments" }, 6430 { "rx_oversize_packets" }, 6431 { "rx_jabbers" }, 6432 { "rx_symbol_errors" }, 6433 { "rx_crc_errors" }, 6434 { "rx_align_errors" }, 6435 { "rx_mac_ctrl_packets" }, 6436 { "rx_pause_packets" }, 6437 { "rx_bcast_packets" }, 6438 { "rx_mcast_packets" }, 6439 { "rx_ucast_packets" }, 6440 { "rx_64_or_less_octet_packets" }, 6441 { "rx_65_to_127_octet_packets" }, 6442 { "rx_128_to_255_octet_packets" }, 6443 { "rx_256_to_511_octet_packets" }, 6444 { "rx_512_to_1023_octet_packets" }, 6445 { "rx_1024_to_1522_octet_packets" }, 6446 6447 { "tx_lo_priority_octets" }, 6448 { "tx_hi_priority_octets" }, 6449 { "tx_late_collisions" }, 6450 { "tx_pause_packets" }, 6451 { "tx_bcast_packets" }, 6452 { "tx_mcast_packets" }, 6453 { "tx_ucast_packets" }, 6454 { "tx_deferred" }, 6455 { "tx_total_collisions" }, 6456 { "tx_excessive_collisions" }, 6457 { "tx_single_collisions" }, 6458 { "tx_mult_collisions" }, 6459 6460 { "rx_discards" }, 6461 { "tx_discards" }, 6462 }; 6463 6464 /** 6465 * netdev_get_strings - get statistics identity strings 6466 * @dev: Network device. 6467 * @stringset: String set identifier. 6468 * @buf: Buffer to store the strings. 6469 * 6470 * This procedure returns the strings used to identify the statistics. 6471 */ 6472 static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 6473 { 6474 struct dev_priv *priv = netdev_priv(dev); 6475 struct dev_info *hw_priv = priv->adapter; 6476 struct ksz_hw *hw = &hw_priv->hw; 6477 6478 if (ETH_SS_STATS == stringset) 6479 memcpy(buf, ðtool_stats_keys, 6480 ETH_GSTRING_LEN * hw->mib_cnt); 6481 } 6482 6483 /** 6484 * netdev_get_sset_count - get statistics size 6485 * @dev: Network device. 6486 * @sset: The statistics set number. 6487 * 6488 * This function returns the size of the statistics to be reported. 6489 * 6490 * Return size of the statistics to be reported. 6491 */ 6492 static int netdev_get_sset_count(struct net_device *dev, int sset) 6493 { 6494 struct dev_priv *priv = netdev_priv(dev); 6495 struct dev_info *hw_priv = priv->adapter; 6496 struct ksz_hw *hw = &hw_priv->hw; 6497 6498 switch (sset) { 6499 case ETH_SS_STATS: 6500 return hw->mib_cnt; 6501 default: 6502 return -EOPNOTSUPP; 6503 } 6504 } 6505 6506 /** 6507 * netdev_get_ethtool_stats - get network device statistics 6508 * @dev: Network device. 6509 * @stats: Ethtool statistics data structure. 6510 * @data: Buffer to store the statistics. 6511 * 6512 * This procedure returns the statistics. 6513 */ 6514 static void netdev_get_ethtool_stats(struct net_device *dev, 6515 struct ethtool_stats *stats, u64 *data) 6516 { 6517 struct dev_priv *priv = netdev_priv(dev); 6518 struct dev_info *hw_priv = priv->adapter; 6519 struct ksz_hw *hw = &hw_priv->hw; 6520 struct ksz_port *port = &priv->port; 6521 int n_stats = stats->n_stats; 6522 int i; 6523 int n; 6524 int p; 6525 int rc; 6526 u64 counter[TOTAL_PORT_COUNTER_NUM]; 6527 6528 mutex_lock(&hw_priv->lock); 6529 n = SWITCH_PORT_NUM; 6530 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { 6531 if (media_connected == hw->port_mib[p].state) { 6532 hw_priv->counter[p].read = 1; 6533 6534 /* Remember first port that requests read. */ 6535 if (n == SWITCH_PORT_NUM) 6536 n = p; 6537 } 6538 } 6539 mutex_unlock(&hw_priv->lock); 6540 6541 if (n < SWITCH_PORT_NUM) 6542 schedule_work(&hw_priv->mib_read); 6543 6544 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) { 6545 p = n; 6546 rc = wait_event_interruptible_timeout( 6547 hw_priv->counter[p].counter, 6548 2 == hw_priv->counter[p].read, 6549 HZ * 1); 6550 } else 6551 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) { 6552 if (0 == i) { 6553 rc = wait_event_interruptible_timeout( 6554 hw_priv->counter[p].counter, 6555 2 == hw_priv->counter[p].read, 6556 HZ * 2); 6557 } else if (hw->port_mib[p].cnt_ptr) { 6558 rc = wait_event_interruptible_timeout( 6559 hw_priv->counter[p].counter, 6560 2 == hw_priv->counter[p].read, 6561 HZ * 1); 6562 } 6563 } 6564 6565 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter); 6566 n = hw->mib_cnt; 6567 if (n > n_stats) 6568 n = n_stats; 6569 n_stats -= n; 6570 for (i = 0; i < n; i++) 6571 *data++ = counter[i]; 6572 } 6573 6574 /** 6575 * netdev_set_features - set receive checksum support 6576 * @dev: Network device. 6577 * @features: New device features (offloads). 6578 * 6579 * This function sets receive checksum support setting. 6580 * 6581 * Return 0 if successful; otherwise an error code. 6582 */ 6583 static int netdev_set_features(struct net_device *dev, 6584 netdev_features_t features) 6585 { 6586 struct dev_priv *priv = netdev_priv(dev); 6587 struct dev_info *hw_priv = priv->adapter; 6588 struct ksz_hw *hw = &hw_priv->hw; 6589 6590 mutex_lock(&hw_priv->lock); 6591 6592 /* see note in hw_setup() */ 6593 if (features & NETIF_F_RXCSUM) 6594 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP; 6595 else 6596 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP); 6597 6598 if (hw->enabled) 6599 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); 6600 6601 mutex_unlock(&hw_priv->lock); 6602 6603 return 0; 6604 } 6605 6606 static const struct ethtool_ops netdev_ethtool_ops = { 6607 .get_settings = netdev_get_settings, 6608 .set_settings = netdev_set_settings, 6609 .nway_reset = netdev_nway_reset, 6610 .get_link = netdev_get_link, 6611 .get_drvinfo = netdev_get_drvinfo, 6612 .get_regs_len = netdev_get_regs_len, 6613 .get_regs = netdev_get_regs, 6614 .get_wol = netdev_get_wol, 6615 .set_wol = netdev_set_wol, 6616 .get_msglevel = netdev_get_msglevel, 6617 .set_msglevel = netdev_set_msglevel, 6618 .get_eeprom_len = netdev_get_eeprom_len, 6619 .get_eeprom = netdev_get_eeprom, 6620 .set_eeprom = netdev_set_eeprom, 6621 .get_pauseparam = netdev_get_pauseparam, 6622 .set_pauseparam = netdev_set_pauseparam, 6623 .get_ringparam = netdev_get_ringparam, 6624 .get_strings = netdev_get_strings, 6625 .get_sset_count = netdev_get_sset_count, 6626 .get_ethtool_stats = netdev_get_ethtool_stats, 6627 }; 6628 6629 /* 6630 * Hardware monitoring 6631 */ 6632 6633 static void update_link(struct net_device *dev, struct dev_priv *priv, 6634 struct ksz_port *port) 6635 { 6636 if (priv->media_state != port->linked->state) { 6637 priv->media_state = port->linked->state; 6638 if (netif_running(dev)) 6639 set_media_state(dev, media_connected); 6640 } 6641 } 6642 6643 static void mib_read_work(struct work_struct *work) 6644 { 6645 struct dev_info *hw_priv = 6646 container_of(work, struct dev_info, mib_read); 6647 struct ksz_hw *hw = &hw_priv->hw; 6648 struct ksz_port_mib *mib; 6649 int i; 6650 6651 next_jiffies = jiffies; 6652 for (i = 0; i < hw->mib_port_cnt; i++) { 6653 mib = &hw->port_mib[i]; 6654 6655 /* Reading MIB counters or requested to read. */ 6656 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) { 6657 6658 /* Need to process receive interrupt. */ 6659 if (port_r_cnt(hw, i)) 6660 break; 6661 hw_priv->counter[i].read = 0; 6662 6663 /* Finish reading counters. */ 6664 if (0 == mib->cnt_ptr) { 6665 hw_priv->counter[i].read = 2; 6666 wake_up_interruptible( 6667 &hw_priv->counter[i].counter); 6668 } 6669 } else if (jiffies >= hw_priv->counter[i].time) { 6670 /* Only read MIB counters when the port is connected. */ 6671 if (media_connected == mib->state) 6672 hw_priv->counter[i].read = 1; 6673 next_jiffies += HZ * 1 * hw->mib_port_cnt; 6674 hw_priv->counter[i].time = next_jiffies; 6675 6676 /* Port is just disconnected. */ 6677 } else if (mib->link_down) { 6678 mib->link_down = 0; 6679 6680 /* Read counters one last time after link is lost. */ 6681 hw_priv->counter[i].read = 1; 6682 } 6683 } 6684 } 6685 6686 static void mib_monitor(unsigned long ptr) 6687 { 6688 struct dev_info *hw_priv = (struct dev_info *) ptr; 6689 6690 mib_read_work(&hw_priv->mib_read); 6691 6692 /* This is used to verify Wake-on-LAN is working. */ 6693 if (hw_priv->pme_wait) { 6694 if (hw_priv->pme_wait <= jiffies) { 6695 hw_clr_wol_pme_status(&hw_priv->hw); 6696 hw_priv->pme_wait = 0; 6697 } 6698 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) { 6699 6700 /* PME is asserted. Wait 2 seconds to clear it. */ 6701 hw_priv->pme_wait = jiffies + HZ * 2; 6702 } 6703 6704 ksz_update_timer(&hw_priv->mib_timer_info); 6705 } 6706 6707 /** 6708 * dev_monitor - periodic monitoring 6709 * @ptr: Network device pointer. 6710 * 6711 * This routine is run in a kernel timer to monitor the network device. 6712 */ 6713 static void dev_monitor(unsigned long ptr) 6714 { 6715 struct net_device *dev = (struct net_device *) ptr; 6716 struct dev_priv *priv = netdev_priv(dev); 6717 struct dev_info *hw_priv = priv->adapter; 6718 struct ksz_hw *hw = &hw_priv->hw; 6719 struct ksz_port *port = &priv->port; 6720 6721 if (!(hw->features & LINK_INT_WORKING)) 6722 port_get_link_speed(port); 6723 update_link(dev, priv, port); 6724 6725 ksz_update_timer(&priv->monitor_timer_info); 6726 } 6727 6728 /* 6729 * Linux network device interface functions 6730 */ 6731 6732 /* Driver exported variables */ 6733 6734 static int msg_enable; 6735 6736 static char *macaddr = ":"; 6737 static char *mac1addr = ":"; 6738 6739 /* 6740 * This enables multiple network device mode for KSZ8842, which contains a 6741 * switch with two physical ports. Some users like to take control of the 6742 * ports for running Spanning Tree Protocol. The driver will create an 6743 * additional eth? device for the other port. 6744 * 6745 * Some limitations are the network devices cannot have different MTU and 6746 * multicast hash tables. 6747 */ 6748 static int multi_dev; 6749 6750 /* 6751 * As most users select multiple network device mode to use Spanning Tree 6752 * Protocol, this enables a feature in which most unicast and multicast packets 6753 * are forwarded inside the switch and not passed to the host. Only packets 6754 * that need the host's attention are passed to it. This prevents the host 6755 * wasting CPU time to examine each and every incoming packets and do the 6756 * forwarding itself. 6757 * 6758 * As the hack requires the private bridge header, the driver cannot compile 6759 * with just the kernel headers. 6760 * 6761 * Enabling STP support also turns on multiple network device mode. 6762 */ 6763 static int stp; 6764 6765 /* 6766 * This enables fast aging in the KSZ8842 switch. Not sure what situation 6767 * needs that. However, fast aging is used to flush the dynamic MAC table when 6768 * STP support is enabled. 6769 */ 6770 static int fast_aging; 6771 6772 /** 6773 * netdev_init - initialize network device. 6774 * @dev: Network device. 6775 * 6776 * This function initializes the network device. 6777 * 6778 * Return 0 if successful; otherwise an error code indicating failure. 6779 */ 6780 static int __init netdev_init(struct net_device *dev) 6781 { 6782 struct dev_priv *priv = netdev_priv(dev); 6783 6784 /* 500 ms timeout */ 6785 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000, 6786 dev_monitor, dev); 6787 6788 /* 500 ms timeout */ 6789 dev->watchdog_timeo = HZ / 2; 6790 6791 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM; 6792 6793 /* 6794 * Hardware does not really support IPv6 checksum generation, but 6795 * driver actually runs faster with this on. 6796 */ 6797 dev->hw_features |= NETIF_F_IPV6_CSUM; 6798 6799 dev->features |= dev->hw_features; 6800 6801 sema_init(&priv->proc_sem, 1); 6802 6803 priv->mii_if.phy_id_mask = 0x1; 6804 priv->mii_if.reg_num_mask = 0x7; 6805 priv->mii_if.dev = dev; 6806 priv->mii_if.mdio_read = mdio_read; 6807 priv->mii_if.mdio_write = mdio_write; 6808 priv->mii_if.phy_id = priv->port.first_port + 1; 6809 6810 priv->msg_enable = netif_msg_init(msg_enable, 6811 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)); 6812 6813 return 0; 6814 } 6815 6816 static const struct net_device_ops netdev_ops = { 6817 .ndo_init = netdev_init, 6818 .ndo_open = netdev_open, 6819 .ndo_stop = netdev_close, 6820 .ndo_get_stats = netdev_query_statistics, 6821 .ndo_start_xmit = netdev_tx, 6822 .ndo_tx_timeout = netdev_tx_timeout, 6823 .ndo_change_mtu = netdev_change_mtu, 6824 .ndo_set_features = netdev_set_features, 6825 .ndo_set_mac_address = netdev_set_mac_address, 6826 .ndo_validate_addr = eth_validate_addr, 6827 .ndo_do_ioctl = netdev_ioctl, 6828 .ndo_set_rx_mode = netdev_set_rx_mode, 6829 #ifdef CONFIG_NET_POLL_CONTROLLER 6830 .ndo_poll_controller = netdev_netpoll, 6831 #endif 6832 }; 6833 6834 static void netdev_free(struct net_device *dev) 6835 { 6836 if (dev->watchdog_timeo) 6837 unregister_netdev(dev); 6838 6839 free_netdev(dev); 6840 } 6841 6842 struct platform_info { 6843 struct dev_info dev_info; 6844 struct net_device *netdev[SWITCH_PORT_NUM]; 6845 }; 6846 6847 static int net_device_present; 6848 6849 static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port) 6850 { 6851 int i; 6852 int j; 6853 int got_num; 6854 int num; 6855 6856 i = j = num = got_num = 0; 6857 while (j < ETH_ALEN) { 6858 if (macaddr[i]) { 6859 int digit; 6860 6861 got_num = 1; 6862 digit = hex_to_bin(macaddr[i]); 6863 if (digit >= 0) 6864 num = num * 16 + digit; 6865 else if (':' == macaddr[i]) 6866 got_num = 2; 6867 else 6868 break; 6869 } else if (got_num) 6870 got_num = 2; 6871 else 6872 break; 6873 if (2 == got_num) { 6874 if (MAIN_PORT == port) { 6875 hw_priv->hw.override_addr[j++] = (u8) num; 6876 hw_priv->hw.override_addr[5] += 6877 hw_priv->hw.id; 6878 } else { 6879 hw_priv->hw.ksz_switch->other_addr[j++] = 6880 (u8) num; 6881 hw_priv->hw.ksz_switch->other_addr[5] += 6882 hw_priv->hw.id; 6883 } 6884 num = got_num = 0; 6885 } 6886 i++; 6887 } 6888 if (ETH_ALEN == j) { 6889 if (MAIN_PORT == port) 6890 hw_priv->hw.mac_override = 1; 6891 } 6892 } 6893 6894 #define KS884X_DMA_MASK (~0x0UL) 6895 6896 static void read_other_addr(struct ksz_hw *hw) 6897 { 6898 int i; 6899 u16 data[3]; 6900 struct ksz_switch *sw = hw->ksz_switch; 6901 6902 for (i = 0; i < 3; i++) 6903 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR); 6904 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) { 6905 sw->other_addr[5] = (u8) data[0]; 6906 sw->other_addr[4] = (u8)(data[0] >> 8); 6907 sw->other_addr[3] = (u8) data[1]; 6908 sw->other_addr[2] = (u8)(data[1] >> 8); 6909 sw->other_addr[1] = (u8) data[2]; 6910 sw->other_addr[0] = (u8)(data[2] >> 8); 6911 } 6912 } 6913 6914 #ifndef PCI_VENDOR_ID_MICREL_KS 6915 #define PCI_VENDOR_ID_MICREL_KS 0x16c6 6916 #endif 6917 6918 static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id) 6919 { 6920 struct net_device *dev; 6921 struct dev_priv *priv; 6922 struct dev_info *hw_priv; 6923 struct ksz_hw *hw; 6924 struct platform_info *info; 6925 struct ksz_port *port; 6926 unsigned long reg_base; 6927 unsigned long reg_len; 6928 int cnt; 6929 int i; 6930 int mib_port_count; 6931 int pi; 6932 int port_count; 6933 int result; 6934 char banner[sizeof(version)]; 6935 struct ksz_switch *sw = NULL; 6936 6937 result = pci_enable_device(pdev); 6938 if (result) 6939 return result; 6940 6941 result = -ENODEV; 6942 6943 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) || 6944 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 6945 return result; 6946 6947 reg_base = pci_resource_start(pdev, 0); 6948 reg_len = pci_resource_len(pdev, 0); 6949 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) 6950 return result; 6951 6952 if (!request_mem_region(reg_base, reg_len, DRV_NAME)) 6953 return result; 6954 pci_set_master(pdev); 6955 6956 result = -ENOMEM; 6957 6958 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL); 6959 if (!info) 6960 goto pcidev_init_dev_err; 6961 6962 hw_priv = &info->dev_info; 6963 hw_priv->pdev = pdev; 6964 6965 hw = &hw_priv->hw; 6966 6967 hw->io = ioremap(reg_base, reg_len); 6968 if (!hw->io) 6969 goto pcidev_init_io_err; 6970 6971 cnt = hw_init(hw); 6972 if (!cnt) { 6973 if (msg_enable & NETIF_MSG_PROBE) 6974 pr_alert("chip not detected\n"); 6975 result = -ENODEV; 6976 goto pcidev_init_alloc_err; 6977 } 6978 6979 snprintf(banner, sizeof(banner), "%s", version); 6980 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */ 6981 dev_info(&hw_priv->pdev->dev, "%s\n", banner); 6982 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq); 6983 6984 /* Assume device is KSZ8841. */ 6985 hw->dev_count = 1; 6986 port_count = 1; 6987 mib_port_count = 1; 6988 hw->addr_list_size = 0; 6989 hw->mib_cnt = PORT_COUNTER_NUM; 6990 hw->mib_port_cnt = 1; 6991 6992 /* KSZ8842 has a switch with multiple ports. */ 6993 if (2 == cnt) { 6994 if (fast_aging) 6995 hw->overrides |= FAST_AGING; 6996 6997 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM; 6998 6999 /* Multiple network device interfaces are required. */ 7000 if (multi_dev) { 7001 hw->dev_count = SWITCH_PORT_NUM; 7002 hw->addr_list_size = SWITCH_PORT_NUM - 1; 7003 } 7004 7005 /* Single network device has multiple ports. */ 7006 if (1 == hw->dev_count) { 7007 port_count = SWITCH_PORT_NUM; 7008 mib_port_count = SWITCH_PORT_NUM; 7009 } 7010 hw->mib_port_cnt = TOTAL_PORT_NUM; 7011 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL); 7012 if (!hw->ksz_switch) 7013 goto pcidev_init_alloc_err; 7014 7015 sw = hw->ksz_switch; 7016 } 7017 for (i = 0; i < hw->mib_port_cnt; i++) 7018 hw->port_mib[i].mib_start = 0; 7019 7020 hw->parent = hw_priv; 7021 7022 /* Default MTU is 1500. */ 7023 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3; 7024 7025 if (ksz_alloc_mem(hw_priv)) 7026 goto pcidev_init_mem_err; 7027 7028 hw_priv->hw.id = net_device_present; 7029 7030 spin_lock_init(&hw_priv->hwlock); 7031 mutex_init(&hw_priv->lock); 7032 7033 for (i = 0; i < TOTAL_PORT_NUM; i++) 7034 init_waitqueue_head(&hw_priv->counter[i].counter); 7035 7036 if (macaddr[0] != ':') 7037 get_mac_addr(hw_priv, macaddr, MAIN_PORT); 7038 7039 /* Read MAC address and initialize override address if not overrided. */ 7040 hw_read_addr(hw); 7041 7042 /* Multiple device interfaces mode requires a second MAC address. */ 7043 if (hw->dev_count > 1) { 7044 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN); 7045 read_other_addr(hw); 7046 if (mac1addr[0] != ':') 7047 get_mac_addr(hw_priv, mac1addr, OTHER_PORT); 7048 } 7049 7050 hw_setup(hw); 7051 if (hw->ksz_switch) 7052 sw_setup(hw); 7053 else { 7054 hw_priv->wol_support = WOL_SUPPORT; 7055 hw_priv->wol_enable = 0; 7056 } 7057 7058 INIT_WORK(&hw_priv->mib_read, mib_read_work); 7059 7060 /* 500 ms timeout */ 7061 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000, 7062 mib_monitor, hw_priv); 7063 7064 for (i = 0; i < hw->dev_count; i++) { 7065 dev = alloc_etherdev(sizeof(struct dev_priv)); 7066 if (!dev) 7067 goto pcidev_init_reg_err; 7068 SET_NETDEV_DEV(dev, &pdev->dev); 7069 info->netdev[i] = dev; 7070 7071 priv = netdev_priv(dev); 7072 priv->adapter = hw_priv; 7073 priv->id = net_device_present++; 7074 7075 port = &priv->port; 7076 port->port_cnt = port_count; 7077 port->mib_port_cnt = mib_port_count; 7078 port->first_port = i; 7079 port->flow_ctrl = PHY_FLOW_CTRL; 7080 7081 port->hw = hw; 7082 port->linked = &hw->port_info[port->first_port]; 7083 7084 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) { 7085 hw->port_info[pi].port_id = pi; 7086 hw->port_info[pi].pdev = dev; 7087 hw->port_info[pi].state = media_disconnected; 7088 } 7089 7090 dev->mem_start = (unsigned long) hw->io; 7091 dev->mem_end = dev->mem_start + reg_len - 1; 7092 dev->irq = pdev->irq; 7093 if (MAIN_PORT == i) 7094 memcpy(dev->dev_addr, hw_priv->hw.override_addr, 7095 ETH_ALEN); 7096 else { 7097 memcpy(dev->dev_addr, sw->other_addr, ETH_ALEN); 7098 if (ether_addr_equal(sw->other_addr, hw->override_addr)) 7099 dev->dev_addr[5] += port->first_port; 7100 } 7101 7102 dev->netdev_ops = &netdev_ops; 7103 dev->ethtool_ops = &netdev_ethtool_ops; 7104 if (register_netdev(dev)) 7105 goto pcidev_init_reg_err; 7106 port_set_power_saving(port, true); 7107 } 7108 7109 pci_dev_get(hw_priv->pdev); 7110 pci_set_drvdata(pdev, info); 7111 return 0; 7112 7113 pcidev_init_reg_err: 7114 for (i = 0; i < hw->dev_count; i++) { 7115 if (info->netdev[i]) { 7116 netdev_free(info->netdev[i]); 7117 info->netdev[i] = NULL; 7118 } 7119 } 7120 7121 pcidev_init_mem_err: 7122 ksz_free_mem(hw_priv); 7123 kfree(hw->ksz_switch); 7124 7125 pcidev_init_alloc_err: 7126 iounmap(hw->io); 7127 7128 pcidev_init_io_err: 7129 kfree(info); 7130 7131 pcidev_init_dev_err: 7132 release_mem_region(reg_base, reg_len); 7133 7134 return result; 7135 } 7136 7137 static void pcidev_exit(struct pci_dev *pdev) 7138 { 7139 int i; 7140 struct platform_info *info = pci_get_drvdata(pdev); 7141 struct dev_info *hw_priv = &info->dev_info; 7142 7143 release_mem_region(pci_resource_start(pdev, 0), 7144 pci_resource_len(pdev, 0)); 7145 for (i = 0; i < hw_priv->hw.dev_count; i++) { 7146 if (info->netdev[i]) 7147 netdev_free(info->netdev[i]); 7148 } 7149 if (hw_priv->hw.io) 7150 iounmap(hw_priv->hw.io); 7151 ksz_free_mem(hw_priv); 7152 kfree(hw_priv->hw.ksz_switch); 7153 pci_dev_put(hw_priv->pdev); 7154 kfree(info); 7155 } 7156 7157 #ifdef CONFIG_PM 7158 static int pcidev_resume(struct pci_dev *pdev) 7159 { 7160 int i; 7161 struct platform_info *info = pci_get_drvdata(pdev); 7162 struct dev_info *hw_priv = &info->dev_info; 7163 struct ksz_hw *hw = &hw_priv->hw; 7164 7165 pci_set_power_state(pdev, PCI_D0); 7166 pci_restore_state(pdev); 7167 pci_enable_wake(pdev, PCI_D0, 0); 7168 7169 if (hw_priv->wol_enable) 7170 hw_cfg_wol_pme(hw, 0); 7171 for (i = 0; i < hw->dev_count; i++) { 7172 if (info->netdev[i]) { 7173 struct net_device *dev = info->netdev[i]; 7174 7175 if (netif_running(dev)) { 7176 netdev_open(dev); 7177 netif_device_attach(dev); 7178 } 7179 } 7180 } 7181 return 0; 7182 } 7183 7184 static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state) 7185 { 7186 int i; 7187 struct platform_info *info = pci_get_drvdata(pdev); 7188 struct dev_info *hw_priv = &info->dev_info; 7189 struct ksz_hw *hw = &hw_priv->hw; 7190 7191 /* Need to find a way to retrieve the device IP address. */ 7192 static const u8 net_addr[] = { 192, 168, 1, 1 }; 7193 7194 for (i = 0; i < hw->dev_count; i++) { 7195 if (info->netdev[i]) { 7196 struct net_device *dev = info->netdev[i]; 7197 7198 if (netif_running(dev)) { 7199 netif_device_detach(dev); 7200 netdev_close(dev); 7201 } 7202 } 7203 } 7204 if (hw_priv->wol_enable) { 7205 hw_enable_wol(hw, hw_priv->wol_enable, net_addr); 7206 hw_cfg_wol_pme(hw, 1); 7207 } 7208 7209 pci_save_state(pdev); 7210 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 7211 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 7212 return 0; 7213 } 7214 #endif 7215 7216 static char pcidev_name[] = "ksz884xp"; 7217 7218 static const struct pci_device_id pcidev_table[] = { 7219 { PCI_VENDOR_ID_MICREL_KS, 0x8841, 7220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 7221 { PCI_VENDOR_ID_MICREL_KS, 0x8842, 7222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 7223 { 0 } 7224 }; 7225 7226 MODULE_DEVICE_TABLE(pci, pcidev_table); 7227 7228 static struct pci_driver pci_device_driver = { 7229 #ifdef CONFIG_PM 7230 .suspend = pcidev_suspend, 7231 .resume = pcidev_resume, 7232 #endif 7233 .name = pcidev_name, 7234 .id_table = pcidev_table, 7235 .probe = pcidev_init, 7236 .remove = pcidev_exit 7237 }; 7238 7239 module_pci_driver(pci_device_driver); 7240 7241 MODULE_DESCRIPTION("KSZ8841/2 PCI network driver"); 7242 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>"); 7243 MODULE_LICENSE("GPL"); 7244 7245 module_param_named(message, msg_enable, int, 0); 7246 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)"); 7247 7248 module_param(macaddr, charp, 0); 7249 module_param(mac1addr, charp, 0); 7250 module_param(fast_aging, int, 0); 7251 module_param(multi_dev, int, 0); 7252 module_param(stp, int, 0); 7253 MODULE_PARM_DESC(macaddr, "MAC address"); 7254 MODULE_PARM_DESC(mac1addr, "Second MAC address"); 7255 MODULE_PARM_DESC(fast_aging, "Fast aging"); 7256 MODULE_PARM_DESC(multi_dev, "Multiple device interfaces"); 7257 MODULE_PARM_DESC(stp, "STP support"); 7258