1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/netdevice.h> 5 #include <linux/netlink.h> 6 #include <linux/random.h> 7 #include <net/vxlan.h> 8 9 #include "reg.h" 10 #include "spectrum.h" 11 #include "spectrum_nve.h" 12 13 /* Eth (18B) | IPv6 (40B) | UDP (8B) | VxLAN (8B) | Eth (14B) | IPv6 (40B) 14 * 15 * In the worst case - where we have a VLAN tag on the outer Ethernet 16 * header and IPv6 in overlay and underlay - we need to parse 128 bytes 17 */ 18 #define MLXSW_SP_NVE_VXLAN_PARSING_DEPTH 128 19 #define MLXSW_SP_NVE_DEFAULT_PARSING_DEPTH 96 20 21 #define MLXSW_SP_NVE_VXLAN_SUPPORTED_FLAGS (VXLAN_F_UDP_ZERO_CSUM_TX | \ 22 VXLAN_F_LEARN) 23 24 static bool mlxsw_sp_nve_vxlan_can_offload(const struct mlxsw_sp_nve *nve, 25 const struct mlxsw_sp_nve_params *params, 26 struct netlink_ext_ack *extack) 27 { 28 struct vxlan_dev *vxlan = netdev_priv(params->dev); 29 struct vxlan_config *cfg = &vxlan->cfg; 30 31 if (cfg->saddr.sa.sa_family != AF_INET) { 32 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Only IPv4 underlay is supported"); 33 return false; 34 } 35 36 if (vxlan_addr_multicast(&cfg->remote_ip)) { 37 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Multicast destination IP is not supported"); 38 return false; 39 } 40 41 if (vxlan_addr_any(&cfg->saddr)) { 42 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Source address must be specified"); 43 return false; 44 } 45 46 if (cfg->remote_ifindex) { 47 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Local interface is not supported"); 48 return false; 49 } 50 51 if (cfg->port_min || cfg->port_max) { 52 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Only default UDP source port range is supported"); 53 return false; 54 } 55 56 if (cfg->tos != 1) { 57 NL_SET_ERR_MSG_MOD(extack, "VxLAN: TOS must be configured to inherit"); 58 return false; 59 } 60 61 if (cfg->flags & VXLAN_F_TTL_INHERIT) { 62 NL_SET_ERR_MSG_MOD(extack, "VxLAN: TTL must not be configured to inherit"); 63 return false; 64 } 65 66 if (!(cfg->flags & VXLAN_F_UDP_ZERO_CSUM_TX)) { 67 NL_SET_ERR_MSG_MOD(extack, "VxLAN: UDP checksum is not supported"); 68 return false; 69 } 70 71 if (cfg->flags & ~MLXSW_SP_NVE_VXLAN_SUPPORTED_FLAGS) { 72 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Unsupported flag"); 73 return false; 74 } 75 76 if (cfg->ttl == 0) { 77 NL_SET_ERR_MSG_MOD(extack, "VxLAN: TTL must not be configured to 0"); 78 return false; 79 } 80 81 if (cfg->label != 0) { 82 NL_SET_ERR_MSG_MOD(extack, "VxLAN: Flow label must be configured to 0"); 83 return false; 84 } 85 86 return true; 87 } 88 89 static bool mlxsw_sp1_nve_vxlan_can_offload(const struct mlxsw_sp_nve *nve, 90 const struct mlxsw_sp_nve_params *params, 91 struct netlink_ext_ack *extack) 92 { 93 if (params->ethertype == ETH_P_8021AD) { 94 NL_SET_ERR_MSG_MOD(extack, "VxLAN: 802.1ad bridge is not supported with VxLAN"); 95 return false; 96 } 97 98 return mlxsw_sp_nve_vxlan_can_offload(nve, params, extack); 99 } 100 101 static void mlxsw_sp_nve_vxlan_config(const struct mlxsw_sp_nve *nve, 102 const struct mlxsw_sp_nve_params *params, 103 struct mlxsw_sp_nve_config *config) 104 { 105 struct vxlan_dev *vxlan = netdev_priv(params->dev); 106 struct vxlan_config *cfg = &vxlan->cfg; 107 108 config->type = MLXSW_SP_NVE_TYPE_VXLAN; 109 config->ttl = cfg->ttl; 110 config->flowlabel = cfg->label; 111 config->learning_en = cfg->flags & VXLAN_F_LEARN ? 1 : 0; 112 config->ul_tb_id = RT_TABLE_MAIN; 113 config->ul_proto = MLXSW_SP_L3_PROTO_IPV4; 114 config->ul_sip.addr4 = cfg->saddr.sin.sin_addr.s_addr; 115 config->udp_dport = cfg->dst_port; 116 } 117 118 static int __mlxsw_sp_nve_parsing_set(struct mlxsw_sp *mlxsw_sp, 119 unsigned int parsing_depth, 120 __be16 udp_dport) 121 { 122 char mprs_pl[MLXSW_REG_MPRS_LEN]; 123 124 mlxsw_reg_mprs_pack(mprs_pl, parsing_depth, be16_to_cpu(udp_dport)); 125 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 126 } 127 128 static int mlxsw_sp_nve_parsing_set(struct mlxsw_sp *mlxsw_sp, 129 __be16 udp_dport) 130 { 131 int parsing_depth = mlxsw_sp->nve->inc_parsing_depth_refs ? 132 MLXSW_SP_NVE_VXLAN_PARSING_DEPTH : 133 MLXSW_SP_NVE_DEFAULT_PARSING_DEPTH; 134 135 return __mlxsw_sp_nve_parsing_set(mlxsw_sp, parsing_depth, udp_dport); 136 } 137 138 static int 139 __mlxsw_sp_nve_inc_parsing_depth_get(struct mlxsw_sp *mlxsw_sp, 140 __be16 udp_dport) 141 { 142 int err; 143 144 mlxsw_sp->nve->inc_parsing_depth_refs++; 145 146 err = mlxsw_sp_nve_parsing_set(mlxsw_sp, udp_dport); 147 if (err) 148 goto err_nve_parsing_set; 149 return 0; 150 151 err_nve_parsing_set: 152 mlxsw_sp->nve->inc_parsing_depth_refs--; 153 return err; 154 } 155 156 static void 157 __mlxsw_sp_nve_inc_parsing_depth_put(struct mlxsw_sp *mlxsw_sp, 158 __be16 udp_dport) 159 { 160 mlxsw_sp->nve->inc_parsing_depth_refs--; 161 mlxsw_sp_nve_parsing_set(mlxsw_sp, udp_dport); 162 } 163 164 int mlxsw_sp_nve_inc_parsing_depth_get(struct mlxsw_sp *mlxsw_sp) 165 { 166 __be16 udp_dport = mlxsw_sp->nve->config.udp_dport; 167 168 return __mlxsw_sp_nve_inc_parsing_depth_get(mlxsw_sp, udp_dport); 169 } 170 171 void mlxsw_sp_nve_inc_parsing_depth_put(struct mlxsw_sp *mlxsw_sp) 172 { 173 __be16 udp_dport = mlxsw_sp->nve->config.udp_dport; 174 175 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, udp_dport); 176 } 177 178 static void 179 mlxsw_sp_nve_vxlan_config_prepare(char *tngcr_pl, 180 const struct mlxsw_sp_nve_config *config) 181 { 182 u8 udp_sport; 183 184 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, true, 185 config->ttl); 186 /* VxLAN driver's default UDP source port range is 32768 (0x8000) 187 * to 60999 (0xee47). Set the upper 8 bits of the UDP source port 188 * to a random number between 0x80 and 0xee 189 */ 190 get_random_bytes(&udp_sport, sizeof(udp_sport)); 191 udp_sport = (udp_sport % (0xee - 0x80 + 1)) + 0x80; 192 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(tngcr_pl, udp_sport); 193 mlxsw_reg_tngcr_usipv4_set(tngcr_pl, be32_to_cpu(config->ul_sip.addr4)); 194 } 195 196 static int 197 mlxsw_sp1_nve_vxlan_config_set(struct mlxsw_sp *mlxsw_sp, 198 const struct mlxsw_sp_nve_config *config) 199 { 200 char tngcr_pl[MLXSW_REG_TNGCR_LEN]; 201 u16 ul_vr_id; 202 int err; 203 204 err = mlxsw_sp_router_tb_id_vr_id(mlxsw_sp, config->ul_tb_id, 205 &ul_vr_id); 206 if (err) 207 return err; 208 209 mlxsw_sp_nve_vxlan_config_prepare(tngcr_pl, config); 210 mlxsw_reg_tngcr_learn_enable_set(tngcr_pl, config->learning_en); 211 mlxsw_reg_tngcr_underlay_virtual_router_set(tngcr_pl, ul_vr_id); 212 213 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl); 214 } 215 216 static void mlxsw_sp1_nve_vxlan_config_clear(struct mlxsw_sp *mlxsw_sp) 217 { 218 char tngcr_pl[MLXSW_REG_TNGCR_LEN]; 219 220 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, false, 0); 221 222 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl); 223 } 224 225 static int mlxsw_sp1_nve_vxlan_rtdp_set(struct mlxsw_sp *mlxsw_sp, 226 unsigned int tunnel_index) 227 { 228 char rtdp_pl[MLXSW_REG_RTDP_LEN]; 229 230 mlxsw_reg_rtdp_pack(rtdp_pl, MLXSW_REG_RTDP_TYPE_NVE, tunnel_index); 231 232 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rtdp), rtdp_pl); 233 } 234 235 static int mlxsw_sp1_nve_vxlan_init(struct mlxsw_sp_nve *nve, 236 const struct mlxsw_sp_nve_config *config) 237 { 238 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp; 239 int err; 240 241 err = __mlxsw_sp_nve_inc_parsing_depth_get(mlxsw_sp, config->udp_dport); 242 if (err) 243 return err; 244 245 err = mlxsw_sp1_nve_vxlan_config_set(mlxsw_sp, config); 246 if (err) 247 goto err_config_set; 248 249 err = mlxsw_sp1_nve_vxlan_rtdp_set(mlxsw_sp, nve->tunnel_index); 250 if (err) 251 goto err_rtdp_set; 252 253 err = mlxsw_sp_router_nve_promote_decap(mlxsw_sp, config->ul_tb_id, 254 config->ul_proto, 255 &config->ul_sip, 256 nve->tunnel_index); 257 if (err) 258 goto err_promote_decap; 259 260 return 0; 261 262 err_promote_decap: 263 err_rtdp_set: 264 mlxsw_sp1_nve_vxlan_config_clear(mlxsw_sp); 265 err_config_set: 266 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0); 267 return err; 268 } 269 270 static void mlxsw_sp1_nve_vxlan_fini(struct mlxsw_sp_nve *nve) 271 { 272 struct mlxsw_sp_nve_config *config = &nve->config; 273 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp; 274 275 mlxsw_sp_router_nve_demote_decap(mlxsw_sp, config->ul_tb_id, 276 config->ul_proto, &config->ul_sip); 277 mlxsw_sp1_nve_vxlan_config_clear(mlxsw_sp); 278 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0); 279 } 280 281 static int 282 mlxsw_sp_nve_vxlan_fdb_replay(const struct net_device *nve_dev, __be32 vni, 283 struct netlink_ext_ack *extack) 284 { 285 if (WARN_ON(!netif_is_vxlan(nve_dev))) 286 return -EINVAL; 287 return vxlan_fdb_replay(nve_dev, vni, &mlxsw_sp_switchdev_notifier, 288 extack); 289 } 290 291 static void 292 mlxsw_sp_nve_vxlan_clear_offload(const struct net_device *nve_dev, __be32 vni) 293 { 294 if (WARN_ON(!netif_is_vxlan(nve_dev))) 295 return; 296 vxlan_fdb_clear_offload(nve_dev, vni); 297 } 298 299 const struct mlxsw_sp_nve_ops mlxsw_sp1_nve_vxlan_ops = { 300 .type = MLXSW_SP_NVE_TYPE_VXLAN, 301 .can_offload = mlxsw_sp1_nve_vxlan_can_offload, 302 .nve_config = mlxsw_sp_nve_vxlan_config, 303 .init = mlxsw_sp1_nve_vxlan_init, 304 .fini = mlxsw_sp1_nve_vxlan_fini, 305 .fdb_replay = mlxsw_sp_nve_vxlan_fdb_replay, 306 .fdb_clear_offload = mlxsw_sp_nve_vxlan_clear_offload, 307 }; 308 309 static bool mlxsw_sp2_nve_vxlan_learning_set(struct mlxsw_sp *mlxsw_sp, 310 bool learning_en) 311 { 312 char tnpc_pl[MLXSW_REG_TNPC_LEN]; 313 314 mlxsw_reg_tnpc_pack(tnpc_pl, MLXSW_REG_TUNNEL_PORT_NVE, 315 learning_en); 316 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tnpc), tnpc_pl); 317 } 318 319 static int 320 mlxsw_sp2_nve_decap_ethertype_set(struct mlxsw_sp *mlxsw_sp) 321 { 322 char spvid_pl[MLXSW_REG_SPVID_LEN] = {}; 323 324 mlxsw_reg_spvid_tport_set(spvid_pl, true); 325 mlxsw_reg_spvid_local_port_set(spvid_pl, 326 MLXSW_REG_TUNNEL_PORT_NVE); 327 mlxsw_reg_spvid_egr_et_set_set(spvid_pl, true); 328 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 329 } 330 331 static int 332 mlxsw_sp2_nve_vxlan_config_set(struct mlxsw_sp *mlxsw_sp, 333 const struct mlxsw_sp_nve_config *config) 334 { 335 char tngcr_pl[MLXSW_REG_TNGCR_LEN]; 336 char spvtr_pl[MLXSW_REG_SPVTR_LEN]; 337 u16 ul_rif_index; 338 int err; 339 340 err = mlxsw_sp_router_ul_rif_get(mlxsw_sp, config->ul_tb_id, 341 &ul_rif_index); 342 if (err) 343 return err; 344 mlxsw_sp->nve->ul_rif_index = ul_rif_index; 345 346 err = mlxsw_sp2_nve_vxlan_learning_set(mlxsw_sp, config->learning_en); 347 if (err) 348 goto err_vxlan_learning_set; 349 350 mlxsw_sp_nve_vxlan_config_prepare(tngcr_pl, config); 351 mlxsw_reg_tngcr_underlay_rif_set(tngcr_pl, ul_rif_index); 352 353 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl); 354 if (err) 355 goto err_tngcr_write; 356 357 mlxsw_reg_spvtr_pack(spvtr_pl, true, MLXSW_REG_TUNNEL_PORT_NVE, 358 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN); 359 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvtr), spvtr_pl); 360 if (err) 361 goto err_spvtr_write; 362 363 err = mlxsw_sp2_nve_decap_ethertype_set(mlxsw_sp); 364 if (err) 365 goto err_decap_ethertype_set; 366 367 return 0; 368 369 err_decap_ethertype_set: 370 mlxsw_reg_spvtr_pack(spvtr_pl, true, MLXSW_REG_TUNNEL_PORT_NVE, 371 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID); 372 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvtr), spvtr_pl); 373 err_spvtr_write: 374 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, false, 0); 375 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl); 376 err_tngcr_write: 377 mlxsw_sp2_nve_vxlan_learning_set(mlxsw_sp, false); 378 err_vxlan_learning_set: 379 mlxsw_sp_router_ul_rif_put(mlxsw_sp, ul_rif_index); 380 return err; 381 } 382 383 static void mlxsw_sp2_nve_vxlan_config_clear(struct mlxsw_sp *mlxsw_sp) 384 { 385 char spvtr_pl[MLXSW_REG_SPVTR_LEN]; 386 char tngcr_pl[MLXSW_REG_TNGCR_LEN]; 387 388 mlxsw_reg_spvtr_pack(spvtr_pl, true, MLXSW_REG_TUNNEL_PORT_NVE, 389 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID); 390 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvtr), spvtr_pl); 391 mlxsw_reg_tngcr_pack(tngcr_pl, MLXSW_REG_TNGCR_TYPE_VXLAN, false, 0); 392 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tngcr), tngcr_pl); 393 mlxsw_sp2_nve_vxlan_learning_set(mlxsw_sp, false); 394 mlxsw_sp_router_ul_rif_put(mlxsw_sp, mlxsw_sp->nve->ul_rif_index); 395 } 396 397 static int mlxsw_sp2_nve_vxlan_rtdp_set(struct mlxsw_sp *mlxsw_sp, 398 unsigned int tunnel_index, 399 u16 ul_rif_index) 400 { 401 char rtdp_pl[MLXSW_REG_RTDP_LEN]; 402 403 mlxsw_reg_rtdp_pack(rtdp_pl, MLXSW_REG_RTDP_TYPE_NVE, tunnel_index); 404 mlxsw_reg_rtdp_egress_router_interface_set(rtdp_pl, ul_rif_index); 405 406 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rtdp), rtdp_pl); 407 } 408 409 static int mlxsw_sp2_nve_vxlan_init(struct mlxsw_sp_nve *nve, 410 const struct mlxsw_sp_nve_config *config) 411 { 412 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp; 413 int err; 414 415 err = __mlxsw_sp_nve_inc_parsing_depth_get(mlxsw_sp, config->udp_dport); 416 if (err) 417 return err; 418 419 err = mlxsw_sp2_nve_vxlan_config_set(mlxsw_sp, config); 420 if (err) 421 goto err_config_set; 422 423 err = mlxsw_sp2_nve_vxlan_rtdp_set(mlxsw_sp, nve->tunnel_index, 424 nve->ul_rif_index); 425 if (err) 426 goto err_rtdp_set; 427 428 err = mlxsw_sp_router_nve_promote_decap(mlxsw_sp, config->ul_tb_id, 429 config->ul_proto, 430 &config->ul_sip, 431 nve->tunnel_index); 432 if (err) 433 goto err_promote_decap; 434 435 return 0; 436 437 err_promote_decap: 438 err_rtdp_set: 439 mlxsw_sp2_nve_vxlan_config_clear(mlxsw_sp); 440 err_config_set: 441 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0); 442 return err; 443 } 444 445 static void mlxsw_sp2_nve_vxlan_fini(struct mlxsw_sp_nve *nve) 446 { 447 struct mlxsw_sp_nve_config *config = &nve->config; 448 struct mlxsw_sp *mlxsw_sp = nve->mlxsw_sp; 449 450 mlxsw_sp_router_nve_demote_decap(mlxsw_sp, config->ul_tb_id, 451 config->ul_proto, &config->ul_sip); 452 mlxsw_sp2_nve_vxlan_config_clear(mlxsw_sp); 453 __mlxsw_sp_nve_inc_parsing_depth_put(mlxsw_sp, 0); 454 } 455 456 const struct mlxsw_sp_nve_ops mlxsw_sp2_nve_vxlan_ops = { 457 .type = MLXSW_SP_NVE_TYPE_VXLAN, 458 .can_offload = mlxsw_sp_nve_vxlan_can_offload, 459 .nve_config = mlxsw_sp_nve_vxlan_config, 460 .init = mlxsw_sp2_nve_vxlan_init, 461 .fini = mlxsw_sp2_nve_vxlan_fini, 462 .fdb_replay = mlxsw_sp_nve_vxlan_fdb_replay, 463 .fdb_clear_offload = mlxsw_sp_nve_vxlan_clear_offload, 464 }; 465