1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2017-2018 Mellanox Technologies. All rights reserved */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include "spectrum.h"
7 #include "item.h"
8 #include "core_acl_flex_keys.h"
9 
10 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_dmac[] = {
11 	MLXSW_AFK_ELEMENT_INST_BUF(DMAC_32_47, 0x00, 2),
12 	MLXSW_AFK_ELEMENT_INST_BUF(DMAC_0_31, 0x02, 4),
13 	MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 13, 3),
14 	MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
15 	MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
16 };
17 
18 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_smac[] = {
19 	MLXSW_AFK_ELEMENT_INST_BUF(SMAC_32_47, 0x00, 2),
20 	MLXSW_AFK_ELEMENT_INST_BUF(SMAC_0_31, 0x02, 4),
21 	MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 13, 3),
22 	MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
23 	MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
24 };
25 
26 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_smac_ex[] = {
27 	MLXSW_AFK_ELEMENT_INST_BUF(SMAC_32_47, 0x02, 2),
28 	MLXSW_AFK_ELEMENT_INST_BUF(SMAC_0_31, 0x04, 4),
29 	MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x0C, 0, 16),
30 };
31 
32 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_sip[] = {
33 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x00, 4),
34 	MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
35 	MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
36 };
37 
38 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_dip[] = {
39 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_0_31, 0x00, 4),
40 	MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
41 	MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
42 };
43 
44 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4[] = {
45 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x00, 4),
46 	MLXSW_AFK_ELEMENT_INST_U32(IP_ECN, 0x04, 4, 2),
47 	MLXSW_AFK_ELEMENT_INST_U32(IP_TTL_, 0x04, 24, 8),
48 	MLXSW_AFK_ELEMENT_INST_U32(IP_DSCP, 0x08, 0, 6),
49 	MLXSW_AFK_ELEMENT_INST_U32(TCP_FLAGS, 0x08, 8, 9), /* TCP_CONTROL+TCP_ECN */
50 };
51 
52 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_ex[] = {
53 	MLXSW_AFK_ELEMENT_INST_U32(VID, 0x00, 0, 12),
54 	MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 29, 3),
55 	MLXSW_AFK_ELEMENT_INST_U32(SRC_L4_PORT, 0x08, 0, 16),
56 	MLXSW_AFK_ELEMENT_INST_U32(DST_L4_PORT, 0x0C, 0, 16),
57 };
58 
59 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_dip[] = {
60 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_32_63, 0x00, 4),
61 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_0_31, 0x04, 4),
62 };
63 
64 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_ex1[] = {
65 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_96_127, 0x00, 4),
66 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_64_95, 0x04, 4),
67 	MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
68 };
69 
70 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_sip[] = {
71 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_32_63, 0x00, 4),
72 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x04, 4),
73 };
74 
75 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_sip_ex[] = {
76 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_96_127, 0x00, 4),
77 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_64_95, 0x04, 4),
78 };
79 
80 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_packet_type[] = {
81 	MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x00, 0, 16),
82 };
83 
84 static const struct mlxsw_afk_block mlxsw_sp1_afk_blocks[] = {
85 	MLXSW_AFK_BLOCK(0x10, mlxsw_sp_afk_element_info_l2_dmac),
86 	MLXSW_AFK_BLOCK(0x11, mlxsw_sp_afk_element_info_l2_smac),
87 	MLXSW_AFK_BLOCK(0x12, mlxsw_sp_afk_element_info_l2_smac_ex),
88 	MLXSW_AFK_BLOCK(0x30, mlxsw_sp_afk_element_info_ipv4_sip),
89 	MLXSW_AFK_BLOCK(0x31, mlxsw_sp_afk_element_info_ipv4_dip),
90 	MLXSW_AFK_BLOCK(0x32, mlxsw_sp_afk_element_info_ipv4),
91 	MLXSW_AFK_BLOCK(0x33, mlxsw_sp_afk_element_info_ipv4_ex),
92 	MLXSW_AFK_BLOCK(0x60, mlxsw_sp_afk_element_info_ipv6_dip),
93 	MLXSW_AFK_BLOCK(0x65, mlxsw_sp_afk_element_info_ipv6_ex1),
94 	MLXSW_AFK_BLOCK(0x62, mlxsw_sp_afk_element_info_ipv6_sip),
95 	MLXSW_AFK_BLOCK(0x63, mlxsw_sp_afk_element_info_ipv6_sip_ex),
96 	MLXSW_AFK_BLOCK(0xB0, mlxsw_sp_afk_element_info_packet_type),
97 };
98 
99 #define MLXSW_SP1_AFK_KEY_BLOCK_SIZE 16
100 
101 static void mlxsw_sp1_afk_encode_block(char *output, int block_index,
102 				       char *block)
103 {
104 	unsigned int offset = block_index * MLXSW_SP1_AFK_KEY_BLOCK_SIZE;
105 	char *output_indexed = output + offset;
106 
107 	memcpy(output_indexed, block, MLXSW_SP1_AFK_KEY_BLOCK_SIZE);
108 }
109 
110 static void mlxsw_sp1_afk_clear_block(char *output, int block_index)
111 {
112 	unsigned int offset = block_index * MLXSW_SP1_AFK_KEY_BLOCK_SIZE;
113 	char *output_indexed = output + offset;
114 
115 	memset(output_indexed, 0, MLXSW_SP1_AFK_KEY_BLOCK_SIZE);
116 }
117 
118 const struct mlxsw_afk_ops mlxsw_sp1_afk_ops = {
119 	.blocks		= mlxsw_sp1_afk_blocks,
120 	.blocks_count	= ARRAY_SIZE(mlxsw_sp1_afk_blocks),
121 	.encode_block	= mlxsw_sp1_afk_encode_block,
122 	.clear_block	= mlxsw_sp1_afk_clear_block,
123 };
124 
125 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_0[] = {
126 	MLXSW_AFK_ELEMENT_INST_U32(FDB_MISS, 0x00, 3, 1),
127 	MLXSW_AFK_ELEMENT_INST_BUF(DMAC_0_31, 0x04, 4),
128 };
129 
130 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_1[] = {
131 	MLXSW_AFK_ELEMENT_INST_U32(FDB_MISS, 0x00, 3, 1),
132 	MLXSW_AFK_ELEMENT_INST_BUF(SMAC_0_31, 0x04, 4),
133 };
134 
135 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_2[] = {
136 	MLXSW_AFK_ELEMENT_INST_BUF(SMAC_32_47, 0x04, 2),
137 	MLXSW_AFK_ELEMENT_INST_BUF(DMAC_32_47, 0x06, 2),
138 };
139 
140 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_3[] = {
141 	MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x00, 0, 3),
142 	MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
143 	MLXSW_AFK_ELEMENT_INST_BUF(DMAC_32_47, 0x06, 2),
144 };
145 
146 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_4[] = {
147 	MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x00, 0, 3),
148 	MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
149 	MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x04, 0, 16),
150 };
151 
152 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_5[] = {
153 	MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
154 	MLXSW_AFK_ELEMENT_INST_EXT_U32(SRC_SYS_PORT, 0x04, 0, 8, -1, true), /* RX_ACL_SYSTEM_PORT */
155 };
156 
157 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_0[] = {
158 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_0_31, 0x04, 4),
159 };
160 
161 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_1[] = {
162 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x04, 4),
163 };
164 
165 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_2[] = {
166 	MLXSW_AFK_ELEMENT_INST_U32(IP_DSCP, 0x04, 0, 6),
167 	MLXSW_AFK_ELEMENT_INST_U32(IP_ECN, 0x04, 6, 2),
168 	MLXSW_AFK_ELEMENT_INST_U32(IP_TTL_, 0x04, 8, 8),
169 	MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x04, 16, 8),
170 };
171 
172 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_4[] = {
173 	MLXSW_AFK_ELEMENT_INST_U32(VIRT_ROUTER_LSB, 0x04, 24, 8),
174 	MLXSW_AFK_ELEMENT_INST_U32(VIRT_ROUTER_MSB, 0x00, 0, 3),
175 };
176 
177 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_0[] = {
178 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_32_63, 0x04, 4),
179 };
180 
181 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_1[] = {
182 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_64_95, 0x04, 4),
183 };
184 
185 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_2[] = {
186 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_96_127, 0x04, 4),
187 };
188 
189 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_3[] = {
190 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_32_63, 0x04, 4),
191 };
192 
193 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_4[] = {
194 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_64_95, 0x04, 4),
195 };
196 
197 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_5[] = {
198 	MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_96_127, 0x04, 4),
199 };
200 
201 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l4_0[] = {
202 	MLXSW_AFK_ELEMENT_INST_U32(SRC_L4_PORT, 0x04, 16, 16),
203 	MLXSW_AFK_ELEMENT_INST_U32(DST_L4_PORT, 0x04, 0, 16),
204 };
205 
206 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l4_2[] = {
207 	MLXSW_AFK_ELEMENT_INST_U32(TCP_FLAGS, 0x04, 16, 9), /* TCP_CONTROL + TCP_ECN */
208 };
209 
210 static const struct mlxsw_afk_block mlxsw_sp2_afk_blocks[] = {
211 	MLXSW_AFK_BLOCK(0x10, mlxsw_sp_afk_element_info_mac_0),
212 	MLXSW_AFK_BLOCK(0x11, mlxsw_sp_afk_element_info_mac_1),
213 	MLXSW_AFK_BLOCK(0x12, mlxsw_sp_afk_element_info_mac_2),
214 	MLXSW_AFK_BLOCK(0x13, mlxsw_sp_afk_element_info_mac_3),
215 	MLXSW_AFK_BLOCK(0x14, mlxsw_sp_afk_element_info_mac_4),
216 	MLXSW_AFK_BLOCK(0x15, mlxsw_sp_afk_element_info_mac_5),
217 	MLXSW_AFK_BLOCK(0x38, mlxsw_sp_afk_element_info_ipv4_0),
218 	MLXSW_AFK_BLOCK(0x39, mlxsw_sp_afk_element_info_ipv4_1),
219 	MLXSW_AFK_BLOCK(0x3A, mlxsw_sp_afk_element_info_ipv4_2),
220 	MLXSW_AFK_BLOCK(0x3C, mlxsw_sp_afk_element_info_ipv4_4),
221 	MLXSW_AFK_BLOCK(0x40, mlxsw_sp_afk_element_info_ipv6_0),
222 	MLXSW_AFK_BLOCK(0x41, mlxsw_sp_afk_element_info_ipv6_1),
223 	MLXSW_AFK_BLOCK(0x42, mlxsw_sp_afk_element_info_ipv6_2),
224 	MLXSW_AFK_BLOCK(0x43, mlxsw_sp_afk_element_info_ipv6_3),
225 	MLXSW_AFK_BLOCK(0x44, mlxsw_sp_afk_element_info_ipv6_4),
226 	MLXSW_AFK_BLOCK(0x45, mlxsw_sp_afk_element_info_ipv6_5),
227 	MLXSW_AFK_BLOCK(0x90, mlxsw_sp_afk_element_info_l4_0),
228 	MLXSW_AFK_BLOCK(0x92, mlxsw_sp_afk_element_info_l4_2),
229 };
230 
231 #define MLXSW_SP2_AFK_BITS_PER_BLOCK 36
232 
233 /* A block in Spectrum-2 is of the following form:
234  *
235  * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
236  * |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |35|34|33|32|
237  * +-----------------------------------------------------------------------------------------------+
238  * |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
239  * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
240  */
241 MLXSW_ITEM64(sp2_afk, block, value, 0x00, 0, MLXSW_SP2_AFK_BITS_PER_BLOCK);
242 
243 /* The key / mask block layout in Spectrum-2 is of the following form:
244  *
245  * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
246  * |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |                block11_high                   |
247  * +-----------------------------------------------------------------------------------------------+
248  * |                    block11_low                               |         block10_high           |
249  * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
250  * ...
251  */
252 
253 struct mlxsw_sp2_afk_block_layout {
254 	unsigned short offset;
255 	struct mlxsw_item item;
256 };
257 
258 #define MLXSW_SP2_AFK_BLOCK_LAYOUT(_block, _offset, _shift)			\
259 	{									\
260 		.offset = _offset,						\
261 		{								\
262 			.shift = _shift,					\
263 			.size = {.bits = MLXSW_SP2_AFK_BITS_PER_BLOCK},		\
264 			.name = #_block,					\
265 		}								\
266 	}									\
267 
268 static const struct mlxsw_sp2_afk_block_layout mlxsw_sp2_afk_blocks_layout[] = {
269 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block0, 0x30, 0),
270 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block1, 0x2C, 4),
271 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block2, 0x28, 8),
272 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block3, 0x24, 12),
273 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block4, 0x20, 16),
274 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block5, 0x1C, 20),
275 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block6, 0x18, 24),
276 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block7, 0x14, 28),
277 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block8, 0x0C, 0),
278 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block9, 0x08, 4),
279 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block10, 0x04, 8),
280 	MLXSW_SP2_AFK_BLOCK_LAYOUT(block11, 0x00, 12),
281 };
282 
283 static void __mlxsw_sp2_afk_block_value_set(char *output, int block_index,
284 					    u64 block_value)
285 {
286 	const struct mlxsw_sp2_afk_block_layout *block_layout;
287 
288 	if (WARN_ON(block_index < 0 ||
289 		    block_index >= ARRAY_SIZE(mlxsw_sp2_afk_blocks_layout)))
290 		return;
291 
292 	block_layout = &mlxsw_sp2_afk_blocks_layout[block_index];
293 	__mlxsw_item_set64(output + block_layout->offset,
294 			   &block_layout->item, 0, block_value);
295 }
296 
297 static void mlxsw_sp2_afk_encode_block(char *output, int block_index,
298 				       char *block)
299 {
300 	u64 block_value = mlxsw_sp2_afk_block_value_get(block);
301 
302 	__mlxsw_sp2_afk_block_value_set(output, block_index, block_value);
303 }
304 
305 static void mlxsw_sp2_afk_clear_block(char *output, int block_index)
306 {
307 	__mlxsw_sp2_afk_block_value_set(output, block_index, 0);
308 }
309 
310 const struct mlxsw_afk_ops mlxsw_sp2_afk_ops = {
311 	.blocks		= mlxsw_sp2_afk_blocks,
312 	.blocks_count	= ARRAY_SIZE(mlxsw_sp2_afk_blocks),
313 	.encode_block	= mlxsw_sp2_afk_encode_block,
314 	.clear_block	= mlxsw_sp2_afk_clear_block,
315 };
316 
317 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_5b[] = {
318 	MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 18, 12),
319 	MLXSW_AFK_ELEMENT_INST_EXT_U32(SRC_SYS_PORT, 0x04, 0, 9, -1, true), /* RX_ACL_SYSTEM_PORT */
320 };
321 
322 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_4b[] = {
323 	MLXSW_AFK_ELEMENT_INST_U32(VIRT_ROUTER_LSB, 0x04, 13, 8),
324 	MLXSW_AFK_ELEMENT_INST_EXT_U32(VIRT_ROUTER_MSB, 0x04, 21, 4, 0, true),
325 };
326 
327 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_2b[] = {
328 	MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_96_127, 0x04, 4),
329 };
330 
331 static const struct mlxsw_afk_block mlxsw_sp4_afk_blocks[] = {
332 	MLXSW_AFK_BLOCK(0x10, mlxsw_sp_afk_element_info_mac_0),
333 	MLXSW_AFK_BLOCK(0x11, mlxsw_sp_afk_element_info_mac_1),
334 	MLXSW_AFK_BLOCK(0x12, mlxsw_sp_afk_element_info_mac_2),
335 	MLXSW_AFK_BLOCK(0x13, mlxsw_sp_afk_element_info_mac_3),
336 	MLXSW_AFK_BLOCK(0x14, mlxsw_sp_afk_element_info_mac_4),
337 	MLXSW_AFK_BLOCK(0x1A, mlxsw_sp_afk_element_info_mac_5b),
338 	MLXSW_AFK_BLOCK(0x38, mlxsw_sp_afk_element_info_ipv4_0),
339 	MLXSW_AFK_BLOCK(0x39, mlxsw_sp_afk_element_info_ipv4_1),
340 	MLXSW_AFK_BLOCK(0x3A, mlxsw_sp_afk_element_info_ipv4_2),
341 	MLXSW_AFK_BLOCK(0x35, mlxsw_sp_afk_element_info_ipv4_4b),
342 	MLXSW_AFK_BLOCK(0x40, mlxsw_sp_afk_element_info_ipv6_0),
343 	MLXSW_AFK_BLOCK(0x41, mlxsw_sp_afk_element_info_ipv6_1),
344 	MLXSW_AFK_BLOCK(0x47, mlxsw_sp_afk_element_info_ipv6_2b),
345 	MLXSW_AFK_BLOCK(0x43, mlxsw_sp_afk_element_info_ipv6_3),
346 	MLXSW_AFK_BLOCK(0x44, mlxsw_sp_afk_element_info_ipv6_4),
347 	MLXSW_AFK_BLOCK(0x45, mlxsw_sp_afk_element_info_ipv6_5),
348 	MLXSW_AFK_BLOCK(0x90, mlxsw_sp_afk_element_info_l4_0),
349 	MLXSW_AFK_BLOCK(0x92, mlxsw_sp_afk_element_info_l4_2),
350 };
351 
352 const struct mlxsw_afk_ops mlxsw_sp4_afk_ops = {
353 	.blocks		= mlxsw_sp4_afk_blocks,
354 	.blocks_count	= ARRAY_SIZE(mlxsw_sp4_afk_blocks),
355 	.encode_block	= mlxsw_sp2_afk_encode_block,
356 	.clear_block	= mlxsw_sp2_afk_clear_block,
357 };
358