1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c 3 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the names of the copyright holders nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") version 2 as published by the Free 22 * Software Foundation. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/types.h> 40 #include <linux/pci.h> 41 #include <linux/netdevice.h> 42 #include <linux/etherdevice.h> 43 #include <linux/ethtool.h> 44 #include <linux/slab.h> 45 #include <linux/device.h> 46 #include <linux/skbuff.h> 47 #include <linux/if_vlan.h> 48 #include <linux/if_bridge.h> 49 #include <linux/workqueue.h> 50 #include <linux/jiffies.h> 51 #include <linux/bitops.h> 52 #include <linux/list.h> 53 #include <linux/notifier.h> 54 #include <linux/dcbnl.h> 55 #include <linux/inetdevice.h> 56 #include <linux/netlink.h> 57 #include <net/switchdev.h> 58 #include <net/pkt_cls.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/netevent.h> 61 #include <net/tc_act/tc_sample.h> 62 #include <net/addrconf.h> 63 64 #include "spectrum.h" 65 #include "pci.h" 66 #include "core.h" 67 #include "reg.h" 68 #include "port.h" 69 #include "trap.h" 70 #include "txheader.h" 71 #include "spectrum_cnt.h" 72 #include "spectrum_dpipe.h" 73 #include "spectrum_acl_flex_actions.h" 74 #include "spectrum_span.h" 75 #include "../mlxfw/mlxfw.h" 76 77 #define MLXSW_FWREV_MAJOR 13 78 #define MLXSW_FWREV_MINOR 1620 79 #define MLXSW_FWREV_SUBMINOR 192 80 #define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100) 81 82 #define MLXSW_SP_FW_FILENAME \ 83 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \ 84 "." __stringify(MLXSW_FWREV_MINOR) \ 85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2" 86 87 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum"; 88 static const char mlxsw_sp_driver_version[] = "1.0"; 89 90 /* tx_hdr_version 91 * Tx header version. 92 * Must be set to 1. 93 */ 94 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 95 96 /* tx_hdr_ctl 97 * Packet control type. 98 * 0 - Ethernet control (e.g. EMADs, LACP) 99 * 1 - Ethernet data 100 */ 101 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 102 103 /* tx_hdr_proto 104 * Packet protocol type. Must be set to 1 (Ethernet). 105 */ 106 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 107 108 /* tx_hdr_rx_is_router 109 * Packet is sent from the router. Valid for data packets only. 110 */ 111 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 112 113 /* tx_hdr_fid_valid 114 * Indicates if the 'fid' field is valid and should be used for 115 * forwarding lookup. Valid for data packets only. 116 */ 117 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 118 119 /* tx_hdr_swid 120 * Switch partition ID. Must be set to 0. 121 */ 122 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 123 124 /* tx_hdr_control_tclass 125 * Indicates if the packet should use the control TClass and not one 126 * of the data TClasses. 127 */ 128 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 129 130 /* tx_hdr_etclass 131 * Egress TClass to be used on the egress device on the egress port. 132 */ 133 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 134 135 /* tx_hdr_port_mid 136 * Destination local port for unicast packets. 137 * Destination multicast ID for multicast packets. 138 * 139 * Control packets are directed to a specific egress port, while data 140 * packets are transmitted through the CPU port (0) into the switch partition, 141 * where forwarding rules are applied. 142 */ 143 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 144 145 /* tx_hdr_fid 146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 147 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 148 * Valid for data packets only. 149 */ 150 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 151 152 /* tx_hdr_type 153 * 0 - Data packets 154 * 6 - Control packets 155 */ 156 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 157 158 struct mlxsw_sp_mlxfw_dev { 159 struct mlxfw_dev mlxfw_dev; 160 struct mlxsw_sp *mlxsw_sp; 161 }; 162 163 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev, 164 u16 component_index, u32 *p_max_size, 165 u8 *p_align_bits, u16 *p_max_write_size) 166 { 167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 170 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 171 int err; 172 173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl); 175 if (err) 176 return err; 177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, 178 p_max_write_size); 179 180 *p_align_bits = max_t(u8, *p_align_bits, 2); 181 *p_max_write_size = min_t(u16, *p_max_write_size, 182 MLXSW_REG_MCDA_MAX_DATA_LEN); 183 return 0; 184 } 185 186 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 187 { 188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 191 char mcc_pl[MLXSW_REG_MCC_LEN]; 192 u8 control_state; 193 int err; 194 195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 197 if (err) 198 return err; 199 200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 201 if (control_state != MLXFW_FSM_STATE_IDLE) 202 return -EBUSY; 203 204 mlxsw_reg_mcc_pack(mcc_pl, 205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 206 0, *fwhandle, 0); 207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 208 } 209 210 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev, 211 u32 fwhandle, u16 component_index, 212 u32 component_size) 213 { 214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 217 char mcc_pl[MLXSW_REG_MCC_LEN]; 218 219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 220 component_index, fwhandle, component_size); 221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 222 } 223 224 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev, 225 u32 fwhandle, u8 *data, u16 size, 226 u32 offset) 227 { 228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 231 char mcda_pl[MLXSW_REG_MCDA_LEN]; 232 233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl); 235 } 236 237 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, 238 u32 fwhandle, u16 component_index) 239 { 240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 243 char mcc_pl[MLXSW_REG_MCC_LEN]; 244 245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 246 component_index, fwhandle, 0); 247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 248 } 249 250 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 251 { 252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 255 char mcc_pl[MLXSW_REG_MCC_LEN]; 256 257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, 258 fwhandle, 0); 259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 260 } 261 262 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 263 enum mlxfw_fsm_state *fsm_state, 264 enum mlxfw_fsm_state_err *fsm_state_err) 265 { 266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 269 char mcc_pl[MLXSW_REG_MCC_LEN]; 270 u8 control_state; 271 u8 error_code; 272 int err; 273 274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 276 if (err) 277 return err; 278 279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 280 *fsm_state = control_state; 281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 282 MLXFW_FSM_STATE_ERR_MAX); 283 return 0; 284 } 285 286 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 287 { 288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 291 char mcc_pl[MLXSW_REG_MCC_LEN]; 292 293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, 294 fwhandle, 0); 295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 296 } 297 298 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 299 { 300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 303 char mcc_pl[MLXSW_REG_MCC_LEN]; 304 305 mlxsw_reg_mcc_pack(mcc_pl, 306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 307 fwhandle, 0); 308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 309 } 310 311 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = { 312 .component_query = mlxsw_sp_component_query, 313 .fsm_lock = mlxsw_sp_fsm_lock, 314 .fsm_component_update = mlxsw_sp_fsm_component_update, 315 .fsm_block_download = mlxsw_sp_fsm_block_download, 316 .fsm_component_verify = mlxsw_sp_fsm_component_verify, 317 .fsm_activate = mlxsw_sp_fsm_activate, 318 .fsm_query_state = mlxsw_sp_fsm_query_state, 319 .fsm_cancel = mlxsw_sp_fsm_cancel, 320 .fsm_release = mlxsw_sp_fsm_release 321 }; 322 323 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp, 324 const struct firmware *firmware) 325 { 326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = { 327 .mlxfw_dev = { 328 .ops = &mlxsw_sp_mlxfw_dev_ops, 329 .psid = mlxsw_sp->bus_info->psid, 330 .psid_size = strlen(mlxsw_sp->bus_info->psid), 331 }, 332 .mlxsw_sp = mlxsw_sp 333 }; 334 335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware); 336 } 337 338 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp) 339 { 340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev; 341 const struct firmware *firmware; 342 int err; 343 344 /* Validate driver & FW are compatible */ 345 if (rev->major != MLXSW_FWREV_MAJOR) { 346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 347 rev->major, MLXSW_FWREV_MAJOR); 348 return -EINVAL; 349 } 350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) == 351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR)) 352 return 0; 353 354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n", 355 rev->major, rev->minor, rev->subminor); 356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n", 357 MLXSW_SP_FW_FILENAME); 358 359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME, 360 mlxsw_sp->bus_info->dev); 361 if (err) { 362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n", 363 MLXSW_SP_FW_FILENAME); 364 return err; 365 } 366 367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 368 release_firmware(firmware); 369 return err; 370 } 371 372 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 373 unsigned int counter_index, u64 *packets, 374 u64 *bytes) 375 { 376 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 377 int err; 378 379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 382 if (err) 383 return err; 384 if (packets) 385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 386 if (bytes) 387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 388 return 0; 389 } 390 391 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 392 unsigned int counter_index) 393 { 394 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 395 396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 399 } 400 401 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 402 unsigned int *p_counter_index) 403 { 404 int err; 405 406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 407 p_counter_index); 408 if (err) 409 return err; 410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 411 if (err) 412 goto err_counter_clear; 413 return 0; 414 415 err_counter_clear: 416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 417 *p_counter_index); 418 return err; 419 } 420 421 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 422 unsigned int counter_index) 423 { 424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 425 counter_index); 426 } 427 428 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 429 const struct mlxsw_tx_info *tx_info) 430 { 431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 432 433 memset(txhdr, 0, MLXSW_TXHDR_LEN); 434 435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 438 mlxsw_tx_hdr_swid_set(txhdr, 0); 439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 442 } 443 444 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 445 { 446 switch (state) { 447 case BR_STATE_FORWARDING: 448 return MLXSW_REG_SPMS_STATE_FORWARDING; 449 case BR_STATE_LEARNING: 450 return MLXSW_REG_SPMS_STATE_LEARNING; 451 case BR_STATE_LISTENING: /* fall-through */ 452 case BR_STATE_DISABLED: /* fall-through */ 453 case BR_STATE_BLOCKING: 454 return MLXSW_REG_SPMS_STATE_DISCARDING; 455 default: 456 BUG(); 457 } 458 } 459 460 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 461 u8 state) 462 { 463 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 464 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 465 char *spms_pl; 466 int err; 467 468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 469 if (!spms_pl) 470 return -ENOMEM; 471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 473 474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 475 kfree(spms_pl); 476 return err; 477 } 478 479 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 480 { 481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 482 int err; 483 484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 485 if (err) 486 return err; 487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 488 return 0; 489 } 490 491 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port, 492 bool enable, u32 rate) 493 { 494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 495 char mpsc_pl[MLXSW_REG_MPSC_LEN]; 496 497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate); 498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl); 499 } 500 501 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 502 bool is_up) 503 { 504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 505 char paos_pl[MLXSW_REG_PAOS_LEN]; 506 507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 509 MLXSW_PORT_ADMIN_STATUS_DOWN); 510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 511 } 512 513 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 514 unsigned char *addr) 515 { 516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 517 char ppad_pl[MLXSW_REG_PPAD_LEN]; 518 519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 522 } 523 524 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 525 { 526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr; 528 529 ether_addr_copy(addr, mlxsw_sp->base_mac); 530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port; 531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr); 532 } 533 534 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 535 { 536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 537 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 538 int max_mtu; 539 int err; 540 541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 544 if (err) 545 return err; 546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 547 548 if (mtu > max_mtu) 549 return -EINVAL; 550 551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 553 } 554 555 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid) 556 { 557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 558 char pspa_pl[MLXSW_REG_PSPA_LEN]; 559 560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port); 561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 562 } 563 564 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 565 { 566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 567 char svpe_pl[MLXSW_REG_SVPE_LEN]; 568 569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 571 } 572 573 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 574 bool learn_enable) 575 { 576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 577 char *spvmlr_pl; 578 int err; 579 580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 581 if (!spvmlr_pl) 582 return -ENOMEM; 583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 584 learn_enable); 585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 586 kfree(spvmlr_pl); 587 return err; 588 } 589 590 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 591 u16 vid) 592 { 593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 594 char spvid_pl[MLXSW_REG_SPVID_LEN]; 595 596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); 597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 598 } 599 600 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 601 bool allow) 602 { 603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 604 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 605 606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 608 } 609 610 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 611 { 612 int err; 613 614 if (!vid) { 615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 616 if (err) 617 return err; 618 } else { 619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid); 620 if (err) 621 return err; 622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 623 if (err) 624 goto err_port_allow_untagged_set; 625 } 626 627 mlxsw_sp_port->pvid = vid; 628 return 0; 629 630 err_port_allow_untagged_set: 631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid); 632 return err; 633 } 634 635 static int 636 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 637 { 638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 639 char sspr_pl[MLXSW_REG_SSPR_LEN]; 640 641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 643 } 644 645 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, 646 u8 local_port, u8 *p_module, 647 u8 *p_width, u8 *p_lane) 648 { 649 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 650 int err; 651 652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 654 if (err) 655 return err; 656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); 658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 659 return 0; 660 } 661 662 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port, 663 u8 module, u8 width, u8 lane) 664 { 665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 666 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 667 int i; 668 669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 670 mlxsw_reg_pmlp_width_set(pmlp_pl, width); 671 for (i = 0; i < width; i++) { 672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); 673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ 674 } 675 676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 677 } 678 679 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port) 680 { 681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 682 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 683 684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 687 } 688 689 static int mlxsw_sp_port_open(struct net_device *dev) 690 { 691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 692 int err; 693 694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 695 if (err) 696 return err; 697 netif_start_queue(dev); 698 return 0; 699 } 700 701 static int mlxsw_sp_port_stop(struct net_device *dev) 702 { 703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 704 705 netif_stop_queue(dev); 706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 707 } 708 709 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 710 struct net_device *dev) 711 { 712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 715 const struct mlxsw_tx_info tx_info = { 716 .local_port = mlxsw_sp_port->local_port, 717 .is_emad = false, 718 }; 719 u64 len; 720 int err; 721 722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 723 return NETDEV_TX_BUSY; 724 725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) { 726 struct sk_buff *skb_orig = skb; 727 728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN); 729 if (!skb) { 730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 731 dev_kfree_skb_any(skb_orig); 732 return NETDEV_TX_OK; 733 } 734 dev_consume_skb_any(skb_orig); 735 } 736 737 if (eth_skb_pad(skb)) { 738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 739 return NETDEV_TX_OK; 740 } 741 742 mlxsw_sp_txhdr_construct(skb, &tx_info); 743 /* TX header is consumed by HW on the way so we shouldn't count its 744 * bytes as being sent. 745 */ 746 len = skb->len - MLXSW_TXHDR_LEN; 747 748 /* Due to a race we might fail here because of a full queue. In that 749 * unlikely case we simply drop the packet. 750 */ 751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 752 753 if (!err) { 754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 755 u64_stats_update_begin(&pcpu_stats->syncp); 756 pcpu_stats->tx_packets++; 757 pcpu_stats->tx_bytes += len; 758 u64_stats_update_end(&pcpu_stats->syncp); 759 } else { 760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 761 dev_kfree_skb_any(skb); 762 } 763 return NETDEV_TX_OK; 764 } 765 766 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 767 { 768 } 769 770 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 771 { 772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 773 struct sockaddr *addr = p; 774 int err; 775 776 if (!is_valid_ether_addr(addr->sa_data)) 777 return -EADDRNOTAVAIL; 778 779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 780 if (err) 781 return err; 782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 783 return 0; 784 } 785 786 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp, 787 int mtu) 788 { 789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu); 790 } 791 792 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ 793 794 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 795 u16 delay) 796 { 797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay, 798 BITS_PER_BYTE)); 799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp, 800 mtu); 801 } 802 803 /* Maximum delay buffer needed in case of PAUSE frames, in bytes. 804 * Assumes 100m cable and maximum MTU. 805 */ 806 #define MLXSW_SP_PAUSE_DELAY 58752 807 808 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 809 u16 delay, bool pfc, bool pause) 810 { 811 if (pfc) 812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay); 813 else if (pause) 814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY); 815 else 816 return 0; 817 } 818 819 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres, 820 bool lossy) 821 { 822 if (lossy) 823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size); 824 else 825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size, 826 thres); 827 } 828 829 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, 830 u8 *prio_tc, bool pause_en, 831 struct ieee_pfc *my_pfc) 832 { 833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0; 835 u16 delay = !!my_pfc ? my_pfc->delay : 0; 836 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 837 int i, j, err; 838 839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0); 840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 841 if (err) 842 return err; 843 844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 845 bool configure = false; 846 bool pfc = false; 847 bool lossy; 848 u16 thres; 849 850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) { 851 if (prio_tc[j] == i) { 852 pfc = pfc_en & BIT(j); 853 configure = true; 854 break; 855 } 856 } 857 858 if (!configure) 859 continue; 860 861 lossy = !(pfc || pause_en); 862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu); 863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc, 864 pause_en); 865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy); 866 } 867 868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 869 } 870 871 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, 872 int mtu, bool pause_en) 873 { 874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0}; 875 bool dcb_en = !!mlxsw_sp_port->dcb.ets; 876 struct ieee_pfc *my_pfc; 877 u8 *prio_tc; 878 879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc; 880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL; 881 882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc, 883 pause_en, my_pfc); 884 } 885 886 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 887 { 888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 890 int err; 891 892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en); 893 if (err) 894 return err; 895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu); 896 if (err) 897 goto err_span_port_mtu_update; 898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 899 if (err) 900 goto err_port_mtu_set; 901 dev->mtu = mtu; 902 return 0; 903 904 err_port_mtu_set: 905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu); 906 err_span_port_mtu_update: 907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 908 return err; 909 } 910 911 static int 912 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 913 struct rtnl_link_stats64 *stats) 914 { 915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 916 struct mlxsw_sp_port_pcpu_stats *p; 917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 918 u32 tx_dropped = 0; 919 unsigned int start; 920 int i; 921 922 for_each_possible_cpu(i) { 923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 924 do { 925 start = u64_stats_fetch_begin_irq(&p->syncp); 926 rx_packets = p->rx_packets; 927 rx_bytes = p->rx_bytes; 928 tx_packets = p->tx_packets; 929 tx_bytes = p->tx_bytes; 930 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 931 932 stats->rx_packets += rx_packets; 933 stats->rx_bytes += rx_bytes; 934 stats->tx_packets += tx_packets; 935 stats->tx_bytes += tx_bytes; 936 /* tx_dropped is u32, updated without syncp protection. */ 937 tx_dropped += p->tx_dropped; 938 } 939 stats->tx_dropped = tx_dropped; 940 return 0; 941 } 942 943 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 944 { 945 switch (attr_id) { 946 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 947 return true; 948 } 949 950 return false; 951 } 952 953 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 954 void *sp) 955 { 956 switch (attr_id) { 957 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 958 return mlxsw_sp_port_get_sw_stats64(dev, sp); 959 } 960 961 return -EINVAL; 962 } 963 964 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 965 int prio, char *ppcnt_pl) 966 { 967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 969 970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 972 } 973 974 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 975 struct rtnl_link_stats64 *stats) 976 { 977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 978 int err; 979 980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 981 0, ppcnt_pl); 982 if (err) 983 goto out; 984 985 stats->tx_packets = 986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 987 stats->rx_packets = 988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 989 stats->tx_bytes = 990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 991 stats->rx_bytes = 992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 993 stats->multicast = 994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 995 996 stats->rx_crc_errors = 997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 998 stats->rx_frame_errors = 999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 1000 1001 stats->rx_length_errors = ( 1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 1005 1006 stats->rx_errors = (stats->rx_crc_errors + 1007 stats->rx_frame_errors + stats->rx_length_errors); 1008 1009 out: 1010 return err; 1011 } 1012 1013 static void 1014 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 1015 struct mlxsw_sp_port_xstats *xstats) 1016 { 1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1018 int err, i; 1019 1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 1021 ppcnt_pl); 1022 if (!err) 1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 1024 1025 for (i = 0; i < TC_MAX_QUEUE; i++) { 1026 err = mlxsw_sp_port_get_stats_raw(dev, 1027 MLXSW_REG_PPCNT_TC_CONG_TC, 1028 i, ppcnt_pl); 1029 if (!err) 1030 xstats->wred_drop[i] = 1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 1032 1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 1034 i, ppcnt_pl); 1035 if (err) 1036 continue; 1037 1038 xstats->backlog[i] = 1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 1040 xstats->tail_drop[i] = 1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 1042 } 1043 1044 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1045 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 1046 i, ppcnt_pl); 1047 if (err) 1048 continue; 1049 1050 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 1051 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 1052 } 1053 } 1054 1055 static void update_stats_cache(struct work_struct *work) 1056 { 1057 struct mlxsw_sp_port *mlxsw_sp_port = 1058 container_of(work, struct mlxsw_sp_port, 1059 periodic_hw_stats.update_dw.work); 1060 1061 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 1062 goto out; 1063 1064 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 1065 &mlxsw_sp_port->periodic_hw_stats.stats); 1066 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 1067 &mlxsw_sp_port->periodic_hw_stats.xstats); 1068 1069 out: 1070 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1071 MLXSW_HW_STATS_UPDATE_TIME); 1072 } 1073 1074 /* Return the stats from a cache that is updated periodically, 1075 * as this function might get called in an atomic context. 1076 */ 1077 static void 1078 mlxsw_sp_port_get_stats64(struct net_device *dev, 1079 struct rtnl_link_stats64 *stats) 1080 { 1081 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1082 1083 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 1084 } 1085 1086 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 1087 u16 vid_begin, u16 vid_end, 1088 bool is_member, bool untagged) 1089 { 1090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1091 char *spvm_pl; 1092 int err; 1093 1094 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1095 if (!spvm_pl) 1096 return -ENOMEM; 1097 1098 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1099 vid_end, is_member, untagged); 1100 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1101 kfree(spvm_pl); 1102 return err; 1103 } 1104 1105 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1106 u16 vid_end, bool is_member, bool untagged) 1107 { 1108 u16 vid, vid_e; 1109 int err; 1110 1111 for (vid = vid_begin; vid <= vid_end; 1112 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1113 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1114 vid_end); 1115 1116 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1117 is_member, untagged); 1118 if (err) 1119 return err; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port) 1126 { 1127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1128 1129 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1130 &mlxsw_sp_port->vlans_list, list) 1131 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1132 } 1133 1134 static struct mlxsw_sp_port_vlan * 1135 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1136 { 1137 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1138 bool untagged = vid == 1; 1139 int err; 1140 1141 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1142 if (err) 1143 return ERR_PTR(err); 1144 1145 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1146 if (!mlxsw_sp_port_vlan) { 1147 err = -ENOMEM; 1148 goto err_port_vlan_alloc; 1149 } 1150 1151 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1152 mlxsw_sp_port_vlan->ref_count = 1; 1153 mlxsw_sp_port_vlan->vid = vid; 1154 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1155 1156 return mlxsw_sp_port_vlan; 1157 1158 err_port_vlan_alloc: 1159 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1160 return ERR_PTR(err); 1161 } 1162 1163 static void 1164 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1165 { 1166 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1167 u16 vid = mlxsw_sp_port_vlan->vid; 1168 1169 list_del(&mlxsw_sp_port_vlan->list); 1170 kfree(mlxsw_sp_port_vlan); 1171 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1172 } 1173 1174 struct mlxsw_sp_port_vlan * 1175 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1176 { 1177 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1178 1179 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1180 if (mlxsw_sp_port_vlan) { 1181 mlxsw_sp_port_vlan->ref_count++; 1182 return mlxsw_sp_port_vlan; 1183 } 1184 1185 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid); 1186 } 1187 1188 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1189 { 1190 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid; 1191 1192 if (--mlxsw_sp_port_vlan->ref_count != 0) 1193 return; 1194 1195 if (mlxsw_sp_port_vlan->bridge_port) 1196 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1197 else if (fid) 1198 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1199 1200 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1201 } 1202 1203 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1204 __be16 __always_unused proto, u16 vid) 1205 { 1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1207 1208 /* VLAN 0 is added to HW filter when device goes up, but it is 1209 * reserved in our case, so simply return. 1210 */ 1211 if (!vid) 1212 return 0; 1213 1214 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid)); 1215 } 1216 1217 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1218 __be16 __always_unused proto, u16 vid) 1219 { 1220 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1221 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1222 1223 /* VLAN 0 is removed from HW filter when device goes down, but 1224 * it is reserved in our case, so simply return. 1225 */ 1226 if (!vid) 1227 return 0; 1228 1229 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1230 if (!mlxsw_sp_port_vlan) 1231 return 0; 1232 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1233 1234 return 0; 1235 } 1236 1237 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name, 1238 size_t len) 1239 { 1240 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1241 1242 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core, 1243 mlxsw_sp_port->local_port, 1244 name, len); 1245 } 1246 1247 static struct mlxsw_sp_port_mall_tc_entry * 1248 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port, 1249 unsigned long cookie) { 1250 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1251 1252 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list) 1253 if (mall_tc_entry->cookie == cookie) 1254 return mall_tc_entry; 1255 1256 return NULL; 1257 } 1258 1259 static int 1260 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1261 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror, 1262 const struct tc_action *a, 1263 bool ingress) 1264 { 1265 enum mlxsw_sp_span_type span_type; 1266 struct net_device *to_dev; 1267 1268 to_dev = tcf_mirred_dev(a); 1269 if (!to_dev) { 1270 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n"); 1271 return -EINVAL; 1272 } 1273 1274 mirror->ingress = ingress; 1275 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1276 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type, 1277 true, &mirror->span_id); 1278 } 1279 1280 static void 1281 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1282 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror) 1283 { 1284 enum mlxsw_sp_span_type span_type; 1285 1286 span_type = mirror->ingress ? 1287 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1288 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id, 1289 span_type, true); 1290 } 1291 1292 static int 1293 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port, 1294 struct tc_cls_matchall_offload *cls, 1295 const struct tc_action *a, 1296 bool ingress) 1297 { 1298 int err; 1299 1300 if (!mlxsw_sp_port->sample) 1301 return -EOPNOTSUPP; 1302 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) { 1303 netdev_err(mlxsw_sp_port->dev, "sample already active\n"); 1304 return -EEXIST; 1305 } 1306 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) { 1307 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n"); 1308 return -EOPNOTSUPP; 1309 } 1310 1311 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group, 1312 tcf_sample_psample_group(a)); 1313 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a); 1314 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a); 1315 mlxsw_sp_port->sample->rate = tcf_sample_rate(a); 1316 1317 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a)); 1318 if (err) 1319 goto err_port_sample_set; 1320 return 0; 1321 1322 err_port_sample_set: 1323 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1324 return err; 1325 } 1326 1327 static void 1328 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port) 1329 { 1330 if (!mlxsw_sp_port->sample) 1331 return; 1332 1333 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1); 1334 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1335 } 1336 1337 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1338 struct tc_cls_matchall_offload *f, 1339 bool ingress) 1340 { 1341 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1342 __be16 protocol = f->common.protocol; 1343 const struct tc_action *a; 1344 LIST_HEAD(actions); 1345 int err; 1346 1347 if (!tcf_exts_has_one_action(f->exts)) { 1348 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n"); 1349 return -EOPNOTSUPP; 1350 } 1351 1352 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL); 1353 if (!mall_tc_entry) 1354 return -ENOMEM; 1355 mall_tc_entry->cookie = f->cookie; 1356 1357 tcf_exts_to_list(f->exts, &actions); 1358 a = list_first_entry(&actions, struct tc_action, list); 1359 1360 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) { 1361 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror; 1362 1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR; 1364 mirror = &mall_tc_entry->mirror; 1365 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, 1366 mirror, a, ingress); 1367 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) { 1368 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE; 1369 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f, 1370 a, ingress); 1371 } else { 1372 err = -EOPNOTSUPP; 1373 } 1374 1375 if (err) 1376 goto err_add_action; 1377 1378 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list); 1379 return 0; 1380 1381 err_add_action: 1382 kfree(mall_tc_entry); 1383 return err; 1384 } 1385 1386 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1387 struct tc_cls_matchall_offload *f) 1388 { 1389 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1390 1391 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port, 1392 f->cookie); 1393 if (!mall_tc_entry) { 1394 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n"); 1395 return; 1396 } 1397 list_del(&mall_tc_entry->list); 1398 1399 switch (mall_tc_entry->type) { 1400 case MLXSW_SP_PORT_MALL_MIRROR: 1401 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port, 1402 &mall_tc_entry->mirror); 1403 break; 1404 case MLXSW_SP_PORT_MALL_SAMPLE: 1405 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port); 1406 break; 1407 default: 1408 WARN_ON(1); 1409 } 1410 1411 kfree(mall_tc_entry); 1412 } 1413 1414 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1415 struct tc_cls_matchall_offload *f, 1416 bool ingress) 1417 { 1418 switch (f->command) { 1419 case TC_CLSMATCHALL_REPLACE: 1420 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f, 1421 ingress); 1422 case TC_CLSMATCHALL_DESTROY: 1423 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f); 1424 return 0; 1425 default: 1426 return -EOPNOTSUPP; 1427 } 1428 } 1429 1430 static int 1431 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block, 1432 struct tc_cls_flower_offload *f) 1433 { 1434 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block); 1435 1436 switch (f->command) { 1437 case TC_CLSFLOWER_REPLACE: 1438 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f); 1439 case TC_CLSFLOWER_DESTROY: 1440 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f); 1441 return 0; 1442 case TC_CLSFLOWER_STATS: 1443 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f); 1444 default: 1445 return -EOPNOTSUPP; 1446 } 1447 } 1448 1449 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type, 1450 void *type_data, 1451 void *cb_priv, bool ingress) 1452 { 1453 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv; 1454 1455 switch (type) { 1456 case TC_SETUP_CLSMATCHALL: 1457 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev, 1458 type_data)) 1459 return -EOPNOTSUPP; 1460 1461 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data, 1462 ingress); 1463 case TC_SETUP_CLSFLOWER: 1464 return 0; 1465 default: 1466 return -EOPNOTSUPP; 1467 } 1468 } 1469 1470 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type, 1471 void *type_data, 1472 void *cb_priv) 1473 { 1474 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1475 cb_priv, true); 1476 } 1477 1478 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type, 1479 void *type_data, 1480 void *cb_priv) 1481 { 1482 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1483 cb_priv, false); 1484 } 1485 1486 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type, 1487 void *type_data, void *cb_priv) 1488 { 1489 struct mlxsw_sp_acl_block *acl_block = cb_priv; 1490 1491 switch (type) { 1492 case TC_SETUP_CLSMATCHALL: 1493 return 0; 1494 case TC_SETUP_CLSFLOWER: 1495 if (mlxsw_sp_acl_block_disabled(acl_block)) 1496 return -EOPNOTSUPP; 1497 1498 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data); 1499 default: 1500 return -EOPNOTSUPP; 1501 } 1502 } 1503 1504 static int 1505 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port, 1506 struct tcf_block *block, bool ingress) 1507 { 1508 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1509 struct mlxsw_sp_acl_block *acl_block; 1510 struct tcf_block_cb *block_cb; 1511 int err; 1512 1513 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1514 mlxsw_sp); 1515 if (!block_cb) { 1516 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net); 1517 if (!acl_block) 1518 return -ENOMEM; 1519 block_cb = __tcf_block_cb_register(block, 1520 mlxsw_sp_setup_tc_block_cb_flower, 1521 mlxsw_sp, acl_block); 1522 if (IS_ERR(block_cb)) { 1523 err = PTR_ERR(block_cb); 1524 goto err_cb_register; 1525 } 1526 } else { 1527 acl_block = tcf_block_cb_priv(block_cb); 1528 } 1529 tcf_block_cb_incref(block_cb); 1530 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block, 1531 mlxsw_sp_port, ingress); 1532 if (err) 1533 goto err_block_bind; 1534 1535 if (ingress) 1536 mlxsw_sp_port->ing_acl_block = acl_block; 1537 else 1538 mlxsw_sp_port->eg_acl_block = acl_block; 1539 1540 return 0; 1541 1542 err_block_bind: 1543 if (!tcf_block_cb_decref(block_cb)) { 1544 __tcf_block_cb_unregister(block_cb); 1545 err_cb_register: 1546 mlxsw_sp_acl_block_destroy(acl_block); 1547 } 1548 return err; 1549 } 1550 1551 static void 1552 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port, 1553 struct tcf_block *block, bool ingress) 1554 { 1555 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1556 struct mlxsw_sp_acl_block *acl_block; 1557 struct tcf_block_cb *block_cb; 1558 int err; 1559 1560 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1561 mlxsw_sp); 1562 if (!block_cb) 1563 return; 1564 1565 if (ingress) 1566 mlxsw_sp_port->ing_acl_block = NULL; 1567 else 1568 mlxsw_sp_port->eg_acl_block = NULL; 1569 1570 acl_block = tcf_block_cb_priv(block_cb); 1571 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block, 1572 mlxsw_sp_port, ingress); 1573 if (!err && !tcf_block_cb_decref(block_cb)) { 1574 __tcf_block_cb_unregister(block_cb); 1575 mlxsw_sp_acl_block_destroy(acl_block); 1576 } 1577 } 1578 1579 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1580 struct tc_block_offload *f) 1581 { 1582 tc_setup_cb_t *cb; 1583 bool ingress; 1584 int err; 1585 1586 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) { 1587 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig; 1588 ingress = true; 1589 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 1590 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg; 1591 ingress = false; 1592 } else { 1593 return -EOPNOTSUPP; 1594 } 1595 1596 switch (f->command) { 1597 case TC_BLOCK_BIND: 1598 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port, 1599 mlxsw_sp_port); 1600 if (err) 1601 return err; 1602 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, 1603 f->block, ingress); 1604 if (err) { 1605 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1606 return err; 1607 } 1608 return 0; 1609 case TC_BLOCK_UNBIND: 1610 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port, 1611 f->block, ingress); 1612 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1613 return 0; 1614 default: 1615 return -EOPNOTSUPP; 1616 } 1617 } 1618 1619 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1620 void *type_data) 1621 { 1622 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1623 1624 switch (type) { 1625 case TC_SETUP_BLOCK: 1626 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1627 case TC_SETUP_QDISC_RED: 1628 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1629 case TC_SETUP_QDISC_PRIO: 1630 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1631 default: 1632 return -EOPNOTSUPP; 1633 } 1634 } 1635 1636 1637 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1638 { 1639 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1640 1641 if (!enable) { 1642 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) || 1643 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) || 1644 !list_empty(&mlxsw_sp_port->mall_tc_list)) { 1645 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1646 return -EINVAL; 1647 } 1648 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block); 1649 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block); 1650 } else { 1651 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block); 1652 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block); 1653 } 1654 return 0; 1655 } 1656 1657 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1658 1659 static int mlxsw_sp_handle_feature(struct net_device *dev, 1660 netdev_features_t wanted_features, 1661 netdev_features_t feature, 1662 mlxsw_sp_feature_handler feature_handler) 1663 { 1664 netdev_features_t changes = wanted_features ^ dev->features; 1665 bool enable = !!(wanted_features & feature); 1666 int err; 1667 1668 if (!(changes & feature)) 1669 return 0; 1670 1671 err = feature_handler(dev, enable); 1672 if (err) { 1673 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1674 enable ? "Enable" : "Disable", &feature, err); 1675 return err; 1676 } 1677 1678 if (enable) 1679 dev->features |= feature; 1680 else 1681 dev->features &= ~feature; 1682 1683 return 0; 1684 } 1685 static int mlxsw_sp_set_features(struct net_device *dev, 1686 netdev_features_t features) 1687 { 1688 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1689 mlxsw_sp_feature_hw_tc); 1690 } 1691 1692 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1693 .ndo_open = mlxsw_sp_port_open, 1694 .ndo_stop = mlxsw_sp_port_stop, 1695 .ndo_start_xmit = mlxsw_sp_port_xmit, 1696 .ndo_setup_tc = mlxsw_sp_setup_tc, 1697 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1698 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1699 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1700 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1701 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1702 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1703 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1704 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1705 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name, 1706 .ndo_set_features = mlxsw_sp_set_features, 1707 }; 1708 1709 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev, 1710 struct ethtool_drvinfo *drvinfo) 1711 { 1712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1714 1715 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver)); 1716 strlcpy(drvinfo->version, mlxsw_sp_driver_version, 1717 sizeof(drvinfo->version)); 1718 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 1719 "%d.%d.%d", 1720 mlxsw_sp->bus_info->fw_rev.major, 1721 mlxsw_sp->bus_info->fw_rev.minor, 1722 mlxsw_sp->bus_info->fw_rev.subminor); 1723 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name, 1724 sizeof(drvinfo->bus_info)); 1725 } 1726 1727 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev, 1728 struct ethtool_pauseparam *pause) 1729 { 1730 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1731 1732 pause->rx_pause = mlxsw_sp_port->link.rx_pause; 1733 pause->tx_pause = mlxsw_sp_port->link.tx_pause; 1734 } 1735 1736 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port, 1737 struct ethtool_pauseparam *pause) 1738 { 1739 char pfcc_pl[MLXSW_REG_PFCC_LEN]; 1740 1741 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port); 1742 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause); 1743 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause); 1744 1745 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc), 1746 pfcc_pl); 1747 } 1748 1749 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev, 1750 struct ethtool_pauseparam *pause) 1751 { 1752 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1753 bool pause_en = pause->tx_pause || pause->rx_pause; 1754 int err; 1755 1756 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) { 1757 netdev_err(dev, "PFC already enabled on port\n"); 1758 return -EINVAL; 1759 } 1760 1761 if (pause->autoneg) { 1762 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n"); 1763 return -EINVAL; 1764 } 1765 1766 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1767 if (err) { 1768 netdev_err(dev, "Failed to configure port's headroom\n"); 1769 return err; 1770 } 1771 1772 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause); 1773 if (err) { 1774 netdev_err(dev, "Failed to set PAUSE parameters\n"); 1775 goto err_port_pause_configure; 1776 } 1777 1778 mlxsw_sp_port->link.rx_pause = pause->rx_pause; 1779 mlxsw_sp_port->link.tx_pause = pause->tx_pause; 1780 1781 return 0; 1782 1783 err_port_pause_configure: 1784 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 1785 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1786 return err; 1787 } 1788 1789 struct mlxsw_sp_port_hw_stats { 1790 char str[ETH_GSTRING_LEN]; 1791 u64 (*getter)(const char *payload); 1792 bool cells_bytes; 1793 }; 1794 1795 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = { 1796 { 1797 .str = "a_frames_transmitted_ok", 1798 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get, 1799 }, 1800 { 1801 .str = "a_frames_received_ok", 1802 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get, 1803 }, 1804 { 1805 .str = "a_frame_check_sequence_errors", 1806 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get, 1807 }, 1808 { 1809 .str = "a_alignment_errors", 1810 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get, 1811 }, 1812 { 1813 .str = "a_octets_transmitted_ok", 1814 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get, 1815 }, 1816 { 1817 .str = "a_octets_received_ok", 1818 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get, 1819 }, 1820 { 1821 .str = "a_multicast_frames_xmitted_ok", 1822 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get, 1823 }, 1824 { 1825 .str = "a_broadcast_frames_xmitted_ok", 1826 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get, 1827 }, 1828 { 1829 .str = "a_multicast_frames_received_ok", 1830 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get, 1831 }, 1832 { 1833 .str = "a_broadcast_frames_received_ok", 1834 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get, 1835 }, 1836 { 1837 .str = "a_in_range_length_errors", 1838 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get, 1839 }, 1840 { 1841 .str = "a_out_of_range_length_field", 1842 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get, 1843 }, 1844 { 1845 .str = "a_frame_too_long_errors", 1846 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get, 1847 }, 1848 { 1849 .str = "a_symbol_error_during_carrier", 1850 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get, 1851 }, 1852 { 1853 .str = "a_mac_control_frames_transmitted", 1854 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get, 1855 }, 1856 { 1857 .str = "a_mac_control_frames_received", 1858 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get, 1859 }, 1860 { 1861 .str = "a_unsupported_opcodes_received", 1862 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get, 1863 }, 1864 { 1865 .str = "a_pause_mac_ctrl_frames_received", 1866 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get, 1867 }, 1868 { 1869 .str = "a_pause_mac_ctrl_frames_xmitted", 1870 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get, 1871 }, 1872 }; 1873 1874 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats) 1875 1876 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = { 1877 { 1878 .str = "rx_octets_prio", 1879 .getter = mlxsw_reg_ppcnt_rx_octets_get, 1880 }, 1881 { 1882 .str = "rx_frames_prio", 1883 .getter = mlxsw_reg_ppcnt_rx_frames_get, 1884 }, 1885 { 1886 .str = "tx_octets_prio", 1887 .getter = mlxsw_reg_ppcnt_tx_octets_get, 1888 }, 1889 { 1890 .str = "tx_frames_prio", 1891 .getter = mlxsw_reg_ppcnt_tx_frames_get, 1892 }, 1893 { 1894 .str = "rx_pause_prio", 1895 .getter = mlxsw_reg_ppcnt_rx_pause_get, 1896 }, 1897 { 1898 .str = "rx_pause_duration_prio", 1899 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get, 1900 }, 1901 { 1902 .str = "tx_pause_prio", 1903 .getter = mlxsw_reg_ppcnt_tx_pause_get, 1904 }, 1905 { 1906 .str = "tx_pause_duration_prio", 1907 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get, 1908 }, 1909 }; 1910 1911 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats) 1912 1913 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = { 1914 { 1915 .str = "tc_transmit_queue_tc", 1916 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get, 1917 .cells_bytes = true, 1918 }, 1919 { 1920 .str = "tc_no_buffer_discard_uc_tc", 1921 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get, 1922 }, 1923 }; 1924 1925 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats) 1926 1927 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \ 1928 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \ 1929 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \ 1930 IEEE_8021QAZ_MAX_TCS) 1931 1932 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio) 1933 { 1934 int i; 1935 1936 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) { 1937 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1938 mlxsw_sp_port_hw_prio_stats[i].str, prio); 1939 *p += ETH_GSTRING_LEN; 1940 } 1941 } 1942 1943 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc) 1944 { 1945 int i; 1946 1947 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) { 1948 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1949 mlxsw_sp_port_hw_tc_stats[i].str, tc); 1950 *p += ETH_GSTRING_LEN; 1951 } 1952 } 1953 1954 static void mlxsw_sp_port_get_strings(struct net_device *dev, 1955 u32 stringset, u8 *data) 1956 { 1957 u8 *p = data; 1958 int i; 1959 1960 switch (stringset) { 1961 case ETH_SS_STATS: 1962 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) { 1963 memcpy(p, mlxsw_sp_port_hw_stats[i].str, 1964 ETH_GSTRING_LEN); 1965 p += ETH_GSTRING_LEN; 1966 } 1967 1968 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 1969 mlxsw_sp_port_get_prio_strings(&p, i); 1970 1971 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 1972 mlxsw_sp_port_get_tc_strings(&p, i); 1973 1974 break; 1975 } 1976 } 1977 1978 static int mlxsw_sp_port_set_phys_id(struct net_device *dev, 1979 enum ethtool_phys_id_state state) 1980 { 1981 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1982 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1983 char mlcr_pl[MLXSW_REG_MLCR_LEN]; 1984 bool active; 1985 1986 switch (state) { 1987 case ETHTOOL_ID_ACTIVE: 1988 active = true; 1989 break; 1990 case ETHTOOL_ID_INACTIVE: 1991 active = false; 1992 break; 1993 default: 1994 return -EOPNOTSUPP; 1995 } 1996 1997 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active); 1998 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl); 1999 } 2000 2001 static int 2002 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats, 2003 int *p_len, enum mlxsw_reg_ppcnt_grp grp) 2004 { 2005 switch (grp) { 2006 case MLXSW_REG_PPCNT_IEEE_8023_CNT: 2007 *p_hw_stats = mlxsw_sp_port_hw_stats; 2008 *p_len = MLXSW_SP_PORT_HW_STATS_LEN; 2009 break; 2010 case MLXSW_REG_PPCNT_PRIO_CNT: 2011 *p_hw_stats = mlxsw_sp_port_hw_prio_stats; 2012 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2013 break; 2014 case MLXSW_REG_PPCNT_TC_CNT: 2015 *p_hw_stats = mlxsw_sp_port_hw_tc_stats; 2016 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN; 2017 break; 2018 default: 2019 WARN_ON(1); 2020 return -EOPNOTSUPP; 2021 } 2022 return 0; 2023 } 2024 2025 static void __mlxsw_sp_port_get_stats(struct net_device *dev, 2026 enum mlxsw_reg_ppcnt_grp grp, int prio, 2027 u64 *data, int data_index) 2028 { 2029 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2030 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2031 struct mlxsw_sp_port_hw_stats *hw_stats; 2032 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 2033 int i, len; 2034 int err; 2035 2036 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp); 2037 if (err) 2038 return; 2039 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl); 2040 for (i = 0; i < len; i++) { 2041 data[data_index + i] = hw_stats[i].getter(ppcnt_pl); 2042 if (!hw_stats[i].cells_bytes) 2043 continue; 2044 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp, 2045 data[data_index + i]); 2046 } 2047 } 2048 2049 static void mlxsw_sp_port_get_stats(struct net_device *dev, 2050 struct ethtool_stats *stats, u64 *data) 2051 { 2052 int i, data_index = 0; 2053 2054 /* IEEE 802.3 Counters */ 2055 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0, 2056 data, data_index); 2057 data_index = MLXSW_SP_PORT_HW_STATS_LEN; 2058 2059 /* Per-Priority Counters */ 2060 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2061 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i, 2062 data, data_index); 2063 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2064 } 2065 2066 /* Per-TC Counters */ 2067 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2068 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i, 2069 data, data_index); 2070 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN; 2071 } 2072 } 2073 2074 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset) 2075 { 2076 switch (sset) { 2077 case ETH_SS_STATS: 2078 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN; 2079 default: 2080 return -EOPNOTSUPP; 2081 } 2082 } 2083 2084 struct mlxsw_sp_port_link_mode { 2085 enum ethtool_link_mode_bit_indices mask_ethtool; 2086 u32 mask; 2087 u32 speed; 2088 }; 2089 2090 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = { 2091 { 2092 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, 2093 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2094 .speed = SPEED_100, 2095 }, 2096 { 2097 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | 2098 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX, 2099 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2100 .speed = SPEED_1000, 2101 }, 2102 { 2103 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, 2104 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2105 .speed = SPEED_10000, 2106 }, 2107 { 2108 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | 2109 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4, 2110 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2111 .speed = SPEED_10000, 2112 }, 2113 { 2114 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2115 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2116 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2117 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR, 2118 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2119 .speed = SPEED_10000, 2120 }, 2121 { 2122 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, 2123 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 2124 .speed = SPEED_20000, 2125 }, 2126 { 2127 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, 2128 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2129 .speed = SPEED_40000, 2130 }, 2131 { 2132 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, 2133 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2134 .speed = SPEED_40000, 2135 }, 2136 { 2137 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, 2138 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2139 .speed = SPEED_40000, 2140 }, 2141 { 2142 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, 2143 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2144 .speed = SPEED_40000, 2145 }, 2146 { 2147 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, 2148 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2149 .speed = SPEED_25000, 2150 }, 2151 { 2152 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, 2153 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2154 .speed = SPEED_25000, 2155 }, 2156 { 2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2158 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2159 .speed = SPEED_25000, 2160 }, 2161 { 2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2163 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2164 .speed = SPEED_25000, 2165 }, 2166 { 2167 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, 2168 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2169 .speed = SPEED_50000, 2170 }, 2171 { 2172 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, 2173 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2174 .speed = SPEED_50000, 2175 }, 2176 { 2177 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, 2178 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2179 .speed = SPEED_50000, 2180 }, 2181 { 2182 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2183 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, 2184 .speed = SPEED_56000, 2185 }, 2186 { 2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2188 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, 2189 .speed = SPEED_56000, 2190 }, 2191 { 2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2193 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, 2194 .speed = SPEED_56000, 2195 }, 2196 { 2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2198 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, 2199 .speed = SPEED_56000, 2200 }, 2201 { 2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, 2203 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2204 .speed = SPEED_100000, 2205 }, 2206 { 2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, 2208 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2209 .speed = SPEED_100000, 2210 }, 2211 { 2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, 2213 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2214 .speed = SPEED_100000, 2215 }, 2216 { 2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, 2218 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2219 .speed = SPEED_100000, 2220 }, 2221 }; 2222 2223 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode) 2224 2225 static void 2226 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto, 2227 struct ethtool_link_ksettings *cmd) 2228 { 2229 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2230 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2231 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2232 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2233 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2234 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2235 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2236 2237 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2238 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2239 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2240 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | 2241 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX)) 2242 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2243 } 2244 2245 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode) 2246 { 2247 int i; 2248 2249 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2250 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) 2251 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2252 mode); 2253 } 2254 } 2255 2256 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto, 2257 struct ethtool_link_ksettings *cmd) 2258 { 2259 u32 speed = SPEED_UNKNOWN; 2260 u8 duplex = DUPLEX_UNKNOWN; 2261 int i; 2262 2263 if (!carrier_ok) 2264 goto out; 2265 2266 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2267 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) { 2268 speed = mlxsw_sp_port_link_mode[i].speed; 2269 duplex = DUPLEX_FULL; 2270 break; 2271 } 2272 } 2273 out: 2274 cmd->base.speed = speed; 2275 cmd->base.duplex = duplex; 2276 } 2277 2278 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto) 2279 { 2280 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2281 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2282 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2283 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2284 return PORT_FIBRE; 2285 2286 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2287 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2288 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4)) 2289 return PORT_DA; 2290 2291 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2292 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2293 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2294 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4)) 2295 return PORT_NONE; 2296 2297 return PORT_OTHER; 2298 } 2299 2300 static u32 2301 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd) 2302 { 2303 u32 ptys_proto = 0; 2304 int i; 2305 2306 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2307 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2308 cmd->link_modes.advertising)) 2309 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2310 } 2311 return ptys_proto; 2312 } 2313 2314 static u32 mlxsw_sp_to_ptys_speed(u32 speed) 2315 { 2316 u32 ptys_proto = 0; 2317 int i; 2318 2319 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2320 if (speed == mlxsw_sp_port_link_mode[i].speed) 2321 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2322 } 2323 return ptys_proto; 2324 } 2325 2326 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed) 2327 { 2328 u32 ptys_proto = 0; 2329 int i; 2330 2331 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2332 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed) 2333 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2334 } 2335 return ptys_proto; 2336 } 2337 2338 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap, 2339 struct ethtool_link_ksettings *cmd) 2340 { 2341 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause); 2342 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 2343 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 2344 2345 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd); 2346 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported); 2347 } 2348 2349 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg, 2350 struct ethtool_link_ksettings *cmd) 2351 { 2352 if (!autoneg) 2353 return; 2354 2355 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 2356 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising); 2357 } 2358 2359 static void 2360 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status, 2361 struct ethtool_link_ksettings *cmd) 2362 { 2363 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp) 2364 return; 2365 2366 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg); 2367 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising); 2368 } 2369 2370 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev, 2371 struct ethtool_link_ksettings *cmd) 2372 { 2373 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp; 2374 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2375 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2376 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2377 u8 autoneg_status; 2378 bool autoneg; 2379 int err; 2380 2381 autoneg = mlxsw_sp_port->link.autoneg; 2382 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2383 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2384 if (err) 2385 return err; 2386 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, 2387 ð_proto_oper); 2388 2389 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd); 2390 2391 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd); 2392 2393 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl); 2394 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl); 2395 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd); 2396 2397 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 2398 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper); 2399 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper, 2400 cmd); 2401 2402 return 0; 2403 } 2404 2405 static int 2406 mlxsw_sp_port_set_link_ksettings(struct net_device *dev, 2407 const struct ethtool_link_ksettings *cmd) 2408 { 2409 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2410 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2411 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2412 u32 eth_proto_cap, eth_proto_new; 2413 bool autoneg; 2414 int err; 2415 2416 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2417 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2418 if (err) 2419 return err; 2420 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); 2421 2422 autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 2423 eth_proto_new = autoneg ? 2424 mlxsw_sp_to_ptys_advert_link(cmd) : 2425 mlxsw_sp_to_ptys_speed(cmd->base.speed); 2426 2427 eth_proto_new = eth_proto_new & eth_proto_cap; 2428 if (!eth_proto_new) { 2429 netdev_err(dev, "No supported speed requested\n"); 2430 return -EINVAL; 2431 } 2432 2433 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2434 eth_proto_new, autoneg); 2435 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2436 if (err) 2437 return err; 2438 2439 if (!netif_running(dev)) 2440 return 0; 2441 2442 mlxsw_sp_port->link.autoneg = autoneg; 2443 2444 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2445 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 2446 2447 return 0; 2448 } 2449 2450 static int mlxsw_sp_flash_device(struct net_device *dev, 2451 struct ethtool_flash *flash) 2452 { 2453 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2455 const struct firmware *firmware; 2456 int err; 2457 2458 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2459 return -EOPNOTSUPP; 2460 2461 dev_hold(dev); 2462 rtnl_unlock(); 2463 2464 err = request_firmware_direct(&firmware, flash->data, &dev->dev); 2465 if (err) 2466 goto out; 2467 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 2468 release_firmware(firmware); 2469 out: 2470 rtnl_lock(); 2471 dev_put(dev); 2472 return err; 2473 } 2474 2475 #define MLXSW_SP_I2C_ADDR_LOW 0x50 2476 #define MLXSW_SP_I2C_ADDR_HIGH 0x51 2477 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256 2478 2479 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port, 2480 u16 offset, u16 size, void *data, 2481 unsigned int *p_read_size) 2482 { 2483 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2484 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE]; 2485 char mcia_pl[MLXSW_REG_MCIA_LEN]; 2486 u16 i2c_addr; 2487 int status; 2488 int err; 2489 2490 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 2491 2492 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH && 2493 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH) 2494 /* Cross pages read, read until offset 256 in low page */ 2495 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset; 2496 2497 i2c_addr = MLXSW_SP_I2C_ADDR_LOW; 2498 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) { 2499 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH; 2500 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH; 2501 } 2502 2503 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module, 2504 0, 0, offset, size, i2c_addr); 2505 2506 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl); 2507 if (err) 2508 return err; 2509 2510 status = mlxsw_reg_mcia_status_get(mcia_pl); 2511 if (status) 2512 return -EIO; 2513 2514 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp); 2515 memcpy(data, eeprom_tmp, size); 2516 *p_read_size = size; 2517 2518 return 0; 2519 } 2520 2521 enum mlxsw_sp_eeprom_module_info_rev_id { 2522 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 2523 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 2524 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 2525 }; 2526 2527 enum mlxsw_sp_eeprom_module_info_id { 2528 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03, 2529 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 2530 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 2531 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 2532 }; 2533 2534 enum mlxsw_sp_eeprom_module_info { 2535 MLXSW_SP_EEPROM_MODULE_INFO_ID, 2536 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID, 2537 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2538 }; 2539 2540 static int mlxsw_sp_get_module_info(struct net_device *netdev, 2541 struct ethtool_modinfo *modinfo) 2542 { 2543 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2544 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE]; 2545 u8 module_rev_id, module_id; 2546 unsigned int read_size; 2547 int err; 2548 2549 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0, 2550 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2551 module_info, &read_size); 2552 if (err) 2553 return err; 2554 2555 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE) 2556 return -EIO; 2557 2558 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID]; 2559 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID]; 2560 2561 switch (module_id) { 2562 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP: 2563 modinfo->type = ETH_MODULE_SFF_8436; 2564 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2565 break; 2566 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS: 2567 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28: 2568 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 || 2569 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) { 2570 modinfo->type = ETH_MODULE_SFF_8636; 2571 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2572 } else { 2573 modinfo->type = ETH_MODULE_SFF_8436; 2574 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2575 } 2576 break; 2577 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP: 2578 modinfo->type = ETH_MODULE_SFF_8472; 2579 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2580 break; 2581 default: 2582 return -EINVAL; 2583 } 2584 2585 return 0; 2586 } 2587 2588 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev, 2589 struct ethtool_eeprom *ee, 2590 u8 *data) 2591 { 2592 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2593 int offset = ee->offset; 2594 unsigned int read_size; 2595 int i = 0; 2596 int err; 2597 2598 if (!ee->len) 2599 return -EINVAL; 2600 2601 memset(data, 0, ee->len); 2602 2603 while (i < ee->len) { 2604 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset, 2605 ee->len - i, data + i, 2606 &read_size); 2607 if (err) { 2608 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n"); 2609 return err; 2610 } 2611 2612 i += read_size; 2613 offset += read_size; 2614 } 2615 2616 return 0; 2617 } 2618 2619 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { 2620 .get_drvinfo = mlxsw_sp_port_get_drvinfo, 2621 .get_link = ethtool_op_get_link, 2622 .get_pauseparam = mlxsw_sp_port_get_pauseparam, 2623 .set_pauseparam = mlxsw_sp_port_set_pauseparam, 2624 .get_strings = mlxsw_sp_port_get_strings, 2625 .set_phys_id = mlxsw_sp_port_set_phys_id, 2626 .get_ethtool_stats = mlxsw_sp_port_get_stats, 2627 .get_sset_count = mlxsw_sp_port_get_sset_count, 2628 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings, 2629 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings, 2630 .flash_device = mlxsw_sp_flash_device, 2631 .get_module_info = mlxsw_sp_get_module_info, 2632 .get_module_eeprom = mlxsw_sp_get_module_eeprom, 2633 }; 2634 2635 static int 2636 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width) 2637 { 2638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2639 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width; 2640 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2641 u32 eth_proto_admin; 2642 2643 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed); 2644 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2645 eth_proto_admin, mlxsw_sp_port->link.autoneg); 2646 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2647 } 2648 2649 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 2650 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 2651 bool dwrr, u8 dwrr_weight) 2652 { 2653 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2654 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2655 2656 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2657 next_index); 2658 mlxsw_reg_qeec_de_set(qeec_pl, true); 2659 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 2660 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 2661 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2662 } 2663 2664 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 2665 enum mlxsw_reg_qeec_hr hr, u8 index, 2666 u8 next_index, u32 maxrate) 2667 { 2668 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2669 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2670 2671 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2672 next_index); 2673 mlxsw_reg_qeec_mase_set(qeec_pl, true); 2674 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 2675 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2676 } 2677 2678 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 2679 u8 switch_prio, u8 tclass) 2680 { 2681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2682 char qtct_pl[MLXSW_REG_QTCT_LEN]; 2683 2684 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 2685 tclass); 2686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 2687 } 2688 2689 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 2690 { 2691 int err, i; 2692 2693 /* Setup the elements hierarcy, so that each TC is linked to 2694 * one subgroup, which are all member in the same group. 2695 */ 2696 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2697 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false, 2698 0); 2699 if (err) 2700 return err; 2701 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2702 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2703 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i, 2704 0, false, 0); 2705 if (err) 2706 return err; 2707 } 2708 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2709 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2710 MLXSW_REG_QEEC_HIERARCY_TC, i, i, 2711 false, 0); 2712 if (err) 2713 return err; 2714 } 2715 2716 /* Make sure the max shaper is disabled in all hierarcies that 2717 * support it. 2718 */ 2719 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2720 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0, 2721 MLXSW_REG_QEEC_MAS_DIS); 2722 if (err) 2723 return err; 2724 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2725 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2726 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2727 i, 0, 2728 MLXSW_REG_QEEC_MAS_DIS); 2729 if (err) 2730 return err; 2731 } 2732 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2733 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2734 MLXSW_REG_QEEC_HIERARCY_TC, 2735 i, i, 2736 MLXSW_REG_QEEC_MAS_DIS); 2737 if (err) 2738 return err; 2739 } 2740 2741 /* Map all priorities to traffic class 0. */ 2742 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2743 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 2744 if (err) 2745 return err; 2746 } 2747 2748 return 0; 2749 } 2750 2751 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 2752 bool split, u8 module, u8 width, u8 lane) 2753 { 2754 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 2755 struct mlxsw_sp_port *mlxsw_sp_port; 2756 struct net_device *dev; 2757 int err; 2758 2759 err = mlxsw_core_port_init(mlxsw_sp->core, local_port); 2760 if (err) { 2761 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 2762 local_port); 2763 return err; 2764 } 2765 2766 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 2767 if (!dev) { 2768 err = -ENOMEM; 2769 goto err_alloc_etherdev; 2770 } 2771 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 2772 mlxsw_sp_port = netdev_priv(dev); 2773 mlxsw_sp_port->dev = dev; 2774 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 2775 mlxsw_sp_port->local_port = local_port; 2776 mlxsw_sp_port->pvid = 1; 2777 mlxsw_sp_port->split = split; 2778 mlxsw_sp_port->mapping.module = module; 2779 mlxsw_sp_port->mapping.width = width; 2780 mlxsw_sp_port->mapping.lane = lane; 2781 mlxsw_sp_port->link.autoneg = 1; 2782 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 2783 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list); 2784 2785 mlxsw_sp_port->pcpu_stats = 2786 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 2787 if (!mlxsw_sp_port->pcpu_stats) { 2788 err = -ENOMEM; 2789 goto err_alloc_stats; 2790 } 2791 2792 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample), 2793 GFP_KERNEL); 2794 if (!mlxsw_sp_port->sample) { 2795 err = -ENOMEM; 2796 goto err_alloc_sample; 2797 } 2798 2799 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 2800 &update_stats_cache); 2801 2802 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 2803 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 2804 2805 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); 2806 if (err) { 2807 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 2808 mlxsw_sp_port->local_port); 2809 goto err_port_module_map; 2810 } 2811 2812 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0); 2813 if (err) { 2814 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 2815 mlxsw_sp_port->local_port); 2816 goto err_port_swid_set; 2817 } 2818 2819 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 2820 if (err) { 2821 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 2822 mlxsw_sp_port->local_port); 2823 goto err_dev_addr_init; 2824 } 2825 2826 netif_carrier_off(dev); 2827 2828 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 2829 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2830 dev->hw_features |= NETIF_F_HW_TC; 2831 2832 dev->min_mtu = 0; 2833 dev->max_mtu = ETH_MAX_MTU; 2834 2835 /* Each packet needs to have a Tx header (metadata) on top all other 2836 * headers. 2837 */ 2838 dev->needed_headroom = MLXSW_TXHDR_LEN; 2839 2840 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 2841 if (err) { 2842 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 2843 mlxsw_sp_port->local_port); 2844 goto err_port_system_port_mapping_set; 2845 } 2846 2847 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width); 2848 if (err) { 2849 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 2850 mlxsw_sp_port->local_port); 2851 goto err_port_speed_by_width_set; 2852 } 2853 2854 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 2855 if (err) { 2856 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 2857 mlxsw_sp_port->local_port); 2858 goto err_port_mtu_set; 2859 } 2860 2861 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2862 if (err) 2863 goto err_port_admin_status_set; 2864 2865 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 2866 if (err) { 2867 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 2868 mlxsw_sp_port->local_port); 2869 goto err_port_buffers_init; 2870 } 2871 2872 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 2873 if (err) { 2874 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 2875 mlxsw_sp_port->local_port); 2876 goto err_port_ets_init; 2877 } 2878 2879 /* ETS and buffers must be initialized before DCB. */ 2880 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 2881 if (err) { 2882 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 2883 mlxsw_sp_port->local_port); 2884 goto err_port_dcb_init; 2885 } 2886 2887 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 2888 if (err) { 2889 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 2890 mlxsw_sp_port->local_port); 2891 goto err_port_fids_init; 2892 } 2893 2894 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 2895 if (err) { 2896 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 2897 mlxsw_sp_port->local_port); 2898 goto err_port_qdiscs_init; 2899 } 2900 2901 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 2902 if (IS_ERR(mlxsw_sp_port_vlan)) { 2903 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 2904 mlxsw_sp_port->local_port); 2905 err = PTR_ERR(mlxsw_sp_port_vlan); 2906 goto err_port_vlan_get; 2907 } 2908 2909 mlxsw_sp_port_switchdev_init(mlxsw_sp_port); 2910 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 2911 err = register_netdev(dev); 2912 if (err) { 2913 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 2914 mlxsw_sp_port->local_port); 2915 goto err_register_netdev; 2916 } 2917 2918 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 2919 mlxsw_sp_port, dev, module + 1, 2920 mlxsw_sp_port->split, lane / width); 2921 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 2922 return 0; 2923 2924 err_register_netdev: 2925 mlxsw_sp->ports[local_port] = NULL; 2926 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 2927 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 2928 err_port_vlan_get: 2929 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 2930 err_port_qdiscs_init: 2931 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 2932 err_port_fids_init: 2933 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 2934 err_port_dcb_init: 2935 err_port_ets_init: 2936 err_port_buffers_init: 2937 err_port_admin_status_set: 2938 err_port_mtu_set: 2939 err_port_speed_by_width_set: 2940 err_port_system_port_mapping_set: 2941 err_dev_addr_init: 2942 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 2943 err_port_swid_set: 2944 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 2945 err_port_module_map: 2946 kfree(mlxsw_sp_port->sample); 2947 err_alloc_sample: 2948 free_percpu(mlxsw_sp_port->pcpu_stats); 2949 err_alloc_stats: 2950 free_netdev(dev); 2951 err_alloc_etherdev: 2952 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 2953 return err; 2954 } 2955 2956 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 2957 { 2958 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2959 2960 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 2961 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 2962 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 2963 mlxsw_sp->ports[local_port] = NULL; 2964 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 2965 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 2966 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 2967 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 2968 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 2969 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 2970 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 2971 kfree(mlxsw_sp_port->sample); 2972 free_percpu(mlxsw_sp_port->pcpu_stats); 2973 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 2974 free_netdev(mlxsw_sp_port->dev); 2975 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 2976 } 2977 2978 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 2979 { 2980 return mlxsw_sp->ports[local_port] != NULL; 2981 } 2982 2983 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 2984 { 2985 int i; 2986 2987 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 2988 if (mlxsw_sp_port_created(mlxsw_sp, i)) 2989 mlxsw_sp_port_remove(mlxsw_sp, i); 2990 kfree(mlxsw_sp->port_to_module); 2991 kfree(mlxsw_sp->ports); 2992 } 2993 2994 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 2995 { 2996 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2997 u8 module, width, lane; 2998 size_t alloc_size; 2999 int i; 3000 int err; 3001 3002 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 3003 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 3004 if (!mlxsw_sp->ports) 3005 return -ENOMEM; 3006 3007 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int), 3008 GFP_KERNEL); 3009 if (!mlxsw_sp->port_to_module) { 3010 err = -ENOMEM; 3011 goto err_port_to_module_alloc; 3012 } 3013 3014 for (i = 1; i < max_ports; i++) { 3015 /* Mark as invalid */ 3016 mlxsw_sp->port_to_module[i] = -1; 3017 3018 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module, 3019 &width, &lane); 3020 if (err) 3021 goto err_port_module_info_get; 3022 if (!width) 3023 continue; 3024 mlxsw_sp->port_to_module[i] = module; 3025 err = mlxsw_sp_port_create(mlxsw_sp, i, false, 3026 module, width, lane); 3027 if (err) 3028 goto err_port_create; 3029 } 3030 return 0; 3031 3032 err_port_create: 3033 err_port_module_info_get: 3034 for (i--; i >= 1; i--) 3035 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3036 mlxsw_sp_port_remove(mlxsw_sp, i); 3037 kfree(mlxsw_sp->port_to_module); 3038 err_port_to_module_alloc: 3039 kfree(mlxsw_sp->ports); 3040 return err; 3041 } 3042 3043 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port) 3044 { 3045 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX; 3046 3047 return local_port - offset; 3048 } 3049 3050 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port, 3051 u8 module, unsigned int count) 3052 { 3053 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count; 3054 int err, i; 3055 3056 for (i = 0; i < count; i++) { 3057 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true, 3058 module, width, i * width); 3059 if (err) 3060 goto err_port_create; 3061 } 3062 3063 return 0; 3064 3065 err_port_create: 3066 for (i--; i >= 0; i--) 3067 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3068 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3069 return err; 3070 } 3071 3072 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 3073 u8 base_port, unsigned int count) 3074 { 3075 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH; 3076 int i; 3077 3078 /* Split by four means we need to re-create two ports, otherwise 3079 * only one. 3080 */ 3081 count = count / 2; 3082 3083 for (i = 0; i < count; i++) { 3084 local_port = base_port + i * 2; 3085 if (mlxsw_sp->port_to_module[local_port] < 0) 3086 continue; 3087 module = mlxsw_sp->port_to_module[local_port]; 3088 3089 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module, 3090 width, 0); 3091 } 3092 } 3093 3094 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 3095 unsigned int count, 3096 struct netlink_ext_ack *extack) 3097 { 3098 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3099 struct mlxsw_sp_port *mlxsw_sp_port; 3100 u8 module, cur_width, base_port; 3101 int i; 3102 int err; 3103 3104 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3105 if (!mlxsw_sp_port) { 3106 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3107 local_port); 3108 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3109 return -EINVAL; 3110 } 3111 3112 module = mlxsw_sp_port->mapping.module; 3113 cur_width = mlxsw_sp_port->mapping.width; 3114 3115 if (count != 2 && count != 4) { 3116 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n"); 3117 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports"); 3118 return -EINVAL; 3119 } 3120 3121 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) { 3122 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n"); 3123 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further"); 3124 return -EINVAL; 3125 } 3126 3127 /* Make sure we have enough slave (even) ports for the split. */ 3128 if (count == 2) { 3129 base_port = local_port; 3130 if (mlxsw_sp->ports[base_port + 1]) { 3131 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3132 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3133 return -EINVAL; 3134 } 3135 } else { 3136 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3137 if (mlxsw_sp->ports[base_port + 1] || 3138 mlxsw_sp->ports[base_port + 3]) { 3139 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3140 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3141 return -EINVAL; 3142 } 3143 } 3144 3145 for (i = 0; i < count; i++) 3146 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3147 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3148 3149 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count); 3150 if (err) { 3151 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 3152 goto err_port_split_create; 3153 } 3154 3155 return 0; 3156 3157 err_port_split_create: 3158 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3159 return err; 3160 } 3161 3162 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port, 3163 struct netlink_ext_ack *extack) 3164 { 3165 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3166 struct mlxsw_sp_port *mlxsw_sp_port; 3167 u8 cur_width, base_port; 3168 unsigned int count; 3169 int i; 3170 3171 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3172 if (!mlxsw_sp_port) { 3173 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3174 local_port); 3175 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3176 return -EINVAL; 3177 } 3178 3179 if (!mlxsw_sp_port->split) { 3180 netdev_err(mlxsw_sp_port->dev, "Port was not split\n"); 3181 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 3182 return -EINVAL; 3183 } 3184 3185 cur_width = mlxsw_sp_port->mapping.width; 3186 count = cur_width == 1 ? 4 : 2; 3187 3188 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3189 3190 /* Determine which ports to remove. */ 3191 if (count == 2 && local_port >= base_port + 2) 3192 base_port = base_port + 2; 3193 3194 for (i = 0; i < count; i++) 3195 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3196 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3197 3198 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3199 3200 return 0; 3201 } 3202 3203 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 3204 char *pude_pl, void *priv) 3205 { 3206 struct mlxsw_sp *mlxsw_sp = priv; 3207 struct mlxsw_sp_port *mlxsw_sp_port; 3208 enum mlxsw_reg_pude_oper_status status; 3209 u8 local_port; 3210 3211 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 3212 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3213 if (!mlxsw_sp_port) 3214 return; 3215 3216 status = mlxsw_reg_pude_oper_status_get(pude_pl); 3217 if (status == MLXSW_PORT_OPER_STATUS_UP) { 3218 netdev_info(mlxsw_sp_port->dev, "link up\n"); 3219 netif_carrier_on(mlxsw_sp_port->dev); 3220 } else { 3221 netdev_info(mlxsw_sp_port->dev, "link down\n"); 3222 netif_carrier_off(mlxsw_sp_port->dev); 3223 } 3224 } 3225 3226 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 3227 u8 local_port, void *priv) 3228 { 3229 struct mlxsw_sp *mlxsw_sp = priv; 3230 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3231 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 3232 3233 if (unlikely(!mlxsw_sp_port)) { 3234 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 3235 local_port); 3236 return; 3237 } 3238 3239 skb->dev = mlxsw_sp_port->dev; 3240 3241 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 3242 u64_stats_update_begin(&pcpu_stats->syncp); 3243 pcpu_stats->rx_packets++; 3244 pcpu_stats->rx_bytes += skb->len; 3245 u64_stats_update_end(&pcpu_stats->syncp); 3246 3247 skb->protocol = eth_type_trans(skb, skb->dev); 3248 netif_receive_skb(skb); 3249 } 3250 3251 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 3252 void *priv) 3253 { 3254 skb->offload_fwd_mark = 1; 3255 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3256 } 3257 3258 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb, 3259 u8 local_port, void *priv) 3260 { 3261 skb->offload_mr_fwd_mark = 1; 3262 skb->offload_fwd_mark = 1; 3263 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3264 } 3265 3266 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port, 3267 void *priv) 3268 { 3269 struct mlxsw_sp *mlxsw_sp = priv; 3270 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3271 struct psample_group *psample_group; 3272 u32 size; 3273 3274 if (unlikely(!mlxsw_sp_port)) { 3275 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n", 3276 local_port); 3277 goto out; 3278 } 3279 if (unlikely(!mlxsw_sp_port->sample)) { 3280 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n", 3281 local_port); 3282 goto out; 3283 } 3284 3285 size = mlxsw_sp_port->sample->truncate ? 3286 mlxsw_sp_port->sample->trunc_size : skb->len; 3287 3288 rcu_read_lock(); 3289 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group); 3290 if (!psample_group) 3291 goto out_unlock; 3292 psample_sample_packet(psample_group, skb, size, 3293 mlxsw_sp_port->dev->ifindex, 0, 3294 mlxsw_sp_port->sample->rate); 3295 out_unlock: 3296 rcu_read_unlock(); 3297 out: 3298 consume_skb(skb); 3299 } 3300 3301 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3302 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 3303 _is_ctrl, SP_##_trap_group, DISCARD) 3304 3305 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3306 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 3307 _is_ctrl, SP_##_trap_group, DISCARD) 3308 3309 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3310 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \ 3311 _is_ctrl, SP_##_trap_group, DISCARD) 3312 3313 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 3314 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 3315 3316 static const struct mlxsw_listener mlxsw_sp_listener[] = { 3317 /* Events */ 3318 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 3319 /* L2 traps */ 3320 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true), 3321 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true), 3322 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true), 3323 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false), 3324 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false), 3325 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false), 3326 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false), 3327 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false), 3328 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false), 3329 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false), 3330 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false), 3331 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false), 3332 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD, 3333 false), 3334 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3335 false), 3336 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD, 3337 false), 3338 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3339 false), 3340 /* L3 traps */ 3341 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3342 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3343 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3344 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false), 3345 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 3346 false), 3347 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false), 3348 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 3349 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false), 3350 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP, 3351 false), 3352 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false), 3353 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false), 3354 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false), 3355 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false), 3356 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false), 3357 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false), 3358 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3359 false), 3360 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3361 false), 3362 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3363 false), 3364 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3365 false), 3366 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false), 3367 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 3368 false), 3369 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false), 3370 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false), 3371 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false), 3372 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false), 3373 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3374 /* PKT Sample trap */ 3375 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU, 3376 false, SP_IP2ME, DISCARD), 3377 /* ACL trap */ 3378 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false), 3379 /* Multicast Router Traps */ 3380 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false), 3381 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false), 3382 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false), 3383 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 3384 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 3385 }; 3386 3387 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 3388 { 3389 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 3390 enum mlxsw_reg_qpcr_ir_units ir_units; 3391 int max_cpu_policers; 3392 bool is_bytes; 3393 u8 burst_size; 3394 u32 rate; 3395 int i, err; 3396 3397 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 3398 return -EIO; 3399 3400 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3401 3402 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 3403 for (i = 0; i < max_cpu_policers; i++) { 3404 is_bytes = false; 3405 switch (i) { 3406 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3407 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3408 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3412 rate = 128; 3413 burst_size = 7; 3414 break; 3415 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3417 rate = 16 * 1024; 3418 burst_size = 10; 3419 break; 3420 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3421 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3422 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3423 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3427 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3428 rate = 1024; 3429 burst_size = 7; 3430 break; 3431 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3432 is_bytes = true; 3433 rate = 4 * 1024; 3434 burst_size = 4; 3435 break; 3436 default: 3437 continue; 3438 } 3439 3440 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 3441 burst_size); 3442 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 3443 if (err) 3444 return err; 3445 } 3446 3447 return 0; 3448 } 3449 3450 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 3451 { 3452 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3453 enum mlxsw_reg_htgt_trap_group i; 3454 int max_cpu_policers; 3455 int max_trap_groups; 3456 u8 priority, tc; 3457 u16 policer_id; 3458 int err; 3459 3460 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 3461 return -EIO; 3462 3463 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 3464 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3465 3466 for (i = 0; i < max_trap_groups; i++) { 3467 policer_id = i; 3468 switch (i) { 3469 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3470 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3471 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3472 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3474 priority = 5; 3475 tc = 5; 3476 break; 3477 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3478 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3479 priority = 4; 3480 tc = 4; 3481 break; 3482 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3483 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3484 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3485 priority = 3; 3486 tc = 3; 3487 break; 3488 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3489 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3491 priority = 2; 3492 tc = 2; 3493 break; 3494 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3495 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3497 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3498 priority = 1; 3499 tc = 1; 3500 break; 3501 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 3502 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 3503 tc = MLXSW_REG_HTGT_DEFAULT_TC; 3504 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 3505 break; 3506 default: 3507 continue; 3508 } 3509 3510 if (max_cpu_policers <= policer_id && 3511 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 3512 return -EIO; 3513 3514 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 3515 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3516 if (err) 3517 return err; 3518 } 3519 3520 return 0; 3521 } 3522 3523 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 3524 { 3525 int i; 3526 int err; 3527 3528 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 3529 if (err) 3530 return err; 3531 3532 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 3533 if (err) 3534 return err; 3535 3536 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3537 err = mlxsw_core_trap_register(mlxsw_sp->core, 3538 &mlxsw_sp_listener[i], 3539 mlxsw_sp); 3540 if (err) 3541 goto err_listener_register; 3542 3543 } 3544 return 0; 3545 3546 err_listener_register: 3547 for (i--; i >= 0; i--) { 3548 mlxsw_core_trap_unregister(mlxsw_sp->core, 3549 &mlxsw_sp_listener[i], 3550 mlxsw_sp); 3551 } 3552 return err; 3553 } 3554 3555 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 3556 { 3557 int i; 3558 3559 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3560 mlxsw_core_trap_unregister(mlxsw_sp->core, 3561 &mlxsw_sp_listener[i], 3562 mlxsw_sp); 3563 } 3564 } 3565 3566 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 3567 { 3568 char slcr_pl[MLXSW_REG_SLCR_LEN]; 3569 int err; 3570 3571 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 3572 MLXSW_REG_SLCR_LAG_HASH_DMAC | 3573 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 3574 MLXSW_REG_SLCR_LAG_HASH_VLANID | 3575 MLXSW_REG_SLCR_LAG_HASH_SIP | 3576 MLXSW_REG_SLCR_LAG_HASH_DIP | 3577 MLXSW_REG_SLCR_LAG_HASH_SPORT | 3578 MLXSW_REG_SLCR_LAG_HASH_DPORT | 3579 MLXSW_REG_SLCR_LAG_HASH_IPPROTO); 3580 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 3581 if (err) 3582 return err; 3583 3584 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 3585 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 3586 return -EIO; 3587 3588 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 3589 sizeof(struct mlxsw_sp_upper), 3590 GFP_KERNEL); 3591 if (!mlxsw_sp->lags) 3592 return -ENOMEM; 3593 3594 return 0; 3595 } 3596 3597 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 3598 { 3599 kfree(mlxsw_sp->lags); 3600 } 3601 3602 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 3603 { 3604 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3605 3606 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3607 MLXSW_REG_HTGT_INVALID_POLICER, 3608 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 3609 MLXSW_REG_HTGT_DEFAULT_TC); 3610 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3611 } 3612 3613 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 3614 unsigned long event, void *ptr); 3615 3616 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 3617 const struct mlxsw_bus_info *mlxsw_bus_info) 3618 { 3619 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3620 int err; 3621 3622 mlxsw_sp->core = mlxsw_core; 3623 mlxsw_sp->bus_info = mlxsw_bus_info; 3624 3625 err = mlxsw_sp_fw_rev_validate(mlxsw_sp); 3626 if (err) { 3627 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n"); 3628 return err; 3629 } 3630 3631 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3632 if (err) { 3633 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3634 return err; 3635 } 3636 3637 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3638 if (err) { 3639 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3640 return err; 3641 } 3642 3643 err = mlxsw_sp_fids_init(mlxsw_sp); 3644 if (err) { 3645 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3646 goto err_fids_init; 3647 } 3648 3649 err = mlxsw_sp_traps_init(mlxsw_sp); 3650 if (err) { 3651 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3652 goto err_traps_init; 3653 } 3654 3655 err = mlxsw_sp_buffers_init(mlxsw_sp); 3656 if (err) { 3657 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3658 goto err_buffers_init; 3659 } 3660 3661 err = mlxsw_sp_lag_init(mlxsw_sp); 3662 if (err) { 3663 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3664 goto err_lag_init; 3665 } 3666 3667 /* Initialize SPAN before router and switchdev, so that those components 3668 * can call mlxsw_sp_span_respin(). 3669 */ 3670 err = mlxsw_sp_span_init(mlxsw_sp); 3671 if (err) { 3672 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3673 goto err_span_init; 3674 } 3675 3676 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3677 if (err) { 3678 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3679 goto err_switchdev_init; 3680 } 3681 3682 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3683 if (err) { 3684 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3685 goto err_counter_pool_init; 3686 } 3687 3688 err = mlxsw_sp_afa_init(mlxsw_sp); 3689 if (err) { 3690 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3691 goto err_afa_init; 3692 } 3693 3694 err = mlxsw_sp_router_init(mlxsw_sp); 3695 if (err) { 3696 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3697 goto err_router_init; 3698 } 3699 3700 /* Initialize netdevice notifier after router and SPAN is initialized, 3701 * so that the event handler can use router structures and call SPAN 3702 * respin. 3703 */ 3704 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3705 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3706 if (err) { 3707 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3708 goto err_netdev_notifier; 3709 } 3710 3711 err = mlxsw_sp_acl_init(mlxsw_sp); 3712 if (err) { 3713 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3714 goto err_acl_init; 3715 } 3716 3717 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3718 if (err) { 3719 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3720 goto err_dpipe_init; 3721 } 3722 3723 err = mlxsw_sp_ports_create(mlxsw_sp); 3724 if (err) { 3725 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3726 goto err_ports_create; 3727 } 3728 3729 return 0; 3730 3731 err_ports_create: 3732 mlxsw_sp_dpipe_fini(mlxsw_sp); 3733 err_dpipe_init: 3734 mlxsw_sp_acl_fini(mlxsw_sp); 3735 err_acl_init: 3736 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3737 err_netdev_notifier: 3738 mlxsw_sp_router_fini(mlxsw_sp); 3739 err_router_init: 3740 mlxsw_sp_afa_fini(mlxsw_sp); 3741 err_afa_init: 3742 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3743 err_counter_pool_init: 3744 mlxsw_sp_switchdev_fini(mlxsw_sp); 3745 err_switchdev_init: 3746 mlxsw_sp_span_fini(mlxsw_sp); 3747 err_span_init: 3748 mlxsw_sp_lag_fini(mlxsw_sp); 3749 err_lag_init: 3750 mlxsw_sp_buffers_fini(mlxsw_sp); 3751 err_buffers_init: 3752 mlxsw_sp_traps_fini(mlxsw_sp); 3753 err_traps_init: 3754 mlxsw_sp_fids_fini(mlxsw_sp); 3755 err_fids_init: 3756 mlxsw_sp_kvdl_fini(mlxsw_sp); 3757 return err; 3758 } 3759 3760 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3761 { 3762 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3763 3764 mlxsw_sp_ports_remove(mlxsw_sp); 3765 mlxsw_sp_dpipe_fini(mlxsw_sp); 3766 mlxsw_sp_acl_fini(mlxsw_sp); 3767 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3768 mlxsw_sp_router_fini(mlxsw_sp); 3769 mlxsw_sp_afa_fini(mlxsw_sp); 3770 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3771 mlxsw_sp_switchdev_fini(mlxsw_sp); 3772 mlxsw_sp_span_fini(mlxsw_sp); 3773 mlxsw_sp_lag_fini(mlxsw_sp); 3774 mlxsw_sp_buffers_fini(mlxsw_sp); 3775 mlxsw_sp_traps_fini(mlxsw_sp); 3776 mlxsw_sp_fids_fini(mlxsw_sp); 3777 mlxsw_sp_kvdl_fini(mlxsw_sp); 3778 } 3779 3780 static const struct mlxsw_config_profile mlxsw_sp_config_profile = { 3781 .used_max_mid = 1, 3782 .max_mid = MLXSW_SP_MID_MAX, 3783 .used_flood_tables = 1, 3784 .used_flood_mode = 1, 3785 .flood_mode = 3, 3786 .max_fid_offset_flood_tables = 3, 3787 .fid_offset_flood_table_size = VLAN_N_VID - 1, 3788 .max_fid_flood_tables = 3, 3789 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 3790 .used_max_ib_mc = 1, 3791 .max_ib_mc = 0, 3792 .used_max_pkey = 1, 3793 .max_pkey = 0, 3794 .used_kvd_sizes = 1, 3795 .kvd_hash_single_parts = 59, 3796 .kvd_hash_double_parts = 41, 3797 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3798 .swid_config = { 3799 { 3800 .used_type = 1, 3801 .type = MLXSW_PORT_SWID_TYPE_ETH, 3802 } 3803 }, 3804 }; 3805 3806 static void 3807 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3808 struct devlink_resource_size_params *kvd_size_params, 3809 struct devlink_resource_size_params *linear_size_params, 3810 struct devlink_resource_size_params *hash_double_size_params, 3811 struct devlink_resource_size_params *hash_single_size_params) 3812 { 3813 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3814 KVD_SINGLE_MIN_SIZE); 3815 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3816 KVD_DOUBLE_MIN_SIZE); 3817 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3818 u32 linear_size_min = 0; 3819 3820 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3821 MLXSW_SP_KVD_GRANULARITY, 3822 DEVLINK_RESOURCE_UNIT_ENTRY); 3823 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3824 kvd_size - single_size_min - 3825 double_size_min, 3826 MLXSW_SP_KVD_GRANULARITY, 3827 DEVLINK_RESOURCE_UNIT_ENTRY); 3828 devlink_resource_size_params_init(hash_double_size_params, 3829 double_size_min, 3830 kvd_size - single_size_min - 3831 linear_size_min, 3832 MLXSW_SP_KVD_GRANULARITY, 3833 DEVLINK_RESOURCE_UNIT_ENTRY); 3834 devlink_resource_size_params_init(hash_single_size_params, 3835 single_size_min, 3836 kvd_size - double_size_min - 3837 linear_size_min, 3838 MLXSW_SP_KVD_GRANULARITY, 3839 DEVLINK_RESOURCE_UNIT_ENTRY); 3840 } 3841 3842 static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core) 3843 { 3844 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3845 struct devlink_resource_size_params hash_single_size_params; 3846 struct devlink_resource_size_params hash_double_size_params; 3847 struct devlink_resource_size_params linear_size_params; 3848 struct devlink_resource_size_params kvd_size_params; 3849 u32 kvd_size, single_size, double_size, linear_size; 3850 const struct mlxsw_config_profile *profile; 3851 int err; 3852 3853 profile = &mlxsw_sp_config_profile; 3854 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3855 return -EIO; 3856 3857 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3858 &linear_size_params, 3859 &hash_double_size_params, 3860 &hash_single_size_params); 3861 3862 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3863 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3864 kvd_size, MLXSW_SP_RESOURCE_KVD, 3865 DEVLINK_RESOURCE_ID_PARENT_TOP, 3866 &kvd_size_params); 3867 if (err) 3868 return err; 3869 3870 linear_size = profile->kvd_linear_size; 3871 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3872 linear_size, 3873 MLXSW_SP_RESOURCE_KVD_LINEAR, 3874 MLXSW_SP_RESOURCE_KVD, 3875 &linear_size_params); 3876 if (err) 3877 return err; 3878 3879 err = mlxsw_sp_kvdl_resources_register(mlxsw_core); 3880 if (err) 3881 return err; 3882 3883 double_size = kvd_size - linear_size; 3884 double_size *= profile->kvd_hash_double_parts; 3885 double_size /= profile->kvd_hash_double_parts + 3886 profile->kvd_hash_single_parts; 3887 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3888 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3889 double_size, 3890 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3891 MLXSW_SP_RESOURCE_KVD, 3892 &hash_double_size_params); 3893 if (err) 3894 return err; 3895 3896 single_size = kvd_size - double_size - linear_size; 3897 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3898 single_size, 3899 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3900 MLXSW_SP_RESOURCE_KVD, 3901 &hash_single_size_params); 3902 if (err) 3903 return err; 3904 3905 return 0; 3906 } 3907 3908 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3909 const struct mlxsw_config_profile *profile, 3910 u64 *p_single_size, u64 *p_double_size, 3911 u64 *p_linear_size) 3912 { 3913 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3914 u32 double_size; 3915 int err; 3916 3917 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3918 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3919 return -EIO; 3920 3921 /* The hash part is what left of the kvd without the 3922 * linear part. It is split to the single size and 3923 * double size by the parts ratio from the profile. 3924 * Both sizes must be a multiplications of the 3925 * granularity from the profile. In case the user 3926 * provided the sizes they are obtained via devlink. 3927 */ 3928 err = devlink_resource_size_get(devlink, 3929 MLXSW_SP_RESOURCE_KVD_LINEAR, 3930 p_linear_size); 3931 if (err) 3932 *p_linear_size = profile->kvd_linear_size; 3933 3934 err = devlink_resource_size_get(devlink, 3935 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3936 p_double_size); 3937 if (err) { 3938 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3939 *p_linear_size; 3940 double_size *= profile->kvd_hash_double_parts; 3941 double_size /= profile->kvd_hash_double_parts + 3942 profile->kvd_hash_single_parts; 3943 *p_double_size = rounddown(double_size, 3944 MLXSW_SP_KVD_GRANULARITY); 3945 } 3946 3947 err = devlink_resource_size_get(devlink, 3948 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3949 p_single_size); 3950 if (err) 3951 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3952 *p_double_size - *p_linear_size; 3953 3954 /* Check results are legal. */ 3955 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3956 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3957 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3958 return -EIO; 3959 3960 return 0; 3961 } 3962 3963 static struct mlxsw_driver mlxsw_sp_driver = { 3964 .kind = mlxsw_sp_driver_name, 3965 .priv_size = sizeof(struct mlxsw_sp), 3966 .init = mlxsw_sp_init, 3967 .fini = mlxsw_sp_fini, 3968 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3969 .port_split = mlxsw_sp_port_split, 3970 .port_unsplit = mlxsw_sp_port_unsplit, 3971 .sb_pool_get = mlxsw_sp_sb_pool_get, 3972 .sb_pool_set = mlxsw_sp_sb_pool_set, 3973 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3974 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3975 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3976 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3977 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3978 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3979 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3980 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3981 .txhdr_construct = mlxsw_sp_txhdr_construct, 3982 .resources_register = mlxsw_sp_resources_register, 3983 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 3984 .txhdr_len = MLXSW_TXHDR_LEN, 3985 .profile = &mlxsw_sp_config_profile, 3986 .res_query_enabled = true, 3987 }; 3988 3989 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 3990 { 3991 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 3992 } 3993 3994 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data) 3995 { 3996 struct mlxsw_sp_port **p_mlxsw_sp_port = data; 3997 int ret = 0; 3998 3999 if (mlxsw_sp_port_dev_check(lower_dev)) { 4000 *p_mlxsw_sp_port = netdev_priv(lower_dev); 4001 ret = 1; 4002 } 4003 4004 return ret; 4005 } 4006 4007 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4008 { 4009 struct mlxsw_sp_port *mlxsw_sp_port; 4010 4011 if (mlxsw_sp_port_dev_check(dev)) 4012 return netdev_priv(dev); 4013 4014 mlxsw_sp_port = NULL; 4015 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port); 4016 4017 return mlxsw_sp_port; 4018 } 4019 4020 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4021 { 4022 struct mlxsw_sp_port *mlxsw_sp_port; 4023 4024 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4025 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4026 } 4027 4028 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4029 { 4030 struct mlxsw_sp_port *mlxsw_sp_port; 4031 4032 if (mlxsw_sp_port_dev_check(dev)) 4033 return netdev_priv(dev); 4034 4035 mlxsw_sp_port = NULL; 4036 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4037 &mlxsw_sp_port); 4038 4039 return mlxsw_sp_port; 4040 } 4041 4042 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4043 { 4044 struct mlxsw_sp_port *mlxsw_sp_port; 4045 4046 rcu_read_lock(); 4047 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4048 if (mlxsw_sp_port) 4049 dev_hold(mlxsw_sp_port->dev); 4050 rcu_read_unlock(); 4051 return mlxsw_sp_port; 4052 } 4053 4054 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4055 { 4056 dev_put(mlxsw_sp_port->dev); 4057 } 4058 4059 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4060 { 4061 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4062 4063 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4064 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4065 } 4066 4067 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4068 { 4069 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4070 4071 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4072 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4073 } 4074 4075 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4076 u16 lag_id, u8 port_index) 4077 { 4078 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4079 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4080 4081 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4082 lag_id, port_index); 4083 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4084 } 4085 4086 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4087 u16 lag_id) 4088 { 4089 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4090 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4091 4092 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4093 lag_id); 4094 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4095 } 4096 4097 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4098 u16 lag_id) 4099 { 4100 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4101 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4102 4103 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4104 lag_id); 4105 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4106 } 4107 4108 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4109 u16 lag_id) 4110 { 4111 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4112 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4113 4114 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4115 lag_id); 4116 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4117 } 4118 4119 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4120 struct net_device *lag_dev, 4121 u16 *p_lag_id) 4122 { 4123 struct mlxsw_sp_upper *lag; 4124 int free_lag_id = -1; 4125 u64 max_lag; 4126 int i; 4127 4128 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 4129 for (i = 0; i < max_lag; i++) { 4130 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4131 if (lag->ref_count) { 4132 if (lag->dev == lag_dev) { 4133 *p_lag_id = i; 4134 return 0; 4135 } 4136 } else if (free_lag_id < 0) { 4137 free_lag_id = i; 4138 } 4139 } 4140 if (free_lag_id < 0) 4141 return -EBUSY; 4142 *p_lag_id = free_lag_id; 4143 return 0; 4144 } 4145 4146 static bool 4147 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4148 struct net_device *lag_dev, 4149 struct netdev_lag_upper_info *lag_upper_info, 4150 struct netlink_ext_ack *extack) 4151 { 4152 u16 lag_id; 4153 4154 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4155 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4156 return false; 4157 } 4158 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4159 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4160 return false; 4161 } 4162 return true; 4163 } 4164 4165 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4166 u16 lag_id, u8 *p_port_index) 4167 { 4168 u64 max_lag_members; 4169 int i; 4170 4171 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4172 MAX_LAG_MEMBERS); 4173 for (i = 0; i < max_lag_members; i++) { 4174 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4175 *p_port_index = i; 4176 return 0; 4177 } 4178 } 4179 return -EBUSY; 4180 } 4181 4182 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4183 struct net_device *lag_dev) 4184 { 4185 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4186 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 4187 struct mlxsw_sp_upper *lag; 4188 u16 lag_id; 4189 u8 port_index; 4190 int err; 4191 4192 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4193 if (err) 4194 return err; 4195 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4196 if (!lag->ref_count) { 4197 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4198 if (err) 4199 return err; 4200 lag->dev = lag_dev; 4201 } 4202 4203 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4204 if (err) 4205 return err; 4206 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4207 if (err) 4208 goto err_col_port_add; 4209 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id); 4210 if (err) 4211 goto err_col_port_enable; 4212 4213 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4214 mlxsw_sp_port->local_port); 4215 mlxsw_sp_port->lag_id = lag_id; 4216 mlxsw_sp_port->lagged = 1; 4217 lag->ref_count++; 4218 4219 /* Port is no longer usable as a router interface */ 4220 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1); 4221 if (mlxsw_sp_port_vlan->fid) 4222 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 4223 4224 return 0; 4225 4226 err_col_port_enable: 4227 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4228 err_col_port_add: 4229 if (!lag->ref_count) 4230 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4231 return err; 4232 } 4233 4234 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4235 struct net_device *lag_dev) 4236 { 4237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4238 u16 lag_id = mlxsw_sp_port->lag_id; 4239 struct mlxsw_sp_upper *lag; 4240 4241 if (!mlxsw_sp_port->lagged) 4242 return; 4243 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4244 WARN_ON(lag->ref_count == 0); 4245 4246 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id); 4247 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4248 4249 /* Any VLANs configured on the port are no longer valid */ 4250 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 4251 4252 if (lag->ref_count == 1) 4253 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4254 4255 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4256 mlxsw_sp_port->local_port); 4257 mlxsw_sp_port->lagged = 0; 4258 lag->ref_count--; 4259 4260 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 4261 /* Make sure untagged frames are allowed to ingress */ 4262 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); 4263 } 4264 4265 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4266 u16 lag_id) 4267 { 4268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4269 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4270 4271 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4272 mlxsw_sp_port->local_port); 4273 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4274 } 4275 4276 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4277 u16 lag_id) 4278 { 4279 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4280 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4281 4282 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4283 mlxsw_sp_port->local_port); 4284 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4285 } 4286 4287 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port, 4288 bool lag_tx_enabled) 4289 { 4290 if (lag_tx_enabled) 4291 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, 4292 mlxsw_sp_port->lag_id); 4293 else 4294 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4295 mlxsw_sp_port->lag_id); 4296 } 4297 4298 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4299 struct netdev_lag_lower_state_info *info) 4300 { 4301 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled); 4302 } 4303 4304 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4305 bool enable) 4306 { 4307 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4308 enum mlxsw_reg_spms_state spms_state; 4309 char *spms_pl; 4310 u16 vid; 4311 int err; 4312 4313 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4314 MLXSW_REG_SPMS_STATE_DISCARDING; 4315 4316 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4317 if (!spms_pl) 4318 return -ENOMEM; 4319 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4320 4321 for (vid = 0; vid < VLAN_N_VID; vid++) 4322 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4323 4324 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4325 kfree(spms_pl); 4326 return err; 4327 } 4328 4329 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4330 { 4331 u16 vid = 1; 4332 int err; 4333 4334 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4335 if (err) 4336 return err; 4337 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4338 if (err) 4339 goto err_port_stp_set; 4340 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4341 true, false); 4342 if (err) 4343 goto err_port_vlan_set; 4344 4345 for (; vid <= VLAN_N_VID - 1; vid++) { 4346 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4347 vid, false); 4348 if (err) 4349 goto err_vid_learning_set; 4350 } 4351 4352 return 0; 4353 4354 err_vid_learning_set: 4355 for (vid--; vid >= 1; vid--) 4356 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4357 err_port_vlan_set: 4358 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4359 err_port_stp_set: 4360 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4361 return err; 4362 } 4363 4364 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4365 { 4366 u16 vid; 4367 4368 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4369 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4370 vid, true); 4371 4372 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4373 false, false); 4374 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4375 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4376 } 4377 4378 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4379 struct net_device *dev, 4380 unsigned long event, void *ptr) 4381 { 4382 struct netdev_notifier_changeupper_info *info; 4383 struct mlxsw_sp_port *mlxsw_sp_port; 4384 struct netlink_ext_ack *extack; 4385 struct net_device *upper_dev; 4386 struct mlxsw_sp *mlxsw_sp; 4387 int err = 0; 4388 4389 mlxsw_sp_port = netdev_priv(dev); 4390 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4391 info = ptr; 4392 extack = netdev_notifier_info_to_extack(&info->info); 4393 4394 switch (event) { 4395 case NETDEV_PRECHANGEUPPER: 4396 upper_dev = info->upper_dev; 4397 if (!is_vlan_dev(upper_dev) && 4398 !netif_is_lag_master(upper_dev) && 4399 !netif_is_bridge_master(upper_dev) && 4400 !netif_is_ovs_master(upper_dev)) { 4401 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4402 return -EINVAL; 4403 } 4404 if (!info->linking) 4405 break; 4406 if (netdev_has_any_upper_dev(upper_dev) && 4407 (!netif_is_bridge_master(upper_dev) || 4408 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4409 upper_dev))) { 4410 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4411 return -EINVAL; 4412 } 4413 if (netif_is_lag_master(upper_dev) && 4414 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4415 info->upper_info, extack)) 4416 return -EINVAL; 4417 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4418 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4419 return -EINVAL; 4420 } 4421 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4422 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4423 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4424 return -EINVAL; 4425 } 4426 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4427 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4428 return -EINVAL; 4429 } 4430 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4431 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4432 return -EINVAL; 4433 } 4434 if (is_vlan_dev(upper_dev) && 4435 vlan_dev_vlan_id(upper_dev) == 1) { 4436 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic"); 4437 return -EINVAL; 4438 } 4439 break; 4440 case NETDEV_CHANGEUPPER: 4441 upper_dev = info->upper_dev; 4442 if (netif_is_bridge_master(upper_dev)) { 4443 if (info->linking) 4444 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4445 lower_dev, 4446 upper_dev, 4447 extack); 4448 else 4449 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4450 lower_dev, 4451 upper_dev); 4452 } else if (netif_is_lag_master(upper_dev)) { 4453 if (info->linking) 4454 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4455 upper_dev); 4456 else 4457 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4458 upper_dev); 4459 } else if (netif_is_ovs_master(upper_dev)) { 4460 if (info->linking) 4461 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4462 else 4463 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4464 } 4465 break; 4466 } 4467 4468 return err; 4469 } 4470 4471 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4472 unsigned long event, void *ptr) 4473 { 4474 struct netdev_notifier_changelowerstate_info *info; 4475 struct mlxsw_sp_port *mlxsw_sp_port; 4476 int err; 4477 4478 mlxsw_sp_port = netdev_priv(dev); 4479 info = ptr; 4480 4481 switch (event) { 4482 case NETDEV_CHANGELOWERSTATE: 4483 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4484 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4485 info->lower_state_info); 4486 if (err) 4487 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4488 } 4489 break; 4490 } 4491 4492 return 0; 4493 } 4494 4495 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4496 struct net_device *port_dev, 4497 unsigned long event, void *ptr) 4498 { 4499 switch (event) { 4500 case NETDEV_PRECHANGEUPPER: 4501 case NETDEV_CHANGEUPPER: 4502 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4503 event, ptr); 4504 case NETDEV_CHANGELOWERSTATE: 4505 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4506 ptr); 4507 } 4508 4509 return 0; 4510 } 4511 4512 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4513 unsigned long event, void *ptr) 4514 { 4515 struct net_device *dev; 4516 struct list_head *iter; 4517 int ret; 4518 4519 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4520 if (mlxsw_sp_port_dev_check(dev)) { 4521 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4522 ptr); 4523 if (ret) 4524 return ret; 4525 } 4526 } 4527 4528 return 0; 4529 } 4530 4531 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4532 struct net_device *dev, 4533 unsigned long event, void *ptr, 4534 u16 vid) 4535 { 4536 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4537 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4538 struct netdev_notifier_changeupper_info *info = ptr; 4539 struct netlink_ext_ack *extack; 4540 struct net_device *upper_dev; 4541 int err = 0; 4542 4543 extack = netdev_notifier_info_to_extack(&info->info); 4544 4545 switch (event) { 4546 case NETDEV_PRECHANGEUPPER: 4547 upper_dev = info->upper_dev; 4548 if (!netif_is_bridge_master(upper_dev)) { 4549 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers"); 4550 return -EINVAL; 4551 } 4552 if (!info->linking) 4553 break; 4554 if (netdev_has_any_upper_dev(upper_dev) && 4555 (!netif_is_bridge_master(upper_dev) || 4556 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4557 upper_dev))) { 4558 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4559 return -EINVAL; 4560 } 4561 break; 4562 case NETDEV_CHANGEUPPER: 4563 upper_dev = info->upper_dev; 4564 if (netif_is_bridge_master(upper_dev)) { 4565 if (info->linking) 4566 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4567 vlan_dev, 4568 upper_dev, 4569 extack); 4570 else 4571 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4572 vlan_dev, 4573 upper_dev); 4574 } else { 4575 err = -EINVAL; 4576 WARN_ON(1); 4577 } 4578 break; 4579 } 4580 4581 return err; 4582 } 4583 4584 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4585 struct net_device *lag_dev, 4586 unsigned long event, 4587 void *ptr, u16 vid) 4588 { 4589 struct net_device *dev; 4590 struct list_head *iter; 4591 int ret; 4592 4593 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4594 if (mlxsw_sp_port_dev_check(dev)) { 4595 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4596 event, ptr, 4597 vid); 4598 if (ret) 4599 return ret; 4600 } 4601 } 4602 4603 return 0; 4604 } 4605 4606 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4607 unsigned long event, void *ptr) 4608 { 4609 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4610 u16 vid = vlan_dev_vlan_id(vlan_dev); 4611 4612 if (mlxsw_sp_port_dev_check(real_dev)) 4613 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 4614 event, ptr, vid); 4615 else if (netif_is_lag_master(real_dev)) 4616 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 4617 real_dev, event, 4618 ptr, vid); 4619 4620 return 0; 4621 } 4622 4623 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 4624 { 4625 struct netdev_notifier_changeupper_info *info = ptr; 4626 4627 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 4628 return false; 4629 return netif_is_l3_master(info->upper_dev); 4630 } 4631 4632 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 4633 unsigned long event, void *ptr) 4634 { 4635 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4636 struct mlxsw_sp_span_entry *span_entry; 4637 struct mlxsw_sp *mlxsw_sp; 4638 int err = 0; 4639 4640 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 4641 if (event == NETDEV_UNREGISTER) { 4642 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 4643 if (span_entry) 4644 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 4645 } 4646 mlxsw_sp_span_respin(mlxsw_sp); 4647 4648 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 4649 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 4650 event, ptr); 4651 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 4652 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 4653 event, ptr); 4654 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU) 4655 err = mlxsw_sp_netdevice_router_port_event(dev); 4656 else if (mlxsw_sp_is_vrf_event(event, ptr)) 4657 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 4658 else if (mlxsw_sp_port_dev_check(dev)) 4659 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 4660 else if (netif_is_lag_master(dev)) 4661 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 4662 else if (is_vlan_dev(dev)) 4663 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 4664 4665 return notifier_from_errno(err); 4666 } 4667 4668 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 4669 .notifier_call = mlxsw_sp_inetaddr_valid_event, 4670 }; 4671 4672 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = { 4673 .notifier_call = mlxsw_sp_inetaddr_event, 4674 }; 4675 4676 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 4677 .notifier_call = mlxsw_sp_inet6addr_valid_event, 4678 }; 4679 4680 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = { 4681 .notifier_call = mlxsw_sp_inet6addr_event, 4682 }; 4683 4684 static const struct pci_device_id mlxsw_sp_pci_id_table[] = { 4685 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 4686 {0, }, 4687 }; 4688 4689 static struct pci_driver mlxsw_sp_pci_driver = { 4690 .name = mlxsw_sp_driver_name, 4691 .id_table = mlxsw_sp_pci_id_table, 4692 }; 4693 4694 static int __init mlxsw_sp_module_init(void) 4695 { 4696 int err; 4697 4698 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4699 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4700 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4701 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4702 4703 err = mlxsw_core_driver_register(&mlxsw_sp_driver); 4704 if (err) 4705 goto err_core_driver_register; 4706 4707 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver); 4708 if (err) 4709 goto err_pci_driver_register; 4710 4711 return 0; 4712 4713 err_pci_driver_register: 4714 mlxsw_core_driver_unregister(&mlxsw_sp_driver); 4715 err_core_driver_register: 4716 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4717 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4718 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4719 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4720 return err; 4721 } 4722 4723 static void __exit mlxsw_sp_module_exit(void) 4724 { 4725 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver); 4726 mlxsw_core_driver_unregister(&mlxsw_sp_driver); 4727 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4728 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4729 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4730 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4731 } 4732 4733 module_init(mlxsw_sp_module_init); 4734 module_exit(mlxsw_sp_module_exit); 4735 4736 MODULE_LICENSE("Dual BSD/GPL"); 4737 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 4738 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 4739 MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table); 4740 MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME); 4741