1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/jhash.h> 25 #include <linux/log2.h> 26 #include <linux/refcount.h> 27 #include <linux/rhashtable.h> 28 #include <net/switchdev.h> 29 #include <net/pkt_cls.h> 30 #include <net/netevent.h> 31 #include <net/addrconf.h> 32 #include <linux/ptp_classify.h> 33 34 #include "spectrum.h" 35 #include "pci.h" 36 #include "core.h" 37 #include "core_env.h" 38 #include "reg.h" 39 #include "port.h" 40 #include "trap.h" 41 #include "txheader.h" 42 #include "spectrum_cnt.h" 43 #include "spectrum_dpipe.h" 44 #include "spectrum_acl_flex_actions.h" 45 #include "spectrum_span.h" 46 #include "spectrum_ptp.h" 47 #include "spectrum_trap.h" 48 49 #define MLXSW_SP_FWREV_MINOR 2010 50 #define MLXSW_SP_FWREV_SUBMINOR 1006 51 52 #define MLXSW_SP1_FWREV_MAJOR 13 53 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 54 55 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 56 .major = MLXSW_SP1_FWREV_MAJOR, 57 .minor = MLXSW_SP_FWREV_MINOR, 58 .subminor = MLXSW_SP_FWREV_SUBMINOR, 59 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 60 }; 61 62 #define MLXSW_SP1_FW_FILENAME \ 63 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 64 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 65 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 66 67 #define MLXSW_SP2_FWREV_MAJOR 29 68 69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = { 70 .major = MLXSW_SP2_FWREV_MAJOR, 71 .minor = MLXSW_SP_FWREV_MINOR, 72 .subminor = MLXSW_SP_FWREV_SUBMINOR, 73 }; 74 75 #define MLXSW_SP2_FW_FILENAME \ 76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \ 77 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 78 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 79 80 #define MLXSW_SP3_FWREV_MAJOR 30 81 82 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = { 83 .major = MLXSW_SP3_FWREV_MAJOR, 84 .minor = MLXSW_SP_FWREV_MINOR, 85 .subminor = MLXSW_SP_FWREV_SUBMINOR, 86 }; 87 88 #define MLXSW_SP3_FW_FILENAME \ 89 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \ 90 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 91 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 92 93 #define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \ 94 "mellanox/lc_ini_bundle_" \ 95 __stringify(MLXSW_SP_FWREV_MINOR) "_" \ 96 __stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin" 97 98 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 99 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 100 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3"; 101 static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4"; 102 103 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = { 104 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00 105 }; 106 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = { 107 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00 108 }; 109 110 /* tx_hdr_version 111 * Tx header version. 112 * Must be set to 1. 113 */ 114 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 115 116 /* tx_hdr_ctl 117 * Packet control type. 118 * 0 - Ethernet control (e.g. EMADs, LACP) 119 * 1 - Ethernet data 120 */ 121 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 122 123 /* tx_hdr_proto 124 * Packet protocol type. Must be set to 1 (Ethernet). 125 */ 126 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 127 128 /* tx_hdr_rx_is_router 129 * Packet is sent from the router. Valid for data packets only. 130 */ 131 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 132 133 /* tx_hdr_fid_valid 134 * Indicates if the 'fid' field is valid and should be used for 135 * forwarding lookup. Valid for data packets only. 136 */ 137 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 138 139 /* tx_hdr_swid 140 * Switch partition ID. Must be set to 0. 141 */ 142 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 143 144 /* tx_hdr_control_tclass 145 * Indicates if the packet should use the control TClass and not one 146 * of the data TClasses. 147 */ 148 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 149 150 /* tx_hdr_etclass 151 * Egress TClass to be used on the egress device on the egress port. 152 */ 153 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 154 155 /* tx_hdr_port_mid 156 * Destination local port for unicast packets. 157 * Destination multicast ID for multicast packets. 158 * 159 * Control packets are directed to a specific egress port, while data 160 * packets are transmitted through the CPU port (0) into the switch partition, 161 * where forwarding rules are applied. 162 */ 163 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 164 165 /* tx_hdr_fid 166 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 167 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 168 * Valid for data packets only. 169 */ 170 MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16); 171 172 /* tx_hdr_type 173 * 0 - Data packets 174 * 6 - Control packets 175 */ 176 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 177 178 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 179 unsigned int counter_index, u64 *packets, 180 u64 *bytes) 181 { 182 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 183 int err; 184 185 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 186 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 187 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 188 if (err) 189 return err; 190 if (packets) 191 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 192 if (bytes) 193 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 194 return 0; 195 } 196 197 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 198 unsigned int counter_index) 199 { 200 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 201 202 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 203 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 204 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 205 } 206 207 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 208 unsigned int *p_counter_index) 209 { 210 int err; 211 212 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 213 p_counter_index); 214 if (err) 215 return err; 216 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 217 if (err) 218 goto err_counter_clear; 219 return 0; 220 221 err_counter_clear: 222 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 223 *p_counter_index); 224 return err; 225 } 226 227 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 228 unsigned int counter_index) 229 { 230 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 231 counter_index); 232 } 233 234 void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 235 const struct mlxsw_tx_info *tx_info) 236 { 237 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 238 239 memset(txhdr, 0, MLXSW_TXHDR_LEN); 240 241 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 242 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 243 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 244 mlxsw_tx_hdr_swid_set(txhdr, 0); 245 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 246 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 247 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 248 } 249 250 int 251 mlxsw_sp_txhdr_ptp_data_construct(struct mlxsw_core *mlxsw_core, 252 struct mlxsw_sp_port *mlxsw_sp_port, 253 struct sk_buff *skb, 254 const struct mlxsw_tx_info *tx_info) 255 { 256 char *txhdr; 257 u16 max_fid; 258 int err; 259 260 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) { 261 err = -ENOMEM; 262 goto err_skb_cow_head; 263 } 264 265 if (!MLXSW_CORE_RES_VALID(mlxsw_core, FID)) { 266 err = -EIO; 267 goto err_res_valid; 268 } 269 max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID); 270 271 txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 272 memset(txhdr, 0, MLXSW_TXHDR_LEN); 273 274 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 275 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 276 mlxsw_tx_hdr_rx_is_router_set(txhdr, true); 277 mlxsw_tx_hdr_fid_valid_set(txhdr, true); 278 mlxsw_tx_hdr_fid_set(txhdr, max_fid + tx_info->local_port - 1); 279 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_DATA); 280 return 0; 281 282 err_res_valid: 283 err_skb_cow_head: 284 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 285 dev_kfree_skb_any(skb); 286 return err; 287 } 288 289 static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb) 290 { 291 unsigned int type; 292 293 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 294 return false; 295 296 type = ptp_classify_raw(skb); 297 return !!ptp_parse_header(skb, type); 298 } 299 300 static int mlxsw_sp_txhdr_handle(struct mlxsw_core *mlxsw_core, 301 struct mlxsw_sp_port *mlxsw_sp_port, 302 struct sk_buff *skb, 303 const struct mlxsw_tx_info *tx_info) 304 { 305 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 306 307 /* In Spectrum-2 and Spectrum-3, PTP events that require a time stamp 308 * need special handling and cannot be transmitted as regular control 309 * packets. 310 */ 311 if (unlikely(mlxsw_sp_skb_requires_ts(skb))) 312 return mlxsw_sp->ptp_ops->txhdr_construct(mlxsw_core, 313 mlxsw_sp_port, skb, 314 tx_info); 315 316 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) { 317 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 318 dev_kfree_skb_any(skb); 319 return -ENOMEM; 320 } 321 322 mlxsw_sp_txhdr_construct(skb, tx_info); 323 return 0; 324 } 325 326 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 327 { 328 switch (state) { 329 case BR_STATE_FORWARDING: 330 return MLXSW_REG_SPMS_STATE_FORWARDING; 331 case BR_STATE_LEARNING: 332 return MLXSW_REG_SPMS_STATE_LEARNING; 333 case BR_STATE_LISTENING: 334 case BR_STATE_DISABLED: 335 case BR_STATE_BLOCKING: 336 return MLXSW_REG_SPMS_STATE_DISCARDING; 337 default: 338 BUG(); 339 } 340 } 341 342 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 343 u8 state) 344 { 345 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 346 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 347 char *spms_pl; 348 int err; 349 350 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 351 if (!spms_pl) 352 return -ENOMEM; 353 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 354 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 355 356 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 357 kfree(spms_pl); 358 return err; 359 } 360 361 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 362 { 363 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 364 int err; 365 366 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 367 if (err) 368 return err; 369 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 370 return 0; 371 } 372 373 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 374 bool is_up) 375 { 376 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 377 char paos_pl[MLXSW_REG_PAOS_LEN]; 378 379 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 380 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 381 MLXSW_PORT_ADMIN_STATUS_DOWN); 382 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 383 } 384 385 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 386 const unsigned char *addr) 387 { 388 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 389 char ppad_pl[MLXSW_REG_PPAD_LEN]; 390 391 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 392 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 393 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 394 } 395 396 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 397 { 398 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 399 400 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac, 401 mlxsw_sp_port->local_port); 402 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, 403 mlxsw_sp_port->dev->dev_addr); 404 } 405 406 static int mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port *mlxsw_sp_port, int *p_max_mtu) 407 { 408 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 409 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 410 int err; 411 412 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 413 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 414 if (err) 415 return err; 416 417 *p_max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 418 return 0; 419 } 420 421 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 422 { 423 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 424 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 425 426 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 427 if (mtu > mlxsw_sp_port->max_mtu) 428 return -EINVAL; 429 430 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 431 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 432 } 433 434 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, 435 u16 local_port, u8 swid) 436 { 437 char pspa_pl[MLXSW_REG_PSPA_LEN]; 438 439 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port); 440 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 441 } 442 443 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 444 { 445 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 446 char svpe_pl[MLXSW_REG_SVPE_LEN]; 447 448 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 449 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 450 } 451 452 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 453 bool learn_enable) 454 { 455 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 456 char *spvmlr_pl; 457 int err; 458 459 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 460 if (!spvmlr_pl) 461 return -ENOMEM; 462 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 463 learn_enable); 464 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 465 kfree(spvmlr_pl); 466 return err; 467 } 468 469 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type) 470 { 471 switch (ethtype) { 472 case ETH_P_8021Q: 473 *p_sver_type = 0; 474 break; 475 case ETH_P_8021AD: 476 *p_sver_type = 1; 477 break; 478 default: 479 return -EINVAL; 480 } 481 482 return 0; 483 } 484 485 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port, 486 u16 ethtype) 487 { 488 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 489 char spevet_pl[MLXSW_REG_SPEVET_LEN]; 490 u8 sver_type; 491 int err; 492 493 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 494 if (err) 495 return err; 496 497 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type); 498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl); 499 } 500 501 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 502 u16 vid, u16 ethtype) 503 { 504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 505 char spvid_pl[MLXSW_REG_SPVID_LEN]; 506 u8 sver_type; 507 int err; 508 509 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 510 if (err) 511 return err; 512 513 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid, 514 sver_type); 515 516 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 517 } 518 519 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 520 bool allow) 521 { 522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 523 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 524 525 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 526 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 527 } 528 529 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 530 u16 ethtype) 531 { 532 int err; 533 534 if (!vid) { 535 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 536 if (err) 537 return err; 538 } else { 539 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype); 540 if (err) 541 return err; 542 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 543 if (err) 544 goto err_port_allow_untagged_set; 545 } 546 547 mlxsw_sp_port->pvid = vid; 548 return 0; 549 550 err_port_allow_untagged_set: 551 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype); 552 return err; 553 } 554 555 static int 556 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 557 { 558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 559 char sspr_pl[MLXSW_REG_SSPR_LEN]; 560 561 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 563 } 564 565 static int 566 mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp, 567 u16 local_port, char *pmlp_pl, 568 struct mlxsw_sp_port_mapping *port_mapping) 569 { 570 bool separate_rxtx; 571 u8 first_lane; 572 u8 slot_index; 573 u8 module; 574 u8 width; 575 int i; 576 577 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 578 slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0); 579 width = mlxsw_reg_pmlp_width_get(pmlp_pl); 580 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl); 581 first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 582 583 if (width && !is_power_of_2(width)) { 584 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n", 585 local_port); 586 return -EINVAL; 587 } 588 589 for (i = 0; i < width; i++) { 590 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) { 591 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n", 592 local_port); 593 return -EINVAL; 594 } 595 if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) { 596 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n", 597 local_port); 598 return -EINVAL; 599 } 600 if (separate_rxtx && 601 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != 602 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) { 603 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n", 604 local_port); 605 return -EINVAL; 606 } 607 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) { 608 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n", 609 local_port); 610 return -EINVAL; 611 } 612 } 613 614 port_mapping->module = module; 615 port_mapping->slot_index = slot_index; 616 port_mapping->width = width; 617 port_mapping->module_width = width; 618 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 619 return 0; 620 } 621 622 static int 623 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port, 624 struct mlxsw_sp_port_mapping *port_mapping) 625 { 626 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 627 int err; 628 629 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 630 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 631 if (err) 632 return err; 633 return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 634 pmlp_pl, port_mapping); 635 } 636 637 static int 638 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port, 639 const struct mlxsw_sp_port_mapping *port_mapping) 640 { 641 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 642 int i, err; 643 644 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index, 645 port_mapping->module); 646 647 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 648 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width); 649 for (i = 0; i < port_mapping->width; i++) { 650 mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i, 651 port_mapping->slot_index); 652 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module); 653 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */ 654 } 655 656 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 657 if (err) 658 goto err_pmlp_write; 659 return 0; 660 661 err_pmlp_write: 662 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index, 663 port_mapping->module); 664 return err; 665 } 666 667 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port, 668 u8 slot_index, u8 module) 669 { 670 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 671 672 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 673 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 674 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 675 mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module); 676 } 677 678 static int mlxsw_sp_port_open(struct net_device *dev) 679 { 680 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 682 int err; 683 684 err = mlxsw_env_module_port_up(mlxsw_sp->core, 685 mlxsw_sp_port->mapping.slot_index, 686 mlxsw_sp_port->mapping.module); 687 if (err) 688 return err; 689 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 690 if (err) 691 goto err_port_admin_status_set; 692 netif_start_queue(dev); 693 return 0; 694 695 err_port_admin_status_set: 696 mlxsw_env_module_port_down(mlxsw_sp->core, 697 mlxsw_sp_port->mapping.slot_index, 698 mlxsw_sp_port->mapping.module); 699 return err; 700 } 701 702 static int mlxsw_sp_port_stop(struct net_device *dev) 703 { 704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 705 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 706 707 netif_stop_queue(dev); 708 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 709 mlxsw_env_module_port_down(mlxsw_sp->core, 710 mlxsw_sp_port->mapping.slot_index, 711 mlxsw_sp_port->mapping.module); 712 return 0; 713 } 714 715 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 716 struct net_device *dev) 717 { 718 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 719 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 720 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 721 const struct mlxsw_tx_info tx_info = { 722 .local_port = mlxsw_sp_port->local_port, 723 .is_emad = false, 724 }; 725 u64 len; 726 int err; 727 728 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb)); 729 730 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 731 return NETDEV_TX_BUSY; 732 733 if (eth_skb_pad(skb)) { 734 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 735 return NETDEV_TX_OK; 736 } 737 738 err = mlxsw_sp_txhdr_handle(mlxsw_sp->core, mlxsw_sp_port, skb, 739 &tx_info); 740 if (err) 741 return NETDEV_TX_OK; 742 743 /* TX header is consumed by HW on the way so we shouldn't count its 744 * bytes as being sent. 745 */ 746 len = skb->len - MLXSW_TXHDR_LEN; 747 748 /* Due to a race we might fail here because of a full queue. In that 749 * unlikely case we simply drop the packet. 750 */ 751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 752 753 if (!err) { 754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 755 u64_stats_update_begin(&pcpu_stats->syncp); 756 pcpu_stats->tx_packets++; 757 pcpu_stats->tx_bytes += len; 758 u64_stats_update_end(&pcpu_stats->syncp); 759 } else { 760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 761 dev_kfree_skb_any(skb); 762 } 763 return NETDEV_TX_OK; 764 } 765 766 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 767 { 768 } 769 770 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 771 { 772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 773 struct sockaddr *addr = p; 774 int err; 775 776 if (!is_valid_ether_addr(addr->sa_data)) 777 return -EADDRNOTAVAIL; 778 779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 780 if (err) 781 return err; 782 eth_hw_addr_set(dev, addr->sa_data); 783 return 0; 784 } 785 786 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 787 { 788 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 789 struct mlxsw_sp_hdroom orig_hdroom; 790 struct mlxsw_sp_hdroom hdroom; 791 int err; 792 793 orig_hdroom = *mlxsw_sp_port->hdroom; 794 795 hdroom = orig_hdroom; 796 hdroom.mtu = mtu; 797 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom); 798 799 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom); 800 if (err) { 801 netdev_err(dev, "Failed to configure port's headroom\n"); 802 return err; 803 } 804 805 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 806 if (err) 807 goto err_port_mtu_set; 808 dev->mtu = mtu; 809 return 0; 810 811 err_port_mtu_set: 812 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom); 813 return err; 814 } 815 816 static int 817 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 818 struct rtnl_link_stats64 *stats) 819 { 820 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 821 struct mlxsw_sp_port_pcpu_stats *p; 822 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 823 u32 tx_dropped = 0; 824 unsigned int start; 825 int i; 826 827 for_each_possible_cpu(i) { 828 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 829 do { 830 start = u64_stats_fetch_begin(&p->syncp); 831 rx_packets = p->rx_packets; 832 rx_bytes = p->rx_bytes; 833 tx_packets = p->tx_packets; 834 tx_bytes = p->tx_bytes; 835 } while (u64_stats_fetch_retry(&p->syncp, start)); 836 837 stats->rx_packets += rx_packets; 838 stats->rx_bytes += rx_bytes; 839 stats->tx_packets += tx_packets; 840 stats->tx_bytes += tx_bytes; 841 /* tx_dropped is u32, updated without syncp protection. */ 842 tx_dropped += p->tx_dropped; 843 } 844 stats->tx_dropped = tx_dropped; 845 return 0; 846 } 847 848 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 849 { 850 switch (attr_id) { 851 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 852 return true; 853 } 854 855 return false; 856 } 857 858 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 859 void *sp) 860 { 861 switch (attr_id) { 862 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 863 return mlxsw_sp_port_get_sw_stats64(dev, sp); 864 } 865 866 return -EINVAL; 867 } 868 869 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 870 int prio, char *ppcnt_pl) 871 { 872 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 873 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 874 875 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 876 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 877 } 878 879 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 880 struct rtnl_link_stats64 *stats) 881 { 882 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 883 int err; 884 885 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 886 0, ppcnt_pl); 887 if (err) 888 goto out; 889 890 stats->tx_packets = 891 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 892 stats->rx_packets = 893 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 894 stats->tx_bytes = 895 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 896 stats->rx_bytes = 897 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 898 stats->multicast = 899 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 900 901 stats->rx_crc_errors = 902 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 903 stats->rx_frame_errors = 904 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 905 906 stats->rx_length_errors = ( 907 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 908 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 909 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 910 911 stats->rx_errors = (stats->rx_crc_errors + 912 stats->rx_frame_errors + stats->rx_length_errors); 913 914 out: 915 return err; 916 } 917 918 static void 919 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 920 struct mlxsw_sp_port_xstats *xstats) 921 { 922 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 923 int err, i; 924 925 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 926 ppcnt_pl); 927 if (!err) 928 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 929 930 for (i = 0; i < TC_MAX_QUEUE; i++) { 931 err = mlxsw_sp_port_get_stats_raw(dev, 932 MLXSW_REG_PPCNT_TC_CONG_CNT, 933 i, ppcnt_pl); 934 if (err) 935 goto tc_cnt; 936 937 xstats->wred_drop[i] = 938 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 939 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl); 940 941 tc_cnt: 942 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 943 i, ppcnt_pl); 944 if (err) 945 continue; 946 947 xstats->backlog[i] = 948 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 949 xstats->tail_drop[i] = 950 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 951 } 952 953 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 954 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 955 i, ppcnt_pl); 956 if (err) 957 continue; 958 959 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 960 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 961 } 962 } 963 964 static void update_stats_cache(struct work_struct *work) 965 { 966 struct mlxsw_sp_port *mlxsw_sp_port = 967 container_of(work, struct mlxsw_sp_port, 968 periodic_hw_stats.update_dw.work); 969 970 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 971 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as 972 * necessary when port goes down. 973 */ 974 goto out; 975 976 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 977 &mlxsw_sp_port->periodic_hw_stats.stats); 978 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 979 &mlxsw_sp_port->periodic_hw_stats.xstats); 980 981 out: 982 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 983 MLXSW_HW_STATS_UPDATE_TIME); 984 } 985 986 /* Return the stats from a cache that is updated periodically, 987 * as this function might get called in an atomic context. 988 */ 989 static void 990 mlxsw_sp_port_get_stats64(struct net_device *dev, 991 struct rtnl_link_stats64 *stats) 992 { 993 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 994 995 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 996 } 997 998 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 999 u16 vid_begin, u16 vid_end, 1000 bool is_member, bool untagged) 1001 { 1002 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1003 char *spvm_pl; 1004 int err; 1005 1006 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1007 if (!spvm_pl) 1008 return -ENOMEM; 1009 1010 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1011 vid_end, is_member, untagged); 1012 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1013 kfree(spvm_pl); 1014 return err; 1015 } 1016 1017 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1018 u16 vid_end, bool is_member, bool untagged) 1019 { 1020 u16 vid, vid_e; 1021 int err; 1022 1023 for (vid = vid_begin; vid <= vid_end; 1024 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1025 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1026 vid_end); 1027 1028 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1029 is_member, untagged); 1030 if (err) 1031 return err; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port, 1038 bool flush_default) 1039 { 1040 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1041 1042 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1043 &mlxsw_sp_port->vlans_list, list) { 1044 if (!flush_default && 1045 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID) 1046 continue; 1047 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1048 } 1049 } 1050 1051 static void 1052 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1053 { 1054 if (mlxsw_sp_port_vlan->bridge_port) 1055 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1056 else if (mlxsw_sp_port_vlan->fid) 1057 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1058 } 1059 1060 struct mlxsw_sp_port_vlan * 1061 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1062 { 1063 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1064 bool untagged = vid == MLXSW_SP_DEFAULT_VID; 1065 int err; 1066 1067 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1068 if (mlxsw_sp_port_vlan) 1069 return ERR_PTR(-EEXIST); 1070 1071 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1072 if (err) 1073 return ERR_PTR(err); 1074 1075 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1076 if (!mlxsw_sp_port_vlan) { 1077 err = -ENOMEM; 1078 goto err_port_vlan_alloc; 1079 } 1080 1081 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1082 mlxsw_sp_port_vlan->vid = vid; 1083 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1084 1085 return mlxsw_sp_port_vlan; 1086 1087 err_port_vlan_alloc: 1088 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1089 return ERR_PTR(err); 1090 } 1091 1092 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1093 { 1094 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1095 u16 vid = mlxsw_sp_port_vlan->vid; 1096 1097 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan); 1098 list_del(&mlxsw_sp_port_vlan->list); 1099 kfree(mlxsw_sp_port_vlan); 1100 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1101 } 1102 1103 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1104 __be16 __always_unused proto, u16 vid) 1105 { 1106 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1107 1108 /* VLAN 0 is added to HW filter when device goes up, but it is 1109 * reserved in our case, so simply return. 1110 */ 1111 if (!vid) 1112 return 0; 1113 1114 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid)); 1115 } 1116 1117 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1118 __be16 __always_unused proto, u16 vid) 1119 { 1120 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1121 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1122 1123 /* VLAN 0 is removed from HW filter when device goes down, but 1124 * it is reserved in our case, so simply return. 1125 */ 1126 if (!vid) 1127 return 0; 1128 1129 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1130 if (!mlxsw_sp_port_vlan) 1131 return 0; 1132 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1133 1134 return 0; 1135 } 1136 1137 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1138 struct flow_block_offload *f) 1139 { 1140 switch (f->binder_type) { 1141 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS: 1142 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true); 1143 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS: 1144 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false); 1145 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP: 1146 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f); 1147 case FLOW_BLOCK_BINDER_TYPE_RED_MARK: 1148 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f); 1149 default: 1150 return -EOPNOTSUPP; 1151 } 1152 } 1153 1154 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1155 void *type_data) 1156 { 1157 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1158 1159 switch (type) { 1160 case TC_SETUP_BLOCK: 1161 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1162 case TC_SETUP_QDISC_RED: 1163 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1164 case TC_SETUP_QDISC_PRIO: 1165 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1166 case TC_SETUP_QDISC_ETS: 1167 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data); 1168 case TC_SETUP_QDISC_TBF: 1169 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data); 1170 case TC_SETUP_QDISC_FIFO: 1171 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data); 1172 default: 1173 return -EOPNOTSUPP; 1174 } 1175 } 1176 1177 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1178 { 1179 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1180 1181 if (!enable) { 1182 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) || 1183 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) { 1184 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1185 return -EINVAL; 1186 } 1187 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block); 1188 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block); 1189 } else { 1190 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block); 1191 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block); 1192 } 1193 return 0; 1194 } 1195 1196 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable) 1197 { 1198 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1199 char pplr_pl[MLXSW_REG_PPLR_LEN]; 1200 int err; 1201 1202 if (netif_running(dev)) 1203 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1204 1205 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable); 1206 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr), 1207 pplr_pl); 1208 1209 if (netif_running(dev)) 1210 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 1211 1212 return err; 1213 } 1214 1215 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1216 1217 static int mlxsw_sp_handle_feature(struct net_device *dev, 1218 netdev_features_t wanted_features, 1219 netdev_features_t feature, 1220 mlxsw_sp_feature_handler feature_handler) 1221 { 1222 netdev_features_t changes = wanted_features ^ dev->features; 1223 bool enable = !!(wanted_features & feature); 1224 int err; 1225 1226 if (!(changes & feature)) 1227 return 0; 1228 1229 err = feature_handler(dev, enable); 1230 if (err) { 1231 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1232 enable ? "Enable" : "Disable", &feature, err); 1233 return err; 1234 } 1235 1236 if (enable) 1237 dev->features |= feature; 1238 else 1239 dev->features &= ~feature; 1240 1241 return 0; 1242 } 1243 static int mlxsw_sp_set_features(struct net_device *dev, 1244 netdev_features_t features) 1245 { 1246 netdev_features_t oper_features = dev->features; 1247 int err = 0; 1248 1249 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1250 mlxsw_sp_feature_hw_tc); 1251 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK, 1252 mlxsw_sp_feature_loopback); 1253 1254 if (err) { 1255 dev->features = oper_features; 1256 return -EINVAL; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static struct devlink_port * 1263 mlxsw_sp_port_get_devlink_port(struct net_device *dev) 1264 { 1265 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1266 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1267 1268 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core, 1269 mlxsw_sp_port->local_port); 1270 } 1271 1272 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port, 1273 struct ifreq *ifr) 1274 { 1275 struct hwtstamp_config config; 1276 int err; 1277 1278 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1279 return -EFAULT; 1280 1281 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, 1282 &config); 1283 if (err) 1284 return err; 1285 1286 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 1287 return -EFAULT; 1288 1289 return 0; 1290 } 1291 1292 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port, 1293 struct ifreq *ifr) 1294 { 1295 struct hwtstamp_config config; 1296 int err; 1297 1298 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port, 1299 &config); 1300 if (err) 1301 return err; 1302 1303 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 1304 return -EFAULT; 1305 1306 return 0; 1307 } 1308 1309 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port) 1310 { 1311 struct hwtstamp_config config = {0}; 1312 1313 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config); 1314 } 1315 1316 static int 1317 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1318 { 1319 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1320 1321 switch (cmd) { 1322 case SIOCSHWTSTAMP: 1323 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr); 1324 case SIOCGHWTSTAMP: 1325 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr); 1326 default: 1327 return -EOPNOTSUPP; 1328 } 1329 } 1330 1331 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1332 .ndo_open = mlxsw_sp_port_open, 1333 .ndo_stop = mlxsw_sp_port_stop, 1334 .ndo_start_xmit = mlxsw_sp_port_xmit, 1335 .ndo_setup_tc = mlxsw_sp_setup_tc, 1336 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1337 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1338 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1339 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1340 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1341 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1342 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1343 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1344 .ndo_set_features = mlxsw_sp_set_features, 1345 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port, 1346 .ndo_eth_ioctl = mlxsw_sp_port_ioctl, 1347 }; 1348 1349 static int 1350 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port) 1351 { 1352 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1353 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper; 1354 const struct mlxsw_sp_port_type_speed_ops *ops; 1355 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1356 u32 eth_proto_cap_masked; 1357 int err; 1358 1359 ops = mlxsw_sp->port_type_speed_ops; 1360 1361 /* Set advertised speeds to speeds supported by both the driver 1362 * and the device. 1363 */ 1364 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1365 0, false); 1366 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1367 if (err) 1368 return err; 1369 1370 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, 1371 ð_proto_admin, ð_proto_oper); 1372 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap); 1373 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1374 eth_proto_cap_masked, 1375 mlxsw_sp_port->link.autoneg); 1376 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1377 } 1378 1379 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed) 1380 { 1381 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops; 1382 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1383 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1384 u32 eth_proto_oper; 1385 int err; 1386 1387 port_type_speed_ops = mlxsw_sp->port_type_speed_ops; 1388 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, 1389 mlxsw_sp_port->local_port, 0, 1390 false); 1391 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1392 if (err) 1393 return err; 1394 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL, 1395 ð_proto_oper); 1396 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper); 1397 return 0; 1398 } 1399 1400 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 1401 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 1402 bool dwrr, u8 dwrr_weight) 1403 { 1404 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1405 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1406 1407 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1408 next_index); 1409 mlxsw_reg_qeec_de_set(qeec_pl, true); 1410 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 1411 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 1412 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1413 } 1414 1415 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 1416 enum mlxsw_reg_qeec_hr hr, u8 index, 1417 u8 next_index, u32 maxrate, u8 burst_size) 1418 { 1419 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1420 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1421 1422 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1423 next_index); 1424 mlxsw_reg_qeec_mase_set(qeec_pl, true); 1425 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 1426 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size); 1427 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1428 } 1429 1430 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 1431 enum mlxsw_reg_qeec_hr hr, u8 index, 1432 u8 next_index, u32 minrate) 1433 { 1434 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1435 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1436 1437 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1438 next_index); 1439 mlxsw_reg_qeec_mise_set(qeec_pl, true); 1440 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 1441 1442 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1443 } 1444 1445 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 1446 u8 switch_prio, u8 tclass) 1447 { 1448 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1449 char qtct_pl[MLXSW_REG_QTCT_LEN]; 1450 1451 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 1452 tclass); 1453 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 1454 } 1455 1456 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 1457 { 1458 int err, i; 1459 1460 /* Setup the elements hierarcy, so that each TC is linked to 1461 * one subgroup, which are all member in the same group. 1462 */ 1463 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1464 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0); 1465 if (err) 1466 return err; 1467 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1468 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1469 MLXSW_REG_QEEC_HR_SUBGROUP, i, 1470 0, false, 0); 1471 if (err) 1472 return err; 1473 } 1474 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1475 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1476 MLXSW_REG_QEEC_HR_TC, i, i, 1477 false, 0); 1478 if (err) 1479 return err; 1480 1481 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1482 MLXSW_REG_QEEC_HR_TC, 1483 i + 8, i, 1484 true, 100); 1485 if (err) 1486 return err; 1487 } 1488 1489 /* Make sure the max shaper is disabled in all hierarchies that support 1490 * it. Note that this disables ptps (PTP shaper), but that is intended 1491 * for the initial configuration. 1492 */ 1493 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1494 MLXSW_REG_QEEC_HR_PORT, 0, 0, 1495 MLXSW_REG_QEEC_MAS_DIS, 0); 1496 if (err) 1497 return err; 1498 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1499 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1500 MLXSW_REG_QEEC_HR_SUBGROUP, 1501 i, 0, 1502 MLXSW_REG_QEEC_MAS_DIS, 0); 1503 if (err) 1504 return err; 1505 } 1506 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1507 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1508 MLXSW_REG_QEEC_HR_TC, 1509 i, i, 1510 MLXSW_REG_QEEC_MAS_DIS, 0); 1511 if (err) 1512 return err; 1513 1514 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1515 MLXSW_REG_QEEC_HR_TC, 1516 i + 8, i, 1517 MLXSW_REG_QEEC_MAS_DIS, 0); 1518 if (err) 1519 return err; 1520 } 1521 1522 /* Configure the min shaper for multicast TCs. */ 1523 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1524 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 1525 MLXSW_REG_QEEC_HR_TC, 1526 i + 8, i, 1527 MLXSW_REG_QEEC_MIS_MIN); 1528 if (err) 1529 return err; 1530 } 1531 1532 /* Map all priorities to traffic class 0. */ 1533 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1534 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 1535 if (err) 1536 return err; 1537 } 1538 1539 return 0; 1540 } 1541 1542 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 1543 bool enable) 1544 { 1545 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1546 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 1547 1548 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 1549 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 1550 } 1551 1552 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port) 1553 { 1554 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1555 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1556 u8 module = mlxsw_sp_port->mapping.module; 1557 u64 overheat_counter; 1558 int err; 1559 1560 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index, 1561 module, &overheat_counter); 1562 if (err) 1563 return err; 1564 1565 mlxsw_sp_port->module_overheat_initial_val = overheat_counter; 1566 return 0; 1567 } 1568 1569 int 1570 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port, 1571 bool is_8021ad_tagged, 1572 bool is_8021q_tagged) 1573 { 1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1575 char spvc_pl[MLXSW_REG_SPVC_LEN]; 1576 1577 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port, 1578 is_8021ad_tagged, is_8021q_tagged); 1579 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl); 1580 } 1581 1582 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp, 1583 u16 local_port, u8 *port_number, 1584 u8 *split_port_subnumber, 1585 u8 *slot_index) 1586 { 1587 char pllp_pl[MLXSW_REG_PLLP_LEN]; 1588 int err; 1589 1590 mlxsw_reg_pllp_pack(pllp_pl, local_port); 1591 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); 1592 if (err) 1593 return err; 1594 mlxsw_reg_pllp_unpack(pllp_pl, port_number, 1595 split_port_subnumber, slot_index); 1596 return 0; 1597 } 1598 1599 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port, 1600 bool split, 1601 struct mlxsw_sp_port_mapping *port_mapping) 1602 { 1603 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1604 struct mlxsw_sp_port *mlxsw_sp_port; 1605 u32 lanes = port_mapping->width; 1606 u8 split_port_subnumber; 1607 struct net_device *dev; 1608 u8 port_number; 1609 u8 slot_index; 1610 bool splittable; 1611 int err; 1612 1613 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping); 1614 if (err) { 1615 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 1616 local_port); 1617 return err; 1618 } 1619 1620 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0); 1621 if (err) { 1622 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 1623 local_port); 1624 goto err_port_swid_set; 1625 } 1626 1627 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number, 1628 &split_port_subnumber, &slot_index); 1629 if (err) { 1630 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n", 1631 local_port); 1632 goto err_port_label_info_get; 1633 } 1634 1635 splittable = lanes > 1 && !split; 1636 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index, 1637 port_number, split, split_port_subnumber, 1638 splittable, lanes, mlxsw_sp->base_mac, 1639 sizeof(mlxsw_sp->base_mac)); 1640 if (err) { 1641 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 1642 local_port); 1643 goto err_core_port_init; 1644 } 1645 1646 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 1647 if (!dev) { 1648 err = -ENOMEM; 1649 goto err_alloc_etherdev; 1650 } 1651 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 1652 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp)); 1653 mlxsw_sp_port = netdev_priv(dev); 1654 mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port, 1655 mlxsw_sp_port, dev); 1656 mlxsw_sp_port->dev = dev; 1657 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1658 mlxsw_sp_port->local_port = local_port; 1659 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; 1660 mlxsw_sp_port->split = split; 1661 mlxsw_sp_port->mapping = *port_mapping; 1662 mlxsw_sp_port->link.autoneg = 1; 1663 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 1664 1665 mlxsw_sp_port->pcpu_stats = 1666 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 1667 if (!mlxsw_sp_port->pcpu_stats) { 1668 err = -ENOMEM; 1669 goto err_alloc_stats; 1670 } 1671 1672 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1673 &update_stats_cache); 1674 1675 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 1676 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 1677 1678 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 1679 if (err) { 1680 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 1681 mlxsw_sp_port->local_port); 1682 goto err_dev_addr_init; 1683 } 1684 1685 netif_carrier_off(dev); 1686 1687 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 1688 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 1689 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK; 1690 1691 dev->min_mtu = 0; 1692 dev->max_mtu = ETH_MAX_MTU; 1693 1694 /* Each packet needs to have a Tx header (metadata) on top all other 1695 * headers. 1696 */ 1697 dev->needed_headroom = MLXSW_TXHDR_LEN; 1698 1699 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 1700 if (err) { 1701 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 1702 mlxsw_sp_port->local_port); 1703 goto err_port_system_port_mapping_set; 1704 } 1705 1706 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port); 1707 if (err) { 1708 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 1709 mlxsw_sp_port->local_port); 1710 goto err_port_speed_by_width_set; 1711 } 1712 1713 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port, 1714 &mlxsw_sp_port->max_speed); 1715 if (err) { 1716 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n", 1717 mlxsw_sp_port->local_port); 1718 goto err_max_speed_get; 1719 } 1720 1721 err = mlxsw_sp_port_max_mtu_get(mlxsw_sp_port, &mlxsw_sp_port->max_mtu); 1722 if (err) { 1723 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n", 1724 mlxsw_sp_port->local_port); 1725 goto err_port_max_mtu_get; 1726 } 1727 1728 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 1729 if (err) { 1730 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 1731 mlxsw_sp_port->local_port); 1732 goto err_port_mtu_set; 1733 } 1734 1735 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1736 if (err) 1737 goto err_port_admin_status_set; 1738 1739 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 1740 if (err) { 1741 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 1742 mlxsw_sp_port->local_port); 1743 goto err_port_buffers_init; 1744 } 1745 1746 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 1747 if (err) { 1748 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 1749 mlxsw_sp_port->local_port); 1750 goto err_port_ets_init; 1751 } 1752 1753 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 1754 if (err) { 1755 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 1756 mlxsw_sp_port->local_port); 1757 goto err_port_tc_mc_mode; 1758 } 1759 1760 /* ETS and buffers must be initialized before DCB. */ 1761 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 1762 if (err) { 1763 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 1764 mlxsw_sp_port->local_port); 1765 goto err_port_dcb_init; 1766 } 1767 1768 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 1769 if (err) { 1770 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 1771 mlxsw_sp_port->local_port); 1772 goto err_port_fids_init; 1773 } 1774 1775 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 1776 if (err) { 1777 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 1778 mlxsw_sp_port->local_port); 1779 goto err_port_qdiscs_init; 1780 } 1781 1782 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false, 1783 false); 1784 if (err) { 1785 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n", 1786 mlxsw_sp_port->local_port); 1787 goto err_port_vlan_clear; 1788 } 1789 1790 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 1791 if (err) { 1792 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 1793 mlxsw_sp_port->local_port); 1794 goto err_port_nve_init; 1795 } 1796 1797 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 1798 ETH_P_8021Q); 1799 if (err) { 1800 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n", 1801 mlxsw_sp_port->local_port); 1802 goto err_port_pvid_set; 1803 } 1804 1805 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, 1806 MLXSW_SP_DEFAULT_VID); 1807 if (IS_ERR(mlxsw_sp_port_vlan)) { 1808 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 1809 mlxsw_sp_port->local_port); 1810 err = PTR_ERR(mlxsw_sp_port_vlan); 1811 goto err_port_vlan_create; 1812 } 1813 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan; 1814 1815 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat 1816 * only packets with 802.1q header as tagged packets. 1817 */ 1818 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true); 1819 if (err) { 1820 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n", 1821 local_port); 1822 goto err_port_vlan_classification_set; 1823 } 1824 1825 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw, 1826 mlxsw_sp->ptp_ops->shaper_work); 1827 1828 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 1829 1830 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port); 1831 if (err) { 1832 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n", 1833 mlxsw_sp_port->local_port); 1834 goto err_port_overheat_init_val_set; 1835 } 1836 1837 err = register_netdev(dev); 1838 if (err) { 1839 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 1840 mlxsw_sp_port->local_port); 1841 goto err_register_netdev; 1842 } 1843 1844 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 1845 return 0; 1846 1847 err_register_netdev: 1848 err_port_overheat_init_val_set: 1849 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1850 err_port_vlan_classification_set: 1851 mlxsw_sp->ports[local_port] = NULL; 1852 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1853 err_port_vlan_create: 1854 err_port_pvid_set: 1855 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1856 err_port_nve_init: 1857 err_port_vlan_clear: 1858 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1859 err_port_qdiscs_init: 1860 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1861 err_port_fids_init: 1862 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1863 err_port_dcb_init: 1864 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1865 err_port_tc_mc_mode: 1866 err_port_ets_init: 1867 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1868 err_port_buffers_init: 1869 err_port_admin_status_set: 1870 err_port_mtu_set: 1871 err_port_max_mtu_get: 1872 err_max_speed_get: 1873 err_port_speed_by_width_set: 1874 err_port_system_port_mapping_set: 1875 err_dev_addr_init: 1876 free_percpu(mlxsw_sp_port->pcpu_stats); 1877 err_alloc_stats: 1878 free_netdev(dev); 1879 err_alloc_etherdev: 1880 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1881 err_core_port_init: 1882 err_port_label_info_get: 1883 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1884 MLXSW_PORT_SWID_DISABLED_PORT); 1885 err_port_swid_set: 1886 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, 1887 port_mapping->slot_index, 1888 port_mapping->module); 1889 return err; 1890 } 1891 1892 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1893 { 1894 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 1895 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1896 u8 module = mlxsw_sp_port->mapping.module; 1897 1898 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 1899 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw); 1900 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 1901 mlxsw_sp_port_ptp_clear(mlxsw_sp_port); 1902 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1903 mlxsw_sp->ports[local_port] = NULL; 1904 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); 1905 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1906 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1907 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1908 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1909 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1910 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1911 free_percpu(mlxsw_sp_port->pcpu_stats); 1912 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 1913 free_netdev(mlxsw_sp_port->dev); 1914 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1915 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1916 MLXSW_PORT_SWID_DISABLED_PORT); 1917 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module); 1918 } 1919 1920 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp) 1921 { 1922 struct mlxsw_sp_port *mlxsw_sp_port; 1923 int err; 1924 1925 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL); 1926 if (!mlxsw_sp_port) 1927 return -ENOMEM; 1928 1929 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1930 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT; 1931 1932 err = mlxsw_core_cpu_port_init(mlxsw_sp->core, 1933 mlxsw_sp_port, 1934 mlxsw_sp->base_mac, 1935 sizeof(mlxsw_sp->base_mac)); 1936 if (err) { 1937 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n"); 1938 goto err_core_cpu_port_init; 1939 } 1940 1941 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port; 1942 return 0; 1943 1944 err_core_cpu_port_init: 1945 kfree(mlxsw_sp_port); 1946 return err; 1947 } 1948 1949 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp) 1950 { 1951 struct mlxsw_sp_port *mlxsw_sp_port = 1952 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT]; 1953 1954 mlxsw_core_cpu_port_fini(mlxsw_sp->core); 1955 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL; 1956 kfree(mlxsw_sp_port); 1957 } 1958 1959 static bool mlxsw_sp_local_port_valid(u16 local_port) 1960 { 1961 return local_port != MLXSW_PORT_CPU_PORT; 1962 } 1963 1964 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1965 { 1966 if (!mlxsw_sp_local_port_valid(local_port)) 1967 return false; 1968 return mlxsw_sp->ports[local_port] != NULL; 1969 } 1970 1971 static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp, 1972 u16 local_port, bool enable) 1973 { 1974 char pmecr_pl[MLXSW_REG_PMECR_LEN]; 1975 1976 mlxsw_reg_pmecr_pack(pmecr_pl, local_port, 1977 enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT : 1978 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT); 1979 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl); 1980 } 1981 1982 struct mlxsw_sp_port_mapping_event { 1983 struct list_head list; 1984 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 1985 }; 1986 1987 static void mlxsw_sp_port_mapping_events_work(struct work_struct *work) 1988 { 1989 struct mlxsw_sp_port_mapping_event *event, *next_event; 1990 struct mlxsw_sp_port_mapping_events *events; 1991 struct mlxsw_sp_port_mapping port_mapping; 1992 struct mlxsw_sp *mlxsw_sp; 1993 struct devlink *devlink; 1994 LIST_HEAD(event_queue); 1995 u16 local_port; 1996 int err; 1997 1998 events = container_of(work, struct mlxsw_sp_port_mapping_events, work); 1999 mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events); 2000 devlink = priv_to_devlink(mlxsw_sp->core); 2001 2002 spin_lock_bh(&events->queue_lock); 2003 list_splice_init(&events->queue, &event_queue); 2004 spin_unlock_bh(&events->queue_lock); 2005 2006 list_for_each_entry_safe(event, next_event, &event_queue, list) { 2007 local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl); 2008 err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 2009 event->pmlp_pl, &port_mapping); 2010 if (err) 2011 goto out; 2012 2013 if (WARN_ON_ONCE(!port_mapping.width)) 2014 goto out; 2015 2016 devl_lock(devlink); 2017 2018 if (!mlxsw_sp_port_created(mlxsw_sp, local_port)) 2019 mlxsw_sp_port_create(mlxsw_sp, local_port, 2020 false, &port_mapping); 2021 else 2022 WARN_ON_ONCE(1); 2023 2024 devl_unlock(devlink); 2025 2026 mlxsw_sp->port_mapping[local_port] = port_mapping; 2027 2028 out: 2029 kfree(event); 2030 } 2031 } 2032 2033 static void 2034 mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg, 2035 char *pmlp_pl, void *priv) 2036 { 2037 struct mlxsw_sp_port_mapping_events *events; 2038 struct mlxsw_sp_port_mapping_event *event; 2039 struct mlxsw_sp *mlxsw_sp = priv; 2040 u16 local_port; 2041 2042 local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl); 2043 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 2044 return; 2045 2046 events = &mlxsw_sp->port_mapping_events; 2047 event = kmalloc(sizeof(*event), GFP_ATOMIC); 2048 if (!event) 2049 return; 2050 memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl)); 2051 spin_lock(&events->queue_lock); 2052 list_add_tail(&event->list, &events->queue); 2053 spin_unlock(&events->queue_lock); 2054 mlxsw_core_schedule_work(&events->work); 2055 } 2056 2057 static void 2058 __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp) 2059 { 2060 struct mlxsw_sp_port_mapping_event *event, *next_event; 2061 struct mlxsw_sp_port_mapping_events *events; 2062 2063 events = &mlxsw_sp->port_mapping_events; 2064 2065 /* Caller needs to make sure that no new event is going to appear. */ 2066 cancel_work_sync(&events->work); 2067 list_for_each_entry_safe(event, next_event, &events->queue, list) { 2068 list_del(&event->list); 2069 kfree(event); 2070 } 2071 } 2072 2073 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 2074 { 2075 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2076 int i; 2077 2078 for (i = 1; i < max_ports; i++) 2079 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 2080 /* Make sure all scheduled events are processed */ 2081 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 2082 2083 for (i = 1; i < max_ports; i++) 2084 if (mlxsw_sp_port_created(mlxsw_sp, i)) 2085 mlxsw_sp_port_remove(mlxsw_sp, i); 2086 mlxsw_sp_cpu_port_remove(mlxsw_sp); 2087 kfree(mlxsw_sp->ports); 2088 mlxsw_sp->ports = NULL; 2089 } 2090 2091 static void 2092 mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core, 2093 bool (*selector)(void *priv, u16 local_port), 2094 void *priv) 2095 { 2096 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2097 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core); 2098 int i; 2099 2100 for (i = 1; i < max_ports; i++) 2101 if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i)) 2102 mlxsw_sp_port_remove(mlxsw_sp, i); 2103 } 2104 2105 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 2106 { 2107 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2108 struct mlxsw_sp_port_mapping_events *events; 2109 struct mlxsw_sp_port_mapping *port_mapping; 2110 size_t alloc_size; 2111 int i; 2112 int err; 2113 2114 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 2115 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 2116 if (!mlxsw_sp->ports) 2117 return -ENOMEM; 2118 2119 events = &mlxsw_sp->port_mapping_events; 2120 INIT_LIST_HEAD(&events->queue); 2121 spin_lock_init(&events->queue_lock); 2122 INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work); 2123 2124 for (i = 1; i < max_ports; i++) { 2125 err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true); 2126 if (err) 2127 goto err_event_enable; 2128 } 2129 2130 err = mlxsw_sp_cpu_port_create(mlxsw_sp); 2131 if (err) 2132 goto err_cpu_port_create; 2133 2134 for (i = 1; i < max_ports; i++) { 2135 port_mapping = &mlxsw_sp->port_mapping[i]; 2136 if (!port_mapping->width) 2137 continue; 2138 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping); 2139 if (err) 2140 goto err_port_create; 2141 } 2142 return 0; 2143 2144 err_port_create: 2145 for (i--; i >= 1; i--) 2146 if (mlxsw_sp_port_created(mlxsw_sp, i)) 2147 mlxsw_sp_port_remove(mlxsw_sp, i); 2148 i = max_ports; 2149 mlxsw_sp_cpu_port_remove(mlxsw_sp); 2150 err_cpu_port_create: 2151 err_event_enable: 2152 for (i--; i >= 1; i--) 2153 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 2154 /* Make sure all scheduled events are processed */ 2155 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 2156 kfree(mlxsw_sp->ports); 2157 mlxsw_sp->ports = NULL; 2158 return err; 2159 } 2160 2161 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp) 2162 { 2163 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2164 struct mlxsw_sp_port_mapping *port_mapping; 2165 int i; 2166 int err; 2167 2168 mlxsw_sp->port_mapping = kcalloc(max_ports, 2169 sizeof(struct mlxsw_sp_port_mapping), 2170 GFP_KERNEL); 2171 if (!mlxsw_sp->port_mapping) 2172 return -ENOMEM; 2173 2174 for (i = 1; i < max_ports; i++) { 2175 port_mapping = &mlxsw_sp->port_mapping[i]; 2176 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping); 2177 if (err) 2178 goto err_port_module_info_get; 2179 } 2180 return 0; 2181 2182 err_port_module_info_get: 2183 kfree(mlxsw_sp->port_mapping); 2184 return err; 2185 } 2186 2187 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp) 2188 { 2189 kfree(mlxsw_sp->port_mapping); 2190 } 2191 2192 static int 2193 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, 2194 struct mlxsw_sp_port_mapping *port_mapping, 2195 unsigned int count, const char *pmtdb_pl) 2196 { 2197 struct mlxsw_sp_port_mapping split_port_mapping; 2198 int err, i; 2199 2200 split_port_mapping = *port_mapping; 2201 split_port_mapping.width /= count; 2202 for (i = 0; i < count; i++) { 2203 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2204 2205 if (!mlxsw_sp_local_port_valid(s_local_port)) 2206 continue; 2207 2208 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port, 2209 true, &split_port_mapping); 2210 if (err) 2211 goto err_port_create; 2212 split_port_mapping.lane += split_port_mapping.width; 2213 } 2214 2215 return 0; 2216 2217 err_port_create: 2218 for (i--; i >= 0; i--) { 2219 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2220 2221 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2222 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2223 } 2224 return err; 2225 } 2226 2227 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 2228 unsigned int count, 2229 const char *pmtdb_pl) 2230 { 2231 struct mlxsw_sp_port_mapping *port_mapping; 2232 int i; 2233 2234 /* Go over original unsplit ports in the gap and recreate them. */ 2235 for (i = 0; i < count; i++) { 2236 u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2237 2238 port_mapping = &mlxsw_sp->port_mapping[local_port]; 2239 if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port)) 2240 continue; 2241 mlxsw_sp_port_create(mlxsw_sp, local_port, 2242 false, port_mapping); 2243 } 2244 } 2245 2246 static struct mlxsw_sp_port * 2247 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port) 2248 { 2249 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port]) 2250 return mlxsw_sp->ports[local_port]; 2251 return NULL; 2252 } 2253 2254 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port, 2255 unsigned int count, 2256 struct netlink_ext_ack *extack) 2257 { 2258 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2259 struct mlxsw_sp_port_mapping port_mapping; 2260 struct mlxsw_sp_port *mlxsw_sp_port; 2261 enum mlxsw_reg_pmtdb_status status; 2262 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2263 int i; 2264 int err; 2265 2266 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2267 if (!mlxsw_sp_port) { 2268 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2269 local_port); 2270 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2271 return -EINVAL; 2272 } 2273 2274 if (mlxsw_sp_port->split) { 2275 NL_SET_ERR_MSG_MOD(extack, "Port is already split"); 2276 return -EINVAL; 2277 } 2278 2279 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2280 mlxsw_sp_port->mapping.module, 2281 mlxsw_sp_port->mapping.module_width / count, 2282 count); 2283 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2284 if (err) { 2285 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2286 return err; 2287 } 2288 2289 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl); 2290 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) { 2291 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration"); 2292 return -EINVAL; 2293 } 2294 2295 port_mapping = mlxsw_sp_port->mapping; 2296 2297 for (i = 0; i < count; i++) { 2298 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2299 2300 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2301 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2302 } 2303 2304 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping, 2305 count, pmtdb_pl); 2306 if (err) { 2307 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 2308 goto err_port_split_create; 2309 } 2310 2311 return 0; 2312 2313 err_port_split_create: 2314 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2315 2316 return err; 2317 } 2318 2319 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port, 2320 struct netlink_ext_ack *extack) 2321 { 2322 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2323 struct mlxsw_sp_port *mlxsw_sp_port; 2324 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2325 unsigned int count; 2326 int i; 2327 int err; 2328 2329 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2330 if (!mlxsw_sp_port) { 2331 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2332 local_port); 2333 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2334 return -EINVAL; 2335 } 2336 2337 if (!mlxsw_sp_port->split) { 2338 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 2339 return -EINVAL; 2340 } 2341 2342 count = mlxsw_sp_port->mapping.module_width / 2343 mlxsw_sp_port->mapping.width; 2344 2345 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2346 mlxsw_sp_port->mapping.module, 2347 mlxsw_sp_port->mapping.module_width / count, 2348 count); 2349 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2350 if (err) { 2351 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2352 return err; 2353 } 2354 2355 for (i = 0; i < count; i++) { 2356 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2357 2358 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2359 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2360 } 2361 2362 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2363 2364 return 0; 2365 } 2366 2367 static void 2368 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port) 2369 { 2370 int i; 2371 2372 for (i = 0; i < TC_MAX_QUEUE; i++) 2373 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0; 2374 } 2375 2376 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 2377 char *pude_pl, void *priv) 2378 { 2379 struct mlxsw_sp *mlxsw_sp = priv; 2380 struct mlxsw_sp_port *mlxsw_sp_port; 2381 enum mlxsw_reg_pude_oper_status status; 2382 u16 local_port; 2383 2384 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 2385 2386 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 2387 return; 2388 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2389 if (!mlxsw_sp_port) 2390 return; 2391 2392 status = mlxsw_reg_pude_oper_status_get(pude_pl); 2393 if (status == MLXSW_PORT_OPER_STATUS_UP) { 2394 netdev_info(mlxsw_sp_port->dev, "link up\n"); 2395 netif_carrier_on(mlxsw_sp_port->dev); 2396 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0); 2397 } else { 2398 netdev_info(mlxsw_sp_port->dev, "link down\n"); 2399 netif_carrier_off(mlxsw_sp_port->dev); 2400 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port); 2401 } 2402 } 2403 2404 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp, 2405 char *mtpptr_pl, bool ingress) 2406 { 2407 u16 local_port; 2408 u8 num_rec; 2409 int i; 2410 2411 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl); 2412 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl); 2413 for (i = 0; i < num_rec; i++) { 2414 u8 domain_number; 2415 u8 message_type; 2416 u16 sequence_id; 2417 u64 timestamp; 2418 2419 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type, 2420 &domain_number, &sequence_id, 2421 ×tamp); 2422 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port, 2423 message_type, domain_number, 2424 sequence_id, timestamp); 2425 } 2426 } 2427 2428 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg, 2429 char *mtpptr_pl, void *priv) 2430 { 2431 struct mlxsw_sp *mlxsw_sp = priv; 2432 2433 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true); 2434 } 2435 2436 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg, 2437 char *mtpptr_pl, void *priv) 2438 { 2439 struct mlxsw_sp *mlxsw_sp = priv; 2440 2441 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false); 2442 } 2443 2444 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 2445 u16 local_port, void *priv) 2446 { 2447 struct mlxsw_sp *mlxsw_sp = priv; 2448 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2449 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 2450 2451 if (unlikely(!mlxsw_sp_port)) { 2452 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 2453 local_port); 2454 return; 2455 } 2456 2457 skb->dev = mlxsw_sp_port->dev; 2458 2459 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 2460 u64_stats_update_begin(&pcpu_stats->syncp); 2461 pcpu_stats->rx_packets++; 2462 pcpu_stats->rx_bytes += skb->len; 2463 u64_stats_update_end(&pcpu_stats->syncp); 2464 2465 skb->protocol = eth_type_trans(skb, skb->dev); 2466 netif_receive_skb(skb); 2467 } 2468 2469 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port, 2470 void *priv) 2471 { 2472 skb->offload_fwd_mark = 1; 2473 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2474 } 2475 2476 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb, 2477 u16 local_port, void *priv) 2478 { 2479 skb->offload_l3_fwd_mark = 1; 2480 skb->offload_fwd_mark = 1; 2481 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2482 } 2483 2484 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 2485 u16 local_port) 2486 { 2487 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port); 2488 } 2489 2490 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2491 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 2492 _is_ctrl, SP_##_trap_group, DISCARD) 2493 2494 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2495 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 2496 _is_ctrl, SP_##_trap_group, DISCARD) 2497 2498 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2499 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \ 2500 _is_ctrl, SP_##_trap_group, DISCARD) 2501 2502 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 2503 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 2504 2505 static const struct mlxsw_listener mlxsw_sp_listener[] = { 2506 /* Events */ 2507 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 2508 /* L2 traps */ 2509 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false), 2510 /* L3 traps */ 2511 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 2512 false), 2513 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 2514 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 2515 false), 2516 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD, 2517 ROUTER_EXP, false), 2518 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD, 2519 ROUTER_EXP, false), 2520 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD, 2521 ROUTER_EXP, false), 2522 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD, 2523 ROUTER_EXP, false), 2524 /* Multicast Router Traps */ 2525 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 2526 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 2527 /* NVE traps */ 2528 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false), 2529 }; 2530 2531 static const struct mlxsw_listener mlxsw_sp1_listener[] = { 2532 /* Events */ 2533 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0), 2534 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0), 2535 }; 2536 2537 static const struct mlxsw_listener mlxsw_sp2_listener[] = { 2538 /* Events */ 2539 MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE), 2540 }; 2541 2542 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 2543 { 2544 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2545 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 2546 enum mlxsw_reg_qpcr_ir_units ir_units; 2547 int max_cpu_policers; 2548 bool is_bytes; 2549 u8 burst_size; 2550 u32 rate; 2551 int i, err; 2552 2553 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 2554 return -EIO; 2555 2556 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2557 2558 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 2559 for (i = 0; i < max_cpu_policers; i++) { 2560 is_bytes = false; 2561 switch (i) { 2562 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2563 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2564 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2565 rate = 1024; 2566 burst_size = 7; 2567 break; 2568 default: 2569 continue; 2570 } 2571 2572 __set_bit(i, mlxsw_sp->trap->policers_usage); 2573 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 2574 burst_size); 2575 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 2576 if (err) 2577 return err; 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 2584 { 2585 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2586 enum mlxsw_reg_htgt_trap_group i; 2587 int max_cpu_policers; 2588 int max_trap_groups; 2589 u8 priority, tc; 2590 u16 policer_id; 2591 int err; 2592 2593 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 2594 return -EIO; 2595 2596 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 2597 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2598 2599 for (i = 0; i < max_trap_groups; i++) { 2600 policer_id = i; 2601 switch (i) { 2602 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2603 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2604 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2605 priority = 1; 2606 tc = 1; 2607 break; 2608 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 2609 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 2610 tc = MLXSW_REG_HTGT_DEFAULT_TC; 2611 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 2612 break; 2613 default: 2614 continue; 2615 } 2616 2617 if (max_cpu_policers <= policer_id && 2618 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 2619 return -EIO; 2620 2621 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 2622 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2623 if (err) 2624 return err; 2625 } 2626 2627 return 0; 2628 } 2629 2630 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 2631 { 2632 struct mlxsw_sp_trap *trap; 2633 u64 max_policers; 2634 int err; 2635 2636 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS)) 2637 return -EIO; 2638 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS); 2639 trap = kzalloc(struct_size(trap, policers_usage, 2640 BITS_TO_LONGS(max_policers)), GFP_KERNEL); 2641 if (!trap) 2642 return -ENOMEM; 2643 trap->max_policers = max_policers; 2644 mlxsw_sp->trap = trap; 2645 2646 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 2647 if (err) 2648 goto err_cpu_policers_set; 2649 2650 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 2651 if (err) 2652 goto err_trap_groups_set; 2653 2654 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener, 2655 ARRAY_SIZE(mlxsw_sp_listener), 2656 mlxsw_sp); 2657 if (err) 2658 goto err_traps_register; 2659 2660 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners, 2661 mlxsw_sp->listeners_count, mlxsw_sp); 2662 if (err) 2663 goto err_extra_traps_init; 2664 2665 return 0; 2666 2667 err_extra_traps_init: 2668 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2669 ARRAY_SIZE(mlxsw_sp_listener), 2670 mlxsw_sp); 2671 err_traps_register: 2672 err_trap_groups_set: 2673 err_cpu_policers_set: 2674 kfree(trap); 2675 return err; 2676 } 2677 2678 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 2679 { 2680 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners, 2681 mlxsw_sp->listeners_count, 2682 mlxsw_sp); 2683 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2684 ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp); 2685 kfree(mlxsw_sp->trap); 2686 } 2687 2688 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe 2689 2690 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 2691 { 2692 char slcr_pl[MLXSW_REG_SLCR_LEN]; 2693 u16 max_lag; 2694 u32 seed; 2695 int err; 2696 2697 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac), 2698 MLXSW_SP_LAG_SEED_INIT); 2699 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 2700 MLXSW_REG_SLCR_LAG_HASH_DMAC | 2701 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 2702 MLXSW_REG_SLCR_LAG_HASH_VLANID | 2703 MLXSW_REG_SLCR_LAG_HASH_SIP | 2704 MLXSW_REG_SLCR_LAG_HASH_DIP | 2705 MLXSW_REG_SLCR_LAG_HASH_SPORT | 2706 MLXSW_REG_SLCR_LAG_HASH_DPORT | 2707 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 2708 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 2709 if (err) 2710 return err; 2711 2712 err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); 2713 if (err) 2714 return err; 2715 2716 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 2717 return -EIO; 2718 2719 mlxsw_sp->lags = kcalloc(max_lag, sizeof(struct mlxsw_sp_upper), 2720 GFP_KERNEL); 2721 if (!mlxsw_sp->lags) 2722 return -ENOMEM; 2723 2724 return 0; 2725 } 2726 2727 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 2728 { 2729 kfree(mlxsw_sp->lags); 2730 } 2731 2732 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = { 2733 .clock_init = mlxsw_sp1_ptp_clock_init, 2734 .clock_fini = mlxsw_sp1_ptp_clock_fini, 2735 .init = mlxsw_sp1_ptp_init, 2736 .fini = mlxsw_sp1_ptp_fini, 2737 .receive = mlxsw_sp1_ptp_receive, 2738 .transmitted = mlxsw_sp1_ptp_transmitted, 2739 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get, 2740 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set, 2741 .shaper_work = mlxsw_sp1_ptp_shaper_work, 2742 .get_ts_info = mlxsw_sp1_ptp_get_ts_info, 2743 .get_stats_count = mlxsw_sp1_get_stats_count, 2744 .get_stats_strings = mlxsw_sp1_get_stats_strings, 2745 .get_stats = mlxsw_sp1_get_stats, 2746 .txhdr_construct = mlxsw_sp_ptp_txhdr_construct, 2747 }; 2748 2749 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = { 2750 .clock_init = mlxsw_sp2_ptp_clock_init, 2751 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2752 .init = mlxsw_sp2_ptp_init, 2753 .fini = mlxsw_sp2_ptp_fini, 2754 .receive = mlxsw_sp2_ptp_receive, 2755 .transmitted = mlxsw_sp2_ptp_transmitted, 2756 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2757 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2758 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2759 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2760 .get_stats_count = mlxsw_sp2_get_stats_count, 2761 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2762 .get_stats = mlxsw_sp2_get_stats, 2763 .txhdr_construct = mlxsw_sp2_ptp_txhdr_construct, 2764 }; 2765 2766 static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = { 2767 .clock_init = mlxsw_sp2_ptp_clock_init, 2768 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2769 .init = mlxsw_sp2_ptp_init, 2770 .fini = mlxsw_sp2_ptp_fini, 2771 .receive = mlxsw_sp2_ptp_receive, 2772 .transmitted = mlxsw_sp2_ptp_transmitted, 2773 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2774 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2775 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2776 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2777 .get_stats_count = mlxsw_sp2_get_stats_count, 2778 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2779 .get_stats = mlxsw_sp2_get_stats, 2780 .txhdr_construct = mlxsw_sp_ptp_txhdr_construct, 2781 }; 2782 2783 struct mlxsw_sp_sample_trigger_node { 2784 struct mlxsw_sp_sample_trigger trigger; 2785 struct mlxsw_sp_sample_params params; 2786 struct rhash_head ht_node; 2787 struct rcu_head rcu; 2788 refcount_t refcount; 2789 }; 2790 2791 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = { 2792 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger), 2793 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node), 2794 .key_len = sizeof(struct mlxsw_sp_sample_trigger), 2795 .automatic_shrinking = true, 2796 }; 2797 2798 static void 2799 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key, 2800 const struct mlxsw_sp_sample_trigger *trigger) 2801 { 2802 memset(key, 0, sizeof(*key)); 2803 key->type = trigger->type; 2804 key->local_port = trigger->local_port; 2805 } 2806 2807 /* RCU read lock must be held */ 2808 struct mlxsw_sp_sample_params * 2809 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp, 2810 const struct mlxsw_sp_sample_trigger *trigger) 2811 { 2812 struct mlxsw_sp_sample_trigger_node *trigger_node; 2813 struct mlxsw_sp_sample_trigger key; 2814 2815 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2816 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key, 2817 mlxsw_sp_sample_trigger_ht_params); 2818 if (!trigger_node) 2819 return NULL; 2820 2821 return &trigger_node->params; 2822 } 2823 2824 static int 2825 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp, 2826 const struct mlxsw_sp_sample_trigger *trigger, 2827 const struct mlxsw_sp_sample_params *params) 2828 { 2829 struct mlxsw_sp_sample_trigger_node *trigger_node; 2830 int err; 2831 2832 trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL); 2833 if (!trigger_node) 2834 return -ENOMEM; 2835 2836 trigger_node->trigger = *trigger; 2837 trigger_node->params = *params; 2838 refcount_set(&trigger_node->refcount, 1); 2839 2840 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht, 2841 &trigger_node->ht_node, 2842 mlxsw_sp_sample_trigger_ht_params); 2843 if (err) 2844 goto err_rhashtable_insert; 2845 2846 return 0; 2847 2848 err_rhashtable_insert: 2849 kfree(trigger_node); 2850 return err; 2851 } 2852 2853 static void 2854 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp, 2855 struct mlxsw_sp_sample_trigger_node *trigger_node) 2856 { 2857 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht, 2858 &trigger_node->ht_node, 2859 mlxsw_sp_sample_trigger_ht_params); 2860 kfree_rcu(trigger_node, rcu); 2861 } 2862 2863 int 2864 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp, 2865 const struct mlxsw_sp_sample_trigger *trigger, 2866 const struct mlxsw_sp_sample_params *params, 2867 struct netlink_ext_ack *extack) 2868 { 2869 struct mlxsw_sp_sample_trigger_node *trigger_node; 2870 struct mlxsw_sp_sample_trigger key; 2871 2872 ASSERT_RTNL(); 2873 2874 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2875 2876 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2877 &key, 2878 mlxsw_sp_sample_trigger_ht_params); 2879 if (!trigger_node) 2880 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key, 2881 params); 2882 2883 if (trigger_node->trigger.local_port) { 2884 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port"); 2885 return -EINVAL; 2886 } 2887 2888 if (trigger_node->params.psample_group != params->psample_group || 2889 trigger_node->params.truncate != params->truncate || 2890 trigger_node->params.rate != params->rate || 2891 trigger_node->params.trunc_size != params->trunc_size) { 2892 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger"); 2893 return -EINVAL; 2894 } 2895 2896 refcount_inc(&trigger_node->refcount); 2897 2898 return 0; 2899 } 2900 2901 void 2902 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp, 2903 const struct mlxsw_sp_sample_trigger *trigger) 2904 { 2905 struct mlxsw_sp_sample_trigger_node *trigger_node; 2906 struct mlxsw_sp_sample_trigger key; 2907 2908 ASSERT_RTNL(); 2909 2910 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2911 2912 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2913 &key, 2914 mlxsw_sp_sample_trigger_ht_params); 2915 if (!trigger_node) 2916 return; 2917 2918 if (!refcount_dec_and_test(&trigger_node->refcount)) 2919 return; 2920 2921 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node); 2922 } 2923 2924 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 2925 unsigned long event, void *ptr); 2926 2927 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96 2928 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128 2929 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789 2930 2931 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp) 2932 { 2933 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 2934 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT; 2935 mutex_init(&mlxsw_sp->parsing.lock); 2936 } 2937 2938 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp) 2939 { 2940 mutex_destroy(&mlxsw_sp->parsing.lock); 2941 } 2942 2943 struct mlxsw_sp_ipv6_addr_node { 2944 struct in6_addr key; 2945 struct rhash_head ht_node; 2946 u32 kvdl_index; 2947 refcount_t refcount; 2948 }; 2949 2950 static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = { 2951 .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key), 2952 .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node), 2953 .key_len = sizeof(struct in6_addr), 2954 .automatic_shrinking = true, 2955 }; 2956 2957 static int 2958 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6, 2959 u32 *p_kvdl_index) 2960 { 2961 struct mlxsw_sp_ipv6_addr_node *node; 2962 char rips_pl[MLXSW_REG_RIPS_LEN]; 2963 int err; 2964 2965 err = mlxsw_sp_kvdl_alloc(mlxsw_sp, 2966 MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2967 p_kvdl_index); 2968 if (err) 2969 return err; 2970 2971 mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6); 2972 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl); 2973 if (err) 2974 goto err_rips_write; 2975 2976 node = kzalloc(sizeof(*node), GFP_KERNEL); 2977 if (!node) { 2978 err = -ENOMEM; 2979 goto err_node_alloc; 2980 } 2981 2982 node->key = *addr6; 2983 node->kvdl_index = *p_kvdl_index; 2984 refcount_set(&node->refcount, 1); 2985 2986 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht, 2987 &node->ht_node, 2988 mlxsw_sp_ipv6_addr_ht_params); 2989 if (err) 2990 goto err_rhashtable_insert; 2991 2992 return 0; 2993 2994 err_rhashtable_insert: 2995 kfree(node); 2996 err_node_alloc: 2997 err_rips_write: 2998 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2999 *p_kvdl_index); 3000 return err; 3001 } 3002 3003 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp, 3004 struct mlxsw_sp_ipv6_addr_node *node) 3005 { 3006 u32 kvdl_index = node->kvdl_index; 3007 3008 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node, 3009 mlxsw_sp_ipv6_addr_ht_params); 3010 kfree(node); 3011 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 3012 kvdl_index); 3013 } 3014 3015 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp, 3016 const struct in6_addr *addr6, 3017 u32 *p_kvdl_index) 3018 { 3019 struct mlxsw_sp_ipv6_addr_node *node; 3020 int err = 0; 3021 3022 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 3023 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 3024 mlxsw_sp_ipv6_addr_ht_params); 3025 if (node) { 3026 refcount_inc(&node->refcount); 3027 *p_kvdl_index = node->kvdl_index; 3028 goto out_unlock; 3029 } 3030 3031 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index); 3032 3033 out_unlock: 3034 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 3035 return err; 3036 } 3037 3038 void 3039 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6) 3040 { 3041 struct mlxsw_sp_ipv6_addr_node *node; 3042 3043 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 3044 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 3045 mlxsw_sp_ipv6_addr_ht_params); 3046 if (WARN_ON(!node)) 3047 goto out_unlock; 3048 3049 if (!refcount_dec_and_test(&node->refcount)) 3050 goto out_unlock; 3051 3052 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node); 3053 3054 out_unlock: 3055 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 3056 } 3057 3058 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp) 3059 { 3060 int err; 3061 3062 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht, 3063 &mlxsw_sp_ipv6_addr_ht_params); 3064 if (err) 3065 return err; 3066 3067 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock); 3068 return 0; 3069 } 3070 3071 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp) 3072 { 3073 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock); 3074 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht); 3075 } 3076 3077 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 3078 const struct mlxsw_bus_info *mlxsw_bus_info, 3079 struct netlink_ext_ack *extack) 3080 { 3081 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3082 int err; 3083 3084 mlxsw_sp->core = mlxsw_core; 3085 mlxsw_sp->bus_info = mlxsw_bus_info; 3086 3087 mlxsw_sp_parsing_init(mlxsw_sp); 3088 mlxsw_core_emad_string_tlv_enable(mlxsw_core); 3089 3090 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3091 if (err) { 3092 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3093 return err; 3094 } 3095 3096 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3097 if (err) { 3098 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3099 return err; 3100 } 3101 3102 err = mlxsw_sp_pgt_init(mlxsw_sp); 3103 if (err) { 3104 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n"); 3105 goto err_pgt_init; 3106 } 3107 3108 err = mlxsw_sp_fids_init(mlxsw_sp); 3109 if (err) { 3110 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3111 goto err_fids_init; 3112 } 3113 3114 err = mlxsw_sp_policers_init(mlxsw_sp); 3115 if (err) { 3116 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n"); 3117 goto err_policers_init; 3118 } 3119 3120 err = mlxsw_sp_traps_init(mlxsw_sp); 3121 if (err) { 3122 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3123 goto err_traps_init; 3124 } 3125 3126 err = mlxsw_sp_devlink_traps_init(mlxsw_sp); 3127 if (err) { 3128 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n"); 3129 goto err_devlink_traps_init; 3130 } 3131 3132 err = mlxsw_sp_buffers_init(mlxsw_sp); 3133 if (err) { 3134 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3135 goto err_buffers_init; 3136 } 3137 3138 err = mlxsw_sp_lag_init(mlxsw_sp); 3139 if (err) { 3140 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3141 goto err_lag_init; 3142 } 3143 3144 /* Initialize SPAN before router and switchdev, so that those components 3145 * can call mlxsw_sp_span_respin(). 3146 */ 3147 err = mlxsw_sp_span_init(mlxsw_sp); 3148 if (err) { 3149 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3150 goto err_span_init; 3151 } 3152 3153 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3154 if (err) { 3155 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3156 goto err_switchdev_init; 3157 } 3158 3159 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3160 if (err) { 3161 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3162 goto err_counter_pool_init; 3163 } 3164 3165 err = mlxsw_sp_afa_init(mlxsw_sp); 3166 if (err) { 3167 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3168 goto err_afa_init; 3169 } 3170 3171 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp); 3172 if (err) { 3173 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n"); 3174 goto err_ipv6_addr_ht_init; 3175 } 3176 3177 err = mlxsw_sp_nve_init(mlxsw_sp); 3178 if (err) { 3179 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 3180 goto err_nve_init; 3181 } 3182 3183 err = mlxsw_sp_acl_init(mlxsw_sp); 3184 if (err) { 3185 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3186 goto err_acl_init; 3187 } 3188 3189 err = mlxsw_sp_router_init(mlxsw_sp, extack); 3190 if (err) { 3191 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3192 goto err_router_init; 3193 } 3194 3195 if (mlxsw_sp->bus_info->read_clock_capable) { 3196 /* NULL is a valid return value from clock_init */ 3197 mlxsw_sp->clock = 3198 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp, 3199 mlxsw_sp->bus_info->dev); 3200 if (IS_ERR(mlxsw_sp->clock)) { 3201 err = PTR_ERR(mlxsw_sp->clock); 3202 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n"); 3203 goto err_ptp_clock_init; 3204 } 3205 } 3206 3207 if (mlxsw_sp->clock) { 3208 /* NULL is a valid return value from ptp_ops->init */ 3209 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp); 3210 if (IS_ERR(mlxsw_sp->ptp_state)) { 3211 err = PTR_ERR(mlxsw_sp->ptp_state); 3212 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n"); 3213 goto err_ptp_init; 3214 } 3215 } 3216 3217 /* Initialize netdevice notifier after SPAN is initialized, so that the 3218 * event handler can call SPAN respin. 3219 */ 3220 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3221 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3222 &mlxsw_sp->netdevice_nb); 3223 if (err) { 3224 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3225 goto err_netdev_notifier; 3226 } 3227 3228 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3229 if (err) { 3230 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3231 goto err_dpipe_init; 3232 } 3233 3234 err = mlxsw_sp_port_module_info_init(mlxsw_sp); 3235 if (err) { 3236 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n"); 3237 goto err_port_module_info_init; 3238 } 3239 3240 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht, 3241 &mlxsw_sp_sample_trigger_ht_params); 3242 if (err) { 3243 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n"); 3244 goto err_sample_trigger_init; 3245 } 3246 3247 err = mlxsw_sp_ports_create(mlxsw_sp); 3248 if (err) { 3249 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3250 goto err_ports_create; 3251 } 3252 3253 return 0; 3254 3255 err_ports_create: 3256 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3257 err_sample_trigger_init: 3258 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3259 err_port_module_info_init: 3260 mlxsw_sp_dpipe_fini(mlxsw_sp); 3261 err_dpipe_init: 3262 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3263 &mlxsw_sp->netdevice_nb); 3264 err_netdev_notifier: 3265 if (mlxsw_sp->clock) 3266 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3267 err_ptp_init: 3268 if (mlxsw_sp->clock) 3269 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3270 err_ptp_clock_init: 3271 mlxsw_sp_router_fini(mlxsw_sp); 3272 err_router_init: 3273 mlxsw_sp_acl_fini(mlxsw_sp); 3274 err_acl_init: 3275 mlxsw_sp_nve_fini(mlxsw_sp); 3276 err_nve_init: 3277 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3278 err_ipv6_addr_ht_init: 3279 mlxsw_sp_afa_fini(mlxsw_sp); 3280 err_afa_init: 3281 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3282 err_counter_pool_init: 3283 mlxsw_sp_switchdev_fini(mlxsw_sp); 3284 err_switchdev_init: 3285 mlxsw_sp_span_fini(mlxsw_sp); 3286 err_span_init: 3287 mlxsw_sp_lag_fini(mlxsw_sp); 3288 err_lag_init: 3289 mlxsw_sp_buffers_fini(mlxsw_sp); 3290 err_buffers_init: 3291 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3292 err_devlink_traps_init: 3293 mlxsw_sp_traps_fini(mlxsw_sp); 3294 err_traps_init: 3295 mlxsw_sp_policers_fini(mlxsw_sp); 3296 err_policers_init: 3297 mlxsw_sp_fids_fini(mlxsw_sp); 3298 err_fids_init: 3299 mlxsw_sp_pgt_fini(mlxsw_sp); 3300 err_pgt_init: 3301 mlxsw_sp_kvdl_fini(mlxsw_sp); 3302 mlxsw_sp_parsing_fini(mlxsw_sp); 3303 return err; 3304 } 3305 3306 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 3307 const struct mlxsw_bus_info *mlxsw_bus_info, 3308 struct netlink_ext_ack *extack) 3309 { 3310 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3311 3312 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops; 3313 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3314 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3315 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3316 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3317 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops; 3318 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3319 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 3320 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask; 3321 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals; 3322 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops; 3323 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops; 3324 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops; 3325 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops; 3326 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops; 3327 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops; 3328 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops; 3329 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops; 3330 mlxsw_sp->listeners = mlxsw_sp1_listener; 3331 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener); 3332 mlxsw_sp->fid_family_arr = mlxsw_sp1_fid_family_arr; 3333 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1; 3334 mlxsw_sp->pgt_smpe_index_valid = true; 3335 3336 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3337 } 3338 3339 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3340 const struct mlxsw_bus_info *mlxsw_bus_info, 3341 struct netlink_ext_ack *extack) 3342 { 3343 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3344 3345 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3346 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3347 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3348 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3349 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3350 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3351 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3352 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3353 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3354 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3355 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3356 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops; 3357 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3358 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3359 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops; 3360 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3361 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3362 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3363 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3364 mlxsw_sp->listeners = mlxsw_sp2_listener; 3365 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3366 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr; 3367 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2; 3368 mlxsw_sp->pgt_smpe_index_valid = false; 3369 3370 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3371 } 3372 3373 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core, 3374 const struct mlxsw_bus_info *mlxsw_bus_info, 3375 struct netlink_ext_ack *extack) 3376 { 3377 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3378 3379 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3380 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3381 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3382 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3383 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3384 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3385 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3386 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3387 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3388 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3389 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3390 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3391 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3392 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3393 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3394 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3395 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3396 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3397 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3398 mlxsw_sp->listeners = mlxsw_sp2_listener; 3399 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3400 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr; 3401 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3; 3402 mlxsw_sp->pgt_smpe_index_valid = false; 3403 3404 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3405 } 3406 3407 static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core, 3408 const struct mlxsw_bus_info *mlxsw_bus_info, 3409 struct netlink_ext_ack *extack) 3410 { 3411 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3412 3413 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3414 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3415 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3416 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops; 3417 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3418 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3419 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3420 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops; 3421 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3422 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3423 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3424 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3425 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3426 mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops; 3427 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3428 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3429 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3430 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3431 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3432 mlxsw_sp->listeners = mlxsw_sp2_listener; 3433 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3434 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr; 3435 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4; 3436 mlxsw_sp->pgt_smpe_index_valid = false; 3437 3438 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3439 } 3440 3441 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3442 { 3443 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3444 3445 mlxsw_sp_ports_remove(mlxsw_sp); 3446 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3447 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3448 mlxsw_sp_dpipe_fini(mlxsw_sp); 3449 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3450 &mlxsw_sp->netdevice_nb); 3451 if (mlxsw_sp->clock) { 3452 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3453 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3454 } 3455 mlxsw_sp_router_fini(mlxsw_sp); 3456 mlxsw_sp_acl_fini(mlxsw_sp); 3457 mlxsw_sp_nve_fini(mlxsw_sp); 3458 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3459 mlxsw_sp_afa_fini(mlxsw_sp); 3460 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3461 mlxsw_sp_switchdev_fini(mlxsw_sp); 3462 mlxsw_sp_span_fini(mlxsw_sp); 3463 mlxsw_sp_lag_fini(mlxsw_sp); 3464 mlxsw_sp_buffers_fini(mlxsw_sp); 3465 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3466 mlxsw_sp_traps_fini(mlxsw_sp); 3467 mlxsw_sp_policers_fini(mlxsw_sp); 3468 mlxsw_sp_fids_fini(mlxsw_sp); 3469 mlxsw_sp_pgt_fini(mlxsw_sp); 3470 mlxsw_sp_kvdl_fini(mlxsw_sp); 3471 mlxsw_sp_parsing_fini(mlxsw_sp); 3472 } 3473 3474 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3475 .used_flood_mode = 1, 3476 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3477 .used_max_ib_mc = 1, 3478 .max_ib_mc = 0, 3479 .used_max_pkey = 1, 3480 .max_pkey = 0, 3481 .used_ubridge = 1, 3482 .ubridge = 1, 3483 .used_kvd_sizes = 1, 3484 .kvd_hash_single_parts = 59, 3485 .kvd_hash_double_parts = 41, 3486 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3487 .swid_config = { 3488 { 3489 .used_type = 1, 3490 .type = MLXSW_PORT_SWID_TYPE_ETH, 3491 } 3492 }, 3493 }; 3494 3495 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3496 .used_flood_mode = 1, 3497 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3498 .used_max_ib_mc = 1, 3499 .max_ib_mc = 0, 3500 .used_max_pkey = 1, 3501 .max_pkey = 0, 3502 .used_ubridge = 1, 3503 .ubridge = 1, 3504 .swid_config = { 3505 { 3506 .used_type = 1, 3507 .type = MLXSW_PORT_SWID_TYPE_ETH, 3508 } 3509 }, 3510 .used_cqe_time_stamp_type = 1, 3511 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3512 }; 3513 3514 /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs 3515 * in Spectrum-2/3, to avoid regression in number of free entries in the PGT 3516 * table. 3517 */ 3518 #define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128 3519 3520 static const struct mlxsw_config_profile mlxsw_sp4_config_profile = { 3521 .used_max_lag = 1, 3522 .max_lag = MLXSW_SP4_CONFIG_PROFILE_MAX_LAG, 3523 .used_flood_mode = 1, 3524 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3525 .used_max_ib_mc = 1, 3526 .max_ib_mc = 0, 3527 .used_max_pkey = 1, 3528 .max_pkey = 0, 3529 .used_ubridge = 1, 3530 .ubridge = 1, 3531 .swid_config = { 3532 { 3533 .used_type = 1, 3534 .type = MLXSW_PORT_SWID_TYPE_ETH, 3535 } 3536 }, 3537 .used_cqe_time_stamp_type = 1, 3538 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3539 }; 3540 3541 static void 3542 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3543 struct devlink_resource_size_params *kvd_size_params, 3544 struct devlink_resource_size_params *linear_size_params, 3545 struct devlink_resource_size_params *hash_double_size_params, 3546 struct devlink_resource_size_params *hash_single_size_params) 3547 { 3548 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3549 KVD_SINGLE_MIN_SIZE); 3550 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3551 KVD_DOUBLE_MIN_SIZE); 3552 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3553 u32 linear_size_min = 0; 3554 3555 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3556 MLXSW_SP_KVD_GRANULARITY, 3557 DEVLINK_RESOURCE_UNIT_ENTRY); 3558 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3559 kvd_size - single_size_min - 3560 double_size_min, 3561 MLXSW_SP_KVD_GRANULARITY, 3562 DEVLINK_RESOURCE_UNIT_ENTRY); 3563 devlink_resource_size_params_init(hash_double_size_params, 3564 double_size_min, 3565 kvd_size - single_size_min - 3566 linear_size_min, 3567 MLXSW_SP_KVD_GRANULARITY, 3568 DEVLINK_RESOURCE_UNIT_ENTRY); 3569 devlink_resource_size_params_init(hash_single_size_params, 3570 single_size_min, 3571 kvd_size - double_size_min - 3572 linear_size_min, 3573 MLXSW_SP_KVD_GRANULARITY, 3574 DEVLINK_RESOURCE_UNIT_ENTRY); 3575 } 3576 3577 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3578 { 3579 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3580 struct devlink_resource_size_params hash_single_size_params; 3581 struct devlink_resource_size_params hash_double_size_params; 3582 struct devlink_resource_size_params linear_size_params; 3583 struct devlink_resource_size_params kvd_size_params; 3584 u32 kvd_size, single_size, double_size, linear_size; 3585 const struct mlxsw_config_profile *profile; 3586 int err; 3587 3588 profile = &mlxsw_sp1_config_profile; 3589 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3590 return -EIO; 3591 3592 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3593 &linear_size_params, 3594 &hash_double_size_params, 3595 &hash_single_size_params); 3596 3597 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3598 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3599 kvd_size, MLXSW_SP_RESOURCE_KVD, 3600 DEVLINK_RESOURCE_ID_PARENT_TOP, 3601 &kvd_size_params); 3602 if (err) 3603 return err; 3604 3605 linear_size = profile->kvd_linear_size; 3606 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3607 linear_size, 3608 MLXSW_SP_RESOURCE_KVD_LINEAR, 3609 MLXSW_SP_RESOURCE_KVD, 3610 &linear_size_params); 3611 if (err) 3612 return err; 3613 3614 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 3615 if (err) 3616 return err; 3617 3618 double_size = kvd_size - linear_size; 3619 double_size *= profile->kvd_hash_double_parts; 3620 double_size /= profile->kvd_hash_double_parts + 3621 profile->kvd_hash_single_parts; 3622 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3623 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3624 double_size, 3625 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3626 MLXSW_SP_RESOURCE_KVD, 3627 &hash_double_size_params); 3628 if (err) 3629 return err; 3630 3631 single_size = kvd_size - double_size - linear_size; 3632 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3633 single_size, 3634 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3635 MLXSW_SP_RESOURCE_KVD, 3636 &hash_single_size_params); 3637 if (err) 3638 return err; 3639 3640 return 0; 3641 } 3642 3643 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3644 { 3645 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3646 struct devlink_resource_size_params kvd_size_params; 3647 u32 kvd_size; 3648 3649 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3650 return -EIO; 3651 3652 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3653 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size, 3654 MLXSW_SP_KVD_GRANULARITY, 3655 DEVLINK_RESOURCE_UNIT_ENTRY); 3656 3657 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3658 kvd_size, MLXSW_SP_RESOURCE_KVD, 3659 DEVLINK_RESOURCE_ID_PARENT_TOP, 3660 &kvd_size_params); 3661 } 3662 3663 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core) 3664 { 3665 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3666 struct devlink_resource_size_params span_size_params; 3667 u32 max_span; 3668 3669 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN)) 3670 return -EIO; 3671 3672 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN); 3673 devlink_resource_size_params_init(&span_size_params, max_span, max_span, 3674 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3675 3676 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN, 3677 max_span, MLXSW_SP_RESOURCE_SPAN, 3678 DEVLINK_RESOURCE_ID_PARENT_TOP, 3679 &span_size_params); 3680 } 3681 3682 static int 3683 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core) 3684 { 3685 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3686 struct devlink_resource_size_params size_params; 3687 u8 max_rif_mac_profiles; 3688 3689 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES)) 3690 max_rif_mac_profiles = 1; 3691 else 3692 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core, 3693 MAX_RIF_MAC_PROFILES); 3694 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles, 3695 max_rif_mac_profiles, 1, 3696 DEVLINK_RESOURCE_UNIT_ENTRY); 3697 3698 return devl_resource_register(devlink, 3699 "rif_mac_profiles", 3700 max_rif_mac_profiles, 3701 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES, 3702 DEVLINK_RESOURCE_ID_PARENT_TOP, 3703 &size_params); 3704 } 3705 3706 static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core) 3707 { 3708 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3709 struct devlink_resource_size_params size_params; 3710 u64 max_rifs; 3711 3712 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS)) 3713 return -EIO; 3714 3715 max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS); 3716 devlink_resource_size_params_init(&size_params, max_rifs, max_rifs, 3717 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3718 3719 return devl_resource_register(devlink, "rifs", max_rifs, 3720 MLXSW_SP_RESOURCE_RIFS, 3721 DEVLINK_RESOURCE_ID_PARENT_TOP, 3722 &size_params); 3723 } 3724 3725 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 3726 { 3727 int err; 3728 3729 err = mlxsw_sp1_resources_kvd_register(mlxsw_core); 3730 if (err) 3731 return err; 3732 3733 err = mlxsw_sp_resources_span_register(mlxsw_core); 3734 if (err) 3735 goto err_resources_span_register; 3736 3737 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3738 if (err) 3739 goto err_resources_counter_register; 3740 3741 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3742 if (err) 3743 goto err_policer_resources_register; 3744 3745 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3746 if (err) 3747 goto err_resources_rif_mac_profile_register; 3748 3749 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3750 if (err) 3751 goto err_resources_rifs_register; 3752 3753 return 0; 3754 3755 err_resources_rifs_register: 3756 err_resources_rif_mac_profile_register: 3757 err_policer_resources_register: 3758 err_resources_counter_register: 3759 err_resources_span_register: 3760 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3761 return err; 3762 } 3763 3764 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 3765 { 3766 int err; 3767 3768 err = mlxsw_sp2_resources_kvd_register(mlxsw_core); 3769 if (err) 3770 return err; 3771 3772 err = mlxsw_sp_resources_span_register(mlxsw_core); 3773 if (err) 3774 goto err_resources_span_register; 3775 3776 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3777 if (err) 3778 goto err_resources_counter_register; 3779 3780 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3781 if (err) 3782 goto err_policer_resources_register; 3783 3784 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3785 if (err) 3786 goto err_resources_rif_mac_profile_register; 3787 3788 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3789 if (err) 3790 goto err_resources_rifs_register; 3791 3792 return 0; 3793 3794 err_resources_rifs_register: 3795 err_resources_rif_mac_profile_register: 3796 err_policer_resources_register: 3797 err_resources_counter_register: 3798 err_resources_span_register: 3799 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3800 return err; 3801 } 3802 3803 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3804 const struct mlxsw_config_profile *profile, 3805 u64 *p_single_size, u64 *p_double_size, 3806 u64 *p_linear_size) 3807 { 3808 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3809 u32 double_size; 3810 int err; 3811 3812 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3813 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3814 return -EIO; 3815 3816 /* The hash part is what left of the kvd without the 3817 * linear part. It is split to the single size and 3818 * double size by the parts ratio from the profile. 3819 * Both sizes must be a multiplications of the 3820 * granularity from the profile. In case the user 3821 * provided the sizes they are obtained via devlink. 3822 */ 3823 err = devl_resource_size_get(devlink, 3824 MLXSW_SP_RESOURCE_KVD_LINEAR, 3825 p_linear_size); 3826 if (err) 3827 *p_linear_size = profile->kvd_linear_size; 3828 3829 err = devl_resource_size_get(devlink, 3830 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3831 p_double_size); 3832 if (err) { 3833 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3834 *p_linear_size; 3835 double_size *= profile->kvd_hash_double_parts; 3836 double_size /= profile->kvd_hash_double_parts + 3837 profile->kvd_hash_single_parts; 3838 *p_double_size = rounddown(double_size, 3839 MLXSW_SP_KVD_GRANULARITY); 3840 } 3841 3842 err = devl_resource_size_get(devlink, 3843 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3844 p_single_size); 3845 if (err) 3846 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3847 *p_double_size - *p_linear_size; 3848 3849 /* Check results are legal. */ 3850 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3851 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3852 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3853 return -EIO; 3854 3855 return 0; 3856 } 3857 3858 static int 3859 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id, 3860 struct devlink_param_gset_ctx *ctx) 3861 { 3862 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3863 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3864 3865 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp); 3866 return 0; 3867 } 3868 3869 static int 3870 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id, 3871 struct devlink_param_gset_ctx *ctx) 3872 { 3873 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3874 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3875 3876 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32); 3877 } 3878 3879 static const struct devlink_param mlxsw_sp2_devlink_params[] = { 3880 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 3881 "acl_region_rehash_interval", 3882 DEVLINK_PARAM_TYPE_U32, 3883 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3884 mlxsw_sp_params_acl_region_rehash_intrvl_get, 3885 mlxsw_sp_params_acl_region_rehash_intrvl_set, 3886 NULL), 3887 }; 3888 3889 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core) 3890 { 3891 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3892 union devlink_param_value value; 3893 int err; 3894 3895 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params, 3896 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 3897 if (err) 3898 return err; 3899 3900 value.vu32 = 0; 3901 devlink_param_driverinit_value_set(devlink, 3902 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 3903 value); 3904 return 0; 3905 } 3906 3907 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core) 3908 { 3909 devlink_params_unregister(priv_to_devlink(mlxsw_core), 3910 mlxsw_sp2_devlink_params, 3911 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 3912 } 3913 3914 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core, 3915 struct sk_buff *skb, u16 local_port) 3916 { 3917 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3918 3919 skb_pull(skb, MLXSW_TXHDR_LEN); 3920 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port); 3921 } 3922 3923 static struct mlxsw_driver mlxsw_sp1_driver = { 3924 .kind = mlxsw_sp1_driver_name, 3925 .priv_size = sizeof(struct mlxsw_sp), 3926 .fw_req_rev = &mlxsw_sp1_fw_rev, 3927 .fw_filename = MLXSW_SP1_FW_FILENAME, 3928 .init = mlxsw_sp1_init, 3929 .fini = mlxsw_sp_fini, 3930 .port_split = mlxsw_sp_port_split, 3931 .port_unsplit = mlxsw_sp_port_unsplit, 3932 .sb_pool_get = mlxsw_sp_sb_pool_get, 3933 .sb_pool_set = mlxsw_sp_sb_pool_set, 3934 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3935 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3936 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3937 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3938 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3939 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3940 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3941 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3942 .trap_init = mlxsw_sp_trap_init, 3943 .trap_fini = mlxsw_sp_trap_fini, 3944 .trap_action_set = mlxsw_sp_trap_action_set, 3945 .trap_group_init = mlxsw_sp_trap_group_init, 3946 .trap_group_set = mlxsw_sp_trap_group_set, 3947 .trap_policer_init = mlxsw_sp_trap_policer_init, 3948 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3949 .trap_policer_set = mlxsw_sp_trap_policer_set, 3950 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3951 .txhdr_construct = mlxsw_sp_txhdr_construct, 3952 .resources_register = mlxsw_sp1_resources_register, 3953 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 3954 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3955 .txhdr_len = MLXSW_TXHDR_LEN, 3956 .profile = &mlxsw_sp1_config_profile, 3957 .sdq_supports_cqe_v2 = false, 3958 }; 3959 3960 static struct mlxsw_driver mlxsw_sp2_driver = { 3961 .kind = mlxsw_sp2_driver_name, 3962 .priv_size = sizeof(struct mlxsw_sp), 3963 .fw_req_rev = &mlxsw_sp2_fw_rev, 3964 .fw_filename = MLXSW_SP2_FW_FILENAME, 3965 .init = mlxsw_sp2_init, 3966 .fini = mlxsw_sp_fini, 3967 .port_split = mlxsw_sp_port_split, 3968 .port_unsplit = mlxsw_sp_port_unsplit, 3969 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3970 .sb_pool_get = mlxsw_sp_sb_pool_get, 3971 .sb_pool_set = mlxsw_sp_sb_pool_set, 3972 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3973 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3974 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3975 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3976 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3977 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3978 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3979 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3980 .trap_init = mlxsw_sp_trap_init, 3981 .trap_fini = mlxsw_sp_trap_fini, 3982 .trap_action_set = mlxsw_sp_trap_action_set, 3983 .trap_group_init = mlxsw_sp_trap_group_init, 3984 .trap_group_set = mlxsw_sp_trap_group_set, 3985 .trap_policer_init = mlxsw_sp_trap_policer_init, 3986 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3987 .trap_policer_set = mlxsw_sp_trap_policer_set, 3988 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3989 .txhdr_construct = mlxsw_sp_txhdr_construct, 3990 .resources_register = mlxsw_sp2_resources_register, 3991 .params_register = mlxsw_sp2_params_register, 3992 .params_unregister = mlxsw_sp2_params_unregister, 3993 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3994 .txhdr_len = MLXSW_TXHDR_LEN, 3995 .profile = &mlxsw_sp2_config_profile, 3996 .sdq_supports_cqe_v2 = true, 3997 }; 3998 3999 static struct mlxsw_driver mlxsw_sp3_driver = { 4000 .kind = mlxsw_sp3_driver_name, 4001 .priv_size = sizeof(struct mlxsw_sp), 4002 .fw_req_rev = &mlxsw_sp3_fw_rev, 4003 .fw_filename = MLXSW_SP3_FW_FILENAME, 4004 .init = mlxsw_sp3_init, 4005 .fini = mlxsw_sp_fini, 4006 .port_split = mlxsw_sp_port_split, 4007 .port_unsplit = mlxsw_sp_port_unsplit, 4008 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 4009 .sb_pool_get = mlxsw_sp_sb_pool_get, 4010 .sb_pool_set = mlxsw_sp_sb_pool_set, 4011 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4012 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4013 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4014 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4015 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4016 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4017 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4018 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4019 .trap_init = mlxsw_sp_trap_init, 4020 .trap_fini = mlxsw_sp_trap_fini, 4021 .trap_action_set = mlxsw_sp_trap_action_set, 4022 .trap_group_init = mlxsw_sp_trap_group_init, 4023 .trap_group_set = mlxsw_sp_trap_group_set, 4024 .trap_policer_init = mlxsw_sp_trap_policer_init, 4025 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 4026 .trap_policer_set = mlxsw_sp_trap_policer_set, 4027 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 4028 .txhdr_construct = mlxsw_sp_txhdr_construct, 4029 .resources_register = mlxsw_sp2_resources_register, 4030 .params_register = mlxsw_sp2_params_register, 4031 .params_unregister = mlxsw_sp2_params_unregister, 4032 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 4033 .txhdr_len = MLXSW_TXHDR_LEN, 4034 .profile = &mlxsw_sp2_config_profile, 4035 .sdq_supports_cqe_v2 = true, 4036 }; 4037 4038 static struct mlxsw_driver mlxsw_sp4_driver = { 4039 .kind = mlxsw_sp4_driver_name, 4040 .priv_size = sizeof(struct mlxsw_sp), 4041 .init = mlxsw_sp4_init, 4042 .fini = mlxsw_sp_fini, 4043 .port_split = mlxsw_sp_port_split, 4044 .port_unsplit = mlxsw_sp_port_unsplit, 4045 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 4046 .sb_pool_get = mlxsw_sp_sb_pool_get, 4047 .sb_pool_set = mlxsw_sp_sb_pool_set, 4048 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4049 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4050 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4051 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4052 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4053 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4054 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4055 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4056 .trap_init = mlxsw_sp_trap_init, 4057 .trap_fini = mlxsw_sp_trap_fini, 4058 .trap_action_set = mlxsw_sp_trap_action_set, 4059 .trap_group_init = mlxsw_sp_trap_group_init, 4060 .trap_group_set = mlxsw_sp_trap_group_set, 4061 .trap_policer_init = mlxsw_sp_trap_policer_init, 4062 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 4063 .trap_policer_set = mlxsw_sp_trap_policer_set, 4064 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 4065 .txhdr_construct = mlxsw_sp_txhdr_construct, 4066 .resources_register = mlxsw_sp2_resources_register, 4067 .params_register = mlxsw_sp2_params_register, 4068 .params_unregister = mlxsw_sp2_params_unregister, 4069 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 4070 .txhdr_len = MLXSW_TXHDR_LEN, 4071 .profile = &mlxsw_sp4_config_profile, 4072 .sdq_supports_cqe_v2 = true, 4073 }; 4074 4075 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 4076 { 4077 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 4078 } 4079 4080 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, 4081 struct netdev_nested_priv *priv) 4082 { 4083 int ret = 0; 4084 4085 if (mlxsw_sp_port_dev_check(lower_dev)) { 4086 priv->data = (void *)netdev_priv(lower_dev); 4087 ret = 1; 4088 } 4089 4090 return ret; 4091 } 4092 4093 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4094 { 4095 struct netdev_nested_priv priv = { 4096 .data = NULL, 4097 }; 4098 4099 if (mlxsw_sp_port_dev_check(dev)) 4100 return netdev_priv(dev); 4101 4102 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv); 4103 4104 return (struct mlxsw_sp_port *)priv.data; 4105 } 4106 4107 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4108 { 4109 struct mlxsw_sp_port *mlxsw_sp_port; 4110 4111 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4112 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4113 } 4114 4115 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4116 { 4117 struct netdev_nested_priv priv = { 4118 .data = NULL, 4119 }; 4120 4121 if (mlxsw_sp_port_dev_check(dev)) 4122 return netdev_priv(dev); 4123 4124 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4125 &priv); 4126 4127 return (struct mlxsw_sp_port *)priv.data; 4128 } 4129 4130 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4131 { 4132 struct mlxsw_sp_port *mlxsw_sp_port; 4133 4134 rcu_read_lock(); 4135 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4136 if (mlxsw_sp_port) 4137 dev_hold(mlxsw_sp_port->dev); 4138 rcu_read_unlock(); 4139 return mlxsw_sp_port; 4140 } 4141 4142 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4143 { 4144 dev_put(mlxsw_sp_port->dev); 4145 } 4146 4147 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp) 4148 { 4149 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4150 int err = 0; 4151 4152 mutex_lock(&mlxsw_sp->parsing.lock); 4153 4154 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref)) 4155 goto out_unlock; 4156 4157 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH, 4158 mlxsw_sp->parsing.vxlan_udp_dport); 4159 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4160 if (err) 4161 goto out_unlock; 4162 4163 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH; 4164 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1); 4165 4166 out_unlock: 4167 mutex_unlock(&mlxsw_sp->parsing.lock); 4168 return err; 4169 } 4170 4171 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp) 4172 { 4173 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4174 4175 mutex_lock(&mlxsw_sp->parsing.lock); 4176 4177 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref)) 4178 goto out_unlock; 4179 4180 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH, 4181 mlxsw_sp->parsing.vxlan_udp_dport); 4182 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4183 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 4184 4185 out_unlock: 4186 mutex_unlock(&mlxsw_sp->parsing.lock); 4187 } 4188 4189 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp, 4190 __be16 udp_dport) 4191 { 4192 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4193 int err; 4194 4195 mutex_lock(&mlxsw_sp->parsing.lock); 4196 4197 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth, 4198 be16_to_cpu(udp_dport)); 4199 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4200 if (err) 4201 goto out_unlock; 4202 4203 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport); 4204 4205 out_unlock: 4206 mutex_unlock(&mlxsw_sp->parsing.lock); 4207 return err; 4208 } 4209 4210 static void 4211 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port, 4212 struct net_device *lag_dev) 4213 { 4214 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev); 4215 struct net_device *upper_dev; 4216 struct list_head *iter; 4217 4218 if (netif_is_bridge_port(lag_dev)) 4219 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev); 4220 4221 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4222 if (!netif_is_bridge_port(upper_dev)) 4223 continue; 4224 br_dev = netdev_master_upper_dev_get(upper_dev); 4225 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev); 4226 } 4227 } 4228 4229 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4230 { 4231 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4232 4233 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4235 } 4236 4237 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4238 { 4239 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4240 4241 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4242 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4243 } 4244 4245 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4246 u16 lag_id, u8 port_index) 4247 { 4248 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4249 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4250 4251 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4252 lag_id, port_index); 4253 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4254 } 4255 4256 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4257 u16 lag_id) 4258 { 4259 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4260 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4261 4262 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4263 lag_id); 4264 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4265 } 4266 4267 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4268 u16 lag_id) 4269 { 4270 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4271 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4272 4273 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4274 lag_id); 4275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4276 } 4277 4278 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4279 u16 lag_id) 4280 { 4281 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4282 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4283 4284 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4285 lag_id); 4286 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4287 } 4288 4289 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4290 struct net_device *lag_dev, 4291 u16 *p_lag_id) 4292 { 4293 struct mlxsw_sp_upper *lag; 4294 int free_lag_id = -1; 4295 u16 max_lag; 4296 int err, i; 4297 4298 err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); 4299 if (err) 4300 return err; 4301 4302 for (i = 0; i < max_lag; i++) { 4303 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4304 if (lag->ref_count) { 4305 if (lag->dev == lag_dev) { 4306 *p_lag_id = i; 4307 return 0; 4308 } 4309 } else if (free_lag_id < 0) { 4310 free_lag_id = i; 4311 } 4312 } 4313 if (free_lag_id < 0) 4314 return -EBUSY; 4315 *p_lag_id = free_lag_id; 4316 return 0; 4317 } 4318 4319 static bool 4320 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4321 struct net_device *lag_dev, 4322 struct netdev_lag_upper_info *lag_upper_info, 4323 struct netlink_ext_ack *extack) 4324 { 4325 u16 lag_id; 4326 4327 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4328 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4329 return false; 4330 } 4331 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4332 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4333 return false; 4334 } 4335 return true; 4336 } 4337 4338 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4339 u16 lag_id, u8 *p_port_index) 4340 { 4341 u64 max_lag_members; 4342 int i; 4343 4344 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4345 MAX_LAG_MEMBERS); 4346 for (i = 0; i < max_lag_members; i++) { 4347 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4348 *p_port_index = i; 4349 return 0; 4350 } 4351 } 4352 return -EBUSY; 4353 } 4354 4355 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4356 struct net_device *lag_dev, 4357 struct netlink_ext_ack *extack) 4358 { 4359 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4360 struct mlxsw_sp_upper *lag; 4361 u16 lag_id; 4362 u8 port_index; 4363 int err; 4364 4365 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4366 if (err) 4367 return err; 4368 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4369 if (!lag->ref_count) { 4370 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4371 if (err) 4372 return err; 4373 lag->dev = lag_dev; 4374 } 4375 4376 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4377 if (err) 4378 return err; 4379 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4380 if (err) 4381 goto err_col_port_add; 4382 4383 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4384 mlxsw_sp_port->local_port); 4385 mlxsw_sp_port->lag_id = lag_id; 4386 mlxsw_sp_port->lagged = 1; 4387 lag->ref_count++; 4388 4389 /* Port is no longer usable as a router interface */ 4390 if (mlxsw_sp_port->default_vlan->fid) 4391 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan); 4392 4393 /* Join a router interface configured on the LAG, if exists */ 4394 err = mlxsw_sp_port_vlan_router_join(mlxsw_sp_port->default_vlan, 4395 lag_dev, extack); 4396 if (err) 4397 goto err_router_join; 4398 4399 return 0; 4400 4401 err_router_join: 4402 lag->ref_count--; 4403 mlxsw_sp_port->lagged = 0; 4404 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4405 mlxsw_sp_port->local_port); 4406 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4407 err_col_port_add: 4408 if (!lag->ref_count) 4409 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4410 return err; 4411 } 4412 4413 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4414 struct net_device *lag_dev) 4415 { 4416 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4417 u16 lag_id = mlxsw_sp_port->lag_id; 4418 struct mlxsw_sp_upper *lag; 4419 4420 if (!mlxsw_sp_port->lagged) 4421 return; 4422 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4423 WARN_ON(lag->ref_count == 0); 4424 4425 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4426 4427 /* Any VLANs configured on the port are no longer valid */ 4428 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false); 4429 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan); 4430 /* Make the LAG and its directly linked uppers leave bridges they 4431 * are memeber in 4432 */ 4433 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev); 4434 4435 if (lag->ref_count == 1) 4436 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4437 4438 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4439 mlxsw_sp_port->local_port); 4440 mlxsw_sp_port->lagged = 0; 4441 lag->ref_count--; 4442 4443 /* Make sure untagged frames are allowed to ingress */ 4444 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 4445 ETH_P_8021Q); 4446 } 4447 4448 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4449 u16 lag_id) 4450 { 4451 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4452 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4453 4454 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4455 mlxsw_sp_port->local_port); 4456 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4457 } 4458 4459 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4460 u16 lag_id) 4461 { 4462 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4463 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4464 4465 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4466 mlxsw_sp_port->local_port); 4467 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4468 } 4469 4470 static int 4471 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port) 4472 { 4473 int err; 4474 4475 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, 4476 mlxsw_sp_port->lag_id); 4477 if (err) 4478 return err; 4479 4480 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4481 if (err) 4482 goto err_dist_port_add; 4483 4484 return 0; 4485 4486 err_dist_port_add: 4487 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4488 return err; 4489 } 4490 4491 static int 4492 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port) 4493 { 4494 int err; 4495 4496 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4497 mlxsw_sp_port->lag_id); 4498 if (err) 4499 return err; 4500 4501 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, 4502 mlxsw_sp_port->lag_id); 4503 if (err) 4504 goto err_col_port_disable; 4505 4506 return 0; 4507 4508 err_col_port_disable: 4509 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4510 return err; 4511 } 4512 4513 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4514 struct netdev_lag_lower_state_info *info) 4515 { 4516 if (info->tx_enabled) 4517 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port); 4518 else 4519 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4520 } 4521 4522 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4523 bool enable) 4524 { 4525 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4526 enum mlxsw_reg_spms_state spms_state; 4527 char *spms_pl; 4528 u16 vid; 4529 int err; 4530 4531 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4532 MLXSW_REG_SPMS_STATE_DISCARDING; 4533 4534 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4535 if (!spms_pl) 4536 return -ENOMEM; 4537 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4538 4539 for (vid = 0; vid < VLAN_N_VID; vid++) 4540 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4541 4542 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4543 kfree(spms_pl); 4544 return err; 4545 } 4546 4547 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4548 { 4549 u16 vid = 1; 4550 int err; 4551 4552 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4553 if (err) 4554 return err; 4555 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4556 if (err) 4557 goto err_port_stp_set; 4558 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4559 true, false); 4560 if (err) 4561 goto err_port_vlan_set; 4562 4563 for (; vid <= VLAN_N_VID - 1; vid++) { 4564 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4565 vid, false); 4566 if (err) 4567 goto err_vid_learning_set; 4568 } 4569 4570 return 0; 4571 4572 err_vid_learning_set: 4573 for (vid--; vid >= 1; vid--) 4574 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4575 err_port_vlan_set: 4576 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4577 err_port_stp_set: 4578 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4579 return err; 4580 } 4581 4582 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4583 { 4584 u16 vid; 4585 4586 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4587 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4588 vid, true); 4589 4590 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4591 false, false); 4592 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4593 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4594 } 4595 4596 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4597 { 4598 unsigned int num_vxlans = 0; 4599 struct net_device *dev; 4600 struct list_head *iter; 4601 4602 netdev_for_each_lower_dev(br_dev, dev, iter) { 4603 if (netif_is_vxlan(dev)) 4604 num_vxlans++; 4605 } 4606 4607 return num_vxlans > 1; 4608 } 4609 4610 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev) 4611 { 4612 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0}; 4613 struct net_device *dev; 4614 struct list_head *iter; 4615 4616 netdev_for_each_lower_dev(br_dev, dev, iter) { 4617 u16 pvid; 4618 int err; 4619 4620 if (!netif_is_vxlan(dev)) 4621 continue; 4622 4623 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid); 4624 if (err || !pvid) 4625 continue; 4626 4627 if (test_and_set_bit(pvid, vlans)) 4628 return false; 4629 } 4630 4631 return true; 4632 } 4633 4634 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4635 struct netlink_ext_ack *extack) 4636 { 4637 if (br_multicast_enabled(br_dev)) { 4638 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4639 return false; 4640 } 4641 4642 if (!br_vlan_enabled(br_dev) && 4643 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4644 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4645 return false; 4646 } 4647 4648 if (br_vlan_enabled(br_dev) && 4649 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) { 4650 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged"); 4651 return false; 4652 } 4653 4654 return true; 4655 } 4656 4657 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4658 struct net_device *dev, 4659 unsigned long event, void *ptr) 4660 { 4661 struct netdev_notifier_changeupper_info *info; 4662 struct mlxsw_sp_port *mlxsw_sp_port; 4663 struct netlink_ext_ack *extack; 4664 struct net_device *upper_dev; 4665 struct mlxsw_sp *mlxsw_sp; 4666 int err = 0; 4667 u16 proto; 4668 4669 mlxsw_sp_port = netdev_priv(dev); 4670 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4671 info = ptr; 4672 extack = netdev_notifier_info_to_extack(&info->info); 4673 4674 switch (event) { 4675 case NETDEV_PRECHANGEUPPER: 4676 upper_dev = info->upper_dev; 4677 if (!is_vlan_dev(upper_dev) && 4678 !netif_is_lag_master(upper_dev) && 4679 !netif_is_bridge_master(upper_dev) && 4680 !netif_is_ovs_master(upper_dev) && 4681 !netif_is_macvlan(upper_dev) && 4682 !netif_is_l3_master(upper_dev)) { 4683 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4684 return -EINVAL; 4685 } 4686 if (!info->linking) 4687 break; 4688 if (netif_is_bridge_master(upper_dev) && 4689 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4690 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4691 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4692 return -EOPNOTSUPP; 4693 if (netdev_has_any_upper_dev(upper_dev) && 4694 (!netif_is_bridge_master(upper_dev) || 4695 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4696 upper_dev))) { 4697 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4698 return -EINVAL; 4699 } 4700 if (netif_is_lag_master(upper_dev) && 4701 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4702 info->upper_info, extack)) 4703 return -EINVAL; 4704 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4705 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4706 return -EINVAL; 4707 } 4708 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4709 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4710 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4711 return -EINVAL; 4712 } 4713 if (netif_is_macvlan(upper_dev) && 4714 !mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) { 4715 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4716 return -EOPNOTSUPP; 4717 } 4718 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4719 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4720 return -EINVAL; 4721 } 4722 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4723 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4724 return -EINVAL; 4725 } 4726 if (netif_is_bridge_master(upper_dev)) { 4727 br_vlan_get_proto(upper_dev, &proto); 4728 if (br_vlan_enabled(upper_dev) && 4729 proto != ETH_P_8021Q && proto != ETH_P_8021AD) { 4730 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported"); 4731 return -EOPNOTSUPP; 4732 } 4733 if (vlan_uses_dev(lower_dev) && 4734 br_vlan_enabled(upper_dev) && 4735 proto == ETH_P_8021AD) { 4736 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported"); 4737 return -EOPNOTSUPP; 4738 } 4739 } 4740 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) { 4741 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev); 4742 4743 if (br_vlan_enabled(br_dev)) { 4744 br_vlan_get_proto(br_dev, &proto); 4745 if (proto == ETH_P_8021AD) { 4746 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge"); 4747 return -EOPNOTSUPP; 4748 } 4749 } 4750 } 4751 if (is_vlan_dev(upper_dev) && 4752 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4753 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4754 return -EOPNOTSUPP; 4755 } 4756 break; 4757 case NETDEV_CHANGEUPPER: 4758 upper_dev = info->upper_dev; 4759 if (netif_is_bridge_master(upper_dev)) { 4760 if (info->linking) 4761 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4762 lower_dev, 4763 upper_dev, 4764 extack); 4765 else 4766 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4767 lower_dev, 4768 upper_dev); 4769 } else if (netif_is_lag_master(upper_dev)) { 4770 if (info->linking) { 4771 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4772 upper_dev, extack); 4773 } else { 4774 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4775 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4776 upper_dev); 4777 } 4778 } else if (netif_is_ovs_master(upper_dev)) { 4779 if (info->linking) 4780 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4781 else 4782 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4783 } else if (netif_is_macvlan(upper_dev)) { 4784 if (!info->linking) 4785 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4786 } else if (is_vlan_dev(upper_dev)) { 4787 struct net_device *br_dev; 4788 4789 if (!netif_is_bridge_port(upper_dev)) 4790 break; 4791 if (info->linking) 4792 break; 4793 br_dev = netdev_master_upper_dev_get(upper_dev); 4794 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, 4795 br_dev); 4796 } 4797 break; 4798 } 4799 4800 return err; 4801 } 4802 4803 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4804 unsigned long event, void *ptr) 4805 { 4806 struct netdev_notifier_changelowerstate_info *info; 4807 struct mlxsw_sp_port *mlxsw_sp_port; 4808 int err; 4809 4810 mlxsw_sp_port = netdev_priv(dev); 4811 info = ptr; 4812 4813 switch (event) { 4814 case NETDEV_CHANGELOWERSTATE: 4815 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4816 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4817 info->lower_state_info); 4818 if (err) 4819 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4820 } 4821 break; 4822 } 4823 4824 return 0; 4825 } 4826 4827 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4828 struct net_device *port_dev, 4829 unsigned long event, void *ptr) 4830 { 4831 switch (event) { 4832 case NETDEV_PRECHANGEUPPER: 4833 case NETDEV_CHANGEUPPER: 4834 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4835 event, ptr); 4836 case NETDEV_CHANGELOWERSTATE: 4837 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4838 ptr); 4839 } 4840 4841 return 0; 4842 } 4843 4844 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4845 unsigned long event, void *ptr) 4846 { 4847 struct net_device *dev; 4848 struct list_head *iter; 4849 int ret; 4850 4851 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4852 if (mlxsw_sp_port_dev_check(dev)) { 4853 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4854 ptr); 4855 if (ret) 4856 return ret; 4857 } 4858 } 4859 4860 return 0; 4861 } 4862 4863 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4864 struct net_device *dev, 4865 unsigned long event, void *ptr, 4866 u16 vid) 4867 { 4868 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4869 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4870 struct netdev_notifier_changeupper_info *info = ptr; 4871 struct netlink_ext_ack *extack; 4872 struct net_device *upper_dev; 4873 int err = 0; 4874 4875 extack = netdev_notifier_info_to_extack(&info->info); 4876 4877 switch (event) { 4878 case NETDEV_PRECHANGEUPPER: 4879 upper_dev = info->upper_dev; 4880 if (!netif_is_bridge_master(upper_dev) && 4881 !netif_is_macvlan(upper_dev) && 4882 !netif_is_l3_master(upper_dev)) { 4883 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4884 return -EINVAL; 4885 } 4886 if (!info->linking) 4887 break; 4888 if (netif_is_bridge_master(upper_dev) && 4889 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4890 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4891 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4892 return -EOPNOTSUPP; 4893 if (netdev_has_any_upper_dev(upper_dev) && 4894 (!netif_is_bridge_master(upper_dev) || 4895 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4896 upper_dev))) { 4897 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4898 return -EINVAL; 4899 } 4900 if (netif_is_macvlan(upper_dev) && 4901 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) { 4902 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4903 return -EOPNOTSUPP; 4904 } 4905 break; 4906 case NETDEV_CHANGEUPPER: 4907 upper_dev = info->upper_dev; 4908 if (netif_is_bridge_master(upper_dev)) { 4909 if (info->linking) 4910 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4911 vlan_dev, 4912 upper_dev, 4913 extack); 4914 else 4915 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4916 vlan_dev, 4917 upper_dev); 4918 } else if (netif_is_macvlan(upper_dev)) { 4919 if (!info->linking) 4920 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4921 } 4922 break; 4923 } 4924 4925 return err; 4926 } 4927 4928 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4929 struct net_device *lag_dev, 4930 unsigned long event, 4931 void *ptr, u16 vid) 4932 { 4933 struct net_device *dev; 4934 struct list_head *iter; 4935 int ret; 4936 4937 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4938 if (mlxsw_sp_port_dev_check(dev)) { 4939 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4940 event, ptr, 4941 vid); 4942 if (ret) 4943 return ret; 4944 } 4945 } 4946 4947 return 0; 4948 } 4949 4950 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev, 4951 struct net_device *br_dev, 4952 unsigned long event, void *ptr, 4953 u16 vid) 4954 { 4955 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev); 4956 struct netdev_notifier_changeupper_info *info = ptr; 4957 struct netlink_ext_ack *extack; 4958 struct net_device *upper_dev; 4959 4960 if (!mlxsw_sp) 4961 return 0; 4962 4963 extack = netdev_notifier_info_to_extack(&info->info); 4964 4965 switch (event) { 4966 case NETDEV_PRECHANGEUPPER: 4967 upper_dev = info->upper_dev; 4968 if (!netif_is_macvlan(upper_dev) && 4969 !netif_is_l3_master(upper_dev)) { 4970 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4971 return -EOPNOTSUPP; 4972 } 4973 if (!info->linking) 4974 break; 4975 if (netif_is_macvlan(upper_dev) && 4976 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) { 4977 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4978 return -EOPNOTSUPP; 4979 } 4980 break; 4981 case NETDEV_CHANGEUPPER: 4982 upper_dev = info->upper_dev; 4983 if (info->linking) 4984 break; 4985 if (netif_is_macvlan(upper_dev)) 4986 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4987 break; 4988 } 4989 4990 return 0; 4991 } 4992 4993 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4994 unsigned long event, void *ptr) 4995 { 4996 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4997 u16 vid = vlan_dev_vlan_id(vlan_dev); 4998 4999 if (mlxsw_sp_port_dev_check(real_dev)) 5000 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 5001 event, ptr, vid); 5002 else if (netif_is_lag_master(real_dev)) 5003 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 5004 real_dev, event, 5005 ptr, vid); 5006 else if (netif_is_bridge_master(real_dev)) 5007 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev, 5008 event, ptr, vid); 5009 5010 return 0; 5011 } 5012 5013 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 5014 unsigned long event, void *ptr) 5015 { 5016 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 5017 struct netdev_notifier_changeupper_info *info = ptr; 5018 struct netlink_ext_ack *extack; 5019 struct net_device *upper_dev; 5020 u16 proto; 5021 5022 if (!mlxsw_sp) 5023 return 0; 5024 5025 extack = netdev_notifier_info_to_extack(&info->info); 5026 5027 switch (event) { 5028 case NETDEV_PRECHANGEUPPER: 5029 upper_dev = info->upper_dev; 5030 if (!is_vlan_dev(upper_dev) && 5031 !netif_is_macvlan(upper_dev) && 5032 !netif_is_l3_master(upper_dev)) { 5033 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5034 return -EOPNOTSUPP; 5035 } 5036 if (!info->linking) 5037 break; 5038 if (br_vlan_enabled(br_dev)) { 5039 br_vlan_get_proto(br_dev, &proto); 5040 if (proto == ETH_P_8021AD) { 5041 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge"); 5042 return -EOPNOTSUPP; 5043 } 5044 } 5045 if (is_vlan_dev(upper_dev) && 5046 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 5047 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 5048 return -EOPNOTSUPP; 5049 } 5050 if (netif_is_macvlan(upper_dev) && 5051 !mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) { 5052 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 5053 return -EOPNOTSUPP; 5054 } 5055 break; 5056 case NETDEV_CHANGEUPPER: 5057 upper_dev = info->upper_dev; 5058 if (info->linking) 5059 break; 5060 if (is_vlan_dev(upper_dev)) 5061 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 5062 if (netif_is_macvlan(upper_dev)) 5063 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5064 break; 5065 } 5066 5067 return 0; 5068 } 5069 5070 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 5071 unsigned long event, void *ptr) 5072 { 5073 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 5074 struct netdev_notifier_changeupper_info *info = ptr; 5075 struct netlink_ext_ack *extack; 5076 struct net_device *upper_dev; 5077 5078 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 5079 return 0; 5080 5081 extack = netdev_notifier_info_to_extack(&info->info); 5082 upper_dev = info->upper_dev; 5083 5084 if (!netif_is_l3_master(upper_dev)) { 5085 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5086 return -EOPNOTSUPP; 5087 } 5088 5089 return 0; 5090 } 5091 5092 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 5093 struct net_device *dev, 5094 unsigned long event, void *ptr) 5095 { 5096 struct netdev_notifier_changeupper_info *cu_info; 5097 struct netdev_notifier_info *info = ptr; 5098 struct netlink_ext_ack *extack; 5099 struct net_device *upper_dev; 5100 5101 extack = netdev_notifier_info_to_extack(info); 5102 5103 switch (event) { 5104 case NETDEV_CHANGEUPPER: 5105 cu_info = container_of(info, 5106 struct netdev_notifier_changeupper_info, 5107 info); 5108 upper_dev = cu_info->upper_dev; 5109 if (!netif_is_bridge_master(upper_dev)) 5110 return 0; 5111 if (!mlxsw_sp_lower_get(upper_dev)) 5112 return 0; 5113 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5114 return -EOPNOTSUPP; 5115 if (cu_info->linking) { 5116 if (!netif_running(dev)) 5117 return 0; 5118 /* When the bridge is VLAN-aware, the VNI of the VxLAN 5119 * device needs to be mapped to a VLAN, but at this 5120 * point no VLANs are configured on the VxLAN device 5121 */ 5122 if (br_vlan_enabled(upper_dev)) 5123 return 0; 5124 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 5125 dev, 0, extack); 5126 } else { 5127 /* VLANs were already flushed, which triggered the 5128 * necessary cleanup 5129 */ 5130 if (br_vlan_enabled(upper_dev)) 5131 return 0; 5132 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5133 } 5134 break; 5135 case NETDEV_PRE_UP: 5136 upper_dev = netdev_master_upper_dev_get(dev); 5137 if (!upper_dev) 5138 return 0; 5139 if (!netif_is_bridge_master(upper_dev)) 5140 return 0; 5141 if (!mlxsw_sp_lower_get(upper_dev)) 5142 return 0; 5143 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0, 5144 extack); 5145 case NETDEV_DOWN: 5146 upper_dev = netdev_master_upper_dev_get(dev); 5147 if (!upper_dev) 5148 return 0; 5149 if (!netif_is_bridge_master(upper_dev)) 5150 return 0; 5151 if (!mlxsw_sp_lower_get(upper_dev)) 5152 return 0; 5153 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5154 break; 5155 } 5156 5157 return 0; 5158 } 5159 5160 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 5161 unsigned long event, void *ptr) 5162 { 5163 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 5164 struct mlxsw_sp_span_entry *span_entry; 5165 struct mlxsw_sp *mlxsw_sp; 5166 int err = 0; 5167 5168 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 5169 if (event == NETDEV_UNREGISTER) { 5170 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 5171 if (span_entry) 5172 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 5173 } 5174 mlxsw_sp_span_respin(mlxsw_sp); 5175 5176 if (netif_is_vxlan(dev)) 5177 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 5178 else if (mlxsw_sp_port_dev_check(dev)) 5179 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 5180 else if (netif_is_lag_master(dev)) 5181 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 5182 else if (is_vlan_dev(dev)) 5183 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 5184 else if (netif_is_bridge_master(dev)) 5185 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 5186 else if (netif_is_macvlan(dev)) 5187 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 5188 5189 return notifier_from_errno(err); 5190 } 5191 5192 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 5193 .notifier_call = mlxsw_sp_inetaddr_valid_event, 5194 }; 5195 5196 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 5197 .notifier_call = mlxsw_sp_inet6addr_valid_event, 5198 }; 5199 5200 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 5201 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 5202 {0, }, 5203 }; 5204 5205 static struct pci_driver mlxsw_sp1_pci_driver = { 5206 .name = mlxsw_sp1_driver_name, 5207 .id_table = mlxsw_sp1_pci_id_table, 5208 }; 5209 5210 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 5211 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 5212 {0, }, 5213 }; 5214 5215 static struct pci_driver mlxsw_sp2_pci_driver = { 5216 .name = mlxsw_sp2_driver_name, 5217 .id_table = mlxsw_sp2_pci_id_table, 5218 }; 5219 5220 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = { 5221 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0}, 5222 {0, }, 5223 }; 5224 5225 static struct pci_driver mlxsw_sp3_pci_driver = { 5226 .name = mlxsw_sp3_driver_name, 5227 .id_table = mlxsw_sp3_pci_id_table, 5228 }; 5229 5230 static const struct pci_device_id mlxsw_sp4_pci_id_table[] = { 5231 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4), 0}, 5232 {0, }, 5233 }; 5234 5235 static struct pci_driver mlxsw_sp4_pci_driver = { 5236 .name = mlxsw_sp4_driver_name, 5237 .id_table = mlxsw_sp4_pci_id_table, 5238 }; 5239 5240 static int __init mlxsw_sp_module_init(void) 5241 { 5242 int err; 5243 5244 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5245 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5246 5247 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5248 if (err) 5249 goto err_sp1_core_driver_register; 5250 5251 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5252 if (err) 5253 goto err_sp2_core_driver_register; 5254 5255 err = mlxsw_core_driver_register(&mlxsw_sp3_driver); 5256 if (err) 5257 goto err_sp3_core_driver_register; 5258 5259 err = mlxsw_core_driver_register(&mlxsw_sp4_driver); 5260 if (err) 5261 goto err_sp4_core_driver_register; 5262 5263 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5264 if (err) 5265 goto err_sp1_pci_driver_register; 5266 5267 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5268 if (err) 5269 goto err_sp2_pci_driver_register; 5270 5271 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver); 5272 if (err) 5273 goto err_sp3_pci_driver_register; 5274 5275 err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver); 5276 if (err) 5277 goto err_sp4_pci_driver_register; 5278 5279 return 0; 5280 5281 err_sp4_pci_driver_register: 5282 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5283 err_sp3_pci_driver_register: 5284 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5285 err_sp2_pci_driver_register: 5286 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5287 err_sp1_pci_driver_register: 5288 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5289 err_sp4_core_driver_register: 5290 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5291 err_sp3_core_driver_register: 5292 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5293 err_sp2_core_driver_register: 5294 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5295 err_sp1_core_driver_register: 5296 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5297 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5298 return err; 5299 } 5300 5301 static void __exit mlxsw_sp_module_exit(void) 5302 { 5303 mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver); 5304 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5305 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5306 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5307 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5308 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5309 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5310 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5311 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5312 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5313 } 5314 5315 module_init(mlxsw_sp_module_init); 5316 module_exit(mlxsw_sp_module_exit); 5317 5318 MODULE_LICENSE("Dual BSD/GPL"); 5319 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5320 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5321 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5322 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5323 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table); 5324 MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table); 5325 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5326 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME); 5327 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME); 5328 MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME); 5329