1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c 3 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the names of the copyright holders nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") version 2 as published by the Free 22 * Software Foundation. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/types.h> 40 #include <linux/pci.h> 41 #include <linux/netdevice.h> 42 #include <linux/etherdevice.h> 43 #include <linux/ethtool.h> 44 #include <linux/slab.h> 45 #include <linux/device.h> 46 #include <linux/skbuff.h> 47 #include <linux/if_vlan.h> 48 #include <linux/if_bridge.h> 49 #include <linux/workqueue.h> 50 #include <linux/jiffies.h> 51 #include <linux/bitops.h> 52 #include <linux/list.h> 53 #include <linux/notifier.h> 54 #include <linux/dcbnl.h> 55 #include <linux/inetdevice.h> 56 #include <linux/netlink.h> 57 #include <net/switchdev.h> 58 #include <net/pkt_cls.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/netevent.h> 61 #include <net/tc_act/tc_sample.h> 62 #include <net/addrconf.h> 63 64 #include "spectrum.h" 65 #include "pci.h" 66 #include "core.h" 67 #include "reg.h" 68 #include "port.h" 69 #include "trap.h" 70 #include "txheader.h" 71 #include "spectrum_cnt.h" 72 #include "spectrum_dpipe.h" 73 #include "spectrum_acl_flex_actions.h" 74 #include "spectrum_span.h" 75 #include "../mlxfw/mlxfw.h" 76 77 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100) 78 79 #define MLXSW_SP1_FWREV_MAJOR 13 80 #define MLXSW_SP1_FWREV_MINOR 1620 81 #define MLXSW_SP1_FWREV_SUBMINOR 192 82 83 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 84 .major = MLXSW_SP1_FWREV_MAJOR, 85 .minor = MLXSW_SP1_FWREV_MINOR, 86 .subminor = MLXSW_SP1_FWREV_SUBMINOR, 87 }; 88 89 #define MLXSW_SP1_FW_FILENAME \ 90 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 91 "." __stringify(MLXSW_SP1_FWREV_MINOR) \ 92 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2" 93 94 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum"; 95 static const char mlxsw_sp_driver_version[] = "1.0"; 96 97 /* tx_hdr_version 98 * Tx header version. 99 * Must be set to 1. 100 */ 101 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 102 103 /* tx_hdr_ctl 104 * Packet control type. 105 * 0 - Ethernet control (e.g. EMADs, LACP) 106 * 1 - Ethernet data 107 */ 108 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 109 110 /* tx_hdr_proto 111 * Packet protocol type. Must be set to 1 (Ethernet). 112 */ 113 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 114 115 /* tx_hdr_rx_is_router 116 * Packet is sent from the router. Valid for data packets only. 117 */ 118 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 119 120 /* tx_hdr_fid_valid 121 * Indicates if the 'fid' field is valid and should be used for 122 * forwarding lookup. Valid for data packets only. 123 */ 124 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 125 126 /* tx_hdr_swid 127 * Switch partition ID. Must be set to 0. 128 */ 129 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 130 131 /* tx_hdr_control_tclass 132 * Indicates if the packet should use the control TClass and not one 133 * of the data TClasses. 134 */ 135 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 136 137 /* tx_hdr_etclass 138 * Egress TClass to be used on the egress device on the egress port. 139 */ 140 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 141 142 /* tx_hdr_port_mid 143 * Destination local port for unicast packets. 144 * Destination multicast ID for multicast packets. 145 * 146 * Control packets are directed to a specific egress port, while data 147 * packets are transmitted through the CPU port (0) into the switch partition, 148 * where forwarding rules are applied. 149 */ 150 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 151 152 /* tx_hdr_fid 153 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 154 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 155 * Valid for data packets only. 156 */ 157 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 158 159 /* tx_hdr_type 160 * 0 - Data packets 161 * 6 - Control packets 162 */ 163 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 164 165 struct mlxsw_sp_mlxfw_dev { 166 struct mlxfw_dev mlxfw_dev; 167 struct mlxsw_sp *mlxsw_sp; 168 }; 169 170 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev, 171 u16 component_index, u32 *p_max_size, 172 u8 *p_align_bits, u16 *p_max_write_size) 173 { 174 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 175 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 176 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 177 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 178 int err; 179 180 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 181 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl); 182 if (err) 183 return err; 184 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, 185 p_max_write_size); 186 187 *p_align_bits = max_t(u8, *p_align_bits, 2); 188 *p_max_write_size = min_t(u16, *p_max_write_size, 189 MLXSW_REG_MCDA_MAX_DATA_LEN); 190 return 0; 191 } 192 193 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 194 { 195 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 196 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 197 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 198 char mcc_pl[MLXSW_REG_MCC_LEN]; 199 u8 control_state; 200 int err; 201 202 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 203 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 204 if (err) 205 return err; 206 207 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 208 if (control_state != MLXFW_FSM_STATE_IDLE) 209 return -EBUSY; 210 211 mlxsw_reg_mcc_pack(mcc_pl, 212 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 213 0, *fwhandle, 0); 214 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 215 } 216 217 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev, 218 u32 fwhandle, u16 component_index, 219 u32 component_size) 220 { 221 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 222 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 223 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 224 char mcc_pl[MLXSW_REG_MCC_LEN]; 225 226 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 227 component_index, fwhandle, component_size); 228 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 229 } 230 231 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev, 232 u32 fwhandle, u8 *data, u16 size, 233 u32 offset) 234 { 235 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 236 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 238 char mcda_pl[MLXSW_REG_MCDA_LEN]; 239 240 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 241 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl); 242 } 243 244 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, 245 u32 fwhandle, u16 component_index) 246 { 247 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 248 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 249 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 250 char mcc_pl[MLXSW_REG_MCC_LEN]; 251 252 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 253 component_index, fwhandle, 0); 254 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 255 } 256 257 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 258 { 259 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 260 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 261 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 262 char mcc_pl[MLXSW_REG_MCC_LEN]; 263 264 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, 265 fwhandle, 0); 266 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 267 } 268 269 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 270 enum mlxfw_fsm_state *fsm_state, 271 enum mlxfw_fsm_state_err *fsm_state_err) 272 { 273 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 274 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 275 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 276 char mcc_pl[MLXSW_REG_MCC_LEN]; 277 u8 control_state; 278 u8 error_code; 279 int err; 280 281 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 282 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 283 if (err) 284 return err; 285 286 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 287 *fsm_state = control_state; 288 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 289 MLXFW_FSM_STATE_ERR_MAX); 290 return 0; 291 } 292 293 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 294 { 295 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 296 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 297 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 298 char mcc_pl[MLXSW_REG_MCC_LEN]; 299 300 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, 301 fwhandle, 0); 302 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 303 } 304 305 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 306 { 307 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 308 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 309 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 310 char mcc_pl[MLXSW_REG_MCC_LEN]; 311 312 mlxsw_reg_mcc_pack(mcc_pl, 313 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 314 fwhandle, 0); 315 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 316 } 317 318 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = { 319 .component_query = mlxsw_sp_component_query, 320 .fsm_lock = mlxsw_sp_fsm_lock, 321 .fsm_component_update = mlxsw_sp_fsm_component_update, 322 .fsm_block_download = mlxsw_sp_fsm_block_download, 323 .fsm_component_verify = mlxsw_sp_fsm_component_verify, 324 .fsm_activate = mlxsw_sp_fsm_activate, 325 .fsm_query_state = mlxsw_sp_fsm_query_state, 326 .fsm_cancel = mlxsw_sp_fsm_cancel, 327 .fsm_release = mlxsw_sp_fsm_release 328 }; 329 330 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp, 331 const struct firmware *firmware) 332 { 333 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = { 334 .mlxfw_dev = { 335 .ops = &mlxsw_sp_mlxfw_dev_ops, 336 .psid = mlxsw_sp->bus_info->psid, 337 .psid_size = strlen(mlxsw_sp->bus_info->psid), 338 }, 339 .mlxsw_sp = mlxsw_sp 340 }; 341 342 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware); 343 } 344 345 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp) 346 { 347 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev; 348 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev; 349 const char *fw_filename = mlxsw_sp->fw_filename; 350 const struct firmware *firmware; 351 int err; 352 353 /* Don't check if driver does not require it */ 354 if (!req_rev || !fw_filename) 355 return 0; 356 357 /* Validate driver & FW are compatible */ 358 if (rev->major != req_rev->major) { 359 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 360 rev->major, req_rev->major); 361 return -EINVAL; 362 } 363 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) == 364 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor)) 365 return 0; 366 367 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n", 368 rev->major, rev->minor, rev->subminor); 369 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n", 370 fw_filename); 371 372 err = request_firmware_direct(&firmware, fw_filename, 373 mlxsw_sp->bus_info->dev); 374 if (err) { 375 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n", 376 fw_filename); 377 return err; 378 } 379 380 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 381 release_firmware(firmware); 382 return err; 383 } 384 385 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 386 unsigned int counter_index, u64 *packets, 387 u64 *bytes) 388 { 389 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 390 int err; 391 392 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 393 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 394 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 395 if (err) 396 return err; 397 if (packets) 398 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 399 if (bytes) 400 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 401 return 0; 402 } 403 404 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 405 unsigned int counter_index) 406 { 407 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 408 409 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 410 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 411 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 412 } 413 414 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 415 unsigned int *p_counter_index) 416 { 417 int err; 418 419 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 420 p_counter_index); 421 if (err) 422 return err; 423 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 424 if (err) 425 goto err_counter_clear; 426 return 0; 427 428 err_counter_clear: 429 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 430 *p_counter_index); 431 return err; 432 } 433 434 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 435 unsigned int counter_index) 436 { 437 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 438 counter_index); 439 } 440 441 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 442 const struct mlxsw_tx_info *tx_info) 443 { 444 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 445 446 memset(txhdr, 0, MLXSW_TXHDR_LEN); 447 448 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 449 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 450 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 451 mlxsw_tx_hdr_swid_set(txhdr, 0); 452 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 453 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 454 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 455 } 456 457 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 458 { 459 switch (state) { 460 case BR_STATE_FORWARDING: 461 return MLXSW_REG_SPMS_STATE_FORWARDING; 462 case BR_STATE_LEARNING: 463 return MLXSW_REG_SPMS_STATE_LEARNING; 464 case BR_STATE_LISTENING: /* fall-through */ 465 case BR_STATE_DISABLED: /* fall-through */ 466 case BR_STATE_BLOCKING: 467 return MLXSW_REG_SPMS_STATE_DISCARDING; 468 default: 469 BUG(); 470 } 471 } 472 473 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 474 u8 state) 475 { 476 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 477 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 478 char *spms_pl; 479 int err; 480 481 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 482 if (!spms_pl) 483 return -ENOMEM; 484 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 485 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 486 487 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 488 kfree(spms_pl); 489 return err; 490 } 491 492 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 493 { 494 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 495 int err; 496 497 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 498 if (err) 499 return err; 500 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 501 return 0; 502 } 503 504 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port, 505 bool enable, u32 rate) 506 { 507 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 508 char mpsc_pl[MLXSW_REG_MPSC_LEN]; 509 510 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate); 511 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl); 512 } 513 514 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 515 bool is_up) 516 { 517 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 518 char paos_pl[MLXSW_REG_PAOS_LEN]; 519 520 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 521 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 522 MLXSW_PORT_ADMIN_STATUS_DOWN); 523 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 524 } 525 526 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 527 unsigned char *addr) 528 { 529 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 530 char ppad_pl[MLXSW_REG_PPAD_LEN]; 531 532 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 533 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 534 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 535 } 536 537 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 538 { 539 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 540 unsigned char *addr = mlxsw_sp_port->dev->dev_addr; 541 542 ether_addr_copy(addr, mlxsw_sp->base_mac); 543 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port; 544 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr); 545 } 546 547 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 548 { 549 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 550 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 551 int max_mtu; 552 int err; 553 554 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 555 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 556 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 557 if (err) 558 return err; 559 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 560 561 if (mtu > max_mtu) 562 return -EINVAL; 563 564 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 565 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 566 } 567 568 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid) 569 { 570 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 571 char pspa_pl[MLXSW_REG_PSPA_LEN]; 572 573 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port); 574 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 575 } 576 577 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 578 { 579 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 580 char svpe_pl[MLXSW_REG_SVPE_LEN]; 581 582 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 583 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 584 } 585 586 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 587 bool learn_enable) 588 { 589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 590 char *spvmlr_pl; 591 int err; 592 593 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 594 if (!spvmlr_pl) 595 return -ENOMEM; 596 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 597 learn_enable); 598 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 599 kfree(spvmlr_pl); 600 return err; 601 } 602 603 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 604 u16 vid) 605 { 606 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 607 char spvid_pl[MLXSW_REG_SPVID_LEN]; 608 609 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); 610 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 611 } 612 613 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 614 bool allow) 615 { 616 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 617 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 618 619 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 620 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 621 } 622 623 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 624 { 625 int err; 626 627 if (!vid) { 628 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 629 if (err) 630 return err; 631 } else { 632 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid); 633 if (err) 634 return err; 635 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 636 if (err) 637 goto err_port_allow_untagged_set; 638 } 639 640 mlxsw_sp_port->pvid = vid; 641 return 0; 642 643 err_port_allow_untagged_set: 644 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid); 645 return err; 646 } 647 648 static int 649 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 650 { 651 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 652 char sspr_pl[MLXSW_REG_SSPR_LEN]; 653 654 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 655 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 656 } 657 658 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, 659 u8 local_port, u8 *p_module, 660 u8 *p_width, u8 *p_lane) 661 { 662 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 663 int err; 664 665 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 666 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 667 if (err) 668 return err; 669 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 670 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); 671 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 672 return 0; 673 } 674 675 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port, 676 u8 module, u8 width, u8 lane) 677 { 678 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 679 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 680 int i; 681 682 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 683 mlxsw_reg_pmlp_width_set(pmlp_pl, width); 684 for (i = 0; i < width; i++) { 685 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); 686 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ 687 } 688 689 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 690 } 691 692 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port) 693 { 694 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 695 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 696 697 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 698 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 699 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 700 } 701 702 static int mlxsw_sp_port_open(struct net_device *dev) 703 { 704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 705 int err; 706 707 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 708 if (err) 709 return err; 710 netif_start_queue(dev); 711 return 0; 712 } 713 714 static int mlxsw_sp_port_stop(struct net_device *dev) 715 { 716 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 717 718 netif_stop_queue(dev); 719 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 720 } 721 722 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 723 struct net_device *dev) 724 { 725 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 726 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 727 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 728 const struct mlxsw_tx_info tx_info = { 729 .local_port = mlxsw_sp_port->local_port, 730 .is_emad = false, 731 }; 732 u64 len; 733 int err; 734 735 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 736 return NETDEV_TX_BUSY; 737 738 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) { 739 struct sk_buff *skb_orig = skb; 740 741 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN); 742 if (!skb) { 743 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 744 dev_kfree_skb_any(skb_orig); 745 return NETDEV_TX_OK; 746 } 747 dev_consume_skb_any(skb_orig); 748 } 749 750 if (eth_skb_pad(skb)) { 751 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 752 return NETDEV_TX_OK; 753 } 754 755 mlxsw_sp_txhdr_construct(skb, &tx_info); 756 /* TX header is consumed by HW on the way so we shouldn't count its 757 * bytes as being sent. 758 */ 759 len = skb->len - MLXSW_TXHDR_LEN; 760 761 /* Due to a race we might fail here because of a full queue. In that 762 * unlikely case we simply drop the packet. 763 */ 764 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 765 766 if (!err) { 767 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 768 u64_stats_update_begin(&pcpu_stats->syncp); 769 pcpu_stats->tx_packets++; 770 pcpu_stats->tx_bytes += len; 771 u64_stats_update_end(&pcpu_stats->syncp); 772 } else { 773 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 774 dev_kfree_skb_any(skb); 775 } 776 return NETDEV_TX_OK; 777 } 778 779 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 780 { 781 } 782 783 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 784 { 785 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 786 struct sockaddr *addr = p; 787 int err; 788 789 if (!is_valid_ether_addr(addr->sa_data)) 790 return -EADDRNOTAVAIL; 791 792 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 793 if (err) 794 return err; 795 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 796 return 0; 797 } 798 799 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp, 800 int mtu) 801 { 802 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu); 803 } 804 805 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ 806 807 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 808 u16 delay) 809 { 810 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay, 811 BITS_PER_BYTE)); 812 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp, 813 mtu); 814 } 815 816 /* Maximum delay buffer needed in case of PAUSE frames, in bytes. 817 * Assumes 100m cable and maximum MTU. 818 */ 819 #define MLXSW_SP_PAUSE_DELAY 58752 820 821 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 822 u16 delay, bool pfc, bool pause) 823 { 824 if (pfc) 825 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay); 826 else if (pause) 827 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY); 828 else 829 return 0; 830 } 831 832 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres, 833 bool lossy) 834 { 835 if (lossy) 836 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size); 837 else 838 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size, 839 thres); 840 } 841 842 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, 843 u8 *prio_tc, bool pause_en, 844 struct ieee_pfc *my_pfc) 845 { 846 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 847 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0; 848 u16 delay = !!my_pfc ? my_pfc->delay : 0; 849 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 850 int i, j, err; 851 852 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0); 853 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 854 if (err) 855 return err; 856 857 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 858 bool configure = false; 859 bool pfc = false; 860 bool lossy; 861 u16 thres; 862 863 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) { 864 if (prio_tc[j] == i) { 865 pfc = pfc_en & BIT(j); 866 configure = true; 867 break; 868 } 869 } 870 871 if (!configure) 872 continue; 873 874 lossy = !(pfc || pause_en); 875 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu); 876 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc, 877 pause_en); 878 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy); 879 } 880 881 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 882 } 883 884 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, 885 int mtu, bool pause_en) 886 { 887 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0}; 888 bool dcb_en = !!mlxsw_sp_port->dcb.ets; 889 struct ieee_pfc *my_pfc; 890 u8 *prio_tc; 891 892 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc; 893 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL; 894 895 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc, 896 pause_en, my_pfc); 897 } 898 899 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 900 { 901 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 902 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 903 int err; 904 905 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en); 906 if (err) 907 return err; 908 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu); 909 if (err) 910 goto err_span_port_mtu_update; 911 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 912 if (err) 913 goto err_port_mtu_set; 914 dev->mtu = mtu; 915 return 0; 916 917 err_port_mtu_set: 918 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu); 919 err_span_port_mtu_update: 920 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 921 return err; 922 } 923 924 static int 925 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 926 struct rtnl_link_stats64 *stats) 927 { 928 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 929 struct mlxsw_sp_port_pcpu_stats *p; 930 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 931 u32 tx_dropped = 0; 932 unsigned int start; 933 int i; 934 935 for_each_possible_cpu(i) { 936 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 937 do { 938 start = u64_stats_fetch_begin_irq(&p->syncp); 939 rx_packets = p->rx_packets; 940 rx_bytes = p->rx_bytes; 941 tx_packets = p->tx_packets; 942 tx_bytes = p->tx_bytes; 943 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 944 945 stats->rx_packets += rx_packets; 946 stats->rx_bytes += rx_bytes; 947 stats->tx_packets += tx_packets; 948 stats->tx_bytes += tx_bytes; 949 /* tx_dropped is u32, updated without syncp protection. */ 950 tx_dropped += p->tx_dropped; 951 } 952 stats->tx_dropped = tx_dropped; 953 return 0; 954 } 955 956 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 957 { 958 switch (attr_id) { 959 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 960 return true; 961 } 962 963 return false; 964 } 965 966 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 967 void *sp) 968 { 969 switch (attr_id) { 970 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 971 return mlxsw_sp_port_get_sw_stats64(dev, sp); 972 } 973 974 return -EINVAL; 975 } 976 977 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 978 int prio, char *ppcnt_pl) 979 { 980 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 981 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 982 983 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 984 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 985 } 986 987 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 988 struct rtnl_link_stats64 *stats) 989 { 990 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 991 int err; 992 993 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 994 0, ppcnt_pl); 995 if (err) 996 goto out; 997 998 stats->tx_packets = 999 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 1000 stats->rx_packets = 1001 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 1002 stats->tx_bytes = 1003 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 1004 stats->rx_bytes = 1005 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 1006 stats->multicast = 1007 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 1008 1009 stats->rx_crc_errors = 1010 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 1011 stats->rx_frame_errors = 1012 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 1013 1014 stats->rx_length_errors = ( 1015 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 1016 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 1017 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 1018 1019 stats->rx_errors = (stats->rx_crc_errors + 1020 stats->rx_frame_errors + stats->rx_length_errors); 1021 1022 out: 1023 return err; 1024 } 1025 1026 static void 1027 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 1028 struct mlxsw_sp_port_xstats *xstats) 1029 { 1030 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1031 int err, i; 1032 1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 1034 ppcnt_pl); 1035 if (!err) 1036 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 1037 1038 for (i = 0; i < TC_MAX_QUEUE; i++) { 1039 err = mlxsw_sp_port_get_stats_raw(dev, 1040 MLXSW_REG_PPCNT_TC_CONG_TC, 1041 i, ppcnt_pl); 1042 if (!err) 1043 xstats->wred_drop[i] = 1044 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 1045 1046 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 1047 i, ppcnt_pl); 1048 if (err) 1049 continue; 1050 1051 xstats->backlog[i] = 1052 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 1053 xstats->tail_drop[i] = 1054 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 1055 } 1056 1057 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1058 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 1059 i, ppcnt_pl); 1060 if (err) 1061 continue; 1062 1063 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 1064 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 1065 } 1066 } 1067 1068 static void update_stats_cache(struct work_struct *work) 1069 { 1070 struct mlxsw_sp_port *mlxsw_sp_port = 1071 container_of(work, struct mlxsw_sp_port, 1072 periodic_hw_stats.update_dw.work); 1073 1074 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 1075 goto out; 1076 1077 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 1078 &mlxsw_sp_port->periodic_hw_stats.stats); 1079 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 1080 &mlxsw_sp_port->periodic_hw_stats.xstats); 1081 1082 out: 1083 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1084 MLXSW_HW_STATS_UPDATE_TIME); 1085 } 1086 1087 /* Return the stats from a cache that is updated periodically, 1088 * as this function might get called in an atomic context. 1089 */ 1090 static void 1091 mlxsw_sp_port_get_stats64(struct net_device *dev, 1092 struct rtnl_link_stats64 *stats) 1093 { 1094 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1095 1096 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 1097 } 1098 1099 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 1100 u16 vid_begin, u16 vid_end, 1101 bool is_member, bool untagged) 1102 { 1103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1104 char *spvm_pl; 1105 int err; 1106 1107 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1108 if (!spvm_pl) 1109 return -ENOMEM; 1110 1111 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1112 vid_end, is_member, untagged); 1113 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1114 kfree(spvm_pl); 1115 return err; 1116 } 1117 1118 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1119 u16 vid_end, bool is_member, bool untagged) 1120 { 1121 u16 vid, vid_e; 1122 int err; 1123 1124 for (vid = vid_begin; vid <= vid_end; 1125 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1126 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1127 vid_end); 1128 1129 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1130 is_member, untagged); 1131 if (err) 1132 return err; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port) 1139 { 1140 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1141 1142 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1143 &mlxsw_sp_port->vlans_list, list) 1144 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1145 } 1146 1147 static struct mlxsw_sp_port_vlan * 1148 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1149 { 1150 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1151 bool untagged = vid == 1; 1152 int err; 1153 1154 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1155 if (err) 1156 return ERR_PTR(err); 1157 1158 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1159 if (!mlxsw_sp_port_vlan) { 1160 err = -ENOMEM; 1161 goto err_port_vlan_alloc; 1162 } 1163 1164 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1165 mlxsw_sp_port_vlan->ref_count = 1; 1166 mlxsw_sp_port_vlan->vid = vid; 1167 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1168 1169 return mlxsw_sp_port_vlan; 1170 1171 err_port_vlan_alloc: 1172 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1173 return ERR_PTR(err); 1174 } 1175 1176 static void 1177 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1178 { 1179 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1180 u16 vid = mlxsw_sp_port_vlan->vid; 1181 1182 list_del(&mlxsw_sp_port_vlan->list); 1183 kfree(mlxsw_sp_port_vlan); 1184 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1185 } 1186 1187 struct mlxsw_sp_port_vlan * 1188 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1189 { 1190 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1191 1192 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1193 if (mlxsw_sp_port_vlan) { 1194 mlxsw_sp_port_vlan->ref_count++; 1195 return mlxsw_sp_port_vlan; 1196 } 1197 1198 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid); 1199 } 1200 1201 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1202 { 1203 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid; 1204 1205 if (--mlxsw_sp_port_vlan->ref_count != 0) 1206 return; 1207 1208 if (mlxsw_sp_port_vlan->bridge_port) 1209 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1210 else if (fid) 1211 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1212 1213 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1214 } 1215 1216 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1217 __be16 __always_unused proto, u16 vid) 1218 { 1219 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1220 1221 /* VLAN 0 is added to HW filter when device goes up, but it is 1222 * reserved in our case, so simply return. 1223 */ 1224 if (!vid) 1225 return 0; 1226 1227 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid)); 1228 } 1229 1230 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1231 __be16 __always_unused proto, u16 vid) 1232 { 1233 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1234 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1235 1236 /* VLAN 0 is removed from HW filter when device goes down, but 1237 * it is reserved in our case, so simply return. 1238 */ 1239 if (!vid) 1240 return 0; 1241 1242 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1243 if (!mlxsw_sp_port_vlan) 1244 return 0; 1245 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1246 1247 return 0; 1248 } 1249 1250 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name, 1251 size_t len) 1252 { 1253 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1254 1255 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core, 1256 mlxsw_sp_port->local_port, 1257 name, len); 1258 } 1259 1260 static struct mlxsw_sp_port_mall_tc_entry * 1261 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port, 1262 unsigned long cookie) { 1263 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1264 1265 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list) 1266 if (mall_tc_entry->cookie == cookie) 1267 return mall_tc_entry; 1268 1269 return NULL; 1270 } 1271 1272 static int 1273 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1274 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror, 1275 const struct tc_action *a, 1276 bool ingress) 1277 { 1278 enum mlxsw_sp_span_type span_type; 1279 struct net_device *to_dev; 1280 1281 to_dev = tcf_mirred_dev(a); 1282 if (!to_dev) { 1283 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n"); 1284 return -EINVAL; 1285 } 1286 1287 mirror->ingress = ingress; 1288 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1289 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type, 1290 true, &mirror->span_id); 1291 } 1292 1293 static void 1294 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1295 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror) 1296 { 1297 enum mlxsw_sp_span_type span_type; 1298 1299 span_type = mirror->ingress ? 1300 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1301 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id, 1302 span_type, true); 1303 } 1304 1305 static int 1306 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port, 1307 struct tc_cls_matchall_offload *cls, 1308 const struct tc_action *a, 1309 bool ingress) 1310 { 1311 int err; 1312 1313 if (!mlxsw_sp_port->sample) 1314 return -EOPNOTSUPP; 1315 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) { 1316 netdev_err(mlxsw_sp_port->dev, "sample already active\n"); 1317 return -EEXIST; 1318 } 1319 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) { 1320 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n"); 1321 return -EOPNOTSUPP; 1322 } 1323 1324 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group, 1325 tcf_sample_psample_group(a)); 1326 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a); 1327 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a); 1328 mlxsw_sp_port->sample->rate = tcf_sample_rate(a); 1329 1330 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a)); 1331 if (err) 1332 goto err_port_sample_set; 1333 return 0; 1334 1335 err_port_sample_set: 1336 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1337 return err; 1338 } 1339 1340 static void 1341 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port) 1342 { 1343 if (!mlxsw_sp_port->sample) 1344 return; 1345 1346 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1); 1347 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1348 } 1349 1350 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1351 struct tc_cls_matchall_offload *f, 1352 bool ingress) 1353 { 1354 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1355 __be16 protocol = f->common.protocol; 1356 const struct tc_action *a; 1357 LIST_HEAD(actions); 1358 int err; 1359 1360 if (!tcf_exts_has_one_action(f->exts)) { 1361 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n"); 1362 return -EOPNOTSUPP; 1363 } 1364 1365 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL); 1366 if (!mall_tc_entry) 1367 return -ENOMEM; 1368 mall_tc_entry->cookie = f->cookie; 1369 1370 tcf_exts_to_list(f->exts, &actions); 1371 a = list_first_entry(&actions, struct tc_action, list); 1372 1373 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) { 1374 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror; 1375 1376 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR; 1377 mirror = &mall_tc_entry->mirror; 1378 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, 1379 mirror, a, ingress); 1380 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) { 1381 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE; 1382 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f, 1383 a, ingress); 1384 } else { 1385 err = -EOPNOTSUPP; 1386 } 1387 1388 if (err) 1389 goto err_add_action; 1390 1391 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list); 1392 return 0; 1393 1394 err_add_action: 1395 kfree(mall_tc_entry); 1396 return err; 1397 } 1398 1399 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1400 struct tc_cls_matchall_offload *f) 1401 { 1402 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1403 1404 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port, 1405 f->cookie); 1406 if (!mall_tc_entry) { 1407 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n"); 1408 return; 1409 } 1410 list_del(&mall_tc_entry->list); 1411 1412 switch (mall_tc_entry->type) { 1413 case MLXSW_SP_PORT_MALL_MIRROR: 1414 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port, 1415 &mall_tc_entry->mirror); 1416 break; 1417 case MLXSW_SP_PORT_MALL_SAMPLE: 1418 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port); 1419 break; 1420 default: 1421 WARN_ON(1); 1422 } 1423 1424 kfree(mall_tc_entry); 1425 } 1426 1427 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1428 struct tc_cls_matchall_offload *f, 1429 bool ingress) 1430 { 1431 switch (f->command) { 1432 case TC_CLSMATCHALL_REPLACE: 1433 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f, 1434 ingress); 1435 case TC_CLSMATCHALL_DESTROY: 1436 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f); 1437 return 0; 1438 default: 1439 return -EOPNOTSUPP; 1440 } 1441 } 1442 1443 static int 1444 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block, 1445 struct tc_cls_flower_offload *f) 1446 { 1447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block); 1448 1449 switch (f->command) { 1450 case TC_CLSFLOWER_REPLACE: 1451 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f); 1452 case TC_CLSFLOWER_DESTROY: 1453 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f); 1454 return 0; 1455 case TC_CLSFLOWER_STATS: 1456 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f); 1457 default: 1458 return -EOPNOTSUPP; 1459 } 1460 } 1461 1462 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type, 1463 void *type_data, 1464 void *cb_priv, bool ingress) 1465 { 1466 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv; 1467 1468 switch (type) { 1469 case TC_SETUP_CLSMATCHALL: 1470 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev, 1471 type_data)) 1472 return -EOPNOTSUPP; 1473 1474 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data, 1475 ingress); 1476 case TC_SETUP_CLSFLOWER: 1477 return 0; 1478 default: 1479 return -EOPNOTSUPP; 1480 } 1481 } 1482 1483 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type, 1484 void *type_data, 1485 void *cb_priv) 1486 { 1487 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1488 cb_priv, true); 1489 } 1490 1491 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type, 1492 void *type_data, 1493 void *cb_priv) 1494 { 1495 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1496 cb_priv, false); 1497 } 1498 1499 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type, 1500 void *type_data, void *cb_priv) 1501 { 1502 struct mlxsw_sp_acl_block *acl_block = cb_priv; 1503 1504 switch (type) { 1505 case TC_SETUP_CLSMATCHALL: 1506 return 0; 1507 case TC_SETUP_CLSFLOWER: 1508 if (mlxsw_sp_acl_block_disabled(acl_block)) 1509 return -EOPNOTSUPP; 1510 1511 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data); 1512 default: 1513 return -EOPNOTSUPP; 1514 } 1515 } 1516 1517 static int 1518 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port, 1519 struct tcf_block *block, bool ingress, 1520 struct netlink_ext_ack *extack) 1521 { 1522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1523 struct mlxsw_sp_acl_block *acl_block; 1524 struct tcf_block_cb *block_cb; 1525 int err; 1526 1527 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1528 mlxsw_sp); 1529 if (!block_cb) { 1530 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net); 1531 if (!acl_block) 1532 return -ENOMEM; 1533 block_cb = __tcf_block_cb_register(block, 1534 mlxsw_sp_setup_tc_block_cb_flower, 1535 mlxsw_sp, acl_block, extack); 1536 if (IS_ERR(block_cb)) { 1537 err = PTR_ERR(block_cb); 1538 goto err_cb_register; 1539 } 1540 } else { 1541 acl_block = tcf_block_cb_priv(block_cb); 1542 } 1543 tcf_block_cb_incref(block_cb); 1544 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block, 1545 mlxsw_sp_port, ingress); 1546 if (err) 1547 goto err_block_bind; 1548 1549 if (ingress) 1550 mlxsw_sp_port->ing_acl_block = acl_block; 1551 else 1552 mlxsw_sp_port->eg_acl_block = acl_block; 1553 1554 return 0; 1555 1556 err_block_bind: 1557 if (!tcf_block_cb_decref(block_cb)) { 1558 __tcf_block_cb_unregister(block, block_cb); 1559 err_cb_register: 1560 mlxsw_sp_acl_block_destroy(acl_block); 1561 } 1562 return err; 1563 } 1564 1565 static void 1566 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port, 1567 struct tcf_block *block, bool ingress) 1568 { 1569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1570 struct mlxsw_sp_acl_block *acl_block; 1571 struct tcf_block_cb *block_cb; 1572 int err; 1573 1574 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1575 mlxsw_sp); 1576 if (!block_cb) 1577 return; 1578 1579 if (ingress) 1580 mlxsw_sp_port->ing_acl_block = NULL; 1581 else 1582 mlxsw_sp_port->eg_acl_block = NULL; 1583 1584 acl_block = tcf_block_cb_priv(block_cb); 1585 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block, 1586 mlxsw_sp_port, ingress); 1587 if (!err && !tcf_block_cb_decref(block_cb)) { 1588 __tcf_block_cb_unregister(block, block_cb); 1589 mlxsw_sp_acl_block_destroy(acl_block); 1590 } 1591 } 1592 1593 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1594 struct tc_block_offload *f) 1595 { 1596 tc_setup_cb_t *cb; 1597 bool ingress; 1598 int err; 1599 1600 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) { 1601 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig; 1602 ingress = true; 1603 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 1604 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg; 1605 ingress = false; 1606 } else { 1607 return -EOPNOTSUPP; 1608 } 1609 1610 switch (f->command) { 1611 case TC_BLOCK_BIND: 1612 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port, 1613 mlxsw_sp_port, f->extack); 1614 if (err) 1615 return err; 1616 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, 1617 f->block, ingress, 1618 f->extack); 1619 if (err) { 1620 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1621 return err; 1622 } 1623 return 0; 1624 case TC_BLOCK_UNBIND: 1625 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port, 1626 f->block, ingress); 1627 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1628 return 0; 1629 default: 1630 return -EOPNOTSUPP; 1631 } 1632 } 1633 1634 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1635 void *type_data) 1636 { 1637 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1638 1639 switch (type) { 1640 case TC_SETUP_BLOCK: 1641 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1642 case TC_SETUP_QDISC_RED: 1643 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1644 case TC_SETUP_QDISC_PRIO: 1645 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1646 default: 1647 return -EOPNOTSUPP; 1648 } 1649 } 1650 1651 1652 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1653 { 1654 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1655 1656 if (!enable) { 1657 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) || 1658 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) || 1659 !list_empty(&mlxsw_sp_port->mall_tc_list)) { 1660 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1661 return -EINVAL; 1662 } 1663 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block); 1664 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block); 1665 } else { 1666 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block); 1667 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block); 1668 } 1669 return 0; 1670 } 1671 1672 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1673 1674 static int mlxsw_sp_handle_feature(struct net_device *dev, 1675 netdev_features_t wanted_features, 1676 netdev_features_t feature, 1677 mlxsw_sp_feature_handler feature_handler) 1678 { 1679 netdev_features_t changes = wanted_features ^ dev->features; 1680 bool enable = !!(wanted_features & feature); 1681 int err; 1682 1683 if (!(changes & feature)) 1684 return 0; 1685 1686 err = feature_handler(dev, enable); 1687 if (err) { 1688 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1689 enable ? "Enable" : "Disable", &feature, err); 1690 return err; 1691 } 1692 1693 if (enable) 1694 dev->features |= feature; 1695 else 1696 dev->features &= ~feature; 1697 1698 return 0; 1699 } 1700 static int mlxsw_sp_set_features(struct net_device *dev, 1701 netdev_features_t features) 1702 { 1703 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1704 mlxsw_sp_feature_hw_tc); 1705 } 1706 1707 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1708 .ndo_open = mlxsw_sp_port_open, 1709 .ndo_stop = mlxsw_sp_port_stop, 1710 .ndo_start_xmit = mlxsw_sp_port_xmit, 1711 .ndo_setup_tc = mlxsw_sp_setup_tc, 1712 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1713 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1714 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1715 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1716 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1717 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1718 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1719 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1720 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name, 1721 .ndo_set_features = mlxsw_sp_set_features, 1722 }; 1723 1724 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev, 1725 struct ethtool_drvinfo *drvinfo) 1726 { 1727 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1728 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1729 1730 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver)); 1731 strlcpy(drvinfo->version, mlxsw_sp_driver_version, 1732 sizeof(drvinfo->version)); 1733 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 1734 "%d.%d.%d", 1735 mlxsw_sp->bus_info->fw_rev.major, 1736 mlxsw_sp->bus_info->fw_rev.minor, 1737 mlxsw_sp->bus_info->fw_rev.subminor); 1738 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name, 1739 sizeof(drvinfo->bus_info)); 1740 } 1741 1742 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev, 1743 struct ethtool_pauseparam *pause) 1744 { 1745 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1746 1747 pause->rx_pause = mlxsw_sp_port->link.rx_pause; 1748 pause->tx_pause = mlxsw_sp_port->link.tx_pause; 1749 } 1750 1751 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port, 1752 struct ethtool_pauseparam *pause) 1753 { 1754 char pfcc_pl[MLXSW_REG_PFCC_LEN]; 1755 1756 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port); 1757 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause); 1758 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause); 1759 1760 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc), 1761 pfcc_pl); 1762 } 1763 1764 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev, 1765 struct ethtool_pauseparam *pause) 1766 { 1767 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1768 bool pause_en = pause->tx_pause || pause->rx_pause; 1769 int err; 1770 1771 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) { 1772 netdev_err(dev, "PFC already enabled on port\n"); 1773 return -EINVAL; 1774 } 1775 1776 if (pause->autoneg) { 1777 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n"); 1778 return -EINVAL; 1779 } 1780 1781 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1782 if (err) { 1783 netdev_err(dev, "Failed to configure port's headroom\n"); 1784 return err; 1785 } 1786 1787 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause); 1788 if (err) { 1789 netdev_err(dev, "Failed to set PAUSE parameters\n"); 1790 goto err_port_pause_configure; 1791 } 1792 1793 mlxsw_sp_port->link.rx_pause = pause->rx_pause; 1794 mlxsw_sp_port->link.tx_pause = pause->tx_pause; 1795 1796 return 0; 1797 1798 err_port_pause_configure: 1799 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 1800 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1801 return err; 1802 } 1803 1804 struct mlxsw_sp_port_hw_stats { 1805 char str[ETH_GSTRING_LEN]; 1806 u64 (*getter)(const char *payload); 1807 bool cells_bytes; 1808 }; 1809 1810 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = { 1811 { 1812 .str = "a_frames_transmitted_ok", 1813 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get, 1814 }, 1815 { 1816 .str = "a_frames_received_ok", 1817 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get, 1818 }, 1819 { 1820 .str = "a_frame_check_sequence_errors", 1821 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get, 1822 }, 1823 { 1824 .str = "a_alignment_errors", 1825 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get, 1826 }, 1827 { 1828 .str = "a_octets_transmitted_ok", 1829 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get, 1830 }, 1831 { 1832 .str = "a_octets_received_ok", 1833 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get, 1834 }, 1835 { 1836 .str = "a_multicast_frames_xmitted_ok", 1837 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get, 1838 }, 1839 { 1840 .str = "a_broadcast_frames_xmitted_ok", 1841 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get, 1842 }, 1843 { 1844 .str = "a_multicast_frames_received_ok", 1845 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get, 1846 }, 1847 { 1848 .str = "a_broadcast_frames_received_ok", 1849 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get, 1850 }, 1851 { 1852 .str = "a_in_range_length_errors", 1853 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get, 1854 }, 1855 { 1856 .str = "a_out_of_range_length_field", 1857 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get, 1858 }, 1859 { 1860 .str = "a_frame_too_long_errors", 1861 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get, 1862 }, 1863 { 1864 .str = "a_symbol_error_during_carrier", 1865 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get, 1866 }, 1867 { 1868 .str = "a_mac_control_frames_transmitted", 1869 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get, 1870 }, 1871 { 1872 .str = "a_mac_control_frames_received", 1873 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get, 1874 }, 1875 { 1876 .str = "a_unsupported_opcodes_received", 1877 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get, 1878 }, 1879 { 1880 .str = "a_pause_mac_ctrl_frames_received", 1881 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get, 1882 }, 1883 { 1884 .str = "a_pause_mac_ctrl_frames_xmitted", 1885 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get, 1886 }, 1887 }; 1888 1889 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats) 1890 1891 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = { 1892 { 1893 .str = "rx_octets_prio", 1894 .getter = mlxsw_reg_ppcnt_rx_octets_get, 1895 }, 1896 { 1897 .str = "rx_frames_prio", 1898 .getter = mlxsw_reg_ppcnt_rx_frames_get, 1899 }, 1900 { 1901 .str = "tx_octets_prio", 1902 .getter = mlxsw_reg_ppcnt_tx_octets_get, 1903 }, 1904 { 1905 .str = "tx_frames_prio", 1906 .getter = mlxsw_reg_ppcnt_tx_frames_get, 1907 }, 1908 { 1909 .str = "rx_pause_prio", 1910 .getter = mlxsw_reg_ppcnt_rx_pause_get, 1911 }, 1912 { 1913 .str = "rx_pause_duration_prio", 1914 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get, 1915 }, 1916 { 1917 .str = "tx_pause_prio", 1918 .getter = mlxsw_reg_ppcnt_tx_pause_get, 1919 }, 1920 { 1921 .str = "tx_pause_duration_prio", 1922 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get, 1923 }, 1924 }; 1925 1926 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats) 1927 1928 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = { 1929 { 1930 .str = "tc_transmit_queue_tc", 1931 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get, 1932 .cells_bytes = true, 1933 }, 1934 { 1935 .str = "tc_no_buffer_discard_uc_tc", 1936 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get, 1937 }, 1938 }; 1939 1940 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats) 1941 1942 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \ 1943 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \ 1944 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \ 1945 IEEE_8021QAZ_MAX_TCS) 1946 1947 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio) 1948 { 1949 int i; 1950 1951 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) { 1952 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1953 mlxsw_sp_port_hw_prio_stats[i].str, prio); 1954 *p += ETH_GSTRING_LEN; 1955 } 1956 } 1957 1958 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc) 1959 { 1960 int i; 1961 1962 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) { 1963 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1964 mlxsw_sp_port_hw_tc_stats[i].str, tc); 1965 *p += ETH_GSTRING_LEN; 1966 } 1967 } 1968 1969 static void mlxsw_sp_port_get_strings(struct net_device *dev, 1970 u32 stringset, u8 *data) 1971 { 1972 u8 *p = data; 1973 int i; 1974 1975 switch (stringset) { 1976 case ETH_SS_STATS: 1977 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) { 1978 memcpy(p, mlxsw_sp_port_hw_stats[i].str, 1979 ETH_GSTRING_LEN); 1980 p += ETH_GSTRING_LEN; 1981 } 1982 1983 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 1984 mlxsw_sp_port_get_prio_strings(&p, i); 1985 1986 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 1987 mlxsw_sp_port_get_tc_strings(&p, i); 1988 1989 break; 1990 } 1991 } 1992 1993 static int mlxsw_sp_port_set_phys_id(struct net_device *dev, 1994 enum ethtool_phys_id_state state) 1995 { 1996 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1997 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1998 char mlcr_pl[MLXSW_REG_MLCR_LEN]; 1999 bool active; 2000 2001 switch (state) { 2002 case ETHTOOL_ID_ACTIVE: 2003 active = true; 2004 break; 2005 case ETHTOOL_ID_INACTIVE: 2006 active = false; 2007 break; 2008 default: 2009 return -EOPNOTSUPP; 2010 } 2011 2012 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active); 2013 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl); 2014 } 2015 2016 static int 2017 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats, 2018 int *p_len, enum mlxsw_reg_ppcnt_grp grp) 2019 { 2020 switch (grp) { 2021 case MLXSW_REG_PPCNT_IEEE_8023_CNT: 2022 *p_hw_stats = mlxsw_sp_port_hw_stats; 2023 *p_len = MLXSW_SP_PORT_HW_STATS_LEN; 2024 break; 2025 case MLXSW_REG_PPCNT_PRIO_CNT: 2026 *p_hw_stats = mlxsw_sp_port_hw_prio_stats; 2027 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2028 break; 2029 case MLXSW_REG_PPCNT_TC_CNT: 2030 *p_hw_stats = mlxsw_sp_port_hw_tc_stats; 2031 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN; 2032 break; 2033 default: 2034 WARN_ON(1); 2035 return -EOPNOTSUPP; 2036 } 2037 return 0; 2038 } 2039 2040 static void __mlxsw_sp_port_get_stats(struct net_device *dev, 2041 enum mlxsw_reg_ppcnt_grp grp, int prio, 2042 u64 *data, int data_index) 2043 { 2044 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2045 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2046 struct mlxsw_sp_port_hw_stats *hw_stats; 2047 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 2048 int i, len; 2049 int err; 2050 2051 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp); 2052 if (err) 2053 return; 2054 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl); 2055 for (i = 0; i < len; i++) { 2056 data[data_index + i] = hw_stats[i].getter(ppcnt_pl); 2057 if (!hw_stats[i].cells_bytes) 2058 continue; 2059 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp, 2060 data[data_index + i]); 2061 } 2062 } 2063 2064 static void mlxsw_sp_port_get_stats(struct net_device *dev, 2065 struct ethtool_stats *stats, u64 *data) 2066 { 2067 int i, data_index = 0; 2068 2069 /* IEEE 802.3 Counters */ 2070 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0, 2071 data, data_index); 2072 data_index = MLXSW_SP_PORT_HW_STATS_LEN; 2073 2074 /* Per-Priority Counters */ 2075 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2076 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i, 2077 data, data_index); 2078 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2079 } 2080 2081 /* Per-TC Counters */ 2082 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2083 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i, 2084 data, data_index); 2085 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN; 2086 } 2087 } 2088 2089 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset) 2090 { 2091 switch (sset) { 2092 case ETH_SS_STATS: 2093 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN; 2094 default: 2095 return -EOPNOTSUPP; 2096 } 2097 } 2098 2099 struct mlxsw_sp_port_link_mode { 2100 enum ethtool_link_mode_bit_indices mask_ethtool; 2101 u32 mask; 2102 u32 speed; 2103 }; 2104 2105 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = { 2106 { 2107 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, 2108 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2109 .speed = SPEED_100, 2110 }, 2111 { 2112 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | 2113 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX, 2114 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2115 .speed = SPEED_1000, 2116 }, 2117 { 2118 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, 2119 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2120 .speed = SPEED_10000, 2121 }, 2122 { 2123 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | 2124 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4, 2125 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2126 .speed = SPEED_10000, 2127 }, 2128 { 2129 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2130 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2131 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2132 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR, 2133 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2134 .speed = SPEED_10000, 2135 }, 2136 { 2137 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, 2138 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 2139 .speed = SPEED_20000, 2140 }, 2141 { 2142 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, 2143 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2144 .speed = SPEED_40000, 2145 }, 2146 { 2147 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, 2148 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2149 .speed = SPEED_40000, 2150 }, 2151 { 2152 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, 2153 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2154 .speed = SPEED_40000, 2155 }, 2156 { 2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, 2158 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2159 .speed = SPEED_40000, 2160 }, 2161 { 2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, 2163 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2164 .speed = SPEED_25000, 2165 }, 2166 { 2167 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, 2168 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2169 .speed = SPEED_25000, 2170 }, 2171 { 2172 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2173 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2174 .speed = SPEED_25000, 2175 }, 2176 { 2177 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2178 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2179 .speed = SPEED_25000, 2180 }, 2181 { 2182 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, 2183 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2184 .speed = SPEED_50000, 2185 }, 2186 { 2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, 2188 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2189 .speed = SPEED_50000, 2190 }, 2191 { 2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, 2193 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2194 .speed = SPEED_50000, 2195 }, 2196 { 2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2198 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, 2199 .speed = SPEED_56000, 2200 }, 2201 { 2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2203 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, 2204 .speed = SPEED_56000, 2205 }, 2206 { 2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2208 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, 2209 .speed = SPEED_56000, 2210 }, 2211 { 2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2213 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, 2214 .speed = SPEED_56000, 2215 }, 2216 { 2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, 2218 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2219 .speed = SPEED_100000, 2220 }, 2221 { 2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, 2223 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2224 .speed = SPEED_100000, 2225 }, 2226 { 2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, 2228 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2229 .speed = SPEED_100000, 2230 }, 2231 { 2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, 2233 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2234 .speed = SPEED_100000, 2235 }, 2236 }; 2237 2238 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode) 2239 2240 static void 2241 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto, 2242 struct ethtool_link_ksettings *cmd) 2243 { 2244 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2245 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2246 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2247 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2248 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2249 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2250 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2251 2252 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2253 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2254 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2255 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | 2256 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX)) 2257 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2258 } 2259 2260 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode) 2261 { 2262 int i; 2263 2264 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2265 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) 2266 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2267 mode); 2268 } 2269 } 2270 2271 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto, 2272 struct ethtool_link_ksettings *cmd) 2273 { 2274 u32 speed = SPEED_UNKNOWN; 2275 u8 duplex = DUPLEX_UNKNOWN; 2276 int i; 2277 2278 if (!carrier_ok) 2279 goto out; 2280 2281 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2282 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) { 2283 speed = mlxsw_sp_port_link_mode[i].speed; 2284 duplex = DUPLEX_FULL; 2285 break; 2286 } 2287 } 2288 out: 2289 cmd->base.speed = speed; 2290 cmd->base.duplex = duplex; 2291 } 2292 2293 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto) 2294 { 2295 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2296 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2297 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2298 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2299 return PORT_FIBRE; 2300 2301 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2302 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2303 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4)) 2304 return PORT_DA; 2305 2306 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2307 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2308 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2309 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4)) 2310 return PORT_NONE; 2311 2312 return PORT_OTHER; 2313 } 2314 2315 static u32 2316 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd) 2317 { 2318 u32 ptys_proto = 0; 2319 int i; 2320 2321 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2322 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2323 cmd->link_modes.advertising)) 2324 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2325 } 2326 return ptys_proto; 2327 } 2328 2329 static u32 mlxsw_sp_to_ptys_speed(u32 speed) 2330 { 2331 u32 ptys_proto = 0; 2332 int i; 2333 2334 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2335 if (speed == mlxsw_sp_port_link_mode[i].speed) 2336 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2337 } 2338 return ptys_proto; 2339 } 2340 2341 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed) 2342 { 2343 u32 ptys_proto = 0; 2344 int i; 2345 2346 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2347 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed) 2348 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2349 } 2350 return ptys_proto; 2351 } 2352 2353 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap, 2354 struct ethtool_link_ksettings *cmd) 2355 { 2356 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause); 2357 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 2358 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 2359 2360 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd); 2361 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported); 2362 } 2363 2364 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg, 2365 struct ethtool_link_ksettings *cmd) 2366 { 2367 if (!autoneg) 2368 return; 2369 2370 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 2371 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising); 2372 } 2373 2374 static void 2375 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status, 2376 struct ethtool_link_ksettings *cmd) 2377 { 2378 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp) 2379 return; 2380 2381 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg); 2382 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising); 2383 } 2384 2385 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev, 2386 struct ethtool_link_ksettings *cmd) 2387 { 2388 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp; 2389 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2390 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2391 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2392 u8 autoneg_status; 2393 bool autoneg; 2394 int err; 2395 2396 autoneg = mlxsw_sp_port->link.autoneg; 2397 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2398 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2399 if (err) 2400 return err; 2401 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, 2402 ð_proto_oper); 2403 2404 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd); 2405 2406 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd); 2407 2408 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl); 2409 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl); 2410 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd); 2411 2412 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 2413 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper); 2414 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper, 2415 cmd); 2416 2417 return 0; 2418 } 2419 2420 static int 2421 mlxsw_sp_port_set_link_ksettings(struct net_device *dev, 2422 const struct ethtool_link_ksettings *cmd) 2423 { 2424 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2425 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2426 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2427 u32 eth_proto_cap, eth_proto_new; 2428 bool autoneg; 2429 int err; 2430 2431 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2432 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2433 if (err) 2434 return err; 2435 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); 2436 2437 autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 2438 eth_proto_new = autoneg ? 2439 mlxsw_sp_to_ptys_advert_link(cmd) : 2440 mlxsw_sp_to_ptys_speed(cmd->base.speed); 2441 2442 eth_proto_new = eth_proto_new & eth_proto_cap; 2443 if (!eth_proto_new) { 2444 netdev_err(dev, "No supported speed requested\n"); 2445 return -EINVAL; 2446 } 2447 2448 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2449 eth_proto_new, autoneg); 2450 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2451 if (err) 2452 return err; 2453 2454 if (!netif_running(dev)) 2455 return 0; 2456 2457 mlxsw_sp_port->link.autoneg = autoneg; 2458 2459 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2460 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 2461 2462 return 0; 2463 } 2464 2465 static int mlxsw_sp_flash_device(struct net_device *dev, 2466 struct ethtool_flash *flash) 2467 { 2468 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2469 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2470 const struct firmware *firmware; 2471 int err; 2472 2473 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2474 return -EOPNOTSUPP; 2475 2476 dev_hold(dev); 2477 rtnl_unlock(); 2478 2479 err = request_firmware_direct(&firmware, flash->data, &dev->dev); 2480 if (err) 2481 goto out; 2482 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 2483 release_firmware(firmware); 2484 out: 2485 rtnl_lock(); 2486 dev_put(dev); 2487 return err; 2488 } 2489 2490 #define MLXSW_SP_I2C_ADDR_LOW 0x50 2491 #define MLXSW_SP_I2C_ADDR_HIGH 0x51 2492 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256 2493 2494 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port, 2495 u16 offset, u16 size, void *data, 2496 unsigned int *p_read_size) 2497 { 2498 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2499 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE]; 2500 char mcia_pl[MLXSW_REG_MCIA_LEN]; 2501 u16 i2c_addr; 2502 int status; 2503 int err; 2504 2505 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 2506 2507 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH && 2508 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH) 2509 /* Cross pages read, read until offset 256 in low page */ 2510 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset; 2511 2512 i2c_addr = MLXSW_SP_I2C_ADDR_LOW; 2513 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) { 2514 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH; 2515 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH; 2516 } 2517 2518 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module, 2519 0, 0, offset, size, i2c_addr); 2520 2521 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl); 2522 if (err) 2523 return err; 2524 2525 status = mlxsw_reg_mcia_status_get(mcia_pl); 2526 if (status) 2527 return -EIO; 2528 2529 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp); 2530 memcpy(data, eeprom_tmp, size); 2531 *p_read_size = size; 2532 2533 return 0; 2534 } 2535 2536 enum mlxsw_sp_eeprom_module_info_rev_id { 2537 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 2538 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 2539 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 2540 }; 2541 2542 enum mlxsw_sp_eeprom_module_info_id { 2543 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03, 2544 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 2545 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 2546 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 2547 }; 2548 2549 enum mlxsw_sp_eeprom_module_info { 2550 MLXSW_SP_EEPROM_MODULE_INFO_ID, 2551 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID, 2552 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2553 }; 2554 2555 static int mlxsw_sp_get_module_info(struct net_device *netdev, 2556 struct ethtool_modinfo *modinfo) 2557 { 2558 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2559 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE]; 2560 u8 module_rev_id, module_id; 2561 unsigned int read_size; 2562 int err; 2563 2564 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0, 2565 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2566 module_info, &read_size); 2567 if (err) 2568 return err; 2569 2570 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE) 2571 return -EIO; 2572 2573 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID]; 2574 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID]; 2575 2576 switch (module_id) { 2577 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP: 2578 modinfo->type = ETH_MODULE_SFF_8436; 2579 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2580 break; 2581 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS: 2582 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28: 2583 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 || 2584 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) { 2585 modinfo->type = ETH_MODULE_SFF_8636; 2586 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2587 } else { 2588 modinfo->type = ETH_MODULE_SFF_8436; 2589 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2590 } 2591 break; 2592 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP: 2593 modinfo->type = ETH_MODULE_SFF_8472; 2594 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2595 break; 2596 default: 2597 return -EINVAL; 2598 } 2599 2600 return 0; 2601 } 2602 2603 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev, 2604 struct ethtool_eeprom *ee, 2605 u8 *data) 2606 { 2607 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2608 int offset = ee->offset; 2609 unsigned int read_size; 2610 int i = 0; 2611 int err; 2612 2613 if (!ee->len) 2614 return -EINVAL; 2615 2616 memset(data, 0, ee->len); 2617 2618 while (i < ee->len) { 2619 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset, 2620 ee->len - i, data + i, 2621 &read_size); 2622 if (err) { 2623 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n"); 2624 return err; 2625 } 2626 2627 i += read_size; 2628 offset += read_size; 2629 } 2630 2631 return 0; 2632 } 2633 2634 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { 2635 .get_drvinfo = mlxsw_sp_port_get_drvinfo, 2636 .get_link = ethtool_op_get_link, 2637 .get_pauseparam = mlxsw_sp_port_get_pauseparam, 2638 .set_pauseparam = mlxsw_sp_port_set_pauseparam, 2639 .get_strings = mlxsw_sp_port_get_strings, 2640 .set_phys_id = mlxsw_sp_port_set_phys_id, 2641 .get_ethtool_stats = mlxsw_sp_port_get_stats, 2642 .get_sset_count = mlxsw_sp_port_get_sset_count, 2643 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings, 2644 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings, 2645 .flash_device = mlxsw_sp_flash_device, 2646 .get_module_info = mlxsw_sp_get_module_info, 2647 .get_module_eeprom = mlxsw_sp_get_module_eeprom, 2648 }; 2649 2650 static int 2651 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width) 2652 { 2653 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2654 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width; 2655 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2656 u32 eth_proto_admin; 2657 2658 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed); 2659 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2660 eth_proto_admin, mlxsw_sp_port->link.autoneg); 2661 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2662 } 2663 2664 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 2665 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 2666 bool dwrr, u8 dwrr_weight) 2667 { 2668 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2669 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2670 2671 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2672 next_index); 2673 mlxsw_reg_qeec_de_set(qeec_pl, true); 2674 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 2675 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 2676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2677 } 2678 2679 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 2680 enum mlxsw_reg_qeec_hr hr, u8 index, 2681 u8 next_index, u32 maxrate) 2682 { 2683 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2684 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2685 2686 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2687 next_index); 2688 mlxsw_reg_qeec_mase_set(qeec_pl, true); 2689 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 2690 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2691 } 2692 2693 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 2694 u8 switch_prio, u8 tclass) 2695 { 2696 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2697 char qtct_pl[MLXSW_REG_QTCT_LEN]; 2698 2699 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 2700 tclass); 2701 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 2702 } 2703 2704 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 2705 { 2706 int err, i; 2707 2708 /* Setup the elements hierarcy, so that each TC is linked to 2709 * one subgroup, which are all member in the same group. 2710 */ 2711 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2712 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false, 2713 0); 2714 if (err) 2715 return err; 2716 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2717 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2718 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i, 2719 0, false, 0); 2720 if (err) 2721 return err; 2722 } 2723 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2724 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2725 MLXSW_REG_QEEC_HIERARCY_TC, i, i, 2726 false, 0); 2727 if (err) 2728 return err; 2729 } 2730 2731 /* Make sure the max shaper is disabled in all hierarcies that 2732 * support it. 2733 */ 2734 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2735 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0, 2736 MLXSW_REG_QEEC_MAS_DIS); 2737 if (err) 2738 return err; 2739 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2740 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2741 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2742 i, 0, 2743 MLXSW_REG_QEEC_MAS_DIS); 2744 if (err) 2745 return err; 2746 } 2747 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2748 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2749 MLXSW_REG_QEEC_HIERARCY_TC, 2750 i, i, 2751 MLXSW_REG_QEEC_MAS_DIS); 2752 if (err) 2753 return err; 2754 } 2755 2756 /* Map all priorities to traffic class 0. */ 2757 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2758 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 2759 if (err) 2760 return err; 2761 } 2762 2763 return 0; 2764 } 2765 2766 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 2767 bool split, u8 module, u8 width, u8 lane) 2768 { 2769 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 2770 struct mlxsw_sp_port *mlxsw_sp_port; 2771 struct net_device *dev; 2772 int err; 2773 2774 err = mlxsw_core_port_init(mlxsw_sp->core, local_port); 2775 if (err) { 2776 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 2777 local_port); 2778 return err; 2779 } 2780 2781 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 2782 if (!dev) { 2783 err = -ENOMEM; 2784 goto err_alloc_etherdev; 2785 } 2786 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 2787 mlxsw_sp_port = netdev_priv(dev); 2788 mlxsw_sp_port->dev = dev; 2789 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 2790 mlxsw_sp_port->local_port = local_port; 2791 mlxsw_sp_port->pvid = 1; 2792 mlxsw_sp_port->split = split; 2793 mlxsw_sp_port->mapping.module = module; 2794 mlxsw_sp_port->mapping.width = width; 2795 mlxsw_sp_port->mapping.lane = lane; 2796 mlxsw_sp_port->link.autoneg = 1; 2797 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 2798 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list); 2799 2800 mlxsw_sp_port->pcpu_stats = 2801 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 2802 if (!mlxsw_sp_port->pcpu_stats) { 2803 err = -ENOMEM; 2804 goto err_alloc_stats; 2805 } 2806 2807 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample), 2808 GFP_KERNEL); 2809 if (!mlxsw_sp_port->sample) { 2810 err = -ENOMEM; 2811 goto err_alloc_sample; 2812 } 2813 2814 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 2815 &update_stats_cache); 2816 2817 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 2818 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 2819 2820 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); 2821 if (err) { 2822 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 2823 mlxsw_sp_port->local_port); 2824 goto err_port_module_map; 2825 } 2826 2827 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0); 2828 if (err) { 2829 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 2830 mlxsw_sp_port->local_port); 2831 goto err_port_swid_set; 2832 } 2833 2834 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 2835 if (err) { 2836 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 2837 mlxsw_sp_port->local_port); 2838 goto err_dev_addr_init; 2839 } 2840 2841 netif_carrier_off(dev); 2842 2843 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 2844 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2845 dev->hw_features |= NETIF_F_HW_TC; 2846 2847 dev->min_mtu = 0; 2848 dev->max_mtu = ETH_MAX_MTU; 2849 2850 /* Each packet needs to have a Tx header (metadata) on top all other 2851 * headers. 2852 */ 2853 dev->needed_headroom = MLXSW_TXHDR_LEN; 2854 2855 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 2856 if (err) { 2857 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 2858 mlxsw_sp_port->local_port); 2859 goto err_port_system_port_mapping_set; 2860 } 2861 2862 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width); 2863 if (err) { 2864 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 2865 mlxsw_sp_port->local_port); 2866 goto err_port_speed_by_width_set; 2867 } 2868 2869 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 2870 if (err) { 2871 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 2872 mlxsw_sp_port->local_port); 2873 goto err_port_mtu_set; 2874 } 2875 2876 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2877 if (err) 2878 goto err_port_admin_status_set; 2879 2880 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 2881 if (err) { 2882 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 2883 mlxsw_sp_port->local_port); 2884 goto err_port_buffers_init; 2885 } 2886 2887 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 2888 if (err) { 2889 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 2890 mlxsw_sp_port->local_port); 2891 goto err_port_ets_init; 2892 } 2893 2894 /* ETS and buffers must be initialized before DCB. */ 2895 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 2896 if (err) { 2897 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 2898 mlxsw_sp_port->local_port); 2899 goto err_port_dcb_init; 2900 } 2901 2902 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 2903 if (err) { 2904 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 2905 mlxsw_sp_port->local_port); 2906 goto err_port_fids_init; 2907 } 2908 2909 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 2910 if (err) { 2911 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 2912 mlxsw_sp_port->local_port); 2913 goto err_port_qdiscs_init; 2914 } 2915 2916 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 2917 if (IS_ERR(mlxsw_sp_port_vlan)) { 2918 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 2919 mlxsw_sp_port->local_port); 2920 err = PTR_ERR(mlxsw_sp_port_vlan); 2921 goto err_port_vlan_get; 2922 } 2923 2924 mlxsw_sp_port_switchdev_init(mlxsw_sp_port); 2925 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 2926 err = register_netdev(dev); 2927 if (err) { 2928 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 2929 mlxsw_sp_port->local_port); 2930 goto err_register_netdev; 2931 } 2932 2933 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 2934 mlxsw_sp_port, dev, module + 1, 2935 mlxsw_sp_port->split, lane / width); 2936 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 2937 return 0; 2938 2939 err_register_netdev: 2940 mlxsw_sp->ports[local_port] = NULL; 2941 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 2942 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 2943 err_port_vlan_get: 2944 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 2945 err_port_qdiscs_init: 2946 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 2947 err_port_fids_init: 2948 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 2949 err_port_dcb_init: 2950 err_port_ets_init: 2951 err_port_buffers_init: 2952 err_port_admin_status_set: 2953 err_port_mtu_set: 2954 err_port_speed_by_width_set: 2955 err_port_system_port_mapping_set: 2956 err_dev_addr_init: 2957 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 2958 err_port_swid_set: 2959 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 2960 err_port_module_map: 2961 kfree(mlxsw_sp_port->sample); 2962 err_alloc_sample: 2963 free_percpu(mlxsw_sp_port->pcpu_stats); 2964 err_alloc_stats: 2965 free_netdev(dev); 2966 err_alloc_etherdev: 2967 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 2968 return err; 2969 } 2970 2971 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 2972 { 2973 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2974 2975 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 2976 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 2977 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 2978 mlxsw_sp->ports[local_port] = NULL; 2979 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 2980 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 2981 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 2982 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 2983 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 2984 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 2985 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 2986 kfree(mlxsw_sp_port->sample); 2987 free_percpu(mlxsw_sp_port->pcpu_stats); 2988 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 2989 free_netdev(mlxsw_sp_port->dev); 2990 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 2991 } 2992 2993 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 2994 { 2995 return mlxsw_sp->ports[local_port] != NULL; 2996 } 2997 2998 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 2999 { 3000 int i; 3001 3002 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 3003 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3004 mlxsw_sp_port_remove(mlxsw_sp, i); 3005 kfree(mlxsw_sp->port_to_module); 3006 kfree(mlxsw_sp->ports); 3007 } 3008 3009 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 3010 { 3011 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 3012 u8 module, width, lane; 3013 size_t alloc_size; 3014 int i; 3015 int err; 3016 3017 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 3018 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 3019 if (!mlxsw_sp->ports) 3020 return -ENOMEM; 3021 3022 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int), 3023 GFP_KERNEL); 3024 if (!mlxsw_sp->port_to_module) { 3025 err = -ENOMEM; 3026 goto err_port_to_module_alloc; 3027 } 3028 3029 for (i = 1; i < max_ports; i++) { 3030 /* Mark as invalid */ 3031 mlxsw_sp->port_to_module[i] = -1; 3032 3033 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module, 3034 &width, &lane); 3035 if (err) 3036 goto err_port_module_info_get; 3037 if (!width) 3038 continue; 3039 mlxsw_sp->port_to_module[i] = module; 3040 err = mlxsw_sp_port_create(mlxsw_sp, i, false, 3041 module, width, lane); 3042 if (err) 3043 goto err_port_create; 3044 } 3045 return 0; 3046 3047 err_port_create: 3048 err_port_module_info_get: 3049 for (i--; i >= 1; i--) 3050 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3051 mlxsw_sp_port_remove(mlxsw_sp, i); 3052 kfree(mlxsw_sp->port_to_module); 3053 err_port_to_module_alloc: 3054 kfree(mlxsw_sp->ports); 3055 return err; 3056 } 3057 3058 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port) 3059 { 3060 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX; 3061 3062 return local_port - offset; 3063 } 3064 3065 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port, 3066 u8 module, unsigned int count) 3067 { 3068 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count; 3069 int err, i; 3070 3071 for (i = 0; i < count; i++) { 3072 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true, 3073 module, width, i * width); 3074 if (err) 3075 goto err_port_create; 3076 } 3077 3078 return 0; 3079 3080 err_port_create: 3081 for (i--; i >= 0; i--) 3082 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3083 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3084 return err; 3085 } 3086 3087 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 3088 u8 base_port, unsigned int count) 3089 { 3090 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH; 3091 int i; 3092 3093 /* Split by four means we need to re-create two ports, otherwise 3094 * only one. 3095 */ 3096 count = count / 2; 3097 3098 for (i = 0; i < count; i++) { 3099 local_port = base_port + i * 2; 3100 if (mlxsw_sp->port_to_module[local_port] < 0) 3101 continue; 3102 module = mlxsw_sp->port_to_module[local_port]; 3103 3104 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module, 3105 width, 0); 3106 } 3107 } 3108 3109 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 3110 unsigned int count, 3111 struct netlink_ext_ack *extack) 3112 { 3113 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3114 struct mlxsw_sp_port *mlxsw_sp_port; 3115 u8 module, cur_width, base_port; 3116 int i; 3117 int err; 3118 3119 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3120 if (!mlxsw_sp_port) { 3121 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3122 local_port); 3123 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3124 return -EINVAL; 3125 } 3126 3127 module = mlxsw_sp_port->mapping.module; 3128 cur_width = mlxsw_sp_port->mapping.width; 3129 3130 if (count != 2 && count != 4) { 3131 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n"); 3132 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports"); 3133 return -EINVAL; 3134 } 3135 3136 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) { 3137 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n"); 3138 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further"); 3139 return -EINVAL; 3140 } 3141 3142 /* Make sure we have enough slave (even) ports for the split. */ 3143 if (count == 2) { 3144 base_port = local_port; 3145 if (mlxsw_sp->ports[base_port + 1]) { 3146 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3147 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3148 return -EINVAL; 3149 } 3150 } else { 3151 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3152 if (mlxsw_sp->ports[base_port + 1] || 3153 mlxsw_sp->ports[base_port + 3]) { 3154 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3155 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3156 return -EINVAL; 3157 } 3158 } 3159 3160 for (i = 0; i < count; i++) 3161 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3162 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3163 3164 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count); 3165 if (err) { 3166 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 3167 goto err_port_split_create; 3168 } 3169 3170 return 0; 3171 3172 err_port_split_create: 3173 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3174 return err; 3175 } 3176 3177 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port, 3178 struct netlink_ext_ack *extack) 3179 { 3180 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3181 struct mlxsw_sp_port *mlxsw_sp_port; 3182 u8 cur_width, base_port; 3183 unsigned int count; 3184 int i; 3185 3186 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3187 if (!mlxsw_sp_port) { 3188 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3189 local_port); 3190 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3191 return -EINVAL; 3192 } 3193 3194 if (!mlxsw_sp_port->split) { 3195 netdev_err(mlxsw_sp_port->dev, "Port was not split\n"); 3196 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 3197 return -EINVAL; 3198 } 3199 3200 cur_width = mlxsw_sp_port->mapping.width; 3201 count = cur_width == 1 ? 4 : 2; 3202 3203 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3204 3205 /* Determine which ports to remove. */ 3206 if (count == 2 && local_port >= base_port + 2) 3207 base_port = base_port + 2; 3208 3209 for (i = 0; i < count; i++) 3210 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3211 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3212 3213 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3214 3215 return 0; 3216 } 3217 3218 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 3219 char *pude_pl, void *priv) 3220 { 3221 struct mlxsw_sp *mlxsw_sp = priv; 3222 struct mlxsw_sp_port *mlxsw_sp_port; 3223 enum mlxsw_reg_pude_oper_status status; 3224 u8 local_port; 3225 3226 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 3227 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3228 if (!mlxsw_sp_port) 3229 return; 3230 3231 status = mlxsw_reg_pude_oper_status_get(pude_pl); 3232 if (status == MLXSW_PORT_OPER_STATUS_UP) { 3233 netdev_info(mlxsw_sp_port->dev, "link up\n"); 3234 netif_carrier_on(mlxsw_sp_port->dev); 3235 } else { 3236 netdev_info(mlxsw_sp_port->dev, "link down\n"); 3237 netif_carrier_off(mlxsw_sp_port->dev); 3238 } 3239 } 3240 3241 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 3242 u8 local_port, void *priv) 3243 { 3244 struct mlxsw_sp *mlxsw_sp = priv; 3245 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3246 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 3247 3248 if (unlikely(!mlxsw_sp_port)) { 3249 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 3250 local_port); 3251 return; 3252 } 3253 3254 skb->dev = mlxsw_sp_port->dev; 3255 3256 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 3257 u64_stats_update_begin(&pcpu_stats->syncp); 3258 pcpu_stats->rx_packets++; 3259 pcpu_stats->rx_bytes += skb->len; 3260 u64_stats_update_end(&pcpu_stats->syncp); 3261 3262 skb->protocol = eth_type_trans(skb, skb->dev); 3263 netif_receive_skb(skb); 3264 } 3265 3266 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 3267 void *priv) 3268 { 3269 skb->offload_fwd_mark = 1; 3270 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3271 } 3272 3273 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb, 3274 u8 local_port, void *priv) 3275 { 3276 skb->offload_mr_fwd_mark = 1; 3277 skb->offload_fwd_mark = 1; 3278 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3279 } 3280 3281 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port, 3282 void *priv) 3283 { 3284 struct mlxsw_sp *mlxsw_sp = priv; 3285 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3286 struct psample_group *psample_group; 3287 u32 size; 3288 3289 if (unlikely(!mlxsw_sp_port)) { 3290 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n", 3291 local_port); 3292 goto out; 3293 } 3294 if (unlikely(!mlxsw_sp_port->sample)) { 3295 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n", 3296 local_port); 3297 goto out; 3298 } 3299 3300 size = mlxsw_sp_port->sample->truncate ? 3301 mlxsw_sp_port->sample->trunc_size : skb->len; 3302 3303 rcu_read_lock(); 3304 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group); 3305 if (!psample_group) 3306 goto out_unlock; 3307 psample_sample_packet(psample_group, skb, size, 3308 mlxsw_sp_port->dev->ifindex, 0, 3309 mlxsw_sp_port->sample->rate); 3310 out_unlock: 3311 rcu_read_unlock(); 3312 out: 3313 consume_skb(skb); 3314 } 3315 3316 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3317 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 3318 _is_ctrl, SP_##_trap_group, DISCARD) 3319 3320 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3321 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 3322 _is_ctrl, SP_##_trap_group, DISCARD) 3323 3324 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3325 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \ 3326 _is_ctrl, SP_##_trap_group, DISCARD) 3327 3328 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 3329 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 3330 3331 static const struct mlxsw_listener mlxsw_sp_listener[] = { 3332 /* Events */ 3333 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 3334 /* L2 traps */ 3335 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true), 3336 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true), 3337 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true), 3338 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false), 3339 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false), 3340 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false), 3341 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false), 3342 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false), 3343 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false), 3344 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false), 3345 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false), 3346 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false), 3347 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD, 3348 false), 3349 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3350 false), 3351 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD, 3352 false), 3353 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3354 false), 3355 /* L3 traps */ 3356 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3357 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3358 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3359 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false), 3360 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 3361 false), 3362 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false), 3363 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 3364 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false), 3365 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP, 3366 false), 3367 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false), 3368 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false), 3369 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false), 3370 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false), 3371 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false), 3372 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false), 3373 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3374 false), 3375 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3376 false), 3377 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3378 false), 3379 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3380 false), 3381 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false), 3382 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 3383 false), 3384 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false), 3385 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false), 3386 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false), 3387 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false), 3388 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3389 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3390 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3391 /* PKT Sample trap */ 3392 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU, 3393 false, SP_IP2ME, DISCARD), 3394 /* ACL trap */ 3395 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false), 3396 /* Multicast Router Traps */ 3397 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false), 3398 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false), 3399 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false), 3400 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 3401 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 3402 }; 3403 3404 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 3405 { 3406 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 3407 enum mlxsw_reg_qpcr_ir_units ir_units; 3408 int max_cpu_policers; 3409 bool is_bytes; 3410 u8 burst_size; 3411 u32 rate; 3412 int i, err; 3413 3414 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 3415 return -EIO; 3416 3417 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3418 3419 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 3420 for (i = 0; i < max_cpu_policers; i++) { 3421 is_bytes = false; 3422 switch (i) { 3423 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3425 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3426 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3427 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3428 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3429 rate = 128; 3430 burst_size = 7; 3431 break; 3432 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3433 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3434 rate = 16 * 1024; 3435 burst_size = 10; 3436 break; 3437 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3438 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3439 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3440 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3441 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3442 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3443 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3444 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3445 rate = 1024; 3446 burst_size = 7; 3447 break; 3448 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3449 is_bytes = true; 3450 rate = 4 * 1024; 3451 burst_size = 4; 3452 break; 3453 default: 3454 continue; 3455 } 3456 3457 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 3458 burst_size); 3459 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 3460 if (err) 3461 return err; 3462 } 3463 3464 return 0; 3465 } 3466 3467 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 3468 { 3469 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3470 enum mlxsw_reg_htgt_trap_group i; 3471 int max_cpu_policers; 3472 int max_trap_groups; 3473 u8 priority, tc; 3474 u16 policer_id; 3475 int err; 3476 3477 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 3478 return -EIO; 3479 3480 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 3481 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3482 3483 for (i = 0; i < max_trap_groups; i++) { 3484 policer_id = i; 3485 switch (i) { 3486 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3487 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3488 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3489 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3491 priority = 5; 3492 tc = 5; 3493 break; 3494 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3495 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3496 priority = 4; 3497 tc = 4; 3498 break; 3499 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3500 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3501 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3502 priority = 3; 3503 tc = 3; 3504 break; 3505 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3506 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3507 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3508 priority = 2; 3509 tc = 2; 3510 break; 3511 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3512 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3513 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3514 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3515 priority = 1; 3516 tc = 1; 3517 break; 3518 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 3519 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 3520 tc = MLXSW_REG_HTGT_DEFAULT_TC; 3521 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 3522 break; 3523 default: 3524 continue; 3525 } 3526 3527 if (max_cpu_policers <= policer_id && 3528 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 3529 return -EIO; 3530 3531 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 3532 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3533 if (err) 3534 return err; 3535 } 3536 3537 return 0; 3538 } 3539 3540 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 3541 { 3542 int i; 3543 int err; 3544 3545 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 3546 if (err) 3547 return err; 3548 3549 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 3550 if (err) 3551 return err; 3552 3553 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3554 err = mlxsw_core_trap_register(mlxsw_sp->core, 3555 &mlxsw_sp_listener[i], 3556 mlxsw_sp); 3557 if (err) 3558 goto err_listener_register; 3559 3560 } 3561 return 0; 3562 3563 err_listener_register: 3564 for (i--; i >= 0; i--) { 3565 mlxsw_core_trap_unregister(mlxsw_sp->core, 3566 &mlxsw_sp_listener[i], 3567 mlxsw_sp); 3568 } 3569 return err; 3570 } 3571 3572 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 3573 { 3574 int i; 3575 3576 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3577 mlxsw_core_trap_unregister(mlxsw_sp->core, 3578 &mlxsw_sp_listener[i], 3579 mlxsw_sp); 3580 } 3581 } 3582 3583 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 3584 { 3585 char slcr_pl[MLXSW_REG_SLCR_LEN]; 3586 int err; 3587 3588 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 3589 MLXSW_REG_SLCR_LAG_HASH_DMAC | 3590 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 3591 MLXSW_REG_SLCR_LAG_HASH_VLANID | 3592 MLXSW_REG_SLCR_LAG_HASH_SIP | 3593 MLXSW_REG_SLCR_LAG_HASH_DIP | 3594 MLXSW_REG_SLCR_LAG_HASH_SPORT | 3595 MLXSW_REG_SLCR_LAG_HASH_DPORT | 3596 MLXSW_REG_SLCR_LAG_HASH_IPPROTO); 3597 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 3598 if (err) 3599 return err; 3600 3601 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 3602 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 3603 return -EIO; 3604 3605 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 3606 sizeof(struct mlxsw_sp_upper), 3607 GFP_KERNEL); 3608 if (!mlxsw_sp->lags) 3609 return -ENOMEM; 3610 3611 return 0; 3612 } 3613 3614 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 3615 { 3616 kfree(mlxsw_sp->lags); 3617 } 3618 3619 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 3620 { 3621 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3622 3623 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3624 MLXSW_REG_HTGT_INVALID_POLICER, 3625 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 3626 MLXSW_REG_HTGT_DEFAULT_TC); 3627 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3628 } 3629 3630 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 3631 unsigned long event, void *ptr); 3632 3633 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 3634 const struct mlxsw_bus_info *mlxsw_bus_info) 3635 { 3636 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3637 int err; 3638 3639 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev; 3640 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME; 3641 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3642 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3643 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3644 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3645 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3646 3647 mlxsw_sp->core = mlxsw_core; 3648 mlxsw_sp->bus_info = mlxsw_bus_info; 3649 3650 err = mlxsw_sp_fw_rev_validate(mlxsw_sp); 3651 if (err) { 3652 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n"); 3653 return err; 3654 } 3655 3656 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3657 if (err) { 3658 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3659 return err; 3660 } 3661 3662 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3663 if (err) { 3664 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3665 return err; 3666 } 3667 3668 err = mlxsw_sp_fids_init(mlxsw_sp); 3669 if (err) { 3670 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3671 goto err_fids_init; 3672 } 3673 3674 err = mlxsw_sp_traps_init(mlxsw_sp); 3675 if (err) { 3676 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3677 goto err_traps_init; 3678 } 3679 3680 err = mlxsw_sp_buffers_init(mlxsw_sp); 3681 if (err) { 3682 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3683 goto err_buffers_init; 3684 } 3685 3686 err = mlxsw_sp_lag_init(mlxsw_sp); 3687 if (err) { 3688 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3689 goto err_lag_init; 3690 } 3691 3692 /* Initialize SPAN before router and switchdev, so that those components 3693 * can call mlxsw_sp_span_respin(). 3694 */ 3695 err = mlxsw_sp_span_init(mlxsw_sp); 3696 if (err) { 3697 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3698 goto err_span_init; 3699 } 3700 3701 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3702 if (err) { 3703 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3704 goto err_switchdev_init; 3705 } 3706 3707 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3708 if (err) { 3709 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3710 goto err_counter_pool_init; 3711 } 3712 3713 err = mlxsw_sp_afa_init(mlxsw_sp); 3714 if (err) { 3715 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3716 goto err_afa_init; 3717 } 3718 3719 err = mlxsw_sp_router_init(mlxsw_sp); 3720 if (err) { 3721 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3722 goto err_router_init; 3723 } 3724 3725 /* Initialize netdevice notifier after router and SPAN is initialized, 3726 * so that the event handler can use router structures and call SPAN 3727 * respin. 3728 */ 3729 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3730 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3731 if (err) { 3732 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3733 goto err_netdev_notifier; 3734 } 3735 3736 err = mlxsw_sp_acl_init(mlxsw_sp); 3737 if (err) { 3738 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3739 goto err_acl_init; 3740 } 3741 3742 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3743 if (err) { 3744 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3745 goto err_dpipe_init; 3746 } 3747 3748 err = mlxsw_sp_ports_create(mlxsw_sp); 3749 if (err) { 3750 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3751 goto err_ports_create; 3752 } 3753 3754 return 0; 3755 3756 err_ports_create: 3757 mlxsw_sp_dpipe_fini(mlxsw_sp); 3758 err_dpipe_init: 3759 mlxsw_sp_acl_fini(mlxsw_sp); 3760 err_acl_init: 3761 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3762 err_netdev_notifier: 3763 mlxsw_sp_router_fini(mlxsw_sp); 3764 err_router_init: 3765 mlxsw_sp_afa_fini(mlxsw_sp); 3766 err_afa_init: 3767 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3768 err_counter_pool_init: 3769 mlxsw_sp_switchdev_fini(mlxsw_sp); 3770 err_switchdev_init: 3771 mlxsw_sp_span_fini(mlxsw_sp); 3772 err_span_init: 3773 mlxsw_sp_lag_fini(mlxsw_sp); 3774 err_lag_init: 3775 mlxsw_sp_buffers_fini(mlxsw_sp); 3776 err_buffers_init: 3777 mlxsw_sp_traps_fini(mlxsw_sp); 3778 err_traps_init: 3779 mlxsw_sp_fids_fini(mlxsw_sp); 3780 err_fids_init: 3781 mlxsw_sp_kvdl_fini(mlxsw_sp); 3782 return err; 3783 } 3784 3785 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3786 { 3787 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3788 3789 mlxsw_sp_ports_remove(mlxsw_sp); 3790 mlxsw_sp_dpipe_fini(mlxsw_sp); 3791 mlxsw_sp_acl_fini(mlxsw_sp); 3792 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3793 mlxsw_sp_router_fini(mlxsw_sp); 3794 mlxsw_sp_afa_fini(mlxsw_sp); 3795 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3796 mlxsw_sp_switchdev_fini(mlxsw_sp); 3797 mlxsw_sp_span_fini(mlxsw_sp); 3798 mlxsw_sp_lag_fini(mlxsw_sp); 3799 mlxsw_sp_buffers_fini(mlxsw_sp); 3800 mlxsw_sp_traps_fini(mlxsw_sp); 3801 mlxsw_sp_fids_fini(mlxsw_sp); 3802 mlxsw_sp_kvdl_fini(mlxsw_sp); 3803 } 3804 3805 static const struct mlxsw_config_profile mlxsw_sp_config_profile = { 3806 .used_max_mid = 1, 3807 .max_mid = MLXSW_SP_MID_MAX, 3808 .used_flood_tables = 1, 3809 .used_flood_mode = 1, 3810 .flood_mode = 3, 3811 .max_fid_offset_flood_tables = 3, 3812 .fid_offset_flood_table_size = VLAN_N_VID - 1, 3813 .max_fid_flood_tables = 3, 3814 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 3815 .used_max_ib_mc = 1, 3816 .max_ib_mc = 0, 3817 .used_max_pkey = 1, 3818 .max_pkey = 0, 3819 .used_kvd_sizes = 1, 3820 .kvd_hash_single_parts = 59, 3821 .kvd_hash_double_parts = 41, 3822 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3823 .swid_config = { 3824 { 3825 .used_type = 1, 3826 .type = MLXSW_PORT_SWID_TYPE_ETH, 3827 } 3828 }, 3829 }; 3830 3831 static void 3832 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3833 struct devlink_resource_size_params *kvd_size_params, 3834 struct devlink_resource_size_params *linear_size_params, 3835 struct devlink_resource_size_params *hash_double_size_params, 3836 struct devlink_resource_size_params *hash_single_size_params) 3837 { 3838 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3839 KVD_SINGLE_MIN_SIZE); 3840 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3841 KVD_DOUBLE_MIN_SIZE); 3842 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3843 u32 linear_size_min = 0; 3844 3845 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3846 MLXSW_SP_KVD_GRANULARITY, 3847 DEVLINK_RESOURCE_UNIT_ENTRY); 3848 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3849 kvd_size - single_size_min - 3850 double_size_min, 3851 MLXSW_SP_KVD_GRANULARITY, 3852 DEVLINK_RESOURCE_UNIT_ENTRY); 3853 devlink_resource_size_params_init(hash_double_size_params, 3854 double_size_min, 3855 kvd_size - single_size_min - 3856 linear_size_min, 3857 MLXSW_SP_KVD_GRANULARITY, 3858 DEVLINK_RESOURCE_UNIT_ENTRY); 3859 devlink_resource_size_params_init(hash_single_size_params, 3860 single_size_min, 3861 kvd_size - double_size_min - 3862 linear_size_min, 3863 MLXSW_SP_KVD_GRANULARITY, 3864 DEVLINK_RESOURCE_UNIT_ENTRY); 3865 } 3866 3867 static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core) 3868 { 3869 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3870 struct devlink_resource_size_params hash_single_size_params; 3871 struct devlink_resource_size_params hash_double_size_params; 3872 struct devlink_resource_size_params linear_size_params; 3873 struct devlink_resource_size_params kvd_size_params; 3874 u32 kvd_size, single_size, double_size, linear_size; 3875 const struct mlxsw_config_profile *profile; 3876 int err; 3877 3878 profile = &mlxsw_sp_config_profile; 3879 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3880 return -EIO; 3881 3882 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3883 &linear_size_params, 3884 &hash_double_size_params, 3885 &hash_single_size_params); 3886 3887 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3888 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3889 kvd_size, MLXSW_SP_RESOURCE_KVD, 3890 DEVLINK_RESOURCE_ID_PARENT_TOP, 3891 &kvd_size_params); 3892 if (err) 3893 return err; 3894 3895 linear_size = profile->kvd_linear_size; 3896 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3897 linear_size, 3898 MLXSW_SP_RESOURCE_KVD_LINEAR, 3899 MLXSW_SP_RESOURCE_KVD, 3900 &linear_size_params); 3901 if (err) 3902 return err; 3903 3904 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 3905 if (err) 3906 return err; 3907 3908 double_size = kvd_size - linear_size; 3909 double_size *= profile->kvd_hash_double_parts; 3910 double_size /= profile->kvd_hash_double_parts + 3911 profile->kvd_hash_single_parts; 3912 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3913 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3914 double_size, 3915 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3916 MLXSW_SP_RESOURCE_KVD, 3917 &hash_double_size_params); 3918 if (err) 3919 return err; 3920 3921 single_size = kvd_size - double_size - linear_size; 3922 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3923 single_size, 3924 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3925 MLXSW_SP_RESOURCE_KVD, 3926 &hash_single_size_params); 3927 if (err) 3928 return err; 3929 3930 return 0; 3931 } 3932 3933 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3934 const struct mlxsw_config_profile *profile, 3935 u64 *p_single_size, u64 *p_double_size, 3936 u64 *p_linear_size) 3937 { 3938 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3939 u32 double_size; 3940 int err; 3941 3942 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3943 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3944 return -EIO; 3945 3946 /* The hash part is what left of the kvd without the 3947 * linear part. It is split to the single size and 3948 * double size by the parts ratio from the profile. 3949 * Both sizes must be a multiplications of the 3950 * granularity from the profile. In case the user 3951 * provided the sizes they are obtained via devlink. 3952 */ 3953 err = devlink_resource_size_get(devlink, 3954 MLXSW_SP_RESOURCE_KVD_LINEAR, 3955 p_linear_size); 3956 if (err) 3957 *p_linear_size = profile->kvd_linear_size; 3958 3959 err = devlink_resource_size_get(devlink, 3960 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3961 p_double_size); 3962 if (err) { 3963 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3964 *p_linear_size; 3965 double_size *= profile->kvd_hash_double_parts; 3966 double_size /= profile->kvd_hash_double_parts + 3967 profile->kvd_hash_single_parts; 3968 *p_double_size = rounddown(double_size, 3969 MLXSW_SP_KVD_GRANULARITY); 3970 } 3971 3972 err = devlink_resource_size_get(devlink, 3973 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3974 p_single_size); 3975 if (err) 3976 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3977 *p_double_size - *p_linear_size; 3978 3979 /* Check results are legal. */ 3980 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3981 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3982 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3983 return -EIO; 3984 3985 return 0; 3986 } 3987 3988 static struct mlxsw_driver mlxsw_sp_driver = { 3989 .kind = mlxsw_sp_driver_name, 3990 .priv_size = sizeof(struct mlxsw_sp), 3991 .init = mlxsw_sp_init, 3992 .fini = mlxsw_sp_fini, 3993 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3994 .port_split = mlxsw_sp_port_split, 3995 .port_unsplit = mlxsw_sp_port_unsplit, 3996 .sb_pool_get = mlxsw_sp_sb_pool_get, 3997 .sb_pool_set = mlxsw_sp_sb_pool_set, 3998 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3999 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4000 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4001 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4002 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4003 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4004 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4005 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4006 .txhdr_construct = mlxsw_sp_txhdr_construct, 4007 .resources_register = mlxsw_sp_resources_register, 4008 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 4009 .txhdr_len = MLXSW_TXHDR_LEN, 4010 .profile = &mlxsw_sp_config_profile, 4011 .res_query_enabled = true, 4012 }; 4013 4014 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 4015 { 4016 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 4017 } 4018 4019 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data) 4020 { 4021 struct mlxsw_sp_port **p_mlxsw_sp_port = data; 4022 int ret = 0; 4023 4024 if (mlxsw_sp_port_dev_check(lower_dev)) { 4025 *p_mlxsw_sp_port = netdev_priv(lower_dev); 4026 ret = 1; 4027 } 4028 4029 return ret; 4030 } 4031 4032 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4033 { 4034 struct mlxsw_sp_port *mlxsw_sp_port; 4035 4036 if (mlxsw_sp_port_dev_check(dev)) 4037 return netdev_priv(dev); 4038 4039 mlxsw_sp_port = NULL; 4040 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port); 4041 4042 return mlxsw_sp_port; 4043 } 4044 4045 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4046 { 4047 struct mlxsw_sp_port *mlxsw_sp_port; 4048 4049 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4050 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4051 } 4052 4053 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4054 { 4055 struct mlxsw_sp_port *mlxsw_sp_port; 4056 4057 if (mlxsw_sp_port_dev_check(dev)) 4058 return netdev_priv(dev); 4059 4060 mlxsw_sp_port = NULL; 4061 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4062 &mlxsw_sp_port); 4063 4064 return mlxsw_sp_port; 4065 } 4066 4067 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4068 { 4069 struct mlxsw_sp_port *mlxsw_sp_port; 4070 4071 rcu_read_lock(); 4072 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4073 if (mlxsw_sp_port) 4074 dev_hold(mlxsw_sp_port->dev); 4075 rcu_read_unlock(); 4076 return mlxsw_sp_port; 4077 } 4078 4079 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4080 { 4081 dev_put(mlxsw_sp_port->dev); 4082 } 4083 4084 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4085 { 4086 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4087 4088 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4089 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4090 } 4091 4092 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4093 { 4094 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4095 4096 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4097 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4098 } 4099 4100 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4101 u16 lag_id, u8 port_index) 4102 { 4103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4104 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4105 4106 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4107 lag_id, port_index); 4108 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4109 } 4110 4111 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4112 u16 lag_id) 4113 { 4114 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4115 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4116 4117 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4118 lag_id); 4119 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4120 } 4121 4122 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4123 u16 lag_id) 4124 { 4125 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4126 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4127 4128 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4129 lag_id); 4130 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4131 } 4132 4133 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4134 u16 lag_id) 4135 { 4136 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4137 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4138 4139 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4140 lag_id); 4141 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4142 } 4143 4144 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4145 struct net_device *lag_dev, 4146 u16 *p_lag_id) 4147 { 4148 struct mlxsw_sp_upper *lag; 4149 int free_lag_id = -1; 4150 u64 max_lag; 4151 int i; 4152 4153 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 4154 for (i = 0; i < max_lag; i++) { 4155 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4156 if (lag->ref_count) { 4157 if (lag->dev == lag_dev) { 4158 *p_lag_id = i; 4159 return 0; 4160 } 4161 } else if (free_lag_id < 0) { 4162 free_lag_id = i; 4163 } 4164 } 4165 if (free_lag_id < 0) 4166 return -EBUSY; 4167 *p_lag_id = free_lag_id; 4168 return 0; 4169 } 4170 4171 static bool 4172 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4173 struct net_device *lag_dev, 4174 struct netdev_lag_upper_info *lag_upper_info, 4175 struct netlink_ext_ack *extack) 4176 { 4177 u16 lag_id; 4178 4179 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4180 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4181 return false; 4182 } 4183 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4184 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4185 return false; 4186 } 4187 return true; 4188 } 4189 4190 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4191 u16 lag_id, u8 *p_port_index) 4192 { 4193 u64 max_lag_members; 4194 int i; 4195 4196 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4197 MAX_LAG_MEMBERS); 4198 for (i = 0; i < max_lag_members; i++) { 4199 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4200 *p_port_index = i; 4201 return 0; 4202 } 4203 } 4204 return -EBUSY; 4205 } 4206 4207 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4208 struct net_device *lag_dev) 4209 { 4210 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4211 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 4212 struct mlxsw_sp_upper *lag; 4213 u16 lag_id; 4214 u8 port_index; 4215 int err; 4216 4217 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4218 if (err) 4219 return err; 4220 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4221 if (!lag->ref_count) { 4222 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4223 if (err) 4224 return err; 4225 lag->dev = lag_dev; 4226 } 4227 4228 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4229 if (err) 4230 return err; 4231 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4232 if (err) 4233 goto err_col_port_add; 4234 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id); 4235 if (err) 4236 goto err_col_port_enable; 4237 4238 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4239 mlxsw_sp_port->local_port); 4240 mlxsw_sp_port->lag_id = lag_id; 4241 mlxsw_sp_port->lagged = 1; 4242 lag->ref_count++; 4243 4244 /* Port is no longer usable as a router interface */ 4245 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1); 4246 if (mlxsw_sp_port_vlan->fid) 4247 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 4248 4249 return 0; 4250 4251 err_col_port_enable: 4252 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4253 err_col_port_add: 4254 if (!lag->ref_count) 4255 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4256 return err; 4257 } 4258 4259 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4260 struct net_device *lag_dev) 4261 { 4262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4263 u16 lag_id = mlxsw_sp_port->lag_id; 4264 struct mlxsw_sp_upper *lag; 4265 4266 if (!mlxsw_sp_port->lagged) 4267 return; 4268 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4269 WARN_ON(lag->ref_count == 0); 4270 4271 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id); 4272 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4273 4274 /* Any VLANs configured on the port are no longer valid */ 4275 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 4276 4277 if (lag->ref_count == 1) 4278 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4279 4280 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4281 mlxsw_sp_port->local_port); 4282 mlxsw_sp_port->lagged = 0; 4283 lag->ref_count--; 4284 4285 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 4286 /* Make sure untagged frames are allowed to ingress */ 4287 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); 4288 } 4289 4290 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4291 u16 lag_id) 4292 { 4293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4294 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4295 4296 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4297 mlxsw_sp_port->local_port); 4298 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4299 } 4300 4301 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4302 u16 lag_id) 4303 { 4304 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4305 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4306 4307 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4308 mlxsw_sp_port->local_port); 4309 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4310 } 4311 4312 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port, 4313 bool lag_tx_enabled) 4314 { 4315 if (lag_tx_enabled) 4316 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, 4317 mlxsw_sp_port->lag_id); 4318 else 4319 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4320 mlxsw_sp_port->lag_id); 4321 } 4322 4323 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4324 struct netdev_lag_lower_state_info *info) 4325 { 4326 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled); 4327 } 4328 4329 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4330 bool enable) 4331 { 4332 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4333 enum mlxsw_reg_spms_state spms_state; 4334 char *spms_pl; 4335 u16 vid; 4336 int err; 4337 4338 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4339 MLXSW_REG_SPMS_STATE_DISCARDING; 4340 4341 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4342 if (!spms_pl) 4343 return -ENOMEM; 4344 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4345 4346 for (vid = 0; vid < VLAN_N_VID; vid++) 4347 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4348 4349 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4350 kfree(spms_pl); 4351 return err; 4352 } 4353 4354 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4355 { 4356 u16 vid = 1; 4357 int err; 4358 4359 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4360 if (err) 4361 return err; 4362 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4363 if (err) 4364 goto err_port_stp_set; 4365 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4366 true, false); 4367 if (err) 4368 goto err_port_vlan_set; 4369 4370 for (; vid <= VLAN_N_VID - 1; vid++) { 4371 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4372 vid, false); 4373 if (err) 4374 goto err_vid_learning_set; 4375 } 4376 4377 return 0; 4378 4379 err_vid_learning_set: 4380 for (vid--; vid >= 1; vid--) 4381 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4382 err_port_vlan_set: 4383 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4384 err_port_stp_set: 4385 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4386 return err; 4387 } 4388 4389 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4390 { 4391 u16 vid; 4392 4393 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4394 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4395 vid, true); 4396 4397 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4398 false, false); 4399 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4400 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4401 } 4402 4403 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4404 struct net_device *dev, 4405 unsigned long event, void *ptr) 4406 { 4407 struct netdev_notifier_changeupper_info *info; 4408 struct mlxsw_sp_port *mlxsw_sp_port; 4409 struct netlink_ext_ack *extack; 4410 struct net_device *upper_dev; 4411 struct mlxsw_sp *mlxsw_sp; 4412 int err = 0; 4413 4414 mlxsw_sp_port = netdev_priv(dev); 4415 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4416 info = ptr; 4417 extack = netdev_notifier_info_to_extack(&info->info); 4418 4419 switch (event) { 4420 case NETDEV_PRECHANGEUPPER: 4421 upper_dev = info->upper_dev; 4422 if (!is_vlan_dev(upper_dev) && 4423 !netif_is_lag_master(upper_dev) && 4424 !netif_is_bridge_master(upper_dev) && 4425 !netif_is_ovs_master(upper_dev) && 4426 !netif_is_macvlan(upper_dev)) { 4427 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4428 return -EINVAL; 4429 } 4430 if (!info->linking) 4431 break; 4432 if (netdev_has_any_upper_dev(upper_dev) && 4433 (!netif_is_bridge_master(upper_dev) || 4434 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4435 upper_dev))) { 4436 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4437 return -EINVAL; 4438 } 4439 if (netif_is_lag_master(upper_dev) && 4440 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4441 info->upper_info, extack)) 4442 return -EINVAL; 4443 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4444 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4445 return -EINVAL; 4446 } 4447 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4448 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4449 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4450 return -EINVAL; 4451 } 4452 if (netif_is_macvlan(upper_dev) && 4453 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) { 4454 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4455 return -EOPNOTSUPP; 4456 } 4457 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4458 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4459 return -EINVAL; 4460 } 4461 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4462 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4463 return -EINVAL; 4464 } 4465 if (is_vlan_dev(upper_dev) && 4466 vlan_dev_vlan_id(upper_dev) == 1) { 4467 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic"); 4468 return -EINVAL; 4469 } 4470 break; 4471 case NETDEV_CHANGEUPPER: 4472 upper_dev = info->upper_dev; 4473 if (netif_is_bridge_master(upper_dev)) { 4474 if (info->linking) 4475 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4476 lower_dev, 4477 upper_dev, 4478 extack); 4479 else 4480 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4481 lower_dev, 4482 upper_dev); 4483 } else if (netif_is_lag_master(upper_dev)) { 4484 if (info->linking) 4485 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4486 upper_dev); 4487 else 4488 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4489 upper_dev); 4490 } else if (netif_is_ovs_master(upper_dev)) { 4491 if (info->linking) 4492 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4493 else 4494 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4495 } else if (netif_is_macvlan(upper_dev)) { 4496 if (!info->linking) 4497 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4498 } 4499 break; 4500 } 4501 4502 return err; 4503 } 4504 4505 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4506 unsigned long event, void *ptr) 4507 { 4508 struct netdev_notifier_changelowerstate_info *info; 4509 struct mlxsw_sp_port *mlxsw_sp_port; 4510 int err; 4511 4512 mlxsw_sp_port = netdev_priv(dev); 4513 info = ptr; 4514 4515 switch (event) { 4516 case NETDEV_CHANGELOWERSTATE: 4517 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4518 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4519 info->lower_state_info); 4520 if (err) 4521 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4522 } 4523 break; 4524 } 4525 4526 return 0; 4527 } 4528 4529 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4530 struct net_device *port_dev, 4531 unsigned long event, void *ptr) 4532 { 4533 switch (event) { 4534 case NETDEV_PRECHANGEUPPER: 4535 case NETDEV_CHANGEUPPER: 4536 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4537 event, ptr); 4538 case NETDEV_CHANGELOWERSTATE: 4539 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4540 ptr); 4541 } 4542 4543 return 0; 4544 } 4545 4546 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4547 unsigned long event, void *ptr) 4548 { 4549 struct net_device *dev; 4550 struct list_head *iter; 4551 int ret; 4552 4553 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4554 if (mlxsw_sp_port_dev_check(dev)) { 4555 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4556 ptr); 4557 if (ret) 4558 return ret; 4559 } 4560 } 4561 4562 return 0; 4563 } 4564 4565 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4566 struct net_device *dev, 4567 unsigned long event, void *ptr, 4568 u16 vid) 4569 { 4570 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4571 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4572 struct netdev_notifier_changeupper_info *info = ptr; 4573 struct netlink_ext_ack *extack; 4574 struct net_device *upper_dev; 4575 int err = 0; 4576 4577 extack = netdev_notifier_info_to_extack(&info->info); 4578 4579 switch (event) { 4580 case NETDEV_PRECHANGEUPPER: 4581 upper_dev = info->upper_dev; 4582 if (!netif_is_bridge_master(upper_dev) && 4583 !netif_is_macvlan(upper_dev)) { 4584 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4585 return -EINVAL; 4586 } 4587 if (!info->linking) 4588 break; 4589 if (netdev_has_any_upper_dev(upper_dev) && 4590 (!netif_is_bridge_master(upper_dev) || 4591 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4592 upper_dev))) { 4593 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4594 return -EINVAL; 4595 } 4596 if (netif_is_macvlan(upper_dev) && 4597 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) { 4598 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4599 return -EOPNOTSUPP; 4600 } 4601 break; 4602 case NETDEV_CHANGEUPPER: 4603 upper_dev = info->upper_dev; 4604 if (netif_is_bridge_master(upper_dev)) { 4605 if (info->linking) 4606 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4607 vlan_dev, 4608 upper_dev, 4609 extack); 4610 else 4611 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4612 vlan_dev, 4613 upper_dev); 4614 } else if (netif_is_macvlan(upper_dev)) { 4615 if (!info->linking) 4616 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4617 } else { 4618 err = -EINVAL; 4619 WARN_ON(1); 4620 } 4621 break; 4622 } 4623 4624 return err; 4625 } 4626 4627 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4628 struct net_device *lag_dev, 4629 unsigned long event, 4630 void *ptr, u16 vid) 4631 { 4632 struct net_device *dev; 4633 struct list_head *iter; 4634 int ret; 4635 4636 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4637 if (mlxsw_sp_port_dev_check(dev)) { 4638 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4639 event, ptr, 4640 vid); 4641 if (ret) 4642 return ret; 4643 } 4644 } 4645 4646 return 0; 4647 } 4648 4649 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4650 unsigned long event, void *ptr) 4651 { 4652 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4653 u16 vid = vlan_dev_vlan_id(vlan_dev); 4654 4655 if (mlxsw_sp_port_dev_check(real_dev)) 4656 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 4657 event, ptr, vid); 4658 else if (netif_is_lag_master(real_dev)) 4659 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 4660 real_dev, event, 4661 ptr, vid); 4662 4663 return 0; 4664 } 4665 4666 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 4667 unsigned long event, void *ptr) 4668 { 4669 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 4670 struct netdev_notifier_changeupper_info *info = ptr; 4671 struct netlink_ext_ack *extack; 4672 struct net_device *upper_dev; 4673 4674 if (!mlxsw_sp) 4675 return 0; 4676 4677 extack = netdev_notifier_info_to_extack(&info->info); 4678 4679 switch (event) { 4680 case NETDEV_PRECHANGEUPPER: 4681 upper_dev = info->upper_dev; 4682 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) { 4683 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4684 return -EOPNOTSUPP; 4685 } 4686 if (!info->linking) 4687 break; 4688 if (netif_is_macvlan(upper_dev) && 4689 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) { 4690 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4691 return -EOPNOTSUPP; 4692 } 4693 break; 4694 case NETDEV_CHANGEUPPER: 4695 upper_dev = info->upper_dev; 4696 if (info->linking) 4697 break; 4698 if (netif_is_macvlan(upper_dev)) 4699 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4700 break; 4701 } 4702 4703 return 0; 4704 } 4705 4706 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 4707 unsigned long event, void *ptr) 4708 { 4709 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 4710 struct netdev_notifier_changeupper_info *info = ptr; 4711 struct netlink_ext_ack *extack; 4712 4713 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 4714 return 0; 4715 4716 extack = netdev_notifier_info_to_extack(&info->info); 4717 4718 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */ 4719 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4720 4721 return -EOPNOTSUPP; 4722 } 4723 4724 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 4725 { 4726 struct netdev_notifier_changeupper_info *info = ptr; 4727 4728 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 4729 return false; 4730 return netif_is_l3_master(info->upper_dev); 4731 } 4732 4733 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 4734 unsigned long event, void *ptr) 4735 { 4736 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4737 struct mlxsw_sp_span_entry *span_entry; 4738 struct mlxsw_sp *mlxsw_sp; 4739 int err = 0; 4740 4741 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 4742 if (event == NETDEV_UNREGISTER) { 4743 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 4744 if (span_entry) 4745 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 4746 } 4747 mlxsw_sp_span_respin(mlxsw_sp); 4748 4749 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 4750 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 4751 event, ptr); 4752 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 4753 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 4754 event, ptr); 4755 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU) 4756 err = mlxsw_sp_netdevice_router_port_event(dev); 4757 else if (mlxsw_sp_is_vrf_event(event, ptr)) 4758 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 4759 else if (mlxsw_sp_port_dev_check(dev)) 4760 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 4761 else if (netif_is_lag_master(dev)) 4762 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 4763 else if (is_vlan_dev(dev)) 4764 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 4765 else if (netif_is_bridge_master(dev)) 4766 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 4767 else if (netif_is_macvlan(dev)) 4768 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 4769 4770 return notifier_from_errno(err); 4771 } 4772 4773 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 4774 .notifier_call = mlxsw_sp_inetaddr_valid_event, 4775 }; 4776 4777 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = { 4778 .notifier_call = mlxsw_sp_inetaddr_event, 4779 }; 4780 4781 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 4782 .notifier_call = mlxsw_sp_inet6addr_valid_event, 4783 }; 4784 4785 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = { 4786 .notifier_call = mlxsw_sp_inet6addr_event, 4787 }; 4788 4789 static const struct pci_device_id mlxsw_sp_pci_id_table[] = { 4790 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 4791 {0, }, 4792 }; 4793 4794 static struct pci_driver mlxsw_sp_pci_driver = { 4795 .name = mlxsw_sp_driver_name, 4796 .id_table = mlxsw_sp_pci_id_table, 4797 }; 4798 4799 static int __init mlxsw_sp_module_init(void) 4800 { 4801 int err; 4802 4803 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4804 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4805 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4806 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4807 4808 err = mlxsw_core_driver_register(&mlxsw_sp_driver); 4809 if (err) 4810 goto err_core_driver_register; 4811 4812 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver); 4813 if (err) 4814 goto err_pci_driver_register; 4815 4816 return 0; 4817 4818 err_pci_driver_register: 4819 mlxsw_core_driver_unregister(&mlxsw_sp_driver); 4820 err_core_driver_register: 4821 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4822 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4823 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4824 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4825 return err; 4826 } 4827 4828 static void __exit mlxsw_sp_module_exit(void) 4829 { 4830 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver); 4831 mlxsw_core_driver_unregister(&mlxsw_sp_driver); 4832 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4833 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4834 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4835 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4836 } 4837 4838 module_init(mlxsw_sp_module_init); 4839 module_exit(mlxsw_sp_module_exit); 4840 4841 MODULE_LICENSE("Dual BSD/GPL"); 4842 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 4843 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 4844 MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table); 4845 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 4846