1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the names of the copyright holders nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") version 2 as published by the Free 22 * Software Foundation. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/types.h> 40 #include <linux/pci.h> 41 #include <linux/netdevice.h> 42 #include <linux/etherdevice.h> 43 #include <linux/ethtool.h> 44 #include <linux/slab.h> 45 #include <linux/device.h> 46 #include <linux/skbuff.h> 47 #include <linux/if_vlan.h> 48 #include <linux/if_bridge.h> 49 #include <linux/workqueue.h> 50 #include <linux/jiffies.h> 51 #include <linux/bitops.h> 52 #include <linux/list.h> 53 #include <linux/notifier.h> 54 #include <linux/dcbnl.h> 55 #include <linux/inetdevice.h> 56 #include <linux/netlink.h> 57 #include <net/switchdev.h> 58 #include <net/pkt_cls.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/netevent.h> 61 #include <net/tc_act/tc_sample.h> 62 #include <net/addrconf.h> 63 64 #include "spectrum.h" 65 #include "pci.h" 66 #include "core.h" 67 #include "reg.h" 68 #include "port.h" 69 #include "trap.h" 70 #include "txheader.h" 71 #include "spectrum_cnt.h" 72 #include "spectrum_dpipe.h" 73 #include "spectrum_acl_flex_actions.h" 74 #include "spectrum_span.h" 75 #include "../mlxfw/mlxfw.h" 76 77 #define MLXSW_FWREV_MAJOR 13 78 #define MLXSW_FWREV_MINOR 1530 79 #define MLXSW_FWREV_SUBMINOR 152 80 #define MLXSW_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100) 81 82 #define MLXSW_SP_FW_FILENAME \ 83 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \ 84 "." __stringify(MLXSW_FWREV_MINOR) \ 85 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2" 86 87 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum"; 88 static const char mlxsw_sp_driver_version[] = "1.0"; 89 90 /* tx_hdr_version 91 * Tx header version. 92 * Must be set to 1. 93 */ 94 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 95 96 /* tx_hdr_ctl 97 * Packet control type. 98 * 0 - Ethernet control (e.g. EMADs, LACP) 99 * 1 - Ethernet data 100 */ 101 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 102 103 /* tx_hdr_proto 104 * Packet protocol type. Must be set to 1 (Ethernet). 105 */ 106 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 107 108 /* tx_hdr_rx_is_router 109 * Packet is sent from the router. Valid for data packets only. 110 */ 111 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 112 113 /* tx_hdr_fid_valid 114 * Indicates if the 'fid' field is valid and should be used for 115 * forwarding lookup. Valid for data packets only. 116 */ 117 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 118 119 /* tx_hdr_swid 120 * Switch partition ID. Must be set to 0. 121 */ 122 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 123 124 /* tx_hdr_control_tclass 125 * Indicates if the packet should use the control TClass and not one 126 * of the data TClasses. 127 */ 128 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 129 130 /* tx_hdr_etclass 131 * Egress TClass to be used on the egress device on the egress port. 132 */ 133 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 134 135 /* tx_hdr_port_mid 136 * Destination local port for unicast packets. 137 * Destination multicast ID for multicast packets. 138 * 139 * Control packets are directed to a specific egress port, while data 140 * packets are transmitted through the CPU port (0) into the switch partition, 141 * where forwarding rules are applied. 142 */ 143 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 144 145 /* tx_hdr_fid 146 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 147 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 148 * Valid for data packets only. 149 */ 150 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 151 152 /* tx_hdr_type 153 * 0 - Data packets 154 * 6 - Control packets 155 */ 156 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 157 158 struct mlxsw_sp_mlxfw_dev { 159 struct mlxfw_dev mlxfw_dev; 160 struct mlxsw_sp *mlxsw_sp; 161 }; 162 163 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev, 164 u16 component_index, u32 *p_max_size, 165 u8 *p_align_bits, u16 *p_max_write_size) 166 { 167 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 168 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 169 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 170 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 171 int err; 172 173 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl); 175 if (err) 176 return err; 177 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, 178 p_max_write_size); 179 180 *p_align_bits = max_t(u8, *p_align_bits, 2); 181 *p_max_write_size = min_t(u16, *p_max_write_size, 182 MLXSW_REG_MCDA_MAX_DATA_LEN); 183 return 0; 184 } 185 186 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 187 { 188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 191 char mcc_pl[MLXSW_REG_MCC_LEN]; 192 u8 control_state; 193 int err; 194 195 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 196 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 197 if (err) 198 return err; 199 200 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 201 if (control_state != MLXFW_FSM_STATE_IDLE) 202 return -EBUSY; 203 204 mlxsw_reg_mcc_pack(mcc_pl, 205 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 206 0, *fwhandle, 0); 207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 208 } 209 210 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev, 211 u32 fwhandle, u16 component_index, 212 u32 component_size) 213 { 214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 217 char mcc_pl[MLXSW_REG_MCC_LEN]; 218 219 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 220 component_index, fwhandle, component_size); 221 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 222 } 223 224 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev, 225 u32 fwhandle, u8 *data, u16 size, 226 u32 offset) 227 { 228 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 229 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 231 char mcda_pl[MLXSW_REG_MCDA_LEN]; 232 233 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl); 235 } 236 237 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, 238 u32 fwhandle, u16 component_index) 239 { 240 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 241 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 242 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 243 char mcc_pl[MLXSW_REG_MCC_LEN]; 244 245 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 246 component_index, fwhandle, 0); 247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 248 } 249 250 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 251 { 252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 255 char mcc_pl[MLXSW_REG_MCC_LEN]; 256 257 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, 258 fwhandle, 0); 259 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 260 } 261 262 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 263 enum mlxfw_fsm_state *fsm_state, 264 enum mlxfw_fsm_state_err *fsm_state_err) 265 { 266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 269 char mcc_pl[MLXSW_REG_MCC_LEN]; 270 u8 control_state; 271 u8 error_code; 272 int err; 273 274 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 275 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 276 if (err) 277 return err; 278 279 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 280 *fsm_state = control_state; 281 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 282 MLXFW_FSM_STATE_ERR_MAX); 283 return 0; 284 } 285 286 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 287 { 288 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 289 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 291 char mcc_pl[MLXSW_REG_MCC_LEN]; 292 293 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, 294 fwhandle, 0); 295 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 296 } 297 298 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 299 { 300 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 301 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 303 char mcc_pl[MLXSW_REG_MCC_LEN]; 304 305 mlxsw_reg_mcc_pack(mcc_pl, 306 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 307 fwhandle, 0); 308 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 309 } 310 311 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = { 312 .component_query = mlxsw_sp_component_query, 313 .fsm_lock = mlxsw_sp_fsm_lock, 314 .fsm_component_update = mlxsw_sp_fsm_component_update, 315 .fsm_block_download = mlxsw_sp_fsm_block_download, 316 .fsm_component_verify = mlxsw_sp_fsm_component_verify, 317 .fsm_activate = mlxsw_sp_fsm_activate, 318 .fsm_query_state = mlxsw_sp_fsm_query_state, 319 .fsm_cancel = mlxsw_sp_fsm_cancel, 320 .fsm_release = mlxsw_sp_fsm_release 321 }; 322 323 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp, 324 const struct firmware *firmware) 325 { 326 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = { 327 .mlxfw_dev = { 328 .ops = &mlxsw_sp_mlxfw_dev_ops, 329 .psid = mlxsw_sp->bus_info->psid, 330 .psid_size = strlen(mlxsw_sp->bus_info->psid), 331 }, 332 .mlxsw_sp = mlxsw_sp 333 }; 334 335 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware); 336 } 337 338 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp) 339 { 340 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev; 341 const struct firmware *firmware; 342 int err; 343 344 /* Validate driver & FW are compatible */ 345 if (rev->major != MLXSW_FWREV_MAJOR) { 346 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 347 rev->major, MLXSW_FWREV_MAJOR); 348 return -EINVAL; 349 } 350 if (MLXSW_FWREV_MINOR_TO_BRANCH(rev->minor) == 351 MLXSW_FWREV_MINOR_TO_BRANCH(MLXSW_FWREV_MINOR)) 352 return 0; 353 354 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n", 355 rev->major, rev->minor, rev->subminor); 356 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n", 357 MLXSW_SP_FW_FILENAME); 358 359 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME, 360 mlxsw_sp->bus_info->dev); 361 if (err) { 362 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n", 363 MLXSW_SP_FW_FILENAME); 364 return err; 365 } 366 367 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 368 release_firmware(firmware); 369 return err; 370 } 371 372 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 373 unsigned int counter_index, u64 *packets, 374 u64 *bytes) 375 { 376 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 377 int err; 378 379 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 380 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 381 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 382 if (err) 383 return err; 384 if (packets) 385 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 386 if (bytes) 387 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 388 return 0; 389 } 390 391 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 392 unsigned int counter_index) 393 { 394 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 395 396 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 397 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 398 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 399 } 400 401 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 402 unsigned int *p_counter_index) 403 { 404 int err; 405 406 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 407 p_counter_index); 408 if (err) 409 return err; 410 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 411 if (err) 412 goto err_counter_clear; 413 return 0; 414 415 err_counter_clear: 416 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 417 *p_counter_index); 418 return err; 419 } 420 421 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 422 unsigned int counter_index) 423 { 424 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 425 counter_index); 426 } 427 428 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 429 const struct mlxsw_tx_info *tx_info) 430 { 431 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 432 433 memset(txhdr, 0, MLXSW_TXHDR_LEN); 434 435 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 436 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 437 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 438 mlxsw_tx_hdr_swid_set(txhdr, 0); 439 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 440 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 441 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 442 } 443 444 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 445 u8 state) 446 { 447 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 448 enum mlxsw_reg_spms_state spms_state; 449 char *spms_pl; 450 int err; 451 452 switch (state) { 453 case BR_STATE_FORWARDING: 454 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING; 455 break; 456 case BR_STATE_LEARNING: 457 spms_state = MLXSW_REG_SPMS_STATE_LEARNING; 458 break; 459 case BR_STATE_LISTENING: /* fall-through */ 460 case BR_STATE_DISABLED: /* fall-through */ 461 case BR_STATE_BLOCKING: 462 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING; 463 break; 464 default: 465 BUG(); 466 } 467 468 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 469 if (!spms_pl) 470 return -ENOMEM; 471 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 472 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 473 474 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 475 kfree(spms_pl); 476 return err; 477 } 478 479 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 480 { 481 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 482 int err; 483 484 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 485 if (err) 486 return err; 487 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 488 return 0; 489 } 490 491 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port, 492 bool enable, u32 rate) 493 { 494 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 495 char mpsc_pl[MLXSW_REG_MPSC_LEN]; 496 497 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate); 498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl); 499 } 500 501 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 502 bool is_up) 503 { 504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 505 char paos_pl[MLXSW_REG_PAOS_LEN]; 506 507 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 508 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 509 MLXSW_PORT_ADMIN_STATUS_DOWN); 510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 511 } 512 513 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 514 unsigned char *addr) 515 { 516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 517 char ppad_pl[MLXSW_REG_PPAD_LEN]; 518 519 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 520 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 521 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 522 } 523 524 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 525 { 526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 527 unsigned char *addr = mlxsw_sp_port->dev->dev_addr; 528 529 ether_addr_copy(addr, mlxsw_sp->base_mac); 530 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port; 531 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr); 532 } 533 534 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 535 { 536 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 537 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 538 int max_mtu; 539 int err; 540 541 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 542 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 543 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 544 if (err) 545 return err; 546 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 547 548 if (mtu > max_mtu) 549 return -EINVAL; 550 551 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 553 } 554 555 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid) 556 { 557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 558 char pspa_pl[MLXSW_REG_PSPA_LEN]; 559 560 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port); 561 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 562 } 563 564 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 565 { 566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 567 char svpe_pl[MLXSW_REG_SVPE_LEN]; 568 569 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 571 } 572 573 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 574 bool learn_enable) 575 { 576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 577 char *spvmlr_pl; 578 int err; 579 580 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 581 if (!spvmlr_pl) 582 return -ENOMEM; 583 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 584 learn_enable); 585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 586 kfree(spvmlr_pl); 587 return err; 588 } 589 590 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 591 u16 vid) 592 { 593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 594 char spvid_pl[MLXSW_REG_SPVID_LEN]; 595 596 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); 597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 598 } 599 600 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 601 bool allow) 602 { 603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 604 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 605 606 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 608 } 609 610 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 611 { 612 int err; 613 614 if (!vid) { 615 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 616 if (err) 617 return err; 618 } else { 619 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid); 620 if (err) 621 return err; 622 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 623 if (err) 624 goto err_port_allow_untagged_set; 625 } 626 627 mlxsw_sp_port->pvid = vid; 628 return 0; 629 630 err_port_allow_untagged_set: 631 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid); 632 return err; 633 } 634 635 static int 636 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 637 { 638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 639 char sspr_pl[MLXSW_REG_SSPR_LEN]; 640 641 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 643 } 644 645 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, 646 u8 local_port, u8 *p_module, 647 u8 *p_width, u8 *p_lane) 648 { 649 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 650 int err; 651 652 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 653 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 654 if (err) 655 return err; 656 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 657 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); 658 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 659 return 0; 660 } 661 662 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port, 663 u8 module, u8 width, u8 lane) 664 { 665 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 666 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 667 int i; 668 669 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 670 mlxsw_reg_pmlp_width_set(pmlp_pl, width); 671 for (i = 0; i < width; i++) { 672 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); 673 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ 674 } 675 676 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 677 } 678 679 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port) 680 { 681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 682 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 683 684 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 685 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 686 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 687 } 688 689 static int mlxsw_sp_port_open(struct net_device *dev) 690 { 691 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 692 int err; 693 694 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 695 if (err) 696 return err; 697 netif_start_queue(dev); 698 return 0; 699 } 700 701 static int mlxsw_sp_port_stop(struct net_device *dev) 702 { 703 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 704 705 netif_stop_queue(dev); 706 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 707 } 708 709 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 710 struct net_device *dev) 711 { 712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 713 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 714 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 715 const struct mlxsw_tx_info tx_info = { 716 .local_port = mlxsw_sp_port->local_port, 717 .is_emad = false, 718 }; 719 u64 len; 720 int err; 721 722 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 723 return NETDEV_TX_BUSY; 724 725 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) { 726 struct sk_buff *skb_orig = skb; 727 728 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN); 729 if (!skb) { 730 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 731 dev_kfree_skb_any(skb_orig); 732 return NETDEV_TX_OK; 733 } 734 dev_consume_skb_any(skb_orig); 735 } 736 737 if (eth_skb_pad(skb)) { 738 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 739 return NETDEV_TX_OK; 740 } 741 742 mlxsw_sp_txhdr_construct(skb, &tx_info); 743 /* TX header is consumed by HW on the way so we shouldn't count its 744 * bytes as being sent. 745 */ 746 len = skb->len - MLXSW_TXHDR_LEN; 747 748 /* Due to a race we might fail here because of a full queue. In that 749 * unlikely case we simply drop the packet. 750 */ 751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 752 753 if (!err) { 754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 755 u64_stats_update_begin(&pcpu_stats->syncp); 756 pcpu_stats->tx_packets++; 757 pcpu_stats->tx_bytes += len; 758 u64_stats_update_end(&pcpu_stats->syncp); 759 } else { 760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 761 dev_kfree_skb_any(skb); 762 } 763 return NETDEV_TX_OK; 764 } 765 766 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 767 { 768 } 769 770 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 771 { 772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 773 struct sockaddr *addr = p; 774 int err; 775 776 if (!is_valid_ether_addr(addr->sa_data)) 777 return -EADDRNOTAVAIL; 778 779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 780 if (err) 781 return err; 782 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 783 return 0; 784 } 785 786 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp, 787 int mtu) 788 { 789 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu); 790 } 791 792 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ 793 794 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 795 u16 delay) 796 { 797 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay, 798 BITS_PER_BYTE)); 799 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp, 800 mtu); 801 } 802 803 /* Maximum delay buffer needed in case of PAUSE frames, in bytes. 804 * Assumes 100m cable and maximum MTU. 805 */ 806 #define MLXSW_SP_PAUSE_DELAY 58752 807 808 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 809 u16 delay, bool pfc, bool pause) 810 { 811 if (pfc) 812 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay); 813 else if (pause) 814 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY); 815 else 816 return 0; 817 } 818 819 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres, 820 bool lossy) 821 { 822 if (lossy) 823 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size); 824 else 825 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size, 826 thres); 827 } 828 829 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, 830 u8 *prio_tc, bool pause_en, 831 struct ieee_pfc *my_pfc) 832 { 833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 834 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0; 835 u16 delay = !!my_pfc ? my_pfc->delay : 0; 836 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 837 int i, j, err; 838 839 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0); 840 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 841 if (err) 842 return err; 843 844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 845 bool configure = false; 846 bool pfc = false; 847 bool lossy; 848 u16 thres; 849 850 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) { 851 if (prio_tc[j] == i) { 852 pfc = pfc_en & BIT(j); 853 configure = true; 854 break; 855 } 856 } 857 858 if (!configure) 859 continue; 860 861 lossy = !(pfc || pause_en); 862 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu); 863 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc, 864 pause_en); 865 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy); 866 } 867 868 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 869 } 870 871 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, 872 int mtu, bool pause_en) 873 { 874 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0}; 875 bool dcb_en = !!mlxsw_sp_port->dcb.ets; 876 struct ieee_pfc *my_pfc; 877 u8 *prio_tc; 878 879 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc; 880 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL; 881 882 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc, 883 pause_en, my_pfc); 884 } 885 886 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 887 { 888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 889 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 890 int err; 891 892 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en); 893 if (err) 894 return err; 895 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu); 896 if (err) 897 goto err_span_port_mtu_update; 898 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 899 if (err) 900 goto err_port_mtu_set; 901 dev->mtu = mtu; 902 return 0; 903 904 err_port_mtu_set: 905 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu); 906 err_span_port_mtu_update: 907 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 908 return err; 909 } 910 911 static int 912 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 913 struct rtnl_link_stats64 *stats) 914 { 915 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 916 struct mlxsw_sp_port_pcpu_stats *p; 917 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 918 u32 tx_dropped = 0; 919 unsigned int start; 920 int i; 921 922 for_each_possible_cpu(i) { 923 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 924 do { 925 start = u64_stats_fetch_begin_irq(&p->syncp); 926 rx_packets = p->rx_packets; 927 rx_bytes = p->rx_bytes; 928 tx_packets = p->tx_packets; 929 tx_bytes = p->tx_bytes; 930 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 931 932 stats->rx_packets += rx_packets; 933 stats->rx_bytes += rx_bytes; 934 stats->tx_packets += tx_packets; 935 stats->tx_bytes += tx_bytes; 936 /* tx_dropped is u32, updated without syncp protection. */ 937 tx_dropped += p->tx_dropped; 938 } 939 stats->tx_dropped = tx_dropped; 940 return 0; 941 } 942 943 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 944 { 945 switch (attr_id) { 946 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 947 return true; 948 } 949 950 return false; 951 } 952 953 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 954 void *sp) 955 { 956 switch (attr_id) { 957 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 958 return mlxsw_sp_port_get_sw_stats64(dev, sp); 959 } 960 961 return -EINVAL; 962 } 963 964 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 965 int prio, char *ppcnt_pl) 966 { 967 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 968 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 969 970 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 971 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 972 } 973 974 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 975 struct rtnl_link_stats64 *stats) 976 { 977 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 978 int err; 979 980 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 981 0, ppcnt_pl); 982 if (err) 983 goto out; 984 985 stats->tx_packets = 986 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 987 stats->rx_packets = 988 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 989 stats->tx_bytes = 990 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 991 stats->rx_bytes = 992 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 993 stats->multicast = 994 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 995 996 stats->rx_crc_errors = 997 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 998 stats->rx_frame_errors = 999 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 1000 1001 stats->rx_length_errors = ( 1002 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 1003 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 1004 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 1005 1006 stats->rx_errors = (stats->rx_crc_errors + 1007 stats->rx_frame_errors + stats->rx_length_errors); 1008 1009 out: 1010 return err; 1011 } 1012 1013 static void 1014 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 1015 struct mlxsw_sp_port_xstats *xstats) 1016 { 1017 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1018 int err, i; 1019 1020 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 1021 ppcnt_pl); 1022 if (!err) 1023 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 1024 1025 for (i = 0; i < TC_MAX_QUEUE; i++) { 1026 err = mlxsw_sp_port_get_stats_raw(dev, 1027 MLXSW_REG_PPCNT_TC_CONG_TC, 1028 i, ppcnt_pl); 1029 if (!err) 1030 xstats->wred_drop[i] = 1031 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 1032 1033 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 1034 i, ppcnt_pl); 1035 if (err) 1036 continue; 1037 1038 xstats->backlog[i] = 1039 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 1040 xstats->tail_drop[i] = 1041 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 1042 } 1043 } 1044 1045 static void update_stats_cache(struct work_struct *work) 1046 { 1047 struct mlxsw_sp_port *mlxsw_sp_port = 1048 container_of(work, struct mlxsw_sp_port, 1049 periodic_hw_stats.update_dw.work); 1050 1051 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 1052 goto out; 1053 1054 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 1055 &mlxsw_sp_port->periodic_hw_stats.stats); 1056 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 1057 &mlxsw_sp_port->periodic_hw_stats.xstats); 1058 1059 out: 1060 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1061 MLXSW_HW_STATS_UPDATE_TIME); 1062 } 1063 1064 /* Return the stats from a cache that is updated periodically, 1065 * as this function might get called in an atomic context. 1066 */ 1067 static void 1068 mlxsw_sp_port_get_stats64(struct net_device *dev, 1069 struct rtnl_link_stats64 *stats) 1070 { 1071 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1072 1073 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 1074 } 1075 1076 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 1077 u16 vid_begin, u16 vid_end, 1078 bool is_member, bool untagged) 1079 { 1080 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1081 char *spvm_pl; 1082 int err; 1083 1084 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1085 if (!spvm_pl) 1086 return -ENOMEM; 1087 1088 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1089 vid_end, is_member, untagged); 1090 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1091 kfree(spvm_pl); 1092 return err; 1093 } 1094 1095 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1096 u16 vid_end, bool is_member, bool untagged) 1097 { 1098 u16 vid, vid_e; 1099 int err; 1100 1101 for (vid = vid_begin; vid <= vid_end; 1102 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1103 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1104 vid_end); 1105 1106 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1107 is_member, untagged); 1108 if (err) 1109 return err; 1110 } 1111 1112 return 0; 1113 } 1114 1115 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port) 1116 { 1117 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1118 1119 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1120 &mlxsw_sp_port->vlans_list, list) 1121 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1122 } 1123 1124 static struct mlxsw_sp_port_vlan * 1125 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1126 { 1127 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1128 bool untagged = vid == 1; 1129 int err; 1130 1131 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1132 if (err) 1133 return ERR_PTR(err); 1134 1135 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1136 if (!mlxsw_sp_port_vlan) { 1137 err = -ENOMEM; 1138 goto err_port_vlan_alloc; 1139 } 1140 1141 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1142 mlxsw_sp_port_vlan->vid = vid; 1143 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1144 1145 return mlxsw_sp_port_vlan; 1146 1147 err_port_vlan_alloc: 1148 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1149 return ERR_PTR(err); 1150 } 1151 1152 static void 1153 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1154 { 1155 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1156 u16 vid = mlxsw_sp_port_vlan->vid; 1157 1158 list_del(&mlxsw_sp_port_vlan->list); 1159 kfree(mlxsw_sp_port_vlan); 1160 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1161 } 1162 1163 struct mlxsw_sp_port_vlan * 1164 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1165 { 1166 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1167 1168 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1169 if (mlxsw_sp_port_vlan) 1170 return mlxsw_sp_port_vlan; 1171 1172 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid); 1173 } 1174 1175 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1176 { 1177 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid; 1178 1179 if (mlxsw_sp_port_vlan->bridge_port) 1180 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1181 else if (fid) 1182 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1183 1184 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1185 } 1186 1187 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1188 __be16 __always_unused proto, u16 vid) 1189 { 1190 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1191 1192 /* VLAN 0 is added to HW filter when device goes up, but it is 1193 * reserved in our case, so simply return. 1194 */ 1195 if (!vid) 1196 return 0; 1197 1198 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid)); 1199 } 1200 1201 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1202 __be16 __always_unused proto, u16 vid) 1203 { 1204 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1205 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1206 1207 /* VLAN 0 is removed from HW filter when device goes down, but 1208 * it is reserved in our case, so simply return. 1209 */ 1210 if (!vid) 1211 return 0; 1212 1213 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1214 if (!mlxsw_sp_port_vlan) 1215 return 0; 1216 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1217 1218 return 0; 1219 } 1220 1221 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name, 1222 size_t len) 1223 { 1224 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1225 u8 module = mlxsw_sp_port->mapping.module; 1226 u8 width = mlxsw_sp_port->mapping.width; 1227 u8 lane = mlxsw_sp_port->mapping.lane; 1228 int err; 1229 1230 if (!mlxsw_sp_port->split) 1231 err = snprintf(name, len, "p%d", module + 1); 1232 else 1233 err = snprintf(name, len, "p%ds%d", module + 1, 1234 lane / width); 1235 1236 if (err >= len) 1237 return -EINVAL; 1238 1239 return 0; 1240 } 1241 1242 static struct mlxsw_sp_port_mall_tc_entry * 1243 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port, 1244 unsigned long cookie) { 1245 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1246 1247 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list) 1248 if (mall_tc_entry->cookie == cookie) 1249 return mall_tc_entry; 1250 1251 return NULL; 1252 } 1253 1254 static int 1255 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1256 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror, 1257 const struct tc_action *a, 1258 bool ingress) 1259 { 1260 enum mlxsw_sp_span_type span_type; 1261 struct mlxsw_sp_port *to_port; 1262 struct net_device *to_dev; 1263 1264 to_dev = tcf_mirred_dev(a); 1265 if (!to_dev) { 1266 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n"); 1267 return -EINVAL; 1268 } 1269 1270 if (!mlxsw_sp_port_dev_check(to_dev)) { 1271 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port"); 1272 return -EOPNOTSUPP; 1273 } 1274 to_port = netdev_priv(to_dev); 1275 1276 mirror->to_local_port = to_port->local_port; 1277 mirror->ingress = ingress; 1278 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1279 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type, 1280 true); 1281 } 1282 1283 static void 1284 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1285 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror) 1286 { 1287 enum mlxsw_sp_span_type span_type; 1288 1289 span_type = mirror->ingress ? 1290 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1291 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->to_local_port, 1292 span_type, true); 1293 } 1294 1295 static int 1296 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port, 1297 struct tc_cls_matchall_offload *cls, 1298 const struct tc_action *a, 1299 bool ingress) 1300 { 1301 int err; 1302 1303 if (!mlxsw_sp_port->sample) 1304 return -EOPNOTSUPP; 1305 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) { 1306 netdev_err(mlxsw_sp_port->dev, "sample already active\n"); 1307 return -EEXIST; 1308 } 1309 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) { 1310 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n"); 1311 return -EOPNOTSUPP; 1312 } 1313 1314 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group, 1315 tcf_sample_psample_group(a)); 1316 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a); 1317 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a); 1318 mlxsw_sp_port->sample->rate = tcf_sample_rate(a); 1319 1320 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a)); 1321 if (err) 1322 goto err_port_sample_set; 1323 return 0; 1324 1325 err_port_sample_set: 1326 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1327 return err; 1328 } 1329 1330 static void 1331 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port) 1332 { 1333 if (!mlxsw_sp_port->sample) 1334 return; 1335 1336 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1); 1337 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1338 } 1339 1340 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1341 struct tc_cls_matchall_offload *f, 1342 bool ingress) 1343 { 1344 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1345 __be16 protocol = f->common.protocol; 1346 const struct tc_action *a; 1347 LIST_HEAD(actions); 1348 int err; 1349 1350 if (!tcf_exts_has_one_action(f->exts)) { 1351 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n"); 1352 return -EOPNOTSUPP; 1353 } 1354 1355 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL); 1356 if (!mall_tc_entry) 1357 return -ENOMEM; 1358 mall_tc_entry->cookie = f->cookie; 1359 1360 tcf_exts_to_list(f->exts, &actions); 1361 a = list_first_entry(&actions, struct tc_action, list); 1362 1363 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) { 1364 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror; 1365 1366 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR; 1367 mirror = &mall_tc_entry->mirror; 1368 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, 1369 mirror, a, ingress); 1370 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) { 1371 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE; 1372 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f, 1373 a, ingress); 1374 } else { 1375 err = -EOPNOTSUPP; 1376 } 1377 1378 if (err) 1379 goto err_add_action; 1380 1381 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list); 1382 return 0; 1383 1384 err_add_action: 1385 kfree(mall_tc_entry); 1386 return err; 1387 } 1388 1389 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1390 struct tc_cls_matchall_offload *f) 1391 { 1392 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1393 1394 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port, 1395 f->cookie); 1396 if (!mall_tc_entry) { 1397 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n"); 1398 return; 1399 } 1400 list_del(&mall_tc_entry->list); 1401 1402 switch (mall_tc_entry->type) { 1403 case MLXSW_SP_PORT_MALL_MIRROR: 1404 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port, 1405 &mall_tc_entry->mirror); 1406 break; 1407 case MLXSW_SP_PORT_MALL_SAMPLE: 1408 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port); 1409 break; 1410 default: 1411 WARN_ON(1); 1412 } 1413 1414 kfree(mall_tc_entry); 1415 } 1416 1417 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1418 struct tc_cls_matchall_offload *f, 1419 bool ingress) 1420 { 1421 switch (f->command) { 1422 case TC_CLSMATCHALL_REPLACE: 1423 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f, 1424 ingress); 1425 case TC_CLSMATCHALL_DESTROY: 1426 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f); 1427 return 0; 1428 default: 1429 return -EOPNOTSUPP; 1430 } 1431 } 1432 1433 static int 1434 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block, 1435 struct tc_cls_flower_offload *f) 1436 { 1437 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block); 1438 1439 switch (f->command) { 1440 case TC_CLSFLOWER_REPLACE: 1441 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f); 1442 case TC_CLSFLOWER_DESTROY: 1443 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f); 1444 return 0; 1445 case TC_CLSFLOWER_STATS: 1446 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f); 1447 default: 1448 return -EOPNOTSUPP; 1449 } 1450 } 1451 1452 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type, 1453 void *type_data, 1454 void *cb_priv, bool ingress) 1455 { 1456 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv; 1457 1458 switch (type) { 1459 case TC_SETUP_CLSMATCHALL: 1460 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev, 1461 type_data)) 1462 return -EOPNOTSUPP; 1463 1464 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data, 1465 ingress); 1466 case TC_SETUP_CLSFLOWER: 1467 return 0; 1468 default: 1469 return -EOPNOTSUPP; 1470 } 1471 } 1472 1473 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type, 1474 void *type_data, 1475 void *cb_priv) 1476 { 1477 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1478 cb_priv, true); 1479 } 1480 1481 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type, 1482 void *type_data, 1483 void *cb_priv) 1484 { 1485 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1486 cb_priv, false); 1487 } 1488 1489 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type, 1490 void *type_data, void *cb_priv) 1491 { 1492 struct mlxsw_sp_acl_block *acl_block = cb_priv; 1493 1494 switch (type) { 1495 case TC_SETUP_CLSMATCHALL: 1496 return 0; 1497 case TC_SETUP_CLSFLOWER: 1498 if (mlxsw_sp_acl_block_disabled(acl_block)) 1499 return -EOPNOTSUPP; 1500 1501 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data); 1502 default: 1503 return -EOPNOTSUPP; 1504 } 1505 } 1506 1507 static int 1508 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port, 1509 struct tcf_block *block, bool ingress) 1510 { 1511 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1512 struct mlxsw_sp_acl_block *acl_block; 1513 struct tcf_block_cb *block_cb; 1514 int err; 1515 1516 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1517 mlxsw_sp); 1518 if (!block_cb) { 1519 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net); 1520 if (!acl_block) 1521 return -ENOMEM; 1522 block_cb = __tcf_block_cb_register(block, 1523 mlxsw_sp_setup_tc_block_cb_flower, 1524 mlxsw_sp, acl_block); 1525 if (IS_ERR(block_cb)) { 1526 err = PTR_ERR(block_cb); 1527 goto err_cb_register; 1528 } 1529 } else { 1530 acl_block = tcf_block_cb_priv(block_cb); 1531 } 1532 tcf_block_cb_incref(block_cb); 1533 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block, 1534 mlxsw_sp_port, ingress); 1535 if (err) 1536 goto err_block_bind; 1537 1538 if (ingress) 1539 mlxsw_sp_port->ing_acl_block = acl_block; 1540 else 1541 mlxsw_sp_port->eg_acl_block = acl_block; 1542 1543 return 0; 1544 1545 err_block_bind: 1546 if (!tcf_block_cb_decref(block_cb)) { 1547 __tcf_block_cb_unregister(block_cb); 1548 err_cb_register: 1549 mlxsw_sp_acl_block_destroy(acl_block); 1550 } 1551 return err; 1552 } 1553 1554 static void 1555 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port, 1556 struct tcf_block *block, bool ingress) 1557 { 1558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1559 struct mlxsw_sp_acl_block *acl_block; 1560 struct tcf_block_cb *block_cb; 1561 int err; 1562 1563 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1564 mlxsw_sp); 1565 if (!block_cb) 1566 return; 1567 1568 if (ingress) 1569 mlxsw_sp_port->ing_acl_block = NULL; 1570 else 1571 mlxsw_sp_port->eg_acl_block = NULL; 1572 1573 acl_block = tcf_block_cb_priv(block_cb); 1574 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block, 1575 mlxsw_sp_port, ingress); 1576 if (!err && !tcf_block_cb_decref(block_cb)) { 1577 __tcf_block_cb_unregister(block_cb); 1578 mlxsw_sp_acl_block_destroy(acl_block); 1579 } 1580 } 1581 1582 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1583 struct tc_block_offload *f) 1584 { 1585 tc_setup_cb_t *cb; 1586 bool ingress; 1587 int err; 1588 1589 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) { 1590 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig; 1591 ingress = true; 1592 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 1593 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg; 1594 ingress = false; 1595 } else { 1596 return -EOPNOTSUPP; 1597 } 1598 1599 switch (f->command) { 1600 case TC_BLOCK_BIND: 1601 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port, 1602 mlxsw_sp_port); 1603 if (err) 1604 return err; 1605 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, 1606 f->block, ingress); 1607 if (err) { 1608 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1609 return err; 1610 } 1611 return 0; 1612 case TC_BLOCK_UNBIND: 1613 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port, 1614 f->block, ingress); 1615 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1616 return 0; 1617 default: 1618 return -EOPNOTSUPP; 1619 } 1620 } 1621 1622 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1623 void *type_data) 1624 { 1625 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1626 1627 switch (type) { 1628 case TC_SETUP_BLOCK: 1629 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1630 case TC_SETUP_QDISC_RED: 1631 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1632 case TC_SETUP_QDISC_PRIO: 1633 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1634 default: 1635 return -EOPNOTSUPP; 1636 } 1637 } 1638 1639 1640 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1641 { 1642 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1643 1644 if (!enable) { 1645 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) || 1646 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) || 1647 !list_empty(&mlxsw_sp_port->mall_tc_list)) { 1648 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1649 return -EINVAL; 1650 } 1651 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block); 1652 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block); 1653 } else { 1654 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block); 1655 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block); 1656 } 1657 return 0; 1658 } 1659 1660 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1661 1662 static int mlxsw_sp_handle_feature(struct net_device *dev, 1663 netdev_features_t wanted_features, 1664 netdev_features_t feature, 1665 mlxsw_sp_feature_handler feature_handler) 1666 { 1667 netdev_features_t changes = wanted_features ^ dev->features; 1668 bool enable = !!(wanted_features & feature); 1669 int err; 1670 1671 if (!(changes & feature)) 1672 return 0; 1673 1674 err = feature_handler(dev, enable); 1675 if (err) { 1676 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1677 enable ? "Enable" : "Disable", &feature, err); 1678 return err; 1679 } 1680 1681 if (enable) 1682 dev->features |= feature; 1683 else 1684 dev->features &= ~feature; 1685 1686 return 0; 1687 } 1688 static int mlxsw_sp_set_features(struct net_device *dev, 1689 netdev_features_t features) 1690 { 1691 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1692 mlxsw_sp_feature_hw_tc); 1693 } 1694 1695 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1696 .ndo_open = mlxsw_sp_port_open, 1697 .ndo_stop = mlxsw_sp_port_stop, 1698 .ndo_start_xmit = mlxsw_sp_port_xmit, 1699 .ndo_setup_tc = mlxsw_sp_setup_tc, 1700 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1701 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1702 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1703 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1704 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1705 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1706 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1707 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1708 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name, 1709 .ndo_set_features = mlxsw_sp_set_features, 1710 }; 1711 1712 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev, 1713 struct ethtool_drvinfo *drvinfo) 1714 { 1715 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1716 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1717 1718 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver)); 1719 strlcpy(drvinfo->version, mlxsw_sp_driver_version, 1720 sizeof(drvinfo->version)); 1721 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 1722 "%d.%d.%d", 1723 mlxsw_sp->bus_info->fw_rev.major, 1724 mlxsw_sp->bus_info->fw_rev.minor, 1725 mlxsw_sp->bus_info->fw_rev.subminor); 1726 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name, 1727 sizeof(drvinfo->bus_info)); 1728 } 1729 1730 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev, 1731 struct ethtool_pauseparam *pause) 1732 { 1733 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1734 1735 pause->rx_pause = mlxsw_sp_port->link.rx_pause; 1736 pause->tx_pause = mlxsw_sp_port->link.tx_pause; 1737 } 1738 1739 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port, 1740 struct ethtool_pauseparam *pause) 1741 { 1742 char pfcc_pl[MLXSW_REG_PFCC_LEN]; 1743 1744 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port); 1745 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause); 1746 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause); 1747 1748 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc), 1749 pfcc_pl); 1750 } 1751 1752 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev, 1753 struct ethtool_pauseparam *pause) 1754 { 1755 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1756 bool pause_en = pause->tx_pause || pause->rx_pause; 1757 int err; 1758 1759 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) { 1760 netdev_err(dev, "PFC already enabled on port\n"); 1761 return -EINVAL; 1762 } 1763 1764 if (pause->autoneg) { 1765 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n"); 1766 return -EINVAL; 1767 } 1768 1769 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1770 if (err) { 1771 netdev_err(dev, "Failed to configure port's headroom\n"); 1772 return err; 1773 } 1774 1775 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause); 1776 if (err) { 1777 netdev_err(dev, "Failed to set PAUSE parameters\n"); 1778 goto err_port_pause_configure; 1779 } 1780 1781 mlxsw_sp_port->link.rx_pause = pause->rx_pause; 1782 mlxsw_sp_port->link.tx_pause = pause->tx_pause; 1783 1784 return 0; 1785 1786 err_port_pause_configure: 1787 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 1788 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1789 return err; 1790 } 1791 1792 struct mlxsw_sp_port_hw_stats { 1793 char str[ETH_GSTRING_LEN]; 1794 u64 (*getter)(const char *payload); 1795 bool cells_bytes; 1796 }; 1797 1798 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = { 1799 { 1800 .str = "a_frames_transmitted_ok", 1801 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get, 1802 }, 1803 { 1804 .str = "a_frames_received_ok", 1805 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get, 1806 }, 1807 { 1808 .str = "a_frame_check_sequence_errors", 1809 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get, 1810 }, 1811 { 1812 .str = "a_alignment_errors", 1813 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get, 1814 }, 1815 { 1816 .str = "a_octets_transmitted_ok", 1817 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get, 1818 }, 1819 { 1820 .str = "a_octets_received_ok", 1821 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get, 1822 }, 1823 { 1824 .str = "a_multicast_frames_xmitted_ok", 1825 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get, 1826 }, 1827 { 1828 .str = "a_broadcast_frames_xmitted_ok", 1829 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get, 1830 }, 1831 { 1832 .str = "a_multicast_frames_received_ok", 1833 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get, 1834 }, 1835 { 1836 .str = "a_broadcast_frames_received_ok", 1837 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get, 1838 }, 1839 { 1840 .str = "a_in_range_length_errors", 1841 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get, 1842 }, 1843 { 1844 .str = "a_out_of_range_length_field", 1845 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get, 1846 }, 1847 { 1848 .str = "a_frame_too_long_errors", 1849 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get, 1850 }, 1851 { 1852 .str = "a_symbol_error_during_carrier", 1853 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get, 1854 }, 1855 { 1856 .str = "a_mac_control_frames_transmitted", 1857 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get, 1858 }, 1859 { 1860 .str = "a_mac_control_frames_received", 1861 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get, 1862 }, 1863 { 1864 .str = "a_unsupported_opcodes_received", 1865 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get, 1866 }, 1867 { 1868 .str = "a_pause_mac_ctrl_frames_received", 1869 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get, 1870 }, 1871 { 1872 .str = "a_pause_mac_ctrl_frames_xmitted", 1873 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get, 1874 }, 1875 }; 1876 1877 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats) 1878 1879 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = { 1880 { 1881 .str = "rx_octets_prio", 1882 .getter = mlxsw_reg_ppcnt_rx_octets_get, 1883 }, 1884 { 1885 .str = "rx_frames_prio", 1886 .getter = mlxsw_reg_ppcnt_rx_frames_get, 1887 }, 1888 { 1889 .str = "tx_octets_prio", 1890 .getter = mlxsw_reg_ppcnt_tx_octets_get, 1891 }, 1892 { 1893 .str = "tx_frames_prio", 1894 .getter = mlxsw_reg_ppcnt_tx_frames_get, 1895 }, 1896 { 1897 .str = "rx_pause_prio", 1898 .getter = mlxsw_reg_ppcnt_rx_pause_get, 1899 }, 1900 { 1901 .str = "rx_pause_duration_prio", 1902 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get, 1903 }, 1904 { 1905 .str = "tx_pause_prio", 1906 .getter = mlxsw_reg_ppcnt_tx_pause_get, 1907 }, 1908 { 1909 .str = "tx_pause_duration_prio", 1910 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get, 1911 }, 1912 }; 1913 1914 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats) 1915 1916 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = { 1917 { 1918 .str = "tc_transmit_queue_tc", 1919 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get, 1920 .cells_bytes = true, 1921 }, 1922 { 1923 .str = "tc_no_buffer_discard_uc_tc", 1924 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get, 1925 }, 1926 }; 1927 1928 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats) 1929 1930 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \ 1931 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \ 1932 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \ 1933 IEEE_8021QAZ_MAX_TCS) 1934 1935 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio) 1936 { 1937 int i; 1938 1939 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) { 1940 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1941 mlxsw_sp_port_hw_prio_stats[i].str, prio); 1942 *p += ETH_GSTRING_LEN; 1943 } 1944 } 1945 1946 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc) 1947 { 1948 int i; 1949 1950 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) { 1951 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1952 mlxsw_sp_port_hw_tc_stats[i].str, tc); 1953 *p += ETH_GSTRING_LEN; 1954 } 1955 } 1956 1957 static void mlxsw_sp_port_get_strings(struct net_device *dev, 1958 u32 stringset, u8 *data) 1959 { 1960 u8 *p = data; 1961 int i; 1962 1963 switch (stringset) { 1964 case ETH_SS_STATS: 1965 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) { 1966 memcpy(p, mlxsw_sp_port_hw_stats[i].str, 1967 ETH_GSTRING_LEN); 1968 p += ETH_GSTRING_LEN; 1969 } 1970 1971 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 1972 mlxsw_sp_port_get_prio_strings(&p, i); 1973 1974 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 1975 mlxsw_sp_port_get_tc_strings(&p, i); 1976 1977 break; 1978 } 1979 } 1980 1981 static int mlxsw_sp_port_set_phys_id(struct net_device *dev, 1982 enum ethtool_phys_id_state state) 1983 { 1984 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1985 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1986 char mlcr_pl[MLXSW_REG_MLCR_LEN]; 1987 bool active; 1988 1989 switch (state) { 1990 case ETHTOOL_ID_ACTIVE: 1991 active = true; 1992 break; 1993 case ETHTOOL_ID_INACTIVE: 1994 active = false; 1995 break; 1996 default: 1997 return -EOPNOTSUPP; 1998 } 1999 2000 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active); 2001 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl); 2002 } 2003 2004 static int 2005 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats, 2006 int *p_len, enum mlxsw_reg_ppcnt_grp grp) 2007 { 2008 switch (grp) { 2009 case MLXSW_REG_PPCNT_IEEE_8023_CNT: 2010 *p_hw_stats = mlxsw_sp_port_hw_stats; 2011 *p_len = MLXSW_SP_PORT_HW_STATS_LEN; 2012 break; 2013 case MLXSW_REG_PPCNT_PRIO_CNT: 2014 *p_hw_stats = mlxsw_sp_port_hw_prio_stats; 2015 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2016 break; 2017 case MLXSW_REG_PPCNT_TC_CNT: 2018 *p_hw_stats = mlxsw_sp_port_hw_tc_stats; 2019 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN; 2020 break; 2021 default: 2022 WARN_ON(1); 2023 return -EOPNOTSUPP; 2024 } 2025 return 0; 2026 } 2027 2028 static void __mlxsw_sp_port_get_stats(struct net_device *dev, 2029 enum mlxsw_reg_ppcnt_grp grp, int prio, 2030 u64 *data, int data_index) 2031 { 2032 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2033 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2034 struct mlxsw_sp_port_hw_stats *hw_stats; 2035 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 2036 int i, len; 2037 int err; 2038 2039 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp); 2040 if (err) 2041 return; 2042 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl); 2043 for (i = 0; i < len; i++) { 2044 data[data_index + i] = hw_stats[i].getter(ppcnt_pl); 2045 if (!hw_stats[i].cells_bytes) 2046 continue; 2047 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp, 2048 data[data_index + i]); 2049 } 2050 } 2051 2052 static void mlxsw_sp_port_get_stats(struct net_device *dev, 2053 struct ethtool_stats *stats, u64 *data) 2054 { 2055 int i, data_index = 0; 2056 2057 /* IEEE 802.3 Counters */ 2058 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0, 2059 data, data_index); 2060 data_index = MLXSW_SP_PORT_HW_STATS_LEN; 2061 2062 /* Per-Priority Counters */ 2063 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2064 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i, 2065 data, data_index); 2066 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2067 } 2068 2069 /* Per-TC Counters */ 2070 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2071 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i, 2072 data, data_index); 2073 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN; 2074 } 2075 } 2076 2077 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset) 2078 { 2079 switch (sset) { 2080 case ETH_SS_STATS: 2081 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN; 2082 default: 2083 return -EOPNOTSUPP; 2084 } 2085 } 2086 2087 struct mlxsw_sp_port_link_mode { 2088 enum ethtool_link_mode_bit_indices mask_ethtool; 2089 u32 mask; 2090 u32 speed; 2091 }; 2092 2093 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = { 2094 { 2095 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, 2096 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2097 .speed = SPEED_100, 2098 }, 2099 { 2100 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | 2101 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX, 2102 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2103 .speed = SPEED_1000, 2104 }, 2105 { 2106 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, 2107 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2108 .speed = SPEED_10000, 2109 }, 2110 { 2111 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | 2112 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4, 2113 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2114 .speed = SPEED_10000, 2115 }, 2116 { 2117 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2118 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2119 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2120 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR, 2121 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2122 .speed = SPEED_10000, 2123 }, 2124 { 2125 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, 2126 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 2127 .speed = SPEED_20000, 2128 }, 2129 { 2130 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, 2131 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2132 .speed = SPEED_40000, 2133 }, 2134 { 2135 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, 2136 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2137 .speed = SPEED_40000, 2138 }, 2139 { 2140 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, 2141 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2142 .speed = SPEED_40000, 2143 }, 2144 { 2145 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, 2146 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2147 .speed = SPEED_40000, 2148 }, 2149 { 2150 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, 2151 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2152 .speed = SPEED_25000, 2153 }, 2154 { 2155 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, 2156 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2157 .speed = SPEED_25000, 2158 }, 2159 { 2160 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2161 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2162 .speed = SPEED_25000, 2163 }, 2164 { 2165 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2166 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2167 .speed = SPEED_25000, 2168 }, 2169 { 2170 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, 2171 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2172 .speed = SPEED_50000, 2173 }, 2174 { 2175 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, 2176 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2177 .speed = SPEED_50000, 2178 }, 2179 { 2180 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, 2181 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2182 .speed = SPEED_50000, 2183 }, 2184 { 2185 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2186 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, 2187 .speed = SPEED_56000, 2188 }, 2189 { 2190 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2191 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, 2192 .speed = SPEED_56000, 2193 }, 2194 { 2195 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2196 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, 2197 .speed = SPEED_56000, 2198 }, 2199 { 2200 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2201 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, 2202 .speed = SPEED_56000, 2203 }, 2204 { 2205 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, 2206 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2207 .speed = SPEED_100000, 2208 }, 2209 { 2210 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, 2211 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2212 .speed = SPEED_100000, 2213 }, 2214 { 2215 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, 2216 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2217 .speed = SPEED_100000, 2218 }, 2219 { 2220 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, 2221 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2222 .speed = SPEED_100000, 2223 }, 2224 }; 2225 2226 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode) 2227 2228 static void 2229 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto, 2230 struct ethtool_link_ksettings *cmd) 2231 { 2232 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2233 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2234 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2235 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2236 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2237 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2238 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2239 2240 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2241 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2242 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2243 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | 2244 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX)) 2245 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2246 } 2247 2248 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode) 2249 { 2250 int i; 2251 2252 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2253 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) 2254 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2255 mode); 2256 } 2257 } 2258 2259 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto, 2260 struct ethtool_link_ksettings *cmd) 2261 { 2262 u32 speed = SPEED_UNKNOWN; 2263 u8 duplex = DUPLEX_UNKNOWN; 2264 int i; 2265 2266 if (!carrier_ok) 2267 goto out; 2268 2269 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2270 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) { 2271 speed = mlxsw_sp_port_link_mode[i].speed; 2272 duplex = DUPLEX_FULL; 2273 break; 2274 } 2275 } 2276 out: 2277 cmd->base.speed = speed; 2278 cmd->base.duplex = duplex; 2279 } 2280 2281 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto) 2282 { 2283 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2284 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2285 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2286 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2287 return PORT_FIBRE; 2288 2289 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2290 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2291 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4)) 2292 return PORT_DA; 2293 2294 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2295 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2296 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2297 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4)) 2298 return PORT_NONE; 2299 2300 return PORT_OTHER; 2301 } 2302 2303 static u32 2304 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd) 2305 { 2306 u32 ptys_proto = 0; 2307 int i; 2308 2309 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2310 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2311 cmd->link_modes.advertising)) 2312 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2313 } 2314 return ptys_proto; 2315 } 2316 2317 static u32 mlxsw_sp_to_ptys_speed(u32 speed) 2318 { 2319 u32 ptys_proto = 0; 2320 int i; 2321 2322 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2323 if (speed == mlxsw_sp_port_link_mode[i].speed) 2324 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2325 } 2326 return ptys_proto; 2327 } 2328 2329 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed) 2330 { 2331 u32 ptys_proto = 0; 2332 int i; 2333 2334 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2335 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed) 2336 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2337 } 2338 return ptys_proto; 2339 } 2340 2341 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap, 2342 struct ethtool_link_ksettings *cmd) 2343 { 2344 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause); 2345 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 2346 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 2347 2348 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd); 2349 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported); 2350 } 2351 2352 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg, 2353 struct ethtool_link_ksettings *cmd) 2354 { 2355 if (!autoneg) 2356 return; 2357 2358 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 2359 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising); 2360 } 2361 2362 static void 2363 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status, 2364 struct ethtool_link_ksettings *cmd) 2365 { 2366 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp) 2367 return; 2368 2369 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg); 2370 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising); 2371 } 2372 2373 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev, 2374 struct ethtool_link_ksettings *cmd) 2375 { 2376 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp; 2377 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2378 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2379 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2380 u8 autoneg_status; 2381 bool autoneg; 2382 int err; 2383 2384 autoneg = mlxsw_sp_port->link.autoneg; 2385 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0); 2386 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2387 if (err) 2388 return err; 2389 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, 2390 ð_proto_oper); 2391 2392 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd); 2393 2394 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd); 2395 2396 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl); 2397 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl); 2398 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd); 2399 2400 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 2401 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper); 2402 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper, 2403 cmd); 2404 2405 return 0; 2406 } 2407 2408 static int 2409 mlxsw_sp_port_set_link_ksettings(struct net_device *dev, 2410 const struct ethtool_link_ksettings *cmd) 2411 { 2412 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2413 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2414 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2415 u32 eth_proto_cap, eth_proto_new; 2416 bool autoneg; 2417 int err; 2418 2419 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0); 2420 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2421 if (err) 2422 return err; 2423 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); 2424 2425 autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 2426 eth_proto_new = autoneg ? 2427 mlxsw_sp_to_ptys_advert_link(cmd) : 2428 mlxsw_sp_to_ptys_speed(cmd->base.speed); 2429 2430 eth_proto_new = eth_proto_new & eth_proto_cap; 2431 if (!eth_proto_new) { 2432 netdev_err(dev, "No supported speed requested\n"); 2433 return -EINVAL; 2434 } 2435 2436 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2437 eth_proto_new); 2438 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2439 if (err) 2440 return err; 2441 2442 if (!netif_running(dev)) 2443 return 0; 2444 2445 mlxsw_sp_port->link.autoneg = autoneg; 2446 2447 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2448 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 2449 2450 return 0; 2451 } 2452 2453 static int mlxsw_sp_flash_device(struct net_device *dev, 2454 struct ethtool_flash *flash) 2455 { 2456 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2458 const struct firmware *firmware; 2459 int err; 2460 2461 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2462 return -EOPNOTSUPP; 2463 2464 dev_hold(dev); 2465 rtnl_unlock(); 2466 2467 err = request_firmware_direct(&firmware, flash->data, &dev->dev); 2468 if (err) 2469 goto out; 2470 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 2471 release_firmware(firmware); 2472 out: 2473 rtnl_lock(); 2474 dev_put(dev); 2475 return err; 2476 } 2477 2478 #define MLXSW_SP_I2C_ADDR_LOW 0x50 2479 #define MLXSW_SP_I2C_ADDR_HIGH 0x51 2480 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256 2481 2482 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port, 2483 u16 offset, u16 size, void *data, 2484 unsigned int *p_read_size) 2485 { 2486 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2487 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE]; 2488 char mcia_pl[MLXSW_REG_MCIA_LEN]; 2489 u16 i2c_addr; 2490 int status; 2491 int err; 2492 2493 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 2494 2495 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH && 2496 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH) 2497 /* Cross pages read, read until offset 256 in low page */ 2498 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset; 2499 2500 i2c_addr = MLXSW_SP_I2C_ADDR_LOW; 2501 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) { 2502 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH; 2503 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH; 2504 } 2505 2506 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module, 2507 0, 0, offset, size, i2c_addr); 2508 2509 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl); 2510 if (err) 2511 return err; 2512 2513 status = mlxsw_reg_mcia_status_get(mcia_pl); 2514 if (status) 2515 return -EIO; 2516 2517 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp); 2518 memcpy(data, eeprom_tmp, size); 2519 *p_read_size = size; 2520 2521 return 0; 2522 } 2523 2524 enum mlxsw_sp_eeprom_module_info_rev_id { 2525 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 2526 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 2527 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 2528 }; 2529 2530 enum mlxsw_sp_eeprom_module_info_id { 2531 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03, 2532 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 2533 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 2534 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 2535 }; 2536 2537 enum mlxsw_sp_eeprom_module_info { 2538 MLXSW_SP_EEPROM_MODULE_INFO_ID, 2539 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID, 2540 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2541 }; 2542 2543 static int mlxsw_sp_get_module_info(struct net_device *netdev, 2544 struct ethtool_modinfo *modinfo) 2545 { 2546 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2547 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE]; 2548 u8 module_rev_id, module_id; 2549 unsigned int read_size; 2550 int err; 2551 2552 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0, 2553 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2554 module_info, &read_size); 2555 if (err) 2556 return err; 2557 2558 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE) 2559 return -EIO; 2560 2561 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID]; 2562 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID]; 2563 2564 switch (module_id) { 2565 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP: 2566 modinfo->type = ETH_MODULE_SFF_8436; 2567 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2568 break; 2569 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS: 2570 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28: 2571 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 || 2572 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) { 2573 modinfo->type = ETH_MODULE_SFF_8636; 2574 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2575 } else { 2576 modinfo->type = ETH_MODULE_SFF_8436; 2577 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2578 } 2579 break; 2580 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP: 2581 modinfo->type = ETH_MODULE_SFF_8472; 2582 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2583 break; 2584 default: 2585 return -EINVAL; 2586 } 2587 2588 return 0; 2589 } 2590 2591 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev, 2592 struct ethtool_eeprom *ee, 2593 u8 *data) 2594 { 2595 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2596 int offset = ee->offset; 2597 unsigned int read_size; 2598 int i = 0; 2599 int err; 2600 2601 if (!ee->len) 2602 return -EINVAL; 2603 2604 memset(data, 0, ee->len); 2605 2606 while (i < ee->len) { 2607 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset, 2608 ee->len - i, data + i, 2609 &read_size); 2610 if (err) { 2611 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n"); 2612 return err; 2613 } 2614 2615 i += read_size; 2616 offset += read_size; 2617 } 2618 2619 return 0; 2620 } 2621 2622 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { 2623 .get_drvinfo = mlxsw_sp_port_get_drvinfo, 2624 .get_link = ethtool_op_get_link, 2625 .get_pauseparam = mlxsw_sp_port_get_pauseparam, 2626 .set_pauseparam = mlxsw_sp_port_set_pauseparam, 2627 .get_strings = mlxsw_sp_port_get_strings, 2628 .set_phys_id = mlxsw_sp_port_set_phys_id, 2629 .get_ethtool_stats = mlxsw_sp_port_get_stats, 2630 .get_sset_count = mlxsw_sp_port_get_sset_count, 2631 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings, 2632 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings, 2633 .flash_device = mlxsw_sp_flash_device, 2634 .get_module_info = mlxsw_sp_get_module_info, 2635 .get_module_eeprom = mlxsw_sp_get_module_eeprom, 2636 }; 2637 2638 static int 2639 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width) 2640 { 2641 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2642 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width; 2643 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2644 u32 eth_proto_admin; 2645 2646 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed); 2647 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2648 eth_proto_admin); 2649 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2650 } 2651 2652 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 2653 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 2654 bool dwrr, u8 dwrr_weight) 2655 { 2656 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2657 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2658 2659 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2660 next_index); 2661 mlxsw_reg_qeec_de_set(qeec_pl, true); 2662 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 2663 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 2664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2665 } 2666 2667 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 2668 enum mlxsw_reg_qeec_hr hr, u8 index, 2669 u8 next_index, u32 maxrate) 2670 { 2671 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2672 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2673 2674 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2675 next_index); 2676 mlxsw_reg_qeec_mase_set(qeec_pl, true); 2677 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 2678 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2679 } 2680 2681 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 2682 u8 switch_prio, u8 tclass) 2683 { 2684 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2685 char qtct_pl[MLXSW_REG_QTCT_LEN]; 2686 2687 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 2688 tclass); 2689 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 2690 } 2691 2692 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 2693 { 2694 int err, i; 2695 2696 /* Setup the elements hierarcy, so that each TC is linked to 2697 * one subgroup, which are all member in the same group. 2698 */ 2699 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2700 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false, 2701 0); 2702 if (err) 2703 return err; 2704 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2705 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2706 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i, 2707 0, false, 0); 2708 if (err) 2709 return err; 2710 } 2711 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2712 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2713 MLXSW_REG_QEEC_HIERARCY_TC, i, i, 2714 false, 0); 2715 if (err) 2716 return err; 2717 } 2718 2719 /* Make sure the max shaper is disabled in all hierarcies that 2720 * support it. 2721 */ 2722 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2723 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0, 2724 MLXSW_REG_QEEC_MAS_DIS); 2725 if (err) 2726 return err; 2727 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2728 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2729 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2730 i, 0, 2731 MLXSW_REG_QEEC_MAS_DIS); 2732 if (err) 2733 return err; 2734 } 2735 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2736 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2737 MLXSW_REG_QEEC_HIERARCY_TC, 2738 i, i, 2739 MLXSW_REG_QEEC_MAS_DIS); 2740 if (err) 2741 return err; 2742 } 2743 2744 /* Map all priorities to traffic class 0. */ 2745 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2746 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 2747 if (err) 2748 return err; 2749 } 2750 2751 return 0; 2752 } 2753 2754 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 2755 bool split, u8 module, u8 width, u8 lane) 2756 { 2757 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 2758 struct mlxsw_sp_port *mlxsw_sp_port; 2759 struct net_device *dev; 2760 int err; 2761 2762 err = mlxsw_core_port_init(mlxsw_sp->core, local_port); 2763 if (err) { 2764 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 2765 local_port); 2766 return err; 2767 } 2768 2769 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 2770 if (!dev) { 2771 err = -ENOMEM; 2772 goto err_alloc_etherdev; 2773 } 2774 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 2775 mlxsw_sp_port = netdev_priv(dev); 2776 mlxsw_sp_port->dev = dev; 2777 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 2778 mlxsw_sp_port->local_port = local_port; 2779 mlxsw_sp_port->pvid = 1; 2780 mlxsw_sp_port->split = split; 2781 mlxsw_sp_port->mapping.module = module; 2782 mlxsw_sp_port->mapping.width = width; 2783 mlxsw_sp_port->mapping.lane = lane; 2784 mlxsw_sp_port->link.autoneg = 1; 2785 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 2786 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list); 2787 2788 mlxsw_sp_port->pcpu_stats = 2789 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 2790 if (!mlxsw_sp_port->pcpu_stats) { 2791 err = -ENOMEM; 2792 goto err_alloc_stats; 2793 } 2794 2795 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample), 2796 GFP_KERNEL); 2797 if (!mlxsw_sp_port->sample) { 2798 err = -ENOMEM; 2799 goto err_alloc_sample; 2800 } 2801 2802 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 2803 &update_stats_cache); 2804 2805 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 2806 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 2807 2808 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); 2809 if (err) { 2810 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 2811 mlxsw_sp_port->local_port); 2812 goto err_port_module_map; 2813 } 2814 2815 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0); 2816 if (err) { 2817 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 2818 mlxsw_sp_port->local_port); 2819 goto err_port_swid_set; 2820 } 2821 2822 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 2823 if (err) { 2824 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 2825 mlxsw_sp_port->local_port); 2826 goto err_dev_addr_init; 2827 } 2828 2829 netif_carrier_off(dev); 2830 2831 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 2832 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2833 dev->hw_features |= NETIF_F_HW_TC; 2834 2835 dev->min_mtu = 0; 2836 dev->max_mtu = ETH_MAX_MTU; 2837 2838 /* Each packet needs to have a Tx header (metadata) on top all other 2839 * headers. 2840 */ 2841 dev->needed_headroom = MLXSW_TXHDR_LEN; 2842 2843 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 2844 if (err) { 2845 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 2846 mlxsw_sp_port->local_port); 2847 goto err_port_system_port_mapping_set; 2848 } 2849 2850 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width); 2851 if (err) { 2852 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 2853 mlxsw_sp_port->local_port); 2854 goto err_port_speed_by_width_set; 2855 } 2856 2857 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 2858 if (err) { 2859 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 2860 mlxsw_sp_port->local_port); 2861 goto err_port_mtu_set; 2862 } 2863 2864 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2865 if (err) 2866 goto err_port_admin_status_set; 2867 2868 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 2869 if (err) { 2870 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 2871 mlxsw_sp_port->local_port); 2872 goto err_port_buffers_init; 2873 } 2874 2875 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 2876 if (err) { 2877 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 2878 mlxsw_sp_port->local_port); 2879 goto err_port_ets_init; 2880 } 2881 2882 /* ETS and buffers must be initialized before DCB. */ 2883 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 2884 if (err) { 2885 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 2886 mlxsw_sp_port->local_port); 2887 goto err_port_dcb_init; 2888 } 2889 2890 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 2891 if (err) { 2892 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 2893 mlxsw_sp_port->local_port); 2894 goto err_port_fids_init; 2895 } 2896 2897 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 2898 if (err) { 2899 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 2900 mlxsw_sp_port->local_port); 2901 goto err_port_qdiscs_init; 2902 } 2903 2904 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 2905 if (IS_ERR(mlxsw_sp_port_vlan)) { 2906 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 2907 mlxsw_sp_port->local_port); 2908 err = PTR_ERR(mlxsw_sp_port_vlan); 2909 goto err_port_vlan_get; 2910 } 2911 2912 mlxsw_sp_port_switchdev_init(mlxsw_sp_port); 2913 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 2914 err = register_netdev(dev); 2915 if (err) { 2916 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 2917 mlxsw_sp_port->local_port); 2918 goto err_register_netdev; 2919 } 2920 2921 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 2922 mlxsw_sp_port, dev, mlxsw_sp_port->split, 2923 module); 2924 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 2925 return 0; 2926 2927 err_register_netdev: 2928 mlxsw_sp->ports[local_port] = NULL; 2929 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 2930 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 2931 err_port_vlan_get: 2932 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 2933 err_port_qdiscs_init: 2934 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 2935 err_port_fids_init: 2936 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 2937 err_port_dcb_init: 2938 err_port_ets_init: 2939 err_port_buffers_init: 2940 err_port_admin_status_set: 2941 err_port_mtu_set: 2942 err_port_speed_by_width_set: 2943 err_port_system_port_mapping_set: 2944 err_dev_addr_init: 2945 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 2946 err_port_swid_set: 2947 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 2948 err_port_module_map: 2949 kfree(mlxsw_sp_port->sample); 2950 err_alloc_sample: 2951 free_percpu(mlxsw_sp_port->pcpu_stats); 2952 err_alloc_stats: 2953 free_netdev(dev); 2954 err_alloc_etherdev: 2955 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 2956 return err; 2957 } 2958 2959 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 2960 { 2961 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2962 2963 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 2964 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 2965 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 2966 mlxsw_sp->ports[local_port] = NULL; 2967 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 2968 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 2969 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 2970 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 2971 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 2972 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 2973 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 2974 kfree(mlxsw_sp_port->sample); 2975 free_percpu(mlxsw_sp_port->pcpu_stats); 2976 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 2977 free_netdev(mlxsw_sp_port->dev); 2978 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 2979 } 2980 2981 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 2982 { 2983 return mlxsw_sp->ports[local_port] != NULL; 2984 } 2985 2986 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 2987 { 2988 int i; 2989 2990 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 2991 if (mlxsw_sp_port_created(mlxsw_sp, i)) 2992 mlxsw_sp_port_remove(mlxsw_sp, i); 2993 kfree(mlxsw_sp->port_to_module); 2994 kfree(mlxsw_sp->ports); 2995 } 2996 2997 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 2998 { 2999 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 3000 u8 module, width, lane; 3001 size_t alloc_size; 3002 int i; 3003 int err; 3004 3005 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 3006 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 3007 if (!mlxsw_sp->ports) 3008 return -ENOMEM; 3009 3010 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int), 3011 GFP_KERNEL); 3012 if (!mlxsw_sp->port_to_module) { 3013 err = -ENOMEM; 3014 goto err_port_to_module_alloc; 3015 } 3016 3017 for (i = 1; i < max_ports; i++) { 3018 /* Mark as invalid */ 3019 mlxsw_sp->port_to_module[i] = -1; 3020 3021 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module, 3022 &width, &lane); 3023 if (err) 3024 goto err_port_module_info_get; 3025 if (!width) 3026 continue; 3027 mlxsw_sp->port_to_module[i] = module; 3028 err = mlxsw_sp_port_create(mlxsw_sp, i, false, 3029 module, width, lane); 3030 if (err) 3031 goto err_port_create; 3032 } 3033 return 0; 3034 3035 err_port_create: 3036 err_port_module_info_get: 3037 for (i--; i >= 1; i--) 3038 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3039 mlxsw_sp_port_remove(mlxsw_sp, i); 3040 kfree(mlxsw_sp->port_to_module); 3041 err_port_to_module_alloc: 3042 kfree(mlxsw_sp->ports); 3043 return err; 3044 } 3045 3046 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port) 3047 { 3048 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX; 3049 3050 return local_port - offset; 3051 } 3052 3053 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port, 3054 u8 module, unsigned int count) 3055 { 3056 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count; 3057 int err, i; 3058 3059 for (i = 0; i < count; i++) { 3060 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true, 3061 module, width, i * width); 3062 if (err) 3063 goto err_port_create; 3064 } 3065 3066 return 0; 3067 3068 err_port_create: 3069 for (i--; i >= 0; i--) 3070 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3071 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3072 return err; 3073 } 3074 3075 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 3076 u8 base_port, unsigned int count) 3077 { 3078 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH; 3079 int i; 3080 3081 /* Split by four means we need to re-create two ports, otherwise 3082 * only one. 3083 */ 3084 count = count / 2; 3085 3086 for (i = 0; i < count; i++) { 3087 local_port = base_port + i * 2; 3088 if (mlxsw_sp->port_to_module[local_port] < 0) 3089 continue; 3090 module = mlxsw_sp->port_to_module[local_port]; 3091 3092 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module, 3093 width, 0); 3094 } 3095 } 3096 3097 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 3098 unsigned int count) 3099 { 3100 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3101 struct mlxsw_sp_port *mlxsw_sp_port; 3102 u8 module, cur_width, base_port; 3103 int i; 3104 int err; 3105 3106 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3107 if (!mlxsw_sp_port) { 3108 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3109 local_port); 3110 return -EINVAL; 3111 } 3112 3113 module = mlxsw_sp_port->mapping.module; 3114 cur_width = mlxsw_sp_port->mapping.width; 3115 3116 if (count != 2 && count != 4) { 3117 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n"); 3118 return -EINVAL; 3119 } 3120 3121 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) { 3122 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n"); 3123 return -EINVAL; 3124 } 3125 3126 /* Make sure we have enough slave (even) ports for the split. */ 3127 if (count == 2) { 3128 base_port = local_port; 3129 if (mlxsw_sp->ports[base_port + 1]) { 3130 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3131 return -EINVAL; 3132 } 3133 } else { 3134 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3135 if (mlxsw_sp->ports[base_port + 1] || 3136 mlxsw_sp->ports[base_port + 3]) { 3137 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3138 return -EINVAL; 3139 } 3140 } 3141 3142 for (i = 0; i < count; i++) 3143 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3144 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3145 3146 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count); 3147 if (err) { 3148 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 3149 goto err_port_split_create; 3150 } 3151 3152 return 0; 3153 3154 err_port_split_create: 3155 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3156 return err; 3157 } 3158 3159 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port) 3160 { 3161 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3162 struct mlxsw_sp_port *mlxsw_sp_port; 3163 u8 cur_width, base_port; 3164 unsigned int count; 3165 int i; 3166 3167 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3168 if (!mlxsw_sp_port) { 3169 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3170 local_port); 3171 return -EINVAL; 3172 } 3173 3174 if (!mlxsw_sp_port->split) { 3175 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n"); 3176 return -EINVAL; 3177 } 3178 3179 cur_width = mlxsw_sp_port->mapping.width; 3180 count = cur_width == 1 ? 4 : 2; 3181 3182 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3183 3184 /* Determine which ports to remove. */ 3185 if (count == 2 && local_port >= base_port + 2) 3186 base_port = base_port + 2; 3187 3188 for (i = 0; i < count; i++) 3189 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3190 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3191 3192 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3193 3194 return 0; 3195 } 3196 3197 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 3198 char *pude_pl, void *priv) 3199 { 3200 struct mlxsw_sp *mlxsw_sp = priv; 3201 struct mlxsw_sp_port *mlxsw_sp_port; 3202 enum mlxsw_reg_pude_oper_status status; 3203 u8 local_port; 3204 3205 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 3206 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3207 if (!mlxsw_sp_port) 3208 return; 3209 3210 status = mlxsw_reg_pude_oper_status_get(pude_pl); 3211 if (status == MLXSW_PORT_OPER_STATUS_UP) { 3212 netdev_info(mlxsw_sp_port->dev, "link up\n"); 3213 netif_carrier_on(mlxsw_sp_port->dev); 3214 } else { 3215 netdev_info(mlxsw_sp_port->dev, "link down\n"); 3216 netif_carrier_off(mlxsw_sp_port->dev); 3217 } 3218 } 3219 3220 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 3221 u8 local_port, void *priv) 3222 { 3223 struct mlxsw_sp *mlxsw_sp = priv; 3224 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3225 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 3226 3227 if (unlikely(!mlxsw_sp_port)) { 3228 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 3229 local_port); 3230 return; 3231 } 3232 3233 skb->dev = mlxsw_sp_port->dev; 3234 3235 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 3236 u64_stats_update_begin(&pcpu_stats->syncp); 3237 pcpu_stats->rx_packets++; 3238 pcpu_stats->rx_bytes += skb->len; 3239 u64_stats_update_end(&pcpu_stats->syncp); 3240 3241 skb->protocol = eth_type_trans(skb, skb->dev); 3242 netif_receive_skb(skb); 3243 } 3244 3245 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 3246 void *priv) 3247 { 3248 skb->offload_fwd_mark = 1; 3249 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3250 } 3251 3252 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb, 3253 u8 local_port, void *priv) 3254 { 3255 skb->offload_mr_fwd_mark = 1; 3256 skb->offload_fwd_mark = 1; 3257 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3258 } 3259 3260 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port, 3261 void *priv) 3262 { 3263 struct mlxsw_sp *mlxsw_sp = priv; 3264 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3265 struct psample_group *psample_group; 3266 u32 size; 3267 3268 if (unlikely(!mlxsw_sp_port)) { 3269 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n", 3270 local_port); 3271 goto out; 3272 } 3273 if (unlikely(!mlxsw_sp_port->sample)) { 3274 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n", 3275 local_port); 3276 goto out; 3277 } 3278 3279 size = mlxsw_sp_port->sample->truncate ? 3280 mlxsw_sp_port->sample->trunc_size : skb->len; 3281 3282 rcu_read_lock(); 3283 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group); 3284 if (!psample_group) 3285 goto out_unlock; 3286 psample_sample_packet(psample_group, skb, size, 3287 mlxsw_sp_port->dev->ifindex, 0, 3288 mlxsw_sp_port->sample->rate); 3289 out_unlock: 3290 rcu_read_unlock(); 3291 out: 3292 consume_skb(skb); 3293 } 3294 3295 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3296 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 3297 _is_ctrl, SP_##_trap_group, DISCARD) 3298 3299 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3300 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 3301 _is_ctrl, SP_##_trap_group, DISCARD) 3302 3303 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3304 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \ 3305 _is_ctrl, SP_##_trap_group, DISCARD) 3306 3307 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 3308 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 3309 3310 static const struct mlxsw_listener mlxsw_sp_listener[] = { 3311 /* Events */ 3312 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 3313 /* L2 traps */ 3314 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true), 3315 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true), 3316 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true), 3317 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false), 3318 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false), 3319 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false), 3320 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false), 3321 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false), 3322 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false), 3323 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false), 3324 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false), 3325 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false), 3326 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD, 3327 false), 3328 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3329 false), 3330 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD, 3331 false), 3332 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3333 false), 3334 /* L3 traps */ 3335 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3336 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3337 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3338 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false), 3339 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 3340 false), 3341 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false), 3342 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 3343 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false), 3344 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP, 3345 false), 3346 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false), 3347 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false), 3348 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false), 3349 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false), 3350 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false), 3351 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false), 3352 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3353 false), 3354 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3355 false), 3356 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3357 false), 3358 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3359 false), 3360 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false), 3361 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 3362 false), 3363 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false), 3364 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false), 3365 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false), 3366 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false), 3367 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3368 /* PKT Sample trap */ 3369 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU, 3370 false, SP_IP2ME, DISCARD), 3371 /* ACL trap */ 3372 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false), 3373 /* Multicast Router Traps */ 3374 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false), 3375 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false), 3376 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 3377 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 3378 }; 3379 3380 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 3381 { 3382 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 3383 enum mlxsw_reg_qpcr_ir_units ir_units; 3384 int max_cpu_policers; 3385 bool is_bytes; 3386 u8 burst_size; 3387 u32 rate; 3388 int i, err; 3389 3390 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 3391 return -EIO; 3392 3393 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3394 3395 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 3396 for (i = 0; i < max_cpu_policers; i++) { 3397 is_bytes = false; 3398 switch (i) { 3399 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3400 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3401 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3402 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3403 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3404 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3405 rate = 128; 3406 burst_size = 7; 3407 break; 3408 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3409 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3410 rate = 16 * 1024; 3411 burst_size = 10; 3412 break; 3413 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3414 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3415 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3417 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3418 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3419 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3420 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3421 rate = 1024; 3422 burst_size = 7; 3423 break; 3424 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3425 is_bytes = true; 3426 rate = 4 * 1024; 3427 burst_size = 4; 3428 break; 3429 default: 3430 continue; 3431 } 3432 3433 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 3434 burst_size); 3435 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 3436 if (err) 3437 return err; 3438 } 3439 3440 return 0; 3441 } 3442 3443 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 3444 { 3445 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3446 enum mlxsw_reg_htgt_trap_group i; 3447 int max_cpu_policers; 3448 int max_trap_groups; 3449 u8 priority, tc; 3450 u16 policer_id; 3451 int err; 3452 3453 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 3454 return -EIO; 3455 3456 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 3457 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3458 3459 for (i = 0; i < max_trap_groups; i++) { 3460 policer_id = i; 3461 switch (i) { 3462 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3463 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3464 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3465 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3466 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3467 priority = 5; 3468 tc = 5; 3469 break; 3470 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3471 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3472 priority = 4; 3473 tc = 4; 3474 break; 3475 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3476 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3477 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3478 priority = 3; 3479 tc = 3; 3480 break; 3481 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3482 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3483 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3484 priority = 2; 3485 tc = 2; 3486 break; 3487 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3488 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3489 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3490 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3491 priority = 1; 3492 tc = 1; 3493 break; 3494 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 3495 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 3496 tc = MLXSW_REG_HTGT_DEFAULT_TC; 3497 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 3498 break; 3499 default: 3500 continue; 3501 } 3502 3503 if (max_cpu_policers <= policer_id && 3504 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 3505 return -EIO; 3506 3507 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 3508 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3509 if (err) 3510 return err; 3511 } 3512 3513 return 0; 3514 } 3515 3516 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 3517 { 3518 int i; 3519 int err; 3520 3521 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 3522 if (err) 3523 return err; 3524 3525 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 3526 if (err) 3527 return err; 3528 3529 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3530 err = mlxsw_core_trap_register(mlxsw_sp->core, 3531 &mlxsw_sp_listener[i], 3532 mlxsw_sp); 3533 if (err) 3534 goto err_listener_register; 3535 3536 } 3537 return 0; 3538 3539 err_listener_register: 3540 for (i--; i >= 0; i--) { 3541 mlxsw_core_trap_unregister(mlxsw_sp->core, 3542 &mlxsw_sp_listener[i], 3543 mlxsw_sp); 3544 } 3545 return err; 3546 } 3547 3548 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 3549 { 3550 int i; 3551 3552 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3553 mlxsw_core_trap_unregister(mlxsw_sp->core, 3554 &mlxsw_sp_listener[i], 3555 mlxsw_sp); 3556 } 3557 } 3558 3559 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 3560 { 3561 char slcr_pl[MLXSW_REG_SLCR_LEN]; 3562 int err; 3563 3564 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 3565 MLXSW_REG_SLCR_LAG_HASH_DMAC | 3566 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 3567 MLXSW_REG_SLCR_LAG_HASH_VLANID | 3568 MLXSW_REG_SLCR_LAG_HASH_SIP | 3569 MLXSW_REG_SLCR_LAG_HASH_DIP | 3570 MLXSW_REG_SLCR_LAG_HASH_SPORT | 3571 MLXSW_REG_SLCR_LAG_HASH_DPORT | 3572 MLXSW_REG_SLCR_LAG_HASH_IPPROTO); 3573 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 3574 if (err) 3575 return err; 3576 3577 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 3578 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 3579 return -EIO; 3580 3581 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 3582 sizeof(struct mlxsw_sp_upper), 3583 GFP_KERNEL); 3584 if (!mlxsw_sp->lags) 3585 return -ENOMEM; 3586 3587 return 0; 3588 } 3589 3590 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 3591 { 3592 kfree(mlxsw_sp->lags); 3593 } 3594 3595 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 3596 { 3597 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3598 3599 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3600 MLXSW_REG_HTGT_INVALID_POLICER, 3601 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 3602 MLXSW_REG_HTGT_DEFAULT_TC); 3603 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3604 } 3605 3606 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 3607 unsigned long event, void *ptr); 3608 3609 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 3610 const struct mlxsw_bus_info *mlxsw_bus_info) 3611 { 3612 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3613 int err; 3614 3615 mlxsw_sp->core = mlxsw_core; 3616 mlxsw_sp->bus_info = mlxsw_bus_info; 3617 3618 err = mlxsw_sp_fw_rev_validate(mlxsw_sp); 3619 if (err) { 3620 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n"); 3621 return err; 3622 } 3623 3624 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3625 if (err) { 3626 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3627 return err; 3628 } 3629 3630 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3631 if (err) { 3632 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3633 return err; 3634 } 3635 3636 err = mlxsw_sp_fids_init(mlxsw_sp); 3637 if (err) { 3638 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3639 goto err_fids_init; 3640 } 3641 3642 err = mlxsw_sp_traps_init(mlxsw_sp); 3643 if (err) { 3644 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3645 goto err_traps_init; 3646 } 3647 3648 err = mlxsw_sp_buffers_init(mlxsw_sp); 3649 if (err) { 3650 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3651 goto err_buffers_init; 3652 } 3653 3654 err = mlxsw_sp_lag_init(mlxsw_sp); 3655 if (err) { 3656 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3657 goto err_lag_init; 3658 } 3659 3660 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3661 if (err) { 3662 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3663 goto err_switchdev_init; 3664 } 3665 3666 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3667 if (err) { 3668 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3669 goto err_counter_pool_init; 3670 } 3671 3672 err = mlxsw_sp_afa_init(mlxsw_sp); 3673 if (err) { 3674 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3675 goto err_afa_init; 3676 } 3677 3678 err = mlxsw_sp_router_init(mlxsw_sp); 3679 if (err) { 3680 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3681 goto err_router_init; 3682 } 3683 3684 /* Initialize netdevice notifier after router is initialized, so that 3685 * the event handler can use router structures. 3686 */ 3687 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3688 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3689 if (err) { 3690 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3691 goto err_netdev_notifier; 3692 } 3693 3694 err = mlxsw_sp_span_init(mlxsw_sp); 3695 if (err) { 3696 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3697 goto err_span_init; 3698 } 3699 3700 err = mlxsw_sp_acl_init(mlxsw_sp); 3701 if (err) { 3702 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3703 goto err_acl_init; 3704 } 3705 3706 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3707 if (err) { 3708 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3709 goto err_dpipe_init; 3710 } 3711 3712 err = mlxsw_sp_ports_create(mlxsw_sp); 3713 if (err) { 3714 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3715 goto err_ports_create; 3716 } 3717 3718 return 0; 3719 3720 err_ports_create: 3721 mlxsw_sp_dpipe_fini(mlxsw_sp); 3722 err_dpipe_init: 3723 mlxsw_sp_acl_fini(mlxsw_sp); 3724 err_acl_init: 3725 mlxsw_sp_span_fini(mlxsw_sp); 3726 err_span_init: 3727 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3728 err_netdev_notifier: 3729 mlxsw_sp_router_fini(mlxsw_sp); 3730 err_router_init: 3731 mlxsw_sp_afa_fini(mlxsw_sp); 3732 err_afa_init: 3733 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3734 err_counter_pool_init: 3735 mlxsw_sp_switchdev_fini(mlxsw_sp); 3736 err_switchdev_init: 3737 mlxsw_sp_lag_fini(mlxsw_sp); 3738 err_lag_init: 3739 mlxsw_sp_buffers_fini(mlxsw_sp); 3740 err_buffers_init: 3741 mlxsw_sp_traps_fini(mlxsw_sp); 3742 err_traps_init: 3743 mlxsw_sp_fids_fini(mlxsw_sp); 3744 err_fids_init: 3745 mlxsw_sp_kvdl_fini(mlxsw_sp); 3746 return err; 3747 } 3748 3749 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3750 { 3751 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3752 3753 mlxsw_sp_ports_remove(mlxsw_sp); 3754 mlxsw_sp_dpipe_fini(mlxsw_sp); 3755 mlxsw_sp_acl_fini(mlxsw_sp); 3756 mlxsw_sp_span_fini(mlxsw_sp); 3757 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3758 mlxsw_sp_router_fini(mlxsw_sp); 3759 mlxsw_sp_afa_fini(mlxsw_sp); 3760 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3761 mlxsw_sp_switchdev_fini(mlxsw_sp); 3762 mlxsw_sp_lag_fini(mlxsw_sp); 3763 mlxsw_sp_buffers_fini(mlxsw_sp); 3764 mlxsw_sp_traps_fini(mlxsw_sp); 3765 mlxsw_sp_fids_fini(mlxsw_sp); 3766 mlxsw_sp_kvdl_fini(mlxsw_sp); 3767 } 3768 3769 static const struct mlxsw_config_profile mlxsw_sp_config_profile = { 3770 .used_max_vepa_channels = 1, 3771 .max_vepa_channels = 0, 3772 .used_max_mid = 1, 3773 .max_mid = MLXSW_SP_MID_MAX, 3774 .used_max_pgt = 1, 3775 .max_pgt = 0, 3776 .used_flood_tables = 1, 3777 .used_flood_mode = 1, 3778 .flood_mode = 3, 3779 .max_fid_offset_flood_tables = 3, 3780 .fid_offset_flood_table_size = VLAN_N_VID - 1, 3781 .max_fid_flood_tables = 3, 3782 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 3783 .used_max_ib_mc = 1, 3784 .max_ib_mc = 0, 3785 .used_max_pkey = 1, 3786 .max_pkey = 0, 3787 .used_kvd_split_data = 1, 3788 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY, 3789 .kvd_hash_single_parts = 59, 3790 .kvd_hash_double_parts = 41, 3791 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3792 .swid_config = { 3793 { 3794 .used_type = 1, 3795 .type = MLXSW_PORT_SWID_TYPE_ETH, 3796 } 3797 }, 3798 .resource_query_enable = 1, 3799 }; 3800 3801 static bool 3802 mlxsw_sp_resource_kvd_granularity_validate(struct netlink_ext_ack *extack, 3803 u64 size) 3804 { 3805 const struct mlxsw_config_profile *profile; 3806 3807 profile = &mlxsw_sp_config_profile; 3808 if (size % profile->kvd_hash_granularity) { 3809 NL_SET_ERR_MSG_MOD(extack, "resource set with wrong granularity"); 3810 return false; 3811 } 3812 return true; 3813 } 3814 3815 static int 3816 mlxsw_sp_resource_kvd_size_validate(struct devlink *devlink, u64 size, 3817 struct netlink_ext_ack *extack) 3818 { 3819 NL_SET_ERR_MSG_MOD(extack, "kvd size cannot be changed"); 3820 return -EINVAL; 3821 } 3822 3823 static int 3824 mlxsw_sp_resource_kvd_linear_size_validate(struct devlink *devlink, u64 size, 3825 struct netlink_ext_ack *extack) 3826 { 3827 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size)) 3828 return -EINVAL; 3829 3830 return 0; 3831 } 3832 3833 static int 3834 mlxsw_sp_resource_kvd_hash_single_size_validate(struct devlink *devlink, u64 size, 3835 struct netlink_ext_ack *extack) 3836 { 3837 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3838 3839 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size)) 3840 return -EINVAL; 3841 3842 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE)) { 3843 NL_SET_ERR_MSG_MOD(extack, "hash single size is smaller than minimum"); 3844 return -EINVAL; 3845 } 3846 return 0; 3847 } 3848 3849 static int 3850 mlxsw_sp_resource_kvd_hash_double_size_validate(struct devlink *devlink, u64 size, 3851 struct netlink_ext_ack *extack) 3852 { 3853 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3854 3855 if (!mlxsw_sp_resource_kvd_granularity_validate(extack, size)) 3856 return -EINVAL; 3857 3858 if (size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) { 3859 NL_SET_ERR_MSG_MOD(extack, "hash double size is smaller than minimum"); 3860 return -EINVAL; 3861 } 3862 return 0; 3863 } 3864 3865 static u64 mlxsw_sp_resource_kvd_linear_occ_get(struct devlink *devlink) 3866 { 3867 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3868 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3869 3870 return mlxsw_sp_kvdl_occ_get(mlxsw_sp); 3871 } 3872 3873 static struct devlink_resource_ops mlxsw_sp_resource_kvd_ops = { 3874 .size_validate = mlxsw_sp_resource_kvd_size_validate, 3875 }; 3876 3877 static struct devlink_resource_ops mlxsw_sp_resource_kvd_linear_ops = { 3878 .size_validate = mlxsw_sp_resource_kvd_linear_size_validate, 3879 .occ_get = mlxsw_sp_resource_kvd_linear_occ_get, 3880 }; 3881 3882 static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_single_ops = { 3883 .size_validate = mlxsw_sp_resource_kvd_hash_single_size_validate, 3884 }; 3885 3886 static struct devlink_resource_ops mlxsw_sp_resource_kvd_hash_double_ops = { 3887 .size_validate = mlxsw_sp_resource_kvd_hash_double_size_validate, 3888 }; 3889 3890 static struct devlink_resource_size_params mlxsw_sp_kvd_size_params; 3891 static struct devlink_resource_size_params mlxsw_sp_linear_size_params; 3892 static struct devlink_resource_size_params mlxsw_sp_hash_single_size_params; 3893 static struct devlink_resource_size_params mlxsw_sp_hash_double_size_params; 3894 3895 static void 3896 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core) 3897 { 3898 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3899 KVD_SINGLE_MIN_SIZE); 3900 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3901 KVD_DOUBLE_MIN_SIZE); 3902 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3903 u32 linear_size_min = 0; 3904 3905 /* KVD top resource */ 3906 mlxsw_sp_kvd_size_params.size_min = kvd_size; 3907 mlxsw_sp_kvd_size_params.size_max = kvd_size; 3908 mlxsw_sp_kvd_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY; 3909 mlxsw_sp_kvd_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY; 3910 3911 /* Linear part init */ 3912 mlxsw_sp_linear_size_params.size_min = linear_size_min; 3913 mlxsw_sp_linear_size_params.size_max = kvd_size - single_size_min - 3914 double_size_min; 3915 mlxsw_sp_linear_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY; 3916 mlxsw_sp_linear_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY; 3917 3918 /* Hash double part init */ 3919 mlxsw_sp_hash_double_size_params.size_min = double_size_min; 3920 mlxsw_sp_hash_double_size_params.size_max = kvd_size - single_size_min - 3921 linear_size_min; 3922 mlxsw_sp_hash_double_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY; 3923 mlxsw_sp_hash_double_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY; 3924 3925 /* Hash single part init */ 3926 mlxsw_sp_hash_single_size_params.size_min = single_size_min; 3927 mlxsw_sp_hash_single_size_params.size_max = kvd_size - double_size_min - 3928 linear_size_min; 3929 mlxsw_sp_hash_single_size_params.size_granularity = MLXSW_SP_KVD_GRANULARITY; 3930 mlxsw_sp_hash_single_size_params.unit = DEVLINK_RESOURCE_UNIT_ENTRY; 3931 } 3932 3933 static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core) 3934 { 3935 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3936 u32 kvd_size, single_size, double_size, linear_size; 3937 const struct mlxsw_config_profile *profile; 3938 int err; 3939 3940 profile = &mlxsw_sp_config_profile; 3941 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3942 return -EIO; 3943 3944 mlxsw_sp_resource_size_params_prepare(mlxsw_core); 3945 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3946 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3947 true, kvd_size, 3948 MLXSW_SP_RESOURCE_KVD, 3949 DEVLINK_RESOURCE_ID_PARENT_TOP, 3950 &mlxsw_sp_kvd_size_params, 3951 &mlxsw_sp_resource_kvd_ops); 3952 if (err) 3953 return err; 3954 3955 linear_size = profile->kvd_linear_size; 3956 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3957 false, linear_size, 3958 MLXSW_SP_RESOURCE_KVD_LINEAR, 3959 MLXSW_SP_RESOURCE_KVD, 3960 &mlxsw_sp_linear_size_params, 3961 &mlxsw_sp_resource_kvd_linear_ops); 3962 if (err) 3963 return err; 3964 3965 double_size = kvd_size - linear_size; 3966 double_size *= profile->kvd_hash_double_parts; 3967 double_size /= profile->kvd_hash_double_parts + 3968 profile->kvd_hash_single_parts; 3969 double_size = rounddown(double_size, profile->kvd_hash_granularity); 3970 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3971 false, double_size, 3972 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3973 MLXSW_SP_RESOURCE_KVD, 3974 &mlxsw_sp_hash_double_size_params, 3975 &mlxsw_sp_resource_kvd_hash_double_ops); 3976 if (err) 3977 return err; 3978 3979 single_size = kvd_size - double_size - linear_size; 3980 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3981 false, single_size, 3982 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3983 MLXSW_SP_RESOURCE_KVD, 3984 &mlxsw_sp_hash_single_size_params, 3985 &mlxsw_sp_resource_kvd_hash_single_ops); 3986 if (err) 3987 return err; 3988 3989 return 0; 3990 } 3991 3992 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3993 const struct mlxsw_config_profile *profile, 3994 u64 *p_single_size, u64 *p_double_size, 3995 u64 *p_linear_size) 3996 { 3997 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3998 u32 double_size; 3999 int err; 4000 4001 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4002 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 4003 !profile->used_kvd_split_data) 4004 return -EIO; 4005 4006 /* The hash part is what left of the kvd without the 4007 * linear part. It is split to the single size and 4008 * double size by the parts ratio from the profile. 4009 * Both sizes must be a multiplications of the 4010 * granularity from the profile. In case the user 4011 * provided the sizes they are obtained via devlink. 4012 */ 4013 err = devlink_resource_size_get(devlink, 4014 MLXSW_SP_RESOURCE_KVD_LINEAR, 4015 p_linear_size); 4016 if (err) 4017 *p_linear_size = profile->kvd_linear_size; 4018 4019 err = devlink_resource_size_get(devlink, 4020 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4021 p_double_size); 4022 if (err) { 4023 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4024 *p_linear_size; 4025 double_size *= profile->kvd_hash_double_parts; 4026 double_size /= profile->kvd_hash_double_parts + 4027 profile->kvd_hash_single_parts; 4028 *p_double_size = rounddown(double_size, 4029 profile->kvd_hash_granularity); 4030 } 4031 4032 err = devlink_resource_size_get(devlink, 4033 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4034 p_single_size); 4035 if (err) 4036 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4037 *p_double_size - *p_linear_size; 4038 4039 /* Check results are legal. */ 4040 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4041 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 4042 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 4043 return -EIO; 4044 4045 return 0; 4046 } 4047 4048 static struct mlxsw_driver mlxsw_sp_driver = { 4049 .kind = mlxsw_sp_driver_name, 4050 .priv_size = sizeof(struct mlxsw_sp), 4051 .init = mlxsw_sp_init, 4052 .fini = mlxsw_sp_fini, 4053 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4054 .port_split = mlxsw_sp_port_split, 4055 .port_unsplit = mlxsw_sp_port_unsplit, 4056 .sb_pool_get = mlxsw_sp_sb_pool_get, 4057 .sb_pool_set = mlxsw_sp_sb_pool_set, 4058 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4059 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4060 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4061 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4062 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4063 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4064 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4065 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4066 .txhdr_construct = mlxsw_sp_txhdr_construct, 4067 .resources_register = mlxsw_sp_resources_register, 4068 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 4069 .txhdr_len = MLXSW_TXHDR_LEN, 4070 .profile = &mlxsw_sp_config_profile, 4071 }; 4072 4073 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 4074 { 4075 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 4076 } 4077 4078 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data) 4079 { 4080 struct mlxsw_sp_port **p_mlxsw_sp_port = data; 4081 int ret = 0; 4082 4083 if (mlxsw_sp_port_dev_check(lower_dev)) { 4084 *p_mlxsw_sp_port = netdev_priv(lower_dev); 4085 ret = 1; 4086 } 4087 4088 return ret; 4089 } 4090 4091 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4092 { 4093 struct mlxsw_sp_port *mlxsw_sp_port; 4094 4095 if (mlxsw_sp_port_dev_check(dev)) 4096 return netdev_priv(dev); 4097 4098 mlxsw_sp_port = NULL; 4099 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port); 4100 4101 return mlxsw_sp_port; 4102 } 4103 4104 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4105 { 4106 struct mlxsw_sp_port *mlxsw_sp_port; 4107 4108 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4109 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4110 } 4111 4112 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4113 { 4114 struct mlxsw_sp_port *mlxsw_sp_port; 4115 4116 if (mlxsw_sp_port_dev_check(dev)) 4117 return netdev_priv(dev); 4118 4119 mlxsw_sp_port = NULL; 4120 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4121 &mlxsw_sp_port); 4122 4123 return mlxsw_sp_port; 4124 } 4125 4126 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4127 { 4128 struct mlxsw_sp_port *mlxsw_sp_port; 4129 4130 rcu_read_lock(); 4131 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4132 if (mlxsw_sp_port) 4133 dev_hold(mlxsw_sp_port->dev); 4134 rcu_read_unlock(); 4135 return mlxsw_sp_port; 4136 } 4137 4138 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4139 { 4140 dev_put(mlxsw_sp_port->dev); 4141 } 4142 4143 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4144 { 4145 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4146 4147 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4148 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4149 } 4150 4151 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4152 { 4153 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4154 4155 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4156 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4157 } 4158 4159 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4160 u16 lag_id, u8 port_index) 4161 { 4162 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4163 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4164 4165 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4166 lag_id, port_index); 4167 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4168 } 4169 4170 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4171 u16 lag_id) 4172 { 4173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4174 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4175 4176 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4177 lag_id); 4178 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4179 } 4180 4181 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4182 u16 lag_id) 4183 { 4184 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4185 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4186 4187 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4188 lag_id); 4189 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4190 } 4191 4192 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4193 u16 lag_id) 4194 { 4195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4196 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4197 4198 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4199 lag_id); 4200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4201 } 4202 4203 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4204 struct net_device *lag_dev, 4205 u16 *p_lag_id) 4206 { 4207 struct mlxsw_sp_upper *lag; 4208 int free_lag_id = -1; 4209 u64 max_lag; 4210 int i; 4211 4212 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 4213 for (i = 0; i < max_lag; i++) { 4214 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4215 if (lag->ref_count) { 4216 if (lag->dev == lag_dev) { 4217 *p_lag_id = i; 4218 return 0; 4219 } 4220 } else if (free_lag_id < 0) { 4221 free_lag_id = i; 4222 } 4223 } 4224 if (free_lag_id < 0) 4225 return -EBUSY; 4226 *p_lag_id = free_lag_id; 4227 return 0; 4228 } 4229 4230 static bool 4231 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4232 struct net_device *lag_dev, 4233 struct netdev_lag_upper_info *lag_upper_info, 4234 struct netlink_ext_ack *extack) 4235 { 4236 u16 lag_id; 4237 4238 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4239 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4240 return false; 4241 } 4242 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4243 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4244 return false; 4245 } 4246 return true; 4247 } 4248 4249 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4250 u16 lag_id, u8 *p_port_index) 4251 { 4252 u64 max_lag_members; 4253 int i; 4254 4255 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4256 MAX_LAG_MEMBERS); 4257 for (i = 0; i < max_lag_members; i++) { 4258 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4259 *p_port_index = i; 4260 return 0; 4261 } 4262 } 4263 return -EBUSY; 4264 } 4265 4266 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4267 struct net_device *lag_dev) 4268 { 4269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4270 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 4271 struct mlxsw_sp_upper *lag; 4272 u16 lag_id; 4273 u8 port_index; 4274 int err; 4275 4276 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4277 if (err) 4278 return err; 4279 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4280 if (!lag->ref_count) { 4281 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4282 if (err) 4283 return err; 4284 lag->dev = lag_dev; 4285 } 4286 4287 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4288 if (err) 4289 return err; 4290 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4291 if (err) 4292 goto err_col_port_add; 4293 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id); 4294 if (err) 4295 goto err_col_port_enable; 4296 4297 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4298 mlxsw_sp_port->local_port); 4299 mlxsw_sp_port->lag_id = lag_id; 4300 mlxsw_sp_port->lagged = 1; 4301 lag->ref_count++; 4302 4303 /* Port is no longer usable as a router interface */ 4304 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1); 4305 if (mlxsw_sp_port_vlan->fid) 4306 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 4307 4308 return 0; 4309 4310 err_col_port_enable: 4311 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4312 err_col_port_add: 4313 if (!lag->ref_count) 4314 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4315 return err; 4316 } 4317 4318 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4319 struct net_device *lag_dev) 4320 { 4321 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4322 u16 lag_id = mlxsw_sp_port->lag_id; 4323 struct mlxsw_sp_upper *lag; 4324 4325 if (!mlxsw_sp_port->lagged) 4326 return; 4327 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4328 WARN_ON(lag->ref_count == 0); 4329 4330 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id); 4331 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4332 4333 /* Any VLANs configured on the port are no longer valid */ 4334 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 4335 4336 if (lag->ref_count == 1) 4337 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4338 4339 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4340 mlxsw_sp_port->local_port); 4341 mlxsw_sp_port->lagged = 0; 4342 lag->ref_count--; 4343 4344 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 4345 /* Make sure untagged frames are allowed to ingress */ 4346 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); 4347 } 4348 4349 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4350 u16 lag_id) 4351 { 4352 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4353 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4354 4355 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4356 mlxsw_sp_port->local_port); 4357 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4358 } 4359 4360 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4361 u16 lag_id) 4362 { 4363 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4364 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4365 4366 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4367 mlxsw_sp_port->local_port); 4368 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4369 } 4370 4371 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port, 4372 bool lag_tx_enabled) 4373 { 4374 if (lag_tx_enabled) 4375 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, 4376 mlxsw_sp_port->lag_id); 4377 else 4378 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4379 mlxsw_sp_port->lag_id); 4380 } 4381 4382 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4383 struct netdev_lag_lower_state_info *info) 4384 { 4385 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled); 4386 } 4387 4388 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4389 bool enable) 4390 { 4391 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4392 enum mlxsw_reg_spms_state spms_state; 4393 char *spms_pl; 4394 u16 vid; 4395 int err; 4396 4397 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4398 MLXSW_REG_SPMS_STATE_DISCARDING; 4399 4400 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4401 if (!spms_pl) 4402 return -ENOMEM; 4403 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4404 4405 for (vid = 0; vid < VLAN_N_VID; vid++) 4406 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4407 4408 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4409 kfree(spms_pl); 4410 return err; 4411 } 4412 4413 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4414 { 4415 u16 vid = 1; 4416 int err; 4417 4418 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4419 if (err) 4420 return err; 4421 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4422 if (err) 4423 goto err_port_stp_set; 4424 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4425 true, false); 4426 if (err) 4427 goto err_port_vlan_set; 4428 4429 for (; vid <= VLAN_N_VID - 1; vid++) { 4430 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4431 vid, false); 4432 if (err) 4433 goto err_vid_learning_set; 4434 } 4435 4436 return 0; 4437 4438 err_vid_learning_set: 4439 for (vid--; vid >= 1; vid--) 4440 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4441 err_port_vlan_set: 4442 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4443 err_port_stp_set: 4444 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4445 return err; 4446 } 4447 4448 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4449 { 4450 u16 vid; 4451 4452 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4453 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4454 vid, true); 4455 4456 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4457 false, false); 4458 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4459 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4460 } 4461 4462 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4463 struct net_device *dev, 4464 unsigned long event, void *ptr) 4465 { 4466 struct netdev_notifier_changeupper_info *info; 4467 struct mlxsw_sp_port *mlxsw_sp_port; 4468 struct netlink_ext_ack *extack; 4469 struct net_device *upper_dev; 4470 struct mlxsw_sp *mlxsw_sp; 4471 int err = 0; 4472 4473 mlxsw_sp_port = netdev_priv(dev); 4474 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4475 info = ptr; 4476 extack = netdev_notifier_info_to_extack(&info->info); 4477 4478 switch (event) { 4479 case NETDEV_PRECHANGEUPPER: 4480 upper_dev = info->upper_dev; 4481 if (!is_vlan_dev(upper_dev) && 4482 !netif_is_lag_master(upper_dev) && 4483 !netif_is_bridge_master(upper_dev) && 4484 !netif_is_ovs_master(upper_dev)) { 4485 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4486 return -EINVAL; 4487 } 4488 if (!info->linking) 4489 break; 4490 if (netdev_has_any_upper_dev(upper_dev) && 4491 (!netif_is_bridge_master(upper_dev) || 4492 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4493 upper_dev))) { 4494 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4495 return -EINVAL; 4496 } 4497 if (netif_is_lag_master(upper_dev) && 4498 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4499 info->upper_info, extack)) 4500 return -EINVAL; 4501 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4502 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4503 return -EINVAL; 4504 } 4505 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4506 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4507 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4508 return -EINVAL; 4509 } 4510 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4511 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4512 return -EINVAL; 4513 } 4514 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4515 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4516 return -EINVAL; 4517 } 4518 break; 4519 case NETDEV_CHANGEUPPER: 4520 upper_dev = info->upper_dev; 4521 if (netif_is_bridge_master(upper_dev)) { 4522 if (info->linking) 4523 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4524 lower_dev, 4525 upper_dev, 4526 extack); 4527 else 4528 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4529 lower_dev, 4530 upper_dev); 4531 } else if (netif_is_lag_master(upper_dev)) { 4532 if (info->linking) 4533 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4534 upper_dev); 4535 else 4536 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4537 upper_dev); 4538 } else if (netif_is_ovs_master(upper_dev)) { 4539 if (info->linking) 4540 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4541 else 4542 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4543 } 4544 break; 4545 } 4546 4547 return err; 4548 } 4549 4550 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4551 unsigned long event, void *ptr) 4552 { 4553 struct netdev_notifier_changelowerstate_info *info; 4554 struct mlxsw_sp_port *mlxsw_sp_port; 4555 int err; 4556 4557 mlxsw_sp_port = netdev_priv(dev); 4558 info = ptr; 4559 4560 switch (event) { 4561 case NETDEV_CHANGELOWERSTATE: 4562 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4563 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4564 info->lower_state_info); 4565 if (err) 4566 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4567 } 4568 break; 4569 } 4570 4571 return 0; 4572 } 4573 4574 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4575 struct net_device *port_dev, 4576 unsigned long event, void *ptr) 4577 { 4578 switch (event) { 4579 case NETDEV_PRECHANGEUPPER: 4580 case NETDEV_CHANGEUPPER: 4581 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4582 event, ptr); 4583 case NETDEV_CHANGELOWERSTATE: 4584 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4585 ptr); 4586 } 4587 4588 return 0; 4589 } 4590 4591 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4592 unsigned long event, void *ptr) 4593 { 4594 struct net_device *dev; 4595 struct list_head *iter; 4596 int ret; 4597 4598 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4599 if (mlxsw_sp_port_dev_check(dev)) { 4600 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4601 ptr); 4602 if (ret) 4603 return ret; 4604 } 4605 } 4606 4607 return 0; 4608 } 4609 4610 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4611 struct net_device *dev, 4612 unsigned long event, void *ptr, 4613 u16 vid) 4614 { 4615 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4616 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4617 struct netdev_notifier_changeupper_info *info = ptr; 4618 struct netlink_ext_ack *extack; 4619 struct net_device *upper_dev; 4620 int err = 0; 4621 4622 extack = netdev_notifier_info_to_extack(&info->info); 4623 4624 switch (event) { 4625 case NETDEV_PRECHANGEUPPER: 4626 upper_dev = info->upper_dev; 4627 if (!netif_is_bridge_master(upper_dev)) { 4628 NL_SET_ERR_MSG_MOD(extack, "VLAN devices only support bridge and VRF uppers"); 4629 return -EINVAL; 4630 } 4631 if (!info->linking) 4632 break; 4633 if (netdev_has_any_upper_dev(upper_dev) && 4634 (!netif_is_bridge_master(upper_dev) || 4635 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4636 upper_dev))) { 4637 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4638 return -EINVAL; 4639 } 4640 break; 4641 case NETDEV_CHANGEUPPER: 4642 upper_dev = info->upper_dev; 4643 if (netif_is_bridge_master(upper_dev)) { 4644 if (info->linking) 4645 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4646 vlan_dev, 4647 upper_dev, 4648 extack); 4649 else 4650 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4651 vlan_dev, 4652 upper_dev); 4653 } else { 4654 err = -EINVAL; 4655 WARN_ON(1); 4656 } 4657 break; 4658 } 4659 4660 return err; 4661 } 4662 4663 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4664 struct net_device *lag_dev, 4665 unsigned long event, 4666 void *ptr, u16 vid) 4667 { 4668 struct net_device *dev; 4669 struct list_head *iter; 4670 int ret; 4671 4672 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4673 if (mlxsw_sp_port_dev_check(dev)) { 4674 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4675 event, ptr, 4676 vid); 4677 if (ret) 4678 return ret; 4679 } 4680 } 4681 4682 return 0; 4683 } 4684 4685 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4686 unsigned long event, void *ptr) 4687 { 4688 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4689 u16 vid = vlan_dev_vlan_id(vlan_dev); 4690 4691 if (mlxsw_sp_port_dev_check(real_dev)) 4692 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 4693 event, ptr, vid); 4694 else if (netif_is_lag_master(real_dev)) 4695 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 4696 real_dev, event, 4697 ptr, vid); 4698 4699 return 0; 4700 } 4701 4702 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 4703 { 4704 struct netdev_notifier_changeupper_info *info = ptr; 4705 4706 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 4707 return false; 4708 return netif_is_l3_master(info->upper_dev); 4709 } 4710 4711 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 4712 unsigned long event, void *ptr) 4713 { 4714 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4715 struct mlxsw_sp *mlxsw_sp; 4716 int err = 0; 4717 4718 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 4719 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 4720 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 4721 event, ptr); 4722 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 4723 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 4724 event, ptr); 4725 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU) 4726 err = mlxsw_sp_netdevice_router_port_event(dev); 4727 else if (mlxsw_sp_is_vrf_event(event, ptr)) 4728 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 4729 else if (mlxsw_sp_port_dev_check(dev)) 4730 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 4731 else if (netif_is_lag_master(dev)) 4732 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 4733 else if (is_vlan_dev(dev)) 4734 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 4735 4736 return notifier_from_errno(err); 4737 } 4738 4739 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 4740 .notifier_call = mlxsw_sp_inetaddr_valid_event, 4741 }; 4742 4743 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = { 4744 .notifier_call = mlxsw_sp_inetaddr_event, 4745 }; 4746 4747 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 4748 .notifier_call = mlxsw_sp_inet6addr_valid_event, 4749 }; 4750 4751 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = { 4752 .notifier_call = mlxsw_sp_inet6addr_event, 4753 }; 4754 4755 static const struct pci_device_id mlxsw_sp_pci_id_table[] = { 4756 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 4757 {0, }, 4758 }; 4759 4760 static struct pci_driver mlxsw_sp_pci_driver = { 4761 .name = mlxsw_sp_driver_name, 4762 .id_table = mlxsw_sp_pci_id_table, 4763 }; 4764 4765 static int __init mlxsw_sp_module_init(void) 4766 { 4767 int err; 4768 4769 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4770 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4771 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4772 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4773 4774 err = mlxsw_core_driver_register(&mlxsw_sp_driver); 4775 if (err) 4776 goto err_core_driver_register; 4777 4778 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver); 4779 if (err) 4780 goto err_pci_driver_register; 4781 4782 return 0; 4783 4784 err_pci_driver_register: 4785 mlxsw_core_driver_unregister(&mlxsw_sp_driver); 4786 err_core_driver_register: 4787 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4788 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4789 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4790 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4791 return err; 4792 } 4793 4794 static void __exit mlxsw_sp_module_exit(void) 4795 { 4796 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver); 4797 mlxsw_core_driver_unregister(&mlxsw_sp_driver); 4798 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4799 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4800 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4801 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4802 } 4803 4804 module_init(mlxsw_sp_module_init); 4805 module_exit(mlxsw_sp_module_exit); 4806 4807 MODULE_LICENSE("Dual BSD/GPL"); 4808 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 4809 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 4810 MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table); 4811 MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME); 4812