1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/jhash.h> 25 #include <linux/log2.h> 26 #include <linux/refcount.h> 27 #include <linux/rhashtable.h> 28 #include <net/switchdev.h> 29 #include <net/pkt_cls.h> 30 #include <net/netevent.h> 31 #include <net/addrconf.h> 32 33 #include "spectrum.h" 34 #include "pci.h" 35 #include "core.h" 36 #include "core_env.h" 37 #include "reg.h" 38 #include "port.h" 39 #include "trap.h" 40 #include "txheader.h" 41 #include "spectrum_cnt.h" 42 #include "spectrum_dpipe.h" 43 #include "spectrum_acl_flex_actions.h" 44 #include "spectrum_span.h" 45 #include "spectrum_ptp.h" 46 #include "spectrum_trap.h" 47 48 #define MLXSW_SP1_FWREV_MAJOR 13 49 #define MLXSW_SP1_FWREV_MINOR 2008 50 #define MLXSW_SP1_FWREV_SUBMINOR 3326 51 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 52 53 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 54 .major = MLXSW_SP1_FWREV_MAJOR, 55 .minor = MLXSW_SP1_FWREV_MINOR, 56 .subminor = MLXSW_SP1_FWREV_SUBMINOR, 57 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 58 }; 59 60 #define MLXSW_SP1_FW_FILENAME \ 61 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 62 "." __stringify(MLXSW_SP1_FWREV_MINOR) \ 63 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2" 64 65 #define MLXSW_SP2_FWREV_MAJOR 29 66 #define MLXSW_SP2_FWREV_MINOR 2008 67 #define MLXSW_SP2_FWREV_SUBMINOR 3326 68 69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = { 70 .major = MLXSW_SP2_FWREV_MAJOR, 71 .minor = MLXSW_SP2_FWREV_MINOR, 72 .subminor = MLXSW_SP2_FWREV_SUBMINOR, 73 }; 74 75 #define MLXSW_SP2_FW_FILENAME \ 76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \ 77 "." __stringify(MLXSW_SP2_FWREV_MINOR) \ 78 "." __stringify(MLXSW_SP2_FWREV_SUBMINOR) ".mfa2" 79 80 #define MLXSW_SP3_FWREV_MAJOR 30 81 #define MLXSW_SP3_FWREV_MINOR 2008 82 #define MLXSW_SP3_FWREV_SUBMINOR 3326 83 84 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = { 85 .major = MLXSW_SP3_FWREV_MAJOR, 86 .minor = MLXSW_SP3_FWREV_MINOR, 87 .subminor = MLXSW_SP3_FWREV_SUBMINOR, 88 }; 89 90 #define MLXSW_SP3_FW_FILENAME \ 91 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \ 92 "." __stringify(MLXSW_SP3_FWREV_MINOR) \ 93 "." __stringify(MLXSW_SP3_FWREV_SUBMINOR) ".mfa2" 94 95 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 96 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 97 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3"; 98 99 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = { 100 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00 101 }; 102 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = { 103 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00 104 }; 105 106 /* tx_hdr_version 107 * Tx header version. 108 * Must be set to 1. 109 */ 110 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 111 112 /* tx_hdr_ctl 113 * Packet control type. 114 * 0 - Ethernet control (e.g. EMADs, LACP) 115 * 1 - Ethernet data 116 */ 117 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 118 119 /* tx_hdr_proto 120 * Packet protocol type. Must be set to 1 (Ethernet). 121 */ 122 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 123 124 /* tx_hdr_rx_is_router 125 * Packet is sent from the router. Valid for data packets only. 126 */ 127 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 128 129 /* tx_hdr_fid_valid 130 * Indicates if the 'fid' field is valid and should be used for 131 * forwarding lookup. Valid for data packets only. 132 */ 133 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 134 135 /* tx_hdr_swid 136 * Switch partition ID. Must be set to 0. 137 */ 138 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 139 140 /* tx_hdr_control_tclass 141 * Indicates if the packet should use the control TClass and not one 142 * of the data TClasses. 143 */ 144 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 145 146 /* tx_hdr_etclass 147 * Egress TClass to be used on the egress device on the egress port. 148 */ 149 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 150 151 /* tx_hdr_port_mid 152 * Destination local port for unicast packets. 153 * Destination multicast ID for multicast packets. 154 * 155 * Control packets are directed to a specific egress port, while data 156 * packets are transmitted through the CPU port (0) into the switch partition, 157 * where forwarding rules are applied. 158 */ 159 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 160 161 /* tx_hdr_fid 162 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 163 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 164 * Valid for data packets only. 165 */ 166 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 167 168 /* tx_hdr_type 169 * 0 - Data packets 170 * 6 - Control packets 171 */ 172 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 173 174 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 175 unsigned int counter_index, u64 *packets, 176 u64 *bytes) 177 { 178 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 179 int err; 180 181 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 182 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 183 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 184 if (err) 185 return err; 186 if (packets) 187 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 188 if (bytes) 189 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 190 return 0; 191 } 192 193 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 194 unsigned int counter_index) 195 { 196 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 197 198 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 199 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 201 } 202 203 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 204 unsigned int *p_counter_index) 205 { 206 int err; 207 208 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 209 p_counter_index); 210 if (err) 211 return err; 212 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 213 if (err) 214 goto err_counter_clear; 215 return 0; 216 217 err_counter_clear: 218 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 219 *p_counter_index); 220 return err; 221 } 222 223 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 224 unsigned int counter_index) 225 { 226 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 227 counter_index); 228 } 229 230 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 231 const struct mlxsw_tx_info *tx_info) 232 { 233 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 234 235 memset(txhdr, 0, MLXSW_TXHDR_LEN); 236 237 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 238 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 239 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 240 mlxsw_tx_hdr_swid_set(txhdr, 0); 241 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 242 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 243 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 244 } 245 246 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 247 { 248 switch (state) { 249 case BR_STATE_FORWARDING: 250 return MLXSW_REG_SPMS_STATE_FORWARDING; 251 case BR_STATE_LEARNING: 252 return MLXSW_REG_SPMS_STATE_LEARNING; 253 case BR_STATE_LISTENING: 254 case BR_STATE_DISABLED: 255 case BR_STATE_BLOCKING: 256 return MLXSW_REG_SPMS_STATE_DISCARDING; 257 default: 258 BUG(); 259 } 260 } 261 262 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 263 u8 state) 264 { 265 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 266 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 267 char *spms_pl; 268 int err; 269 270 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 271 if (!spms_pl) 272 return -ENOMEM; 273 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 274 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 275 276 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 277 kfree(spms_pl); 278 return err; 279 } 280 281 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 282 { 283 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 284 int err; 285 286 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 287 if (err) 288 return err; 289 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 290 return 0; 291 } 292 293 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 294 bool is_up) 295 { 296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 297 char paos_pl[MLXSW_REG_PAOS_LEN]; 298 299 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 300 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 301 MLXSW_PORT_ADMIN_STATUS_DOWN); 302 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 303 } 304 305 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 306 unsigned char *addr) 307 { 308 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 309 char ppad_pl[MLXSW_REG_PPAD_LEN]; 310 311 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 312 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 313 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 314 } 315 316 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 317 { 318 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 319 320 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac, 321 mlxsw_sp_port->local_port); 322 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, 323 mlxsw_sp_port->dev->dev_addr); 324 } 325 326 static int mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port *mlxsw_sp_port, int *p_max_mtu) 327 { 328 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 329 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 330 int err; 331 332 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 333 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 334 if (err) 335 return err; 336 337 *p_max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 338 return 0; 339 } 340 341 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 342 { 343 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 344 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 345 346 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 347 if (mtu > mlxsw_sp_port->max_mtu) 348 return -EINVAL; 349 350 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 351 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 352 } 353 354 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, 355 u8 local_port, u8 swid) 356 { 357 char pspa_pl[MLXSW_REG_PSPA_LEN]; 358 359 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port); 360 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 361 } 362 363 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 364 { 365 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 366 char svpe_pl[MLXSW_REG_SVPE_LEN]; 367 368 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 369 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 370 } 371 372 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 373 bool learn_enable) 374 { 375 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 376 char *spvmlr_pl; 377 int err; 378 379 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 380 if (!spvmlr_pl) 381 return -ENOMEM; 382 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 383 learn_enable); 384 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 385 kfree(spvmlr_pl); 386 return err; 387 } 388 389 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type) 390 { 391 switch (ethtype) { 392 case ETH_P_8021Q: 393 *p_sver_type = 0; 394 break; 395 case ETH_P_8021AD: 396 *p_sver_type = 1; 397 break; 398 default: 399 return -EINVAL; 400 } 401 402 return 0; 403 } 404 405 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port, 406 u16 ethtype) 407 { 408 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 409 char spevet_pl[MLXSW_REG_SPEVET_LEN]; 410 u8 sver_type; 411 int err; 412 413 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 414 if (err) 415 return err; 416 417 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type); 418 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl); 419 } 420 421 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 422 u16 vid, u16 ethtype) 423 { 424 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 425 char spvid_pl[MLXSW_REG_SPVID_LEN]; 426 u8 sver_type; 427 int err; 428 429 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 430 if (err) 431 return err; 432 433 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid, 434 sver_type); 435 436 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 437 } 438 439 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 440 bool allow) 441 { 442 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 443 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 444 445 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 446 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 447 } 448 449 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 450 u16 ethtype) 451 { 452 int err; 453 454 if (!vid) { 455 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 456 if (err) 457 return err; 458 } else { 459 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype); 460 if (err) 461 return err; 462 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 463 if (err) 464 goto err_port_allow_untagged_set; 465 } 466 467 mlxsw_sp_port->pvid = vid; 468 return 0; 469 470 err_port_allow_untagged_set: 471 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype); 472 return err; 473 } 474 475 static int 476 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 477 { 478 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 479 char sspr_pl[MLXSW_REG_SSPR_LEN]; 480 481 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 482 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 483 } 484 485 static int 486 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u8 local_port, 487 struct mlxsw_sp_port_mapping *port_mapping) 488 { 489 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 490 bool separate_rxtx; 491 u8 module; 492 u8 width; 493 int err; 494 int i; 495 496 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 497 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 498 if (err) 499 return err; 500 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 501 width = mlxsw_reg_pmlp_width_get(pmlp_pl); 502 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl); 503 504 if (width && !is_power_of_2(width)) { 505 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n", 506 local_port); 507 return -EINVAL; 508 } 509 510 for (i = 0; i < width; i++) { 511 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) { 512 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n", 513 local_port); 514 return -EINVAL; 515 } 516 if (separate_rxtx && 517 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != 518 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) { 519 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n", 520 local_port); 521 return -EINVAL; 522 } 523 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i) { 524 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n", 525 local_port); 526 return -EINVAL; 527 } 528 } 529 530 port_mapping->module = module; 531 port_mapping->width = width; 532 port_mapping->module_width = width; 533 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 534 return 0; 535 } 536 537 static int 538 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port, 539 const struct mlxsw_sp_port_mapping *port_mapping) 540 { 541 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 542 int i, err; 543 544 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->module); 545 546 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 547 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width); 548 for (i = 0; i < port_mapping->width; i++) { 549 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module); 550 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */ 551 } 552 553 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 554 if (err) 555 goto err_pmlp_write; 556 return 0; 557 558 err_pmlp_write: 559 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->module); 560 return err; 561 } 562 563 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port, 564 u8 module) 565 { 566 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 567 568 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 569 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 570 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 571 mlxsw_env_module_port_unmap(mlxsw_sp->core, module); 572 } 573 574 static int mlxsw_sp_port_open(struct net_device *dev) 575 { 576 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 577 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 578 int err; 579 580 err = mlxsw_env_module_port_up(mlxsw_sp->core, 581 mlxsw_sp_port->mapping.module); 582 if (err) 583 return err; 584 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 585 if (err) 586 goto err_port_admin_status_set; 587 netif_start_queue(dev); 588 return 0; 589 590 err_port_admin_status_set: 591 mlxsw_env_module_port_down(mlxsw_sp->core, 592 mlxsw_sp_port->mapping.module); 593 return err; 594 } 595 596 static int mlxsw_sp_port_stop(struct net_device *dev) 597 { 598 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 600 601 netif_stop_queue(dev); 602 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 603 mlxsw_env_module_port_down(mlxsw_sp->core, 604 mlxsw_sp_port->mapping.module); 605 return 0; 606 } 607 608 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 609 struct net_device *dev) 610 { 611 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 612 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 613 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 614 const struct mlxsw_tx_info tx_info = { 615 .local_port = mlxsw_sp_port->local_port, 616 .is_emad = false, 617 }; 618 u64 len; 619 int err; 620 621 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) { 622 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 623 dev_kfree_skb_any(skb); 624 return NETDEV_TX_OK; 625 } 626 627 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb)); 628 629 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 630 return NETDEV_TX_BUSY; 631 632 if (eth_skb_pad(skb)) { 633 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 634 return NETDEV_TX_OK; 635 } 636 637 mlxsw_sp_txhdr_construct(skb, &tx_info); 638 /* TX header is consumed by HW on the way so we shouldn't count its 639 * bytes as being sent. 640 */ 641 len = skb->len - MLXSW_TXHDR_LEN; 642 643 /* Due to a race we might fail here because of a full queue. In that 644 * unlikely case we simply drop the packet. 645 */ 646 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 647 648 if (!err) { 649 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 650 u64_stats_update_begin(&pcpu_stats->syncp); 651 pcpu_stats->tx_packets++; 652 pcpu_stats->tx_bytes += len; 653 u64_stats_update_end(&pcpu_stats->syncp); 654 } else { 655 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 656 dev_kfree_skb_any(skb); 657 } 658 return NETDEV_TX_OK; 659 } 660 661 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 662 { 663 } 664 665 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 666 { 667 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 668 struct sockaddr *addr = p; 669 int err; 670 671 if (!is_valid_ether_addr(addr->sa_data)) 672 return -EADDRNOTAVAIL; 673 674 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 675 if (err) 676 return err; 677 eth_hw_addr_set(dev, addr->sa_data); 678 return 0; 679 } 680 681 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 682 { 683 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 684 struct mlxsw_sp_hdroom orig_hdroom; 685 struct mlxsw_sp_hdroom hdroom; 686 int err; 687 688 orig_hdroom = *mlxsw_sp_port->hdroom; 689 690 hdroom = orig_hdroom; 691 hdroom.mtu = mtu; 692 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom); 693 694 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom); 695 if (err) { 696 netdev_err(dev, "Failed to configure port's headroom\n"); 697 return err; 698 } 699 700 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 701 if (err) 702 goto err_port_mtu_set; 703 dev->mtu = mtu; 704 return 0; 705 706 err_port_mtu_set: 707 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom); 708 return err; 709 } 710 711 static int 712 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 713 struct rtnl_link_stats64 *stats) 714 { 715 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 716 struct mlxsw_sp_port_pcpu_stats *p; 717 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 718 u32 tx_dropped = 0; 719 unsigned int start; 720 int i; 721 722 for_each_possible_cpu(i) { 723 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 724 do { 725 start = u64_stats_fetch_begin_irq(&p->syncp); 726 rx_packets = p->rx_packets; 727 rx_bytes = p->rx_bytes; 728 tx_packets = p->tx_packets; 729 tx_bytes = p->tx_bytes; 730 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 731 732 stats->rx_packets += rx_packets; 733 stats->rx_bytes += rx_bytes; 734 stats->tx_packets += tx_packets; 735 stats->tx_bytes += tx_bytes; 736 /* tx_dropped is u32, updated without syncp protection. */ 737 tx_dropped += p->tx_dropped; 738 } 739 stats->tx_dropped = tx_dropped; 740 return 0; 741 } 742 743 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 744 { 745 switch (attr_id) { 746 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 747 return true; 748 } 749 750 return false; 751 } 752 753 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 754 void *sp) 755 { 756 switch (attr_id) { 757 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 758 return mlxsw_sp_port_get_sw_stats64(dev, sp); 759 } 760 761 return -EINVAL; 762 } 763 764 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 765 int prio, char *ppcnt_pl) 766 { 767 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 768 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 769 770 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 771 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 772 } 773 774 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 775 struct rtnl_link_stats64 *stats) 776 { 777 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 778 int err; 779 780 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 781 0, ppcnt_pl); 782 if (err) 783 goto out; 784 785 stats->tx_packets = 786 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 787 stats->rx_packets = 788 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 789 stats->tx_bytes = 790 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 791 stats->rx_bytes = 792 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 793 stats->multicast = 794 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 795 796 stats->rx_crc_errors = 797 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 798 stats->rx_frame_errors = 799 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 800 801 stats->rx_length_errors = ( 802 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 803 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 804 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 805 806 stats->rx_errors = (stats->rx_crc_errors + 807 stats->rx_frame_errors + stats->rx_length_errors); 808 809 out: 810 return err; 811 } 812 813 static void 814 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 815 struct mlxsw_sp_port_xstats *xstats) 816 { 817 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 818 int err, i; 819 820 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 821 ppcnt_pl); 822 if (!err) 823 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 824 825 for (i = 0; i < TC_MAX_QUEUE; i++) { 826 err = mlxsw_sp_port_get_stats_raw(dev, 827 MLXSW_REG_PPCNT_TC_CONG_CNT, 828 i, ppcnt_pl); 829 if (err) 830 goto tc_cnt; 831 832 xstats->wred_drop[i] = 833 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 834 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl); 835 836 tc_cnt: 837 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 838 i, ppcnt_pl); 839 if (err) 840 continue; 841 842 xstats->backlog[i] = 843 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 844 xstats->tail_drop[i] = 845 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 846 } 847 848 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 849 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 850 i, ppcnt_pl); 851 if (err) 852 continue; 853 854 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 855 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 856 } 857 } 858 859 static void update_stats_cache(struct work_struct *work) 860 { 861 struct mlxsw_sp_port *mlxsw_sp_port = 862 container_of(work, struct mlxsw_sp_port, 863 periodic_hw_stats.update_dw.work); 864 865 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 866 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as 867 * necessary when port goes down. 868 */ 869 goto out; 870 871 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 872 &mlxsw_sp_port->periodic_hw_stats.stats); 873 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 874 &mlxsw_sp_port->periodic_hw_stats.xstats); 875 876 out: 877 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 878 MLXSW_HW_STATS_UPDATE_TIME); 879 } 880 881 /* Return the stats from a cache that is updated periodically, 882 * as this function might get called in an atomic context. 883 */ 884 static void 885 mlxsw_sp_port_get_stats64(struct net_device *dev, 886 struct rtnl_link_stats64 *stats) 887 { 888 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 889 890 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 891 } 892 893 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 894 u16 vid_begin, u16 vid_end, 895 bool is_member, bool untagged) 896 { 897 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 898 char *spvm_pl; 899 int err; 900 901 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 902 if (!spvm_pl) 903 return -ENOMEM; 904 905 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 906 vid_end, is_member, untagged); 907 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 908 kfree(spvm_pl); 909 return err; 910 } 911 912 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 913 u16 vid_end, bool is_member, bool untagged) 914 { 915 u16 vid, vid_e; 916 int err; 917 918 for (vid = vid_begin; vid <= vid_end; 919 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 920 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 921 vid_end); 922 923 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 924 is_member, untagged); 925 if (err) 926 return err; 927 } 928 929 return 0; 930 } 931 932 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port, 933 bool flush_default) 934 { 935 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 936 937 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 938 &mlxsw_sp_port->vlans_list, list) { 939 if (!flush_default && 940 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID) 941 continue; 942 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 943 } 944 } 945 946 static void 947 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 948 { 949 if (mlxsw_sp_port_vlan->bridge_port) 950 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 951 else if (mlxsw_sp_port_vlan->fid) 952 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 953 } 954 955 struct mlxsw_sp_port_vlan * 956 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 957 { 958 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 959 bool untagged = vid == MLXSW_SP_DEFAULT_VID; 960 int err; 961 962 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 963 if (mlxsw_sp_port_vlan) 964 return ERR_PTR(-EEXIST); 965 966 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 967 if (err) 968 return ERR_PTR(err); 969 970 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 971 if (!mlxsw_sp_port_vlan) { 972 err = -ENOMEM; 973 goto err_port_vlan_alloc; 974 } 975 976 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 977 mlxsw_sp_port_vlan->vid = vid; 978 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 979 980 return mlxsw_sp_port_vlan; 981 982 err_port_vlan_alloc: 983 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 984 return ERR_PTR(err); 985 } 986 987 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 988 { 989 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 990 u16 vid = mlxsw_sp_port_vlan->vid; 991 992 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan); 993 list_del(&mlxsw_sp_port_vlan->list); 994 kfree(mlxsw_sp_port_vlan); 995 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 996 } 997 998 static int mlxsw_sp_port_add_vid(struct net_device *dev, 999 __be16 __always_unused proto, u16 vid) 1000 { 1001 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1002 1003 /* VLAN 0 is added to HW filter when device goes up, but it is 1004 * reserved in our case, so simply return. 1005 */ 1006 if (!vid) 1007 return 0; 1008 1009 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid)); 1010 } 1011 1012 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1013 __be16 __always_unused proto, u16 vid) 1014 { 1015 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1016 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1017 1018 /* VLAN 0 is removed from HW filter when device goes down, but 1019 * it is reserved in our case, so simply return. 1020 */ 1021 if (!vid) 1022 return 0; 1023 1024 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1025 if (!mlxsw_sp_port_vlan) 1026 return 0; 1027 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1028 1029 return 0; 1030 } 1031 1032 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1033 struct flow_block_offload *f) 1034 { 1035 switch (f->binder_type) { 1036 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS: 1037 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true); 1038 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS: 1039 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false); 1040 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP: 1041 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f); 1042 case FLOW_BLOCK_BINDER_TYPE_RED_MARK: 1043 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f); 1044 default: 1045 return -EOPNOTSUPP; 1046 } 1047 } 1048 1049 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1050 void *type_data) 1051 { 1052 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1053 1054 switch (type) { 1055 case TC_SETUP_BLOCK: 1056 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1057 case TC_SETUP_QDISC_RED: 1058 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1059 case TC_SETUP_QDISC_PRIO: 1060 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1061 case TC_SETUP_QDISC_ETS: 1062 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data); 1063 case TC_SETUP_QDISC_TBF: 1064 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data); 1065 case TC_SETUP_QDISC_FIFO: 1066 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data); 1067 default: 1068 return -EOPNOTSUPP; 1069 } 1070 } 1071 1072 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1073 { 1074 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1075 1076 if (!enable) { 1077 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) || 1078 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) { 1079 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1080 return -EINVAL; 1081 } 1082 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block); 1083 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block); 1084 } else { 1085 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block); 1086 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block); 1087 } 1088 return 0; 1089 } 1090 1091 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable) 1092 { 1093 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1094 char pplr_pl[MLXSW_REG_PPLR_LEN]; 1095 int err; 1096 1097 if (netif_running(dev)) 1098 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1099 1100 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable); 1101 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr), 1102 pplr_pl); 1103 1104 if (netif_running(dev)) 1105 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 1106 1107 return err; 1108 } 1109 1110 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1111 1112 static int mlxsw_sp_handle_feature(struct net_device *dev, 1113 netdev_features_t wanted_features, 1114 netdev_features_t feature, 1115 mlxsw_sp_feature_handler feature_handler) 1116 { 1117 netdev_features_t changes = wanted_features ^ dev->features; 1118 bool enable = !!(wanted_features & feature); 1119 int err; 1120 1121 if (!(changes & feature)) 1122 return 0; 1123 1124 err = feature_handler(dev, enable); 1125 if (err) { 1126 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1127 enable ? "Enable" : "Disable", &feature, err); 1128 return err; 1129 } 1130 1131 if (enable) 1132 dev->features |= feature; 1133 else 1134 dev->features &= ~feature; 1135 1136 return 0; 1137 } 1138 static int mlxsw_sp_set_features(struct net_device *dev, 1139 netdev_features_t features) 1140 { 1141 netdev_features_t oper_features = dev->features; 1142 int err = 0; 1143 1144 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1145 mlxsw_sp_feature_hw_tc); 1146 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK, 1147 mlxsw_sp_feature_loopback); 1148 1149 if (err) { 1150 dev->features = oper_features; 1151 return -EINVAL; 1152 } 1153 1154 return 0; 1155 } 1156 1157 static struct devlink_port * 1158 mlxsw_sp_port_get_devlink_port(struct net_device *dev) 1159 { 1160 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1161 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1162 1163 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core, 1164 mlxsw_sp_port->local_port); 1165 } 1166 1167 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port, 1168 struct ifreq *ifr) 1169 { 1170 struct hwtstamp_config config; 1171 int err; 1172 1173 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1174 return -EFAULT; 1175 1176 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, 1177 &config); 1178 if (err) 1179 return err; 1180 1181 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 1182 return -EFAULT; 1183 1184 return 0; 1185 } 1186 1187 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port, 1188 struct ifreq *ifr) 1189 { 1190 struct hwtstamp_config config; 1191 int err; 1192 1193 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port, 1194 &config); 1195 if (err) 1196 return err; 1197 1198 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 1199 return -EFAULT; 1200 1201 return 0; 1202 } 1203 1204 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port) 1205 { 1206 struct hwtstamp_config config = {0}; 1207 1208 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config); 1209 } 1210 1211 static int 1212 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1213 { 1214 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1215 1216 switch (cmd) { 1217 case SIOCSHWTSTAMP: 1218 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr); 1219 case SIOCGHWTSTAMP: 1220 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr); 1221 default: 1222 return -EOPNOTSUPP; 1223 } 1224 } 1225 1226 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1227 .ndo_open = mlxsw_sp_port_open, 1228 .ndo_stop = mlxsw_sp_port_stop, 1229 .ndo_start_xmit = mlxsw_sp_port_xmit, 1230 .ndo_setup_tc = mlxsw_sp_setup_tc, 1231 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1232 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1233 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1234 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1235 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1236 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1237 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1238 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1239 .ndo_set_features = mlxsw_sp_set_features, 1240 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port, 1241 .ndo_eth_ioctl = mlxsw_sp_port_ioctl, 1242 }; 1243 1244 static int 1245 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port) 1246 { 1247 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1248 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper; 1249 const struct mlxsw_sp_port_type_speed_ops *ops; 1250 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1251 u32 eth_proto_cap_masked; 1252 int err; 1253 1254 ops = mlxsw_sp->port_type_speed_ops; 1255 1256 /* Set advertised speeds to speeds supported by both the driver 1257 * and the device. 1258 */ 1259 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1260 0, false); 1261 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1262 if (err) 1263 return err; 1264 1265 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, 1266 ð_proto_admin, ð_proto_oper); 1267 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap); 1268 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1269 eth_proto_cap_masked, 1270 mlxsw_sp_port->link.autoneg); 1271 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1272 } 1273 1274 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed) 1275 { 1276 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops; 1277 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1278 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1279 u32 eth_proto_oper; 1280 int err; 1281 1282 port_type_speed_ops = mlxsw_sp->port_type_speed_ops; 1283 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, 1284 mlxsw_sp_port->local_port, 0, 1285 false); 1286 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1287 if (err) 1288 return err; 1289 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL, 1290 ð_proto_oper); 1291 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper); 1292 return 0; 1293 } 1294 1295 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 1296 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 1297 bool dwrr, u8 dwrr_weight) 1298 { 1299 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1300 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1301 1302 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1303 next_index); 1304 mlxsw_reg_qeec_de_set(qeec_pl, true); 1305 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 1306 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 1307 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1308 } 1309 1310 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 1311 enum mlxsw_reg_qeec_hr hr, u8 index, 1312 u8 next_index, u32 maxrate, u8 burst_size) 1313 { 1314 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1315 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1316 1317 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1318 next_index); 1319 mlxsw_reg_qeec_mase_set(qeec_pl, true); 1320 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 1321 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size); 1322 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1323 } 1324 1325 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 1326 enum mlxsw_reg_qeec_hr hr, u8 index, 1327 u8 next_index, u32 minrate) 1328 { 1329 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1330 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1331 1332 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1333 next_index); 1334 mlxsw_reg_qeec_mise_set(qeec_pl, true); 1335 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 1336 1337 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1338 } 1339 1340 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 1341 u8 switch_prio, u8 tclass) 1342 { 1343 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1344 char qtct_pl[MLXSW_REG_QTCT_LEN]; 1345 1346 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 1347 tclass); 1348 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 1349 } 1350 1351 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 1352 { 1353 int err, i; 1354 1355 /* Setup the elements hierarcy, so that each TC is linked to 1356 * one subgroup, which are all member in the same group. 1357 */ 1358 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1359 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0); 1360 if (err) 1361 return err; 1362 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1363 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1364 MLXSW_REG_QEEC_HR_SUBGROUP, i, 1365 0, false, 0); 1366 if (err) 1367 return err; 1368 } 1369 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1370 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1371 MLXSW_REG_QEEC_HR_TC, i, i, 1372 false, 0); 1373 if (err) 1374 return err; 1375 1376 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1377 MLXSW_REG_QEEC_HR_TC, 1378 i + 8, i, 1379 true, 100); 1380 if (err) 1381 return err; 1382 } 1383 1384 /* Make sure the max shaper is disabled in all hierarchies that support 1385 * it. Note that this disables ptps (PTP shaper), but that is intended 1386 * for the initial configuration. 1387 */ 1388 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1389 MLXSW_REG_QEEC_HR_PORT, 0, 0, 1390 MLXSW_REG_QEEC_MAS_DIS, 0); 1391 if (err) 1392 return err; 1393 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1394 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1395 MLXSW_REG_QEEC_HR_SUBGROUP, 1396 i, 0, 1397 MLXSW_REG_QEEC_MAS_DIS, 0); 1398 if (err) 1399 return err; 1400 } 1401 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1402 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1403 MLXSW_REG_QEEC_HR_TC, 1404 i, i, 1405 MLXSW_REG_QEEC_MAS_DIS, 0); 1406 if (err) 1407 return err; 1408 1409 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1410 MLXSW_REG_QEEC_HR_TC, 1411 i + 8, i, 1412 MLXSW_REG_QEEC_MAS_DIS, 0); 1413 if (err) 1414 return err; 1415 } 1416 1417 /* Configure the min shaper for multicast TCs. */ 1418 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1419 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 1420 MLXSW_REG_QEEC_HR_TC, 1421 i + 8, i, 1422 MLXSW_REG_QEEC_MIS_MIN); 1423 if (err) 1424 return err; 1425 } 1426 1427 /* Map all priorities to traffic class 0. */ 1428 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1429 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 1430 if (err) 1431 return err; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 1438 bool enable) 1439 { 1440 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1441 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 1442 1443 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 1444 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 1445 } 1446 1447 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port) 1448 { 1449 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1450 u8 module = mlxsw_sp_port->mapping.module; 1451 u64 overheat_counter; 1452 int err; 1453 1454 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, module, 1455 &overheat_counter); 1456 if (err) 1457 return err; 1458 1459 mlxsw_sp_port->module_overheat_initial_val = overheat_counter; 1460 return 0; 1461 } 1462 1463 int 1464 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port, 1465 bool is_8021ad_tagged, 1466 bool is_8021q_tagged) 1467 { 1468 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1469 char spvc_pl[MLXSW_REG_SPVC_LEN]; 1470 1471 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port, 1472 is_8021ad_tagged, is_8021q_tagged); 1473 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl); 1474 } 1475 1476 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp, 1477 u8 local_port, u8 *port_number, 1478 u8 *split_port_subnumber, 1479 u8 *slot_index) 1480 { 1481 char pllp_pl[MLXSW_REG_PLLP_LEN]; 1482 int err; 1483 1484 mlxsw_reg_pllp_pack(pllp_pl, local_port); 1485 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); 1486 if (err) 1487 return err; 1488 mlxsw_reg_pllp_unpack(pllp_pl, port_number, 1489 split_port_subnumber, slot_index); 1490 return 0; 1491 } 1492 1493 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 1494 bool split, 1495 struct mlxsw_sp_port_mapping *port_mapping) 1496 { 1497 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1498 struct mlxsw_sp_port *mlxsw_sp_port; 1499 u32 lanes = port_mapping->width; 1500 u8 split_port_subnumber; 1501 struct net_device *dev; 1502 u8 port_number; 1503 u8 slot_index; 1504 bool splittable; 1505 int err; 1506 1507 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping); 1508 if (err) { 1509 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 1510 local_port); 1511 return err; 1512 } 1513 1514 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0); 1515 if (err) { 1516 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 1517 local_port); 1518 goto err_port_swid_set; 1519 } 1520 1521 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number, 1522 &split_port_subnumber, &slot_index); 1523 if (err) { 1524 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n", 1525 local_port); 1526 goto err_port_label_info_get; 1527 } 1528 1529 splittable = lanes > 1 && !split; 1530 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, 1531 port_number, split, split_port_subnumber, 1532 splittable, lanes, mlxsw_sp->base_mac, 1533 sizeof(mlxsw_sp->base_mac)); 1534 if (err) { 1535 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 1536 local_port); 1537 goto err_core_port_init; 1538 } 1539 1540 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 1541 if (!dev) { 1542 err = -ENOMEM; 1543 goto err_alloc_etherdev; 1544 } 1545 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 1546 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp)); 1547 mlxsw_sp_port = netdev_priv(dev); 1548 mlxsw_sp_port->dev = dev; 1549 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1550 mlxsw_sp_port->local_port = local_port; 1551 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; 1552 mlxsw_sp_port->split = split; 1553 mlxsw_sp_port->mapping = *port_mapping; 1554 mlxsw_sp_port->link.autoneg = 1; 1555 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 1556 1557 mlxsw_sp_port->pcpu_stats = 1558 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 1559 if (!mlxsw_sp_port->pcpu_stats) { 1560 err = -ENOMEM; 1561 goto err_alloc_stats; 1562 } 1563 1564 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1565 &update_stats_cache); 1566 1567 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 1568 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 1569 1570 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 1571 if (err) { 1572 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 1573 mlxsw_sp_port->local_port); 1574 goto err_dev_addr_init; 1575 } 1576 1577 netif_carrier_off(dev); 1578 1579 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 1580 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 1581 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK; 1582 1583 dev->min_mtu = 0; 1584 dev->max_mtu = ETH_MAX_MTU; 1585 1586 /* Each packet needs to have a Tx header (metadata) on top all other 1587 * headers. 1588 */ 1589 dev->needed_headroom = MLXSW_TXHDR_LEN; 1590 1591 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 1592 if (err) { 1593 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 1594 mlxsw_sp_port->local_port); 1595 goto err_port_system_port_mapping_set; 1596 } 1597 1598 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port); 1599 if (err) { 1600 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 1601 mlxsw_sp_port->local_port); 1602 goto err_port_speed_by_width_set; 1603 } 1604 1605 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port, 1606 &mlxsw_sp_port->max_speed); 1607 if (err) { 1608 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n", 1609 mlxsw_sp_port->local_port); 1610 goto err_max_speed_get; 1611 } 1612 1613 err = mlxsw_sp_port_max_mtu_get(mlxsw_sp_port, &mlxsw_sp_port->max_mtu); 1614 if (err) { 1615 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n", 1616 mlxsw_sp_port->local_port); 1617 goto err_port_max_mtu_get; 1618 } 1619 1620 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 1621 if (err) { 1622 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 1623 mlxsw_sp_port->local_port); 1624 goto err_port_mtu_set; 1625 } 1626 1627 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1628 if (err) 1629 goto err_port_admin_status_set; 1630 1631 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 1632 if (err) { 1633 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 1634 mlxsw_sp_port->local_port); 1635 goto err_port_buffers_init; 1636 } 1637 1638 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 1639 if (err) { 1640 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 1641 mlxsw_sp_port->local_port); 1642 goto err_port_ets_init; 1643 } 1644 1645 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 1646 if (err) { 1647 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 1648 mlxsw_sp_port->local_port); 1649 goto err_port_tc_mc_mode; 1650 } 1651 1652 /* ETS and buffers must be initialized before DCB. */ 1653 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 1654 if (err) { 1655 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 1656 mlxsw_sp_port->local_port); 1657 goto err_port_dcb_init; 1658 } 1659 1660 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 1661 if (err) { 1662 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 1663 mlxsw_sp_port->local_port); 1664 goto err_port_fids_init; 1665 } 1666 1667 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 1668 if (err) { 1669 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 1670 mlxsw_sp_port->local_port); 1671 goto err_port_qdiscs_init; 1672 } 1673 1674 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false, 1675 false); 1676 if (err) { 1677 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n", 1678 mlxsw_sp_port->local_port); 1679 goto err_port_vlan_clear; 1680 } 1681 1682 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 1683 if (err) { 1684 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 1685 mlxsw_sp_port->local_port); 1686 goto err_port_nve_init; 1687 } 1688 1689 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 1690 ETH_P_8021Q); 1691 if (err) { 1692 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n", 1693 mlxsw_sp_port->local_port); 1694 goto err_port_pvid_set; 1695 } 1696 1697 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, 1698 MLXSW_SP_DEFAULT_VID); 1699 if (IS_ERR(mlxsw_sp_port_vlan)) { 1700 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 1701 mlxsw_sp_port->local_port); 1702 err = PTR_ERR(mlxsw_sp_port_vlan); 1703 goto err_port_vlan_create; 1704 } 1705 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan; 1706 1707 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat 1708 * only packets with 802.1q header as tagged packets. 1709 */ 1710 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true); 1711 if (err) { 1712 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n", 1713 local_port); 1714 goto err_port_vlan_classification_set; 1715 } 1716 1717 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw, 1718 mlxsw_sp->ptp_ops->shaper_work); 1719 1720 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 1721 1722 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port); 1723 if (err) { 1724 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n", 1725 mlxsw_sp_port->local_port); 1726 goto err_port_overheat_init_val_set; 1727 } 1728 1729 err = register_netdev(dev); 1730 if (err) { 1731 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 1732 mlxsw_sp_port->local_port); 1733 goto err_register_netdev; 1734 } 1735 1736 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 1737 mlxsw_sp_port, dev); 1738 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 1739 return 0; 1740 1741 err_register_netdev: 1742 err_port_overheat_init_val_set: 1743 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1744 err_port_vlan_classification_set: 1745 mlxsw_sp->ports[local_port] = NULL; 1746 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1747 err_port_vlan_create: 1748 err_port_pvid_set: 1749 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1750 err_port_nve_init: 1751 err_port_vlan_clear: 1752 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1753 err_port_qdiscs_init: 1754 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1755 err_port_fids_init: 1756 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1757 err_port_dcb_init: 1758 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1759 err_port_tc_mc_mode: 1760 err_port_ets_init: 1761 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1762 err_port_buffers_init: 1763 err_port_admin_status_set: 1764 err_port_mtu_set: 1765 err_port_max_mtu_get: 1766 err_max_speed_get: 1767 err_port_speed_by_width_set: 1768 err_port_system_port_mapping_set: 1769 err_dev_addr_init: 1770 free_percpu(mlxsw_sp_port->pcpu_stats); 1771 err_alloc_stats: 1772 free_netdev(dev); 1773 err_alloc_etherdev: 1774 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1775 err_core_port_init: 1776 err_port_label_info_get: 1777 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1778 MLXSW_PORT_SWID_DISABLED_PORT); 1779 err_port_swid_set: 1780 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, port_mapping->module); 1781 return err; 1782 } 1783 1784 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 1785 { 1786 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 1787 u8 module = mlxsw_sp_port->mapping.module; 1788 1789 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 1790 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw); 1791 mlxsw_sp_port_ptp_clear(mlxsw_sp_port); 1792 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 1793 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 1794 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1795 mlxsw_sp->ports[local_port] = NULL; 1796 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); 1797 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1798 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1799 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1800 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1801 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1802 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1803 free_percpu(mlxsw_sp_port->pcpu_stats); 1804 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 1805 free_netdev(mlxsw_sp_port->dev); 1806 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1807 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1808 MLXSW_PORT_SWID_DISABLED_PORT); 1809 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, module); 1810 } 1811 1812 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp) 1813 { 1814 struct mlxsw_sp_port *mlxsw_sp_port; 1815 int err; 1816 1817 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL); 1818 if (!mlxsw_sp_port) 1819 return -ENOMEM; 1820 1821 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1822 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT; 1823 1824 err = mlxsw_core_cpu_port_init(mlxsw_sp->core, 1825 mlxsw_sp_port, 1826 mlxsw_sp->base_mac, 1827 sizeof(mlxsw_sp->base_mac)); 1828 if (err) { 1829 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n"); 1830 goto err_core_cpu_port_init; 1831 } 1832 1833 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port; 1834 return 0; 1835 1836 err_core_cpu_port_init: 1837 kfree(mlxsw_sp_port); 1838 return err; 1839 } 1840 1841 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp) 1842 { 1843 struct mlxsw_sp_port *mlxsw_sp_port = 1844 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT]; 1845 1846 mlxsw_core_cpu_port_fini(mlxsw_sp->core); 1847 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL; 1848 kfree(mlxsw_sp_port); 1849 } 1850 1851 static bool mlxsw_sp_local_port_valid(u8 local_port) 1852 { 1853 return local_port != MLXSW_PORT_CPU_PORT; 1854 } 1855 1856 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 1857 { 1858 if (!mlxsw_sp_local_port_valid(local_port)) 1859 return false; 1860 return mlxsw_sp->ports[local_port] != NULL; 1861 } 1862 1863 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 1864 { 1865 int i; 1866 1867 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 1868 if (mlxsw_sp_port_created(mlxsw_sp, i)) 1869 mlxsw_sp_port_remove(mlxsw_sp, i); 1870 mlxsw_sp_cpu_port_remove(mlxsw_sp); 1871 kfree(mlxsw_sp->ports); 1872 mlxsw_sp->ports = NULL; 1873 } 1874 1875 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 1876 { 1877 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1878 struct mlxsw_sp_port_mapping *port_mapping; 1879 size_t alloc_size; 1880 int i; 1881 int err; 1882 1883 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 1884 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 1885 if (!mlxsw_sp->ports) 1886 return -ENOMEM; 1887 1888 err = mlxsw_sp_cpu_port_create(mlxsw_sp); 1889 if (err) 1890 goto err_cpu_port_create; 1891 1892 for (i = 1; i < max_ports; i++) { 1893 port_mapping = mlxsw_sp->port_mapping[i]; 1894 if (!port_mapping) 1895 continue; 1896 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping); 1897 if (err) 1898 goto err_port_create; 1899 } 1900 return 0; 1901 1902 err_port_create: 1903 for (i--; i >= 1; i--) 1904 if (mlxsw_sp_port_created(mlxsw_sp, i)) 1905 mlxsw_sp_port_remove(mlxsw_sp, i); 1906 mlxsw_sp_cpu_port_remove(mlxsw_sp); 1907 err_cpu_port_create: 1908 kfree(mlxsw_sp->ports); 1909 mlxsw_sp->ports = NULL; 1910 return err; 1911 } 1912 1913 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp) 1914 { 1915 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1916 struct mlxsw_sp_port_mapping port_mapping; 1917 int i; 1918 int err; 1919 1920 mlxsw_sp->port_mapping = kcalloc(max_ports, 1921 sizeof(struct mlxsw_sp_port_mapping *), 1922 GFP_KERNEL); 1923 if (!mlxsw_sp->port_mapping) 1924 return -ENOMEM; 1925 1926 for (i = 1; i < max_ports; i++) { 1927 if (mlxsw_core_port_is_xm(mlxsw_sp->core, i)) 1928 continue; 1929 1930 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &port_mapping); 1931 if (err) 1932 goto err_port_module_info_get; 1933 if (!port_mapping.width) 1934 continue; 1935 1936 mlxsw_sp->port_mapping[i] = kmemdup(&port_mapping, 1937 sizeof(port_mapping), 1938 GFP_KERNEL); 1939 if (!mlxsw_sp->port_mapping[i]) { 1940 err = -ENOMEM; 1941 goto err_port_module_info_dup; 1942 } 1943 } 1944 return 0; 1945 1946 err_port_module_info_get: 1947 err_port_module_info_dup: 1948 for (i--; i >= 1; i--) 1949 kfree(mlxsw_sp->port_mapping[i]); 1950 kfree(mlxsw_sp->port_mapping); 1951 return err; 1952 } 1953 1954 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp) 1955 { 1956 int i; 1957 1958 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 1959 kfree(mlxsw_sp->port_mapping[i]); 1960 kfree(mlxsw_sp->port_mapping); 1961 } 1962 1963 static int 1964 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, 1965 struct mlxsw_sp_port_mapping *port_mapping, 1966 unsigned int count, const char *pmtdb_pl) 1967 { 1968 struct mlxsw_sp_port_mapping split_port_mapping; 1969 int err, i; 1970 1971 split_port_mapping = *port_mapping; 1972 split_port_mapping.width /= count; 1973 for (i = 0; i < count; i++) { 1974 u8 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 1975 1976 if (!mlxsw_sp_local_port_valid(s_local_port)) 1977 continue; 1978 1979 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port, 1980 true, &split_port_mapping); 1981 if (err) 1982 goto err_port_create; 1983 split_port_mapping.lane += split_port_mapping.width; 1984 } 1985 1986 return 0; 1987 1988 err_port_create: 1989 for (i--; i >= 0; i--) { 1990 u8 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 1991 1992 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 1993 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 1994 } 1995 return err; 1996 } 1997 1998 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 1999 unsigned int count, 2000 const char *pmtdb_pl) 2001 { 2002 struct mlxsw_sp_port_mapping *port_mapping; 2003 int i; 2004 2005 /* Go over original unsplit ports in the gap and recreate them. */ 2006 for (i = 0; i < count; i++) { 2007 u8 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2008 2009 port_mapping = mlxsw_sp->port_mapping[local_port]; 2010 if (!port_mapping || !mlxsw_sp_local_port_valid(local_port)) 2011 continue; 2012 mlxsw_sp_port_create(mlxsw_sp, local_port, 2013 false, port_mapping); 2014 } 2015 } 2016 2017 static struct mlxsw_sp_port * 2018 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u8 local_port) 2019 { 2020 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port]) 2021 return mlxsw_sp->ports[local_port]; 2022 return NULL; 2023 } 2024 2025 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 2026 unsigned int count, 2027 struct netlink_ext_ack *extack) 2028 { 2029 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2030 struct mlxsw_sp_port_mapping port_mapping; 2031 struct mlxsw_sp_port *mlxsw_sp_port; 2032 enum mlxsw_reg_pmtdb_status status; 2033 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2034 int i; 2035 int err; 2036 2037 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2038 if (!mlxsw_sp_port) { 2039 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2040 local_port); 2041 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2042 return -EINVAL; 2043 } 2044 2045 if (mlxsw_sp_port->split) { 2046 NL_SET_ERR_MSG_MOD(extack, "Port is already split"); 2047 return -EINVAL; 2048 } 2049 2050 mlxsw_reg_pmtdb_pack(pmtdb_pl, 0, mlxsw_sp_port->mapping.module, 2051 mlxsw_sp_port->mapping.module_width / count, 2052 count); 2053 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2054 if (err) { 2055 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2056 return err; 2057 } 2058 2059 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl); 2060 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) { 2061 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration"); 2062 return -EINVAL; 2063 } 2064 2065 port_mapping = mlxsw_sp_port->mapping; 2066 2067 for (i = 0; i < count; i++) { 2068 u8 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2069 2070 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2071 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2072 } 2073 2074 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping, 2075 count, pmtdb_pl); 2076 if (err) { 2077 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 2078 goto err_port_split_create; 2079 } 2080 2081 return 0; 2082 2083 err_port_split_create: 2084 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2085 return err; 2086 } 2087 2088 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port, 2089 struct netlink_ext_ack *extack) 2090 { 2091 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2092 struct mlxsw_sp_port *mlxsw_sp_port; 2093 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2094 unsigned int count; 2095 int i; 2096 int err; 2097 2098 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2099 if (!mlxsw_sp_port) { 2100 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2101 local_port); 2102 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2103 return -EINVAL; 2104 } 2105 2106 if (!mlxsw_sp_port->split) { 2107 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 2108 return -EINVAL; 2109 } 2110 2111 count = mlxsw_sp_port->mapping.module_width / 2112 mlxsw_sp_port->mapping.width; 2113 2114 mlxsw_reg_pmtdb_pack(pmtdb_pl, 0, mlxsw_sp_port->mapping.module, 2115 mlxsw_sp_port->mapping.module_width / count, 2116 count); 2117 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2118 if (err) { 2119 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2120 return err; 2121 } 2122 2123 for (i = 0; i < count; i++) { 2124 u8 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2125 2126 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2127 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2128 } 2129 2130 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2131 2132 return 0; 2133 } 2134 2135 static void 2136 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port) 2137 { 2138 int i; 2139 2140 for (i = 0; i < TC_MAX_QUEUE; i++) 2141 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0; 2142 } 2143 2144 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 2145 char *pude_pl, void *priv) 2146 { 2147 struct mlxsw_sp *mlxsw_sp = priv; 2148 struct mlxsw_sp_port *mlxsw_sp_port; 2149 enum mlxsw_reg_pude_oper_status status; 2150 unsigned int max_ports; 2151 u8 local_port; 2152 2153 max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2154 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 2155 2156 if (WARN_ON_ONCE(!local_port || local_port >= max_ports)) 2157 return; 2158 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2159 if (!mlxsw_sp_port) 2160 return; 2161 2162 status = mlxsw_reg_pude_oper_status_get(pude_pl); 2163 if (status == MLXSW_PORT_OPER_STATUS_UP) { 2164 netdev_info(mlxsw_sp_port->dev, "link up\n"); 2165 netif_carrier_on(mlxsw_sp_port->dev); 2166 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0); 2167 } else { 2168 netdev_info(mlxsw_sp_port->dev, "link down\n"); 2169 netif_carrier_off(mlxsw_sp_port->dev); 2170 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port); 2171 } 2172 } 2173 2174 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp, 2175 char *mtpptr_pl, bool ingress) 2176 { 2177 u8 local_port; 2178 u8 num_rec; 2179 int i; 2180 2181 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl); 2182 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl); 2183 for (i = 0; i < num_rec; i++) { 2184 u8 domain_number; 2185 u8 message_type; 2186 u16 sequence_id; 2187 u64 timestamp; 2188 2189 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type, 2190 &domain_number, &sequence_id, 2191 ×tamp); 2192 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port, 2193 message_type, domain_number, 2194 sequence_id, timestamp); 2195 } 2196 } 2197 2198 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg, 2199 char *mtpptr_pl, void *priv) 2200 { 2201 struct mlxsw_sp *mlxsw_sp = priv; 2202 2203 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true); 2204 } 2205 2206 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg, 2207 char *mtpptr_pl, void *priv) 2208 { 2209 struct mlxsw_sp *mlxsw_sp = priv; 2210 2211 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false); 2212 } 2213 2214 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 2215 u8 local_port, void *priv) 2216 { 2217 struct mlxsw_sp *mlxsw_sp = priv; 2218 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2219 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 2220 2221 if (unlikely(!mlxsw_sp_port)) { 2222 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 2223 local_port); 2224 return; 2225 } 2226 2227 skb->dev = mlxsw_sp_port->dev; 2228 2229 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 2230 u64_stats_update_begin(&pcpu_stats->syncp); 2231 pcpu_stats->rx_packets++; 2232 pcpu_stats->rx_bytes += skb->len; 2233 u64_stats_update_end(&pcpu_stats->syncp); 2234 2235 skb->protocol = eth_type_trans(skb, skb->dev); 2236 netif_receive_skb(skb); 2237 } 2238 2239 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 2240 void *priv) 2241 { 2242 skb->offload_fwd_mark = 1; 2243 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2244 } 2245 2246 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb, 2247 u8 local_port, void *priv) 2248 { 2249 skb->offload_l3_fwd_mark = 1; 2250 skb->offload_fwd_mark = 1; 2251 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2252 } 2253 2254 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 2255 u8 local_port) 2256 { 2257 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port); 2258 } 2259 2260 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2261 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 2262 _is_ctrl, SP_##_trap_group, DISCARD) 2263 2264 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2265 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 2266 _is_ctrl, SP_##_trap_group, DISCARD) 2267 2268 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2269 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \ 2270 _is_ctrl, SP_##_trap_group, DISCARD) 2271 2272 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 2273 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 2274 2275 static const struct mlxsw_listener mlxsw_sp_listener[] = { 2276 /* Events */ 2277 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 2278 /* L2 traps */ 2279 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false), 2280 /* L3 traps */ 2281 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 2282 false), 2283 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 2284 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 2285 false), 2286 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD, 2287 ROUTER_EXP, false), 2288 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD, 2289 ROUTER_EXP, false), 2290 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD, 2291 ROUTER_EXP, false), 2292 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD, 2293 ROUTER_EXP, false), 2294 /* Multicast Router Traps */ 2295 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 2296 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 2297 /* NVE traps */ 2298 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false), 2299 }; 2300 2301 static const struct mlxsw_listener mlxsw_sp1_listener[] = { 2302 /* Events */ 2303 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0), 2304 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0), 2305 }; 2306 2307 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 2308 { 2309 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2310 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 2311 enum mlxsw_reg_qpcr_ir_units ir_units; 2312 int max_cpu_policers; 2313 bool is_bytes; 2314 u8 burst_size; 2315 u32 rate; 2316 int i, err; 2317 2318 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 2319 return -EIO; 2320 2321 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2322 2323 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 2324 for (i = 0; i < max_cpu_policers; i++) { 2325 is_bytes = false; 2326 switch (i) { 2327 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2328 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2329 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2330 rate = 1024; 2331 burst_size = 7; 2332 break; 2333 default: 2334 continue; 2335 } 2336 2337 __set_bit(i, mlxsw_sp->trap->policers_usage); 2338 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 2339 burst_size); 2340 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 2341 if (err) 2342 return err; 2343 } 2344 2345 return 0; 2346 } 2347 2348 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 2349 { 2350 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2351 enum mlxsw_reg_htgt_trap_group i; 2352 int max_cpu_policers; 2353 int max_trap_groups; 2354 u8 priority, tc; 2355 u16 policer_id; 2356 int err; 2357 2358 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 2359 return -EIO; 2360 2361 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 2362 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2363 2364 for (i = 0; i < max_trap_groups; i++) { 2365 policer_id = i; 2366 switch (i) { 2367 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2368 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2369 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2370 priority = 1; 2371 tc = 1; 2372 break; 2373 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 2374 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 2375 tc = MLXSW_REG_HTGT_DEFAULT_TC; 2376 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 2377 break; 2378 default: 2379 continue; 2380 } 2381 2382 if (max_cpu_policers <= policer_id && 2383 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 2384 return -EIO; 2385 2386 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 2387 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2388 if (err) 2389 return err; 2390 } 2391 2392 return 0; 2393 } 2394 2395 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp, 2396 const struct mlxsw_listener listeners[], 2397 size_t listeners_count) 2398 { 2399 int i; 2400 int err; 2401 2402 for (i = 0; i < listeners_count; i++) { 2403 err = mlxsw_core_trap_register(mlxsw_sp->core, 2404 &listeners[i], 2405 mlxsw_sp); 2406 if (err) 2407 goto err_listener_register; 2408 2409 } 2410 return 0; 2411 2412 err_listener_register: 2413 for (i--; i >= 0; i--) { 2414 mlxsw_core_trap_unregister(mlxsw_sp->core, 2415 &listeners[i], 2416 mlxsw_sp); 2417 } 2418 return err; 2419 } 2420 2421 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp, 2422 const struct mlxsw_listener listeners[], 2423 size_t listeners_count) 2424 { 2425 int i; 2426 2427 for (i = 0; i < listeners_count; i++) { 2428 mlxsw_core_trap_unregister(mlxsw_sp->core, 2429 &listeners[i], 2430 mlxsw_sp); 2431 } 2432 } 2433 2434 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 2435 { 2436 struct mlxsw_sp_trap *trap; 2437 u64 max_policers; 2438 int err; 2439 2440 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS)) 2441 return -EIO; 2442 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS); 2443 trap = kzalloc(struct_size(trap, policers_usage, 2444 BITS_TO_LONGS(max_policers)), GFP_KERNEL); 2445 if (!trap) 2446 return -ENOMEM; 2447 trap->max_policers = max_policers; 2448 mlxsw_sp->trap = trap; 2449 2450 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 2451 if (err) 2452 goto err_cpu_policers_set; 2453 2454 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 2455 if (err) 2456 goto err_trap_groups_set; 2457 2458 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener, 2459 ARRAY_SIZE(mlxsw_sp_listener)); 2460 if (err) 2461 goto err_traps_register; 2462 2463 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners, 2464 mlxsw_sp->listeners_count); 2465 if (err) 2466 goto err_extra_traps_init; 2467 2468 return 0; 2469 2470 err_extra_traps_init: 2471 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener, 2472 ARRAY_SIZE(mlxsw_sp_listener)); 2473 err_traps_register: 2474 err_trap_groups_set: 2475 err_cpu_policers_set: 2476 kfree(trap); 2477 return err; 2478 } 2479 2480 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 2481 { 2482 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners, 2483 mlxsw_sp->listeners_count); 2484 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener, 2485 ARRAY_SIZE(mlxsw_sp_listener)); 2486 kfree(mlxsw_sp->trap); 2487 } 2488 2489 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe 2490 2491 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 2492 { 2493 char slcr_pl[MLXSW_REG_SLCR_LEN]; 2494 u32 seed; 2495 int err; 2496 2497 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac), 2498 MLXSW_SP_LAG_SEED_INIT); 2499 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 2500 MLXSW_REG_SLCR_LAG_HASH_DMAC | 2501 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 2502 MLXSW_REG_SLCR_LAG_HASH_VLANID | 2503 MLXSW_REG_SLCR_LAG_HASH_SIP | 2504 MLXSW_REG_SLCR_LAG_HASH_DIP | 2505 MLXSW_REG_SLCR_LAG_HASH_SPORT | 2506 MLXSW_REG_SLCR_LAG_HASH_DPORT | 2507 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 2508 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 2509 if (err) 2510 return err; 2511 2512 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 2513 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 2514 return -EIO; 2515 2516 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 2517 sizeof(struct mlxsw_sp_upper), 2518 GFP_KERNEL); 2519 if (!mlxsw_sp->lags) 2520 return -ENOMEM; 2521 2522 return 0; 2523 } 2524 2525 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 2526 { 2527 kfree(mlxsw_sp->lags); 2528 } 2529 2530 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 2531 { 2532 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2533 int err; 2534 2535 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 2536 MLXSW_REG_HTGT_INVALID_POLICER, 2537 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2538 MLXSW_REG_HTGT_DEFAULT_TC); 2539 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2540 if (err) 2541 return err; 2542 2543 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_MFDE, 2544 MLXSW_REG_HTGT_INVALID_POLICER, 2545 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2546 MLXSW_REG_HTGT_DEFAULT_TC); 2547 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2548 if (err) 2549 return err; 2550 2551 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_MTWE, 2552 MLXSW_REG_HTGT_INVALID_POLICER, 2553 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2554 MLXSW_REG_HTGT_DEFAULT_TC); 2555 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2556 if (err) 2557 return err; 2558 2559 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_PMPE, 2560 MLXSW_REG_HTGT_INVALID_POLICER, 2561 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2562 MLXSW_REG_HTGT_DEFAULT_TC); 2563 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2564 } 2565 2566 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = { 2567 .clock_init = mlxsw_sp1_ptp_clock_init, 2568 .clock_fini = mlxsw_sp1_ptp_clock_fini, 2569 .init = mlxsw_sp1_ptp_init, 2570 .fini = mlxsw_sp1_ptp_fini, 2571 .receive = mlxsw_sp1_ptp_receive, 2572 .transmitted = mlxsw_sp1_ptp_transmitted, 2573 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get, 2574 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set, 2575 .shaper_work = mlxsw_sp1_ptp_shaper_work, 2576 .get_ts_info = mlxsw_sp1_ptp_get_ts_info, 2577 .get_stats_count = mlxsw_sp1_get_stats_count, 2578 .get_stats_strings = mlxsw_sp1_get_stats_strings, 2579 .get_stats = mlxsw_sp1_get_stats, 2580 }; 2581 2582 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = { 2583 .clock_init = mlxsw_sp2_ptp_clock_init, 2584 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2585 .init = mlxsw_sp2_ptp_init, 2586 .fini = mlxsw_sp2_ptp_fini, 2587 .receive = mlxsw_sp2_ptp_receive, 2588 .transmitted = mlxsw_sp2_ptp_transmitted, 2589 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2590 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2591 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2592 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2593 .get_stats_count = mlxsw_sp2_get_stats_count, 2594 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2595 .get_stats = mlxsw_sp2_get_stats, 2596 }; 2597 2598 struct mlxsw_sp_sample_trigger_node { 2599 struct mlxsw_sp_sample_trigger trigger; 2600 struct mlxsw_sp_sample_params params; 2601 struct rhash_head ht_node; 2602 struct rcu_head rcu; 2603 refcount_t refcount; 2604 }; 2605 2606 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = { 2607 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger), 2608 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node), 2609 .key_len = sizeof(struct mlxsw_sp_sample_trigger), 2610 .automatic_shrinking = true, 2611 }; 2612 2613 static void 2614 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key, 2615 const struct mlxsw_sp_sample_trigger *trigger) 2616 { 2617 memset(key, 0, sizeof(*key)); 2618 key->type = trigger->type; 2619 key->local_port = trigger->local_port; 2620 } 2621 2622 /* RCU read lock must be held */ 2623 struct mlxsw_sp_sample_params * 2624 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp, 2625 const struct mlxsw_sp_sample_trigger *trigger) 2626 { 2627 struct mlxsw_sp_sample_trigger_node *trigger_node; 2628 struct mlxsw_sp_sample_trigger key; 2629 2630 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2631 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key, 2632 mlxsw_sp_sample_trigger_ht_params); 2633 if (!trigger_node) 2634 return NULL; 2635 2636 return &trigger_node->params; 2637 } 2638 2639 static int 2640 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp, 2641 const struct mlxsw_sp_sample_trigger *trigger, 2642 const struct mlxsw_sp_sample_params *params) 2643 { 2644 struct mlxsw_sp_sample_trigger_node *trigger_node; 2645 int err; 2646 2647 trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL); 2648 if (!trigger_node) 2649 return -ENOMEM; 2650 2651 trigger_node->trigger = *trigger; 2652 trigger_node->params = *params; 2653 refcount_set(&trigger_node->refcount, 1); 2654 2655 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht, 2656 &trigger_node->ht_node, 2657 mlxsw_sp_sample_trigger_ht_params); 2658 if (err) 2659 goto err_rhashtable_insert; 2660 2661 return 0; 2662 2663 err_rhashtable_insert: 2664 kfree(trigger_node); 2665 return err; 2666 } 2667 2668 static void 2669 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp, 2670 struct mlxsw_sp_sample_trigger_node *trigger_node) 2671 { 2672 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht, 2673 &trigger_node->ht_node, 2674 mlxsw_sp_sample_trigger_ht_params); 2675 kfree_rcu(trigger_node, rcu); 2676 } 2677 2678 int 2679 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp, 2680 const struct mlxsw_sp_sample_trigger *trigger, 2681 const struct mlxsw_sp_sample_params *params, 2682 struct netlink_ext_ack *extack) 2683 { 2684 struct mlxsw_sp_sample_trigger_node *trigger_node; 2685 struct mlxsw_sp_sample_trigger key; 2686 2687 ASSERT_RTNL(); 2688 2689 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2690 2691 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2692 &key, 2693 mlxsw_sp_sample_trigger_ht_params); 2694 if (!trigger_node) 2695 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key, 2696 params); 2697 2698 if (trigger_node->trigger.local_port) { 2699 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port"); 2700 return -EINVAL; 2701 } 2702 2703 if (trigger_node->params.psample_group != params->psample_group || 2704 trigger_node->params.truncate != params->truncate || 2705 trigger_node->params.rate != params->rate || 2706 trigger_node->params.trunc_size != params->trunc_size) { 2707 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger"); 2708 return -EINVAL; 2709 } 2710 2711 refcount_inc(&trigger_node->refcount); 2712 2713 return 0; 2714 } 2715 2716 void 2717 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp, 2718 const struct mlxsw_sp_sample_trigger *trigger) 2719 { 2720 struct mlxsw_sp_sample_trigger_node *trigger_node; 2721 struct mlxsw_sp_sample_trigger key; 2722 2723 ASSERT_RTNL(); 2724 2725 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2726 2727 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2728 &key, 2729 mlxsw_sp_sample_trigger_ht_params); 2730 if (!trigger_node) 2731 return; 2732 2733 if (!refcount_dec_and_test(&trigger_node->refcount)) 2734 return; 2735 2736 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node); 2737 } 2738 2739 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 2740 unsigned long event, void *ptr); 2741 2742 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96 2743 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128 2744 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789 2745 2746 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp) 2747 { 2748 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 2749 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT; 2750 mutex_init(&mlxsw_sp->parsing.lock); 2751 } 2752 2753 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp) 2754 { 2755 mutex_destroy(&mlxsw_sp->parsing.lock); 2756 } 2757 2758 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 2759 const struct mlxsw_bus_info *mlxsw_bus_info, 2760 struct netlink_ext_ack *extack) 2761 { 2762 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2763 int err; 2764 2765 mlxsw_sp->core = mlxsw_core; 2766 mlxsw_sp->bus_info = mlxsw_bus_info; 2767 2768 mlxsw_sp_parsing_init(mlxsw_sp); 2769 mlxsw_core_emad_string_tlv_enable(mlxsw_core); 2770 2771 err = mlxsw_sp_base_mac_get(mlxsw_sp); 2772 if (err) { 2773 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 2774 return err; 2775 } 2776 2777 err = mlxsw_sp_kvdl_init(mlxsw_sp); 2778 if (err) { 2779 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 2780 return err; 2781 } 2782 2783 err = mlxsw_sp_fids_init(mlxsw_sp); 2784 if (err) { 2785 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 2786 goto err_fids_init; 2787 } 2788 2789 err = mlxsw_sp_policers_init(mlxsw_sp); 2790 if (err) { 2791 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n"); 2792 goto err_policers_init; 2793 } 2794 2795 err = mlxsw_sp_traps_init(mlxsw_sp); 2796 if (err) { 2797 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 2798 goto err_traps_init; 2799 } 2800 2801 err = mlxsw_sp_devlink_traps_init(mlxsw_sp); 2802 if (err) { 2803 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n"); 2804 goto err_devlink_traps_init; 2805 } 2806 2807 err = mlxsw_sp_buffers_init(mlxsw_sp); 2808 if (err) { 2809 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 2810 goto err_buffers_init; 2811 } 2812 2813 err = mlxsw_sp_lag_init(mlxsw_sp); 2814 if (err) { 2815 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 2816 goto err_lag_init; 2817 } 2818 2819 /* Initialize SPAN before router and switchdev, so that those components 2820 * can call mlxsw_sp_span_respin(). 2821 */ 2822 err = mlxsw_sp_span_init(mlxsw_sp); 2823 if (err) { 2824 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 2825 goto err_span_init; 2826 } 2827 2828 err = mlxsw_sp_switchdev_init(mlxsw_sp); 2829 if (err) { 2830 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 2831 goto err_switchdev_init; 2832 } 2833 2834 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 2835 if (err) { 2836 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 2837 goto err_counter_pool_init; 2838 } 2839 2840 err = mlxsw_sp_afa_init(mlxsw_sp); 2841 if (err) { 2842 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 2843 goto err_afa_init; 2844 } 2845 2846 err = mlxsw_sp_nve_init(mlxsw_sp); 2847 if (err) { 2848 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 2849 goto err_nve_init; 2850 } 2851 2852 err = mlxsw_sp_acl_init(mlxsw_sp); 2853 if (err) { 2854 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 2855 goto err_acl_init; 2856 } 2857 2858 err = mlxsw_sp_router_init(mlxsw_sp, extack); 2859 if (err) { 2860 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 2861 goto err_router_init; 2862 } 2863 2864 if (mlxsw_sp->bus_info->read_frc_capable) { 2865 /* NULL is a valid return value from clock_init */ 2866 mlxsw_sp->clock = 2867 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp, 2868 mlxsw_sp->bus_info->dev); 2869 if (IS_ERR(mlxsw_sp->clock)) { 2870 err = PTR_ERR(mlxsw_sp->clock); 2871 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n"); 2872 goto err_ptp_clock_init; 2873 } 2874 } 2875 2876 if (mlxsw_sp->clock) { 2877 /* NULL is a valid return value from ptp_ops->init */ 2878 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp); 2879 if (IS_ERR(mlxsw_sp->ptp_state)) { 2880 err = PTR_ERR(mlxsw_sp->ptp_state); 2881 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n"); 2882 goto err_ptp_init; 2883 } 2884 } 2885 2886 /* Initialize netdevice notifier after router and SPAN is initialized, 2887 * so that the event handler can use router structures and call SPAN 2888 * respin. 2889 */ 2890 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 2891 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 2892 &mlxsw_sp->netdevice_nb); 2893 if (err) { 2894 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 2895 goto err_netdev_notifier; 2896 } 2897 2898 err = mlxsw_sp_dpipe_init(mlxsw_sp); 2899 if (err) { 2900 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 2901 goto err_dpipe_init; 2902 } 2903 2904 err = mlxsw_sp_port_module_info_init(mlxsw_sp); 2905 if (err) { 2906 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n"); 2907 goto err_port_module_info_init; 2908 } 2909 2910 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht, 2911 &mlxsw_sp_sample_trigger_ht_params); 2912 if (err) { 2913 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n"); 2914 goto err_sample_trigger_init; 2915 } 2916 2917 err = mlxsw_sp_ports_create(mlxsw_sp); 2918 if (err) { 2919 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 2920 goto err_ports_create; 2921 } 2922 2923 return 0; 2924 2925 err_ports_create: 2926 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 2927 err_sample_trigger_init: 2928 mlxsw_sp_port_module_info_fini(mlxsw_sp); 2929 err_port_module_info_init: 2930 mlxsw_sp_dpipe_fini(mlxsw_sp); 2931 err_dpipe_init: 2932 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 2933 &mlxsw_sp->netdevice_nb); 2934 err_netdev_notifier: 2935 if (mlxsw_sp->clock) 2936 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 2937 err_ptp_init: 2938 if (mlxsw_sp->clock) 2939 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 2940 err_ptp_clock_init: 2941 mlxsw_sp_router_fini(mlxsw_sp); 2942 err_router_init: 2943 mlxsw_sp_acl_fini(mlxsw_sp); 2944 err_acl_init: 2945 mlxsw_sp_nve_fini(mlxsw_sp); 2946 err_nve_init: 2947 mlxsw_sp_afa_fini(mlxsw_sp); 2948 err_afa_init: 2949 mlxsw_sp_counter_pool_fini(mlxsw_sp); 2950 err_counter_pool_init: 2951 mlxsw_sp_switchdev_fini(mlxsw_sp); 2952 err_switchdev_init: 2953 mlxsw_sp_span_fini(mlxsw_sp); 2954 err_span_init: 2955 mlxsw_sp_lag_fini(mlxsw_sp); 2956 err_lag_init: 2957 mlxsw_sp_buffers_fini(mlxsw_sp); 2958 err_buffers_init: 2959 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 2960 err_devlink_traps_init: 2961 mlxsw_sp_traps_fini(mlxsw_sp); 2962 err_traps_init: 2963 mlxsw_sp_policers_fini(mlxsw_sp); 2964 err_policers_init: 2965 mlxsw_sp_fids_fini(mlxsw_sp); 2966 err_fids_init: 2967 mlxsw_sp_kvdl_fini(mlxsw_sp); 2968 mlxsw_sp_parsing_fini(mlxsw_sp); 2969 return err; 2970 } 2971 2972 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 2973 const struct mlxsw_bus_info *mlxsw_bus_info, 2974 struct netlink_ext_ack *extack) 2975 { 2976 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2977 2978 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops; 2979 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 2980 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 2981 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 2982 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 2983 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops; 2984 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 2985 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 2986 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask; 2987 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals; 2988 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops; 2989 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops; 2990 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops; 2991 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops; 2992 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops; 2993 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops; 2994 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops; 2995 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops; 2996 mlxsw_sp->listeners = mlxsw_sp1_listener; 2997 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener); 2998 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1; 2999 3000 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3001 } 3002 3003 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3004 const struct mlxsw_bus_info *mlxsw_bus_info, 3005 struct netlink_ext_ack *extack) 3006 { 3007 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3008 3009 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3010 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3011 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3012 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3013 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3014 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3015 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3016 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3017 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3018 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3019 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops; 3020 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3021 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3022 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops; 3023 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3024 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3025 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3026 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3027 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2; 3028 3029 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3030 } 3031 3032 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core, 3033 const struct mlxsw_bus_info *mlxsw_bus_info, 3034 struct netlink_ext_ack *extack) 3035 { 3036 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3037 3038 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3039 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3040 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3041 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3042 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3043 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3044 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3045 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3046 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3047 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3048 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3049 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3050 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3051 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3052 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3053 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3054 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3055 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3056 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3; 3057 3058 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3059 } 3060 3061 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3062 { 3063 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3064 3065 mlxsw_sp_ports_remove(mlxsw_sp); 3066 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3067 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3068 mlxsw_sp_dpipe_fini(mlxsw_sp); 3069 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3070 &mlxsw_sp->netdevice_nb); 3071 if (mlxsw_sp->clock) { 3072 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3073 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3074 } 3075 mlxsw_sp_router_fini(mlxsw_sp); 3076 mlxsw_sp_acl_fini(mlxsw_sp); 3077 mlxsw_sp_nve_fini(mlxsw_sp); 3078 mlxsw_sp_afa_fini(mlxsw_sp); 3079 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3080 mlxsw_sp_switchdev_fini(mlxsw_sp); 3081 mlxsw_sp_span_fini(mlxsw_sp); 3082 mlxsw_sp_lag_fini(mlxsw_sp); 3083 mlxsw_sp_buffers_fini(mlxsw_sp); 3084 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3085 mlxsw_sp_traps_fini(mlxsw_sp); 3086 mlxsw_sp_policers_fini(mlxsw_sp); 3087 mlxsw_sp_fids_fini(mlxsw_sp); 3088 mlxsw_sp_kvdl_fini(mlxsw_sp); 3089 mlxsw_sp_parsing_fini(mlxsw_sp); 3090 } 3091 3092 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated 3093 * 802.1Q FIDs 3094 */ 3095 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE (MLXSW_SP_FID_8021D_MAX + \ 3096 VLAN_VID_MASK - 1) 3097 3098 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3099 .used_max_mid = 1, 3100 .max_mid = MLXSW_SP_MID_MAX, 3101 .used_flood_tables = 1, 3102 .used_flood_mode = 1, 3103 .flood_mode = 3, 3104 .max_fid_flood_tables = 3, 3105 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE, 3106 .used_max_ib_mc = 1, 3107 .max_ib_mc = 0, 3108 .used_max_pkey = 1, 3109 .max_pkey = 0, 3110 .used_kvd_sizes = 1, 3111 .kvd_hash_single_parts = 59, 3112 .kvd_hash_double_parts = 41, 3113 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3114 .swid_config = { 3115 { 3116 .used_type = 1, 3117 .type = MLXSW_PORT_SWID_TYPE_ETH, 3118 } 3119 }, 3120 }; 3121 3122 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3123 .used_max_mid = 1, 3124 .max_mid = MLXSW_SP_MID_MAX, 3125 .used_flood_tables = 1, 3126 .used_flood_mode = 1, 3127 .flood_mode = 3, 3128 .max_fid_flood_tables = 3, 3129 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE, 3130 .used_max_ib_mc = 1, 3131 .max_ib_mc = 0, 3132 .used_max_pkey = 1, 3133 .max_pkey = 0, 3134 .used_kvh_xlt_cache_mode = 1, 3135 .kvh_xlt_cache_mode = 1, 3136 .swid_config = { 3137 { 3138 .used_type = 1, 3139 .type = MLXSW_PORT_SWID_TYPE_ETH, 3140 } 3141 }, 3142 }; 3143 3144 static void 3145 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3146 struct devlink_resource_size_params *kvd_size_params, 3147 struct devlink_resource_size_params *linear_size_params, 3148 struct devlink_resource_size_params *hash_double_size_params, 3149 struct devlink_resource_size_params *hash_single_size_params) 3150 { 3151 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3152 KVD_SINGLE_MIN_SIZE); 3153 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3154 KVD_DOUBLE_MIN_SIZE); 3155 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3156 u32 linear_size_min = 0; 3157 3158 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3159 MLXSW_SP_KVD_GRANULARITY, 3160 DEVLINK_RESOURCE_UNIT_ENTRY); 3161 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3162 kvd_size - single_size_min - 3163 double_size_min, 3164 MLXSW_SP_KVD_GRANULARITY, 3165 DEVLINK_RESOURCE_UNIT_ENTRY); 3166 devlink_resource_size_params_init(hash_double_size_params, 3167 double_size_min, 3168 kvd_size - single_size_min - 3169 linear_size_min, 3170 MLXSW_SP_KVD_GRANULARITY, 3171 DEVLINK_RESOURCE_UNIT_ENTRY); 3172 devlink_resource_size_params_init(hash_single_size_params, 3173 single_size_min, 3174 kvd_size - double_size_min - 3175 linear_size_min, 3176 MLXSW_SP_KVD_GRANULARITY, 3177 DEVLINK_RESOURCE_UNIT_ENTRY); 3178 } 3179 3180 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3181 { 3182 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3183 struct devlink_resource_size_params hash_single_size_params; 3184 struct devlink_resource_size_params hash_double_size_params; 3185 struct devlink_resource_size_params linear_size_params; 3186 struct devlink_resource_size_params kvd_size_params; 3187 u32 kvd_size, single_size, double_size, linear_size; 3188 const struct mlxsw_config_profile *profile; 3189 int err; 3190 3191 profile = &mlxsw_sp1_config_profile; 3192 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3193 return -EIO; 3194 3195 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3196 &linear_size_params, 3197 &hash_double_size_params, 3198 &hash_single_size_params); 3199 3200 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3201 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3202 kvd_size, MLXSW_SP_RESOURCE_KVD, 3203 DEVLINK_RESOURCE_ID_PARENT_TOP, 3204 &kvd_size_params); 3205 if (err) 3206 return err; 3207 3208 linear_size = profile->kvd_linear_size; 3209 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3210 linear_size, 3211 MLXSW_SP_RESOURCE_KVD_LINEAR, 3212 MLXSW_SP_RESOURCE_KVD, 3213 &linear_size_params); 3214 if (err) 3215 return err; 3216 3217 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 3218 if (err) 3219 return err; 3220 3221 double_size = kvd_size - linear_size; 3222 double_size *= profile->kvd_hash_double_parts; 3223 double_size /= profile->kvd_hash_double_parts + 3224 profile->kvd_hash_single_parts; 3225 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3226 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3227 double_size, 3228 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3229 MLXSW_SP_RESOURCE_KVD, 3230 &hash_double_size_params); 3231 if (err) 3232 return err; 3233 3234 single_size = kvd_size - double_size - linear_size; 3235 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3236 single_size, 3237 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3238 MLXSW_SP_RESOURCE_KVD, 3239 &hash_single_size_params); 3240 if (err) 3241 return err; 3242 3243 return 0; 3244 } 3245 3246 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3247 { 3248 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3249 struct devlink_resource_size_params kvd_size_params; 3250 u32 kvd_size; 3251 3252 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3253 return -EIO; 3254 3255 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3256 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size, 3257 MLXSW_SP_KVD_GRANULARITY, 3258 DEVLINK_RESOURCE_UNIT_ENTRY); 3259 3260 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3261 kvd_size, MLXSW_SP_RESOURCE_KVD, 3262 DEVLINK_RESOURCE_ID_PARENT_TOP, 3263 &kvd_size_params); 3264 } 3265 3266 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core) 3267 { 3268 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3269 struct devlink_resource_size_params span_size_params; 3270 u32 max_span; 3271 3272 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN)) 3273 return -EIO; 3274 3275 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN); 3276 devlink_resource_size_params_init(&span_size_params, max_span, max_span, 3277 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3278 3279 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN, 3280 max_span, MLXSW_SP_RESOURCE_SPAN, 3281 DEVLINK_RESOURCE_ID_PARENT_TOP, 3282 &span_size_params); 3283 } 3284 3285 static int 3286 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core) 3287 { 3288 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3289 struct devlink_resource_size_params size_params; 3290 u8 max_rif_mac_profiles; 3291 3292 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES)) 3293 max_rif_mac_profiles = 1; 3294 else 3295 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core, 3296 MAX_RIF_MAC_PROFILES); 3297 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles, 3298 max_rif_mac_profiles, 1, 3299 DEVLINK_RESOURCE_UNIT_ENTRY); 3300 3301 return devlink_resource_register(devlink, 3302 "rif_mac_profiles", 3303 max_rif_mac_profiles, 3304 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES, 3305 DEVLINK_RESOURCE_ID_PARENT_TOP, 3306 &size_params); 3307 } 3308 3309 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 3310 { 3311 int err; 3312 3313 err = mlxsw_sp1_resources_kvd_register(mlxsw_core); 3314 if (err) 3315 return err; 3316 3317 err = mlxsw_sp_resources_span_register(mlxsw_core); 3318 if (err) 3319 goto err_resources_span_register; 3320 3321 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3322 if (err) 3323 goto err_resources_counter_register; 3324 3325 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3326 if (err) 3327 goto err_policer_resources_register; 3328 3329 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3330 if (err) 3331 goto err_resources_rif_mac_profile_register; 3332 3333 return 0; 3334 3335 err_resources_rif_mac_profile_register: 3336 err_policer_resources_register: 3337 err_resources_counter_register: 3338 err_resources_span_register: 3339 devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL); 3340 return err; 3341 } 3342 3343 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 3344 { 3345 int err; 3346 3347 err = mlxsw_sp2_resources_kvd_register(mlxsw_core); 3348 if (err) 3349 return err; 3350 3351 err = mlxsw_sp_resources_span_register(mlxsw_core); 3352 if (err) 3353 goto err_resources_span_register; 3354 3355 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3356 if (err) 3357 goto err_resources_counter_register; 3358 3359 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3360 if (err) 3361 goto err_policer_resources_register; 3362 3363 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3364 if (err) 3365 goto err_resources_rif_mac_profile_register; 3366 3367 return 0; 3368 3369 err_resources_rif_mac_profile_register: 3370 err_policer_resources_register: 3371 err_resources_counter_register: 3372 err_resources_span_register: 3373 devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL); 3374 return err; 3375 } 3376 3377 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3378 const struct mlxsw_config_profile *profile, 3379 u64 *p_single_size, u64 *p_double_size, 3380 u64 *p_linear_size) 3381 { 3382 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3383 u32 double_size; 3384 int err; 3385 3386 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3387 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3388 return -EIO; 3389 3390 /* The hash part is what left of the kvd without the 3391 * linear part. It is split to the single size and 3392 * double size by the parts ratio from the profile. 3393 * Both sizes must be a multiplications of the 3394 * granularity from the profile. In case the user 3395 * provided the sizes they are obtained via devlink. 3396 */ 3397 err = devlink_resource_size_get(devlink, 3398 MLXSW_SP_RESOURCE_KVD_LINEAR, 3399 p_linear_size); 3400 if (err) 3401 *p_linear_size = profile->kvd_linear_size; 3402 3403 err = devlink_resource_size_get(devlink, 3404 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3405 p_double_size); 3406 if (err) { 3407 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3408 *p_linear_size; 3409 double_size *= profile->kvd_hash_double_parts; 3410 double_size /= profile->kvd_hash_double_parts + 3411 profile->kvd_hash_single_parts; 3412 *p_double_size = rounddown(double_size, 3413 MLXSW_SP_KVD_GRANULARITY); 3414 } 3415 3416 err = devlink_resource_size_get(devlink, 3417 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3418 p_single_size); 3419 if (err) 3420 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3421 *p_double_size - *p_linear_size; 3422 3423 /* Check results are legal. */ 3424 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3425 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3426 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3427 return -EIO; 3428 3429 return 0; 3430 } 3431 3432 static int 3433 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id, 3434 struct devlink_param_gset_ctx *ctx) 3435 { 3436 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3437 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3438 3439 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp); 3440 return 0; 3441 } 3442 3443 static int 3444 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id, 3445 struct devlink_param_gset_ctx *ctx) 3446 { 3447 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3448 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3449 3450 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32); 3451 } 3452 3453 static const struct devlink_param mlxsw_sp2_devlink_params[] = { 3454 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 3455 "acl_region_rehash_interval", 3456 DEVLINK_PARAM_TYPE_U32, 3457 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3458 mlxsw_sp_params_acl_region_rehash_intrvl_get, 3459 mlxsw_sp_params_acl_region_rehash_intrvl_set, 3460 NULL), 3461 }; 3462 3463 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core) 3464 { 3465 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3466 union devlink_param_value value; 3467 int err; 3468 3469 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params, 3470 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 3471 if (err) 3472 return err; 3473 3474 value.vu32 = 0; 3475 devlink_param_driverinit_value_set(devlink, 3476 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 3477 value); 3478 return 0; 3479 } 3480 3481 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core) 3482 { 3483 devlink_params_unregister(priv_to_devlink(mlxsw_core), 3484 mlxsw_sp2_devlink_params, 3485 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 3486 } 3487 3488 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core, 3489 struct sk_buff *skb, u8 local_port) 3490 { 3491 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3492 3493 skb_pull(skb, MLXSW_TXHDR_LEN); 3494 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port); 3495 } 3496 3497 static struct mlxsw_driver mlxsw_sp1_driver = { 3498 .kind = mlxsw_sp1_driver_name, 3499 .priv_size = sizeof(struct mlxsw_sp), 3500 .fw_req_rev = &mlxsw_sp1_fw_rev, 3501 .fw_filename = MLXSW_SP1_FW_FILENAME, 3502 .init = mlxsw_sp1_init, 3503 .fini = mlxsw_sp_fini, 3504 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3505 .port_split = mlxsw_sp_port_split, 3506 .port_unsplit = mlxsw_sp_port_unsplit, 3507 .sb_pool_get = mlxsw_sp_sb_pool_get, 3508 .sb_pool_set = mlxsw_sp_sb_pool_set, 3509 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3510 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3511 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3512 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3513 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3514 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3515 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3516 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3517 .trap_init = mlxsw_sp_trap_init, 3518 .trap_fini = mlxsw_sp_trap_fini, 3519 .trap_action_set = mlxsw_sp_trap_action_set, 3520 .trap_group_init = mlxsw_sp_trap_group_init, 3521 .trap_group_set = mlxsw_sp_trap_group_set, 3522 .trap_policer_init = mlxsw_sp_trap_policer_init, 3523 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3524 .trap_policer_set = mlxsw_sp_trap_policer_set, 3525 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3526 .txhdr_construct = mlxsw_sp_txhdr_construct, 3527 .resources_register = mlxsw_sp1_resources_register, 3528 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 3529 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3530 .txhdr_len = MLXSW_TXHDR_LEN, 3531 .profile = &mlxsw_sp1_config_profile, 3532 .res_query_enabled = true, 3533 .fw_fatal_enabled = true, 3534 .temp_warn_enabled = true, 3535 }; 3536 3537 static struct mlxsw_driver mlxsw_sp2_driver = { 3538 .kind = mlxsw_sp2_driver_name, 3539 .priv_size = sizeof(struct mlxsw_sp), 3540 .fw_req_rev = &mlxsw_sp2_fw_rev, 3541 .fw_filename = MLXSW_SP2_FW_FILENAME, 3542 .init = mlxsw_sp2_init, 3543 .fini = mlxsw_sp_fini, 3544 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3545 .port_split = mlxsw_sp_port_split, 3546 .port_unsplit = mlxsw_sp_port_unsplit, 3547 .sb_pool_get = mlxsw_sp_sb_pool_get, 3548 .sb_pool_set = mlxsw_sp_sb_pool_set, 3549 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3550 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3551 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3552 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3553 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3554 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3555 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3556 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3557 .trap_init = mlxsw_sp_trap_init, 3558 .trap_fini = mlxsw_sp_trap_fini, 3559 .trap_action_set = mlxsw_sp_trap_action_set, 3560 .trap_group_init = mlxsw_sp_trap_group_init, 3561 .trap_group_set = mlxsw_sp_trap_group_set, 3562 .trap_policer_init = mlxsw_sp_trap_policer_init, 3563 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3564 .trap_policer_set = mlxsw_sp_trap_policer_set, 3565 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3566 .txhdr_construct = mlxsw_sp_txhdr_construct, 3567 .resources_register = mlxsw_sp2_resources_register, 3568 .params_register = mlxsw_sp2_params_register, 3569 .params_unregister = mlxsw_sp2_params_unregister, 3570 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3571 .txhdr_len = MLXSW_TXHDR_LEN, 3572 .profile = &mlxsw_sp2_config_profile, 3573 .res_query_enabled = true, 3574 .fw_fatal_enabled = true, 3575 .temp_warn_enabled = true, 3576 }; 3577 3578 static struct mlxsw_driver mlxsw_sp3_driver = { 3579 .kind = mlxsw_sp3_driver_name, 3580 .priv_size = sizeof(struct mlxsw_sp), 3581 .fw_req_rev = &mlxsw_sp3_fw_rev, 3582 .fw_filename = MLXSW_SP3_FW_FILENAME, 3583 .init = mlxsw_sp3_init, 3584 .fini = mlxsw_sp_fini, 3585 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3586 .port_split = mlxsw_sp_port_split, 3587 .port_unsplit = mlxsw_sp_port_unsplit, 3588 .sb_pool_get = mlxsw_sp_sb_pool_get, 3589 .sb_pool_set = mlxsw_sp_sb_pool_set, 3590 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3591 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3592 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3593 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3594 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3595 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3596 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3597 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3598 .trap_init = mlxsw_sp_trap_init, 3599 .trap_fini = mlxsw_sp_trap_fini, 3600 .trap_action_set = mlxsw_sp_trap_action_set, 3601 .trap_group_init = mlxsw_sp_trap_group_init, 3602 .trap_group_set = mlxsw_sp_trap_group_set, 3603 .trap_policer_init = mlxsw_sp_trap_policer_init, 3604 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3605 .trap_policer_set = mlxsw_sp_trap_policer_set, 3606 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3607 .txhdr_construct = mlxsw_sp_txhdr_construct, 3608 .resources_register = mlxsw_sp2_resources_register, 3609 .params_register = mlxsw_sp2_params_register, 3610 .params_unregister = mlxsw_sp2_params_unregister, 3611 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3612 .txhdr_len = MLXSW_TXHDR_LEN, 3613 .profile = &mlxsw_sp2_config_profile, 3614 .res_query_enabled = true, 3615 .fw_fatal_enabled = true, 3616 .temp_warn_enabled = true, 3617 }; 3618 3619 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 3620 { 3621 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 3622 } 3623 3624 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, 3625 struct netdev_nested_priv *priv) 3626 { 3627 int ret = 0; 3628 3629 if (mlxsw_sp_port_dev_check(lower_dev)) { 3630 priv->data = (void *)netdev_priv(lower_dev); 3631 ret = 1; 3632 } 3633 3634 return ret; 3635 } 3636 3637 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 3638 { 3639 struct netdev_nested_priv priv = { 3640 .data = NULL, 3641 }; 3642 3643 if (mlxsw_sp_port_dev_check(dev)) 3644 return netdev_priv(dev); 3645 3646 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv); 3647 3648 return (struct mlxsw_sp_port *)priv.data; 3649 } 3650 3651 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 3652 { 3653 struct mlxsw_sp_port *mlxsw_sp_port; 3654 3655 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 3656 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 3657 } 3658 3659 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 3660 { 3661 struct netdev_nested_priv priv = { 3662 .data = NULL, 3663 }; 3664 3665 if (mlxsw_sp_port_dev_check(dev)) 3666 return netdev_priv(dev); 3667 3668 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 3669 &priv); 3670 3671 return (struct mlxsw_sp_port *)priv.data; 3672 } 3673 3674 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 3675 { 3676 struct mlxsw_sp_port *mlxsw_sp_port; 3677 3678 rcu_read_lock(); 3679 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 3680 if (mlxsw_sp_port) 3681 dev_hold(mlxsw_sp_port->dev); 3682 rcu_read_unlock(); 3683 return mlxsw_sp_port; 3684 } 3685 3686 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 3687 { 3688 dev_put(mlxsw_sp_port->dev); 3689 } 3690 3691 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp) 3692 { 3693 char mprs_pl[MLXSW_REG_MPRS_LEN]; 3694 int err = 0; 3695 3696 mutex_lock(&mlxsw_sp->parsing.lock); 3697 3698 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref)) 3699 goto out_unlock; 3700 3701 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH, 3702 mlxsw_sp->parsing.vxlan_udp_dport); 3703 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 3704 if (err) 3705 goto out_unlock; 3706 3707 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH; 3708 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1); 3709 3710 out_unlock: 3711 mutex_unlock(&mlxsw_sp->parsing.lock); 3712 return err; 3713 } 3714 3715 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp) 3716 { 3717 char mprs_pl[MLXSW_REG_MPRS_LEN]; 3718 3719 mutex_lock(&mlxsw_sp->parsing.lock); 3720 3721 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref)) 3722 goto out_unlock; 3723 3724 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH, 3725 mlxsw_sp->parsing.vxlan_udp_dport); 3726 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 3727 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 3728 3729 out_unlock: 3730 mutex_unlock(&mlxsw_sp->parsing.lock); 3731 } 3732 3733 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp, 3734 __be16 udp_dport) 3735 { 3736 char mprs_pl[MLXSW_REG_MPRS_LEN]; 3737 int err; 3738 3739 mutex_lock(&mlxsw_sp->parsing.lock); 3740 3741 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth, 3742 be16_to_cpu(udp_dport)); 3743 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 3744 if (err) 3745 goto out_unlock; 3746 3747 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport); 3748 3749 out_unlock: 3750 mutex_unlock(&mlxsw_sp->parsing.lock); 3751 return err; 3752 } 3753 3754 static void 3755 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port, 3756 struct net_device *lag_dev) 3757 { 3758 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev); 3759 struct net_device *upper_dev; 3760 struct list_head *iter; 3761 3762 if (netif_is_bridge_port(lag_dev)) 3763 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev); 3764 3765 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 3766 if (!netif_is_bridge_port(upper_dev)) 3767 continue; 3768 br_dev = netdev_master_upper_dev_get(upper_dev); 3769 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev); 3770 } 3771 } 3772 3773 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 3774 { 3775 char sldr_pl[MLXSW_REG_SLDR_LEN]; 3776 3777 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 3778 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 3779 } 3780 3781 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 3782 { 3783 char sldr_pl[MLXSW_REG_SLDR_LEN]; 3784 3785 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 3786 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 3787 } 3788 3789 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 3790 u16 lag_id, u8 port_index) 3791 { 3792 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3793 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 3794 3795 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 3796 lag_id, port_index); 3797 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 3798 } 3799 3800 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 3801 u16 lag_id) 3802 { 3803 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3804 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 3805 3806 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 3807 lag_id); 3808 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 3809 } 3810 3811 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 3812 u16 lag_id) 3813 { 3814 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3815 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 3816 3817 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 3818 lag_id); 3819 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 3820 } 3821 3822 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 3823 u16 lag_id) 3824 { 3825 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3826 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 3827 3828 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 3829 lag_id); 3830 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 3831 } 3832 3833 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 3834 struct net_device *lag_dev, 3835 u16 *p_lag_id) 3836 { 3837 struct mlxsw_sp_upper *lag; 3838 int free_lag_id = -1; 3839 u64 max_lag; 3840 int i; 3841 3842 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 3843 for (i = 0; i < max_lag; i++) { 3844 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 3845 if (lag->ref_count) { 3846 if (lag->dev == lag_dev) { 3847 *p_lag_id = i; 3848 return 0; 3849 } 3850 } else if (free_lag_id < 0) { 3851 free_lag_id = i; 3852 } 3853 } 3854 if (free_lag_id < 0) 3855 return -EBUSY; 3856 *p_lag_id = free_lag_id; 3857 return 0; 3858 } 3859 3860 static bool 3861 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 3862 struct net_device *lag_dev, 3863 struct netdev_lag_upper_info *lag_upper_info, 3864 struct netlink_ext_ack *extack) 3865 { 3866 u16 lag_id; 3867 3868 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 3869 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 3870 return false; 3871 } 3872 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 3873 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 3874 return false; 3875 } 3876 return true; 3877 } 3878 3879 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 3880 u16 lag_id, u8 *p_port_index) 3881 { 3882 u64 max_lag_members; 3883 int i; 3884 3885 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 3886 MAX_LAG_MEMBERS); 3887 for (i = 0; i < max_lag_members; i++) { 3888 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 3889 *p_port_index = i; 3890 return 0; 3891 } 3892 } 3893 return -EBUSY; 3894 } 3895 3896 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 3897 struct net_device *lag_dev, 3898 struct netlink_ext_ack *extack) 3899 { 3900 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3901 struct mlxsw_sp_upper *lag; 3902 u16 lag_id; 3903 u8 port_index; 3904 int err; 3905 3906 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 3907 if (err) 3908 return err; 3909 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 3910 if (!lag->ref_count) { 3911 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 3912 if (err) 3913 return err; 3914 lag->dev = lag_dev; 3915 } 3916 3917 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 3918 if (err) 3919 return err; 3920 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 3921 if (err) 3922 goto err_col_port_add; 3923 3924 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 3925 mlxsw_sp_port->local_port); 3926 mlxsw_sp_port->lag_id = lag_id; 3927 mlxsw_sp_port->lagged = 1; 3928 lag->ref_count++; 3929 3930 /* Port is no longer usable as a router interface */ 3931 if (mlxsw_sp_port->default_vlan->fid) 3932 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan); 3933 3934 /* Join a router interface configured on the LAG, if exists */ 3935 err = mlxsw_sp_port_vlan_router_join(mlxsw_sp_port->default_vlan, 3936 lag_dev, extack); 3937 if (err) 3938 goto err_router_join; 3939 3940 return 0; 3941 3942 err_router_join: 3943 lag->ref_count--; 3944 mlxsw_sp_port->lagged = 0; 3945 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 3946 mlxsw_sp_port->local_port); 3947 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 3948 err_col_port_add: 3949 if (!lag->ref_count) 3950 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 3951 return err; 3952 } 3953 3954 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 3955 struct net_device *lag_dev) 3956 { 3957 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3958 u16 lag_id = mlxsw_sp_port->lag_id; 3959 struct mlxsw_sp_upper *lag; 3960 3961 if (!mlxsw_sp_port->lagged) 3962 return; 3963 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 3964 WARN_ON(lag->ref_count == 0); 3965 3966 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 3967 3968 /* Any VLANs configured on the port are no longer valid */ 3969 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false); 3970 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan); 3971 /* Make the LAG and its directly linked uppers leave bridges they 3972 * are memeber in 3973 */ 3974 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev); 3975 3976 if (lag->ref_count == 1) 3977 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 3978 3979 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 3980 mlxsw_sp_port->local_port); 3981 mlxsw_sp_port->lagged = 0; 3982 lag->ref_count--; 3983 3984 /* Make sure untagged frames are allowed to ingress */ 3985 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 3986 ETH_P_8021Q); 3987 } 3988 3989 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 3990 u16 lag_id) 3991 { 3992 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3993 char sldr_pl[MLXSW_REG_SLDR_LEN]; 3994 3995 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 3996 mlxsw_sp_port->local_port); 3997 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 3998 } 3999 4000 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4001 u16 lag_id) 4002 { 4003 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4004 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4005 4006 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4007 mlxsw_sp_port->local_port); 4008 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4009 } 4010 4011 static int 4012 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port) 4013 { 4014 int err; 4015 4016 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, 4017 mlxsw_sp_port->lag_id); 4018 if (err) 4019 return err; 4020 4021 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4022 if (err) 4023 goto err_dist_port_add; 4024 4025 return 0; 4026 4027 err_dist_port_add: 4028 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4029 return err; 4030 } 4031 4032 static int 4033 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port) 4034 { 4035 int err; 4036 4037 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4038 mlxsw_sp_port->lag_id); 4039 if (err) 4040 return err; 4041 4042 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, 4043 mlxsw_sp_port->lag_id); 4044 if (err) 4045 goto err_col_port_disable; 4046 4047 return 0; 4048 4049 err_col_port_disable: 4050 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4051 return err; 4052 } 4053 4054 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4055 struct netdev_lag_lower_state_info *info) 4056 { 4057 if (info->tx_enabled) 4058 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port); 4059 else 4060 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4061 } 4062 4063 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4064 bool enable) 4065 { 4066 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4067 enum mlxsw_reg_spms_state spms_state; 4068 char *spms_pl; 4069 u16 vid; 4070 int err; 4071 4072 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4073 MLXSW_REG_SPMS_STATE_DISCARDING; 4074 4075 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4076 if (!spms_pl) 4077 return -ENOMEM; 4078 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4079 4080 for (vid = 0; vid < VLAN_N_VID; vid++) 4081 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4082 4083 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4084 kfree(spms_pl); 4085 return err; 4086 } 4087 4088 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4089 { 4090 u16 vid = 1; 4091 int err; 4092 4093 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4094 if (err) 4095 return err; 4096 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4097 if (err) 4098 goto err_port_stp_set; 4099 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4100 true, false); 4101 if (err) 4102 goto err_port_vlan_set; 4103 4104 for (; vid <= VLAN_N_VID - 1; vid++) { 4105 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4106 vid, false); 4107 if (err) 4108 goto err_vid_learning_set; 4109 } 4110 4111 return 0; 4112 4113 err_vid_learning_set: 4114 for (vid--; vid >= 1; vid--) 4115 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4116 err_port_vlan_set: 4117 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4118 err_port_stp_set: 4119 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4120 return err; 4121 } 4122 4123 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4124 { 4125 u16 vid; 4126 4127 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4128 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4129 vid, true); 4130 4131 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4132 false, false); 4133 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4134 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4135 } 4136 4137 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4138 { 4139 unsigned int num_vxlans = 0; 4140 struct net_device *dev; 4141 struct list_head *iter; 4142 4143 netdev_for_each_lower_dev(br_dev, dev, iter) { 4144 if (netif_is_vxlan(dev)) 4145 num_vxlans++; 4146 } 4147 4148 return num_vxlans > 1; 4149 } 4150 4151 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev) 4152 { 4153 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0}; 4154 struct net_device *dev; 4155 struct list_head *iter; 4156 4157 netdev_for_each_lower_dev(br_dev, dev, iter) { 4158 u16 pvid; 4159 int err; 4160 4161 if (!netif_is_vxlan(dev)) 4162 continue; 4163 4164 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid); 4165 if (err || !pvid) 4166 continue; 4167 4168 if (test_and_set_bit(pvid, vlans)) 4169 return false; 4170 } 4171 4172 return true; 4173 } 4174 4175 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4176 struct netlink_ext_ack *extack) 4177 { 4178 if (br_multicast_enabled(br_dev)) { 4179 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4180 return false; 4181 } 4182 4183 if (!br_vlan_enabled(br_dev) && 4184 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4185 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4186 return false; 4187 } 4188 4189 if (br_vlan_enabled(br_dev) && 4190 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) { 4191 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged"); 4192 return false; 4193 } 4194 4195 return true; 4196 } 4197 4198 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4199 struct net_device *dev, 4200 unsigned long event, void *ptr) 4201 { 4202 struct netdev_notifier_changeupper_info *info; 4203 struct mlxsw_sp_port *mlxsw_sp_port; 4204 struct netlink_ext_ack *extack; 4205 struct net_device *upper_dev; 4206 struct mlxsw_sp *mlxsw_sp; 4207 int err = 0; 4208 u16 proto; 4209 4210 mlxsw_sp_port = netdev_priv(dev); 4211 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4212 info = ptr; 4213 extack = netdev_notifier_info_to_extack(&info->info); 4214 4215 switch (event) { 4216 case NETDEV_PRECHANGEUPPER: 4217 upper_dev = info->upper_dev; 4218 if (!is_vlan_dev(upper_dev) && 4219 !netif_is_lag_master(upper_dev) && 4220 !netif_is_bridge_master(upper_dev) && 4221 !netif_is_ovs_master(upper_dev) && 4222 !netif_is_macvlan(upper_dev)) { 4223 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4224 return -EINVAL; 4225 } 4226 if (!info->linking) 4227 break; 4228 if (netif_is_bridge_master(upper_dev) && 4229 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4230 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4231 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4232 return -EOPNOTSUPP; 4233 if (netdev_has_any_upper_dev(upper_dev) && 4234 (!netif_is_bridge_master(upper_dev) || 4235 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4236 upper_dev))) { 4237 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4238 return -EINVAL; 4239 } 4240 if (netif_is_lag_master(upper_dev) && 4241 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4242 info->upper_info, extack)) 4243 return -EINVAL; 4244 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4245 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4246 return -EINVAL; 4247 } 4248 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4249 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4250 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4251 return -EINVAL; 4252 } 4253 if (netif_is_macvlan(upper_dev) && 4254 !mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) { 4255 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4256 return -EOPNOTSUPP; 4257 } 4258 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4259 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4260 return -EINVAL; 4261 } 4262 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4263 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4264 return -EINVAL; 4265 } 4266 if (netif_is_bridge_master(upper_dev)) { 4267 br_vlan_get_proto(upper_dev, &proto); 4268 if (br_vlan_enabled(upper_dev) && 4269 proto != ETH_P_8021Q && proto != ETH_P_8021AD) { 4270 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported"); 4271 return -EOPNOTSUPP; 4272 } 4273 if (vlan_uses_dev(lower_dev) && 4274 br_vlan_enabled(upper_dev) && 4275 proto == ETH_P_8021AD) { 4276 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported"); 4277 return -EOPNOTSUPP; 4278 } 4279 } 4280 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) { 4281 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev); 4282 4283 if (br_vlan_enabled(br_dev)) { 4284 br_vlan_get_proto(br_dev, &proto); 4285 if (proto == ETH_P_8021AD) { 4286 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge"); 4287 return -EOPNOTSUPP; 4288 } 4289 } 4290 } 4291 if (is_vlan_dev(upper_dev) && 4292 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4293 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4294 return -EOPNOTSUPP; 4295 } 4296 break; 4297 case NETDEV_CHANGEUPPER: 4298 upper_dev = info->upper_dev; 4299 if (netif_is_bridge_master(upper_dev)) { 4300 if (info->linking) 4301 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4302 lower_dev, 4303 upper_dev, 4304 extack); 4305 else 4306 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4307 lower_dev, 4308 upper_dev); 4309 } else if (netif_is_lag_master(upper_dev)) { 4310 if (info->linking) { 4311 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4312 upper_dev, extack); 4313 } else { 4314 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4315 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4316 upper_dev); 4317 } 4318 } else if (netif_is_ovs_master(upper_dev)) { 4319 if (info->linking) 4320 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4321 else 4322 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4323 } else if (netif_is_macvlan(upper_dev)) { 4324 if (!info->linking) 4325 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4326 } else if (is_vlan_dev(upper_dev)) { 4327 struct net_device *br_dev; 4328 4329 if (!netif_is_bridge_port(upper_dev)) 4330 break; 4331 if (info->linking) 4332 break; 4333 br_dev = netdev_master_upper_dev_get(upper_dev); 4334 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, 4335 br_dev); 4336 } 4337 break; 4338 } 4339 4340 return err; 4341 } 4342 4343 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4344 unsigned long event, void *ptr) 4345 { 4346 struct netdev_notifier_changelowerstate_info *info; 4347 struct mlxsw_sp_port *mlxsw_sp_port; 4348 int err; 4349 4350 mlxsw_sp_port = netdev_priv(dev); 4351 info = ptr; 4352 4353 switch (event) { 4354 case NETDEV_CHANGELOWERSTATE: 4355 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4356 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4357 info->lower_state_info); 4358 if (err) 4359 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4360 } 4361 break; 4362 } 4363 4364 return 0; 4365 } 4366 4367 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4368 struct net_device *port_dev, 4369 unsigned long event, void *ptr) 4370 { 4371 switch (event) { 4372 case NETDEV_PRECHANGEUPPER: 4373 case NETDEV_CHANGEUPPER: 4374 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4375 event, ptr); 4376 case NETDEV_CHANGELOWERSTATE: 4377 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4378 ptr); 4379 } 4380 4381 return 0; 4382 } 4383 4384 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4385 unsigned long event, void *ptr) 4386 { 4387 struct net_device *dev; 4388 struct list_head *iter; 4389 int ret; 4390 4391 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4392 if (mlxsw_sp_port_dev_check(dev)) { 4393 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4394 ptr); 4395 if (ret) 4396 return ret; 4397 } 4398 } 4399 4400 return 0; 4401 } 4402 4403 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4404 struct net_device *dev, 4405 unsigned long event, void *ptr, 4406 u16 vid) 4407 { 4408 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4409 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4410 struct netdev_notifier_changeupper_info *info = ptr; 4411 struct netlink_ext_ack *extack; 4412 struct net_device *upper_dev; 4413 int err = 0; 4414 4415 extack = netdev_notifier_info_to_extack(&info->info); 4416 4417 switch (event) { 4418 case NETDEV_PRECHANGEUPPER: 4419 upper_dev = info->upper_dev; 4420 if (!netif_is_bridge_master(upper_dev) && 4421 !netif_is_macvlan(upper_dev)) { 4422 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4423 return -EINVAL; 4424 } 4425 if (!info->linking) 4426 break; 4427 if (netif_is_bridge_master(upper_dev) && 4428 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4429 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4430 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4431 return -EOPNOTSUPP; 4432 if (netdev_has_any_upper_dev(upper_dev) && 4433 (!netif_is_bridge_master(upper_dev) || 4434 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4435 upper_dev))) { 4436 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4437 return -EINVAL; 4438 } 4439 if (netif_is_macvlan(upper_dev) && 4440 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) { 4441 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4442 return -EOPNOTSUPP; 4443 } 4444 break; 4445 case NETDEV_CHANGEUPPER: 4446 upper_dev = info->upper_dev; 4447 if (netif_is_bridge_master(upper_dev)) { 4448 if (info->linking) 4449 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4450 vlan_dev, 4451 upper_dev, 4452 extack); 4453 else 4454 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4455 vlan_dev, 4456 upper_dev); 4457 } else if (netif_is_macvlan(upper_dev)) { 4458 if (!info->linking) 4459 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4460 } else { 4461 err = -EINVAL; 4462 WARN_ON(1); 4463 } 4464 break; 4465 } 4466 4467 return err; 4468 } 4469 4470 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4471 struct net_device *lag_dev, 4472 unsigned long event, 4473 void *ptr, u16 vid) 4474 { 4475 struct net_device *dev; 4476 struct list_head *iter; 4477 int ret; 4478 4479 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4480 if (mlxsw_sp_port_dev_check(dev)) { 4481 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4482 event, ptr, 4483 vid); 4484 if (ret) 4485 return ret; 4486 } 4487 } 4488 4489 return 0; 4490 } 4491 4492 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev, 4493 struct net_device *br_dev, 4494 unsigned long event, void *ptr, 4495 u16 vid) 4496 { 4497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev); 4498 struct netdev_notifier_changeupper_info *info = ptr; 4499 struct netlink_ext_ack *extack; 4500 struct net_device *upper_dev; 4501 4502 if (!mlxsw_sp) 4503 return 0; 4504 4505 extack = netdev_notifier_info_to_extack(&info->info); 4506 4507 switch (event) { 4508 case NETDEV_PRECHANGEUPPER: 4509 upper_dev = info->upper_dev; 4510 if (!netif_is_macvlan(upper_dev)) { 4511 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4512 return -EOPNOTSUPP; 4513 } 4514 if (!info->linking) 4515 break; 4516 if (netif_is_macvlan(upper_dev) && 4517 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) { 4518 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4519 return -EOPNOTSUPP; 4520 } 4521 break; 4522 case NETDEV_CHANGEUPPER: 4523 upper_dev = info->upper_dev; 4524 if (info->linking) 4525 break; 4526 if (netif_is_macvlan(upper_dev)) 4527 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4528 break; 4529 } 4530 4531 return 0; 4532 } 4533 4534 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4535 unsigned long event, void *ptr) 4536 { 4537 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4538 u16 vid = vlan_dev_vlan_id(vlan_dev); 4539 4540 if (mlxsw_sp_port_dev_check(real_dev)) 4541 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 4542 event, ptr, vid); 4543 else if (netif_is_lag_master(real_dev)) 4544 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 4545 real_dev, event, 4546 ptr, vid); 4547 else if (netif_is_bridge_master(real_dev)) 4548 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev, 4549 event, ptr, vid); 4550 4551 return 0; 4552 } 4553 4554 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 4555 unsigned long event, void *ptr) 4556 { 4557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 4558 struct netdev_notifier_changeupper_info *info = ptr; 4559 struct netlink_ext_ack *extack; 4560 struct net_device *upper_dev; 4561 u16 proto; 4562 4563 if (!mlxsw_sp) 4564 return 0; 4565 4566 extack = netdev_notifier_info_to_extack(&info->info); 4567 4568 switch (event) { 4569 case NETDEV_PRECHANGEUPPER: 4570 upper_dev = info->upper_dev; 4571 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) { 4572 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4573 return -EOPNOTSUPP; 4574 } 4575 if (!info->linking) 4576 break; 4577 if (br_vlan_enabled(br_dev)) { 4578 br_vlan_get_proto(br_dev, &proto); 4579 if (proto == ETH_P_8021AD) { 4580 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge"); 4581 return -EOPNOTSUPP; 4582 } 4583 } 4584 if (is_vlan_dev(upper_dev) && 4585 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4586 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4587 return -EOPNOTSUPP; 4588 } 4589 if (netif_is_macvlan(upper_dev) && 4590 !mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) { 4591 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4592 return -EOPNOTSUPP; 4593 } 4594 break; 4595 case NETDEV_CHANGEUPPER: 4596 upper_dev = info->upper_dev; 4597 if (info->linking) 4598 break; 4599 if (is_vlan_dev(upper_dev)) 4600 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 4601 if (netif_is_macvlan(upper_dev)) 4602 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4603 break; 4604 } 4605 4606 return 0; 4607 } 4608 4609 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 4610 unsigned long event, void *ptr) 4611 { 4612 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 4613 struct netdev_notifier_changeupper_info *info = ptr; 4614 struct netlink_ext_ack *extack; 4615 4616 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 4617 return 0; 4618 4619 extack = netdev_notifier_info_to_extack(&info->info); 4620 4621 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */ 4622 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4623 4624 return -EOPNOTSUPP; 4625 } 4626 4627 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 4628 { 4629 struct netdev_notifier_changeupper_info *info = ptr; 4630 4631 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 4632 return false; 4633 return netif_is_l3_master(info->upper_dev); 4634 } 4635 4636 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 4637 struct net_device *dev, 4638 unsigned long event, void *ptr) 4639 { 4640 struct netdev_notifier_changeupper_info *cu_info; 4641 struct netdev_notifier_info *info = ptr; 4642 struct netlink_ext_ack *extack; 4643 struct net_device *upper_dev; 4644 4645 extack = netdev_notifier_info_to_extack(info); 4646 4647 switch (event) { 4648 case NETDEV_CHANGEUPPER: 4649 cu_info = container_of(info, 4650 struct netdev_notifier_changeupper_info, 4651 info); 4652 upper_dev = cu_info->upper_dev; 4653 if (!netif_is_bridge_master(upper_dev)) 4654 return 0; 4655 if (!mlxsw_sp_lower_get(upper_dev)) 4656 return 0; 4657 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4658 return -EOPNOTSUPP; 4659 if (cu_info->linking) { 4660 if (!netif_running(dev)) 4661 return 0; 4662 /* When the bridge is VLAN-aware, the VNI of the VxLAN 4663 * device needs to be mapped to a VLAN, but at this 4664 * point no VLANs are configured on the VxLAN device 4665 */ 4666 if (br_vlan_enabled(upper_dev)) 4667 return 0; 4668 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 4669 dev, 0, extack); 4670 } else { 4671 /* VLANs were already flushed, which triggered the 4672 * necessary cleanup 4673 */ 4674 if (br_vlan_enabled(upper_dev)) 4675 return 0; 4676 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 4677 } 4678 break; 4679 case NETDEV_PRE_UP: 4680 upper_dev = netdev_master_upper_dev_get(dev); 4681 if (!upper_dev) 4682 return 0; 4683 if (!netif_is_bridge_master(upper_dev)) 4684 return 0; 4685 if (!mlxsw_sp_lower_get(upper_dev)) 4686 return 0; 4687 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0, 4688 extack); 4689 case NETDEV_DOWN: 4690 upper_dev = netdev_master_upper_dev_get(dev); 4691 if (!upper_dev) 4692 return 0; 4693 if (!netif_is_bridge_master(upper_dev)) 4694 return 0; 4695 if (!mlxsw_sp_lower_get(upper_dev)) 4696 return 0; 4697 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 4698 break; 4699 } 4700 4701 return 0; 4702 } 4703 4704 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 4705 unsigned long event, void *ptr) 4706 { 4707 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4708 struct mlxsw_sp_span_entry *span_entry; 4709 struct mlxsw_sp *mlxsw_sp; 4710 int err = 0; 4711 4712 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 4713 if (event == NETDEV_UNREGISTER) { 4714 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 4715 if (span_entry) 4716 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 4717 } 4718 mlxsw_sp_span_respin(mlxsw_sp); 4719 4720 if (netif_is_vxlan(dev)) 4721 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 4722 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 4723 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 4724 event, ptr); 4725 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 4726 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 4727 event, ptr); 4728 else if (event == NETDEV_PRE_CHANGEADDR || 4729 event == NETDEV_CHANGEADDR || 4730 event == NETDEV_CHANGEMTU) 4731 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr); 4732 else if (mlxsw_sp_is_vrf_event(event, ptr)) 4733 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 4734 else if (mlxsw_sp_port_dev_check(dev)) 4735 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 4736 else if (netif_is_lag_master(dev)) 4737 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 4738 else if (is_vlan_dev(dev)) 4739 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 4740 else if (netif_is_bridge_master(dev)) 4741 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 4742 else if (netif_is_macvlan(dev)) 4743 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 4744 4745 return notifier_from_errno(err); 4746 } 4747 4748 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 4749 .notifier_call = mlxsw_sp_inetaddr_valid_event, 4750 }; 4751 4752 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 4753 .notifier_call = mlxsw_sp_inet6addr_valid_event, 4754 }; 4755 4756 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 4757 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 4758 {0, }, 4759 }; 4760 4761 static struct pci_driver mlxsw_sp1_pci_driver = { 4762 .name = mlxsw_sp1_driver_name, 4763 .id_table = mlxsw_sp1_pci_id_table, 4764 }; 4765 4766 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 4767 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 4768 {0, }, 4769 }; 4770 4771 static struct pci_driver mlxsw_sp2_pci_driver = { 4772 .name = mlxsw_sp2_driver_name, 4773 .id_table = mlxsw_sp2_pci_id_table, 4774 }; 4775 4776 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = { 4777 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0}, 4778 {0, }, 4779 }; 4780 4781 static struct pci_driver mlxsw_sp3_pci_driver = { 4782 .name = mlxsw_sp3_driver_name, 4783 .id_table = mlxsw_sp3_pci_id_table, 4784 }; 4785 4786 static int __init mlxsw_sp_module_init(void) 4787 { 4788 int err; 4789 4790 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4791 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4792 4793 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 4794 if (err) 4795 goto err_sp1_core_driver_register; 4796 4797 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 4798 if (err) 4799 goto err_sp2_core_driver_register; 4800 4801 err = mlxsw_core_driver_register(&mlxsw_sp3_driver); 4802 if (err) 4803 goto err_sp3_core_driver_register; 4804 4805 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 4806 if (err) 4807 goto err_sp1_pci_driver_register; 4808 4809 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 4810 if (err) 4811 goto err_sp2_pci_driver_register; 4812 4813 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver); 4814 if (err) 4815 goto err_sp3_pci_driver_register; 4816 4817 return 0; 4818 4819 err_sp3_pci_driver_register: 4820 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 4821 err_sp2_pci_driver_register: 4822 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 4823 err_sp1_pci_driver_register: 4824 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 4825 err_sp3_core_driver_register: 4826 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 4827 err_sp2_core_driver_register: 4828 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 4829 err_sp1_core_driver_register: 4830 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4831 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4832 return err; 4833 } 4834 4835 static void __exit mlxsw_sp_module_exit(void) 4836 { 4837 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 4838 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 4839 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 4840 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 4841 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 4842 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 4843 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4844 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4845 } 4846 4847 module_init(mlxsw_sp_module_init); 4848 module_exit(mlxsw_sp_module_exit); 4849 4850 MODULE_LICENSE("Dual BSD/GPL"); 4851 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 4852 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 4853 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 4854 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 4855 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table); 4856 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 4857 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME); 4858 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME); 4859