1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/random.h> 25 #include <net/switchdev.h> 26 #include <net/pkt_cls.h> 27 #include <net/tc_act/tc_mirred.h> 28 #include <net/netevent.h> 29 #include <net/tc_act/tc_sample.h> 30 #include <net/addrconf.h> 31 32 #include "spectrum.h" 33 #include "pci.h" 34 #include "core.h" 35 #include "reg.h" 36 #include "port.h" 37 #include "trap.h" 38 #include "txheader.h" 39 #include "spectrum_cnt.h" 40 #include "spectrum_dpipe.h" 41 #include "spectrum_acl_flex_actions.h" 42 #include "spectrum_span.h" 43 #include "../mlxfw/mlxfw.h" 44 45 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100) 46 47 #define MLXSW_SP1_FWREV_MAJOR 13 48 #define MLXSW_SP1_FWREV_MINOR 1703 49 #define MLXSW_SP1_FWREV_SUBMINOR 4 50 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 51 52 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 53 .major = MLXSW_SP1_FWREV_MAJOR, 54 .minor = MLXSW_SP1_FWREV_MINOR, 55 .subminor = MLXSW_SP1_FWREV_SUBMINOR, 56 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 57 }; 58 59 #define MLXSW_SP1_FW_FILENAME \ 60 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 61 "." __stringify(MLXSW_SP1_FWREV_MINOR) \ 62 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2" 63 64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 66 static const char mlxsw_sp_driver_version[] = "1.0"; 67 68 /* tx_hdr_version 69 * Tx header version. 70 * Must be set to 1. 71 */ 72 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 73 74 /* tx_hdr_ctl 75 * Packet control type. 76 * 0 - Ethernet control (e.g. EMADs, LACP) 77 * 1 - Ethernet data 78 */ 79 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 80 81 /* tx_hdr_proto 82 * Packet protocol type. Must be set to 1 (Ethernet). 83 */ 84 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 85 86 /* tx_hdr_rx_is_router 87 * Packet is sent from the router. Valid for data packets only. 88 */ 89 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 90 91 /* tx_hdr_fid_valid 92 * Indicates if the 'fid' field is valid and should be used for 93 * forwarding lookup. Valid for data packets only. 94 */ 95 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 96 97 /* tx_hdr_swid 98 * Switch partition ID. Must be set to 0. 99 */ 100 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 101 102 /* tx_hdr_control_tclass 103 * Indicates if the packet should use the control TClass and not one 104 * of the data TClasses. 105 */ 106 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 107 108 /* tx_hdr_etclass 109 * Egress TClass to be used on the egress device on the egress port. 110 */ 111 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 112 113 /* tx_hdr_port_mid 114 * Destination local port for unicast packets. 115 * Destination multicast ID for multicast packets. 116 * 117 * Control packets are directed to a specific egress port, while data 118 * packets are transmitted through the CPU port (0) into the switch partition, 119 * where forwarding rules are applied. 120 */ 121 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 122 123 /* tx_hdr_fid 124 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 125 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 126 * Valid for data packets only. 127 */ 128 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 129 130 /* tx_hdr_type 131 * 0 - Data packets 132 * 6 - Control packets 133 */ 134 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 135 136 struct mlxsw_sp_mlxfw_dev { 137 struct mlxfw_dev mlxfw_dev; 138 struct mlxsw_sp *mlxsw_sp; 139 }; 140 141 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev, 142 u16 component_index, u32 *p_max_size, 143 u8 *p_align_bits, u16 *p_max_write_size) 144 { 145 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 146 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 148 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 149 int err; 150 151 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 152 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl); 153 if (err) 154 return err; 155 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, 156 p_max_write_size); 157 158 *p_align_bits = max_t(u8, *p_align_bits, 2); 159 *p_max_write_size = min_t(u16, *p_max_write_size, 160 MLXSW_REG_MCDA_MAX_DATA_LEN); 161 return 0; 162 } 163 164 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 165 { 166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 169 char mcc_pl[MLXSW_REG_MCC_LEN]; 170 u8 control_state; 171 int err; 172 173 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 175 if (err) 176 return err; 177 178 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 179 if (control_state != MLXFW_FSM_STATE_IDLE) 180 return -EBUSY; 181 182 mlxsw_reg_mcc_pack(mcc_pl, 183 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 184 0, *fwhandle, 0); 185 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 186 } 187 188 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev, 189 u32 fwhandle, u16 component_index, 190 u32 component_size) 191 { 192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 195 char mcc_pl[MLXSW_REG_MCC_LEN]; 196 197 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 198 component_index, fwhandle, component_size); 199 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 200 } 201 202 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev, 203 u32 fwhandle, u8 *data, u16 size, 204 u32 offset) 205 { 206 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 207 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 209 char mcda_pl[MLXSW_REG_MCDA_LEN]; 210 211 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 212 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl); 213 } 214 215 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, 216 u32 fwhandle, u16 component_index) 217 { 218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 221 char mcc_pl[MLXSW_REG_MCC_LEN]; 222 223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 224 component_index, fwhandle, 0); 225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 226 } 227 228 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 229 { 230 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 231 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 233 char mcc_pl[MLXSW_REG_MCC_LEN]; 234 235 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, 236 fwhandle, 0); 237 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 238 } 239 240 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 241 enum mlxfw_fsm_state *fsm_state, 242 enum mlxfw_fsm_state_err *fsm_state_err) 243 { 244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 247 char mcc_pl[MLXSW_REG_MCC_LEN]; 248 u8 control_state; 249 u8 error_code; 250 int err; 251 252 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 253 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 254 if (err) 255 return err; 256 257 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 258 *fsm_state = control_state; 259 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 260 MLXFW_FSM_STATE_ERR_MAX); 261 return 0; 262 } 263 264 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 265 { 266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 269 char mcc_pl[MLXSW_REG_MCC_LEN]; 270 271 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, 272 fwhandle, 0); 273 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 274 } 275 276 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 277 { 278 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 279 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 280 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 281 char mcc_pl[MLXSW_REG_MCC_LEN]; 282 283 mlxsw_reg_mcc_pack(mcc_pl, 284 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 285 fwhandle, 0); 286 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 287 } 288 289 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = { 290 .component_query = mlxsw_sp_component_query, 291 .fsm_lock = mlxsw_sp_fsm_lock, 292 .fsm_component_update = mlxsw_sp_fsm_component_update, 293 .fsm_block_download = mlxsw_sp_fsm_block_download, 294 .fsm_component_verify = mlxsw_sp_fsm_component_verify, 295 .fsm_activate = mlxsw_sp_fsm_activate, 296 .fsm_query_state = mlxsw_sp_fsm_query_state, 297 .fsm_cancel = mlxsw_sp_fsm_cancel, 298 .fsm_release = mlxsw_sp_fsm_release 299 }; 300 301 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp, 302 const struct firmware *firmware) 303 { 304 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = { 305 .mlxfw_dev = { 306 .ops = &mlxsw_sp_mlxfw_dev_ops, 307 .psid = mlxsw_sp->bus_info->psid, 308 .psid_size = strlen(mlxsw_sp->bus_info->psid), 309 }, 310 .mlxsw_sp = mlxsw_sp 311 }; 312 313 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware); 314 } 315 316 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp) 317 { 318 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev; 319 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev; 320 const char *fw_filename = mlxsw_sp->fw_filename; 321 const struct firmware *firmware; 322 int err; 323 324 /* Don't check if driver does not require it */ 325 if (!req_rev || !fw_filename) 326 return 0; 327 328 /* Validate driver & FW are compatible */ 329 if (rev->major != req_rev->major) { 330 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 331 rev->major, req_rev->major); 332 return -EINVAL; 333 } 334 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) == 335 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) && 336 (rev->minor > req_rev->minor || 337 (rev->minor == req_rev->minor && 338 rev->subminor >= req_rev->subminor))) 339 return 0; 340 341 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n", 342 rev->major, rev->minor, rev->subminor); 343 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n", 344 fw_filename); 345 346 err = request_firmware_direct(&firmware, fw_filename, 347 mlxsw_sp->bus_info->dev); 348 if (err) { 349 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n", 350 fw_filename); 351 return err; 352 } 353 354 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 355 release_firmware(firmware); 356 if (err) 357 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n"); 358 359 /* On FW flash success, tell the caller FW reset is needed 360 * if current FW supports it. 361 */ 362 if (rev->minor >= req_rev->can_reset_minor) 363 return err ? err : -EAGAIN; 364 else 365 return 0; 366 } 367 368 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 369 unsigned int counter_index, u64 *packets, 370 u64 *bytes) 371 { 372 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 373 int err; 374 375 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 376 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 377 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 378 if (err) 379 return err; 380 if (packets) 381 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 382 if (bytes) 383 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 384 return 0; 385 } 386 387 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 388 unsigned int counter_index) 389 { 390 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 391 392 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 393 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 394 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 395 } 396 397 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 398 unsigned int *p_counter_index) 399 { 400 int err; 401 402 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 403 p_counter_index); 404 if (err) 405 return err; 406 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 407 if (err) 408 goto err_counter_clear; 409 return 0; 410 411 err_counter_clear: 412 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 413 *p_counter_index); 414 return err; 415 } 416 417 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 418 unsigned int counter_index) 419 { 420 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 421 counter_index); 422 } 423 424 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 425 const struct mlxsw_tx_info *tx_info) 426 { 427 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 428 429 memset(txhdr, 0, MLXSW_TXHDR_LEN); 430 431 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 432 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 433 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 434 mlxsw_tx_hdr_swid_set(txhdr, 0); 435 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 436 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 437 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 438 } 439 440 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 441 { 442 switch (state) { 443 case BR_STATE_FORWARDING: 444 return MLXSW_REG_SPMS_STATE_FORWARDING; 445 case BR_STATE_LEARNING: 446 return MLXSW_REG_SPMS_STATE_LEARNING; 447 case BR_STATE_LISTENING: /* fall-through */ 448 case BR_STATE_DISABLED: /* fall-through */ 449 case BR_STATE_BLOCKING: 450 return MLXSW_REG_SPMS_STATE_DISCARDING; 451 default: 452 BUG(); 453 } 454 } 455 456 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 457 u8 state) 458 { 459 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 460 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 461 char *spms_pl; 462 int err; 463 464 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 465 if (!spms_pl) 466 return -ENOMEM; 467 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 468 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 469 470 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 471 kfree(spms_pl); 472 return err; 473 } 474 475 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 476 { 477 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 478 int err; 479 480 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 481 if (err) 482 return err; 483 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 484 return 0; 485 } 486 487 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port, 488 bool enable, u32 rate) 489 { 490 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 491 char mpsc_pl[MLXSW_REG_MPSC_LEN]; 492 493 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate); 494 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl); 495 } 496 497 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 498 bool is_up) 499 { 500 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 501 char paos_pl[MLXSW_REG_PAOS_LEN]; 502 503 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 504 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 505 MLXSW_PORT_ADMIN_STATUS_DOWN); 506 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 507 } 508 509 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 510 unsigned char *addr) 511 { 512 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 513 char ppad_pl[MLXSW_REG_PPAD_LEN]; 514 515 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 516 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 517 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 518 } 519 520 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 521 { 522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 523 unsigned char *addr = mlxsw_sp_port->dev->dev_addr; 524 525 ether_addr_copy(addr, mlxsw_sp->base_mac); 526 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port; 527 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr); 528 } 529 530 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 531 { 532 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 533 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 534 int max_mtu; 535 int err; 536 537 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 538 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 539 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 540 if (err) 541 return err; 542 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 543 544 if (mtu > max_mtu) 545 return -EINVAL; 546 547 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 548 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 549 } 550 551 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid) 552 { 553 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 554 char pspa_pl[MLXSW_REG_PSPA_LEN]; 555 556 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port); 557 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 558 } 559 560 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 561 { 562 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 563 char svpe_pl[MLXSW_REG_SVPE_LEN]; 564 565 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 566 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 567 } 568 569 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 570 bool learn_enable) 571 { 572 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 573 char *spvmlr_pl; 574 int err; 575 576 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 577 if (!spvmlr_pl) 578 return -ENOMEM; 579 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 580 learn_enable); 581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 582 kfree(spvmlr_pl); 583 return err; 584 } 585 586 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 587 u16 vid) 588 { 589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 590 char spvid_pl[MLXSW_REG_SPVID_LEN]; 591 592 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); 593 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 594 } 595 596 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 597 bool allow) 598 { 599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 600 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 601 602 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 603 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 604 } 605 606 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 607 { 608 int err; 609 610 if (!vid) { 611 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 612 if (err) 613 return err; 614 } else { 615 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid); 616 if (err) 617 return err; 618 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 619 if (err) 620 goto err_port_allow_untagged_set; 621 } 622 623 mlxsw_sp_port->pvid = vid; 624 return 0; 625 626 err_port_allow_untagged_set: 627 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid); 628 return err; 629 } 630 631 static int 632 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 633 { 634 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 635 char sspr_pl[MLXSW_REG_SSPR_LEN]; 636 637 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 638 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 639 } 640 641 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, 642 u8 local_port, u8 *p_module, 643 u8 *p_width, u8 *p_lane) 644 { 645 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 646 int err; 647 648 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 649 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 650 if (err) 651 return err; 652 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 653 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); 654 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 655 return 0; 656 } 657 658 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port, 659 u8 module, u8 width, u8 lane) 660 { 661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 662 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 663 int i; 664 665 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 666 mlxsw_reg_pmlp_width_set(pmlp_pl, width); 667 for (i = 0; i < width; i++) { 668 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); 669 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ 670 } 671 672 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 673 } 674 675 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port) 676 { 677 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 678 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 679 680 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 681 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 682 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 683 } 684 685 static int mlxsw_sp_port_open(struct net_device *dev) 686 { 687 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 688 int err; 689 690 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 691 if (err) 692 return err; 693 netif_start_queue(dev); 694 return 0; 695 } 696 697 static int mlxsw_sp_port_stop(struct net_device *dev) 698 { 699 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 700 701 netif_stop_queue(dev); 702 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 703 } 704 705 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 706 struct net_device *dev) 707 { 708 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 709 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 710 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 711 const struct mlxsw_tx_info tx_info = { 712 .local_port = mlxsw_sp_port->local_port, 713 .is_emad = false, 714 }; 715 u64 len; 716 int err; 717 718 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 719 return NETDEV_TX_BUSY; 720 721 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) { 722 struct sk_buff *skb_orig = skb; 723 724 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN); 725 if (!skb) { 726 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 727 dev_kfree_skb_any(skb_orig); 728 return NETDEV_TX_OK; 729 } 730 dev_consume_skb_any(skb_orig); 731 } 732 733 if (eth_skb_pad(skb)) { 734 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 735 return NETDEV_TX_OK; 736 } 737 738 mlxsw_sp_txhdr_construct(skb, &tx_info); 739 /* TX header is consumed by HW on the way so we shouldn't count its 740 * bytes as being sent. 741 */ 742 len = skb->len - MLXSW_TXHDR_LEN; 743 744 /* Due to a race we might fail here because of a full queue. In that 745 * unlikely case we simply drop the packet. 746 */ 747 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 748 749 if (!err) { 750 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 751 u64_stats_update_begin(&pcpu_stats->syncp); 752 pcpu_stats->tx_packets++; 753 pcpu_stats->tx_bytes += len; 754 u64_stats_update_end(&pcpu_stats->syncp); 755 } else { 756 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 757 dev_kfree_skb_any(skb); 758 } 759 return NETDEV_TX_OK; 760 } 761 762 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 763 { 764 } 765 766 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 767 { 768 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 769 struct sockaddr *addr = p; 770 int err; 771 772 if (!is_valid_ether_addr(addr->sa_data)) 773 return -EADDRNOTAVAIL; 774 775 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 776 if (err) 777 return err; 778 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 779 return 0; 780 } 781 782 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp, 783 int mtu) 784 { 785 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu); 786 } 787 788 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ 789 790 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 791 u16 delay) 792 { 793 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay, 794 BITS_PER_BYTE)); 795 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp, 796 mtu); 797 } 798 799 /* Maximum delay buffer needed in case of PAUSE frames, in bytes. 800 * Assumes 100m cable and maximum MTU. 801 */ 802 #define MLXSW_SP_PAUSE_DELAY 58752 803 804 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 805 u16 delay, bool pfc, bool pause) 806 { 807 if (pfc) 808 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay); 809 else if (pause) 810 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY); 811 else 812 return 0; 813 } 814 815 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres, 816 bool lossy) 817 { 818 if (lossy) 819 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size); 820 else 821 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size, 822 thres); 823 } 824 825 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, 826 u8 *prio_tc, bool pause_en, 827 struct ieee_pfc *my_pfc) 828 { 829 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 830 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0; 831 u16 delay = !!my_pfc ? my_pfc->delay : 0; 832 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 833 int i, j, err; 834 835 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0); 836 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 837 if (err) 838 return err; 839 840 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 841 bool configure = false; 842 bool pfc = false; 843 bool lossy; 844 u16 thres; 845 846 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) { 847 if (prio_tc[j] == i) { 848 pfc = pfc_en & BIT(j); 849 configure = true; 850 break; 851 } 852 } 853 854 if (!configure) 855 continue; 856 857 lossy = !(pfc || pause_en); 858 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu); 859 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc, 860 pause_en); 861 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy); 862 } 863 864 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 865 } 866 867 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, 868 int mtu, bool pause_en) 869 { 870 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0}; 871 bool dcb_en = !!mlxsw_sp_port->dcb.ets; 872 struct ieee_pfc *my_pfc; 873 u8 *prio_tc; 874 875 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc; 876 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL; 877 878 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc, 879 pause_en, my_pfc); 880 } 881 882 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 883 { 884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 885 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 886 int err; 887 888 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en); 889 if (err) 890 return err; 891 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu); 892 if (err) 893 goto err_span_port_mtu_update; 894 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 895 if (err) 896 goto err_port_mtu_set; 897 dev->mtu = mtu; 898 return 0; 899 900 err_port_mtu_set: 901 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu); 902 err_span_port_mtu_update: 903 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 904 return err; 905 } 906 907 static int 908 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 909 struct rtnl_link_stats64 *stats) 910 { 911 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 912 struct mlxsw_sp_port_pcpu_stats *p; 913 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 914 u32 tx_dropped = 0; 915 unsigned int start; 916 int i; 917 918 for_each_possible_cpu(i) { 919 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 920 do { 921 start = u64_stats_fetch_begin_irq(&p->syncp); 922 rx_packets = p->rx_packets; 923 rx_bytes = p->rx_bytes; 924 tx_packets = p->tx_packets; 925 tx_bytes = p->tx_bytes; 926 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 927 928 stats->rx_packets += rx_packets; 929 stats->rx_bytes += rx_bytes; 930 stats->tx_packets += tx_packets; 931 stats->tx_bytes += tx_bytes; 932 /* tx_dropped is u32, updated without syncp protection. */ 933 tx_dropped += p->tx_dropped; 934 } 935 stats->tx_dropped = tx_dropped; 936 return 0; 937 } 938 939 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 940 { 941 switch (attr_id) { 942 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 943 return true; 944 } 945 946 return false; 947 } 948 949 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 950 void *sp) 951 { 952 switch (attr_id) { 953 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 954 return mlxsw_sp_port_get_sw_stats64(dev, sp); 955 } 956 957 return -EINVAL; 958 } 959 960 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 961 int prio, char *ppcnt_pl) 962 { 963 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 964 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 965 966 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 967 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 968 } 969 970 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 971 struct rtnl_link_stats64 *stats) 972 { 973 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 974 int err; 975 976 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 977 0, ppcnt_pl); 978 if (err) 979 goto out; 980 981 stats->tx_packets = 982 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 983 stats->rx_packets = 984 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 985 stats->tx_bytes = 986 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 987 stats->rx_bytes = 988 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 989 stats->multicast = 990 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 991 992 stats->rx_crc_errors = 993 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 994 stats->rx_frame_errors = 995 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 996 997 stats->rx_length_errors = ( 998 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 999 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 1000 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 1001 1002 stats->rx_errors = (stats->rx_crc_errors + 1003 stats->rx_frame_errors + stats->rx_length_errors); 1004 1005 out: 1006 return err; 1007 } 1008 1009 static void 1010 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 1011 struct mlxsw_sp_port_xstats *xstats) 1012 { 1013 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1014 int err, i; 1015 1016 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 1017 ppcnt_pl); 1018 if (!err) 1019 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 1020 1021 for (i = 0; i < TC_MAX_QUEUE; i++) { 1022 err = mlxsw_sp_port_get_stats_raw(dev, 1023 MLXSW_REG_PPCNT_TC_CONG_TC, 1024 i, ppcnt_pl); 1025 if (!err) 1026 xstats->wred_drop[i] = 1027 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 1028 1029 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 1030 i, ppcnt_pl); 1031 if (err) 1032 continue; 1033 1034 xstats->backlog[i] = 1035 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 1036 xstats->tail_drop[i] = 1037 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 1038 } 1039 1040 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1041 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 1042 i, ppcnt_pl); 1043 if (err) 1044 continue; 1045 1046 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 1047 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 1048 } 1049 } 1050 1051 static void update_stats_cache(struct work_struct *work) 1052 { 1053 struct mlxsw_sp_port *mlxsw_sp_port = 1054 container_of(work, struct mlxsw_sp_port, 1055 periodic_hw_stats.update_dw.work); 1056 1057 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 1058 goto out; 1059 1060 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 1061 &mlxsw_sp_port->periodic_hw_stats.stats); 1062 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 1063 &mlxsw_sp_port->periodic_hw_stats.xstats); 1064 1065 out: 1066 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1067 MLXSW_HW_STATS_UPDATE_TIME); 1068 } 1069 1070 /* Return the stats from a cache that is updated periodically, 1071 * as this function might get called in an atomic context. 1072 */ 1073 static void 1074 mlxsw_sp_port_get_stats64(struct net_device *dev, 1075 struct rtnl_link_stats64 *stats) 1076 { 1077 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1078 1079 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 1080 } 1081 1082 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 1083 u16 vid_begin, u16 vid_end, 1084 bool is_member, bool untagged) 1085 { 1086 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1087 char *spvm_pl; 1088 int err; 1089 1090 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1091 if (!spvm_pl) 1092 return -ENOMEM; 1093 1094 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1095 vid_end, is_member, untagged); 1096 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1097 kfree(spvm_pl); 1098 return err; 1099 } 1100 1101 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1102 u16 vid_end, bool is_member, bool untagged) 1103 { 1104 u16 vid, vid_e; 1105 int err; 1106 1107 for (vid = vid_begin; vid <= vid_end; 1108 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1109 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1110 vid_end); 1111 1112 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1113 is_member, untagged); 1114 if (err) 1115 return err; 1116 } 1117 1118 return 0; 1119 } 1120 1121 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port) 1122 { 1123 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1124 1125 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1126 &mlxsw_sp_port->vlans_list, list) 1127 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1128 } 1129 1130 static struct mlxsw_sp_port_vlan * 1131 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1132 { 1133 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1134 bool untagged = vid == 1; 1135 int err; 1136 1137 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1138 if (err) 1139 return ERR_PTR(err); 1140 1141 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1142 if (!mlxsw_sp_port_vlan) { 1143 err = -ENOMEM; 1144 goto err_port_vlan_alloc; 1145 } 1146 1147 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1148 mlxsw_sp_port_vlan->ref_count = 1; 1149 mlxsw_sp_port_vlan->vid = vid; 1150 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1151 1152 return mlxsw_sp_port_vlan; 1153 1154 err_port_vlan_alloc: 1155 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1156 return ERR_PTR(err); 1157 } 1158 1159 static void 1160 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1161 { 1162 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1163 u16 vid = mlxsw_sp_port_vlan->vid; 1164 1165 list_del(&mlxsw_sp_port_vlan->list); 1166 kfree(mlxsw_sp_port_vlan); 1167 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1168 } 1169 1170 struct mlxsw_sp_port_vlan * 1171 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1172 { 1173 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1174 1175 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1176 if (mlxsw_sp_port_vlan) { 1177 mlxsw_sp_port_vlan->ref_count++; 1178 return mlxsw_sp_port_vlan; 1179 } 1180 1181 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid); 1182 } 1183 1184 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1185 { 1186 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid; 1187 1188 if (--mlxsw_sp_port_vlan->ref_count != 0) 1189 return; 1190 1191 if (mlxsw_sp_port_vlan->bridge_port) 1192 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1193 else if (fid) 1194 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1195 1196 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1197 } 1198 1199 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1200 __be16 __always_unused proto, u16 vid) 1201 { 1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1203 1204 /* VLAN 0 is added to HW filter when device goes up, but it is 1205 * reserved in our case, so simply return. 1206 */ 1207 if (!vid) 1208 return 0; 1209 1210 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid)); 1211 } 1212 1213 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1214 __be16 __always_unused proto, u16 vid) 1215 { 1216 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1217 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1218 1219 /* VLAN 0 is removed from HW filter when device goes down, but 1220 * it is reserved in our case, so simply return. 1221 */ 1222 if (!vid) 1223 return 0; 1224 1225 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1226 if (!mlxsw_sp_port_vlan) 1227 return 0; 1228 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1229 1230 return 0; 1231 } 1232 1233 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name, 1234 size_t len) 1235 { 1236 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1237 1238 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core, 1239 mlxsw_sp_port->local_port, 1240 name, len); 1241 } 1242 1243 static struct mlxsw_sp_port_mall_tc_entry * 1244 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port, 1245 unsigned long cookie) { 1246 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1247 1248 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list) 1249 if (mall_tc_entry->cookie == cookie) 1250 return mall_tc_entry; 1251 1252 return NULL; 1253 } 1254 1255 static int 1256 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1257 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror, 1258 const struct tc_action *a, 1259 bool ingress) 1260 { 1261 enum mlxsw_sp_span_type span_type; 1262 struct net_device *to_dev; 1263 1264 to_dev = tcf_mirred_dev(a); 1265 if (!to_dev) { 1266 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n"); 1267 return -EINVAL; 1268 } 1269 1270 mirror->ingress = ingress; 1271 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1272 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type, 1273 true, &mirror->span_id); 1274 } 1275 1276 static void 1277 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1278 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror) 1279 { 1280 enum mlxsw_sp_span_type span_type; 1281 1282 span_type = mirror->ingress ? 1283 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1284 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id, 1285 span_type, true); 1286 } 1287 1288 static int 1289 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port, 1290 struct tc_cls_matchall_offload *cls, 1291 const struct tc_action *a, 1292 bool ingress) 1293 { 1294 int err; 1295 1296 if (!mlxsw_sp_port->sample) 1297 return -EOPNOTSUPP; 1298 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) { 1299 netdev_err(mlxsw_sp_port->dev, "sample already active\n"); 1300 return -EEXIST; 1301 } 1302 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) { 1303 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n"); 1304 return -EOPNOTSUPP; 1305 } 1306 1307 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group, 1308 tcf_sample_psample_group(a)); 1309 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a); 1310 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a); 1311 mlxsw_sp_port->sample->rate = tcf_sample_rate(a); 1312 1313 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a)); 1314 if (err) 1315 goto err_port_sample_set; 1316 return 0; 1317 1318 err_port_sample_set: 1319 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1320 return err; 1321 } 1322 1323 static void 1324 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port) 1325 { 1326 if (!mlxsw_sp_port->sample) 1327 return; 1328 1329 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1); 1330 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1331 } 1332 1333 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1334 struct tc_cls_matchall_offload *f, 1335 bool ingress) 1336 { 1337 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1338 __be16 protocol = f->common.protocol; 1339 const struct tc_action *a; 1340 LIST_HEAD(actions); 1341 int err; 1342 1343 if (!tcf_exts_has_one_action(f->exts)) { 1344 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n"); 1345 return -EOPNOTSUPP; 1346 } 1347 1348 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL); 1349 if (!mall_tc_entry) 1350 return -ENOMEM; 1351 mall_tc_entry->cookie = f->cookie; 1352 1353 a = tcf_exts_first_action(f->exts); 1354 1355 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) { 1356 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror; 1357 1358 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR; 1359 mirror = &mall_tc_entry->mirror; 1360 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, 1361 mirror, a, ingress); 1362 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) { 1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE; 1364 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f, 1365 a, ingress); 1366 } else { 1367 err = -EOPNOTSUPP; 1368 } 1369 1370 if (err) 1371 goto err_add_action; 1372 1373 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list); 1374 return 0; 1375 1376 err_add_action: 1377 kfree(mall_tc_entry); 1378 return err; 1379 } 1380 1381 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1382 struct tc_cls_matchall_offload *f) 1383 { 1384 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1385 1386 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port, 1387 f->cookie); 1388 if (!mall_tc_entry) { 1389 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n"); 1390 return; 1391 } 1392 list_del(&mall_tc_entry->list); 1393 1394 switch (mall_tc_entry->type) { 1395 case MLXSW_SP_PORT_MALL_MIRROR: 1396 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port, 1397 &mall_tc_entry->mirror); 1398 break; 1399 case MLXSW_SP_PORT_MALL_SAMPLE: 1400 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port); 1401 break; 1402 default: 1403 WARN_ON(1); 1404 } 1405 1406 kfree(mall_tc_entry); 1407 } 1408 1409 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1410 struct tc_cls_matchall_offload *f, 1411 bool ingress) 1412 { 1413 switch (f->command) { 1414 case TC_CLSMATCHALL_REPLACE: 1415 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f, 1416 ingress); 1417 case TC_CLSMATCHALL_DESTROY: 1418 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f); 1419 return 0; 1420 default: 1421 return -EOPNOTSUPP; 1422 } 1423 } 1424 1425 static int 1426 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block, 1427 struct tc_cls_flower_offload *f) 1428 { 1429 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block); 1430 1431 switch (f->command) { 1432 case TC_CLSFLOWER_REPLACE: 1433 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f); 1434 case TC_CLSFLOWER_DESTROY: 1435 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f); 1436 return 0; 1437 case TC_CLSFLOWER_STATS: 1438 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f); 1439 case TC_CLSFLOWER_TMPLT_CREATE: 1440 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f); 1441 case TC_CLSFLOWER_TMPLT_DESTROY: 1442 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f); 1443 return 0; 1444 default: 1445 return -EOPNOTSUPP; 1446 } 1447 } 1448 1449 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type, 1450 void *type_data, 1451 void *cb_priv, bool ingress) 1452 { 1453 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv; 1454 1455 switch (type) { 1456 case TC_SETUP_CLSMATCHALL: 1457 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev, 1458 type_data)) 1459 return -EOPNOTSUPP; 1460 1461 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data, 1462 ingress); 1463 case TC_SETUP_CLSFLOWER: 1464 return 0; 1465 default: 1466 return -EOPNOTSUPP; 1467 } 1468 } 1469 1470 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type, 1471 void *type_data, 1472 void *cb_priv) 1473 { 1474 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1475 cb_priv, true); 1476 } 1477 1478 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type, 1479 void *type_data, 1480 void *cb_priv) 1481 { 1482 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1483 cb_priv, false); 1484 } 1485 1486 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type, 1487 void *type_data, void *cb_priv) 1488 { 1489 struct mlxsw_sp_acl_block *acl_block = cb_priv; 1490 1491 switch (type) { 1492 case TC_SETUP_CLSMATCHALL: 1493 return 0; 1494 case TC_SETUP_CLSFLOWER: 1495 if (mlxsw_sp_acl_block_disabled(acl_block)) 1496 return -EOPNOTSUPP; 1497 1498 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data); 1499 default: 1500 return -EOPNOTSUPP; 1501 } 1502 } 1503 1504 static int 1505 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port, 1506 struct tcf_block *block, bool ingress, 1507 struct netlink_ext_ack *extack) 1508 { 1509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1510 struct mlxsw_sp_acl_block *acl_block; 1511 struct tcf_block_cb *block_cb; 1512 int err; 1513 1514 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1515 mlxsw_sp); 1516 if (!block_cb) { 1517 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net); 1518 if (!acl_block) 1519 return -ENOMEM; 1520 block_cb = __tcf_block_cb_register(block, 1521 mlxsw_sp_setup_tc_block_cb_flower, 1522 mlxsw_sp, acl_block, extack); 1523 if (IS_ERR(block_cb)) { 1524 err = PTR_ERR(block_cb); 1525 goto err_cb_register; 1526 } 1527 } else { 1528 acl_block = tcf_block_cb_priv(block_cb); 1529 } 1530 tcf_block_cb_incref(block_cb); 1531 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block, 1532 mlxsw_sp_port, ingress); 1533 if (err) 1534 goto err_block_bind; 1535 1536 if (ingress) 1537 mlxsw_sp_port->ing_acl_block = acl_block; 1538 else 1539 mlxsw_sp_port->eg_acl_block = acl_block; 1540 1541 return 0; 1542 1543 err_block_bind: 1544 if (!tcf_block_cb_decref(block_cb)) { 1545 __tcf_block_cb_unregister(block, block_cb); 1546 err_cb_register: 1547 mlxsw_sp_acl_block_destroy(acl_block); 1548 } 1549 return err; 1550 } 1551 1552 static void 1553 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port, 1554 struct tcf_block *block, bool ingress) 1555 { 1556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1557 struct mlxsw_sp_acl_block *acl_block; 1558 struct tcf_block_cb *block_cb; 1559 int err; 1560 1561 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1562 mlxsw_sp); 1563 if (!block_cb) 1564 return; 1565 1566 if (ingress) 1567 mlxsw_sp_port->ing_acl_block = NULL; 1568 else 1569 mlxsw_sp_port->eg_acl_block = NULL; 1570 1571 acl_block = tcf_block_cb_priv(block_cb); 1572 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block, 1573 mlxsw_sp_port, ingress); 1574 if (!err && !tcf_block_cb_decref(block_cb)) { 1575 __tcf_block_cb_unregister(block, block_cb); 1576 mlxsw_sp_acl_block_destroy(acl_block); 1577 } 1578 } 1579 1580 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1581 struct tc_block_offload *f) 1582 { 1583 tc_setup_cb_t *cb; 1584 bool ingress; 1585 int err; 1586 1587 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) { 1588 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig; 1589 ingress = true; 1590 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 1591 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg; 1592 ingress = false; 1593 } else { 1594 return -EOPNOTSUPP; 1595 } 1596 1597 switch (f->command) { 1598 case TC_BLOCK_BIND: 1599 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port, 1600 mlxsw_sp_port, f->extack); 1601 if (err) 1602 return err; 1603 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, 1604 f->block, ingress, 1605 f->extack); 1606 if (err) { 1607 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1608 return err; 1609 } 1610 return 0; 1611 case TC_BLOCK_UNBIND: 1612 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port, 1613 f->block, ingress); 1614 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1615 return 0; 1616 default: 1617 return -EOPNOTSUPP; 1618 } 1619 } 1620 1621 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1622 void *type_data) 1623 { 1624 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1625 1626 switch (type) { 1627 case TC_SETUP_BLOCK: 1628 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1629 case TC_SETUP_QDISC_RED: 1630 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1631 case TC_SETUP_QDISC_PRIO: 1632 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1633 default: 1634 return -EOPNOTSUPP; 1635 } 1636 } 1637 1638 1639 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1640 { 1641 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1642 1643 if (!enable) { 1644 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) || 1645 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) || 1646 !list_empty(&mlxsw_sp_port->mall_tc_list)) { 1647 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1648 return -EINVAL; 1649 } 1650 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block); 1651 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block); 1652 } else { 1653 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block); 1654 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block); 1655 } 1656 return 0; 1657 } 1658 1659 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1660 1661 static int mlxsw_sp_handle_feature(struct net_device *dev, 1662 netdev_features_t wanted_features, 1663 netdev_features_t feature, 1664 mlxsw_sp_feature_handler feature_handler) 1665 { 1666 netdev_features_t changes = wanted_features ^ dev->features; 1667 bool enable = !!(wanted_features & feature); 1668 int err; 1669 1670 if (!(changes & feature)) 1671 return 0; 1672 1673 err = feature_handler(dev, enable); 1674 if (err) { 1675 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1676 enable ? "Enable" : "Disable", &feature, err); 1677 return err; 1678 } 1679 1680 if (enable) 1681 dev->features |= feature; 1682 else 1683 dev->features &= ~feature; 1684 1685 return 0; 1686 } 1687 static int mlxsw_sp_set_features(struct net_device *dev, 1688 netdev_features_t features) 1689 { 1690 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1691 mlxsw_sp_feature_hw_tc); 1692 } 1693 1694 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1695 .ndo_open = mlxsw_sp_port_open, 1696 .ndo_stop = mlxsw_sp_port_stop, 1697 .ndo_start_xmit = mlxsw_sp_port_xmit, 1698 .ndo_setup_tc = mlxsw_sp_setup_tc, 1699 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1700 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1701 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1702 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1703 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1704 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1705 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1706 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1707 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name, 1708 .ndo_set_features = mlxsw_sp_set_features, 1709 }; 1710 1711 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev, 1712 struct ethtool_drvinfo *drvinfo) 1713 { 1714 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1716 1717 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind, 1718 sizeof(drvinfo->driver)); 1719 strlcpy(drvinfo->version, mlxsw_sp_driver_version, 1720 sizeof(drvinfo->version)); 1721 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 1722 "%d.%d.%d", 1723 mlxsw_sp->bus_info->fw_rev.major, 1724 mlxsw_sp->bus_info->fw_rev.minor, 1725 mlxsw_sp->bus_info->fw_rev.subminor); 1726 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name, 1727 sizeof(drvinfo->bus_info)); 1728 } 1729 1730 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev, 1731 struct ethtool_pauseparam *pause) 1732 { 1733 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1734 1735 pause->rx_pause = mlxsw_sp_port->link.rx_pause; 1736 pause->tx_pause = mlxsw_sp_port->link.tx_pause; 1737 } 1738 1739 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port, 1740 struct ethtool_pauseparam *pause) 1741 { 1742 char pfcc_pl[MLXSW_REG_PFCC_LEN]; 1743 1744 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port); 1745 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause); 1746 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause); 1747 1748 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc), 1749 pfcc_pl); 1750 } 1751 1752 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev, 1753 struct ethtool_pauseparam *pause) 1754 { 1755 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1756 bool pause_en = pause->tx_pause || pause->rx_pause; 1757 int err; 1758 1759 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) { 1760 netdev_err(dev, "PFC already enabled on port\n"); 1761 return -EINVAL; 1762 } 1763 1764 if (pause->autoneg) { 1765 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n"); 1766 return -EINVAL; 1767 } 1768 1769 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1770 if (err) { 1771 netdev_err(dev, "Failed to configure port's headroom\n"); 1772 return err; 1773 } 1774 1775 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause); 1776 if (err) { 1777 netdev_err(dev, "Failed to set PAUSE parameters\n"); 1778 goto err_port_pause_configure; 1779 } 1780 1781 mlxsw_sp_port->link.rx_pause = pause->rx_pause; 1782 mlxsw_sp_port->link.tx_pause = pause->tx_pause; 1783 1784 return 0; 1785 1786 err_port_pause_configure: 1787 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 1788 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1789 return err; 1790 } 1791 1792 struct mlxsw_sp_port_hw_stats { 1793 char str[ETH_GSTRING_LEN]; 1794 u64 (*getter)(const char *payload); 1795 bool cells_bytes; 1796 }; 1797 1798 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = { 1799 { 1800 .str = "a_frames_transmitted_ok", 1801 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get, 1802 }, 1803 { 1804 .str = "a_frames_received_ok", 1805 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get, 1806 }, 1807 { 1808 .str = "a_frame_check_sequence_errors", 1809 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get, 1810 }, 1811 { 1812 .str = "a_alignment_errors", 1813 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get, 1814 }, 1815 { 1816 .str = "a_octets_transmitted_ok", 1817 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get, 1818 }, 1819 { 1820 .str = "a_octets_received_ok", 1821 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get, 1822 }, 1823 { 1824 .str = "a_multicast_frames_xmitted_ok", 1825 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get, 1826 }, 1827 { 1828 .str = "a_broadcast_frames_xmitted_ok", 1829 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get, 1830 }, 1831 { 1832 .str = "a_multicast_frames_received_ok", 1833 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get, 1834 }, 1835 { 1836 .str = "a_broadcast_frames_received_ok", 1837 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get, 1838 }, 1839 { 1840 .str = "a_in_range_length_errors", 1841 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get, 1842 }, 1843 { 1844 .str = "a_out_of_range_length_field", 1845 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get, 1846 }, 1847 { 1848 .str = "a_frame_too_long_errors", 1849 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get, 1850 }, 1851 { 1852 .str = "a_symbol_error_during_carrier", 1853 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get, 1854 }, 1855 { 1856 .str = "a_mac_control_frames_transmitted", 1857 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get, 1858 }, 1859 { 1860 .str = "a_mac_control_frames_received", 1861 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get, 1862 }, 1863 { 1864 .str = "a_unsupported_opcodes_received", 1865 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get, 1866 }, 1867 { 1868 .str = "a_pause_mac_ctrl_frames_received", 1869 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get, 1870 }, 1871 { 1872 .str = "a_pause_mac_ctrl_frames_xmitted", 1873 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get, 1874 }, 1875 }; 1876 1877 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats) 1878 1879 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = { 1880 { 1881 .str = "if_in_discards", 1882 .getter = mlxsw_reg_ppcnt_if_in_discards_get, 1883 }, 1884 { 1885 .str = "if_out_discards", 1886 .getter = mlxsw_reg_ppcnt_if_out_discards_get, 1887 }, 1888 { 1889 .str = "if_out_errors", 1890 .getter = mlxsw_reg_ppcnt_if_out_errors_get, 1891 }, 1892 }; 1893 1894 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \ 1895 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats) 1896 1897 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = { 1898 { 1899 .str = "ether_stats_undersize_pkts", 1900 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get, 1901 }, 1902 { 1903 .str = "ether_stats_oversize_pkts", 1904 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get, 1905 }, 1906 { 1907 .str = "ether_stats_fragments", 1908 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get, 1909 }, 1910 { 1911 .str = "ether_pkts64octets", 1912 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get, 1913 }, 1914 { 1915 .str = "ether_pkts65to127octets", 1916 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get, 1917 }, 1918 { 1919 .str = "ether_pkts128to255octets", 1920 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get, 1921 }, 1922 { 1923 .str = "ether_pkts256to511octets", 1924 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get, 1925 }, 1926 { 1927 .str = "ether_pkts512to1023octets", 1928 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get, 1929 }, 1930 { 1931 .str = "ether_pkts1024to1518octets", 1932 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get, 1933 }, 1934 { 1935 .str = "ether_pkts1519to2047octets", 1936 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get, 1937 }, 1938 { 1939 .str = "ether_pkts2048to4095octets", 1940 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get, 1941 }, 1942 { 1943 .str = "ether_pkts4096to8191octets", 1944 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get, 1945 }, 1946 { 1947 .str = "ether_pkts8192to10239octets", 1948 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get, 1949 }, 1950 }; 1951 1952 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \ 1953 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats) 1954 1955 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = { 1956 { 1957 .str = "dot3stats_fcs_errors", 1958 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get, 1959 }, 1960 { 1961 .str = "dot3stats_symbol_errors", 1962 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get, 1963 }, 1964 { 1965 .str = "dot3control_in_unknown_opcodes", 1966 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get, 1967 }, 1968 { 1969 .str = "dot3in_pause_frames", 1970 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get, 1971 }, 1972 }; 1973 1974 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \ 1975 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats) 1976 1977 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = { 1978 { 1979 .str = "discard_ingress_general", 1980 .getter = mlxsw_reg_ppcnt_ingress_general_get, 1981 }, 1982 { 1983 .str = "discard_ingress_policy_engine", 1984 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get, 1985 }, 1986 { 1987 .str = "discard_ingress_vlan_membership", 1988 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get, 1989 }, 1990 { 1991 .str = "discard_ingress_tag_frame_type", 1992 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get, 1993 }, 1994 { 1995 .str = "discard_egress_vlan_membership", 1996 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get, 1997 }, 1998 { 1999 .str = "discard_loopback_filter", 2000 .getter = mlxsw_reg_ppcnt_loopback_filter_get, 2001 }, 2002 { 2003 .str = "discard_egress_general", 2004 .getter = mlxsw_reg_ppcnt_egress_general_get, 2005 }, 2006 { 2007 .str = "discard_egress_hoq", 2008 .getter = mlxsw_reg_ppcnt_egress_hoq_get, 2009 }, 2010 { 2011 .str = "discard_egress_policy_engine", 2012 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get, 2013 }, 2014 { 2015 .str = "discard_ingress_tx_link_down", 2016 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get, 2017 }, 2018 { 2019 .str = "discard_egress_stp_filter", 2020 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get, 2021 }, 2022 { 2023 .str = "discard_egress_sll", 2024 .getter = mlxsw_reg_ppcnt_egress_sll_get, 2025 }, 2026 }; 2027 2028 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \ 2029 ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats) 2030 2031 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = { 2032 { 2033 .str = "rx_octets_prio", 2034 .getter = mlxsw_reg_ppcnt_rx_octets_get, 2035 }, 2036 { 2037 .str = "rx_frames_prio", 2038 .getter = mlxsw_reg_ppcnt_rx_frames_get, 2039 }, 2040 { 2041 .str = "tx_octets_prio", 2042 .getter = mlxsw_reg_ppcnt_tx_octets_get, 2043 }, 2044 { 2045 .str = "tx_frames_prio", 2046 .getter = mlxsw_reg_ppcnt_tx_frames_get, 2047 }, 2048 { 2049 .str = "rx_pause_prio", 2050 .getter = mlxsw_reg_ppcnt_rx_pause_get, 2051 }, 2052 { 2053 .str = "rx_pause_duration_prio", 2054 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get, 2055 }, 2056 { 2057 .str = "tx_pause_prio", 2058 .getter = mlxsw_reg_ppcnt_tx_pause_get, 2059 }, 2060 { 2061 .str = "tx_pause_duration_prio", 2062 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get, 2063 }, 2064 }; 2065 2066 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats) 2067 2068 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = { 2069 { 2070 .str = "tc_transmit_queue_tc", 2071 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get, 2072 .cells_bytes = true, 2073 }, 2074 { 2075 .str = "tc_no_buffer_discard_uc_tc", 2076 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get, 2077 }, 2078 }; 2079 2080 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats) 2081 2082 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \ 2083 MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \ 2084 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \ 2085 MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \ 2086 MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \ 2087 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \ 2088 IEEE_8021QAZ_MAX_TCS) + \ 2089 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \ 2090 TC_MAX_QUEUE)) 2091 2092 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio) 2093 { 2094 int i; 2095 2096 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) { 2097 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 2098 mlxsw_sp_port_hw_prio_stats[i].str, prio); 2099 *p += ETH_GSTRING_LEN; 2100 } 2101 } 2102 2103 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc) 2104 { 2105 int i; 2106 2107 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) { 2108 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 2109 mlxsw_sp_port_hw_tc_stats[i].str, tc); 2110 *p += ETH_GSTRING_LEN; 2111 } 2112 } 2113 2114 static void mlxsw_sp_port_get_strings(struct net_device *dev, 2115 u32 stringset, u8 *data) 2116 { 2117 u8 *p = data; 2118 int i; 2119 2120 switch (stringset) { 2121 case ETH_SS_STATS: 2122 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) { 2123 memcpy(p, mlxsw_sp_port_hw_stats[i].str, 2124 ETH_GSTRING_LEN); 2125 p += ETH_GSTRING_LEN; 2126 } 2127 2128 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) { 2129 memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str, 2130 ETH_GSTRING_LEN); 2131 p += ETH_GSTRING_LEN; 2132 } 2133 2134 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) { 2135 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str, 2136 ETH_GSTRING_LEN); 2137 p += ETH_GSTRING_LEN; 2138 } 2139 2140 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) { 2141 memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str, 2142 ETH_GSTRING_LEN); 2143 p += ETH_GSTRING_LEN; 2144 } 2145 2146 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) { 2147 memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str, 2148 ETH_GSTRING_LEN); 2149 p += ETH_GSTRING_LEN; 2150 } 2151 2152 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 2153 mlxsw_sp_port_get_prio_strings(&p, i); 2154 2155 for (i = 0; i < TC_MAX_QUEUE; i++) 2156 mlxsw_sp_port_get_tc_strings(&p, i); 2157 2158 break; 2159 } 2160 } 2161 2162 static int mlxsw_sp_port_set_phys_id(struct net_device *dev, 2163 enum ethtool_phys_id_state state) 2164 { 2165 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2167 char mlcr_pl[MLXSW_REG_MLCR_LEN]; 2168 bool active; 2169 2170 switch (state) { 2171 case ETHTOOL_ID_ACTIVE: 2172 active = true; 2173 break; 2174 case ETHTOOL_ID_INACTIVE: 2175 active = false; 2176 break; 2177 default: 2178 return -EOPNOTSUPP; 2179 } 2180 2181 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active); 2182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl); 2183 } 2184 2185 static int 2186 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats, 2187 int *p_len, enum mlxsw_reg_ppcnt_grp grp) 2188 { 2189 switch (grp) { 2190 case MLXSW_REG_PPCNT_IEEE_8023_CNT: 2191 *p_hw_stats = mlxsw_sp_port_hw_stats; 2192 *p_len = MLXSW_SP_PORT_HW_STATS_LEN; 2193 break; 2194 case MLXSW_REG_PPCNT_RFC_2863_CNT: 2195 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats; 2196 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; 2197 break; 2198 case MLXSW_REG_PPCNT_RFC_2819_CNT: 2199 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats; 2200 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2201 break; 2202 case MLXSW_REG_PPCNT_RFC_3635_CNT: 2203 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats; 2204 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; 2205 break; 2206 case MLXSW_REG_PPCNT_DISCARD_CNT: 2207 *p_hw_stats = mlxsw_sp_port_hw_discard_stats; 2208 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; 2209 break; 2210 case MLXSW_REG_PPCNT_PRIO_CNT: 2211 *p_hw_stats = mlxsw_sp_port_hw_prio_stats; 2212 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2213 break; 2214 case MLXSW_REG_PPCNT_TC_CNT: 2215 *p_hw_stats = mlxsw_sp_port_hw_tc_stats; 2216 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN; 2217 break; 2218 default: 2219 WARN_ON(1); 2220 return -EOPNOTSUPP; 2221 } 2222 return 0; 2223 } 2224 2225 static void __mlxsw_sp_port_get_stats(struct net_device *dev, 2226 enum mlxsw_reg_ppcnt_grp grp, int prio, 2227 u64 *data, int data_index) 2228 { 2229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2231 struct mlxsw_sp_port_hw_stats *hw_stats; 2232 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 2233 int i, len; 2234 int err; 2235 2236 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp); 2237 if (err) 2238 return; 2239 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl); 2240 for (i = 0; i < len; i++) { 2241 data[data_index + i] = hw_stats[i].getter(ppcnt_pl); 2242 if (!hw_stats[i].cells_bytes) 2243 continue; 2244 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp, 2245 data[data_index + i]); 2246 } 2247 } 2248 2249 static void mlxsw_sp_port_get_stats(struct net_device *dev, 2250 struct ethtool_stats *stats, u64 *data) 2251 { 2252 int i, data_index = 0; 2253 2254 /* IEEE 802.3 Counters */ 2255 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0, 2256 data, data_index); 2257 data_index = MLXSW_SP_PORT_HW_STATS_LEN; 2258 2259 /* RFC 2863 Counters */ 2260 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0, 2261 data, data_index); 2262 data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; 2263 2264 /* RFC 2819 Counters */ 2265 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0, 2266 data, data_index); 2267 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2268 2269 /* RFC 3635 Counters */ 2270 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0, 2271 data, data_index); 2272 data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; 2273 2274 /* Discard Counters */ 2275 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0, 2276 data, data_index); 2277 data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; 2278 2279 /* Per-Priority Counters */ 2280 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2281 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i, 2282 data, data_index); 2283 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2284 } 2285 2286 /* Per-TC Counters */ 2287 for (i = 0; i < TC_MAX_QUEUE; i++) { 2288 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i, 2289 data, data_index); 2290 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN; 2291 } 2292 } 2293 2294 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset) 2295 { 2296 switch (sset) { 2297 case ETH_SS_STATS: 2298 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN; 2299 default: 2300 return -EOPNOTSUPP; 2301 } 2302 } 2303 2304 struct mlxsw_sp_port_link_mode { 2305 enum ethtool_link_mode_bit_indices mask_ethtool; 2306 u32 mask; 2307 u32 speed; 2308 }; 2309 2310 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = { 2311 { 2312 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, 2313 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2314 .speed = SPEED_100, 2315 }, 2316 { 2317 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | 2318 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX, 2319 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2320 .speed = SPEED_1000, 2321 }, 2322 { 2323 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, 2324 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2325 .speed = SPEED_10000, 2326 }, 2327 { 2328 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | 2329 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4, 2330 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2331 .speed = SPEED_10000, 2332 }, 2333 { 2334 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2335 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2336 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2337 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR, 2338 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2339 .speed = SPEED_10000, 2340 }, 2341 { 2342 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, 2343 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 2344 .speed = SPEED_20000, 2345 }, 2346 { 2347 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, 2348 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2349 .speed = SPEED_40000, 2350 }, 2351 { 2352 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, 2353 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2354 .speed = SPEED_40000, 2355 }, 2356 { 2357 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, 2358 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2359 .speed = SPEED_40000, 2360 }, 2361 { 2362 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, 2363 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2364 .speed = SPEED_40000, 2365 }, 2366 { 2367 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, 2368 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2369 .speed = SPEED_25000, 2370 }, 2371 { 2372 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, 2373 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2374 .speed = SPEED_25000, 2375 }, 2376 { 2377 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2378 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2379 .speed = SPEED_25000, 2380 }, 2381 { 2382 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2383 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2384 .speed = SPEED_25000, 2385 }, 2386 { 2387 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, 2388 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2389 .speed = SPEED_50000, 2390 }, 2391 { 2392 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, 2393 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2394 .speed = SPEED_50000, 2395 }, 2396 { 2397 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, 2398 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2399 .speed = SPEED_50000, 2400 }, 2401 { 2402 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2403 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, 2404 .speed = SPEED_56000, 2405 }, 2406 { 2407 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2408 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, 2409 .speed = SPEED_56000, 2410 }, 2411 { 2412 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2413 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, 2414 .speed = SPEED_56000, 2415 }, 2416 { 2417 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2418 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, 2419 .speed = SPEED_56000, 2420 }, 2421 { 2422 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, 2423 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2424 .speed = SPEED_100000, 2425 }, 2426 { 2427 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, 2428 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2429 .speed = SPEED_100000, 2430 }, 2431 { 2432 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, 2433 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2434 .speed = SPEED_100000, 2435 }, 2436 { 2437 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, 2438 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2439 .speed = SPEED_100000, 2440 }, 2441 }; 2442 2443 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode) 2444 2445 static void 2446 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto, 2447 struct ethtool_link_ksettings *cmd) 2448 { 2449 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2450 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2451 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2452 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2453 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2454 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2455 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2456 2457 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2458 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2459 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2460 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | 2461 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX)) 2462 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2463 } 2464 2465 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode) 2466 { 2467 int i; 2468 2469 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2470 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) 2471 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2472 mode); 2473 } 2474 } 2475 2476 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto, 2477 struct ethtool_link_ksettings *cmd) 2478 { 2479 u32 speed = SPEED_UNKNOWN; 2480 u8 duplex = DUPLEX_UNKNOWN; 2481 int i; 2482 2483 if (!carrier_ok) 2484 goto out; 2485 2486 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2487 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) { 2488 speed = mlxsw_sp_port_link_mode[i].speed; 2489 duplex = DUPLEX_FULL; 2490 break; 2491 } 2492 } 2493 out: 2494 cmd->base.speed = speed; 2495 cmd->base.duplex = duplex; 2496 } 2497 2498 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto) 2499 { 2500 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2501 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2502 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2503 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2504 return PORT_FIBRE; 2505 2506 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2507 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2508 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4)) 2509 return PORT_DA; 2510 2511 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2512 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2513 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2514 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4)) 2515 return PORT_NONE; 2516 2517 return PORT_OTHER; 2518 } 2519 2520 static u32 2521 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd) 2522 { 2523 u32 ptys_proto = 0; 2524 int i; 2525 2526 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2527 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2528 cmd->link_modes.advertising)) 2529 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2530 } 2531 return ptys_proto; 2532 } 2533 2534 static u32 mlxsw_sp_to_ptys_speed(u32 speed) 2535 { 2536 u32 ptys_proto = 0; 2537 int i; 2538 2539 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2540 if (speed == mlxsw_sp_port_link_mode[i].speed) 2541 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2542 } 2543 return ptys_proto; 2544 } 2545 2546 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed) 2547 { 2548 u32 ptys_proto = 0; 2549 int i; 2550 2551 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2552 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed) 2553 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2554 } 2555 return ptys_proto; 2556 } 2557 2558 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap, 2559 struct ethtool_link_ksettings *cmd) 2560 { 2561 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause); 2562 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 2563 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 2564 2565 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd); 2566 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported); 2567 } 2568 2569 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg, 2570 struct ethtool_link_ksettings *cmd) 2571 { 2572 if (!autoneg) 2573 return; 2574 2575 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 2576 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising); 2577 } 2578 2579 static void 2580 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status, 2581 struct ethtool_link_ksettings *cmd) 2582 { 2583 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp) 2584 return; 2585 2586 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg); 2587 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising); 2588 } 2589 2590 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev, 2591 struct ethtool_link_ksettings *cmd) 2592 { 2593 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp; 2594 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2595 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2596 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2597 u8 autoneg_status; 2598 bool autoneg; 2599 int err; 2600 2601 autoneg = mlxsw_sp_port->link.autoneg; 2602 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2603 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2604 if (err) 2605 return err; 2606 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, 2607 ð_proto_oper); 2608 2609 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd); 2610 2611 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd); 2612 2613 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl); 2614 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl); 2615 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd); 2616 2617 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 2618 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper); 2619 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper, 2620 cmd); 2621 2622 return 0; 2623 } 2624 2625 static int 2626 mlxsw_sp_port_set_link_ksettings(struct net_device *dev, 2627 const struct ethtool_link_ksettings *cmd) 2628 { 2629 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2630 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2631 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2632 u32 eth_proto_cap, eth_proto_new; 2633 bool autoneg; 2634 int err; 2635 2636 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2637 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2638 if (err) 2639 return err; 2640 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); 2641 2642 autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 2643 eth_proto_new = autoneg ? 2644 mlxsw_sp_to_ptys_advert_link(cmd) : 2645 mlxsw_sp_to_ptys_speed(cmd->base.speed); 2646 2647 eth_proto_new = eth_proto_new & eth_proto_cap; 2648 if (!eth_proto_new) { 2649 netdev_err(dev, "No supported speed requested\n"); 2650 return -EINVAL; 2651 } 2652 2653 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2654 eth_proto_new, autoneg); 2655 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2656 if (err) 2657 return err; 2658 2659 if (!netif_running(dev)) 2660 return 0; 2661 2662 mlxsw_sp_port->link.autoneg = autoneg; 2663 2664 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2665 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 2666 2667 return 0; 2668 } 2669 2670 static int mlxsw_sp_flash_device(struct net_device *dev, 2671 struct ethtool_flash *flash) 2672 { 2673 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2674 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2675 const struct firmware *firmware; 2676 int err; 2677 2678 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2679 return -EOPNOTSUPP; 2680 2681 dev_hold(dev); 2682 rtnl_unlock(); 2683 2684 err = request_firmware_direct(&firmware, flash->data, &dev->dev); 2685 if (err) 2686 goto out; 2687 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 2688 release_firmware(firmware); 2689 out: 2690 rtnl_lock(); 2691 dev_put(dev); 2692 return err; 2693 } 2694 2695 #define MLXSW_SP_I2C_ADDR_LOW 0x50 2696 #define MLXSW_SP_I2C_ADDR_HIGH 0x51 2697 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256 2698 2699 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port, 2700 u16 offset, u16 size, void *data, 2701 unsigned int *p_read_size) 2702 { 2703 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2704 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE]; 2705 char mcia_pl[MLXSW_REG_MCIA_LEN]; 2706 u16 i2c_addr; 2707 int status; 2708 int err; 2709 2710 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 2711 2712 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH && 2713 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH) 2714 /* Cross pages read, read until offset 256 in low page */ 2715 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset; 2716 2717 i2c_addr = MLXSW_SP_I2C_ADDR_LOW; 2718 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) { 2719 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH; 2720 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH; 2721 } 2722 2723 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module, 2724 0, 0, offset, size, i2c_addr); 2725 2726 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl); 2727 if (err) 2728 return err; 2729 2730 status = mlxsw_reg_mcia_status_get(mcia_pl); 2731 if (status) 2732 return -EIO; 2733 2734 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp); 2735 memcpy(data, eeprom_tmp, size); 2736 *p_read_size = size; 2737 2738 return 0; 2739 } 2740 2741 enum mlxsw_sp_eeprom_module_info_rev_id { 2742 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 2743 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 2744 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 2745 }; 2746 2747 enum mlxsw_sp_eeprom_module_info_id { 2748 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03, 2749 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 2750 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 2751 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 2752 }; 2753 2754 enum mlxsw_sp_eeprom_module_info { 2755 MLXSW_SP_EEPROM_MODULE_INFO_ID, 2756 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID, 2757 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2758 }; 2759 2760 static int mlxsw_sp_get_module_info(struct net_device *netdev, 2761 struct ethtool_modinfo *modinfo) 2762 { 2763 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2764 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE]; 2765 u8 module_rev_id, module_id; 2766 unsigned int read_size; 2767 int err; 2768 2769 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0, 2770 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2771 module_info, &read_size); 2772 if (err) 2773 return err; 2774 2775 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE) 2776 return -EIO; 2777 2778 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID]; 2779 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID]; 2780 2781 switch (module_id) { 2782 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP: 2783 modinfo->type = ETH_MODULE_SFF_8436; 2784 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2785 break; 2786 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS: 2787 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28: 2788 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 || 2789 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) { 2790 modinfo->type = ETH_MODULE_SFF_8636; 2791 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2792 } else { 2793 modinfo->type = ETH_MODULE_SFF_8436; 2794 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2795 } 2796 break; 2797 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP: 2798 modinfo->type = ETH_MODULE_SFF_8472; 2799 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2800 break; 2801 default: 2802 return -EINVAL; 2803 } 2804 2805 return 0; 2806 } 2807 2808 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev, 2809 struct ethtool_eeprom *ee, 2810 u8 *data) 2811 { 2812 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2813 int offset = ee->offset; 2814 unsigned int read_size; 2815 int i = 0; 2816 int err; 2817 2818 if (!ee->len) 2819 return -EINVAL; 2820 2821 memset(data, 0, ee->len); 2822 2823 while (i < ee->len) { 2824 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset, 2825 ee->len - i, data + i, 2826 &read_size); 2827 if (err) { 2828 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n"); 2829 return err; 2830 } 2831 2832 i += read_size; 2833 offset += read_size; 2834 } 2835 2836 return 0; 2837 } 2838 2839 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { 2840 .get_drvinfo = mlxsw_sp_port_get_drvinfo, 2841 .get_link = ethtool_op_get_link, 2842 .get_pauseparam = mlxsw_sp_port_get_pauseparam, 2843 .set_pauseparam = mlxsw_sp_port_set_pauseparam, 2844 .get_strings = mlxsw_sp_port_get_strings, 2845 .set_phys_id = mlxsw_sp_port_set_phys_id, 2846 .get_ethtool_stats = mlxsw_sp_port_get_stats, 2847 .get_sset_count = mlxsw_sp_port_get_sset_count, 2848 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings, 2849 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings, 2850 .flash_device = mlxsw_sp_flash_device, 2851 .get_module_info = mlxsw_sp_get_module_info, 2852 .get_module_eeprom = mlxsw_sp_get_module_eeprom, 2853 }; 2854 2855 static int 2856 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width) 2857 { 2858 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2859 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width; 2860 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2861 u32 eth_proto_admin; 2862 2863 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed); 2864 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2865 eth_proto_admin, mlxsw_sp_port->link.autoneg); 2866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2867 } 2868 2869 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 2870 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 2871 bool dwrr, u8 dwrr_weight) 2872 { 2873 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2874 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2875 2876 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2877 next_index); 2878 mlxsw_reg_qeec_de_set(qeec_pl, true); 2879 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 2880 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 2881 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2882 } 2883 2884 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 2885 enum mlxsw_reg_qeec_hr hr, u8 index, 2886 u8 next_index, u32 maxrate) 2887 { 2888 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2889 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2890 2891 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2892 next_index); 2893 mlxsw_reg_qeec_mase_set(qeec_pl, true); 2894 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 2895 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2896 } 2897 2898 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 2899 enum mlxsw_reg_qeec_hr hr, u8 index, 2900 u8 next_index, u32 minrate) 2901 { 2902 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2903 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2904 2905 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2906 next_index); 2907 mlxsw_reg_qeec_mise_set(qeec_pl, true); 2908 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 2909 2910 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2911 } 2912 2913 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 2914 u8 switch_prio, u8 tclass) 2915 { 2916 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2917 char qtct_pl[MLXSW_REG_QTCT_LEN]; 2918 2919 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 2920 tclass); 2921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 2922 } 2923 2924 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 2925 { 2926 int err, i; 2927 2928 /* Setup the elements hierarcy, so that each TC is linked to 2929 * one subgroup, which are all member in the same group. 2930 */ 2931 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2932 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false, 2933 0); 2934 if (err) 2935 return err; 2936 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2937 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2938 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i, 2939 0, false, 0); 2940 if (err) 2941 return err; 2942 } 2943 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2944 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2945 MLXSW_REG_QEEC_HIERARCY_TC, i, i, 2946 false, 0); 2947 if (err) 2948 return err; 2949 2950 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2951 MLXSW_REG_QEEC_HIERARCY_TC, 2952 i + 8, i, 2953 false, 0); 2954 if (err) 2955 return err; 2956 } 2957 2958 /* Make sure the max shaper is disabled in all hierarchies that 2959 * support it. 2960 */ 2961 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2962 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0, 2963 MLXSW_REG_QEEC_MAS_DIS); 2964 if (err) 2965 return err; 2966 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2967 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2968 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2969 i, 0, 2970 MLXSW_REG_QEEC_MAS_DIS); 2971 if (err) 2972 return err; 2973 } 2974 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2975 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2976 MLXSW_REG_QEEC_HIERARCY_TC, 2977 i, i, 2978 MLXSW_REG_QEEC_MAS_DIS); 2979 if (err) 2980 return err; 2981 2982 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2983 MLXSW_REG_QEEC_HIERARCY_TC, 2984 i + 8, i, 2985 MLXSW_REG_QEEC_MAS_DIS); 2986 if (err) 2987 return err; 2988 } 2989 2990 /* Configure the min shaper for multicast TCs. */ 2991 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2992 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 2993 MLXSW_REG_QEEC_HIERARCY_TC, 2994 i + 8, i, 2995 MLXSW_REG_QEEC_MIS_MIN); 2996 if (err) 2997 return err; 2998 } 2999 3000 /* Map all priorities to traffic class 0. */ 3001 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 3002 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 3003 if (err) 3004 return err; 3005 } 3006 3007 return 0; 3008 } 3009 3010 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 3011 bool enable) 3012 { 3013 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3014 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 3015 3016 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 3017 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 3018 } 3019 3020 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 3021 bool split, u8 module, u8 width, u8 lane) 3022 { 3023 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 3024 struct mlxsw_sp_port *mlxsw_sp_port; 3025 struct net_device *dev; 3026 int err; 3027 3028 err = mlxsw_core_port_init(mlxsw_sp->core, local_port); 3029 if (err) { 3030 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 3031 local_port); 3032 return err; 3033 } 3034 3035 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 3036 if (!dev) { 3037 err = -ENOMEM; 3038 goto err_alloc_etherdev; 3039 } 3040 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 3041 mlxsw_sp_port = netdev_priv(dev); 3042 mlxsw_sp_port->dev = dev; 3043 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 3044 mlxsw_sp_port->local_port = local_port; 3045 mlxsw_sp_port->pvid = 1; 3046 mlxsw_sp_port->split = split; 3047 mlxsw_sp_port->mapping.module = module; 3048 mlxsw_sp_port->mapping.width = width; 3049 mlxsw_sp_port->mapping.lane = lane; 3050 mlxsw_sp_port->link.autoneg = 1; 3051 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 3052 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list); 3053 3054 mlxsw_sp_port->pcpu_stats = 3055 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 3056 if (!mlxsw_sp_port->pcpu_stats) { 3057 err = -ENOMEM; 3058 goto err_alloc_stats; 3059 } 3060 3061 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample), 3062 GFP_KERNEL); 3063 if (!mlxsw_sp_port->sample) { 3064 err = -ENOMEM; 3065 goto err_alloc_sample; 3066 } 3067 3068 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 3069 &update_stats_cache); 3070 3071 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 3072 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 3073 3074 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); 3075 if (err) { 3076 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 3077 mlxsw_sp_port->local_port); 3078 goto err_port_module_map; 3079 } 3080 3081 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0); 3082 if (err) { 3083 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 3084 mlxsw_sp_port->local_port); 3085 goto err_port_swid_set; 3086 } 3087 3088 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 3089 if (err) { 3090 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 3091 mlxsw_sp_port->local_port); 3092 goto err_dev_addr_init; 3093 } 3094 3095 netif_carrier_off(dev); 3096 3097 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 3098 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 3099 dev->hw_features |= NETIF_F_HW_TC; 3100 3101 dev->min_mtu = 0; 3102 dev->max_mtu = ETH_MAX_MTU; 3103 3104 /* Each packet needs to have a Tx header (metadata) on top all other 3105 * headers. 3106 */ 3107 dev->needed_headroom = MLXSW_TXHDR_LEN; 3108 3109 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 3110 if (err) { 3111 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 3112 mlxsw_sp_port->local_port); 3113 goto err_port_system_port_mapping_set; 3114 } 3115 3116 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width); 3117 if (err) { 3118 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 3119 mlxsw_sp_port->local_port); 3120 goto err_port_speed_by_width_set; 3121 } 3122 3123 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 3124 if (err) { 3125 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 3126 mlxsw_sp_port->local_port); 3127 goto err_port_mtu_set; 3128 } 3129 3130 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 3131 if (err) 3132 goto err_port_admin_status_set; 3133 3134 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 3135 if (err) { 3136 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 3137 mlxsw_sp_port->local_port); 3138 goto err_port_buffers_init; 3139 } 3140 3141 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 3142 if (err) { 3143 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 3144 mlxsw_sp_port->local_port); 3145 goto err_port_ets_init; 3146 } 3147 3148 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 3149 if (err) { 3150 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 3151 mlxsw_sp_port->local_port); 3152 goto err_port_tc_mc_mode; 3153 } 3154 3155 /* ETS and buffers must be initialized before DCB. */ 3156 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 3157 if (err) { 3158 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 3159 mlxsw_sp_port->local_port); 3160 goto err_port_dcb_init; 3161 } 3162 3163 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 3164 if (err) { 3165 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 3166 mlxsw_sp_port->local_port); 3167 goto err_port_fids_init; 3168 } 3169 3170 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 3171 if (err) { 3172 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 3173 mlxsw_sp_port->local_port); 3174 goto err_port_qdiscs_init; 3175 } 3176 3177 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 3178 if (err) { 3179 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 3180 mlxsw_sp_port->local_port); 3181 goto err_port_nve_init; 3182 } 3183 3184 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 3185 if (IS_ERR(mlxsw_sp_port_vlan)) { 3186 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 3187 mlxsw_sp_port->local_port); 3188 err = PTR_ERR(mlxsw_sp_port_vlan); 3189 goto err_port_vlan_get; 3190 } 3191 3192 mlxsw_sp_port_switchdev_init(mlxsw_sp_port); 3193 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 3194 err = register_netdev(dev); 3195 if (err) { 3196 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 3197 mlxsw_sp_port->local_port); 3198 goto err_register_netdev; 3199 } 3200 3201 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 3202 mlxsw_sp_port, dev, module + 1, 3203 mlxsw_sp_port->split, lane / width); 3204 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 3205 return 0; 3206 3207 err_register_netdev: 3208 mlxsw_sp->ports[local_port] = NULL; 3209 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 3210 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 3211 err_port_vlan_get: 3212 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 3213 err_port_nve_init: 3214 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3215 err_port_qdiscs_init: 3216 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3217 err_port_fids_init: 3218 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3219 err_port_dcb_init: 3220 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3221 err_port_tc_mc_mode: 3222 err_port_ets_init: 3223 err_port_buffers_init: 3224 err_port_admin_status_set: 3225 err_port_mtu_set: 3226 err_port_speed_by_width_set: 3227 err_port_system_port_mapping_set: 3228 err_dev_addr_init: 3229 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3230 err_port_swid_set: 3231 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3232 err_port_module_map: 3233 kfree(mlxsw_sp_port->sample); 3234 err_alloc_sample: 3235 free_percpu(mlxsw_sp_port->pcpu_stats); 3236 err_alloc_stats: 3237 free_netdev(dev); 3238 err_alloc_etherdev: 3239 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3240 return err; 3241 } 3242 3243 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3244 { 3245 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3246 3247 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 3248 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 3249 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 3250 mlxsw_sp->ports[local_port] = NULL; 3251 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 3252 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 3253 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 3254 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3255 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3256 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3257 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3258 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3259 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3260 kfree(mlxsw_sp_port->sample); 3261 free_percpu(mlxsw_sp_port->pcpu_stats); 3262 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 3263 free_netdev(mlxsw_sp_port->dev); 3264 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3265 } 3266 3267 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3268 { 3269 return mlxsw_sp->ports[local_port] != NULL; 3270 } 3271 3272 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 3273 { 3274 int i; 3275 3276 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 3277 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3278 mlxsw_sp_port_remove(mlxsw_sp, i); 3279 kfree(mlxsw_sp->port_to_module); 3280 kfree(mlxsw_sp->ports); 3281 } 3282 3283 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 3284 { 3285 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 3286 u8 module, width, lane; 3287 size_t alloc_size; 3288 int i; 3289 int err; 3290 3291 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 3292 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 3293 if (!mlxsw_sp->ports) 3294 return -ENOMEM; 3295 3296 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int), 3297 GFP_KERNEL); 3298 if (!mlxsw_sp->port_to_module) { 3299 err = -ENOMEM; 3300 goto err_port_to_module_alloc; 3301 } 3302 3303 for (i = 1; i < max_ports; i++) { 3304 /* Mark as invalid */ 3305 mlxsw_sp->port_to_module[i] = -1; 3306 3307 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module, 3308 &width, &lane); 3309 if (err) 3310 goto err_port_module_info_get; 3311 if (!width) 3312 continue; 3313 mlxsw_sp->port_to_module[i] = module; 3314 err = mlxsw_sp_port_create(mlxsw_sp, i, false, 3315 module, width, lane); 3316 if (err) 3317 goto err_port_create; 3318 } 3319 return 0; 3320 3321 err_port_create: 3322 err_port_module_info_get: 3323 for (i--; i >= 1; i--) 3324 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3325 mlxsw_sp_port_remove(mlxsw_sp, i); 3326 kfree(mlxsw_sp->port_to_module); 3327 err_port_to_module_alloc: 3328 kfree(mlxsw_sp->ports); 3329 return err; 3330 } 3331 3332 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port) 3333 { 3334 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX; 3335 3336 return local_port - offset; 3337 } 3338 3339 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port, 3340 u8 module, unsigned int count) 3341 { 3342 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count; 3343 int err, i; 3344 3345 for (i = 0; i < count; i++) { 3346 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true, 3347 module, width, i * width); 3348 if (err) 3349 goto err_port_create; 3350 } 3351 3352 return 0; 3353 3354 err_port_create: 3355 for (i--; i >= 0; i--) 3356 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3357 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3358 return err; 3359 } 3360 3361 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 3362 u8 base_port, unsigned int count) 3363 { 3364 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH; 3365 int i; 3366 3367 /* Split by four means we need to re-create two ports, otherwise 3368 * only one. 3369 */ 3370 count = count / 2; 3371 3372 for (i = 0; i < count; i++) { 3373 local_port = base_port + i * 2; 3374 if (mlxsw_sp->port_to_module[local_port] < 0) 3375 continue; 3376 module = mlxsw_sp->port_to_module[local_port]; 3377 3378 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module, 3379 width, 0); 3380 } 3381 } 3382 3383 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 3384 unsigned int count, 3385 struct netlink_ext_ack *extack) 3386 { 3387 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3388 struct mlxsw_sp_port *mlxsw_sp_port; 3389 u8 module, cur_width, base_port; 3390 int i; 3391 int err; 3392 3393 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3394 if (!mlxsw_sp_port) { 3395 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3396 local_port); 3397 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3398 return -EINVAL; 3399 } 3400 3401 module = mlxsw_sp_port->mapping.module; 3402 cur_width = mlxsw_sp_port->mapping.width; 3403 3404 if (count != 2 && count != 4) { 3405 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n"); 3406 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports"); 3407 return -EINVAL; 3408 } 3409 3410 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) { 3411 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n"); 3412 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further"); 3413 return -EINVAL; 3414 } 3415 3416 /* Make sure we have enough slave (even) ports for the split. */ 3417 if (count == 2) { 3418 base_port = local_port; 3419 if (mlxsw_sp->ports[base_port + 1]) { 3420 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3421 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3422 return -EINVAL; 3423 } 3424 } else { 3425 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3426 if (mlxsw_sp->ports[base_port + 1] || 3427 mlxsw_sp->ports[base_port + 3]) { 3428 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3429 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3430 return -EINVAL; 3431 } 3432 } 3433 3434 for (i = 0; i < count; i++) 3435 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3436 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3437 3438 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count); 3439 if (err) { 3440 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 3441 goto err_port_split_create; 3442 } 3443 3444 return 0; 3445 3446 err_port_split_create: 3447 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3448 return err; 3449 } 3450 3451 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port, 3452 struct netlink_ext_ack *extack) 3453 { 3454 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3455 struct mlxsw_sp_port *mlxsw_sp_port; 3456 u8 cur_width, base_port; 3457 unsigned int count; 3458 int i; 3459 3460 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3461 if (!mlxsw_sp_port) { 3462 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3463 local_port); 3464 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3465 return -EINVAL; 3466 } 3467 3468 if (!mlxsw_sp_port->split) { 3469 netdev_err(mlxsw_sp_port->dev, "Port was not split\n"); 3470 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 3471 return -EINVAL; 3472 } 3473 3474 cur_width = mlxsw_sp_port->mapping.width; 3475 count = cur_width == 1 ? 4 : 2; 3476 3477 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3478 3479 /* Determine which ports to remove. */ 3480 if (count == 2 && local_port >= base_port + 2) 3481 base_port = base_port + 2; 3482 3483 for (i = 0; i < count; i++) 3484 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3485 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3486 3487 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3488 3489 return 0; 3490 } 3491 3492 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 3493 char *pude_pl, void *priv) 3494 { 3495 struct mlxsw_sp *mlxsw_sp = priv; 3496 struct mlxsw_sp_port *mlxsw_sp_port; 3497 enum mlxsw_reg_pude_oper_status status; 3498 u8 local_port; 3499 3500 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 3501 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3502 if (!mlxsw_sp_port) 3503 return; 3504 3505 status = mlxsw_reg_pude_oper_status_get(pude_pl); 3506 if (status == MLXSW_PORT_OPER_STATUS_UP) { 3507 netdev_info(mlxsw_sp_port->dev, "link up\n"); 3508 netif_carrier_on(mlxsw_sp_port->dev); 3509 } else { 3510 netdev_info(mlxsw_sp_port->dev, "link down\n"); 3511 netif_carrier_off(mlxsw_sp_port->dev); 3512 } 3513 } 3514 3515 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 3516 u8 local_port, void *priv) 3517 { 3518 struct mlxsw_sp *mlxsw_sp = priv; 3519 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3520 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 3521 3522 if (unlikely(!mlxsw_sp_port)) { 3523 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 3524 local_port); 3525 return; 3526 } 3527 3528 skb->dev = mlxsw_sp_port->dev; 3529 3530 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 3531 u64_stats_update_begin(&pcpu_stats->syncp); 3532 pcpu_stats->rx_packets++; 3533 pcpu_stats->rx_bytes += skb->len; 3534 u64_stats_update_end(&pcpu_stats->syncp); 3535 3536 skb->protocol = eth_type_trans(skb, skb->dev); 3537 netif_receive_skb(skb); 3538 } 3539 3540 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 3541 void *priv) 3542 { 3543 skb->offload_fwd_mark = 1; 3544 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3545 } 3546 3547 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb, 3548 u8 local_port, void *priv) 3549 { 3550 skb->offload_mr_fwd_mark = 1; 3551 skb->offload_fwd_mark = 1; 3552 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3553 } 3554 3555 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port, 3556 void *priv) 3557 { 3558 struct mlxsw_sp *mlxsw_sp = priv; 3559 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3560 struct psample_group *psample_group; 3561 u32 size; 3562 3563 if (unlikely(!mlxsw_sp_port)) { 3564 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n", 3565 local_port); 3566 goto out; 3567 } 3568 if (unlikely(!mlxsw_sp_port->sample)) { 3569 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n", 3570 local_port); 3571 goto out; 3572 } 3573 3574 size = mlxsw_sp_port->sample->truncate ? 3575 mlxsw_sp_port->sample->trunc_size : skb->len; 3576 3577 rcu_read_lock(); 3578 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group); 3579 if (!psample_group) 3580 goto out_unlock; 3581 psample_sample_packet(psample_group, skb, size, 3582 mlxsw_sp_port->dev->ifindex, 0, 3583 mlxsw_sp_port->sample->rate); 3584 out_unlock: 3585 rcu_read_unlock(); 3586 out: 3587 consume_skb(skb); 3588 } 3589 3590 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3591 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 3592 _is_ctrl, SP_##_trap_group, DISCARD) 3593 3594 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3595 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 3596 _is_ctrl, SP_##_trap_group, DISCARD) 3597 3598 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3599 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \ 3600 _is_ctrl, SP_##_trap_group, DISCARD) 3601 3602 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 3603 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 3604 3605 static const struct mlxsw_listener mlxsw_sp_listener[] = { 3606 /* Events */ 3607 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 3608 /* L2 traps */ 3609 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true), 3610 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true), 3611 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true), 3612 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false), 3613 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false), 3614 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false), 3615 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false), 3616 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false), 3617 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false), 3618 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false), 3619 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false), 3620 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false), 3621 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD, 3622 false), 3623 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3624 false), 3625 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD, 3626 false), 3627 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3628 false), 3629 /* L3 traps */ 3630 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3631 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3632 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3633 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false), 3634 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 3635 false), 3636 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false), 3637 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 3638 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false), 3639 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP, 3640 false), 3641 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false), 3642 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false), 3643 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false), 3644 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false), 3645 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false), 3646 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false), 3647 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3648 false), 3649 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3650 false), 3651 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3652 false), 3653 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3654 false), 3655 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false), 3656 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 3657 false), 3658 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false), 3659 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false), 3660 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false), 3661 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false), 3662 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3663 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false), 3664 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3665 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3666 /* PKT Sample trap */ 3667 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU, 3668 false, SP_IP2ME, DISCARD), 3669 /* ACL trap */ 3670 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false), 3671 /* Multicast Router Traps */ 3672 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false), 3673 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false), 3674 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false), 3675 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 3676 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 3677 /* NVE traps */ 3678 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false), 3679 }; 3680 3681 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 3682 { 3683 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 3684 enum mlxsw_reg_qpcr_ir_units ir_units; 3685 int max_cpu_policers; 3686 bool is_bytes; 3687 u8 burst_size; 3688 u32 rate; 3689 int i, err; 3690 3691 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 3692 return -EIO; 3693 3694 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3695 3696 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 3697 for (i = 0; i < max_cpu_policers; i++) { 3698 is_bytes = false; 3699 switch (i) { 3700 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3701 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3702 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3703 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3704 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3705 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3706 rate = 128; 3707 burst_size = 7; 3708 break; 3709 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3710 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3711 rate = 16 * 1024; 3712 burst_size = 10; 3713 break; 3714 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3715 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3716 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3717 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3718 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3719 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3720 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3721 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3722 rate = 1024; 3723 burst_size = 7; 3724 break; 3725 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3726 rate = 4 * 1024; 3727 burst_size = 4; 3728 break; 3729 default: 3730 continue; 3731 } 3732 3733 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 3734 burst_size); 3735 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 3736 if (err) 3737 return err; 3738 } 3739 3740 return 0; 3741 } 3742 3743 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 3744 { 3745 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3746 enum mlxsw_reg_htgt_trap_group i; 3747 int max_cpu_policers; 3748 int max_trap_groups; 3749 u8 priority, tc; 3750 u16 policer_id; 3751 int err; 3752 3753 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 3754 return -EIO; 3755 3756 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 3757 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3758 3759 for (i = 0; i < max_trap_groups; i++) { 3760 policer_id = i; 3761 switch (i) { 3762 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3763 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3764 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3765 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3766 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3767 priority = 5; 3768 tc = 5; 3769 break; 3770 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3771 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3772 priority = 4; 3773 tc = 4; 3774 break; 3775 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3776 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3777 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3778 priority = 3; 3779 tc = 3; 3780 break; 3781 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3782 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3783 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3784 priority = 2; 3785 tc = 2; 3786 break; 3787 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3788 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3789 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3790 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3791 priority = 1; 3792 tc = 1; 3793 break; 3794 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 3795 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 3796 tc = MLXSW_REG_HTGT_DEFAULT_TC; 3797 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 3798 break; 3799 default: 3800 continue; 3801 } 3802 3803 if (max_cpu_policers <= policer_id && 3804 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 3805 return -EIO; 3806 3807 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 3808 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3809 if (err) 3810 return err; 3811 } 3812 3813 return 0; 3814 } 3815 3816 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 3817 { 3818 int i; 3819 int err; 3820 3821 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 3822 if (err) 3823 return err; 3824 3825 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 3826 if (err) 3827 return err; 3828 3829 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3830 err = mlxsw_core_trap_register(mlxsw_sp->core, 3831 &mlxsw_sp_listener[i], 3832 mlxsw_sp); 3833 if (err) 3834 goto err_listener_register; 3835 3836 } 3837 return 0; 3838 3839 err_listener_register: 3840 for (i--; i >= 0; i--) { 3841 mlxsw_core_trap_unregister(mlxsw_sp->core, 3842 &mlxsw_sp_listener[i], 3843 mlxsw_sp); 3844 } 3845 return err; 3846 } 3847 3848 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 3849 { 3850 int i; 3851 3852 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3853 mlxsw_core_trap_unregister(mlxsw_sp->core, 3854 &mlxsw_sp_listener[i], 3855 mlxsw_sp); 3856 } 3857 } 3858 3859 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 3860 { 3861 char slcr_pl[MLXSW_REG_SLCR_LEN]; 3862 u32 seed; 3863 int err; 3864 3865 get_random_bytes(&seed, sizeof(seed)); 3866 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 3867 MLXSW_REG_SLCR_LAG_HASH_DMAC | 3868 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 3869 MLXSW_REG_SLCR_LAG_HASH_VLANID | 3870 MLXSW_REG_SLCR_LAG_HASH_SIP | 3871 MLXSW_REG_SLCR_LAG_HASH_DIP | 3872 MLXSW_REG_SLCR_LAG_HASH_SPORT | 3873 MLXSW_REG_SLCR_LAG_HASH_DPORT | 3874 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 3875 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 3876 if (err) 3877 return err; 3878 3879 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 3880 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 3881 return -EIO; 3882 3883 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 3884 sizeof(struct mlxsw_sp_upper), 3885 GFP_KERNEL); 3886 if (!mlxsw_sp->lags) 3887 return -ENOMEM; 3888 3889 return 0; 3890 } 3891 3892 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 3893 { 3894 kfree(mlxsw_sp->lags); 3895 } 3896 3897 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 3898 { 3899 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3900 3901 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3902 MLXSW_REG_HTGT_INVALID_POLICER, 3903 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 3904 MLXSW_REG_HTGT_DEFAULT_TC); 3905 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3906 } 3907 3908 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 3909 unsigned long event, void *ptr); 3910 3911 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 3912 const struct mlxsw_bus_info *mlxsw_bus_info) 3913 { 3914 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3915 int err; 3916 3917 mlxsw_sp->core = mlxsw_core; 3918 mlxsw_sp->bus_info = mlxsw_bus_info; 3919 3920 err = mlxsw_sp_fw_rev_validate(mlxsw_sp); 3921 if (err) 3922 return err; 3923 3924 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3925 if (err) { 3926 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3927 return err; 3928 } 3929 3930 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3931 if (err) { 3932 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3933 return err; 3934 } 3935 3936 err = mlxsw_sp_fids_init(mlxsw_sp); 3937 if (err) { 3938 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3939 goto err_fids_init; 3940 } 3941 3942 err = mlxsw_sp_traps_init(mlxsw_sp); 3943 if (err) { 3944 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3945 goto err_traps_init; 3946 } 3947 3948 err = mlxsw_sp_buffers_init(mlxsw_sp); 3949 if (err) { 3950 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3951 goto err_buffers_init; 3952 } 3953 3954 err = mlxsw_sp_lag_init(mlxsw_sp); 3955 if (err) { 3956 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3957 goto err_lag_init; 3958 } 3959 3960 /* Initialize SPAN before router and switchdev, so that those components 3961 * can call mlxsw_sp_span_respin(). 3962 */ 3963 err = mlxsw_sp_span_init(mlxsw_sp); 3964 if (err) { 3965 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3966 goto err_span_init; 3967 } 3968 3969 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3970 if (err) { 3971 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3972 goto err_switchdev_init; 3973 } 3974 3975 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3976 if (err) { 3977 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3978 goto err_counter_pool_init; 3979 } 3980 3981 err = mlxsw_sp_afa_init(mlxsw_sp); 3982 if (err) { 3983 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3984 goto err_afa_init; 3985 } 3986 3987 err = mlxsw_sp_nve_init(mlxsw_sp); 3988 if (err) { 3989 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 3990 goto err_nve_init; 3991 } 3992 3993 err = mlxsw_sp_router_init(mlxsw_sp); 3994 if (err) { 3995 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3996 goto err_router_init; 3997 } 3998 3999 /* Initialize netdevice notifier after router and SPAN is initialized, 4000 * so that the event handler can use router structures and call SPAN 4001 * respin. 4002 */ 4003 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 4004 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb); 4005 if (err) { 4006 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 4007 goto err_netdev_notifier; 4008 } 4009 4010 err = mlxsw_sp_acl_init(mlxsw_sp); 4011 if (err) { 4012 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 4013 goto err_acl_init; 4014 } 4015 4016 err = mlxsw_sp_dpipe_init(mlxsw_sp); 4017 if (err) { 4018 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 4019 goto err_dpipe_init; 4020 } 4021 4022 err = mlxsw_sp_ports_create(mlxsw_sp); 4023 if (err) { 4024 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 4025 goto err_ports_create; 4026 } 4027 4028 return 0; 4029 4030 err_ports_create: 4031 mlxsw_sp_dpipe_fini(mlxsw_sp); 4032 err_dpipe_init: 4033 mlxsw_sp_acl_fini(mlxsw_sp); 4034 err_acl_init: 4035 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 4036 err_netdev_notifier: 4037 mlxsw_sp_router_fini(mlxsw_sp); 4038 err_router_init: 4039 mlxsw_sp_nve_fini(mlxsw_sp); 4040 err_nve_init: 4041 mlxsw_sp_afa_fini(mlxsw_sp); 4042 err_afa_init: 4043 mlxsw_sp_counter_pool_fini(mlxsw_sp); 4044 err_counter_pool_init: 4045 mlxsw_sp_switchdev_fini(mlxsw_sp); 4046 err_switchdev_init: 4047 mlxsw_sp_span_fini(mlxsw_sp); 4048 err_span_init: 4049 mlxsw_sp_lag_fini(mlxsw_sp); 4050 err_lag_init: 4051 mlxsw_sp_buffers_fini(mlxsw_sp); 4052 err_buffers_init: 4053 mlxsw_sp_traps_fini(mlxsw_sp); 4054 err_traps_init: 4055 mlxsw_sp_fids_fini(mlxsw_sp); 4056 err_fids_init: 4057 mlxsw_sp_kvdl_fini(mlxsw_sp); 4058 return err; 4059 } 4060 4061 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 4062 const struct mlxsw_bus_info *mlxsw_bus_info) 4063 { 4064 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4065 4066 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev; 4067 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME; 4068 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 4069 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 4070 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 4071 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 4072 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 4073 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 4074 4075 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 4076 } 4077 4078 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 4079 const struct mlxsw_bus_info *mlxsw_bus_info) 4080 { 4081 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4082 4083 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 4084 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 4085 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 4086 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 4087 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 4088 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 4089 4090 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 4091 } 4092 4093 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 4094 { 4095 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4096 4097 mlxsw_sp_ports_remove(mlxsw_sp); 4098 mlxsw_sp_dpipe_fini(mlxsw_sp); 4099 mlxsw_sp_acl_fini(mlxsw_sp); 4100 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 4101 mlxsw_sp_router_fini(mlxsw_sp); 4102 mlxsw_sp_nve_fini(mlxsw_sp); 4103 mlxsw_sp_afa_fini(mlxsw_sp); 4104 mlxsw_sp_counter_pool_fini(mlxsw_sp); 4105 mlxsw_sp_switchdev_fini(mlxsw_sp); 4106 mlxsw_sp_span_fini(mlxsw_sp); 4107 mlxsw_sp_lag_fini(mlxsw_sp); 4108 mlxsw_sp_buffers_fini(mlxsw_sp); 4109 mlxsw_sp_traps_fini(mlxsw_sp); 4110 mlxsw_sp_fids_fini(mlxsw_sp); 4111 mlxsw_sp_kvdl_fini(mlxsw_sp); 4112 } 4113 4114 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 4115 .used_max_mid = 1, 4116 .max_mid = MLXSW_SP_MID_MAX, 4117 .used_flood_tables = 1, 4118 .used_flood_mode = 1, 4119 .flood_mode = 3, 4120 .max_fid_offset_flood_tables = 3, 4121 .fid_offset_flood_table_size = VLAN_N_VID - 1, 4122 .max_fid_flood_tables = 3, 4123 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 4124 .used_max_ib_mc = 1, 4125 .max_ib_mc = 0, 4126 .used_max_pkey = 1, 4127 .max_pkey = 0, 4128 .used_kvd_sizes = 1, 4129 .kvd_hash_single_parts = 59, 4130 .kvd_hash_double_parts = 41, 4131 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 4132 .swid_config = { 4133 { 4134 .used_type = 1, 4135 .type = MLXSW_PORT_SWID_TYPE_ETH, 4136 } 4137 }, 4138 }; 4139 4140 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 4141 .used_max_mid = 1, 4142 .max_mid = MLXSW_SP_MID_MAX, 4143 .used_flood_tables = 1, 4144 .used_flood_mode = 1, 4145 .flood_mode = 3, 4146 .max_fid_offset_flood_tables = 3, 4147 .fid_offset_flood_table_size = VLAN_N_VID - 1, 4148 .max_fid_flood_tables = 3, 4149 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 4150 .used_max_ib_mc = 1, 4151 .max_ib_mc = 0, 4152 .used_max_pkey = 1, 4153 .max_pkey = 0, 4154 .swid_config = { 4155 { 4156 .used_type = 1, 4157 .type = MLXSW_PORT_SWID_TYPE_ETH, 4158 } 4159 }, 4160 }; 4161 4162 static void 4163 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 4164 struct devlink_resource_size_params *kvd_size_params, 4165 struct devlink_resource_size_params *linear_size_params, 4166 struct devlink_resource_size_params *hash_double_size_params, 4167 struct devlink_resource_size_params *hash_single_size_params) 4168 { 4169 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 4170 KVD_SINGLE_MIN_SIZE); 4171 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 4172 KVD_DOUBLE_MIN_SIZE); 4173 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 4174 u32 linear_size_min = 0; 4175 4176 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 4177 MLXSW_SP_KVD_GRANULARITY, 4178 DEVLINK_RESOURCE_UNIT_ENTRY); 4179 devlink_resource_size_params_init(linear_size_params, linear_size_min, 4180 kvd_size - single_size_min - 4181 double_size_min, 4182 MLXSW_SP_KVD_GRANULARITY, 4183 DEVLINK_RESOURCE_UNIT_ENTRY); 4184 devlink_resource_size_params_init(hash_double_size_params, 4185 double_size_min, 4186 kvd_size - single_size_min - 4187 linear_size_min, 4188 MLXSW_SP_KVD_GRANULARITY, 4189 DEVLINK_RESOURCE_UNIT_ENTRY); 4190 devlink_resource_size_params_init(hash_single_size_params, 4191 single_size_min, 4192 kvd_size - double_size_min - 4193 linear_size_min, 4194 MLXSW_SP_KVD_GRANULARITY, 4195 DEVLINK_RESOURCE_UNIT_ENTRY); 4196 } 4197 4198 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 4199 { 4200 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4201 struct devlink_resource_size_params hash_single_size_params; 4202 struct devlink_resource_size_params hash_double_size_params; 4203 struct devlink_resource_size_params linear_size_params; 4204 struct devlink_resource_size_params kvd_size_params; 4205 u32 kvd_size, single_size, double_size, linear_size; 4206 const struct mlxsw_config_profile *profile; 4207 int err; 4208 4209 profile = &mlxsw_sp1_config_profile; 4210 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 4211 return -EIO; 4212 4213 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 4214 &linear_size_params, 4215 &hash_double_size_params, 4216 &hash_single_size_params); 4217 4218 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 4219 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 4220 kvd_size, MLXSW_SP_RESOURCE_KVD, 4221 DEVLINK_RESOURCE_ID_PARENT_TOP, 4222 &kvd_size_params); 4223 if (err) 4224 return err; 4225 4226 linear_size = profile->kvd_linear_size; 4227 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 4228 linear_size, 4229 MLXSW_SP_RESOURCE_KVD_LINEAR, 4230 MLXSW_SP_RESOURCE_KVD, 4231 &linear_size_params); 4232 if (err) 4233 return err; 4234 4235 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 4236 if (err) 4237 return err; 4238 4239 double_size = kvd_size - linear_size; 4240 double_size *= profile->kvd_hash_double_parts; 4241 double_size /= profile->kvd_hash_double_parts + 4242 profile->kvd_hash_single_parts; 4243 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 4244 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 4245 double_size, 4246 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4247 MLXSW_SP_RESOURCE_KVD, 4248 &hash_double_size_params); 4249 if (err) 4250 return err; 4251 4252 single_size = kvd_size - double_size - linear_size; 4253 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 4254 single_size, 4255 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4256 MLXSW_SP_RESOURCE_KVD, 4257 &hash_single_size_params); 4258 if (err) 4259 return err; 4260 4261 return 0; 4262 } 4263 4264 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 4265 { 4266 return mlxsw_sp1_resources_kvd_register(mlxsw_core); 4267 } 4268 4269 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 4270 { 4271 return 0; 4272 } 4273 4274 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 4275 const struct mlxsw_config_profile *profile, 4276 u64 *p_single_size, u64 *p_double_size, 4277 u64 *p_linear_size) 4278 { 4279 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4280 u32 double_size; 4281 int err; 4282 4283 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4284 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 4285 return -EIO; 4286 4287 /* The hash part is what left of the kvd without the 4288 * linear part. It is split to the single size and 4289 * double size by the parts ratio from the profile. 4290 * Both sizes must be a multiplications of the 4291 * granularity from the profile. In case the user 4292 * provided the sizes they are obtained via devlink. 4293 */ 4294 err = devlink_resource_size_get(devlink, 4295 MLXSW_SP_RESOURCE_KVD_LINEAR, 4296 p_linear_size); 4297 if (err) 4298 *p_linear_size = profile->kvd_linear_size; 4299 4300 err = devlink_resource_size_get(devlink, 4301 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4302 p_double_size); 4303 if (err) { 4304 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4305 *p_linear_size; 4306 double_size *= profile->kvd_hash_double_parts; 4307 double_size /= profile->kvd_hash_double_parts + 4308 profile->kvd_hash_single_parts; 4309 *p_double_size = rounddown(double_size, 4310 MLXSW_SP_KVD_GRANULARITY); 4311 } 4312 4313 err = devlink_resource_size_get(devlink, 4314 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4315 p_single_size); 4316 if (err) 4317 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4318 *p_double_size - *p_linear_size; 4319 4320 /* Check results are legal. */ 4321 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4322 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 4323 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 4324 return -EIO; 4325 4326 return 0; 4327 } 4328 4329 static struct mlxsw_driver mlxsw_sp1_driver = { 4330 .kind = mlxsw_sp1_driver_name, 4331 .priv_size = sizeof(struct mlxsw_sp), 4332 .init = mlxsw_sp1_init, 4333 .fini = mlxsw_sp_fini, 4334 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4335 .port_split = mlxsw_sp_port_split, 4336 .port_unsplit = mlxsw_sp_port_unsplit, 4337 .sb_pool_get = mlxsw_sp_sb_pool_get, 4338 .sb_pool_set = mlxsw_sp_sb_pool_set, 4339 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4340 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4341 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4342 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4343 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4344 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4345 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4346 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4347 .txhdr_construct = mlxsw_sp_txhdr_construct, 4348 .resources_register = mlxsw_sp1_resources_register, 4349 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 4350 .txhdr_len = MLXSW_TXHDR_LEN, 4351 .profile = &mlxsw_sp1_config_profile, 4352 .res_query_enabled = true, 4353 }; 4354 4355 static struct mlxsw_driver mlxsw_sp2_driver = { 4356 .kind = mlxsw_sp2_driver_name, 4357 .priv_size = sizeof(struct mlxsw_sp), 4358 .init = mlxsw_sp2_init, 4359 .fini = mlxsw_sp_fini, 4360 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4361 .port_split = mlxsw_sp_port_split, 4362 .port_unsplit = mlxsw_sp_port_unsplit, 4363 .sb_pool_get = mlxsw_sp_sb_pool_get, 4364 .sb_pool_set = mlxsw_sp_sb_pool_set, 4365 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4366 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4367 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4368 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4369 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4370 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4371 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4372 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4373 .txhdr_construct = mlxsw_sp_txhdr_construct, 4374 .resources_register = mlxsw_sp2_resources_register, 4375 .txhdr_len = MLXSW_TXHDR_LEN, 4376 .profile = &mlxsw_sp2_config_profile, 4377 .res_query_enabled = true, 4378 }; 4379 4380 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 4381 { 4382 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 4383 } 4384 4385 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data) 4386 { 4387 struct mlxsw_sp_port **p_mlxsw_sp_port = data; 4388 int ret = 0; 4389 4390 if (mlxsw_sp_port_dev_check(lower_dev)) { 4391 *p_mlxsw_sp_port = netdev_priv(lower_dev); 4392 ret = 1; 4393 } 4394 4395 return ret; 4396 } 4397 4398 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4399 { 4400 struct mlxsw_sp_port *mlxsw_sp_port; 4401 4402 if (mlxsw_sp_port_dev_check(dev)) 4403 return netdev_priv(dev); 4404 4405 mlxsw_sp_port = NULL; 4406 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port); 4407 4408 return mlxsw_sp_port; 4409 } 4410 4411 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4412 { 4413 struct mlxsw_sp_port *mlxsw_sp_port; 4414 4415 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4416 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4417 } 4418 4419 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4420 { 4421 struct mlxsw_sp_port *mlxsw_sp_port; 4422 4423 if (mlxsw_sp_port_dev_check(dev)) 4424 return netdev_priv(dev); 4425 4426 mlxsw_sp_port = NULL; 4427 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4428 &mlxsw_sp_port); 4429 4430 return mlxsw_sp_port; 4431 } 4432 4433 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4434 { 4435 struct mlxsw_sp_port *mlxsw_sp_port; 4436 4437 rcu_read_lock(); 4438 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4439 if (mlxsw_sp_port) 4440 dev_hold(mlxsw_sp_port->dev); 4441 rcu_read_unlock(); 4442 return mlxsw_sp_port; 4443 } 4444 4445 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4446 { 4447 dev_put(mlxsw_sp_port->dev); 4448 } 4449 4450 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4451 { 4452 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4453 4454 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4455 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4456 } 4457 4458 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4459 { 4460 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4461 4462 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4463 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4464 } 4465 4466 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4467 u16 lag_id, u8 port_index) 4468 { 4469 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4470 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4471 4472 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4473 lag_id, port_index); 4474 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4475 } 4476 4477 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4478 u16 lag_id) 4479 { 4480 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4481 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4482 4483 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4484 lag_id); 4485 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4486 } 4487 4488 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4489 u16 lag_id) 4490 { 4491 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4492 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4493 4494 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4495 lag_id); 4496 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4497 } 4498 4499 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4500 u16 lag_id) 4501 { 4502 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4503 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4504 4505 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4506 lag_id); 4507 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4508 } 4509 4510 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4511 struct net_device *lag_dev, 4512 u16 *p_lag_id) 4513 { 4514 struct mlxsw_sp_upper *lag; 4515 int free_lag_id = -1; 4516 u64 max_lag; 4517 int i; 4518 4519 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 4520 for (i = 0; i < max_lag; i++) { 4521 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4522 if (lag->ref_count) { 4523 if (lag->dev == lag_dev) { 4524 *p_lag_id = i; 4525 return 0; 4526 } 4527 } else if (free_lag_id < 0) { 4528 free_lag_id = i; 4529 } 4530 } 4531 if (free_lag_id < 0) 4532 return -EBUSY; 4533 *p_lag_id = free_lag_id; 4534 return 0; 4535 } 4536 4537 static bool 4538 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4539 struct net_device *lag_dev, 4540 struct netdev_lag_upper_info *lag_upper_info, 4541 struct netlink_ext_ack *extack) 4542 { 4543 u16 lag_id; 4544 4545 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4546 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4547 return false; 4548 } 4549 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4550 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4551 return false; 4552 } 4553 return true; 4554 } 4555 4556 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4557 u16 lag_id, u8 *p_port_index) 4558 { 4559 u64 max_lag_members; 4560 int i; 4561 4562 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4563 MAX_LAG_MEMBERS); 4564 for (i = 0; i < max_lag_members; i++) { 4565 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4566 *p_port_index = i; 4567 return 0; 4568 } 4569 } 4570 return -EBUSY; 4571 } 4572 4573 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4574 struct net_device *lag_dev) 4575 { 4576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4577 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 4578 struct mlxsw_sp_upper *lag; 4579 u16 lag_id; 4580 u8 port_index; 4581 int err; 4582 4583 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4584 if (err) 4585 return err; 4586 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4587 if (!lag->ref_count) { 4588 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4589 if (err) 4590 return err; 4591 lag->dev = lag_dev; 4592 } 4593 4594 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4595 if (err) 4596 return err; 4597 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4598 if (err) 4599 goto err_col_port_add; 4600 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id); 4601 if (err) 4602 goto err_col_port_enable; 4603 4604 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4605 mlxsw_sp_port->local_port); 4606 mlxsw_sp_port->lag_id = lag_id; 4607 mlxsw_sp_port->lagged = 1; 4608 lag->ref_count++; 4609 4610 /* Port is no longer usable as a router interface */ 4611 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1); 4612 if (mlxsw_sp_port_vlan->fid) 4613 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 4614 4615 return 0; 4616 4617 err_col_port_enable: 4618 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4619 err_col_port_add: 4620 if (!lag->ref_count) 4621 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4622 return err; 4623 } 4624 4625 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4626 struct net_device *lag_dev) 4627 { 4628 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4629 u16 lag_id = mlxsw_sp_port->lag_id; 4630 struct mlxsw_sp_upper *lag; 4631 4632 if (!mlxsw_sp_port->lagged) 4633 return; 4634 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4635 WARN_ON(lag->ref_count == 0); 4636 4637 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id); 4638 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4639 4640 /* Any VLANs configured on the port are no longer valid */ 4641 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 4642 4643 if (lag->ref_count == 1) 4644 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4645 4646 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4647 mlxsw_sp_port->local_port); 4648 mlxsw_sp_port->lagged = 0; 4649 lag->ref_count--; 4650 4651 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 4652 /* Make sure untagged frames are allowed to ingress */ 4653 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); 4654 } 4655 4656 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4657 u16 lag_id) 4658 { 4659 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4660 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4661 4662 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4663 mlxsw_sp_port->local_port); 4664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4665 } 4666 4667 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4668 u16 lag_id) 4669 { 4670 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4671 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4672 4673 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4674 mlxsw_sp_port->local_port); 4675 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4676 } 4677 4678 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port, 4679 bool lag_tx_enabled) 4680 { 4681 if (lag_tx_enabled) 4682 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, 4683 mlxsw_sp_port->lag_id); 4684 else 4685 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4686 mlxsw_sp_port->lag_id); 4687 } 4688 4689 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4690 struct netdev_lag_lower_state_info *info) 4691 { 4692 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled); 4693 } 4694 4695 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4696 bool enable) 4697 { 4698 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4699 enum mlxsw_reg_spms_state spms_state; 4700 char *spms_pl; 4701 u16 vid; 4702 int err; 4703 4704 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4705 MLXSW_REG_SPMS_STATE_DISCARDING; 4706 4707 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4708 if (!spms_pl) 4709 return -ENOMEM; 4710 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4711 4712 for (vid = 0; vid < VLAN_N_VID; vid++) 4713 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4714 4715 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4716 kfree(spms_pl); 4717 return err; 4718 } 4719 4720 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4721 { 4722 u16 vid = 1; 4723 int err; 4724 4725 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4726 if (err) 4727 return err; 4728 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4729 if (err) 4730 goto err_port_stp_set; 4731 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4732 true, false); 4733 if (err) 4734 goto err_port_vlan_set; 4735 4736 for (; vid <= VLAN_N_VID - 1; vid++) { 4737 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4738 vid, false); 4739 if (err) 4740 goto err_vid_learning_set; 4741 } 4742 4743 return 0; 4744 4745 err_vid_learning_set: 4746 for (vid--; vid >= 1; vid--) 4747 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4748 err_port_vlan_set: 4749 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4750 err_port_stp_set: 4751 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4752 return err; 4753 } 4754 4755 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4756 { 4757 u16 vid; 4758 4759 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4760 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4761 vid, true); 4762 4763 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4764 false, false); 4765 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4766 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4767 } 4768 4769 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4770 { 4771 unsigned int num_vxlans = 0; 4772 struct net_device *dev; 4773 struct list_head *iter; 4774 4775 netdev_for_each_lower_dev(br_dev, dev, iter) { 4776 if (netif_is_vxlan(dev)) 4777 num_vxlans++; 4778 } 4779 4780 return num_vxlans > 1; 4781 } 4782 4783 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4784 struct netlink_ext_ack *extack) 4785 { 4786 if (br_multicast_enabled(br_dev)) { 4787 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4788 return false; 4789 } 4790 4791 if (br_vlan_enabled(br_dev)) { 4792 NL_SET_ERR_MSG_MOD(extack, "VLAN filtering can not be enabled on a bridge with a VxLAN device"); 4793 return false; 4794 } 4795 4796 if (mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4797 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4798 return false; 4799 } 4800 4801 return true; 4802 } 4803 4804 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4805 struct net_device *dev, 4806 unsigned long event, void *ptr) 4807 { 4808 struct netdev_notifier_changeupper_info *info; 4809 struct mlxsw_sp_port *mlxsw_sp_port; 4810 struct netlink_ext_ack *extack; 4811 struct net_device *upper_dev; 4812 struct mlxsw_sp *mlxsw_sp; 4813 int err = 0; 4814 4815 mlxsw_sp_port = netdev_priv(dev); 4816 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4817 info = ptr; 4818 extack = netdev_notifier_info_to_extack(&info->info); 4819 4820 switch (event) { 4821 case NETDEV_PRECHANGEUPPER: 4822 upper_dev = info->upper_dev; 4823 if (!is_vlan_dev(upper_dev) && 4824 !netif_is_lag_master(upper_dev) && 4825 !netif_is_bridge_master(upper_dev) && 4826 !netif_is_ovs_master(upper_dev) && 4827 !netif_is_macvlan(upper_dev)) { 4828 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4829 return -EINVAL; 4830 } 4831 if (!info->linking) 4832 break; 4833 if (netif_is_bridge_master(upper_dev) && 4834 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4835 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4836 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4837 return -EOPNOTSUPP; 4838 if (netdev_has_any_upper_dev(upper_dev) && 4839 (!netif_is_bridge_master(upper_dev) || 4840 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4841 upper_dev))) { 4842 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4843 return -EINVAL; 4844 } 4845 if (netif_is_lag_master(upper_dev) && 4846 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4847 info->upper_info, extack)) 4848 return -EINVAL; 4849 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4850 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4851 return -EINVAL; 4852 } 4853 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4854 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4855 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4856 return -EINVAL; 4857 } 4858 if (netif_is_macvlan(upper_dev) && 4859 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) { 4860 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4861 return -EOPNOTSUPP; 4862 } 4863 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4864 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4865 return -EINVAL; 4866 } 4867 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4868 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4869 return -EINVAL; 4870 } 4871 if (is_vlan_dev(upper_dev) && 4872 vlan_dev_vlan_id(upper_dev) == 1) { 4873 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic"); 4874 return -EINVAL; 4875 } 4876 break; 4877 case NETDEV_CHANGEUPPER: 4878 upper_dev = info->upper_dev; 4879 if (netif_is_bridge_master(upper_dev)) { 4880 if (info->linking) 4881 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4882 lower_dev, 4883 upper_dev, 4884 extack); 4885 else 4886 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4887 lower_dev, 4888 upper_dev); 4889 } else if (netif_is_lag_master(upper_dev)) { 4890 if (info->linking) 4891 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4892 upper_dev); 4893 else 4894 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4895 upper_dev); 4896 } else if (netif_is_ovs_master(upper_dev)) { 4897 if (info->linking) 4898 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4899 else 4900 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4901 } else if (netif_is_macvlan(upper_dev)) { 4902 if (!info->linking) 4903 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4904 } 4905 break; 4906 } 4907 4908 return err; 4909 } 4910 4911 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4912 unsigned long event, void *ptr) 4913 { 4914 struct netdev_notifier_changelowerstate_info *info; 4915 struct mlxsw_sp_port *mlxsw_sp_port; 4916 int err; 4917 4918 mlxsw_sp_port = netdev_priv(dev); 4919 info = ptr; 4920 4921 switch (event) { 4922 case NETDEV_CHANGELOWERSTATE: 4923 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4924 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4925 info->lower_state_info); 4926 if (err) 4927 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4928 } 4929 break; 4930 } 4931 4932 return 0; 4933 } 4934 4935 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4936 struct net_device *port_dev, 4937 unsigned long event, void *ptr) 4938 { 4939 switch (event) { 4940 case NETDEV_PRECHANGEUPPER: 4941 case NETDEV_CHANGEUPPER: 4942 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4943 event, ptr); 4944 case NETDEV_CHANGELOWERSTATE: 4945 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4946 ptr); 4947 } 4948 4949 return 0; 4950 } 4951 4952 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4953 unsigned long event, void *ptr) 4954 { 4955 struct net_device *dev; 4956 struct list_head *iter; 4957 int ret; 4958 4959 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4960 if (mlxsw_sp_port_dev_check(dev)) { 4961 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4962 ptr); 4963 if (ret) 4964 return ret; 4965 } 4966 } 4967 4968 return 0; 4969 } 4970 4971 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4972 struct net_device *dev, 4973 unsigned long event, void *ptr, 4974 u16 vid) 4975 { 4976 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4977 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4978 struct netdev_notifier_changeupper_info *info = ptr; 4979 struct netlink_ext_ack *extack; 4980 struct net_device *upper_dev; 4981 int err = 0; 4982 4983 extack = netdev_notifier_info_to_extack(&info->info); 4984 4985 switch (event) { 4986 case NETDEV_PRECHANGEUPPER: 4987 upper_dev = info->upper_dev; 4988 if (!netif_is_bridge_master(upper_dev) && 4989 !netif_is_macvlan(upper_dev)) { 4990 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4991 return -EINVAL; 4992 } 4993 if (!info->linking) 4994 break; 4995 if (netif_is_bridge_master(upper_dev) && 4996 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4997 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4998 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4999 return -EOPNOTSUPP; 5000 if (netdev_has_any_upper_dev(upper_dev) && 5001 (!netif_is_bridge_master(upper_dev) || 5002 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 5003 upper_dev))) { 5004 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 5005 return -EINVAL; 5006 } 5007 if (netif_is_macvlan(upper_dev) && 5008 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) { 5009 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 5010 return -EOPNOTSUPP; 5011 } 5012 break; 5013 case NETDEV_CHANGEUPPER: 5014 upper_dev = info->upper_dev; 5015 if (netif_is_bridge_master(upper_dev)) { 5016 if (info->linking) 5017 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 5018 vlan_dev, 5019 upper_dev, 5020 extack); 5021 else 5022 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 5023 vlan_dev, 5024 upper_dev); 5025 } else if (netif_is_macvlan(upper_dev)) { 5026 if (!info->linking) 5027 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5028 } else { 5029 err = -EINVAL; 5030 WARN_ON(1); 5031 } 5032 break; 5033 } 5034 5035 return err; 5036 } 5037 5038 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 5039 struct net_device *lag_dev, 5040 unsigned long event, 5041 void *ptr, u16 vid) 5042 { 5043 struct net_device *dev; 5044 struct list_head *iter; 5045 int ret; 5046 5047 netdev_for_each_lower_dev(lag_dev, dev, iter) { 5048 if (mlxsw_sp_port_dev_check(dev)) { 5049 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 5050 event, ptr, 5051 vid); 5052 if (ret) 5053 return ret; 5054 } 5055 } 5056 5057 return 0; 5058 } 5059 5060 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 5061 unsigned long event, void *ptr) 5062 { 5063 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 5064 u16 vid = vlan_dev_vlan_id(vlan_dev); 5065 5066 if (mlxsw_sp_port_dev_check(real_dev)) 5067 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 5068 event, ptr, vid); 5069 else if (netif_is_lag_master(real_dev)) 5070 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 5071 real_dev, event, 5072 ptr, vid); 5073 5074 return 0; 5075 } 5076 5077 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 5078 unsigned long event, void *ptr) 5079 { 5080 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 5081 struct netdev_notifier_changeupper_info *info = ptr; 5082 struct netlink_ext_ack *extack; 5083 struct net_device *upper_dev; 5084 5085 if (!mlxsw_sp) 5086 return 0; 5087 5088 extack = netdev_notifier_info_to_extack(&info->info); 5089 5090 switch (event) { 5091 case NETDEV_PRECHANGEUPPER: 5092 upper_dev = info->upper_dev; 5093 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) { 5094 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5095 return -EOPNOTSUPP; 5096 } 5097 if (!info->linking) 5098 break; 5099 if (netif_is_macvlan(upper_dev) && 5100 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) { 5101 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 5102 return -EOPNOTSUPP; 5103 } 5104 break; 5105 case NETDEV_CHANGEUPPER: 5106 upper_dev = info->upper_dev; 5107 if (info->linking) 5108 break; 5109 if (is_vlan_dev(upper_dev)) 5110 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 5111 if (netif_is_macvlan(upper_dev)) 5112 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5113 break; 5114 } 5115 5116 return 0; 5117 } 5118 5119 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 5120 unsigned long event, void *ptr) 5121 { 5122 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 5123 struct netdev_notifier_changeupper_info *info = ptr; 5124 struct netlink_ext_ack *extack; 5125 5126 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 5127 return 0; 5128 5129 extack = netdev_notifier_info_to_extack(&info->info); 5130 5131 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */ 5132 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5133 5134 return -EOPNOTSUPP; 5135 } 5136 5137 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 5138 { 5139 struct netdev_notifier_changeupper_info *info = ptr; 5140 5141 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 5142 return false; 5143 return netif_is_l3_master(info->upper_dev); 5144 } 5145 5146 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 5147 struct net_device *dev, 5148 unsigned long event, void *ptr) 5149 { 5150 struct netdev_notifier_changeupper_info *cu_info; 5151 struct netdev_notifier_info *info = ptr; 5152 struct netlink_ext_ack *extack; 5153 struct net_device *upper_dev; 5154 5155 extack = netdev_notifier_info_to_extack(info); 5156 5157 switch (event) { 5158 case NETDEV_CHANGEUPPER: 5159 cu_info = container_of(info, 5160 struct netdev_notifier_changeupper_info, 5161 info); 5162 upper_dev = cu_info->upper_dev; 5163 if (!netif_is_bridge_master(upper_dev)) 5164 return 0; 5165 if (!mlxsw_sp_lower_get(upper_dev)) 5166 return 0; 5167 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5168 return -EOPNOTSUPP; 5169 if (cu_info->linking) { 5170 if (!netif_running(dev)) 5171 return 0; 5172 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 5173 dev, extack); 5174 } else { 5175 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev); 5176 } 5177 break; 5178 case NETDEV_PRE_UP: 5179 upper_dev = netdev_master_upper_dev_get(dev); 5180 if (!upper_dev) 5181 return 0; 5182 if (!netif_is_bridge_master(upper_dev)) 5183 return 0; 5184 if (!mlxsw_sp_lower_get(upper_dev)) 5185 return 0; 5186 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 5187 extack); 5188 case NETDEV_DOWN: 5189 upper_dev = netdev_master_upper_dev_get(dev); 5190 if (!upper_dev) 5191 return 0; 5192 if (!netif_is_bridge_master(upper_dev)) 5193 return 0; 5194 if (!mlxsw_sp_lower_get(upper_dev)) 5195 return 0; 5196 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev); 5197 break; 5198 } 5199 5200 return 0; 5201 } 5202 5203 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 5204 unsigned long event, void *ptr) 5205 { 5206 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 5207 struct mlxsw_sp_span_entry *span_entry; 5208 struct mlxsw_sp *mlxsw_sp; 5209 int err = 0; 5210 5211 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 5212 if (event == NETDEV_UNREGISTER) { 5213 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 5214 if (span_entry) 5215 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 5216 } 5217 mlxsw_sp_span_respin(mlxsw_sp); 5218 5219 if (netif_is_vxlan(dev)) 5220 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 5221 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 5222 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 5223 event, ptr); 5224 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 5225 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 5226 event, ptr); 5227 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU) 5228 err = mlxsw_sp_netdevice_router_port_event(dev); 5229 else if (mlxsw_sp_is_vrf_event(event, ptr)) 5230 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 5231 else if (mlxsw_sp_port_dev_check(dev)) 5232 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 5233 else if (netif_is_lag_master(dev)) 5234 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 5235 else if (is_vlan_dev(dev)) 5236 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 5237 else if (netif_is_bridge_master(dev)) 5238 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 5239 else if (netif_is_macvlan(dev)) 5240 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 5241 5242 return notifier_from_errno(err); 5243 } 5244 5245 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 5246 .notifier_call = mlxsw_sp_inetaddr_valid_event, 5247 }; 5248 5249 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = { 5250 .notifier_call = mlxsw_sp_inetaddr_event, 5251 }; 5252 5253 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 5254 .notifier_call = mlxsw_sp_inet6addr_valid_event, 5255 }; 5256 5257 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = { 5258 .notifier_call = mlxsw_sp_inet6addr_event, 5259 }; 5260 5261 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 5262 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 5263 {0, }, 5264 }; 5265 5266 static struct pci_driver mlxsw_sp1_pci_driver = { 5267 .name = mlxsw_sp1_driver_name, 5268 .id_table = mlxsw_sp1_pci_id_table, 5269 }; 5270 5271 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 5272 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 5273 {0, }, 5274 }; 5275 5276 static struct pci_driver mlxsw_sp2_pci_driver = { 5277 .name = mlxsw_sp2_driver_name, 5278 .id_table = mlxsw_sp2_pci_id_table, 5279 }; 5280 5281 static int __init mlxsw_sp_module_init(void) 5282 { 5283 int err; 5284 5285 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5286 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5287 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5288 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5289 5290 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5291 if (err) 5292 goto err_sp1_core_driver_register; 5293 5294 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5295 if (err) 5296 goto err_sp2_core_driver_register; 5297 5298 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5299 if (err) 5300 goto err_sp1_pci_driver_register; 5301 5302 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5303 if (err) 5304 goto err_sp2_pci_driver_register; 5305 5306 return 0; 5307 5308 err_sp2_pci_driver_register: 5309 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5310 err_sp1_pci_driver_register: 5311 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5312 err_sp2_core_driver_register: 5313 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5314 err_sp1_core_driver_register: 5315 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5316 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5317 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5318 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5319 return err; 5320 } 5321 5322 static void __exit mlxsw_sp_module_exit(void) 5323 { 5324 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5325 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5326 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5327 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5328 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5329 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5330 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5331 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5332 } 5333 5334 module_init(mlxsw_sp_module_init); 5335 module_exit(mlxsw_sp_module_exit); 5336 5337 MODULE_LICENSE("Dual BSD/GPL"); 5338 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5339 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5340 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5341 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5342 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5343