1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/jhash.h> 25 #include <linux/log2.h> 26 #include <linux/refcount.h> 27 #include <linux/rhashtable.h> 28 #include <net/switchdev.h> 29 #include <net/pkt_cls.h> 30 #include <net/netevent.h> 31 #include <net/addrconf.h> 32 33 #include "spectrum.h" 34 #include "pci.h" 35 #include "core.h" 36 #include "core_env.h" 37 #include "reg.h" 38 #include "port.h" 39 #include "trap.h" 40 #include "txheader.h" 41 #include "spectrum_cnt.h" 42 #include "spectrum_dpipe.h" 43 #include "spectrum_acl_flex_actions.h" 44 #include "spectrum_span.h" 45 #include "spectrum_ptp.h" 46 #include "spectrum_trap.h" 47 48 #define MLXSW_SP1_FWREV_MAJOR 13 49 #define MLXSW_SP1_FWREV_MINOR 2010 50 #define MLXSW_SP1_FWREV_SUBMINOR 1006 51 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 52 53 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 54 .major = MLXSW_SP1_FWREV_MAJOR, 55 .minor = MLXSW_SP1_FWREV_MINOR, 56 .subminor = MLXSW_SP1_FWREV_SUBMINOR, 57 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 58 }; 59 60 #define MLXSW_SP1_FW_FILENAME \ 61 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 62 "." __stringify(MLXSW_SP1_FWREV_MINOR) \ 63 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2" 64 65 #define MLXSW_SP2_FWREV_MAJOR 29 66 #define MLXSW_SP2_FWREV_MINOR 2010 67 #define MLXSW_SP2_FWREV_SUBMINOR 1006 68 69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = { 70 .major = MLXSW_SP2_FWREV_MAJOR, 71 .minor = MLXSW_SP2_FWREV_MINOR, 72 .subminor = MLXSW_SP2_FWREV_SUBMINOR, 73 }; 74 75 #define MLXSW_SP2_FW_FILENAME \ 76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \ 77 "." __stringify(MLXSW_SP2_FWREV_MINOR) \ 78 "." __stringify(MLXSW_SP2_FWREV_SUBMINOR) ".mfa2" 79 80 #define MLXSW_SP3_FWREV_MAJOR 30 81 #define MLXSW_SP3_FWREV_MINOR 2010 82 #define MLXSW_SP3_FWREV_SUBMINOR 1006 83 84 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = { 85 .major = MLXSW_SP3_FWREV_MAJOR, 86 .minor = MLXSW_SP3_FWREV_MINOR, 87 .subminor = MLXSW_SP3_FWREV_SUBMINOR, 88 }; 89 90 #define MLXSW_SP3_FW_FILENAME \ 91 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \ 92 "." __stringify(MLXSW_SP3_FWREV_MINOR) \ 93 "." __stringify(MLXSW_SP3_FWREV_SUBMINOR) ".mfa2" 94 95 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 96 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 97 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3"; 98 static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4"; 99 100 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = { 101 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00 102 }; 103 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = { 104 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00 105 }; 106 107 /* tx_hdr_version 108 * Tx header version. 109 * Must be set to 1. 110 */ 111 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 112 113 /* tx_hdr_ctl 114 * Packet control type. 115 * 0 - Ethernet control (e.g. EMADs, LACP) 116 * 1 - Ethernet data 117 */ 118 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 119 120 /* tx_hdr_proto 121 * Packet protocol type. Must be set to 1 (Ethernet). 122 */ 123 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 124 125 /* tx_hdr_rx_is_router 126 * Packet is sent from the router. Valid for data packets only. 127 */ 128 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 129 130 /* tx_hdr_fid_valid 131 * Indicates if the 'fid' field is valid and should be used for 132 * forwarding lookup. Valid for data packets only. 133 */ 134 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 135 136 /* tx_hdr_swid 137 * Switch partition ID. Must be set to 0. 138 */ 139 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 140 141 /* tx_hdr_control_tclass 142 * Indicates if the packet should use the control TClass and not one 143 * of the data TClasses. 144 */ 145 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 146 147 /* tx_hdr_etclass 148 * Egress TClass to be used on the egress device on the egress port. 149 */ 150 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 151 152 /* tx_hdr_port_mid 153 * Destination local port for unicast packets. 154 * Destination multicast ID for multicast packets. 155 * 156 * Control packets are directed to a specific egress port, while data 157 * packets are transmitted through the CPU port (0) into the switch partition, 158 * where forwarding rules are applied. 159 */ 160 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 161 162 /* tx_hdr_fid 163 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 164 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 165 * Valid for data packets only. 166 */ 167 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 168 169 /* tx_hdr_type 170 * 0 - Data packets 171 * 6 - Control packets 172 */ 173 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 174 175 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 176 unsigned int counter_index, u64 *packets, 177 u64 *bytes) 178 { 179 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 180 int err; 181 182 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 183 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 185 if (err) 186 return err; 187 if (packets) 188 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 189 if (bytes) 190 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 191 return 0; 192 } 193 194 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 195 unsigned int counter_index) 196 { 197 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 198 199 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 200 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 201 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 202 } 203 204 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 205 unsigned int *p_counter_index) 206 { 207 int err; 208 209 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 210 p_counter_index); 211 if (err) 212 return err; 213 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 214 if (err) 215 goto err_counter_clear; 216 return 0; 217 218 err_counter_clear: 219 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 220 *p_counter_index); 221 return err; 222 } 223 224 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 225 unsigned int counter_index) 226 { 227 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 228 counter_index); 229 } 230 231 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 232 const struct mlxsw_tx_info *tx_info) 233 { 234 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 235 236 memset(txhdr, 0, MLXSW_TXHDR_LEN); 237 238 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 239 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 240 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 241 mlxsw_tx_hdr_swid_set(txhdr, 0); 242 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 243 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 244 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 245 } 246 247 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 248 { 249 switch (state) { 250 case BR_STATE_FORWARDING: 251 return MLXSW_REG_SPMS_STATE_FORWARDING; 252 case BR_STATE_LEARNING: 253 return MLXSW_REG_SPMS_STATE_LEARNING; 254 case BR_STATE_LISTENING: 255 case BR_STATE_DISABLED: 256 case BR_STATE_BLOCKING: 257 return MLXSW_REG_SPMS_STATE_DISCARDING; 258 default: 259 BUG(); 260 } 261 } 262 263 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 264 u8 state) 265 { 266 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 268 char *spms_pl; 269 int err; 270 271 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 272 if (!spms_pl) 273 return -ENOMEM; 274 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 275 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 276 277 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 278 kfree(spms_pl); 279 return err; 280 } 281 282 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 283 { 284 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 285 int err; 286 287 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 288 if (err) 289 return err; 290 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 291 return 0; 292 } 293 294 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 295 bool is_up) 296 { 297 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 298 char paos_pl[MLXSW_REG_PAOS_LEN]; 299 300 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 301 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 302 MLXSW_PORT_ADMIN_STATUS_DOWN); 303 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 304 } 305 306 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 307 const unsigned char *addr) 308 { 309 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 310 char ppad_pl[MLXSW_REG_PPAD_LEN]; 311 312 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 313 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 315 } 316 317 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 318 { 319 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 320 321 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac, 322 mlxsw_sp_port->local_port); 323 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, 324 mlxsw_sp_port->dev->dev_addr); 325 } 326 327 static int mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port *mlxsw_sp_port, int *p_max_mtu) 328 { 329 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 330 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 331 int err; 332 333 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 334 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 335 if (err) 336 return err; 337 338 *p_max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 339 return 0; 340 } 341 342 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 343 { 344 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 345 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 346 347 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 348 if (mtu > mlxsw_sp_port->max_mtu) 349 return -EINVAL; 350 351 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 352 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 353 } 354 355 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, 356 u16 local_port, u8 swid) 357 { 358 char pspa_pl[MLXSW_REG_PSPA_LEN]; 359 360 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port); 361 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 362 } 363 364 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 365 { 366 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 367 char svpe_pl[MLXSW_REG_SVPE_LEN]; 368 369 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 370 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 371 } 372 373 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 374 bool learn_enable) 375 { 376 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 377 char *spvmlr_pl; 378 int err; 379 380 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 381 if (!spvmlr_pl) 382 return -ENOMEM; 383 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 384 learn_enable); 385 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 386 kfree(spvmlr_pl); 387 return err; 388 } 389 390 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type) 391 { 392 switch (ethtype) { 393 case ETH_P_8021Q: 394 *p_sver_type = 0; 395 break; 396 case ETH_P_8021AD: 397 *p_sver_type = 1; 398 break; 399 default: 400 return -EINVAL; 401 } 402 403 return 0; 404 } 405 406 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port, 407 u16 ethtype) 408 { 409 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 410 char spevet_pl[MLXSW_REG_SPEVET_LEN]; 411 u8 sver_type; 412 int err; 413 414 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 415 if (err) 416 return err; 417 418 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type); 419 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl); 420 } 421 422 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 423 u16 vid, u16 ethtype) 424 { 425 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 426 char spvid_pl[MLXSW_REG_SPVID_LEN]; 427 u8 sver_type; 428 int err; 429 430 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 431 if (err) 432 return err; 433 434 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid, 435 sver_type); 436 437 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 438 } 439 440 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 441 bool allow) 442 { 443 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 444 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 445 446 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 447 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 448 } 449 450 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 451 u16 ethtype) 452 { 453 int err; 454 455 if (!vid) { 456 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 457 if (err) 458 return err; 459 } else { 460 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype); 461 if (err) 462 return err; 463 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 464 if (err) 465 goto err_port_allow_untagged_set; 466 } 467 468 mlxsw_sp_port->pvid = vid; 469 return 0; 470 471 err_port_allow_untagged_set: 472 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype); 473 return err; 474 } 475 476 static int 477 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 478 { 479 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 480 char sspr_pl[MLXSW_REG_SSPR_LEN]; 481 482 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 483 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 484 } 485 486 static int 487 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port, 488 struct mlxsw_sp_port_mapping *port_mapping) 489 { 490 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 491 bool separate_rxtx; 492 u8 module; 493 u8 width; 494 int err; 495 int i; 496 497 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 498 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 499 if (err) 500 return err; 501 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 502 width = mlxsw_reg_pmlp_width_get(pmlp_pl); 503 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl); 504 505 if (width && !is_power_of_2(width)) { 506 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n", 507 local_port); 508 return -EINVAL; 509 } 510 511 for (i = 0; i < width; i++) { 512 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) { 513 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n", 514 local_port); 515 return -EINVAL; 516 } 517 if (separate_rxtx && 518 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != 519 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) { 520 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n", 521 local_port); 522 return -EINVAL; 523 } 524 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i) { 525 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n", 526 local_port); 527 return -EINVAL; 528 } 529 } 530 531 port_mapping->module = module; 532 port_mapping->width = width; 533 port_mapping->module_width = width; 534 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 535 return 0; 536 } 537 538 static int 539 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port, 540 const struct mlxsw_sp_port_mapping *port_mapping) 541 { 542 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 543 int i, err; 544 545 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->module); 546 547 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 548 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width); 549 for (i = 0; i < port_mapping->width; i++) { 550 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module); 551 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */ 552 } 553 554 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 555 if (err) 556 goto err_pmlp_write; 557 return 0; 558 559 err_pmlp_write: 560 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->module); 561 return err; 562 } 563 564 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port, 565 u8 module) 566 { 567 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 568 569 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 570 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 571 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 572 mlxsw_env_module_port_unmap(mlxsw_sp->core, module); 573 } 574 575 static int mlxsw_sp_port_open(struct net_device *dev) 576 { 577 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 578 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 579 int err; 580 581 err = mlxsw_env_module_port_up(mlxsw_sp->core, 582 mlxsw_sp_port->mapping.module); 583 if (err) 584 return err; 585 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 586 if (err) 587 goto err_port_admin_status_set; 588 netif_start_queue(dev); 589 return 0; 590 591 err_port_admin_status_set: 592 mlxsw_env_module_port_down(mlxsw_sp->core, 593 mlxsw_sp_port->mapping.module); 594 return err; 595 } 596 597 static int mlxsw_sp_port_stop(struct net_device *dev) 598 { 599 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 600 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 601 602 netif_stop_queue(dev); 603 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 604 mlxsw_env_module_port_down(mlxsw_sp->core, 605 mlxsw_sp_port->mapping.module); 606 return 0; 607 } 608 609 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 610 struct net_device *dev) 611 { 612 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 613 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 614 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 615 const struct mlxsw_tx_info tx_info = { 616 .local_port = mlxsw_sp_port->local_port, 617 .is_emad = false, 618 }; 619 u64 len; 620 int err; 621 622 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) { 623 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 624 dev_kfree_skb_any(skb); 625 return NETDEV_TX_OK; 626 } 627 628 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb)); 629 630 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 631 return NETDEV_TX_BUSY; 632 633 if (eth_skb_pad(skb)) { 634 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 635 return NETDEV_TX_OK; 636 } 637 638 mlxsw_sp_txhdr_construct(skb, &tx_info); 639 /* TX header is consumed by HW on the way so we shouldn't count its 640 * bytes as being sent. 641 */ 642 len = skb->len - MLXSW_TXHDR_LEN; 643 644 /* Due to a race we might fail here because of a full queue. In that 645 * unlikely case we simply drop the packet. 646 */ 647 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 648 649 if (!err) { 650 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 651 u64_stats_update_begin(&pcpu_stats->syncp); 652 pcpu_stats->tx_packets++; 653 pcpu_stats->tx_bytes += len; 654 u64_stats_update_end(&pcpu_stats->syncp); 655 } else { 656 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 657 dev_kfree_skb_any(skb); 658 } 659 return NETDEV_TX_OK; 660 } 661 662 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 663 { 664 } 665 666 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 667 { 668 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 669 struct sockaddr *addr = p; 670 int err; 671 672 if (!is_valid_ether_addr(addr->sa_data)) 673 return -EADDRNOTAVAIL; 674 675 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 676 if (err) 677 return err; 678 eth_hw_addr_set(dev, addr->sa_data); 679 return 0; 680 } 681 682 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 683 { 684 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 685 struct mlxsw_sp_hdroom orig_hdroom; 686 struct mlxsw_sp_hdroom hdroom; 687 int err; 688 689 orig_hdroom = *mlxsw_sp_port->hdroom; 690 691 hdroom = orig_hdroom; 692 hdroom.mtu = mtu; 693 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom); 694 695 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom); 696 if (err) { 697 netdev_err(dev, "Failed to configure port's headroom\n"); 698 return err; 699 } 700 701 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 702 if (err) 703 goto err_port_mtu_set; 704 dev->mtu = mtu; 705 return 0; 706 707 err_port_mtu_set: 708 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom); 709 return err; 710 } 711 712 static int 713 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 714 struct rtnl_link_stats64 *stats) 715 { 716 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 717 struct mlxsw_sp_port_pcpu_stats *p; 718 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 719 u32 tx_dropped = 0; 720 unsigned int start; 721 int i; 722 723 for_each_possible_cpu(i) { 724 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 725 do { 726 start = u64_stats_fetch_begin_irq(&p->syncp); 727 rx_packets = p->rx_packets; 728 rx_bytes = p->rx_bytes; 729 tx_packets = p->tx_packets; 730 tx_bytes = p->tx_bytes; 731 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 732 733 stats->rx_packets += rx_packets; 734 stats->rx_bytes += rx_bytes; 735 stats->tx_packets += tx_packets; 736 stats->tx_bytes += tx_bytes; 737 /* tx_dropped is u32, updated without syncp protection. */ 738 tx_dropped += p->tx_dropped; 739 } 740 stats->tx_dropped = tx_dropped; 741 return 0; 742 } 743 744 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 745 { 746 switch (attr_id) { 747 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 748 return true; 749 } 750 751 return false; 752 } 753 754 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 755 void *sp) 756 { 757 switch (attr_id) { 758 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 759 return mlxsw_sp_port_get_sw_stats64(dev, sp); 760 } 761 762 return -EINVAL; 763 } 764 765 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 766 int prio, char *ppcnt_pl) 767 { 768 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 769 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 770 771 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 772 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 773 } 774 775 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 776 struct rtnl_link_stats64 *stats) 777 { 778 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 779 int err; 780 781 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 782 0, ppcnt_pl); 783 if (err) 784 goto out; 785 786 stats->tx_packets = 787 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 788 stats->rx_packets = 789 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 790 stats->tx_bytes = 791 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 792 stats->rx_bytes = 793 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 794 stats->multicast = 795 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 796 797 stats->rx_crc_errors = 798 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 799 stats->rx_frame_errors = 800 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 801 802 stats->rx_length_errors = ( 803 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 804 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 805 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 806 807 stats->rx_errors = (stats->rx_crc_errors + 808 stats->rx_frame_errors + stats->rx_length_errors); 809 810 out: 811 return err; 812 } 813 814 static void 815 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 816 struct mlxsw_sp_port_xstats *xstats) 817 { 818 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 819 int err, i; 820 821 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 822 ppcnt_pl); 823 if (!err) 824 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 825 826 for (i = 0; i < TC_MAX_QUEUE; i++) { 827 err = mlxsw_sp_port_get_stats_raw(dev, 828 MLXSW_REG_PPCNT_TC_CONG_CNT, 829 i, ppcnt_pl); 830 if (err) 831 goto tc_cnt; 832 833 xstats->wred_drop[i] = 834 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 835 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl); 836 837 tc_cnt: 838 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 839 i, ppcnt_pl); 840 if (err) 841 continue; 842 843 xstats->backlog[i] = 844 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 845 xstats->tail_drop[i] = 846 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 847 } 848 849 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 850 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 851 i, ppcnt_pl); 852 if (err) 853 continue; 854 855 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 856 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 857 } 858 } 859 860 static void update_stats_cache(struct work_struct *work) 861 { 862 struct mlxsw_sp_port *mlxsw_sp_port = 863 container_of(work, struct mlxsw_sp_port, 864 periodic_hw_stats.update_dw.work); 865 866 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 867 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as 868 * necessary when port goes down. 869 */ 870 goto out; 871 872 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 873 &mlxsw_sp_port->periodic_hw_stats.stats); 874 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 875 &mlxsw_sp_port->periodic_hw_stats.xstats); 876 877 out: 878 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 879 MLXSW_HW_STATS_UPDATE_TIME); 880 } 881 882 /* Return the stats from a cache that is updated periodically, 883 * as this function might get called in an atomic context. 884 */ 885 static void 886 mlxsw_sp_port_get_stats64(struct net_device *dev, 887 struct rtnl_link_stats64 *stats) 888 { 889 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 890 891 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 892 } 893 894 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 895 u16 vid_begin, u16 vid_end, 896 bool is_member, bool untagged) 897 { 898 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 899 char *spvm_pl; 900 int err; 901 902 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 903 if (!spvm_pl) 904 return -ENOMEM; 905 906 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 907 vid_end, is_member, untagged); 908 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 909 kfree(spvm_pl); 910 return err; 911 } 912 913 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 914 u16 vid_end, bool is_member, bool untagged) 915 { 916 u16 vid, vid_e; 917 int err; 918 919 for (vid = vid_begin; vid <= vid_end; 920 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 921 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 922 vid_end); 923 924 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 925 is_member, untagged); 926 if (err) 927 return err; 928 } 929 930 return 0; 931 } 932 933 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port, 934 bool flush_default) 935 { 936 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 937 938 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 939 &mlxsw_sp_port->vlans_list, list) { 940 if (!flush_default && 941 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID) 942 continue; 943 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 944 } 945 } 946 947 static void 948 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 949 { 950 if (mlxsw_sp_port_vlan->bridge_port) 951 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 952 else if (mlxsw_sp_port_vlan->fid) 953 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 954 } 955 956 struct mlxsw_sp_port_vlan * 957 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 958 { 959 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 960 bool untagged = vid == MLXSW_SP_DEFAULT_VID; 961 int err; 962 963 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 964 if (mlxsw_sp_port_vlan) 965 return ERR_PTR(-EEXIST); 966 967 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 968 if (err) 969 return ERR_PTR(err); 970 971 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 972 if (!mlxsw_sp_port_vlan) { 973 err = -ENOMEM; 974 goto err_port_vlan_alloc; 975 } 976 977 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 978 mlxsw_sp_port_vlan->vid = vid; 979 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 980 981 return mlxsw_sp_port_vlan; 982 983 err_port_vlan_alloc: 984 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 985 return ERR_PTR(err); 986 } 987 988 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 989 { 990 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 991 u16 vid = mlxsw_sp_port_vlan->vid; 992 993 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan); 994 list_del(&mlxsw_sp_port_vlan->list); 995 kfree(mlxsw_sp_port_vlan); 996 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 997 } 998 999 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1000 __be16 __always_unused proto, u16 vid) 1001 { 1002 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1003 1004 /* VLAN 0 is added to HW filter when device goes up, but it is 1005 * reserved in our case, so simply return. 1006 */ 1007 if (!vid) 1008 return 0; 1009 1010 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid)); 1011 } 1012 1013 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1014 __be16 __always_unused proto, u16 vid) 1015 { 1016 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1017 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1018 1019 /* VLAN 0 is removed from HW filter when device goes down, but 1020 * it is reserved in our case, so simply return. 1021 */ 1022 if (!vid) 1023 return 0; 1024 1025 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1026 if (!mlxsw_sp_port_vlan) 1027 return 0; 1028 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1029 1030 return 0; 1031 } 1032 1033 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1034 struct flow_block_offload *f) 1035 { 1036 switch (f->binder_type) { 1037 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS: 1038 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true); 1039 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS: 1040 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false); 1041 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP: 1042 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f); 1043 case FLOW_BLOCK_BINDER_TYPE_RED_MARK: 1044 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f); 1045 default: 1046 return -EOPNOTSUPP; 1047 } 1048 } 1049 1050 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1051 void *type_data) 1052 { 1053 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1054 1055 switch (type) { 1056 case TC_SETUP_BLOCK: 1057 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1058 case TC_SETUP_QDISC_RED: 1059 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1060 case TC_SETUP_QDISC_PRIO: 1061 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1062 case TC_SETUP_QDISC_ETS: 1063 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data); 1064 case TC_SETUP_QDISC_TBF: 1065 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data); 1066 case TC_SETUP_QDISC_FIFO: 1067 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data); 1068 default: 1069 return -EOPNOTSUPP; 1070 } 1071 } 1072 1073 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1074 { 1075 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1076 1077 if (!enable) { 1078 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) || 1079 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) { 1080 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1081 return -EINVAL; 1082 } 1083 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block); 1084 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block); 1085 } else { 1086 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block); 1087 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block); 1088 } 1089 return 0; 1090 } 1091 1092 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable) 1093 { 1094 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1095 char pplr_pl[MLXSW_REG_PPLR_LEN]; 1096 int err; 1097 1098 if (netif_running(dev)) 1099 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1100 1101 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable); 1102 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr), 1103 pplr_pl); 1104 1105 if (netif_running(dev)) 1106 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 1107 1108 return err; 1109 } 1110 1111 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1112 1113 static int mlxsw_sp_handle_feature(struct net_device *dev, 1114 netdev_features_t wanted_features, 1115 netdev_features_t feature, 1116 mlxsw_sp_feature_handler feature_handler) 1117 { 1118 netdev_features_t changes = wanted_features ^ dev->features; 1119 bool enable = !!(wanted_features & feature); 1120 int err; 1121 1122 if (!(changes & feature)) 1123 return 0; 1124 1125 err = feature_handler(dev, enable); 1126 if (err) { 1127 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1128 enable ? "Enable" : "Disable", &feature, err); 1129 return err; 1130 } 1131 1132 if (enable) 1133 dev->features |= feature; 1134 else 1135 dev->features &= ~feature; 1136 1137 return 0; 1138 } 1139 static int mlxsw_sp_set_features(struct net_device *dev, 1140 netdev_features_t features) 1141 { 1142 netdev_features_t oper_features = dev->features; 1143 int err = 0; 1144 1145 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1146 mlxsw_sp_feature_hw_tc); 1147 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK, 1148 mlxsw_sp_feature_loopback); 1149 1150 if (err) { 1151 dev->features = oper_features; 1152 return -EINVAL; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static struct devlink_port * 1159 mlxsw_sp_port_get_devlink_port(struct net_device *dev) 1160 { 1161 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1162 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1163 1164 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core, 1165 mlxsw_sp_port->local_port); 1166 } 1167 1168 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port, 1169 struct ifreq *ifr) 1170 { 1171 struct hwtstamp_config config; 1172 int err; 1173 1174 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1175 return -EFAULT; 1176 1177 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, 1178 &config); 1179 if (err) 1180 return err; 1181 1182 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 1183 return -EFAULT; 1184 1185 return 0; 1186 } 1187 1188 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port, 1189 struct ifreq *ifr) 1190 { 1191 struct hwtstamp_config config; 1192 int err; 1193 1194 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port, 1195 &config); 1196 if (err) 1197 return err; 1198 1199 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 1200 return -EFAULT; 1201 1202 return 0; 1203 } 1204 1205 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port) 1206 { 1207 struct hwtstamp_config config = {0}; 1208 1209 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config); 1210 } 1211 1212 static int 1213 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1214 { 1215 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1216 1217 switch (cmd) { 1218 case SIOCSHWTSTAMP: 1219 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr); 1220 case SIOCGHWTSTAMP: 1221 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr); 1222 default: 1223 return -EOPNOTSUPP; 1224 } 1225 } 1226 1227 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1228 .ndo_open = mlxsw_sp_port_open, 1229 .ndo_stop = mlxsw_sp_port_stop, 1230 .ndo_start_xmit = mlxsw_sp_port_xmit, 1231 .ndo_setup_tc = mlxsw_sp_setup_tc, 1232 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1233 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1234 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1235 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1236 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1237 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1238 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1239 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1240 .ndo_set_features = mlxsw_sp_set_features, 1241 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port, 1242 .ndo_eth_ioctl = mlxsw_sp_port_ioctl, 1243 }; 1244 1245 static int 1246 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port) 1247 { 1248 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1249 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper; 1250 const struct mlxsw_sp_port_type_speed_ops *ops; 1251 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1252 u32 eth_proto_cap_masked; 1253 int err; 1254 1255 ops = mlxsw_sp->port_type_speed_ops; 1256 1257 /* Set advertised speeds to speeds supported by both the driver 1258 * and the device. 1259 */ 1260 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1261 0, false); 1262 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1263 if (err) 1264 return err; 1265 1266 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, 1267 ð_proto_admin, ð_proto_oper); 1268 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap); 1269 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1270 eth_proto_cap_masked, 1271 mlxsw_sp_port->link.autoneg); 1272 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1273 } 1274 1275 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed) 1276 { 1277 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops; 1278 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1279 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1280 u32 eth_proto_oper; 1281 int err; 1282 1283 port_type_speed_ops = mlxsw_sp->port_type_speed_ops; 1284 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, 1285 mlxsw_sp_port->local_port, 0, 1286 false); 1287 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1288 if (err) 1289 return err; 1290 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL, 1291 ð_proto_oper); 1292 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper); 1293 return 0; 1294 } 1295 1296 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 1297 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 1298 bool dwrr, u8 dwrr_weight) 1299 { 1300 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1301 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1302 1303 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1304 next_index); 1305 mlxsw_reg_qeec_de_set(qeec_pl, true); 1306 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 1307 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 1308 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1309 } 1310 1311 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 1312 enum mlxsw_reg_qeec_hr hr, u8 index, 1313 u8 next_index, u32 maxrate, u8 burst_size) 1314 { 1315 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1316 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1317 1318 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1319 next_index); 1320 mlxsw_reg_qeec_mase_set(qeec_pl, true); 1321 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 1322 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size); 1323 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1324 } 1325 1326 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 1327 enum mlxsw_reg_qeec_hr hr, u8 index, 1328 u8 next_index, u32 minrate) 1329 { 1330 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1331 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1332 1333 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1334 next_index); 1335 mlxsw_reg_qeec_mise_set(qeec_pl, true); 1336 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 1337 1338 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1339 } 1340 1341 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 1342 u8 switch_prio, u8 tclass) 1343 { 1344 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1345 char qtct_pl[MLXSW_REG_QTCT_LEN]; 1346 1347 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 1348 tclass); 1349 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 1350 } 1351 1352 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 1353 { 1354 int err, i; 1355 1356 /* Setup the elements hierarcy, so that each TC is linked to 1357 * one subgroup, which are all member in the same group. 1358 */ 1359 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1360 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0); 1361 if (err) 1362 return err; 1363 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1364 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1365 MLXSW_REG_QEEC_HR_SUBGROUP, i, 1366 0, false, 0); 1367 if (err) 1368 return err; 1369 } 1370 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1371 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1372 MLXSW_REG_QEEC_HR_TC, i, i, 1373 false, 0); 1374 if (err) 1375 return err; 1376 1377 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1378 MLXSW_REG_QEEC_HR_TC, 1379 i + 8, i, 1380 true, 100); 1381 if (err) 1382 return err; 1383 } 1384 1385 /* Make sure the max shaper is disabled in all hierarchies that support 1386 * it. Note that this disables ptps (PTP shaper), but that is intended 1387 * for the initial configuration. 1388 */ 1389 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1390 MLXSW_REG_QEEC_HR_PORT, 0, 0, 1391 MLXSW_REG_QEEC_MAS_DIS, 0); 1392 if (err) 1393 return err; 1394 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1395 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1396 MLXSW_REG_QEEC_HR_SUBGROUP, 1397 i, 0, 1398 MLXSW_REG_QEEC_MAS_DIS, 0); 1399 if (err) 1400 return err; 1401 } 1402 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1403 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1404 MLXSW_REG_QEEC_HR_TC, 1405 i, i, 1406 MLXSW_REG_QEEC_MAS_DIS, 0); 1407 if (err) 1408 return err; 1409 1410 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1411 MLXSW_REG_QEEC_HR_TC, 1412 i + 8, i, 1413 MLXSW_REG_QEEC_MAS_DIS, 0); 1414 if (err) 1415 return err; 1416 } 1417 1418 /* Configure the min shaper for multicast TCs. */ 1419 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1420 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 1421 MLXSW_REG_QEEC_HR_TC, 1422 i + 8, i, 1423 MLXSW_REG_QEEC_MIS_MIN); 1424 if (err) 1425 return err; 1426 } 1427 1428 /* Map all priorities to traffic class 0. */ 1429 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1430 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 1431 if (err) 1432 return err; 1433 } 1434 1435 return 0; 1436 } 1437 1438 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 1439 bool enable) 1440 { 1441 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1442 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 1443 1444 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 1445 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 1446 } 1447 1448 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port) 1449 { 1450 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1451 u8 module = mlxsw_sp_port->mapping.module; 1452 u64 overheat_counter; 1453 int err; 1454 1455 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, module, 1456 &overheat_counter); 1457 if (err) 1458 return err; 1459 1460 mlxsw_sp_port->module_overheat_initial_val = overheat_counter; 1461 return 0; 1462 } 1463 1464 int 1465 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port, 1466 bool is_8021ad_tagged, 1467 bool is_8021q_tagged) 1468 { 1469 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1470 char spvc_pl[MLXSW_REG_SPVC_LEN]; 1471 1472 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port, 1473 is_8021ad_tagged, is_8021q_tagged); 1474 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl); 1475 } 1476 1477 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp, 1478 u16 local_port, u8 *port_number, 1479 u8 *split_port_subnumber, 1480 u8 *slot_index) 1481 { 1482 char pllp_pl[MLXSW_REG_PLLP_LEN]; 1483 int err; 1484 1485 mlxsw_reg_pllp_pack(pllp_pl, local_port); 1486 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); 1487 if (err) 1488 return err; 1489 mlxsw_reg_pllp_unpack(pllp_pl, port_number, 1490 split_port_subnumber, slot_index); 1491 return 0; 1492 } 1493 1494 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port, 1495 bool split, 1496 struct mlxsw_sp_port_mapping *port_mapping) 1497 { 1498 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1499 struct mlxsw_sp_port *mlxsw_sp_port; 1500 u32 lanes = port_mapping->width; 1501 u8 split_port_subnumber; 1502 struct net_device *dev; 1503 u8 port_number; 1504 u8 slot_index; 1505 bool splittable; 1506 int err; 1507 1508 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping); 1509 if (err) { 1510 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 1511 local_port); 1512 return err; 1513 } 1514 1515 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0); 1516 if (err) { 1517 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 1518 local_port); 1519 goto err_port_swid_set; 1520 } 1521 1522 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number, 1523 &split_port_subnumber, &slot_index); 1524 if (err) { 1525 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n", 1526 local_port); 1527 goto err_port_label_info_get; 1528 } 1529 1530 splittable = lanes > 1 && !split; 1531 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, 1532 port_number, split, split_port_subnumber, 1533 splittable, lanes, mlxsw_sp->base_mac, 1534 sizeof(mlxsw_sp->base_mac)); 1535 if (err) { 1536 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 1537 local_port); 1538 goto err_core_port_init; 1539 } 1540 1541 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 1542 if (!dev) { 1543 err = -ENOMEM; 1544 goto err_alloc_etherdev; 1545 } 1546 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 1547 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp)); 1548 mlxsw_sp_port = netdev_priv(dev); 1549 mlxsw_sp_port->dev = dev; 1550 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1551 mlxsw_sp_port->local_port = local_port; 1552 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; 1553 mlxsw_sp_port->split = split; 1554 mlxsw_sp_port->mapping = *port_mapping; 1555 mlxsw_sp_port->link.autoneg = 1; 1556 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 1557 1558 mlxsw_sp_port->pcpu_stats = 1559 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 1560 if (!mlxsw_sp_port->pcpu_stats) { 1561 err = -ENOMEM; 1562 goto err_alloc_stats; 1563 } 1564 1565 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1566 &update_stats_cache); 1567 1568 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 1569 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 1570 1571 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 1572 if (err) { 1573 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 1574 mlxsw_sp_port->local_port); 1575 goto err_dev_addr_init; 1576 } 1577 1578 netif_carrier_off(dev); 1579 1580 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 1581 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 1582 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK; 1583 1584 dev->min_mtu = 0; 1585 dev->max_mtu = ETH_MAX_MTU; 1586 1587 /* Each packet needs to have a Tx header (metadata) on top all other 1588 * headers. 1589 */ 1590 dev->needed_headroom = MLXSW_TXHDR_LEN; 1591 1592 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 1593 if (err) { 1594 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 1595 mlxsw_sp_port->local_port); 1596 goto err_port_system_port_mapping_set; 1597 } 1598 1599 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port); 1600 if (err) { 1601 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 1602 mlxsw_sp_port->local_port); 1603 goto err_port_speed_by_width_set; 1604 } 1605 1606 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port, 1607 &mlxsw_sp_port->max_speed); 1608 if (err) { 1609 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n", 1610 mlxsw_sp_port->local_port); 1611 goto err_max_speed_get; 1612 } 1613 1614 err = mlxsw_sp_port_max_mtu_get(mlxsw_sp_port, &mlxsw_sp_port->max_mtu); 1615 if (err) { 1616 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n", 1617 mlxsw_sp_port->local_port); 1618 goto err_port_max_mtu_get; 1619 } 1620 1621 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 1622 if (err) { 1623 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 1624 mlxsw_sp_port->local_port); 1625 goto err_port_mtu_set; 1626 } 1627 1628 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1629 if (err) 1630 goto err_port_admin_status_set; 1631 1632 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 1633 if (err) { 1634 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 1635 mlxsw_sp_port->local_port); 1636 goto err_port_buffers_init; 1637 } 1638 1639 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 1640 if (err) { 1641 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 1642 mlxsw_sp_port->local_port); 1643 goto err_port_ets_init; 1644 } 1645 1646 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 1647 if (err) { 1648 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 1649 mlxsw_sp_port->local_port); 1650 goto err_port_tc_mc_mode; 1651 } 1652 1653 /* ETS and buffers must be initialized before DCB. */ 1654 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 1655 if (err) { 1656 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 1657 mlxsw_sp_port->local_port); 1658 goto err_port_dcb_init; 1659 } 1660 1661 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 1662 if (err) { 1663 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 1664 mlxsw_sp_port->local_port); 1665 goto err_port_fids_init; 1666 } 1667 1668 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 1669 if (err) { 1670 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 1671 mlxsw_sp_port->local_port); 1672 goto err_port_qdiscs_init; 1673 } 1674 1675 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false, 1676 false); 1677 if (err) { 1678 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n", 1679 mlxsw_sp_port->local_port); 1680 goto err_port_vlan_clear; 1681 } 1682 1683 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 1684 if (err) { 1685 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 1686 mlxsw_sp_port->local_port); 1687 goto err_port_nve_init; 1688 } 1689 1690 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 1691 ETH_P_8021Q); 1692 if (err) { 1693 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n", 1694 mlxsw_sp_port->local_port); 1695 goto err_port_pvid_set; 1696 } 1697 1698 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, 1699 MLXSW_SP_DEFAULT_VID); 1700 if (IS_ERR(mlxsw_sp_port_vlan)) { 1701 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 1702 mlxsw_sp_port->local_port); 1703 err = PTR_ERR(mlxsw_sp_port_vlan); 1704 goto err_port_vlan_create; 1705 } 1706 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan; 1707 1708 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat 1709 * only packets with 802.1q header as tagged packets. 1710 */ 1711 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true); 1712 if (err) { 1713 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n", 1714 local_port); 1715 goto err_port_vlan_classification_set; 1716 } 1717 1718 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw, 1719 mlxsw_sp->ptp_ops->shaper_work); 1720 1721 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 1722 1723 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port); 1724 if (err) { 1725 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n", 1726 mlxsw_sp_port->local_port); 1727 goto err_port_overheat_init_val_set; 1728 } 1729 1730 err = register_netdev(dev); 1731 if (err) { 1732 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 1733 mlxsw_sp_port->local_port); 1734 goto err_register_netdev; 1735 } 1736 1737 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 1738 mlxsw_sp_port, dev); 1739 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 1740 return 0; 1741 1742 err_register_netdev: 1743 err_port_overheat_init_val_set: 1744 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1745 err_port_vlan_classification_set: 1746 mlxsw_sp->ports[local_port] = NULL; 1747 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1748 err_port_vlan_create: 1749 err_port_pvid_set: 1750 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1751 err_port_nve_init: 1752 err_port_vlan_clear: 1753 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1754 err_port_qdiscs_init: 1755 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1756 err_port_fids_init: 1757 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1758 err_port_dcb_init: 1759 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1760 err_port_tc_mc_mode: 1761 err_port_ets_init: 1762 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1763 err_port_buffers_init: 1764 err_port_admin_status_set: 1765 err_port_mtu_set: 1766 err_port_max_mtu_get: 1767 err_max_speed_get: 1768 err_port_speed_by_width_set: 1769 err_port_system_port_mapping_set: 1770 err_dev_addr_init: 1771 free_percpu(mlxsw_sp_port->pcpu_stats); 1772 err_alloc_stats: 1773 free_netdev(dev); 1774 err_alloc_etherdev: 1775 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1776 err_core_port_init: 1777 err_port_label_info_get: 1778 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1779 MLXSW_PORT_SWID_DISABLED_PORT); 1780 err_port_swid_set: 1781 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, port_mapping->module); 1782 return err; 1783 } 1784 1785 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1786 { 1787 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 1788 u8 module = mlxsw_sp_port->mapping.module; 1789 1790 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 1791 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw); 1792 mlxsw_sp_port_ptp_clear(mlxsw_sp_port); 1793 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 1794 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 1795 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1796 mlxsw_sp->ports[local_port] = NULL; 1797 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); 1798 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1799 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1800 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1801 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1802 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1803 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1804 free_percpu(mlxsw_sp_port->pcpu_stats); 1805 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 1806 free_netdev(mlxsw_sp_port->dev); 1807 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1808 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1809 MLXSW_PORT_SWID_DISABLED_PORT); 1810 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, module); 1811 } 1812 1813 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp) 1814 { 1815 struct mlxsw_sp_port *mlxsw_sp_port; 1816 int err; 1817 1818 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL); 1819 if (!mlxsw_sp_port) 1820 return -ENOMEM; 1821 1822 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1823 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT; 1824 1825 err = mlxsw_core_cpu_port_init(mlxsw_sp->core, 1826 mlxsw_sp_port, 1827 mlxsw_sp->base_mac, 1828 sizeof(mlxsw_sp->base_mac)); 1829 if (err) { 1830 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n"); 1831 goto err_core_cpu_port_init; 1832 } 1833 1834 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port; 1835 return 0; 1836 1837 err_core_cpu_port_init: 1838 kfree(mlxsw_sp_port); 1839 return err; 1840 } 1841 1842 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp) 1843 { 1844 struct mlxsw_sp_port *mlxsw_sp_port = 1845 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT]; 1846 1847 mlxsw_core_cpu_port_fini(mlxsw_sp->core); 1848 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL; 1849 kfree(mlxsw_sp_port); 1850 } 1851 1852 static bool mlxsw_sp_local_port_valid(u16 local_port) 1853 { 1854 return local_port != MLXSW_PORT_CPU_PORT; 1855 } 1856 1857 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1858 { 1859 if (!mlxsw_sp_local_port_valid(local_port)) 1860 return false; 1861 return mlxsw_sp->ports[local_port] != NULL; 1862 } 1863 1864 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 1865 { 1866 int i; 1867 1868 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 1869 if (mlxsw_sp_port_created(mlxsw_sp, i)) 1870 mlxsw_sp_port_remove(mlxsw_sp, i); 1871 mlxsw_sp_cpu_port_remove(mlxsw_sp); 1872 kfree(mlxsw_sp->ports); 1873 mlxsw_sp->ports = NULL; 1874 } 1875 1876 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 1877 { 1878 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1879 struct mlxsw_sp_port_mapping *port_mapping; 1880 size_t alloc_size; 1881 int i; 1882 int err; 1883 1884 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 1885 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 1886 if (!mlxsw_sp->ports) 1887 return -ENOMEM; 1888 1889 err = mlxsw_sp_cpu_port_create(mlxsw_sp); 1890 if (err) 1891 goto err_cpu_port_create; 1892 1893 for (i = 1; i < max_ports; i++) { 1894 port_mapping = mlxsw_sp->port_mapping[i]; 1895 if (!port_mapping) 1896 continue; 1897 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping); 1898 if (err) 1899 goto err_port_create; 1900 } 1901 return 0; 1902 1903 err_port_create: 1904 for (i--; i >= 1; i--) 1905 if (mlxsw_sp_port_created(mlxsw_sp, i)) 1906 mlxsw_sp_port_remove(mlxsw_sp, i); 1907 mlxsw_sp_cpu_port_remove(mlxsw_sp); 1908 err_cpu_port_create: 1909 kfree(mlxsw_sp->ports); 1910 mlxsw_sp->ports = NULL; 1911 return err; 1912 } 1913 1914 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp) 1915 { 1916 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1917 struct mlxsw_sp_port_mapping port_mapping; 1918 int i; 1919 int err; 1920 1921 mlxsw_sp->port_mapping = kcalloc(max_ports, 1922 sizeof(struct mlxsw_sp_port_mapping *), 1923 GFP_KERNEL); 1924 if (!mlxsw_sp->port_mapping) 1925 return -ENOMEM; 1926 1927 for (i = 1; i < max_ports; i++) { 1928 if (mlxsw_core_port_is_xm(mlxsw_sp->core, i)) 1929 continue; 1930 1931 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &port_mapping); 1932 if (err) 1933 goto err_port_module_info_get; 1934 if (!port_mapping.width) 1935 continue; 1936 1937 mlxsw_sp->port_mapping[i] = kmemdup(&port_mapping, 1938 sizeof(port_mapping), 1939 GFP_KERNEL); 1940 if (!mlxsw_sp->port_mapping[i]) { 1941 err = -ENOMEM; 1942 goto err_port_module_info_dup; 1943 } 1944 } 1945 return 0; 1946 1947 err_port_module_info_get: 1948 err_port_module_info_dup: 1949 for (i--; i >= 1; i--) 1950 kfree(mlxsw_sp->port_mapping[i]); 1951 kfree(mlxsw_sp->port_mapping); 1952 return err; 1953 } 1954 1955 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp) 1956 { 1957 int i; 1958 1959 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 1960 kfree(mlxsw_sp->port_mapping[i]); 1961 kfree(mlxsw_sp->port_mapping); 1962 } 1963 1964 static int 1965 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, 1966 struct mlxsw_sp_port_mapping *port_mapping, 1967 unsigned int count, const char *pmtdb_pl) 1968 { 1969 struct mlxsw_sp_port_mapping split_port_mapping; 1970 int err, i; 1971 1972 split_port_mapping = *port_mapping; 1973 split_port_mapping.width /= count; 1974 for (i = 0; i < count; i++) { 1975 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 1976 1977 if (!mlxsw_sp_local_port_valid(s_local_port)) 1978 continue; 1979 1980 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port, 1981 true, &split_port_mapping); 1982 if (err) 1983 goto err_port_create; 1984 split_port_mapping.lane += split_port_mapping.width; 1985 } 1986 1987 return 0; 1988 1989 err_port_create: 1990 for (i--; i >= 0; i--) { 1991 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 1992 1993 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 1994 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 1995 } 1996 return err; 1997 } 1998 1999 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 2000 unsigned int count, 2001 const char *pmtdb_pl) 2002 { 2003 struct mlxsw_sp_port_mapping *port_mapping; 2004 int i; 2005 2006 /* Go over original unsplit ports in the gap and recreate them. */ 2007 for (i = 0; i < count; i++) { 2008 u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2009 2010 port_mapping = mlxsw_sp->port_mapping[local_port]; 2011 if (!port_mapping || !mlxsw_sp_local_port_valid(local_port)) 2012 continue; 2013 mlxsw_sp_port_create(mlxsw_sp, local_port, 2014 false, port_mapping); 2015 } 2016 } 2017 2018 static struct mlxsw_sp_port * 2019 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port) 2020 { 2021 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port]) 2022 return mlxsw_sp->ports[local_port]; 2023 return NULL; 2024 } 2025 2026 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port, 2027 unsigned int count, 2028 struct netlink_ext_ack *extack) 2029 { 2030 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2031 struct mlxsw_sp_port_mapping port_mapping; 2032 struct mlxsw_sp_port *mlxsw_sp_port; 2033 enum mlxsw_reg_pmtdb_status status; 2034 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2035 int i; 2036 int err; 2037 2038 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2039 if (!mlxsw_sp_port) { 2040 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2041 local_port); 2042 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2043 return -EINVAL; 2044 } 2045 2046 if (mlxsw_sp_port->split) { 2047 NL_SET_ERR_MSG_MOD(extack, "Port is already split"); 2048 return -EINVAL; 2049 } 2050 2051 mlxsw_reg_pmtdb_pack(pmtdb_pl, 0, mlxsw_sp_port->mapping.module, 2052 mlxsw_sp_port->mapping.module_width / count, 2053 count); 2054 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2055 if (err) { 2056 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2057 return err; 2058 } 2059 2060 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl); 2061 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) { 2062 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration"); 2063 return -EINVAL; 2064 } 2065 2066 port_mapping = mlxsw_sp_port->mapping; 2067 2068 for (i = 0; i < count; i++) { 2069 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2070 2071 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2072 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2073 } 2074 2075 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping, 2076 count, pmtdb_pl); 2077 if (err) { 2078 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 2079 goto err_port_split_create; 2080 } 2081 2082 return 0; 2083 2084 err_port_split_create: 2085 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2086 return err; 2087 } 2088 2089 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port, 2090 struct netlink_ext_ack *extack) 2091 { 2092 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2093 struct mlxsw_sp_port *mlxsw_sp_port; 2094 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2095 unsigned int count; 2096 int i; 2097 int err; 2098 2099 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2100 if (!mlxsw_sp_port) { 2101 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2102 local_port); 2103 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2104 return -EINVAL; 2105 } 2106 2107 if (!mlxsw_sp_port->split) { 2108 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 2109 return -EINVAL; 2110 } 2111 2112 count = mlxsw_sp_port->mapping.module_width / 2113 mlxsw_sp_port->mapping.width; 2114 2115 mlxsw_reg_pmtdb_pack(pmtdb_pl, 0, mlxsw_sp_port->mapping.module, 2116 mlxsw_sp_port->mapping.module_width / count, 2117 count); 2118 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2119 if (err) { 2120 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2121 return err; 2122 } 2123 2124 for (i = 0; i < count; i++) { 2125 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2126 2127 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2128 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2129 } 2130 2131 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2132 2133 return 0; 2134 } 2135 2136 static void 2137 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port) 2138 { 2139 int i; 2140 2141 for (i = 0; i < TC_MAX_QUEUE; i++) 2142 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0; 2143 } 2144 2145 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 2146 char *pude_pl, void *priv) 2147 { 2148 struct mlxsw_sp *mlxsw_sp = priv; 2149 struct mlxsw_sp_port *mlxsw_sp_port; 2150 enum mlxsw_reg_pude_oper_status status; 2151 unsigned int max_ports; 2152 u16 local_port; 2153 2154 max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2155 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 2156 2157 if (WARN_ON_ONCE(!local_port || local_port >= max_ports)) 2158 return; 2159 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2160 if (!mlxsw_sp_port) 2161 return; 2162 2163 status = mlxsw_reg_pude_oper_status_get(pude_pl); 2164 if (status == MLXSW_PORT_OPER_STATUS_UP) { 2165 netdev_info(mlxsw_sp_port->dev, "link up\n"); 2166 netif_carrier_on(mlxsw_sp_port->dev); 2167 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0); 2168 } else { 2169 netdev_info(mlxsw_sp_port->dev, "link down\n"); 2170 netif_carrier_off(mlxsw_sp_port->dev); 2171 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port); 2172 } 2173 } 2174 2175 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp, 2176 char *mtpptr_pl, bool ingress) 2177 { 2178 u16 local_port; 2179 u8 num_rec; 2180 int i; 2181 2182 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl); 2183 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl); 2184 for (i = 0; i < num_rec; i++) { 2185 u8 domain_number; 2186 u8 message_type; 2187 u16 sequence_id; 2188 u64 timestamp; 2189 2190 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type, 2191 &domain_number, &sequence_id, 2192 ×tamp); 2193 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port, 2194 message_type, domain_number, 2195 sequence_id, timestamp); 2196 } 2197 } 2198 2199 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg, 2200 char *mtpptr_pl, void *priv) 2201 { 2202 struct mlxsw_sp *mlxsw_sp = priv; 2203 2204 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true); 2205 } 2206 2207 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg, 2208 char *mtpptr_pl, void *priv) 2209 { 2210 struct mlxsw_sp *mlxsw_sp = priv; 2211 2212 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false); 2213 } 2214 2215 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 2216 u16 local_port, void *priv) 2217 { 2218 struct mlxsw_sp *mlxsw_sp = priv; 2219 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2220 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 2221 2222 if (unlikely(!mlxsw_sp_port)) { 2223 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 2224 local_port); 2225 return; 2226 } 2227 2228 skb->dev = mlxsw_sp_port->dev; 2229 2230 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 2231 u64_stats_update_begin(&pcpu_stats->syncp); 2232 pcpu_stats->rx_packets++; 2233 pcpu_stats->rx_bytes += skb->len; 2234 u64_stats_update_end(&pcpu_stats->syncp); 2235 2236 skb->protocol = eth_type_trans(skb, skb->dev); 2237 netif_receive_skb(skb); 2238 } 2239 2240 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port, 2241 void *priv) 2242 { 2243 skb->offload_fwd_mark = 1; 2244 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2245 } 2246 2247 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb, 2248 u16 local_port, void *priv) 2249 { 2250 skb->offload_l3_fwd_mark = 1; 2251 skb->offload_fwd_mark = 1; 2252 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2253 } 2254 2255 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 2256 u16 local_port) 2257 { 2258 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port); 2259 } 2260 2261 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2262 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 2263 _is_ctrl, SP_##_trap_group, DISCARD) 2264 2265 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2266 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 2267 _is_ctrl, SP_##_trap_group, DISCARD) 2268 2269 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2270 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \ 2271 _is_ctrl, SP_##_trap_group, DISCARD) 2272 2273 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 2274 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 2275 2276 static const struct mlxsw_listener mlxsw_sp_listener[] = { 2277 /* Events */ 2278 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 2279 /* L2 traps */ 2280 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false), 2281 /* L3 traps */ 2282 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 2283 false), 2284 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 2285 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 2286 false), 2287 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD, 2288 ROUTER_EXP, false), 2289 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD, 2290 ROUTER_EXP, false), 2291 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD, 2292 ROUTER_EXP, false), 2293 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD, 2294 ROUTER_EXP, false), 2295 /* Multicast Router Traps */ 2296 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 2297 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 2298 /* NVE traps */ 2299 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false), 2300 }; 2301 2302 static const struct mlxsw_listener mlxsw_sp1_listener[] = { 2303 /* Events */ 2304 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0), 2305 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0), 2306 }; 2307 2308 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 2309 { 2310 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2311 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 2312 enum mlxsw_reg_qpcr_ir_units ir_units; 2313 int max_cpu_policers; 2314 bool is_bytes; 2315 u8 burst_size; 2316 u32 rate; 2317 int i, err; 2318 2319 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 2320 return -EIO; 2321 2322 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2323 2324 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 2325 for (i = 0; i < max_cpu_policers; i++) { 2326 is_bytes = false; 2327 switch (i) { 2328 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2329 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2330 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2331 rate = 1024; 2332 burst_size = 7; 2333 break; 2334 default: 2335 continue; 2336 } 2337 2338 __set_bit(i, mlxsw_sp->trap->policers_usage); 2339 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 2340 burst_size); 2341 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 2342 if (err) 2343 return err; 2344 } 2345 2346 return 0; 2347 } 2348 2349 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 2350 { 2351 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2352 enum mlxsw_reg_htgt_trap_group i; 2353 int max_cpu_policers; 2354 int max_trap_groups; 2355 u8 priority, tc; 2356 u16 policer_id; 2357 int err; 2358 2359 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 2360 return -EIO; 2361 2362 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 2363 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2364 2365 for (i = 0; i < max_trap_groups; i++) { 2366 policer_id = i; 2367 switch (i) { 2368 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2369 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2370 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2371 priority = 1; 2372 tc = 1; 2373 break; 2374 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 2375 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 2376 tc = MLXSW_REG_HTGT_DEFAULT_TC; 2377 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 2378 break; 2379 default: 2380 continue; 2381 } 2382 2383 if (max_cpu_policers <= policer_id && 2384 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 2385 return -EIO; 2386 2387 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 2388 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2389 if (err) 2390 return err; 2391 } 2392 2393 return 0; 2394 } 2395 2396 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp, 2397 const struct mlxsw_listener listeners[], 2398 size_t listeners_count) 2399 { 2400 int i; 2401 int err; 2402 2403 for (i = 0; i < listeners_count; i++) { 2404 err = mlxsw_core_trap_register(mlxsw_sp->core, 2405 &listeners[i], 2406 mlxsw_sp); 2407 if (err) 2408 goto err_listener_register; 2409 2410 } 2411 return 0; 2412 2413 err_listener_register: 2414 for (i--; i >= 0; i--) { 2415 mlxsw_core_trap_unregister(mlxsw_sp->core, 2416 &listeners[i], 2417 mlxsw_sp); 2418 } 2419 return err; 2420 } 2421 2422 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp, 2423 const struct mlxsw_listener listeners[], 2424 size_t listeners_count) 2425 { 2426 int i; 2427 2428 for (i = 0; i < listeners_count; i++) { 2429 mlxsw_core_trap_unregister(mlxsw_sp->core, 2430 &listeners[i], 2431 mlxsw_sp); 2432 } 2433 } 2434 2435 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 2436 { 2437 struct mlxsw_sp_trap *trap; 2438 u64 max_policers; 2439 int err; 2440 2441 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS)) 2442 return -EIO; 2443 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS); 2444 trap = kzalloc(struct_size(trap, policers_usage, 2445 BITS_TO_LONGS(max_policers)), GFP_KERNEL); 2446 if (!trap) 2447 return -ENOMEM; 2448 trap->max_policers = max_policers; 2449 mlxsw_sp->trap = trap; 2450 2451 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 2452 if (err) 2453 goto err_cpu_policers_set; 2454 2455 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 2456 if (err) 2457 goto err_trap_groups_set; 2458 2459 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener, 2460 ARRAY_SIZE(mlxsw_sp_listener)); 2461 if (err) 2462 goto err_traps_register; 2463 2464 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners, 2465 mlxsw_sp->listeners_count); 2466 if (err) 2467 goto err_extra_traps_init; 2468 2469 return 0; 2470 2471 err_extra_traps_init: 2472 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener, 2473 ARRAY_SIZE(mlxsw_sp_listener)); 2474 err_traps_register: 2475 err_trap_groups_set: 2476 err_cpu_policers_set: 2477 kfree(trap); 2478 return err; 2479 } 2480 2481 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 2482 { 2483 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners, 2484 mlxsw_sp->listeners_count); 2485 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener, 2486 ARRAY_SIZE(mlxsw_sp_listener)); 2487 kfree(mlxsw_sp->trap); 2488 } 2489 2490 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe 2491 2492 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 2493 { 2494 char slcr_pl[MLXSW_REG_SLCR_LEN]; 2495 u32 seed; 2496 int err; 2497 2498 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac), 2499 MLXSW_SP_LAG_SEED_INIT); 2500 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 2501 MLXSW_REG_SLCR_LAG_HASH_DMAC | 2502 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 2503 MLXSW_REG_SLCR_LAG_HASH_VLANID | 2504 MLXSW_REG_SLCR_LAG_HASH_SIP | 2505 MLXSW_REG_SLCR_LAG_HASH_DIP | 2506 MLXSW_REG_SLCR_LAG_HASH_SPORT | 2507 MLXSW_REG_SLCR_LAG_HASH_DPORT | 2508 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 2509 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 2510 if (err) 2511 return err; 2512 2513 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 2514 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 2515 return -EIO; 2516 2517 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 2518 sizeof(struct mlxsw_sp_upper), 2519 GFP_KERNEL); 2520 if (!mlxsw_sp->lags) 2521 return -ENOMEM; 2522 2523 return 0; 2524 } 2525 2526 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 2527 { 2528 kfree(mlxsw_sp->lags); 2529 } 2530 2531 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 2532 { 2533 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2534 int err; 2535 2536 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 2537 MLXSW_REG_HTGT_INVALID_POLICER, 2538 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2539 MLXSW_REG_HTGT_DEFAULT_TC); 2540 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2541 if (err) 2542 return err; 2543 2544 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_MFDE, 2545 MLXSW_REG_HTGT_INVALID_POLICER, 2546 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2547 MLXSW_REG_HTGT_DEFAULT_TC); 2548 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2549 if (err) 2550 return err; 2551 2552 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_MTWE, 2553 MLXSW_REG_HTGT_INVALID_POLICER, 2554 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2555 MLXSW_REG_HTGT_DEFAULT_TC); 2556 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2557 if (err) 2558 return err; 2559 2560 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_PMPE, 2561 MLXSW_REG_HTGT_INVALID_POLICER, 2562 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 2563 MLXSW_REG_HTGT_DEFAULT_TC); 2564 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2565 } 2566 2567 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = { 2568 .clock_init = mlxsw_sp1_ptp_clock_init, 2569 .clock_fini = mlxsw_sp1_ptp_clock_fini, 2570 .init = mlxsw_sp1_ptp_init, 2571 .fini = mlxsw_sp1_ptp_fini, 2572 .receive = mlxsw_sp1_ptp_receive, 2573 .transmitted = mlxsw_sp1_ptp_transmitted, 2574 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get, 2575 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set, 2576 .shaper_work = mlxsw_sp1_ptp_shaper_work, 2577 .get_ts_info = mlxsw_sp1_ptp_get_ts_info, 2578 .get_stats_count = mlxsw_sp1_get_stats_count, 2579 .get_stats_strings = mlxsw_sp1_get_stats_strings, 2580 .get_stats = mlxsw_sp1_get_stats, 2581 }; 2582 2583 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = { 2584 .clock_init = mlxsw_sp2_ptp_clock_init, 2585 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2586 .init = mlxsw_sp2_ptp_init, 2587 .fini = mlxsw_sp2_ptp_fini, 2588 .receive = mlxsw_sp2_ptp_receive, 2589 .transmitted = mlxsw_sp2_ptp_transmitted, 2590 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2591 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2592 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2593 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2594 .get_stats_count = mlxsw_sp2_get_stats_count, 2595 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2596 .get_stats = mlxsw_sp2_get_stats, 2597 }; 2598 2599 struct mlxsw_sp_sample_trigger_node { 2600 struct mlxsw_sp_sample_trigger trigger; 2601 struct mlxsw_sp_sample_params params; 2602 struct rhash_head ht_node; 2603 struct rcu_head rcu; 2604 refcount_t refcount; 2605 }; 2606 2607 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = { 2608 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger), 2609 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node), 2610 .key_len = sizeof(struct mlxsw_sp_sample_trigger), 2611 .automatic_shrinking = true, 2612 }; 2613 2614 static void 2615 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key, 2616 const struct mlxsw_sp_sample_trigger *trigger) 2617 { 2618 memset(key, 0, sizeof(*key)); 2619 key->type = trigger->type; 2620 key->local_port = trigger->local_port; 2621 } 2622 2623 /* RCU read lock must be held */ 2624 struct mlxsw_sp_sample_params * 2625 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp, 2626 const struct mlxsw_sp_sample_trigger *trigger) 2627 { 2628 struct mlxsw_sp_sample_trigger_node *trigger_node; 2629 struct mlxsw_sp_sample_trigger key; 2630 2631 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2632 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key, 2633 mlxsw_sp_sample_trigger_ht_params); 2634 if (!trigger_node) 2635 return NULL; 2636 2637 return &trigger_node->params; 2638 } 2639 2640 static int 2641 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp, 2642 const struct mlxsw_sp_sample_trigger *trigger, 2643 const struct mlxsw_sp_sample_params *params) 2644 { 2645 struct mlxsw_sp_sample_trigger_node *trigger_node; 2646 int err; 2647 2648 trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL); 2649 if (!trigger_node) 2650 return -ENOMEM; 2651 2652 trigger_node->trigger = *trigger; 2653 trigger_node->params = *params; 2654 refcount_set(&trigger_node->refcount, 1); 2655 2656 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht, 2657 &trigger_node->ht_node, 2658 mlxsw_sp_sample_trigger_ht_params); 2659 if (err) 2660 goto err_rhashtable_insert; 2661 2662 return 0; 2663 2664 err_rhashtable_insert: 2665 kfree(trigger_node); 2666 return err; 2667 } 2668 2669 static void 2670 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp, 2671 struct mlxsw_sp_sample_trigger_node *trigger_node) 2672 { 2673 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht, 2674 &trigger_node->ht_node, 2675 mlxsw_sp_sample_trigger_ht_params); 2676 kfree_rcu(trigger_node, rcu); 2677 } 2678 2679 int 2680 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp, 2681 const struct mlxsw_sp_sample_trigger *trigger, 2682 const struct mlxsw_sp_sample_params *params, 2683 struct netlink_ext_ack *extack) 2684 { 2685 struct mlxsw_sp_sample_trigger_node *trigger_node; 2686 struct mlxsw_sp_sample_trigger key; 2687 2688 ASSERT_RTNL(); 2689 2690 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2691 2692 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2693 &key, 2694 mlxsw_sp_sample_trigger_ht_params); 2695 if (!trigger_node) 2696 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key, 2697 params); 2698 2699 if (trigger_node->trigger.local_port) { 2700 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port"); 2701 return -EINVAL; 2702 } 2703 2704 if (trigger_node->params.psample_group != params->psample_group || 2705 trigger_node->params.truncate != params->truncate || 2706 trigger_node->params.rate != params->rate || 2707 trigger_node->params.trunc_size != params->trunc_size) { 2708 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger"); 2709 return -EINVAL; 2710 } 2711 2712 refcount_inc(&trigger_node->refcount); 2713 2714 return 0; 2715 } 2716 2717 void 2718 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp, 2719 const struct mlxsw_sp_sample_trigger *trigger) 2720 { 2721 struct mlxsw_sp_sample_trigger_node *trigger_node; 2722 struct mlxsw_sp_sample_trigger key; 2723 2724 ASSERT_RTNL(); 2725 2726 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2727 2728 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2729 &key, 2730 mlxsw_sp_sample_trigger_ht_params); 2731 if (!trigger_node) 2732 return; 2733 2734 if (!refcount_dec_and_test(&trigger_node->refcount)) 2735 return; 2736 2737 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node); 2738 } 2739 2740 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 2741 unsigned long event, void *ptr); 2742 2743 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96 2744 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128 2745 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789 2746 2747 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp) 2748 { 2749 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 2750 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT; 2751 mutex_init(&mlxsw_sp->parsing.lock); 2752 } 2753 2754 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp) 2755 { 2756 mutex_destroy(&mlxsw_sp->parsing.lock); 2757 } 2758 2759 struct mlxsw_sp_ipv6_addr_node { 2760 struct in6_addr key; 2761 struct rhash_head ht_node; 2762 u32 kvdl_index; 2763 refcount_t refcount; 2764 }; 2765 2766 static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = { 2767 .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key), 2768 .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node), 2769 .key_len = sizeof(struct in6_addr), 2770 .automatic_shrinking = true, 2771 }; 2772 2773 static int 2774 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6, 2775 u32 *p_kvdl_index) 2776 { 2777 struct mlxsw_sp_ipv6_addr_node *node; 2778 char rips_pl[MLXSW_REG_RIPS_LEN]; 2779 int err; 2780 2781 err = mlxsw_sp_kvdl_alloc(mlxsw_sp, 2782 MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2783 p_kvdl_index); 2784 if (err) 2785 return err; 2786 2787 mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6); 2788 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl); 2789 if (err) 2790 goto err_rips_write; 2791 2792 node = kzalloc(sizeof(*node), GFP_KERNEL); 2793 if (!node) { 2794 err = -ENOMEM; 2795 goto err_node_alloc; 2796 } 2797 2798 node->key = *addr6; 2799 node->kvdl_index = *p_kvdl_index; 2800 refcount_set(&node->refcount, 1); 2801 2802 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht, 2803 &node->ht_node, 2804 mlxsw_sp_ipv6_addr_ht_params); 2805 if (err) 2806 goto err_rhashtable_insert; 2807 2808 return 0; 2809 2810 err_rhashtable_insert: 2811 kfree(node); 2812 err_node_alloc: 2813 err_rips_write: 2814 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2815 *p_kvdl_index); 2816 return err; 2817 } 2818 2819 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp, 2820 struct mlxsw_sp_ipv6_addr_node *node) 2821 { 2822 u32 kvdl_index = node->kvdl_index; 2823 2824 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node, 2825 mlxsw_sp_ipv6_addr_ht_params); 2826 kfree(node); 2827 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2828 kvdl_index); 2829 } 2830 2831 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp, 2832 const struct in6_addr *addr6, 2833 u32 *p_kvdl_index) 2834 { 2835 struct mlxsw_sp_ipv6_addr_node *node; 2836 int err = 0; 2837 2838 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2839 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2840 mlxsw_sp_ipv6_addr_ht_params); 2841 if (node) { 2842 refcount_inc(&node->refcount); 2843 *p_kvdl_index = node->kvdl_index; 2844 goto out_unlock; 2845 } 2846 2847 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index); 2848 2849 out_unlock: 2850 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2851 return err; 2852 } 2853 2854 void 2855 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6) 2856 { 2857 struct mlxsw_sp_ipv6_addr_node *node; 2858 2859 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2860 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2861 mlxsw_sp_ipv6_addr_ht_params); 2862 if (WARN_ON(!node)) 2863 goto out_unlock; 2864 2865 if (!refcount_dec_and_test(&node->refcount)) 2866 goto out_unlock; 2867 2868 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node); 2869 2870 out_unlock: 2871 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2872 } 2873 2874 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp) 2875 { 2876 int err; 2877 2878 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht, 2879 &mlxsw_sp_ipv6_addr_ht_params); 2880 if (err) 2881 return err; 2882 2883 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock); 2884 return 0; 2885 } 2886 2887 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp) 2888 { 2889 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock); 2890 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht); 2891 } 2892 2893 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 2894 const struct mlxsw_bus_info *mlxsw_bus_info, 2895 struct netlink_ext_ack *extack) 2896 { 2897 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2898 int err; 2899 2900 mlxsw_sp->core = mlxsw_core; 2901 mlxsw_sp->bus_info = mlxsw_bus_info; 2902 2903 mlxsw_sp_parsing_init(mlxsw_sp); 2904 mlxsw_core_emad_string_tlv_enable(mlxsw_core); 2905 2906 err = mlxsw_sp_base_mac_get(mlxsw_sp); 2907 if (err) { 2908 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 2909 return err; 2910 } 2911 2912 err = mlxsw_sp_kvdl_init(mlxsw_sp); 2913 if (err) { 2914 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 2915 return err; 2916 } 2917 2918 err = mlxsw_sp_fids_init(mlxsw_sp); 2919 if (err) { 2920 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 2921 goto err_fids_init; 2922 } 2923 2924 err = mlxsw_sp_policers_init(mlxsw_sp); 2925 if (err) { 2926 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n"); 2927 goto err_policers_init; 2928 } 2929 2930 err = mlxsw_sp_traps_init(mlxsw_sp); 2931 if (err) { 2932 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 2933 goto err_traps_init; 2934 } 2935 2936 err = mlxsw_sp_devlink_traps_init(mlxsw_sp); 2937 if (err) { 2938 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n"); 2939 goto err_devlink_traps_init; 2940 } 2941 2942 err = mlxsw_sp_buffers_init(mlxsw_sp); 2943 if (err) { 2944 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 2945 goto err_buffers_init; 2946 } 2947 2948 err = mlxsw_sp_lag_init(mlxsw_sp); 2949 if (err) { 2950 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 2951 goto err_lag_init; 2952 } 2953 2954 /* Initialize SPAN before router and switchdev, so that those components 2955 * can call mlxsw_sp_span_respin(). 2956 */ 2957 err = mlxsw_sp_span_init(mlxsw_sp); 2958 if (err) { 2959 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 2960 goto err_span_init; 2961 } 2962 2963 err = mlxsw_sp_switchdev_init(mlxsw_sp); 2964 if (err) { 2965 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 2966 goto err_switchdev_init; 2967 } 2968 2969 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 2970 if (err) { 2971 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 2972 goto err_counter_pool_init; 2973 } 2974 2975 err = mlxsw_sp_afa_init(mlxsw_sp); 2976 if (err) { 2977 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 2978 goto err_afa_init; 2979 } 2980 2981 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp); 2982 if (err) { 2983 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n"); 2984 goto err_ipv6_addr_ht_init; 2985 } 2986 2987 err = mlxsw_sp_nve_init(mlxsw_sp); 2988 if (err) { 2989 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 2990 goto err_nve_init; 2991 } 2992 2993 err = mlxsw_sp_acl_init(mlxsw_sp); 2994 if (err) { 2995 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 2996 goto err_acl_init; 2997 } 2998 2999 err = mlxsw_sp_router_init(mlxsw_sp, extack); 3000 if (err) { 3001 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3002 goto err_router_init; 3003 } 3004 3005 if (mlxsw_sp->bus_info->read_frc_capable) { 3006 /* NULL is a valid return value from clock_init */ 3007 mlxsw_sp->clock = 3008 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp, 3009 mlxsw_sp->bus_info->dev); 3010 if (IS_ERR(mlxsw_sp->clock)) { 3011 err = PTR_ERR(mlxsw_sp->clock); 3012 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n"); 3013 goto err_ptp_clock_init; 3014 } 3015 } 3016 3017 if (mlxsw_sp->clock) { 3018 /* NULL is a valid return value from ptp_ops->init */ 3019 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp); 3020 if (IS_ERR(mlxsw_sp->ptp_state)) { 3021 err = PTR_ERR(mlxsw_sp->ptp_state); 3022 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n"); 3023 goto err_ptp_init; 3024 } 3025 } 3026 3027 /* Initialize netdevice notifier after router and SPAN is initialized, 3028 * so that the event handler can use router structures and call SPAN 3029 * respin. 3030 */ 3031 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3032 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3033 &mlxsw_sp->netdevice_nb); 3034 if (err) { 3035 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3036 goto err_netdev_notifier; 3037 } 3038 3039 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3040 if (err) { 3041 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3042 goto err_dpipe_init; 3043 } 3044 3045 err = mlxsw_sp_port_module_info_init(mlxsw_sp); 3046 if (err) { 3047 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n"); 3048 goto err_port_module_info_init; 3049 } 3050 3051 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht, 3052 &mlxsw_sp_sample_trigger_ht_params); 3053 if (err) { 3054 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n"); 3055 goto err_sample_trigger_init; 3056 } 3057 3058 err = mlxsw_sp_ports_create(mlxsw_sp); 3059 if (err) { 3060 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3061 goto err_ports_create; 3062 } 3063 3064 return 0; 3065 3066 err_ports_create: 3067 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3068 err_sample_trigger_init: 3069 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3070 err_port_module_info_init: 3071 mlxsw_sp_dpipe_fini(mlxsw_sp); 3072 err_dpipe_init: 3073 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3074 &mlxsw_sp->netdevice_nb); 3075 err_netdev_notifier: 3076 if (mlxsw_sp->clock) 3077 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3078 err_ptp_init: 3079 if (mlxsw_sp->clock) 3080 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3081 err_ptp_clock_init: 3082 mlxsw_sp_router_fini(mlxsw_sp); 3083 err_router_init: 3084 mlxsw_sp_acl_fini(mlxsw_sp); 3085 err_acl_init: 3086 mlxsw_sp_nve_fini(mlxsw_sp); 3087 err_nve_init: 3088 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3089 err_ipv6_addr_ht_init: 3090 mlxsw_sp_afa_fini(mlxsw_sp); 3091 err_afa_init: 3092 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3093 err_counter_pool_init: 3094 mlxsw_sp_switchdev_fini(mlxsw_sp); 3095 err_switchdev_init: 3096 mlxsw_sp_span_fini(mlxsw_sp); 3097 err_span_init: 3098 mlxsw_sp_lag_fini(mlxsw_sp); 3099 err_lag_init: 3100 mlxsw_sp_buffers_fini(mlxsw_sp); 3101 err_buffers_init: 3102 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3103 err_devlink_traps_init: 3104 mlxsw_sp_traps_fini(mlxsw_sp); 3105 err_traps_init: 3106 mlxsw_sp_policers_fini(mlxsw_sp); 3107 err_policers_init: 3108 mlxsw_sp_fids_fini(mlxsw_sp); 3109 err_fids_init: 3110 mlxsw_sp_kvdl_fini(mlxsw_sp); 3111 mlxsw_sp_parsing_fini(mlxsw_sp); 3112 return err; 3113 } 3114 3115 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 3116 const struct mlxsw_bus_info *mlxsw_bus_info, 3117 struct netlink_ext_ack *extack) 3118 { 3119 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3120 3121 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops; 3122 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3123 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3124 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3125 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3126 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops; 3127 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3128 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 3129 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask; 3130 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals; 3131 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops; 3132 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops; 3133 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops; 3134 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops; 3135 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops; 3136 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops; 3137 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops; 3138 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops; 3139 mlxsw_sp->listeners = mlxsw_sp1_listener; 3140 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener); 3141 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1; 3142 3143 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3144 } 3145 3146 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3147 const struct mlxsw_bus_info *mlxsw_bus_info, 3148 struct netlink_ext_ack *extack) 3149 { 3150 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3151 3152 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3153 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3154 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3155 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3156 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3157 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3158 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3159 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3160 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3161 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3162 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3163 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops; 3164 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3165 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3166 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops; 3167 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3168 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3169 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3170 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3171 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2; 3172 3173 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3174 } 3175 3176 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core, 3177 const struct mlxsw_bus_info *mlxsw_bus_info, 3178 struct netlink_ext_ack *extack) 3179 { 3180 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3181 3182 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3183 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3184 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3185 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3186 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3187 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3188 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3189 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3190 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3191 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3192 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3193 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3194 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3195 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3196 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3197 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3198 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3199 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3200 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3201 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3; 3202 3203 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3204 } 3205 3206 static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core, 3207 const struct mlxsw_bus_info *mlxsw_bus_info, 3208 struct netlink_ext_ack *extack) 3209 { 3210 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3211 3212 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3213 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3214 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3215 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops; 3216 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3217 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3218 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3219 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops; 3220 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3221 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3222 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3223 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3224 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3225 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3226 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3227 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3228 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3229 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3230 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3231 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4; 3232 3233 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3234 } 3235 3236 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3237 { 3238 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3239 3240 mlxsw_sp_ports_remove(mlxsw_sp); 3241 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3242 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3243 mlxsw_sp_dpipe_fini(mlxsw_sp); 3244 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3245 &mlxsw_sp->netdevice_nb); 3246 if (mlxsw_sp->clock) { 3247 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3248 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3249 } 3250 mlxsw_sp_router_fini(mlxsw_sp); 3251 mlxsw_sp_acl_fini(mlxsw_sp); 3252 mlxsw_sp_nve_fini(mlxsw_sp); 3253 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3254 mlxsw_sp_afa_fini(mlxsw_sp); 3255 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3256 mlxsw_sp_switchdev_fini(mlxsw_sp); 3257 mlxsw_sp_span_fini(mlxsw_sp); 3258 mlxsw_sp_lag_fini(mlxsw_sp); 3259 mlxsw_sp_buffers_fini(mlxsw_sp); 3260 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3261 mlxsw_sp_traps_fini(mlxsw_sp); 3262 mlxsw_sp_policers_fini(mlxsw_sp); 3263 mlxsw_sp_fids_fini(mlxsw_sp); 3264 mlxsw_sp_kvdl_fini(mlxsw_sp); 3265 mlxsw_sp_parsing_fini(mlxsw_sp); 3266 } 3267 3268 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated 3269 * 802.1Q FIDs 3270 */ 3271 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE (MLXSW_SP_FID_8021D_MAX + \ 3272 VLAN_VID_MASK - 1) 3273 3274 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3275 .used_max_mid = 1, 3276 .max_mid = MLXSW_SP_MID_MAX, 3277 .used_flood_tables = 1, 3278 .used_flood_mode = 1, 3279 .flood_mode = 3, 3280 .max_fid_flood_tables = 3, 3281 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE, 3282 .used_max_ib_mc = 1, 3283 .max_ib_mc = 0, 3284 .used_max_pkey = 1, 3285 .max_pkey = 0, 3286 .used_kvd_sizes = 1, 3287 .kvd_hash_single_parts = 59, 3288 .kvd_hash_double_parts = 41, 3289 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3290 .swid_config = { 3291 { 3292 .used_type = 1, 3293 .type = MLXSW_PORT_SWID_TYPE_ETH, 3294 } 3295 }, 3296 }; 3297 3298 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3299 .used_max_mid = 1, 3300 .max_mid = MLXSW_SP_MID_MAX, 3301 .used_flood_tables = 1, 3302 .used_flood_mode = 1, 3303 .flood_mode = 3, 3304 .max_fid_flood_tables = 3, 3305 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE, 3306 .used_max_ib_mc = 1, 3307 .max_ib_mc = 0, 3308 .used_max_pkey = 1, 3309 .max_pkey = 0, 3310 .used_kvh_xlt_cache_mode = 1, 3311 .kvh_xlt_cache_mode = 1, 3312 .swid_config = { 3313 { 3314 .used_type = 1, 3315 .type = MLXSW_PORT_SWID_TYPE_ETH, 3316 } 3317 }, 3318 }; 3319 3320 static void 3321 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3322 struct devlink_resource_size_params *kvd_size_params, 3323 struct devlink_resource_size_params *linear_size_params, 3324 struct devlink_resource_size_params *hash_double_size_params, 3325 struct devlink_resource_size_params *hash_single_size_params) 3326 { 3327 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3328 KVD_SINGLE_MIN_SIZE); 3329 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3330 KVD_DOUBLE_MIN_SIZE); 3331 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3332 u32 linear_size_min = 0; 3333 3334 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3335 MLXSW_SP_KVD_GRANULARITY, 3336 DEVLINK_RESOURCE_UNIT_ENTRY); 3337 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3338 kvd_size - single_size_min - 3339 double_size_min, 3340 MLXSW_SP_KVD_GRANULARITY, 3341 DEVLINK_RESOURCE_UNIT_ENTRY); 3342 devlink_resource_size_params_init(hash_double_size_params, 3343 double_size_min, 3344 kvd_size - single_size_min - 3345 linear_size_min, 3346 MLXSW_SP_KVD_GRANULARITY, 3347 DEVLINK_RESOURCE_UNIT_ENTRY); 3348 devlink_resource_size_params_init(hash_single_size_params, 3349 single_size_min, 3350 kvd_size - double_size_min - 3351 linear_size_min, 3352 MLXSW_SP_KVD_GRANULARITY, 3353 DEVLINK_RESOURCE_UNIT_ENTRY); 3354 } 3355 3356 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3357 { 3358 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3359 struct devlink_resource_size_params hash_single_size_params; 3360 struct devlink_resource_size_params hash_double_size_params; 3361 struct devlink_resource_size_params linear_size_params; 3362 struct devlink_resource_size_params kvd_size_params; 3363 u32 kvd_size, single_size, double_size, linear_size; 3364 const struct mlxsw_config_profile *profile; 3365 int err; 3366 3367 profile = &mlxsw_sp1_config_profile; 3368 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3369 return -EIO; 3370 3371 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3372 &linear_size_params, 3373 &hash_double_size_params, 3374 &hash_single_size_params); 3375 3376 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3377 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3378 kvd_size, MLXSW_SP_RESOURCE_KVD, 3379 DEVLINK_RESOURCE_ID_PARENT_TOP, 3380 &kvd_size_params); 3381 if (err) 3382 return err; 3383 3384 linear_size = profile->kvd_linear_size; 3385 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3386 linear_size, 3387 MLXSW_SP_RESOURCE_KVD_LINEAR, 3388 MLXSW_SP_RESOURCE_KVD, 3389 &linear_size_params); 3390 if (err) 3391 return err; 3392 3393 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 3394 if (err) 3395 return err; 3396 3397 double_size = kvd_size - linear_size; 3398 double_size *= profile->kvd_hash_double_parts; 3399 double_size /= profile->kvd_hash_double_parts + 3400 profile->kvd_hash_single_parts; 3401 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3402 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3403 double_size, 3404 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3405 MLXSW_SP_RESOURCE_KVD, 3406 &hash_double_size_params); 3407 if (err) 3408 return err; 3409 3410 single_size = kvd_size - double_size - linear_size; 3411 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3412 single_size, 3413 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3414 MLXSW_SP_RESOURCE_KVD, 3415 &hash_single_size_params); 3416 if (err) 3417 return err; 3418 3419 return 0; 3420 } 3421 3422 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3423 { 3424 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3425 struct devlink_resource_size_params kvd_size_params; 3426 u32 kvd_size; 3427 3428 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3429 return -EIO; 3430 3431 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3432 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size, 3433 MLXSW_SP_KVD_GRANULARITY, 3434 DEVLINK_RESOURCE_UNIT_ENTRY); 3435 3436 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3437 kvd_size, MLXSW_SP_RESOURCE_KVD, 3438 DEVLINK_RESOURCE_ID_PARENT_TOP, 3439 &kvd_size_params); 3440 } 3441 3442 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core) 3443 { 3444 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3445 struct devlink_resource_size_params span_size_params; 3446 u32 max_span; 3447 3448 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN)) 3449 return -EIO; 3450 3451 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN); 3452 devlink_resource_size_params_init(&span_size_params, max_span, max_span, 3453 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3454 3455 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN, 3456 max_span, MLXSW_SP_RESOURCE_SPAN, 3457 DEVLINK_RESOURCE_ID_PARENT_TOP, 3458 &span_size_params); 3459 } 3460 3461 static int 3462 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core) 3463 { 3464 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3465 struct devlink_resource_size_params size_params; 3466 u8 max_rif_mac_profiles; 3467 3468 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES)) 3469 max_rif_mac_profiles = 1; 3470 else 3471 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core, 3472 MAX_RIF_MAC_PROFILES); 3473 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles, 3474 max_rif_mac_profiles, 1, 3475 DEVLINK_RESOURCE_UNIT_ENTRY); 3476 3477 return devlink_resource_register(devlink, 3478 "rif_mac_profiles", 3479 max_rif_mac_profiles, 3480 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES, 3481 DEVLINK_RESOURCE_ID_PARENT_TOP, 3482 &size_params); 3483 } 3484 3485 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 3486 { 3487 int err; 3488 3489 err = mlxsw_sp1_resources_kvd_register(mlxsw_core); 3490 if (err) 3491 return err; 3492 3493 err = mlxsw_sp_resources_span_register(mlxsw_core); 3494 if (err) 3495 goto err_resources_span_register; 3496 3497 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3498 if (err) 3499 goto err_resources_counter_register; 3500 3501 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3502 if (err) 3503 goto err_policer_resources_register; 3504 3505 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3506 if (err) 3507 goto err_resources_rif_mac_profile_register; 3508 3509 return 0; 3510 3511 err_resources_rif_mac_profile_register: 3512 err_policer_resources_register: 3513 err_resources_counter_register: 3514 err_resources_span_register: 3515 devlink_resources_unregister(priv_to_devlink(mlxsw_core)); 3516 return err; 3517 } 3518 3519 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 3520 { 3521 int err; 3522 3523 err = mlxsw_sp2_resources_kvd_register(mlxsw_core); 3524 if (err) 3525 return err; 3526 3527 err = mlxsw_sp_resources_span_register(mlxsw_core); 3528 if (err) 3529 goto err_resources_span_register; 3530 3531 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3532 if (err) 3533 goto err_resources_counter_register; 3534 3535 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3536 if (err) 3537 goto err_policer_resources_register; 3538 3539 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3540 if (err) 3541 goto err_resources_rif_mac_profile_register; 3542 3543 return 0; 3544 3545 err_resources_rif_mac_profile_register: 3546 err_policer_resources_register: 3547 err_resources_counter_register: 3548 err_resources_span_register: 3549 devlink_resources_unregister(priv_to_devlink(mlxsw_core)); 3550 return err; 3551 } 3552 3553 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3554 const struct mlxsw_config_profile *profile, 3555 u64 *p_single_size, u64 *p_double_size, 3556 u64 *p_linear_size) 3557 { 3558 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3559 u32 double_size; 3560 int err; 3561 3562 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3563 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3564 return -EIO; 3565 3566 /* The hash part is what left of the kvd without the 3567 * linear part. It is split to the single size and 3568 * double size by the parts ratio from the profile. 3569 * Both sizes must be a multiplications of the 3570 * granularity from the profile. In case the user 3571 * provided the sizes they are obtained via devlink. 3572 */ 3573 err = devlink_resource_size_get(devlink, 3574 MLXSW_SP_RESOURCE_KVD_LINEAR, 3575 p_linear_size); 3576 if (err) 3577 *p_linear_size = profile->kvd_linear_size; 3578 3579 err = devlink_resource_size_get(devlink, 3580 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3581 p_double_size); 3582 if (err) { 3583 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3584 *p_linear_size; 3585 double_size *= profile->kvd_hash_double_parts; 3586 double_size /= profile->kvd_hash_double_parts + 3587 profile->kvd_hash_single_parts; 3588 *p_double_size = rounddown(double_size, 3589 MLXSW_SP_KVD_GRANULARITY); 3590 } 3591 3592 err = devlink_resource_size_get(devlink, 3593 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3594 p_single_size); 3595 if (err) 3596 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3597 *p_double_size - *p_linear_size; 3598 3599 /* Check results are legal. */ 3600 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3601 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3602 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3603 return -EIO; 3604 3605 return 0; 3606 } 3607 3608 static int 3609 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id, 3610 struct devlink_param_gset_ctx *ctx) 3611 { 3612 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3613 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3614 3615 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp); 3616 return 0; 3617 } 3618 3619 static int 3620 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id, 3621 struct devlink_param_gset_ctx *ctx) 3622 { 3623 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 3624 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3625 3626 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32); 3627 } 3628 3629 static const struct devlink_param mlxsw_sp2_devlink_params[] = { 3630 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 3631 "acl_region_rehash_interval", 3632 DEVLINK_PARAM_TYPE_U32, 3633 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3634 mlxsw_sp_params_acl_region_rehash_intrvl_get, 3635 mlxsw_sp_params_acl_region_rehash_intrvl_set, 3636 NULL), 3637 }; 3638 3639 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core) 3640 { 3641 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3642 union devlink_param_value value; 3643 int err; 3644 3645 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params, 3646 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 3647 if (err) 3648 return err; 3649 3650 value.vu32 = 0; 3651 devlink_param_driverinit_value_set(devlink, 3652 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 3653 value); 3654 return 0; 3655 } 3656 3657 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core) 3658 { 3659 devlink_params_unregister(priv_to_devlink(mlxsw_core), 3660 mlxsw_sp2_devlink_params, 3661 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 3662 } 3663 3664 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core, 3665 struct sk_buff *skb, u16 local_port) 3666 { 3667 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3668 3669 skb_pull(skb, MLXSW_TXHDR_LEN); 3670 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port); 3671 } 3672 3673 static struct mlxsw_driver mlxsw_sp1_driver = { 3674 .kind = mlxsw_sp1_driver_name, 3675 .priv_size = sizeof(struct mlxsw_sp), 3676 .fw_req_rev = &mlxsw_sp1_fw_rev, 3677 .fw_filename = MLXSW_SP1_FW_FILENAME, 3678 .init = mlxsw_sp1_init, 3679 .fini = mlxsw_sp_fini, 3680 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3681 .port_split = mlxsw_sp_port_split, 3682 .port_unsplit = mlxsw_sp_port_unsplit, 3683 .sb_pool_get = mlxsw_sp_sb_pool_get, 3684 .sb_pool_set = mlxsw_sp_sb_pool_set, 3685 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3686 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3687 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3688 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3689 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3690 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3691 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3692 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3693 .trap_init = mlxsw_sp_trap_init, 3694 .trap_fini = mlxsw_sp_trap_fini, 3695 .trap_action_set = mlxsw_sp_trap_action_set, 3696 .trap_group_init = mlxsw_sp_trap_group_init, 3697 .trap_group_set = mlxsw_sp_trap_group_set, 3698 .trap_policer_init = mlxsw_sp_trap_policer_init, 3699 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3700 .trap_policer_set = mlxsw_sp_trap_policer_set, 3701 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3702 .txhdr_construct = mlxsw_sp_txhdr_construct, 3703 .resources_register = mlxsw_sp1_resources_register, 3704 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 3705 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3706 .txhdr_len = MLXSW_TXHDR_LEN, 3707 .profile = &mlxsw_sp1_config_profile, 3708 .res_query_enabled = true, 3709 .fw_fatal_enabled = true, 3710 .temp_warn_enabled = true, 3711 }; 3712 3713 static struct mlxsw_driver mlxsw_sp2_driver = { 3714 .kind = mlxsw_sp2_driver_name, 3715 .priv_size = sizeof(struct mlxsw_sp), 3716 .fw_req_rev = &mlxsw_sp2_fw_rev, 3717 .fw_filename = MLXSW_SP2_FW_FILENAME, 3718 .init = mlxsw_sp2_init, 3719 .fini = mlxsw_sp_fini, 3720 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3721 .port_split = mlxsw_sp_port_split, 3722 .port_unsplit = mlxsw_sp_port_unsplit, 3723 .sb_pool_get = mlxsw_sp_sb_pool_get, 3724 .sb_pool_set = mlxsw_sp_sb_pool_set, 3725 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3726 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3727 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3728 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3729 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3730 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3731 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3732 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3733 .trap_init = mlxsw_sp_trap_init, 3734 .trap_fini = mlxsw_sp_trap_fini, 3735 .trap_action_set = mlxsw_sp_trap_action_set, 3736 .trap_group_init = mlxsw_sp_trap_group_init, 3737 .trap_group_set = mlxsw_sp_trap_group_set, 3738 .trap_policer_init = mlxsw_sp_trap_policer_init, 3739 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3740 .trap_policer_set = mlxsw_sp_trap_policer_set, 3741 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3742 .txhdr_construct = mlxsw_sp_txhdr_construct, 3743 .resources_register = mlxsw_sp2_resources_register, 3744 .params_register = mlxsw_sp2_params_register, 3745 .params_unregister = mlxsw_sp2_params_unregister, 3746 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3747 .txhdr_len = MLXSW_TXHDR_LEN, 3748 .profile = &mlxsw_sp2_config_profile, 3749 .res_query_enabled = true, 3750 .fw_fatal_enabled = true, 3751 .temp_warn_enabled = true, 3752 }; 3753 3754 static struct mlxsw_driver mlxsw_sp3_driver = { 3755 .kind = mlxsw_sp3_driver_name, 3756 .priv_size = sizeof(struct mlxsw_sp), 3757 .fw_req_rev = &mlxsw_sp3_fw_rev, 3758 .fw_filename = MLXSW_SP3_FW_FILENAME, 3759 .init = mlxsw_sp3_init, 3760 .fini = mlxsw_sp_fini, 3761 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3762 .port_split = mlxsw_sp_port_split, 3763 .port_unsplit = mlxsw_sp_port_unsplit, 3764 .sb_pool_get = mlxsw_sp_sb_pool_get, 3765 .sb_pool_set = mlxsw_sp_sb_pool_set, 3766 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3767 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3768 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3769 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3770 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3771 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3772 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3773 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3774 .trap_init = mlxsw_sp_trap_init, 3775 .trap_fini = mlxsw_sp_trap_fini, 3776 .trap_action_set = mlxsw_sp_trap_action_set, 3777 .trap_group_init = mlxsw_sp_trap_group_init, 3778 .trap_group_set = mlxsw_sp_trap_group_set, 3779 .trap_policer_init = mlxsw_sp_trap_policer_init, 3780 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3781 .trap_policer_set = mlxsw_sp_trap_policer_set, 3782 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3783 .txhdr_construct = mlxsw_sp_txhdr_construct, 3784 .resources_register = mlxsw_sp2_resources_register, 3785 .params_register = mlxsw_sp2_params_register, 3786 .params_unregister = mlxsw_sp2_params_unregister, 3787 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3788 .txhdr_len = MLXSW_TXHDR_LEN, 3789 .profile = &mlxsw_sp2_config_profile, 3790 .res_query_enabled = true, 3791 .fw_fatal_enabled = true, 3792 .temp_warn_enabled = true, 3793 }; 3794 3795 static struct mlxsw_driver mlxsw_sp4_driver = { 3796 .kind = mlxsw_sp4_driver_name, 3797 .priv_size = sizeof(struct mlxsw_sp), 3798 .init = mlxsw_sp4_init, 3799 .fini = mlxsw_sp_fini, 3800 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 3801 .port_split = mlxsw_sp_port_split, 3802 .port_unsplit = mlxsw_sp_port_unsplit, 3803 .sb_pool_get = mlxsw_sp_sb_pool_get, 3804 .sb_pool_set = mlxsw_sp_sb_pool_set, 3805 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3806 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3807 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3808 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3809 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3810 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3811 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3812 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3813 .trap_init = mlxsw_sp_trap_init, 3814 .trap_fini = mlxsw_sp_trap_fini, 3815 .trap_action_set = mlxsw_sp_trap_action_set, 3816 .trap_group_init = mlxsw_sp_trap_group_init, 3817 .trap_group_set = mlxsw_sp_trap_group_set, 3818 .trap_policer_init = mlxsw_sp_trap_policer_init, 3819 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3820 .trap_policer_set = mlxsw_sp_trap_policer_set, 3821 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3822 .txhdr_construct = mlxsw_sp_txhdr_construct, 3823 .resources_register = mlxsw_sp2_resources_register, 3824 .params_register = mlxsw_sp2_params_register, 3825 .params_unregister = mlxsw_sp2_params_unregister, 3826 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3827 .txhdr_len = MLXSW_TXHDR_LEN, 3828 .profile = &mlxsw_sp2_config_profile, 3829 .res_query_enabled = true, 3830 .fw_fatal_enabled = true, 3831 .temp_warn_enabled = true, 3832 }; 3833 3834 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 3835 { 3836 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 3837 } 3838 3839 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, 3840 struct netdev_nested_priv *priv) 3841 { 3842 int ret = 0; 3843 3844 if (mlxsw_sp_port_dev_check(lower_dev)) { 3845 priv->data = (void *)netdev_priv(lower_dev); 3846 ret = 1; 3847 } 3848 3849 return ret; 3850 } 3851 3852 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 3853 { 3854 struct netdev_nested_priv priv = { 3855 .data = NULL, 3856 }; 3857 3858 if (mlxsw_sp_port_dev_check(dev)) 3859 return netdev_priv(dev); 3860 3861 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv); 3862 3863 return (struct mlxsw_sp_port *)priv.data; 3864 } 3865 3866 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 3867 { 3868 struct mlxsw_sp_port *mlxsw_sp_port; 3869 3870 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 3871 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 3872 } 3873 3874 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 3875 { 3876 struct netdev_nested_priv priv = { 3877 .data = NULL, 3878 }; 3879 3880 if (mlxsw_sp_port_dev_check(dev)) 3881 return netdev_priv(dev); 3882 3883 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 3884 &priv); 3885 3886 return (struct mlxsw_sp_port *)priv.data; 3887 } 3888 3889 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 3890 { 3891 struct mlxsw_sp_port *mlxsw_sp_port; 3892 3893 rcu_read_lock(); 3894 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 3895 if (mlxsw_sp_port) 3896 dev_hold(mlxsw_sp_port->dev); 3897 rcu_read_unlock(); 3898 return mlxsw_sp_port; 3899 } 3900 3901 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 3902 { 3903 dev_put(mlxsw_sp_port->dev); 3904 } 3905 3906 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp) 3907 { 3908 char mprs_pl[MLXSW_REG_MPRS_LEN]; 3909 int err = 0; 3910 3911 mutex_lock(&mlxsw_sp->parsing.lock); 3912 3913 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref)) 3914 goto out_unlock; 3915 3916 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH, 3917 mlxsw_sp->parsing.vxlan_udp_dport); 3918 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 3919 if (err) 3920 goto out_unlock; 3921 3922 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH; 3923 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1); 3924 3925 out_unlock: 3926 mutex_unlock(&mlxsw_sp->parsing.lock); 3927 return err; 3928 } 3929 3930 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp) 3931 { 3932 char mprs_pl[MLXSW_REG_MPRS_LEN]; 3933 3934 mutex_lock(&mlxsw_sp->parsing.lock); 3935 3936 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref)) 3937 goto out_unlock; 3938 3939 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH, 3940 mlxsw_sp->parsing.vxlan_udp_dport); 3941 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 3942 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 3943 3944 out_unlock: 3945 mutex_unlock(&mlxsw_sp->parsing.lock); 3946 } 3947 3948 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp, 3949 __be16 udp_dport) 3950 { 3951 char mprs_pl[MLXSW_REG_MPRS_LEN]; 3952 int err; 3953 3954 mutex_lock(&mlxsw_sp->parsing.lock); 3955 3956 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth, 3957 be16_to_cpu(udp_dport)); 3958 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 3959 if (err) 3960 goto out_unlock; 3961 3962 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport); 3963 3964 out_unlock: 3965 mutex_unlock(&mlxsw_sp->parsing.lock); 3966 return err; 3967 } 3968 3969 static void 3970 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port, 3971 struct net_device *lag_dev) 3972 { 3973 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev); 3974 struct net_device *upper_dev; 3975 struct list_head *iter; 3976 3977 if (netif_is_bridge_port(lag_dev)) 3978 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev); 3979 3980 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 3981 if (!netif_is_bridge_port(upper_dev)) 3982 continue; 3983 br_dev = netdev_master_upper_dev_get(upper_dev); 3984 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev); 3985 } 3986 } 3987 3988 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 3989 { 3990 char sldr_pl[MLXSW_REG_SLDR_LEN]; 3991 3992 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 3993 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 3994 } 3995 3996 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 3997 { 3998 char sldr_pl[MLXSW_REG_SLDR_LEN]; 3999 4000 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4001 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4002 } 4003 4004 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4005 u16 lag_id, u8 port_index) 4006 { 4007 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4008 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4009 4010 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4011 lag_id, port_index); 4012 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4013 } 4014 4015 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4016 u16 lag_id) 4017 { 4018 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4019 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4020 4021 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4022 lag_id); 4023 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4024 } 4025 4026 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4027 u16 lag_id) 4028 { 4029 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4030 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4031 4032 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4033 lag_id); 4034 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4035 } 4036 4037 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4038 u16 lag_id) 4039 { 4040 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4041 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4042 4043 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4044 lag_id); 4045 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4046 } 4047 4048 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4049 struct net_device *lag_dev, 4050 u16 *p_lag_id) 4051 { 4052 struct mlxsw_sp_upper *lag; 4053 int free_lag_id = -1; 4054 u64 max_lag; 4055 int i; 4056 4057 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 4058 for (i = 0; i < max_lag; i++) { 4059 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4060 if (lag->ref_count) { 4061 if (lag->dev == lag_dev) { 4062 *p_lag_id = i; 4063 return 0; 4064 } 4065 } else if (free_lag_id < 0) { 4066 free_lag_id = i; 4067 } 4068 } 4069 if (free_lag_id < 0) 4070 return -EBUSY; 4071 *p_lag_id = free_lag_id; 4072 return 0; 4073 } 4074 4075 static bool 4076 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4077 struct net_device *lag_dev, 4078 struct netdev_lag_upper_info *lag_upper_info, 4079 struct netlink_ext_ack *extack) 4080 { 4081 u16 lag_id; 4082 4083 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4084 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4085 return false; 4086 } 4087 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4088 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4089 return false; 4090 } 4091 return true; 4092 } 4093 4094 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4095 u16 lag_id, u8 *p_port_index) 4096 { 4097 u64 max_lag_members; 4098 int i; 4099 4100 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4101 MAX_LAG_MEMBERS); 4102 for (i = 0; i < max_lag_members; i++) { 4103 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4104 *p_port_index = i; 4105 return 0; 4106 } 4107 } 4108 return -EBUSY; 4109 } 4110 4111 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4112 struct net_device *lag_dev, 4113 struct netlink_ext_ack *extack) 4114 { 4115 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4116 struct mlxsw_sp_upper *lag; 4117 u16 lag_id; 4118 u8 port_index; 4119 int err; 4120 4121 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4122 if (err) 4123 return err; 4124 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4125 if (!lag->ref_count) { 4126 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4127 if (err) 4128 return err; 4129 lag->dev = lag_dev; 4130 } 4131 4132 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4133 if (err) 4134 return err; 4135 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4136 if (err) 4137 goto err_col_port_add; 4138 4139 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4140 mlxsw_sp_port->local_port); 4141 mlxsw_sp_port->lag_id = lag_id; 4142 mlxsw_sp_port->lagged = 1; 4143 lag->ref_count++; 4144 4145 /* Port is no longer usable as a router interface */ 4146 if (mlxsw_sp_port->default_vlan->fid) 4147 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan); 4148 4149 /* Join a router interface configured on the LAG, if exists */ 4150 err = mlxsw_sp_port_vlan_router_join(mlxsw_sp_port->default_vlan, 4151 lag_dev, extack); 4152 if (err) 4153 goto err_router_join; 4154 4155 return 0; 4156 4157 err_router_join: 4158 lag->ref_count--; 4159 mlxsw_sp_port->lagged = 0; 4160 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4161 mlxsw_sp_port->local_port); 4162 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4163 err_col_port_add: 4164 if (!lag->ref_count) 4165 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4166 return err; 4167 } 4168 4169 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4170 struct net_device *lag_dev) 4171 { 4172 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4173 u16 lag_id = mlxsw_sp_port->lag_id; 4174 struct mlxsw_sp_upper *lag; 4175 4176 if (!mlxsw_sp_port->lagged) 4177 return; 4178 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4179 WARN_ON(lag->ref_count == 0); 4180 4181 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4182 4183 /* Any VLANs configured on the port are no longer valid */ 4184 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false); 4185 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan); 4186 /* Make the LAG and its directly linked uppers leave bridges they 4187 * are memeber in 4188 */ 4189 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev); 4190 4191 if (lag->ref_count == 1) 4192 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4193 4194 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4195 mlxsw_sp_port->local_port); 4196 mlxsw_sp_port->lagged = 0; 4197 lag->ref_count--; 4198 4199 /* Make sure untagged frames are allowed to ingress */ 4200 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 4201 ETH_P_8021Q); 4202 } 4203 4204 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4205 u16 lag_id) 4206 { 4207 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4208 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4209 4210 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4211 mlxsw_sp_port->local_port); 4212 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4213 } 4214 4215 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4216 u16 lag_id) 4217 { 4218 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4219 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4220 4221 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4222 mlxsw_sp_port->local_port); 4223 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4224 } 4225 4226 static int 4227 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port) 4228 { 4229 int err; 4230 4231 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, 4232 mlxsw_sp_port->lag_id); 4233 if (err) 4234 return err; 4235 4236 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4237 if (err) 4238 goto err_dist_port_add; 4239 4240 return 0; 4241 4242 err_dist_port_add: 4243 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4244 return err; 4245 } 4246 4247 static int 4248 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port) 4249 { 4250 int err; 4251 4252 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4253 mlxsw_sp_port->lag_id); 4254 if (err) 4255 return err; 4256 4257 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, 4258 mlxsw_sp_port->lag_id); 4259 if (err) 4260 goto err_col_port_disable; 4261 4262 return 0; 4263 4264 err_col_port_disable: 4265 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4266 return err; 4267 } 4268 4269 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4270 struct netdev_lag_lower_state_info *info) 4271 { 4272 if (info->tx_enabled) 4273 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port); 4274 else 4275 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4276 } 4277 4278 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4279 bool enable) 4280 { 4281 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4282 enum mlxsw_reg_spms_state spms_state; 4283 char *spms_pl; 4284 u16 vid; 4285 int err; 4286 4287 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4288 MLXSW_REG_SPMS_STATE_DISCARDING; 4289 4290 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4291 if (!spms_pl) 4292 return -ENOMEM; 4293 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4294 4295 for (vid = 0; vid < VLAN_N_VID; vid++) 4296 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4297 4298 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4299 kfree(spms_pl); 4300 return err; 4301 } 4302 4303 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4304 { 4305 u16 vid = 1; 4306 int err; 4307 4308 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4309 if (err) 4310 return err; 4311 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4312 if (err) 4313 goto err_port_stp_set; 4314 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4315 true, false); 4316 if (err) 4317 goto err_port_vlan_set; 4318 4319 for (; vid <= VLAN_N_VID - 1; vid++) { 4320 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4321 vid, false); 4322 if (err) 4323 goto err_vid_learning_set; 4324 } 4325 4326 return 0; 4327 4328 err_vid_learning_set: 4329 for (vid--; vid >= 1; vid--) 4330 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4331 err_port_vlan_set: 4332 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4333 err_port_stp_set: 4334 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4335 return err; 4336 } 4337 4338 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4339 { 4340 u16 vid; 4341 4342 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4343 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4344 vid, true); 4345 4346 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4347 false, false); 4348 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4349 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4350 } 4351 4352 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4353 { 4354 unsigned int num_vxlans = 0; 4355 struct net_device *dev; 4356 struct list_head *iter; 4357 4358 netdev_for_each_lower_dev(br_dev, dev, iter) { 4359 if (netif_is_vxlan(dev)) 4360 num_vxlans++; 4361 } 4362 4363 return num_vxlans > 1; 4364 } 4365 4366 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev) 4367 { 4368 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0}; 4369 struct net_device *dev; 4370 struct list_head *iter; 4371 4372 netdev_for_each_lower_dev(br_dev, dev, iter) { 4373 u16 pvid; 4374 int err; 4375 4376 if (!netif_is_vxlan(dev)) 4377 continue; 4378 4379 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid); 4380 if (err || !pvid) 4381 continue; 4382 4383 if (test_and_set_bit(pvid, vlans)) 4384 return false; 4385 } 4386 4387 return true; 4388 } 4389 4390 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4391 struct netlink_ext_ack *extack) 4392 { 4393 if (br_multicast_enabled(br_dev)) { 4394 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4395 return false; 4396 } 4397 4398 if (!br_vlan_enabled(br_dev) && 4399 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4400 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4401 return false; 4402 } 4403 4404 if (br_vlan_enabled(br_dev) && 4405 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) { 4406 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged"); 4407 return false; 4408 } 4409 4410 return true; 4411 } 4412 4413 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4414 struct net_device *dev, 4415 unsigned long event, void *ptr) 4416 { 4417 struct netdev_notifier_changeupper_info *info; 4418 struct mlxsw_sp_port *mlxsw_sp_port; 4419 struct netlink_ext_ack *extack; 4420 struct net_device *upper_dev; 4421 struct mlxsw_sp *mlxsw_sp; 4422 int err = 0; 4423 u16 proto; 4424 4425 mlxsw_sp_port = netdev_priv(dev); 4426 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4427 info = ptr; 4428 extack = netdev_notifier_info_to_extack(&info->info); 4429 4430 switch (event) { 4431 case NETDEV_PRECHANGEUPPER: 4432 upper_dev = info->upper_dev; 4433 if (!is_vlan_dev(upper_dev) && 4434 !netif_is_lag_master(upper_dev) && 4435 !netif_is_bridge_master(upper_dev) && 4436 !netif_is_ovs_master(upper_dev) && 4437 !netif_is_macvlan(upper_dev)) { 4438 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4439 return -EINVAL; 4440 } 4441 if (!info->linking) 4442 break; 4443 if (netif_is_bridge_master(upper_dev) && 4444 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4445 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4446 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4447 return -EOPNOTSUPP; 4448 if (netdev_has_any_upper_dev(upper_dev) && 4449 (!netif_is_bridge_master(upper_dev) || 4450 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4451 upper_dev))) { 4452 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4453 return -EINVAL; 4454 } 4455 if (netif_is_lag_master(upper_dev) && 4456 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4457 info->upper_info, extack)) 4458 return -EINVAL; 4459 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4460 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4461 return -EINVAL; 4462 } 4463 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4464 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4465 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4466 return -EINVAL; 4467 } 4468 if (netif_is_macvlan(upper_dev) && 4469 !mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) { 4470 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4471 return -EOPNOTSUPP; 4472 } 4473 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4474 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4475 return -EINVAL; 4476 } 4477 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4478 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4479 return -EINVAL; 4480 } 4481 if (netif_is_bridge_master(upper_dev)) { 4482 br_vlan_get_proto(upper_dev, &proto); 4483 if (br_vlan_enabled(upper_dev) && 4484 proto != ETH_P_8021Q && proto != ETH_P_8021AD) { 4485 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported"); 4486 return -EOPNOTSUPP; 4487 } 4488 if (vlan_uses_dev(lower_dev) && 4489 br_vlan_enabled(upper_dev) && 4490 proto == ETH_P_8021AD) { 4491 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported"); 4492 return -EOPNOTSUPP; 4493 } 4494 } 4495 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) { 4496 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev); 4497 4498 if (br_vlan_enabled(br_dev)) { 4499 br_vlan_get_proto(br_dev, &proto); 4500 if (proto == ETH_P_8021AD) { 4501 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge"); 4502 return -EOPNOTSUPP; 4503 } 4504 } 4505 } 4506 if (is_vlan_dev(upper_dev) && 4507 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4508 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4509 return -EOPNOTSUPP; 4510 } 4511 break; 4512 case NETDEV_CHANGEUPPER: 4513 upper_dev = info->upper_dev; 4514 if (netif_is_bridge_master(upper_dev)) { 4515 if (info->linking) 4516 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4517 lower_dev, 4518 upper_dev, 4519 extack); 4520 else 4521 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4522 lower_dev, 4523 upper_dev); 4524 } else if (netif_is_lag_master(upper_dev)) { 4525 if (info->linking) { 4526 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4527 upper_dev, extack); 4528 } else { 4529 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4530 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4531 upper_dev); 4532 } 4533 } else if (netif_is_ovs_master(upper_dev)) { 4534 if (info->linking) 4535 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4536 else 4537 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4538 } else if (netif_is_macvlan(upper_dev)) { 4539 if (!info->linking) 4540 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4541 } else if (is_vlan_dev(upper_dev)) { 4542 struct net_device *br_dev; 4543 4544 if (!netif_is_bridge_port(upper_dev)) 4545 break; 4546 if (info->linking) 4547 break; 4548 br_dev = netdev_master_upper_dev_get(upper_dev); 4549 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, 4550 br_dev); 4551 } 4552 break; 4553 } 4554 4555 return err; 4556 } 4557 4558 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4559 unsigned long event, void *ptr) 4560 { 4561 struct netdev_notifier_changelowerstate_info *info; 4562 struct mlxsw_sp_port *mlxsw_sp_port; 4563 int err; 4564 4565 mlxsw_sp_port = netdev_priv(dev); 4566 info = ptr; 4567 4568 switch (event) { 4569 case NETDEV_CHANGELOWERSTATE: 4570 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4571 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4572 info->lower_state_info); 4573 if (err) 4574 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4575 } 4576 break; 4577 } 4578 4579 return 0; 4580 } 4581 4582 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4583 struct net_device *port_dev, 4584 unsigned long event, void *ptr) 4585 { 4586 switch (event) { 4587 case NETDEV_PRECHANGEUPPER: 4588 case NETDEV_CHANGEUPPER: 4589 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4590 event, ptr); 4591 case NETDEV_CHANGELOWERSTATE: 4592 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4593 ptr); 4594 } 4595 4596 return 0; 4597 } 4598 4599 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4600 unsigned long event, void *ptr) 4601 { 4602 struct net_device *dev; 4603 struct list_head *iter; 4604 int ret; 4605 4606 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4607 if (mlxsw_sp_port_dev_check(dev)) { 4608 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4609 ptr); 4610 if (ret) 4611 return ret; 4612 } 4613 } 4614 4615 return 0; 4616 } 4617 4618 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4619 struct net_device *dev, 4620 unsigned long event, void *ptr, 4621 u16 vid) 4622 { 4623 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4624 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4625 struct netdev_notifier_changeupper_info *info = ptr; 4626 struct netlink_ext_ack *extack; 4627 struct net_device *upper_dev; 4628 int err = 0; 4629 4630 extack = netdev_notifier_info_to_extack(&info->info); 4631 4632 switch (event) { 4633 case NETDEV_PRECHANGEUPPER: 4634 upper_dev = info->upper_dev; 4635 if (!netif_is_bridge_master(upper_dev) && 4636 !netif_is_macvlan(upper_dev)) { 4637 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4638 return -EINVAL; 4639 } 4640 if (!info->linking) 4641 break; 4642 if (netif_is_bridge_master(upper_dev) && 4643 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4644 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4645 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4646 return -EOPNOTSUPP; 4647 if (netdev_has_any_upper_dev(upper_dev) && 4648 (!netif_is_bridge_master(upper_dev) || 4649 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4650 upper_dev))) { 4651 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4652 return -EINVAL; 4653 } 4654 if (netif_is_macvlan(upper_dev) && 4655 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) { 4656 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4657 return -EOPNOTSUPP; 4658 } 4659 break; 4660 case NETDEV_CHANGEUPPER: 4661 upper_dev = info->upper_dev; 4662 if (netif_is_bridge_master(upper_dev)) { 4663 if (info->linking) 4664 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4665 vlan_dev, 4666 upper_dev, 4667 extack); 4668 else 4669 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4670 vlan_dev, 4671 upper_dev); 4672 } else if (netif_is_macvlan(upper_dev)) { 4673 if (!info->linking) 4674 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4675 } else { 4676 err = -EINVAL; 4677 WARN_ON(1); 4678 } 4679 break; 4680 } 4681 4682 return err; 4683 } 4684 4685 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4686 struct net_device *lag_dev, 4687 unsigned long event, 4688 void *ptr, u16 vid) 4689 { 4690 struct net_device *dev; 4691 struct list_head *iter; 4692 int ret; 4693 4694 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4695 if (mlxsw_sp_port_dev_check(dev)) { 4696 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4697 event, ptr, 4698 vid); 4699 if (ret) 4700 return ret; 4701 } 4702 } 4703 4704 return 0; 4705 } 4706 4707 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev, 4708 struct net_device *br_dev, 4709 unsigned long event, void *ptr, 4710 u16 vid) 4711 { 4712 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev); 4713 struct netdev_notifier_changeupper_info *info = ptr; 4714 struct netlink_ext_ack *extack; 4715 struct net_device *upper_dev; 4716 4717 if (!mlxsw_sp) 4718 return 0; 4719 4720 extack = netdev_notifier_info_to_extack(&info->info); 4721 4722 switch (event) { 4723 case NETDEV_PRECHANGEUPPER: 4724 upper_dev = info->upper_dev; 4725 if (!netif_is_macvlan(upper_dev)) { 4726 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4727 return -EOPNOTSUPP; 4728 } 4729 if (!info->linking) 4730 break; 4731 if (netif_is_macvlan(upper_dev) && 4732 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) { 4733 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4734 return -EOPNOTSUPP; 4735 } 4736 break; 4737 case NETDEV_CHANGEUPPER: 4738 upper_dev = info->upper_dev; 4739 if (info->linking) 4740 break; 4741 if (netif_is_macvlan(upper_dev)) 4742 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4743 break; 4744 } 4745 4746 return 0; 4747 } 4748 4749 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4750 unsigned long event, void *ptr) 4751 { 4752 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4753 u16 vid = vlan_dev_vlan_id(vlan_dev); 4754 4755 if (mlxsw_sp_port_dev_check(real_dev)) 4756 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 4757 event, ptr, vid); 4758 else if (netif_is_lag_master(real_dev)) 4759 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 4760 real_dev, event, 4761 ptr, vid); 4762 else if (netif_is_bridge_master(real_dev)) 4763 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev, 4764 event, ptr, vid); 4765 4766 return 0; 4767 } 4768 4769 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 4770 unsigned long event, void *ptr) 4771 { 4772 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 4773 struct netdev_notifier_changeupper_info *info = ptr; 4774 struct netlink_ext_ack *extack; 4775 struct net_device *upper_dev; 4776 u16 proto; 4777 4778 if (!mlxsw_sp) 4779 return 0; 4780 4781 extack = netdev_notifier_info_to_extack(&info->info); 4782 4783 switch (event) { 4784 case NETDEV_PRECHANGEUPPER: 4785 upper_dev = info->upper_dev; 4786 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) { 4787 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4788 return -EOPNOTSUPP; 4789 } 4790 if (!info->linking) 4791 break; 4792 if (br_vlan_enabled(br_dev)) { 4793 br_vlan_get_proto(br_dev, &proto); 4794 if (proto == ETH_P_8021AD) { 4795 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge"); 4796 return -EOPNOTSUPP; 4797 } 4798 } 4799 if (is_vlan_dev(upper_dev) && 4800 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4801 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4802 return -EOPNOTSUPP; 4803 } 4804 if (netif_is_macvlan(upper_dev) && 4805 !mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) { 4806 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4807 return -EOPNOTSUPP; 4808 } 4809 break; 4810 case NETDEV_CHANGEUPPER: 4811 upper_dev = info->upper_dev; 4812 if (info->linking) 4813 break; 4814 if (is_vlan_dev(upper_dev)) 4815 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 4816 if (netif_is_macvlan(upper_dev)) 4817 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4818 break; 4819 } 4820 4821 return 0; 4822 } 4823 4824 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 4825 unsigned long event, void *ptr) 4826 { 4827 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 4828 struct netdev_notifier_changeupper_info *info = ptr; 4829 struct netlink_ext_ack *extack; 4830 4831 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 4832 return 0; 4833 4834 extack = netdev_notifier_info_to_extack(&info->info); 4835 4836 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */ 4837 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4838 4839 return -EOPNOTSUPP; 4840 } 4841 4842 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 4843 { 4844 struct netdev_notifier_changeupper_info *info = ptr; 4845 4846 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 4847 return false; 4848 return netif_is_l3_master(info->upper_dev); 4849 } 4850 4851 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 4852 struct net_device *dev, 4853 unsigned long event, void *ptr) 4854 { 4855 struct netdev_notifier_changeupper_info *cu_info; 4856 struct netdev_notifier_info *info = ptr; 4857 struct netlink_ext_ack *extack; 4858 struct net_device *upper_dev; 4859 4860 extack = netdev_notifier_info_to_extack(info); 4861 4862 switch (event) { 4863 case NETDEV_CHANGEUPPER: 4864 cu_info = container_of(info, 4865 struct netdev_notifier_changeupper_info, 4866 info); 4867 upper_dev = cu_info->upper_dev; 4868 if (!netif_is_bridge_master(upper_dev)) 4869 return 0; 4870 if (!mlxsw_sp_lower_get(upper_dev)) 4871 return 0; 4872 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4873 return -EOPNOTSUPP; 4874 if (cu_info->linking) { 4875 if (!netif_running(dev)) 4876 return 0; 4877 /* When the bridge is VLAN-aware, the VNI of the VxLAN 4878 * device needs to be mapped to a VLAN, but at this 4879 * point no VLANs are configured on the VxLAN device 4880 */ 4881 if (br_vlan_enabled(upper_dev)) 4882 return 0; 4883 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 4884 dev, 0, extack); 4885 } else { 4886 /* VLANs were already flushed, which triggered the 4887 * necessary cleanup 4888 */ 4889 if (br_vlan_enabled(upper_dev)) 4890 return 0; 4891 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 4892 } 4893 break; 4894 case NETDEV_PRE_UP: 4895 upper_dev = netdev_master_upper_dev_get(dev); 4896 if (!upper_dev) 4897 return 0; 4898 if (!netif_is_bridge_master(upper_dev)) 4899 return 0; 4900 if (!mlxsw_sp_lower_get(upper_dev)) 4901 return 0; 4902 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0, 4903 extack); 4904 case NETDEV_DOWN: 4905 upper_dev = netdev_master_upper_dev_get(dev); 4906 if (!upper_dev) 4907 return 0; 4908 if (!netif_is_bridge_master(upper_dev)) 4909 return 0; 4910 if (!mlxsw_sp_lower_get(upper_dev)) 4911 return 0; 4912 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 4913 break; 4914 } 4915 4916 return 0; 4917 } 4918 4919 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 4920 unsigned long event, void *ptr) 4921 { 4922 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4923 struct mlxsw_sp_span_entry *span_entry; 4924 struct mlxsw_sp *mlxsw_sp; 4925 int err = 0; 4926 4927 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 4928 if (event == NETDEV_UNREGISTER) { 4929 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 4930 if (span_entry) 4931 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 4932 } 4933 mlxsw_sp_span_respin(mlxsw_sp); 4934 4935 if (netif_is_vxlan(dev)) 4936 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 4937 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 4938 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 4939 event, ptr); 4940 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 4941 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 4942 event, ptr); 4943 else if (event == NETDEV_PRE_CHANGEADDR || 4944 event == NETDEV_CHANGEADDR || 4945 event == NETDEV_CHANGEMTU) 4946 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr); 4947 else if (mlxsw_sp_is_vrf_event(event, ptr)) 4948 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 4949 else if (mlxsw_sp_port_dev_check(dev)) 4950 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 4951 else if (netif_is_lag_master(dev)) 4952 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 4953 else if (is_vlan_dev(dev)) 4954 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 4955 else if (netif_is_bridge_master(dev)) 4956 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 4957 else if (netif_is_macvlan(dev)) 4958 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 4959 4960 return notifier_from_errno(err); 4961 } 4962 4963 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 4964 .notifier_call = mlxsw_sp_inetaddr_valid_event, 4965 }; 4966 4967 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 4968 .notifier_call = mlxsw_sp_inet6addr_valid_event, 4969 }; 4970 4971 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 4972 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 4973 {0, }, 4974 }; 4975 4976 static struct pci_driver mlxsw_sp1_pci_driver = { 4977 .name = mlxsw_sp1_driver_name, 4978 .id_table = mlxsw_sp1_pci_id_table, 4979 }; 4980 4981 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 4982 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 4983 {0, }, 4984 }; 4985 4986 static struct pci_driver mlxsw_sp2_pci_driver = { 4987 .name = mlxsw_sp2_driver_name, 4988 .id_table = mlxsw_sp2_pci_id_table, 4989 }; 4990 4991 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = { 4992 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0}, 4993 {0, }, 4994 }; 4995 4996 static struct pci_driver mlxsw_sp3_pci_driver = { 4997 .name = mlxsw_sp3_driver_name, 4998 .id_table = mlxsw_sp3_pci_id_table, 4999 }; 5000 5001 static const struct pci_device_id mlxsw_sp4_pci_id_table[] = { 5002 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4), 0}, 5003 {0, }, 5004 }; 5005 5006 static struct pci_driver mlxsw_sp4_pci_driver = { 5007 .name = mlxsw_sp4_driver_name, 5008 .id_table = mlxsw_sp4_pci_id_table, 5009 }; 5010 5011 static int __init mlxsw_sp_module_init(void) 5012 { 5013 int err; 5014 5015 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5016 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5017 5018 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5019 if (err) 5020 goto err_sp1_core_driver_register; 5021 5022 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5023 if (err) 5024 goto err_sp2_core_driver_register; 5025 5026 err = mlxsw_core_driver_register(&mlxsw_sp3_driver); 5027 if (err) 5028 goto err_sp3_core_driver_register; 5029 5030 err = mlxsw_core_driver_register(&mlxsw_sp4_driver); 5031 if (err) 5032 goto err_sp4_core_driver_register; 5033 5034 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5035 if (err) 5036 goto err_sp1_pci_driver_register; 5037 5038 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5039 if (err) 5040 goto err_sp2_pci_driver_register; 5041 5042 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver); 5043 if (err) 5044 goto err_sp3_pci_driver_register; 5045 5046 err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver); 5047 if (err) 5048 goto err_sp4_pci_driver_register; 5049 5050 return 0; 5051 5052 err_sp4_pci_driver_register: 5053 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5054 err_sp3_pci_driver_register: 5055 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5056 err_sp2_pci_driver_register: 5057 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5058 err_sp1_pci_driver_register: 5059 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5060 err_sp4_core_driver_register: 5061 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5062 err_sp3_core_driver_register: 5063 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5064 err_sp2_core_driver_register: 5065 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5066 err_sp1_core_driver_register: 5067 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5068 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5069 return err; 5070 } 5071 5072 static void __exit mlxsw_sp_module_exit(void) 5073 { 5074 mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver); 5075 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5076 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5077 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5078 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5079 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5080 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5081 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5082 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5083 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5084 } 5085 5086 module_init(mlxsw_sp_module_init); 5087 module_exit(mlxsw_sp_module_exit); 5088 5089 MODULE_LICENSE("Dual BSD/GPL"); 5090 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5091 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5092 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5093 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5094 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table); 5095 MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table); 5096 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5097 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME); 5098 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME); 5099