1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/random.h> 25 #include <net/switchdev.h> 26 #include <net/pkt_cls.h> 27 #include <net/tc_act/tc_mirred.h> 28 #include <net/netevent.h> 29 #include <net/tc_act/tc_sample.h> 30 #include <net/addrconf.h> 31 32 #include "spectrum.h" 33 #include "pci.h" 34 #include "core.h" 35 #include "core_env.h" 36 #include "reg.h" 37 #include "port.h" 38 #include "trap.h" 39 #include "txheader.h" 40 #include "spectrum_cnt.h" 41 #include "spectrum_dpipe.h" 42 #include "spectrum_acl_flex_actions.h" 43 #include "spectrum_span.h" 44 #include "../mlxfw/mlxfw.h" 45 46 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100) 47 48 #define MLXSW_SP1_FWREV_MAJOR 13 49 #define MLXSW_SP1_FWREV_MINOR 1910 50 #define MLXSW_SP1_FWREV_SUBMINOR 622 51 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 52 53 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 54 .major = MLXSW_SP1_FWREV_MAJOR, 55 .minor = MLXSW_SP1_FWREV_MINOR, 56 .subminor = MLXSW_SP1_FWREV_SUBMINOR, 57 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 58 }; 59 60 #define MLXSW_SP1_FW_FILENAME \ 61 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 62 "." __stringify(MLXSW_SP1_FWREV_MINOR) \ 63 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2" 64 65 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 66 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 67 static const char mlxsw_sp_driver_version[] = "1.0"; 68 69 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = { 70 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00 71 }; 72 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = { 73 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00 74 }; 75 76 /* tx_hdr_version 77 * Tx header version. 78 * Must be set to 1. 79 */ 80 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 81 82 /* tx_hdr_ctl 83 * Packet control type. 84 * 0 - Ethernet control (e.g. EMADs, LACP) 85 * 1 - Ethernet data 86 */ 87 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 88 89 /* tx_hdr_proto 90 * Packet protocol type. Must be set to 1 (Ethernet). 91 */ 92 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 93 94 /* tx_hdr_rx_is_router 95 * Packet is sent from the router. Valid for data packets only. 96 */ 97 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 98 99 /* tx_hdr_fid_valid 100 * Indicates if the 'fid' field is valid and should be used for 101 * forwarding lookup. Valid for data packets only. 102 */ 103 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 104 105 /* tx_hdr_swid 106 * Switch partition ID. Must be set to 0. 107 */ 108 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 109 110 /* tx_hdr_control_tclass 111 * Indicates if the packet should use the control TClass and not one 112 * of the data TClasses. 113 */ 114 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 115 116 /* tx_hdr_etclass 117 * Egress TClass to be used on the egress device on the egress port. 118 */ 119 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 120 121 /* tx_hdr_port_mid 122 * Destination local port for unicast packets. 123 * Destination multicast ID for multicast packets. 124 * 125 * Control packets are directed to a specific egress port, while data 126 * packets are transmitted through the CPU port (0) into the switch partition, 127 * where forwarding rules are applied. 128 */ 129 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 130 131 /* tx_hdr_fid 132 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 133 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 134 * Valid for data packets only. 135 */ 136 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 137 138 /* tx_hdr_type 139 * 0 - Data packets 140 * 6 - Control packets 141 */ 142 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 143 144 struct mlxsw_sp_mlxfw_dev { 145 struct mlxfw_dev mlxfw_dev; 146 struct mlxsw_sp *mlxsw_sp; 147 }; 148 149 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev, 150 u16 component_index, u32 *p_max_size, 151 u8 *p_align_bits, u16 *p_max_write_size) 152 { 153 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 154 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 155 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 156 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 157 int err; 158 159 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 160 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl); 161 if (err) 162 return err; 163 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, 164 p_max_write_size); 165 166 *p_align_bits = max_t(u8, *p_align_bits, 2); 167 *p_max_write_size = min_t(u16, *p_max_write_size, 168 MLXSW_REG_MCDA_MAX_DATA_LEN); 169 return 0; 170 } 171 172 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 173 { 174 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 175 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 176 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 177 char mcc_pl[MLXSW_REG_MCC_LEN]; 178 u8 control_state; 179 int err; 180 181 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 182 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 183 if (err) 184 return err; 185 186 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 187 if (control_state != MLXFW_FSM_STATE_IDLE) 188 return -EBUSY; 189 190 mlxsw_reg_mcc_pack(mcc_pl, 191 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 192 0, *fwhandle, 0); 193 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 194 } 195 196 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev, 197 u32 fwhandle, u16 component_index, 198 u32 component_size) 199 { 200 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 201 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 202 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 203 char mcc_pl[MLXSW_REG_MCC_LEN]; 204 205 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 206 component_index, fwhandle, component_size); 207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 208 } 209 210 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev, 211 u32 fwhandle, u8 *data, u16 size, 212 u32 offset) 213 { 214 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 215 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 217 char mcda_pl[MLXSW_REG_MCDA_LEN]; 218 219 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 220 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl); 221 } 222 223 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, 224 u32 fwhandle, u16 component_index) 225 { 226 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 227 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 228 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 229 char mcc_pl[MLXSW_REG_MCC_LEN]; 230 231 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 232 component_index, fwhandle, 0); 233 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 234 } 235 236 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 237 { 238 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 239 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 240 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 241 char mcc_pl[MLXSW_REG_MCC_LEN]; 242 243 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, 244 fwhandle, 0); 245 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 246 } 247 248 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 249 enum mlxfw_fsm_state *fsm_state, 250 enum mlxfw_fsm_state_err *fsm_state_err) 251 { 252 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 253 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 254 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 255 char mcc_pl[MLXSW_REG_MCC_LEN]; 256 u8 control_state; 257 u8 error_code; 258 int err; 259 260 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 261 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 262 if (err) 263 return err; 264 265 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 266 *fsm_state = control_state; 267 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 268 MLXFW_FSM_STATE_ERR_MAX); 269 return 0; 270 } 271 272 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 273 { 274 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 275 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 276 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 277 char mcc_pl[MLXSW_REG_MCC_LEN]; 278 279 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, 280 fwhandle, 0); 281 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 282 } 283 284 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 285 { 286 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 287 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 288 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 289 char mcc_pl[MLXSW_REG_MCC_LEN]; 290 291 mlxsw_reg_mcc_pack(mcc_pl, 292 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 293 fwhandle, 0); 294 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 295 } 296 297 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = { 298 .component_query = mlxsw_sp_component_query, 299 .fsm_lock = mlxsw_sp_fsm_lock, 300 .fsm_component_update = mlxsw_sp_fsm_component_update, 301 .fsm_block_download = mlxsw_sp_fsm_block_download, 302 .fsm_component_verify = mlxsw_sp_fsm_component_verify, 303 .fsm_activate = mlxsw_sp_fsm_activate, 304 .fsm_query_state = mlxsw_sp_fsm_query_state, 305 .fsm_cancel = mlxsw_sp_fsm_cancel, 306 .fsm_release = mlxsw_sp_fsm_release 307 }; 308 309 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp, 310 const struct firmware *firmware) 311 { 312 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = { 313 .mlxfw_dev = { 314 .ops = &mlxsw_sp_mlxfw_dev_ops, 315 .psid = mlxsw_sp->bus_info->psid, 316 .psid_size = strlen(mlxsw_sp->bus_info->psid), 317 }, 318 .mlxsw_sp = mlxsw_sp 319 }; 320 int err; 321 322 mlxsw_core_fw_flash_start(mlxsw_sp->core); 323 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware); 324 mlxsw_core_fw_flash_end(mlxsw_sp->core); 325 326 return err; 327 } 328 329 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp) 330 { 331 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev; 332 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev; 333 const char *fw_filename = mlxsw_sp->fw_filename; 334 union devlink_param_value value; 335 const struct firmware *firmware; 336 int err; 337 338 /* Don't check if driver does not require it */ 339 if (!req_rev || !fw_filename) 340 return 0; 341 342 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 343 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core), 344 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 345 &value); 346 if (err) 347 return err; 348 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 349 return 0; 350 351 /* Validate driver & FW are compatible */ 352 if (rev->major != req_rev->major) { 353 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 354 rev->major, req_rev->major); 355 return -EINVAL; 356 } 357 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) == 358 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) && 359 (rev->minor > req_rev->minor || 360 (rev->minor == req_rev->minor && 361 rev->subminor >= req_rev->subminor))) 362 return 0; 363 364 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n", 365 rev->major, rev->minor, rev->subminor); 366 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n", 367 fw_filename); 368 369 err = request_firmware_direct(&firmware, fw_filename, 370 mlxsw_sp->bus_info->dev); 371 if (err) { 372 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n", 373 fw_filename); 374 return err; 375 } 376 377 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 378 release_firmware(firmware); 379 if (err) 380 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n"); 381 382 /* On FW flash success, tell the caller FW reset is needed 383 * if current FW supports it. 384 */ 385 if (rev->minor >= req_rev->can_reset_minor) 386 return err ? err : -EAGAIN; 387 else 388 return 0; 389 } 390 391 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 392 unsigned int counter_index, u64 *packets, 393 u64 *bytes) 394 { 395 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 396 int err; 397 398 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 399 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 400 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 401 if (err) 402 return err; 403 if (packets) 404 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 405 if (bytes) 406 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 407 return 0; 408 } 409 410 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 411 unsigned int counter_index) 412 { 413 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 414 415 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 416 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 417 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 418 } 419 420 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 421 unsigned int *p_counter_index) 422 { 423 int err; 424 425 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 426 p_counter_index); 427 if (err) 428 return err; 429 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 430 if (err) 431 goto err_counter_clear; 432 return 0; 433 434 err_counter_clear: 435 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 436 *p_counter_index); 437 return err; 438 } 439 440 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 441 unsigned int counter_index) 442 { 443 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 444 counter_index); 445 } 446 447 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 448 const struct mlxsw_tx_info *tx_info) 449 { 450 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 451 452 memset(txhdr, 0, MLXSW_TXHDR_LEN); 453 454 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 455 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 456 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 457 mlxsw_tx_hdr_swid_set(txhdr, 0); 458 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 459 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 460 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 461 } 462 463 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 464 { 465 switch (state) { 466 case BR_STATE_FORWARDING: 467 return MLXSW_REG_SPMS_STATE_FORWARDING; 468 case BR_STATE_LEARNING: 469 return MLXSW_REG_SPMS_STATE_LEARNING; 470 case BR_STATE_LISTENING: /* fall-through */ 471 case BR_STATE_DISABLED: /* fall-through */ 472 case BR_STATE_BLOCKING: 473 return MLXSW_REG_SPMS_STATE_DISCARDING; 474 default: 475 BUG(); 476 } 477 } 478 479 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 480 u8 state) 481 { 482 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 483 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 484 char *spms_pl; 485 int err; 486 487 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 488 if (!spms_pl) 489 return -ENOMEM; 490 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 491 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 492 493 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 494 kfree(spms_pl); 495 return err; 496 } 497 498 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 499 { 500 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 501 int err; 502 503 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 504 if (err) 505 return err; 506 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 507 return 0; 508 } 509 510 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port, 511 bool enable, u32 rate) 512 { 513 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 514 char mpsc_pl[MLXSW_REG_MPSC_LEN]; 515 516 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate); 517 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl); 518 } 519 520 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 521 bool is_up) 522 { 523 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 524 char paos_pl[MLXSW_REG_PAOS_LEN]; 525 526 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 527 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 528 MLXSW_PORT_ADMIN_STATUS_DOWN); 529 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 530 } 531 532 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 533 unsigned char *addr) 534 { 535 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 536 char ppad_pl[MLXSW_REG_PPAD_LEN]; 537 538 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 539 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 540 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 541 } 542 543 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 544 { 545 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 546 unsigned char *addr = mlxsw_sp_port->dev->dev_addr; 547 548 ether_addr_copy(addr, mlxsw_sp->base_mac); 549 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port; 550 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr); 551 } 552 553 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 554 { 555 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 556 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 557 int max_mtu; 558 int err; 559 560 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 561 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 562 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 563 if (err) 564 return err; 565 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 566 567 if (mtu > max_mtu) 568 return -EINVAL; 569 570 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 571 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 572 } 573 574 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid) 575 { 576 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 577 char pspa_pl[MLXSW_REG_PSPA_LEN]; 578 579 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port); 580 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 581 } 582 583 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 584 { 585 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 586 char svpe_pl[MLXSW_REG_SVPE_LEN]; 587 588 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 589 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 590 } 591 592 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 593 bool learn_enable) 594 { 595 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 596 char *spvmlr_pl; 597 int err; 598 599 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 600 if (!spvmlr_pl) 601 return -ENOMEM; 602 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 603 learn_enable); 604 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 605 kfree(spvmlr_pl); 606 return err; 607 } 608 609 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 610 u16 vid) 611 { 612 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 613 char spvid_pl[MLXSW_REG_SPVID_LEN]; 614 615 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); 616 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 617 } 618 619 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 620 bool allow) 621 { 622 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 623 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 624 625 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 626 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 627 } 628 629 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 630 { 631 int err; 632 633 if (!vid) { 634 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 635 if (err) 636 return err; 637 } else { 638 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid); 639 if (err) 640 return err; 641 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 642 if (err) 643 goto err_port_allow_untagged_set; 644 } 645 646 mlxsw_sp_port->pvid = vid; 647 return 0; 648 649 err_port_allow_untagged_set: 650 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid); 651 return err; 652 } 653 654 static int 655 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 656 { 657 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 658 char sspr_pl[MLXSW_REG_SSPR_LEN]; 659 660 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 661 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 662 } 663 664 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, 665 u8 local_port, u8 *p_module, 666 u8 *p_width, u8 *p_lane) 667 { 668 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 669 int err; 670 671 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 672 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 673 if (err) 674 return err; 675 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 676 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); 677 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 678 return 0; 679 } 680 681 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port, 682 u8 module, u8 width, u8 lane) 683 { 684 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 685 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 686 int i; 687 688 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 689 mlxsw_reg_pmlp_width_set(pmlp_pl, width); 690 for (i = 0; i < width; i++) { 691 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); 692 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ 693 } 694 695 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 696 } 697 698 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port) 699 { 700 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 701 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 702 703 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 704 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 705 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 706 } 707 708 static int mlxsw_sp_port_open(struct net_device *dev) 709 { 710 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 711 int err; 712 713 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 714 if (err) 715 return err; 716 netif_start_queue(dev); 717 return 0; 718 } 719 720 static int mlxsw_sp_port_stop(struct net_device *dev) 721 { 722 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 723 724 netif_stop_queue(dev); 725 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 726 } 727 728 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 729 struct net_device *dev) 730 { 731 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 732 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 733 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 734 const struct mlxsw_tx_info tx_info = { 735 .local_port = mlxsw_sp_port->local_port, 736 .is_emad = false, 737 }; 738 u64 len; 739 int err; 740 741 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 742 return NETDEV_TX_BUSY; 743 744 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) { 745 struct sk_buff *skb_orig = skb; 746 747 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN); 748 if (!skb) { 749 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 750 dev_kfree_skb_any(skb_orig); 751 return NETDEV_TX_OK; 752 } 753 dev_consume_skb_any(skb_orig); 754 } 755 756 if (eth_skb_pad(skb)) { 757 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 758 return NETDEV_TX_OK; 759 } 760 761 mlxsw_sp_txhdr_construct(skb, &tx_info); 762 /* TX header is consumed by HW on the way so we shouldn't count its 763 * bytes as being sent. 764 */ 765 len = skb->len - MLXSW_TXHDR_LEN; 766 767 /* Due to a race we might fail here because of a full queue. In that 768 * unlikely case we simply drop the packet. 769 */ 770 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 771 772 if (!err) { 773 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 774 u64_stats_update_begin(&pcpu_stats->syncp); 775 pcpu_stats->tx_packets++; 776 pcpu_stats->tx_bytes += len; 777 u64_stats_update_end(&pcpu_stats->syncp); 778 } else { 779 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 780 dev_kfree_skb_any(skb); 781 } 782 return NETDEV_TX_OK; 783 } 784 785 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 786 { 787 } 788 789 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 790 { 791 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 792 struct sockaddr *addr = p; 793 int err; 794 795 if (!is_valid_ether_addr(addr->sa_data)) 796 return -EADDRNOTAVAIL; 797 798 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 799 if (err) 800 return err; 801 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 802 return 0; 803 } 804 805 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp, 806 int mtu) 807 { 808 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu); 809 } 810 811 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ 812 813 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 814 u16 delay) 815 { 816 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay, 817 BITS_PER_BYTE)); 818 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp, 819 mtu); 820 } 821 822 /* Maximum delay buffer needed in case of PAUSE frames, in bytes. 823 * Assumes 100m cable and maximum MTU. 824 */ 825 #define MLXSW_SP_PAUSE_DELAY 58752 826 827 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 828 u16 delay, bool pfc, bool pause) 829 { 830 if (pfc) 831 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay); 832 else if (pause) 833 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY); 834 else 835 return 0; 836 } 837 838 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres, 839 bool lossy) 840 { 841 if (lossy) 842 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size); 843 else 844 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size, 845 thres); 846 } 847 848 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, 849 u8 *prio_tc, bool pause_en, 850 struct ieee_pfc *my_pfc) 851 { 852 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 853 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0; 854 u16 delay = !!my_pfc ? my_pfc->delay : 0; 855 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 856 u32 taken_headroom_cells = 0; 857 u32 max_headroom_cells; 858 int i, j, err; 859 860 max_headroom_cells = mlxsw_sp_sb_max_headroom_cells(mlxsw_sp); 861 862 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0); 863 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 864 if (err) 865 return err; 866 867 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 868 bool configure = false; 869 bool pfc = false; 870 u16 thres_cells; 871 u16 delay_cells; 872 u16 total_cells; 873 bool lossy; 874 875 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) { 876 if (prio_tc[j] == i) { 877 pfc = pfc_en & BIT(j); 878 configure = true; 879 break; 880 } 881 } 882 883 if (!configure) 884 continue; 885 886 lossy = !(pfc || pause_en); 887 thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu); 888 delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, 889 pfc, pause_en); 890 total_cells = thres_cells + delay_cells; 891 892 taken_headroom_cells += total_cells; 893 if (taken_headroom_cells > max_headroom_cells) 894 return -ENOBUFS; 895 896 mlxsw_sp_pg_buf_pack(pbmc_pl, i, total_cells, 897 thres_cells, lossy); 898 } 899 900 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 901 } 902 903 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, 904 int mtu, bool pause_en) 905 { 906 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0}; 907 bool dcb_en = !!mlxsw_sp_port->dcb.ets; 908 struct ieee_pfc *my_pfc; 909 u8 *prio_tc; 910 911 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc; 912 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL; 913 914 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc, 915 pause_en, my_pfc); 916 } 917 918 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 919 { 920 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 921 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 922 int err; 923 924 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en); 925 if (err) 926 return err; 927 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu); 928 if (err) 929 goto err_span_port_mtu_update; 930 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 931 if (err) 932 goto err_port_mtu_set; 933 dev->mtu = mtu; 934 return 0; 935 936 err_port_mtu_set: 937 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu); 938 err_span_port_mtu_update: 939 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 940 return err; 941 } 942 943 static int 944 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 945 struct rtnl_link_stats64 *stats) 946 { 947 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 948 struct mlxsw_sp_port_pcpu_stats *p; 949 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 950 u32 tx_dropped = 0; 951 unsigned int start; 952 int i; 953 954 for_each_possible_cpu(i) { 955 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 956 do { 957 start = u64_stats_fetch_begin_irq(&p->syncp); 958 rx_packets = p->rx_packets; 959 rx_bytes = p->rx_bytes; 960 tx_packets = p->tx_packets; 961 tx_bytes = p->tx_bytes; 962 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 963 964 stats->rx_packets += rx_packets; 965 stats->rx_bytes += rx_bytes; 966 stats->tx_packets += tx_packets; 967 stats->tx_bytes += tx_bytes; 968 /* tx_dropped is u32, updated without syncp protection. */ 969 tx_dropped += p->tx_dropped; 970 } 971 stats->tx_dropped = tx_dropped; 972 return 0; 973 } 974 975 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 976 { 977 switch (attr_id) { 978 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 979 return true; 980 } 981 982 return false; 983 } 984 985 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 986 void *sp) 987 { 988 switch (attr_id) { 989 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 990 return mlxsw_sp_port_get_sw_stats64(dev, sp); 991 } 992 993 return -EINVAL; 994 } 995 996 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 997 int prio, char *ppcnt_pl) 998 { 999 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1000 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1001 1002 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 1003 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 1004 } 1005 1006 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 1007 struct rtnl_link_stats64 *stats) 1008 { 1009 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1010 int err; 1011 1012 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 1013 0, ppcnt_pl); 1014 if (err) 1015 goto out; 1016 1017 stats->tx_packets = 1018 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 1019 stats->rx_packets = 1020 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 1021 stats->tx_bytes = 1022 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 1023 stats->rx_bytes = 1024 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 1025 stats->multicast = 1026 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 1027 1028 stats->rx_crc_errors = 1029 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 1030 stats->rx_frame_errors = 1031 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 1032 1033 stats->rx_length_errors = ( 1034 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 1035 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 1036 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 1037 1038 stats->rx_errors = (stats->rx_crc_errors + 1039 stats->rx_frame_errors + stats->rx_length_errors); 1040 1041 out: 1042 return err; 1043 } 1044 1045 static void 1046 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 1047 struct mlxsw_sp_port_xstats *xstats) 1048 { 1049 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1050 int err, i; 1051 1052 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 1053 ppcnt_pl); 1054 if (!err) 1055 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 1056 1057 for (i = 0; i < TC_MAX_QUEUE; i++) { 1058 err = mlxsw_sp_port_get_stats_raw(dev, 1059 MLXSW_REG_PPCNT_TC_CONG_TC, 1060 i, ppcnt_pl); 1061 if (!err) 1062 xstats->wred_drop[i] = 1063 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 1064 1065 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 1066 i, ppcnt_pl); 1067 if (err) 1068 continue; 1069 1070 xstats->backlog[i] = 1071 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 1072 xstats->tail_drop[i] = 1073 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 1074 } 1075 1076 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1077 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 1078 i, ppcnt_pl); 1079 if (err) 1080 continue; 1081 1082 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 1083 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 1084 } 1085 } 1086 1087 static void update_stats_cache(struct work_struct *work) 1088 { 1089 struct mlxsw_sp_port *mlxsw_sp_port = 1090 container_of(work, struct mlxsw_sp_port, 1091 periodic_hw_stats.update_dw.work); 1092 1093 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 1094 goto out; 1095 1096 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 1097 &mlxsw_sp_port->periodic_hw_stats.stats); 1098 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 1099 &mlxsw_sp_port->periodic_hw_stats.xstats); 1100 1101 out: 1102 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1103 MLXSW_HW_STATS_UPDATE_TIME); 1104 } 1105 1106 /* Return the stats from a cache that is updated periodically, 1107 * as this function might get called in an atomic context. 1108 */ 1109 static void 1110 mlxsw_sp_port_get_stats64(struct net_device *dev, 1111 struct rtnl_link_stats64 *stats) 1112 { 1113 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1114 1115 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 1116 } 1117 1118 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 1119 u16 vid_begin, u16 vid_end, 1120 bool is_member, bool untagged) 1121 { 1122 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1123 char *spvm_pl; 1124 int err; 1125 1126 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1127 if (!spvm_pl) 1128 return -ENOMEM; 1129 1130 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1131 vid_end, is_member, untagged); 1132 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1133 kfree(spvm_pl); 1134 return err; 1135 } 1136 1137 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1138 u16 vid_end, bool is_member, bool untagged) 1139 { 1140 u16 vid, vid_e; 1141 int err; 1142 1143 for (vid = vid_begin; vid <= vid_end; 1144 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1145 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1146 vid_end); 1147 1148 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1149 is_member, untagged); 1150 if (err) 1151 return err; 1152 } 1153 1154 return 0; 1155 } 1156 1157 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port, 1158 bool flush_default) 1159 { 1160 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1161 1162 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1163 &mlxsw_sp_port->vlans_list, list) { 1164 if (!flush_default && 1165 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID) 1166 continue; 1167 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1168 } 1169 } 1170 1171 static void 1172 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1173 { 1174 if (mlxsw_sp_port_vlan->bridge_port) 1175 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1176 else if (mlxsw_sp_port_vlan->fid) 1177 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1178 } 1179 1180 struct mlxsw_sp_port_vlan * 1181 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1182 { 1183 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1184 bool untagged = vid == MLXSW_SP_DEFAULT_VID; 1185 int err; 1186 1187 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1188 if (mlxsw_sp_port_vlan) 1189 return ERR_PTR(-EEXIST); 1190 1191 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1192 if (err) 1193 return ERR_PTR(err); 1194 1195 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1196 if (!mlxsw_sp_port_vlan) { 1197 err = -ENOMEM; 1198 goto err_port_vlan_alloc; 1199 } 1200 1201 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1202 mlxsw_sp_port_vlan->vid = vid; 1203 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1204 1205 return mlxsw_sp_port_vlan; 1206 1207 err_port_vlan_alloc: 1208 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1209 return ERR_PTR(err); 1210 } 1211 1212 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1213 { 1214 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1215 u16 vid = mlxsw_sp_port_vlan->vid; 1216 1217 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan); 1218 list_del(&mlxsw_sp_port_vlan->list); 1219 kfree(mlxsw_sp_port_vlan); 1220 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1221 } 1222 1223 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1224 __be16 __always_unused proto, u16 vid) 1225 { 1226 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1227 1228 /* VLAN 0 is added to HW filter when device goes up, but it is 1229 * reserved in our case, so simply return. 1230 */ 1231 if (!vid) 1232 return 0; 1233 1234 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid)); 1235 } 1236 1237 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1238 __be16 __always_unused proto, u16 vid) 1239 { 1240 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1241 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1242 1243 /* VLAN 0 is removed from HW filter when device goes down, but 1244 * it is reserved in our case, so simply return. 1245 */ 1246 if (!vid) 1247 return 0; 1248 1249 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1250 if (!mlxsw_sp_port_vlan) 1251 return 0; 1252 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1253 1254 return 0; 1255 } 1256 1257 static struct mlxsw_sp_port_mall_tc_entry * 1258 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port, 1259 unsigned long cookie) { 1260 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1261 1262 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list) 1263 if (mall_tc_entry->cookie == cookie) 1264 return mall_tc_entry; 1265 1266 return NULL; 1267 } 1268 1269 static int 1270 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1271 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror, 1272 const struct tc_action *a, 1273 bool ingress) 1274 { 1275 enum mlxsw_sp_span_type span_type; 1276 struct net_device *to_dev; 1277 1278 to_dev = tcf_mirred_dev(a); 1279 if (!to_dev) { 1280 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n"); 1281 return -EINVAL; 1282 } 1283 1284 mirror->ingress = ingress; 1285 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1286 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type, 1287 true, &mirror->span_id); 1288 } 1289 1290 static void 1291 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1292 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror) 1293 { 1294 enum mlxsw_sp_span_type span_type; 1295 1296 span_type = mirror->ingress ? 1297 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1298 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id, 1299 span_type, true); 1300 } 1301 1302 static int 1303 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port, 1304 struct tc_cls_matchall_offload *cls, 1305 const struct tc_action *a, 1306 bool ingress) 1307 { 1308 int err; 1309 1310 if (!mlxsw_sp_port->sample) 1311 return -EOPNOTSUPP; 1312 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) { 1313 netdev_err(mlxsw_sp_port->dev, "sample already active\n"); 1314 return -EEXIST; 1315 } 1316 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) { 1317 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n"); 1318 return -EOPNOTSUPP; 1319 } 1320 1321 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group, 1322 tcf_sample_psample_group(a)); 1323 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a); 1324 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a); 1325 mlxsw_sp_port->sample->rate = tcf_sample_rate(a); 1326 1327 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a)); 1328 if (err) 1329 goto err_port_sample_set; 1330 return 0; 1331 1332 err_port_sample_set: 1333 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1334 return err; 1335 } 1336 1337 static void 1338 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port) 1339 { 1340 if (!mlxsw_sp_port->sample) 1341 return; 1342 1343 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1); 1344 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1345 } 1346 1347 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1348 struct tc_cls_matchall_offload *f, 1349 bool ingress) 1350 { 1351 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1352 __be16 protocol = f->common.protocol; 1353 const struct tc_action *a; 1354 int err; 1355 1356 if (!tcf_exts_has_one_action(f->exts)) { 1357 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n"); 1358 return -EOPNOTSUPP; 1359 } 1360 1361 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL); 1362 if (!mall_tc_entry) 1363 return -ENOMEM; 1364 mall_tc_entry->cookie = f->cookie; 1365 1366 a = tcf_exts_first_action(f->exts); 1367 1368 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) { 1369 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror; 1370 1371 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR; 1372 mirror = &mall_tc_entry->mirror; 1373 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, 1374 mirror, a, ingress); 1375 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) { 1376 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE; 1377 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f, 1378 a, ingress); 1379 } else { 1380 err = -EOPNOTSUPP; 1381 } 1382 1383 if (err) 1384 goto err_add_action; 1385 1386 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list); 1387 return 0; 1388 1389 err_add_action: 1390 kfree(mall_tc_entry); 1391 return err; 1392 } 1393 1394 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1395 struct tc_cls_matchall_offload *f) 1396 { 1397 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1398 1399 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port, 1400 f->cookie); 1401 if (!mall_tc_entry) { 1402 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n"); 1403 return; 1404 } 1405 list_del(&mall_tc_entry->list); 1406 1407 switch (mall_tc_entry->type) { 1408 case MLXSW_SP_PORT_MALL_MIRROR: 1409 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port, 1410 &mall_tc_entry->mirror); 1411 break; 1412 case MLXSW_SP_PORT_MALL_SAMPLE: 1413 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port); 1414 break; 1415 default: 1416 WARN_ON(1); 1417 } 1418 1419 kfree(mall_tc_entry); 1420 } 1421 1422 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1423 struct tc_cls_matchall_offload *f, 1424 bool ingress) 1425 { 1426 switch (f->command) { 1427 case TC_CLSMATCHALL_REPLACE: 1428 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f, 1429 ingress); 1430 case TC_CLSMATCHALL_DESTROY: 1431 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f); 1432 return 0; 1433 default: 1434 return -EOPNOTSUPP; 1435 } 1436 } 1437 1438 static int 1439 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block, 1440 struct tc_cls_flower_offload *f) 1441 { 1442 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block); 1443 1444 switch (f->command) { 1445 case TC_CLSFLOWER_REPLACE: 1446 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f); 1447 case TC_CLSFLOWER_DESTROY: 1448 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f); 1449 return 0; 1450 case TC_CLSFLOWER_STATS: 1451 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f); 1452 case TC_CLSFLOWER_TMPLT_CREATE: 1453 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f); 1454 case TC_CLSFLOWER_TMPLT_DESTROY: 1455 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f); 1456 return 0; 1457 default: 1458 return -EOPNOTSUPP; 1459 } 1460 } 1461 1462 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type, 1463 void *type_data, 1464 void *cb_priv, bool ingress) 1465 { 1466 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv; 1467 1468 switch (type) { 1469 case TC_SETUP_CLSMATCHALL: 1470 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev, 1471 type_data)) 1472 return -EOPNOTSUPP; 1473 1474 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data, 1475 ingress); 1476 case TC_SETUP_CLSFLOWER: 1477 return 0; 1478 default: 1479 return -EOPNOTSUPP; 1480 } 1481 } 1482 1483 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type, 1484 void *type_data, 1485 void *cb_priv) 1486 { 1487 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1488 cb_priv, true); 1489 } 1490 1491 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type, 1492 void *type_data, 1493 void *cb_priv) 1494 { 1495 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1496 cb_priv, false); 1497 } 1498 1499 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type, 1500 void *type_data, void *cb_priv) 1501 { 1502 struct mlxsw_sp_acl_block *acl_block = cb_priv; 1503 1504 switch (type) { 1505 case TC_SETUP_CLSMATCHALL: 1506 return 0; 1507 case TC_SETUP_CLSFLOWER: 1508 if (mlxsw_sp_acl_block_disabled(acl_block)) 1509 return -EOPNOTSUPP; 1510 1511 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data); 1512 default: 1513 return -EOPNOTSUPP; 1514 } 1515 } 1516 1517 static int 1518 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port, 1519 struct tcf_block *block, bool ingress, 1520 struct netlink_ext_ack *extack) 1521 { 1522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1523 struct mlxsw_sp_acl_block *acl_block; 1524 struct tcf_block_cb *block_cb; 1525 int err; 1526 1527 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1528 mlxsw_sp); 1529 if (!block_cb) { 1530 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net); 1531 if (!acl_block) 1532 return -ENOMEM; 1533 block_cb = __tcf_block_cb_register(block, 1534 mlxsw_sp_setup_tc_block_cb_flower, 1535 mlxsw_sp, acl_block, extack); 1536 if (IS_ERR(block_cb)) { 1537 err = PTR_ERR(block_cb); 1538 goto err_cb_register; 1539 } 1540 } else { 1541 acl_block = tcf_block_cb_priv(block_cb); 1542 } 1543 tcf_block_cb_incref(block_cb); 1544 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block, 1545 mlxsw_sp_port, ingress); 1546 if (err) 1547 goto err_block_bind; 1548 1549 if (ingress) 1550 mlxsw_sp_port->ing_acl_block = acl_block; 1551 else 1552 mlxsw_sp_port->eg_acl_block = acl_block; 1553 1554 return 0; 1555 1556 err_block_bind: 1557 if (!tcf_block_cb_decref(block_cb)) { 1558 __tcf_block_cb_unregister(block, block_cb); 1559 err_cb_register: 1560 mlxsw_sp_acl_block_destroy(acl_block); 1561 } 1562 return err; 1563 } 1564 1565 static void 1566 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port, 1567 struct tcf_block *block, bool ingress) 1568 { 1569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1570 struct mlxsw_sp_acl_block *acl_block; 1571 struct tcf_block_cb *block_cb; 1572 int err; 1573 1574 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1575 mlxsw_sp); 1576 if (!block_cb) 1577 return; 1578 1579 if (ingress) 1580 mlxsw_sp_port->ing_acl_block = NULL; 1581 else 1582 mlxsw_sp_port->eg_acl_block = NULL; 1583 1584 acl_block = tcf_block_cb_priv(block_cb); 1585 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block, 1586 mlxsw_sp_port, ingress); 1587 if (!err && !tcf_block_cb_decref(block_cb)) { 1588 __tcf_block_cb_unregister(block, block_cb); 1589 mlxsw_sp_acl_block_destroy(acl_block); 1590 } 1591 } 1592 1593 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1594 struct tc_block_offload *f) 1595 { 1596 tc_setup_cb_t *cb; 1597 bool ingress; 1598 int err; 1599 1600 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) { 1601 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig; 1602 ingress = true; 1603 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 1604 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg; 1605 ingress = false; 1606 } else { 1607 return -EOPNOTSUPP; 1608 } 1609 1610 switch (f->command) { 1611 case TC_BLOCK_BIND: 1612 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port, 1613 mlxsw_sp_port, f->extack); 1614 if (err) 1615 return err; 1616 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, 1617 f->block, ingress, 1618 f->extack); 1619 if (err) { 1620 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1621 return err; 1622 } 1623 return 0; 1624 case TC_BLOCK_UNBIND: 1625 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port, 1626 f->block, ingress); 1627 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1628 return 0; 1629 default: 1630 return -EOPNOTSUPP; 1631 } 1632 } 1633 1634 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1635 void *type_data) 1636 { 1637 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1638 1639 switch (type) { 1640 case TC_SETUP_BLOCK: 1641 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1642 case TC_SETUP_QDISC_RED: 1643 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1644 case TC_SETUP_QDISC_PRIO: 1645 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1646 default: 1647 return -EOPNOTSUPP; 1648 } 1649 } 1650 1651 1652 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1653 { 1654 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1655 1656 if (!enable) { 1657 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) || 1658 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) || 1659 !list_empty(&mlxsw_sp_port->mall_tc_list)) { 1660 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1661 return -EINVAL; 1662 } 1663 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block); 1664 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block); 1665 } else { 1666 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block); 1667 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block); 1668 } 1669 return 0; 1670 } 1671 1672 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1673 1674 static int mlxsw_sp_handle_feature(struct net_device *dev, 1675 netdev_features_t wanted_features, 1676 netdev_features_t feature, 1677 mlxsw_sp_feature_handler feature_handler) 1678 { 1679 netdev_features_t changes = wanted_features ^ dev->features; 1680 bool enable = !!(wanted_features & feature); 1681 int err; 1682 1683 if (!(changes & feature)) 1684 return 0; 1685 1686 err = feature_handler(dev, enable); 1687 if (err) { 1688 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1689 enable ? "Enable" : "Disable", &feature, err); 1690 return err; 1691 } 1692 1693 if (enable) 1694 dev->features |= feature; 1695 else 1696 dev->features &= ~feature; 1697 1698 return 0; 1699 } 1700 static int mlxsw_sp_set_features(struct net_device *dev, 1701 netdev_features_t features) 1702 { 1703 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1704 mlxsw_sp_feature_hw_tc); 1705 } 1706 1707 static struct devlink_port * 1708 mlxsw_sp_port_get_devlink_port(struct net_device *dev) 1709 { 1710 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1711 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1712 1713 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core, 1714 mlxsw_sp_port->local_port); 1715 } 1716 1717 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1718 .ndo_open = mlxsw_sp_port_open, 1719 .ndo_stop = mlxsw_sp_port_stop, 1720 .ndo_start_xmit = mlxsw_sp_port_xmit, 1721 .ndo_setup_tc = mlxsw_sp_setup_tc, 1722 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1723 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1724 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1725 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1726 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1727 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1728 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1729 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1730 .ndo_set_features = mlxsw_sp_set_features, 1731 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port, 1732 }; 1733 1734 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev, 1735 struct ethtool_drvinfo *drvinfo) 1736 { 1737 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1738 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1739 1740 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind, 1741 sizeof(drvinfo->driver)); 1742 strlcpy(drvinfo->version, mlxsw_sp_driver_version, 1743 sizeof(drvinfo->version)); 1744 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 1745 "%d.%d.%d", 1746 mlxsw_sp->bus_info->fw_rev.major, 1747 mlxsw_sp->bus_info->fw_rev.minor, 1748 mlxsw_sp->bus_info->fw_rev.subminor); 1749 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name, 1750 sizeof(drvinfo->bus_info)); 1751 } 1752 1753 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev, 1754 struct ethtool_pauseparam *pause) 1755 { 1756 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1757 1758 pause->rx_pause = mlxsw_sp_port->link.rx_pause; 1759 pause->tx_pause = mlxsw_sp_port->link.tx_pause; 1760 } 1761 1762 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port, 1763 struct ethtool_pauseparam *pause) 1764 { 1765 char pfcc_pl[MLXSW_REG_PFCC_LEN]; 1766 1767 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port); 1768 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause); 1769 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause); 1770 1771 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc), 1772 pfcc_pl); 1773 } 1774 1775 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev, 1776 struct ethtool_pauseparam *pause) 1777 { 1778 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1779 bool pause_en = pause->tx_pause || pause->rx_pause; 1780 int err; 1781 1782 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) { 1783 netdev_err(dev, "PFC already enabled on port\n"); 1784 return -EINVAL; 1785 } 1786 1787 if (pause->autoneg) { 1788 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n"); 1789 return -EINVAL; 1790 } 1791 1792 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1793 if (err) { 1794 netdev_err(dev, "Failed to configure port's headroom\n"); 1795 return err; 1796 } 1797 1798 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause); 1799 if (err) { 1800 netdev_err(dev, "Failed to set PAUSE parameters\n"); 1801 goto err_port_pause_configure; 1802 } 1803 1804 mlxsw_sp_port->link.rx_pause = pause->rx_pause; 1805 mlxsw_sp_port->link.tx_pause = pause->tx_pause; 1806 1807 return 0; 1808 1809 err_port_pause_configure: 1810 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 1811 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1812 return err; 1813 } 1814 1815 struct mlxsw_sp_port_hw_stats { 1816 char str[ETH_GSTRING_LEN]; 1817 u64 (*getter)(const char *payload); 1818 bool cells_bytes; 1819 }; 1820 1821 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = { 1822 { 1823 .str = "a_frames_transmitted_ok", 1824 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get, 1825 }, 1826 { 1827 .str = "a_frames_received_ok", 1828 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get, 1829 }, 1830 { 1831 .str = "a_frame_check_sequence_errors", 1832 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get, 1833 }, 1834 { 1835 .str = "a_alignment_errors", 1836 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get, 1837 }, 1838 { 1839 .str = "a_octets_transmitted_ok", 1840 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get, 1841 }, 1842 { 1843 .str = "a_octets_received_ok", 1844 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get, 1845 }, 1846 { 1847 .str = "a_multicast_frames_xmitted_ok", 1848 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get, 1849 }, 1850 { 1851 .str = "a_broadcast_frames_xmitted_ok", 1852 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get, 1853 }, 1854 { 1855 .str = "a_multicast_frames_received_ok", 1856 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get, 1857 }, 1858 { 1859 .str = "a_broadcast_frames_received_ok", 1860 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get, 1861 }, 1862 { 1863 .str = "a_in_range_length_errors", 1864 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get, 1865 }, 1866 { 1867 .str = "a_out_of_range_length_field", 1868 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get, 1869 }, 1870 { 1871 .str = "a_frame_too_long_errors", 1872 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get, 1873 }, 1874 { 1875 .str = "a_symbol_error_during_carrier", 1876 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get, 1877 }, 1878 { 1879 .str = "a_mac_control_frames_transmitted", 1880 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get, 1881 }, 1882 { 1883 .str = "a_mac_control_frames_received", 1884 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get, 1885 }, 1886 { 1887 .str = "a_unsupported_opcodes_received", 1888 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get, 1889 }, 1890 { 1891 .str = "a_pause_mac_ctrl_frames_received", 1892 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get, 1893 }, 1894 { 1895 .str = "a_pause_mac_ctrl_frames_xmitted", 1896 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get, 1897 }, 1898 }; 1899 1900 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats) 1901 1902 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = { 1903 { 1904 .str = "if_in_discards", 1905 .getter = mlxsw_reg_ppcnt_if_in_discards_get, 1906 }, 1907 { 1908 .str = "if_out_discards", 1909 .getter = mlxsw_reg_ppcnt_if_out_discards_get, 1910 }, 1911 { 1912 .str = "if_out_errors", 1913 .getter = mlxsw_reg_ppcnt_if_out_errors_get, 1914 }, 1915 }; 1916 1917 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \ 1918 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats) 1919 1920 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = { 1921 { 1922 .str = "ether_stats_undersize_pkts", 1923 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get, 1924 }, 1925 { 1926 .str = "ether_stats_oversize_pkts", 1927 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get, 1928 }, 1929 { 1930 .str = "ether_stats_fragments", 1931 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get, 1932 }, 1933 { 1934 .str = "ether_pkts64octets", 1935 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get, 1936 }, 1937 { 1938 .str = "ether_pkts65to127octets", 1939 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get, 1940 }, 1941 { 1942 .str = "ether_pkts128to255octets", 1943 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get, 1944 }, 1945 { 1946 .str = "ether_pkts256to511octets", 1947 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get, 1948 }, 1949 { 1950 .str = "ether_pkts512to1023octets", 1951 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get, 1952 }, 1953 { 1954 .str = "ether_pkts1024to1518octets", 1955 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get, 1956 }, 1957 { 1958 .str = "ether_pkts1519to2047octets", 1959 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get, 1960 }, 1961 { 1962 .str = "ether_pkts2048to4095octets", 1963 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get, 1964 }, 1965 { 1966 .str = "ether_pkts4096to8191octets", 1967 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get, 1968 }, 1969 { 1970 .str = "ether_pkts8192to10239octets", 1971 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get, 1972 }, 1973 }; 1974 1975 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \ 1976 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats) 1977 1978 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = { 1979 { 1980 .str = "dot3stats_fcs_errors", 1981 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get, 1982 }, 1983 { 1984 .str = "dot3stats_symbol_errors", 1985 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get, 1986 }, 1987 { 1988 .str = "dot3control_in_unknown_opcodes", 1989 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get, 1990 }, 1991 { 1992 .str = "dot3in_pause_frames", 1993 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get, 1994 }, 1995 }; 1996 1997 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \ 1998 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats) 1999 2000 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = { 2001 { 2002 .str = "discard_ingress_general", 2003 .getter = mlxsw_reg_ppcnt_ingress_general_get, 2004 }, 2005 { 2006 .str = "discard_ingress_policy_engine", 2007 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get, 2008 }, 2009 { 2010 .str = "discard_ingress_vlan_membership", 2011 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get, 2012 }, 2013 { 2014 .str = "discard_ingress_tag_frame_type", 2015 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get, 2016 }, 2017 { 2018 .str = "discard_egress_vlan_membership", 2019 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get, 2020 }, 2021 { 2022 .str = "discard_loopback_filter", 2023 .getter = mlxsw_reg_ppcnt_loopback_filter_get, 2024 }, 2025 { 2026 .str = "discard_egress_general", 2027 .getter = mlxsw_reg_ppcnt_egress_general_get, 2028 }, 2029 { 2030 .str = "discard_egress_hoq", 2031 .getter = mlxsw_reg_ppcnt_egress_hoq_get, 2032 }, 2033 { 2034 .str = "discard_egress_policy_engine", 2035 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get, 2036 }, 2037 { 2038 .str = "discard_ingress_tx_link_down", 2039 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get, 2040 }, 2041 { 2042 .str = "discard_egress_stp_filter", 2043 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get, 2044 }, 2045 { 2046 .str = "discard_egress_sll", 2047 .getter = mlxsw_reg_ppcnt_egress_sll_get, 2048 }, 2049 }; 2050 2051 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \ 2052 ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats) 2053 2054 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = { 2055 { 2056 .str = "rx_octets_prio", 2057 .getter = mlxsw_reg_ppcnt_rx_octets_get, 2058 }, 2059 { 2060 .str = "rx_frames_prio", 2061 .getter = mlxsw_reg_ppcnt_rx_frames_get, 2062 }, 2063 { 2064 .str = "tx_octets_prio", 2065 .getter = mlxsw_reg_ppcnt_tx_octets_get, 2066 }, 2067 { 2068 .str = "tx_frames_prio", 2069 .getter = mlxsw_reg_ppcnt_tx_frames_get, 2070 }, 2071 { 2072 .str = "rx_pause_prio", 2073 .getter = mlxsw_reg_ppcnt_rx_pause_get, 2074 }, 2075 { 2076 .str = "rx_pause_duration_prio", 2077 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get, 2078 }, 2079 { 2080 .str = "tx_pause_prio", 2081 .getter = mlxsw_reg_ppcnt_tx_pause_get, 2082 }, 2083 { 2084 .str = "tx_pause_duration_prio", 2085 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get, 2086 }, 2087 }; 2088 2089 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats) 2090 2091 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = { 2092 { 2093 .str = "tc_transmit_queue_tc", 2094 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get, 2095 .cells_bytes = true, 2096 }, 2097 { 2098 .str = "tc_no_buffer_discard_uc_tc", 2099 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get, 2100 }, 2101 }; 2102 2103 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats) 2104 2105 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \ 2106 MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \ 2107 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \ 2108 MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \ 2109 MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \ 2110 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \ 2111 IEEE_8021QAZ_MAX_TCS) + \ 2112 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \ 2113 TC_MAX_QUEUE)) 2114 2115 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio) 2116 { 2117 int i; 2118 2119 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) { 2120 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d", 2121 mlxsw_sp_port_hw_prio_stats[i].str, prio); 2122 *p += ETH_GSTRING_LEN; 2123 } 2124 } 2125 2126 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc) 2127 { 2128 int i; 2129 2130 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) { 2131 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d", 2132 mlxsw_sp_port_hw_tc_stats[i].str, tc); 2133 *p += ETH_GSTRING_LEN; 2134 } 2135 } 2136 2137 static void mlxsw_sp_port_get_strings(struct net_device *dev, 2138 u32 stringset, u8 *data) 2139 { 2140 u8 *p = data; 2141 int i; 2142 2143 switch (stringset) { 2144 case ETH_SS_STATS: 2145 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) { 2146 memcpy(p, mlxsw_sp_port_hw_stats[i].str, 2147 ETH_GSTRING_LEN); 2148 p += ETH_GSTRING_LEN; 2149 } 2150 2151 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) { 2152 memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str, 2153 ETH_GSTRING_LEN); 2154 p += ETH_GSTRING_LEN; 2155 } 2156 2157 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) { 2158 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str, 2159 ETH_GSTRING_LEN); 2160 p += ETH_GSTRING_LEN; 2161 } 2162 2163 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) { 2164 memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str, 2165 ETH_GSTRING_LEN); 2166 p += ETH_GSTRING_LEN; 2167 } 2168 2169 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) { 2170 memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str, 2171 ETH_GSTRING_LEN); 2172 p += ETH_GSTRING_LEN; 2173 } 2174 2175 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 2176 mlxsw_sp_port_get_prio_strings(&p, i); 2177 2178 for (i = 0; i < TC_MAX_QUEUE; i++) 2179 mlxsw_sp_port_get_tc_strings(&p, i); 2180 2181 break; 2182 } 2183 } 2184 2185 static int mlxsw_sp_port_set_phys_id(struct net_device *dev, 2186 enum ethtool_phys_id_state state) 2187 { 2188 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2190 char mlcr_pl[MLXSW_REG_MLCR_LEN]; 2191 bool active; 2192 2193 switch (state) { 2194 case ETHTOOL_ID_ACTIVE: 2195 active = true; 2196 break; 2197 case ETHTOOL_ID_INACTIVE: 2198 active = false; 2199 break; 2200 default: 2201 return -EOPNOTSUPP; 2202 } 2203 2204 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active); 2205 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl); 2206 } 2207 2208 static int 2209 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats, 2210 int *p_len, enum mlxsw_reg_ppcnt_grp grp) 2211 { 2212 switch (grp) { 2213 case MLXSW_REG_PPCNT_IEEE_8023_CNT: 2214 *p_hw_stats = mlxsw_sp_port_hw_stats; 2215 *p_len = MLXSW_SP_PORT_HW_STATS_LEN; 2216 break; 2217 case MLXSW_REG_PPCNT_RFC_2863_CNT: 2218 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats; 2219 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; 2220 break; 2221 case MLXSW_REG_PPCNT_RFC_2819_CNT: 2222 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats; 2223 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2224 break; 2225 case MLXSW_REG_PPCNT_RFC_3635_CNT: 2226 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats; 2227 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; 2228 break; 2229 case MLXSW_REG_PPCNT_DISCARD_CNT: 2230 *p_hw_stats = mlxsw_sp_port_hw_discard_stats; 2231 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; 2232 break; 2233 case MLXSW_REG_PPCNT_PRIO_CNT: 2234 *p_hw_stats = mlxsw_sp_port_hw_prio_stats; 2235 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2236 break; 2237 case MLXSW_REG_PPCNT_TC_CNT: 2238 *p_hw_stats = mlxsw_sp_port_hw_tc_stats; 2239 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN; 2240 break; 2241 default: 2242 WARN_ON(1); 2243 return -EOPNOTSUPP; 2244 } 2245 return 0; 2246 } 2247 2248 static void __mlxsw_sp_port_get_stats(struct net_device *dev, 2249 enum mlxsw_reg_ppcnt_grp grp, int prio, 2250 u64 *data, int data_index) 2251 { 2252 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2254 struct mlxsw_sp_port_hw_stats *hw_stats; 2255 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 2256 int i, len; 2257 int err; 2258 2259 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp); 2260 if (err) 2261 return; 2262 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl); 2263 for (i = 0; i < len; i++) { 2264 data[data_index + i] = hw_stats[i].getter(ppcnt_pl); 2265 if (!hw_stats[i].cells_bytes) 2266 continue; 2267 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp, 2268 data[data_index + i]); 2269 } 2270 } 2271 2272 static void mlxsw_sp_port_get_stats(struct net_device *dev, 2273 struct ethtool_stats *stats, u64 *data) 2274 { 2275 int i, data_index = 0; 2276 2277 /* IEEE 802.3 Counters */ 2278 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0, 2279 data, data_index); 2280 data_index = MLXSW_SP_PORT_HW_STATS_LEN; 2281 2282 /* RFC 2863 Counters */ 2283 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0, 2284 data, data_index); 2285 data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; 2286 2287 /* RFC 2819 Counters */ 2288 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0, 2289 data, data_index); 2290 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2291 2292 /* RFC 3635 Counters */ 2293 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0, 2294 data, data_index); 2295 data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; 2296 2297 /* Discard Counters */ 2298 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0, 2299 data, data_index); 2300 data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; 2301 2302 /* Per-Priority Counters */ 2303 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2304 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i, 2305 data, data_index); 2306 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2307 } 2308 2309 /* Per-TC Counters */ 2310 for (i = 0; i < TC_MAX_QUEUE; i++) { 2311 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i, 2312 data, data_index); 2313 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN; 2314 } 2315 } 2316 2317 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset) 2318 { 2319 switch (sset) { 2320 case ETH_SS_STATS: 2321 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN; 2322 default: 2323 return -EOPNOTSUPP; 2324 } 2325 } 2326 2327 struct mlxsw_sp1_port_link_mode { 2328 enum ethtool_link_mode_bit_indices mask_ethtool; 2329 u32 mask; 2330 u32 speed; 2331 }; 2332 2333 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = { 2334 { 2335 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, 2336 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2337 .speed = SPEED_100, 2338 }, 2339 { 2340 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | 2341 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX, 2342 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2343 .speed = SPEED_1000, 2344 }, 2345 { 2346 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, 2347 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2348 .speed = SPEED_10000, 2349 }, 2350 { 2351 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | 2352 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4, 2353 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2354 .speed = SPEED_10000, 2355 }, 2356 { 2357 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2358 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2359 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2360 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR, 2361 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2362 .speed = SPEED_10000, 2363 }, 2364 { 2365 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, 2366 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 2367 .speed = SPEED_20000, 2368 }, 2369 { 2370 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, 2371 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2372 .speed = SPEED_40000, 2373 }, 2374 { 2375 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, 2376 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2377 .speed = SPEED_40000, 2378 }, 2379 { 2380 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, 2381 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2382 .speed = SPEED_40000, 2383 }, 2384 { 2385 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, 2386 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2387 .speed = SPEED_40000, 2388 }, 2389 { 2390 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, 2391 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2392 .speed = SPEED_25000, 2393 }, 2394 { 2395 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, 2396 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2397 .speed = SPEED_25000, 2398 }, 2399 { 2400 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2401 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2402 .speed = SPEED_25000, 2403 }, 2404 { 2405 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, 2406 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2407 .speed = SPEED_50000, 2408 }, 2409 { 2410 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, 2411 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2412 .speed = SPEED_50000, 2413 }, 2414 { 2415 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, 2416 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2417 .speed = SPEED_50000, 2418 }, 2419 { 2420 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2421 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, 2422 .speed = SPEED_56000, 2423 }, 2424 { 2425 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2426 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, 2427 .speed = SPEED_56000, 2428 }, 2429 { 2430 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2431 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, 2432 .speed = SPEED_56000, 2433 }, 2434 { 2435 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2436 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, 2437 .speed = SPEED_56000, 2438 }, 2439 { 2440 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, 2441 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2442 .speed = SPEED_100000, 2443 }, 2444 { 2445 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, 2446 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2447 .speed = SPEED_100000, 2448 }, 2449 { 2450 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, 2451 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2452 .speed = SPEED_100000, 2453 }, 2454 { 2455 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, 2456 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2457 .speed = SPEED_100000, 2458 }, 2459 }; 2460 2461 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode) 2462 2463 static void 2464 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp, 2465 u32 ptys_eth_proto, 2466 struct ethtool_link_ksettings *cmd) 2467 { 2468 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2469 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2470 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2471 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2472 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2473 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2474 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2475 2476 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2477 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2478 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2479 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | 2480 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX)) 2481 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2482 } 2483 2484 static void 2485 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto, 2486 unsigned long *mode) 2487 { 2488 int i; 2489 2490 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) { 2491 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask) 2492 __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool, 2493 mode); 2494 } 2495 } 2496 2497 static void 2498 mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok, 2499 u32 ptys_eth_proto, 2500 struct ethtool_link_ksettings *cmd) 2501 { 2502 u32 speed = SPEED_UNKNOWN; 2503 u8 duplex = DUPLEX_UNKNOWN; 2504 int i; 2505 2506 if (!carrier_ok) 2507 goto out; 2508 2509 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) { 2510 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask) { 2511 speed = mlxsw_sp1_port_link_mode[i].speed; 2512 duplex = DUPLEX_FULL; 2513 break; 2514 } 2515 } 2516 out: 2517 cmd->base.speed = speed; 2518 cmd->base.duplex = duplex; 2519 } 2520 2521 static u32 2522 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, 2523 const struct ethtool_link_ksettings *cmd) 2524 { 2525 u32 ptys_proto = 0; 2526 int i; 2527 2528 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) { 2529 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool, 2530 cmd->link_modes.advertising)) 2531 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask; 2532 } 2533 return ptys_proto; 2534 } 2535 2536 static u32 mlxsw_sp1_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 speed) 2537 { 2538 u32 ptys_proto = 0; 2539 int i; 2540 2541 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) { 2542 if (speed == mlxsw_sp1_port_link_mode[i].speed) 2543 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask; 2544 } 2545 return ptys_proto; 2546 } 2547 2548 static u32 2549 mlxsw_sp1_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed) 2550 { 2551 u32 ptys_proto = 0; 2552 int i; 2553 2554 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) { 2555 if (mlxsw_sp1_port_link_mode[i].speed <= upper_speed) 2556 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask; 2557 } 2558 return ptys_proto; 2559 } 2560 2561 static int 2562 mlxsw_sp1_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port, 2563 u32 *base_speed) 2564 { 2565 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G; 2566 return 0; 2567 } 2568 2569 static void 2570 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload, 2571 u8 local_port, u32 proto_admin, bool autoneg) 2572 { 2573 mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg); 2574 } 2575 2576 static void 2577 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload, 2578 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin, 2579 u32 *p_eth_proto_oper) 2580 { 2581 mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin, 2582 p_eth_proto_oper); 2583 } 2584 2585 static const struct mlxsw_sp_port_type_speed_ops 2586 mlxsw_sp1_port_type_speed_ops = { 2587 .from_ptys_supported_port = mlxsw_sp1_from_ptys_supported_port, 2588 .from_ptys_link = mlxsw_sp1_from_ptys_link, 2589 .from_ptys_speed_duplex = mlxsw_sp1_from_ptys_speed_duplex, 2590 .to_ptys_advert_link = mlxsw_sp1_to_ptys_advert_link, 2591 .to_ptys_speed = mlxsw_sp1_to_ptys_speed, 2592 .to_ptys_upper_speed = mlxsw_sp1_to_ptys_upper_speed, 2593 .port_speed_base = mlxsw_sp1_port_speed_base, 2594 .reg_ptys_eth_pack = mlxsw_sp1_reg_ptys_eth_pack, 2595 .reg_ptys_eth_unpack = mlxsw_sp1_reg_ptys_eth_unpack, 2596 }; 2597 2598 static const enum ethtool_link_mode_bit_indices 2599 mlxsw_sp2_mask_ethtool_sgmii_100m[] = { 2600 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2601 }; 2602 2603 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \ 2604 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m) 2605 2606 static const enum ethtool_link_mode_bit_indices 2607 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = { 2608 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2609 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2610 }; 2611 2612 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \ 2613 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii) 2614 2615 static const enum ethtool_link_mode_bit_indices 2616 mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = { 2617 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 2618 }; 2619 2620 #define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \ 2621 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii) 2622 2623 static const enum ethtool_link_mode_bit_indices 2624 mlxsw_sp2_mask_ethtool_5gbase_r[] = { 2625 ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 2626 }; 2627 2628 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \ 2629 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r) 2630 2631 static const enum ethtool_link_mode_bit_indices 2632 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = { 2633 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2634 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2635 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 2636 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 2637 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 2638 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 2639 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 2640 }; 2641 2642 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \ 2643 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g) 2644 2645 static const enum ethtool_link_mode_bit_indices 2646 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = { 2647 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2648 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2649 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2650 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2651 }; 2652 2653 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \ 2654 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g) 2655 2656 static const enum ethtool_link_mode_bit_indices 2657 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = { 2658 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2659 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2660 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2661 }; 2662 2663 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \ 2664 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr) 2665 2666 static const enum ethtool_link_mode_bit_indices 2667 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = { 2668 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2669 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2670 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2671 }; 2672 2673 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \ 2674 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2) 2675 2676 static const enum ethtool_link_mode_bit_indices 2677 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = { 2678 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 2679 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 2680 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 2681 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 2682 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 2683 }; 2684 2685 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \ 2686 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr) 2687 2688 static const enum ethtool_link_mode_bit_indices 2689 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = { 2690 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2691 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2692 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2693 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2694 }; 2695 2696 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \ 2697 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4) 2698 2699 static const enum ethtool_link_mode_bit_indices 2700 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = { 2701 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 2702 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 2703 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 2704 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 2705 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 2706 }; 2707 2708 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \ 2709 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2) 2710 2711 static const enum ethtool_link_mode_bit_indices 2712 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = { 2713 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 2714 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 2715 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 2716 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, 2717 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 2718 }; 2719 2720 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \ 2721 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4) 2722 2723 struct mlxsw_sp2_port_link_mode { 2724 const enum ethtool_link_mode_bit_indices *mask_ethtool; 2725 int m_ethtool_len; 2726 u32 mask; 2727 u32 speed; 2728 }; 2729 2730 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 2731 { 2732 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M, 2733 .mask_ethtool = mlxsw_sp2_mask_ethtool_sgmii_100m, 2734 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN, 2735 .speed = SPEED_100, 2736 }, 2737 { 2738 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII, 2739 .mask_ethtool = mlxsw_sp2_mask_ethtool_1000base_x_sgmii, 2740 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN, 2741 .speed = SPEED_1000, 2742 }, 2743 { 2744 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII, 2745 .mask_ethtool = mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii, 2746 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN, 2747 .speed = SPEED_2500, 2748 }, 2749 { 2750 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R, 2751 .mask_ethtool = mlxsw_sp2_mask_ethtool_5gbase_r, 2752 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN, 2753 .speed = SPEED_5000, 2754 }, 2755 { 2756 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G, 2757 .mask_ethtool = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g, 2758 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN, 2759 .speed = SPEED_10000, 2760 }, 2761 { 2762 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G, 2763 .mask_ethtool = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g, 2764 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN, 2765 .speed = SPEED_40000, 2766 }, 2767 { 2768 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR, 2769 .mask_ethtool = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr, 2770 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN, 2771 .speed = SPEED_25000, 2772 }, 2773 { 2774 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, 2775 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2, 2776 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN, 2777 .speed = SPEED_50000, 2778 }, 2779 { 2780 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR, 2781 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr, 2782 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN, 2783 .speed = SPEED_50000, 2784 }, 2785 { 2786 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4, 2787 .mask_ethtool = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4, 2788 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN, 2789 .speed = SPEED_100000, 2790 }, 2791 { 2792 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2, 2793 .mask_ethtool = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2, 2794 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN, 2795 .speed = SPEED_100000, 2796 }, 2797 { 2798 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4, 2799 .mask_ethtool = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4, 2800 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN, 2801 .speed = SPEED_200000, 2802 }, 2803 }; 2804 2805 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode) 2806 2807 static void 2808 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp, 2809 u32 ptys_eth_proto, 2810 struct ethtool_link_ksettings *cmd) 2811 { 2812 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2813 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2814 } 2815 2816 static void 2817 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode, 2818 unsigned long *mode) 2819 { 2820 int i; 2821 2822 for (i = 0; i < link_mode->m_ethtool_len; i++) 2823 __set_bit(link_mode->mask_ethtool[i], mode); 2824 } 2825 2826 static void 2827 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto, 2828 unsigned long *mode) 2829 { 2830 int i; 2831 2832 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { 2833 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) 2834 mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i], 2835 mode); 2836 } 2837 } 2838 2839 static void 2840 mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok, 2841 u32 ptys_eth_proto, 2842 struct ethtool_link_ksettings *cmd) 2843 { 2844 u32 speed = SPEED_UNKNOWN; 2845 u8 duplex = DUPLEX_UNKNOWN; 2846 int i; 2847 2848 if (!carrier_ok) 2849 goto out; 2850 2851 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { 2852 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) { 2853 speed = mlxsw_sp2_port_link_mode[i].speed; 2854 duplex = DUPLEX_FULL; 2855 break; 2856 } 2857 } 2858 out: 2859 cmd->base.speed = speed; 2860 cmd->base.duplex = duplex; 2861 } 2862 2863 static bool 2864 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode, 2865 const unsigned long *mode) 2866 { 2867 int cnt = 0; 2868 int i; 2869 2870 for (i = 0; i < link_mode->m_ethtool_len; i++) { 2871 if (test_bit(link_mode->mask_ethtool[i], mode)) 2872 cnt++; 2873 } 2874 2875 return cnt == link_mode->m_ethtool_len; 2876 } 2877 2878 static u32 2879 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, 2880 const struct ethtool_link_ksettings *cmd) 2881 { 2882 u32 ptys_proto = 0; 2883 int i; 2884 2885 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { 2886 if (mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i], 2887 cmd->link_modes.advertising)) 2888 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask; 2889 } 2890 return ptys_proto; 2891 } 2892 2893 static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 speed) 2894 { 2895 u32 ptys_proto = 0; 2896 int i; 2897 2898 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { 2899 if (speed == mlxsw_sp2_port_link_mode[i].speed) 2900 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask; 2901 } 2902 return ptys_proto; 2903 } 2904 2905 static u32 2906 mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed) 2907 { 2908 u32 ptys_proto = 0; 2909 int i; 2910 2911 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) { 2912 if (mlxsw_sp2_port_link_mode[i].speed <= upper_speed) 2913 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask; 2914 } 2915 return ptys_proto; 2916 } 2917 2918 static int 2919 mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port, 2920 u32 *base_speed) 2921 { 2922 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2923 u32 eth_proto_cap; 2924 int err; 2925 2926 /* In Spectrum-2, the speed of 1x can change from port to port, so query 2927 * it from firmware. 2928 */ 2929 mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false); 2930 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2931 if (err) 2932 return err; 2933 mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); 2934 2935 if (eth_proto_cap & 2936 MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) { 2937 *base_speed = MLXSW_SP_PORT_BASE_SPEED_50G; 2938 return 0; 2939 } 2940 2941 if (eth_proto_cap & 2942 MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) { 2943 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G; 2944 return 0; 2945 } 2946 2947 return -EIO; 2948 } 2949 2950 static void 2951 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload, 2952 u8 local_port, u32 proto_admin, 2953 bool autoneg) 2954 { 2955 mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg); 2956 } 2957 2958 static void 2959 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload, 2960 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin, 2961 u32 *p_eth_proto_oper) 2962 { 2963 mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap, 2964 p_eth_proto_admin, p_eth_proto_oper); 2965 } 2966 2967 static const struct mlxsw_sp_port_type_speed_ops 2968 mlxsw_sp2_port_type_speed_ops = { 2969 .from_ptys_supported_port = mlxsw_sp2_from_ptys_supported_port, 2970 .from_ptys_link = mlxsw_sp2_from_ptys_link, 2971 .from_ptys_speed_duplex = mlxsw_sp2_from_ptys_speed_duplex, 2972 .to_ptys_advert_link = mlxsw_sp2_to_ptys_advert_link, 2973 .to_ptys_speed = mlxsw_sp2_to_ptys_speed, 2974 .to_ptys_upper_speed = mlxsw_sp2_to_ptys_upper_speed, 2975 .port_speed_base = mlxsw_sp2_port_speed_base, 2976 .reg_ptys_eth_pack = mlxsw_sp2_reg_ptys_eth_pack, 2977 .reg_ptys_eth_unpack = mlxsw_sp2_reg_ptys_eth_unpack, 2978 }; 2979 2980 static void 2981 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap, 2982 struct ethtool_link_ksettings *cmd) 2983 { 2984 const struct mlxsw_sp_port_type_speed_ops *ops; 2985 2986 ops = mlxsw_sp->port_type_speed_ops; 2987 2988 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause); 2989 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 2990 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 2991 2992 ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd); 2993 ops->from_ptys_link(mlxsw_sp, eth_proto_cap, cmd->link_modes.supported); 2994 } 2995 2996 static void 2997 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp, 2998 u32 eth_proto_admin, bool autoneg, 2999 struct ethtool_link_ksettings *cmd) 3000 { 3001 const struct mlxsw_sp_port_type_speed_ops *ops; 3002 3003 ops = mlxsw_sp->port_type_speed_ops; 3004 3005 if (!autoneg) 3006 return; 3007 3008 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 3009 ops->from_ptys_link(mlxsw_sp, eth_proto_admin, 3010 cmd->link_modes.advertising); 3011 } 3012 3013 static u8 3014 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type) 3015 { 3016 switch (connector_type) { 3017 case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR: 3018 return PORT_OTHER; 3019 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE: 3020 return PORT_NONE; 3021 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP: 3022 return PORT_TP; 3023 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI: 3024 return PORT_AUI; 3025 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC: 3026 return PORT_BNC; 3027 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII: 3028 return PORT_MII; 3029 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE: 3030 return PORT_FIBRE; 3031 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA: 3032 return PORT_DA; 3033 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER: 3034 return PORT_OTHER; 3035 default: 3036 WARN_ON_ONCE(1); 3037 return PORT_OTHER; 3038 } 3039 } 3040 3041 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev, 3042 struct ethtool_link_ksettings *cmd) 3043 { 3044 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper; 3045 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 3046 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3047 const struct mlxsw_sp_port_type_speed_ops *ops; 3048 char ptys_pl[MLXSW_REG_PTYS_LEN]; 3049 u8 connector_type; 3050 bool autoneg; 3051 int err; 3052 3053 ops = mlxsw_sp->port_type_speed_ops; 3054 3055 autoneg = mlxsw_sp_port->link.autoneg; 3056 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 3057 0, false); 3058 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 3059 if (err) 3060 return err; 3061 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, 3062 ð_proto_admin, ð_proto_oper); 3063 3064 mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap, cmd); 3065 3066 mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg, 3067 cmd); 3068 3069 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3070 connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl); 3071 cmd->base.port = mlxsw_sp_port_connector_port(connector_type); 3072 ops->from_ptys_speed_duplex(mlxsw_sp, netif_carrier_ok(dev), 3073 eth_proto_oper, cmd); 3074 3075 return 0; 3076 } 3077 3078 static int 3079 mlxsw_sp_port_set_link_ksettings(struct net_device *dev, 3080 const struct ethtool_link_ksettings *cmd) 3081 { 3082 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 3083 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3084 const struct mlxsw_sp_port_type_speed_ops *ops; 3085 char ptys_pl[MLXSW_REG_PTYS_LEN]; 3086 u32 eth_proto_cap, eth_proto_new; 3087 bool autoneg; 3088 int err; 3089 3090 ops = mlxsw_sp->port_type_speed_ops; 3091 3092 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 3093 0, false); 3094 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 3095 if (err) 3096 return err; 3097 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, NULL, NULL); 3098 3099 autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 3100 eth_proto_new = autoneg ? 3101 ops->to_ptys_advert_link(mlxsw_sp, cmd) : 3102 ops->to_ptys_speed(mlxsw_sp, cmd->base.speed); 3103 3104 eth_proto_new = eth_proto_new & eth_proto_cap; 3105 if (!eth_proto_new) { 3106 netdev_err(dev, "No supported speed requested\n"); 3107 return -EINVAL; 3108 } 3109 3110 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 3111 eth_proto_new, autoneg); 3112 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 3113 if (err) 3114 return err; 3115 3116 if (!netif_running(dev)) 3117 return 0; 3118 3119 mlxsw_sp_port->link.autoneg = autoneg; 3120 3121 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 3122 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 3123 3124 return 0; 3125 } 3126 3127 static int mlxsw_sp_flash_device(struct net_device *dev, 3128 struct ethtool_flash *flash) 3129 { 3130 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 3131 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3132 const struct firmware *firmware; 3133 int err; 3134 3135 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 3136 return -EOPNOTSUPP; 3137 3138 dev_hold(dev); 3139 rtnl_unlock(); 3140 3141 err = request_firmware_direct(&firmware, flash->data, &dev->dev); 3142 if (err) 3143 goto out; 3144 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 3145 release_firmware(firmware); 3146 out: 3147 rtnl_lock(); 3148 dev_put(dev); 3149 return err; 3150 } 3151 3152 static int mlxsw_sp_get_module_info(struct net_device *netdev, 3153 struct ethtool_modinfo *modinfo) 3154 { 3155 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 3156 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3157 int err; 3158 3159 err = mlxsw_env_get_module_info(mlxsw_sp->core, 3160 mlxsw_sp_port->mapping.module, 3161 modinfo); 3162 3163 return err; 3164 } 3165 3166 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev, 3167 struct ethtool_eeprom *ee, 3168 u8 *data) 3169 { 3170 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 3171 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3172 int err; 3173 3174 err = mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core, 3175 mlxsw_sp_port->mapping.module, ee, 3176 data); 3177 3178 return err; 3179 } 3180 3181 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { 3182 .get_drvinfo = mlxsw_sp_port_get_drvinfo, 3183 .get_link = ethtool_op_get_link, 3184 .get_pauseparam = mlxsw_sp_port_get_pauseparam, 3185 .set_pauseparam = mlxsw_sp_port_set_pauseparam, 3186 .get_strings = mlxsw_sp_port_get_strings, 3187 .set_phys_id = mlxsw_sp_port_set_phys_id, 3188 .get_ethtool_stats = mlxsw_sp_port_get_stats, 3189 .get_sset_count = mlxsw_sp_port_get_sset_count, 3190 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings, 3191 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings, 3192 .flash_device = mlxsw_sp_flash_device, 3193 .get_module_info = mlxsw_sp_get_module_info, 3194 .get_module_eeprom = mlxsw_sp_get_module_eeprom, 3195 }; 3196 3197 static int 3198 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width) 3199 { 3200 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3201 const struct mlxsw_sp_port_type_speed_ops *ops; 3202 char ptys_pl[MLXSW_REG_PTYS_LEN]; 3203 u32 eth_proto_admin; 3204 u32 upper_speed; 3205 u32 base_speed; 3206 int err; 3207 3208 ops = mlxsw_sp->port_type_speed_ops; 3209 3210 err = ops->port_speed_base(mlxsw_sp, mlxsw_sp_port->local_port, 3211 &base_speed); 3212 if (err) 3213 return err; 3214 upper_speed = base_speed * width; 3215 3216 eth_proto_admin = ops->to_ptys_upper_speed(mlxsw_sp, upper_speed); 3217 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 3218 eth_proto_admin, mlxsw_sp_port->link.autoneg); 3219 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 3220 } 3221 3222 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 3223 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 3224 bool dwrr, u8 dwrr_weight) 3225 { 3226 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3227 char qeec_pl[MLXSW_REG_QEEC_LEN]; 3228 3229 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 3230 next_index); 3231 mlxsw_reg_qeec_de_set(qeec_pl, true); 3232 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 3233 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 3234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 3235 } 3236 3237 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 3238 enum mlxsw_reg_qeec_hr hr, u8 index, 3239 u8 next_index, u32 maxrate) 3240 { 3241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3242 char qeec_pl[MLXSW_REG_QEEC_LEN]; 3243 3244 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 3245 next_index); 3246 mlxsw_reg_qeec_mase_set(qeec_pl, true); 3247 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 3248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 3249 } 3250 3251 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 3252 enum mlxsw_reg_qeec_hr hr, u8 index, 3253 u8 next_index, u32 minrate) 3254 { 3255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3256 char qeec_pl[MLXSW_REG_QEEC_LEN]; 3257 3258 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 3259 next_index); 3260 mlxsw_reg_qeec_mise_set(qeec_pl, true); 3261 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 3262 3263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 3264 } 3265 3266 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 3267 u8 switch_prio, u8 tclass) 3268 { 3269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3270 char qtct_pl[MLXSW_REG_QTCT_LEN]; 3271 3272 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 3273 tclass); 3274 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 3275 } 3276 3277 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 3278 { 3279 int err, i; 3280 3281 /* Setup the elements hierarcy, so that each TC is linked to 3282 * one subgroup, which are all member in the same group. 3283 */ 3284 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 3285 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false, 3286 0); 3287 if (err) 3288 return err; 3289 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 3290 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 3291 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i, 3292 0, false, 0); 3293 if (err) 3294 return err; 3295 } 3296 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 3297 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 3298 MLXSW_REG_QEEC_HIERARCY_TC, i, i, 3299 false, 0); 3300 if (err) 3301 return err; 3302 3303 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 3304 MLXSW_REG_QEEC_HIERARCY_TC, 3305 i + 8, i, 3306 false, 0); 3307 if (err) 3308 return err; 3309 } 3310 3311 /* Make sure the max shaper is disabled in all hierarchies that 3312 * support it. 3313 */ 3314 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 3315 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0, 3316 MLXSW_REG_QEEC_MAS_DIS); 3317 if (err) 3318 return err; 3319 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 3320 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 3321 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3322 i, 0, 3323 MLXSW_REG_QEEC_MAS_DIS); 3324 if (err) 3325 return err; 3326 } 3327 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 3328 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 3329 MLXSW_REG_QEEC_HIERARCY_TC, 3330 i, i, 3331 MLXSW_REG_QEEC_MAS_DIS); 3332 if (err) 3333 return err; 3334 3335 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 3336 MLXSW_REG_QEEC_HIERARCY_TC, 3337 i + 8, i, 3338 MLXSW_REG_QEEC_MAS_DIS); 3339 if (err) 3340 return err; 3341 } 3342 3343 /* Configure the min shaper for multicast TCs. */ 3344 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 3345 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 3346 MLXSW_REG_QEEC_HIERARCY_TC, 3347 i + 8, i, 3348 MLXSW_REG_QEEC_MIS_MIN); 3349 if (err) 3350 return err; 3351 } 3352 3353 /* Map all priorities to traffic class 0. */ 3354 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 3355 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 3356 if (err) 3357 return err; 3358 } 3359 3360 return 0; 3361 } 3362 3363 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 3364 bool enable) 3365 { 3366 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 3367 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 3368 3369 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 3370 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 3371 } 3372 3373 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 3374 bool split, u8 module, u8 width, u8 lane) 3375 { 3376 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 3377 struct mlxsw_sp_port *mlxsw_sp_port; 3378 struct net_device *dev; 3379 int err; 3380 3381 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, 3382 module + 1, split, lane / width, 3383 mlxsw_sp->base_mac, 3384 sizeof(mlxsw_sp->base_mac)); 3385 if (err) { 3386 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 3387 local_port); 3388 return err; 3389 } 3390 3391 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 3392 if (!dev) { 3393 err = -ENOMEM; 3394 goto err_alloc_etherdev; 3395 } 3396 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 3397 mlxsw_sp_port = netdev_priv(dev); 3398 mlxsw_sp_port->dev = dev; 3399 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 3400 mlxsw_sp_port->local_port = local_port; 3401 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; 3402 mlxsw_sp_port->split = split; 3403 mlxsw_sp_port->mapping.module = module; 3404 mlxsw_sp_port->mapping.width = width; 3405 mlxsw_sp_port->mapping.lane = lane; 3406 mlxsw_sp_port->link.autoneg = 1; 3407 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 3408 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list); 3409 3410 mlxsw_sp_port->pcpu_stats = 3411 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 3412 if (!mlxsw_sp_port->pcpu_stats) { 3413 err = -ENOMEM; 3414 goto err_alloc_stats; 3415 } 3416 3417 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample), 3418 GFP_KERNEL); 3419 if (!mlxsw_sp_port->sample) { 3420 err = -ENOMEM; 3421 goto err_alloc_sample; 3422 } 3423 3424 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 3425 &update_stats_cache); 3426 3427 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 3428 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 3429 3430 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); 3431 if (err) { 3432 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 3433 mlxsw_sp_port->local_port); 3434 goto err_port_module_map; 3435 } 3436 3437 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0); 3438 if (err) { 3439 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 3440 mlxsw_sp_port->local_port); 3441 goto err_port_swid_set; 3442 } 3443 3444 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 3445 if (err) { 3446 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 3447 mlxsw_sp_port->local_port); 3448 goto err_dev_addr_init; 3449 } 3450 3451 netif_carrier_off(dev); 3452 3453 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 3454 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 3455 dev->hw_features |= NETIF_F_HW_TC; 3456 3457 dev->min_mtu = 0; 3458 dev->max_mtu = ETH_MAX_MTU; 3459 3460 /* Each packet needs to have a Tx header (metadata) on top all other 3461 * headers. 3462 */ 3463 dev->needed_headroom = MLXSW_TXHDR_LEN; 3464 3465 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 3466 if (err) { 3467 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 3468 mlxsw_sp_port->local_port); 3469 goto err_port_system_port_mapping_set; 3470 } 3471 3472 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width); 3473 if (err) { 3474 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 3475 mlxsw_sp_port->local_port); 3476 goto err_port_speed_by_width_set; 3477 } 3478 3479 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 3480 if (err) { 3481 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 3482 mlxsw_sp_port->local_port); 3483 goto err_port_mtu_set; 3484 } 3485 3486 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 3487 if (err) 3488 goto err_port_admin_status_set; 3489 3490 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 3491 if (err) { 3492 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 3493 mlxsw_sp_port->local_port); 3494 goto err_port_buffers_init; 3495 } 3496 3497 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 3498 if (err) { 3499 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 3500 mlxsw_sp_port->local_port); 3501 goto err_port_ets_init; 3502 } 3503 3504 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 3505 if (err) { 3506 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 3507 mlxsw_sp_port->local_port); 3508 goto err_port_tc_mc_mode; 3509 } 3510 3511 /* ETS and buffers must be initialized before DCB. */ 3512 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 3513 if (err) { 3514 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 3515 mlxsw_sp_port->local_port); 3516 goto err_port_dcb_init; 3517 } 3518 3519 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 3520 if (err) { 3521 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 3522 mlxsw_sp_port->local_port); 3523 goto err_port_fids_init; 3524 } 3525 3526 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 3527 if (err) { 3528 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 3529 mlxsw_sp_port->local_port); 3530 goto err_port_qdiscs_init; 3531 } 3532 3533 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 3534 if (err) { 3535 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 3536 mlxsw_sp_port->local_port); 3537 goto err_port_nve_init; 3538 } 3539 3540 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID); 3541 if (err) { 3542 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n", 3543 mlxsw_sp_port->local_port); 3544 goto err_port_pvid_set; 3545 } 3546 3547 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, 3548 MLXSW_SP_DEFAULT_VID); 3549 if (IS_ERR(mlxsw_sp_port_vlan)) { 3550 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 3551 mlxsw_sp_port->local_port); 3552 err = PTR_ERR(mlxsw_sp_port_vlan); 3553 goto err_port_vlan_create; 3554 } 3555 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan; 3556 3557 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 3558 err = register_netdev(dev); 3559 if (err) { 3560 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 3561 mlxsw_sp_port->local_port); 3562 goto err_register_netdev; 3563 } 3564 3565 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 3566 mlxsw_sp_port, dev); 3567 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 3568 return 0; 3569 3570 err_register_netdev: 3571 mlxsw_sp->ports[local_port] = NULL; 3572 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 3573 err_port_vlan_create: 3574 err_port_pvid_set: 3575 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 3576 err_port_nve_init: 3577 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3578 err_port_qdiscs_init: 3579 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3580 err_port_fids_init: 3581 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3582 err_port_dcb_init: 3583 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3584 err_port_tc_mc_mode: 3585 err_port_ets_init: 3586 err_port_buffers_init: 3587 err_port_admin_status_set: 3588 err_port_mtu_set: 3589 err_port_speed_by_width_set: 3590 err_port_system_port_mapping_set: 3591 err_dev_addr_init: 3592 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3593 err_port_swid_set: 3594 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3595 err_port_module_map: 3596 kfree(mlxsw_sp_port->sample); 3597 err_alloc_sample: 3598 free_percpu(mlxsw_sp_port->pcpu_stats); 3599 err_alloc_stats: 3600 free_netdev(dev); 3601 err_alloc_etherdev: 3602 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3603 return err; 3604 } 3605 3606 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3607 { 3608 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3609 3610 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 3611 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 3612 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 3613 mlxsw_sp->ports[local_port] = NULL; 3614 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); 3615 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 3616 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3617 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3618 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3619 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3620 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3621 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3622 kfree(mlxsw_sp_port->sample); 3623 free_percpu(mlxsw_sp_port->pcpu_stats); 3624 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 3625 free_netdev(mlxsw_sp_port->dev); 3626 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3627 } 3628 3629 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3630 { 3631 return mlxsw_sp->ports[local_port] != NULL; 3632 } 3633 3634 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 3635 { 3636 int i; 3637 3638 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 3639 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3640 mlxsw_sp_port_remove(mlxsw_sp, i); 3641 kfree(mlxsw_sp->port_to_module); 3642 kfree(mlxsw_sp->ports); 3643 } 3644 3645 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 3646 { 3647 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 3648 u8 module, width, lane; 3649 size_t alloc_size; 3650 int i; 3651 int err; 3652 3653 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 3654 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 3655 if (!mlxsw_sp->ports) 3656 return -ENOMEM; 3657 3658 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int), 3659 GFP_KERNEL); 3660 if (!mlxsw_sp->port_to_module) { 3661 err = -ENOMEM; 3662 goto err_port_to_module_alloc; 3663 } 3664 3665 for (i = 1; i < max_ports; i++) { 3666 /* Mark as invalid */ 3667 mlxsw_sp->port_to_module[i] = -1; 3668 3669 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module, 3670 &width, &lane); 3671 if (err) 3672 goto err_port_module_info_get; 3673 if (!width) 3674 continue; 3675 mlxsw_sp->port_to_module[i] = module; 3676 err = mlxsw_sp_port_create(mlxsw_sp, i, false, 3677 module, width, lane); 3678 if (err) 3679 goto err_port_create; 3680 } 3681 return 0; 3682 3683 err_port_create: 3684 err_port_module_info_get: 3685 for (i--; i >= 1; i--) 3686 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3687 mlxsw_sp_port_remove(mlxsw_sp, i); 3688 kfree(mlxsw_sp->port_to_module); 3689 err_port_to_module_alloc: 3690 kfree(mlxsw_sp->ports); 3691 return err; 3692 } 3693 3694 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port) 3695 { 3696 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX; 3697 3698 return local_port - offset; 3699 } 3700 3701 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port, 3702 u8 module, unsigned int count) 3703 { 3704 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count; 3705 int err, i; 3706 3707 for (i = 0; i < count; i++) { 3708 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true, 3709 module, width, i * width); 3710 if (err) 3711 goto err_port_create; 3712 } 3713 3714 return 0; 3715 3716 err_port_create: 3717 for (i--; i >= 0; i--) 3718 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3719 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3720 return err; 3721 } 3722 3723 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 3724 u8 base_port, unsigned int count) 3725 { 3726 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH; 3727 int i; 3728 3729 /* Split by four means we need to re-create two ports, otherwise 3730 * only one. 3731 */ 3732 count = count / 2; 3733 3734 for (i = 0; i < count; i++) { 3735 local_port = base_port + i * 2; 3736 if (mlxsw_sp->port_to_module[local_port] < 0) 3737 continue; 3738 module = mlxsw_sp->port_to_module[local_port]; 3739 3740 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module, 3741 width, 0); 3742 } 3743 } 3744 3745 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 3746 unsigned int count, 3747 struct netlink_ext_ack *extack) 3748 { 3749 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3750 struct mlxsw_sp_port *mlxsw_sp_port; 3751 u8 module, cur_width, base_port; 3752 int i; 3753 int err; 3754 3755 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3756 if (!mlxsw_sp_port) { 3757 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3758 local_port); 3759 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3760 return -EINVAL; 3761 } 3762 3763 module = mlxsw_sp_port->mapping.module; 3764 cur_width = mlxsw_sp_port->mapping.width; 3765 3766 if (count != 2 && count != 4) { 3767 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n"); 3768 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports"); 3769 return -EINVAL; 3770 } 3771 3772 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) { 3773 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n"); 3774 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further"); 3775 return -EINVAL; 3776 } 3777 3778 /* Make sure we have enough slave (even) ports for the split. */ 3779 if (count == 2) { 3780 base_port = local_port; 3781 if (mlxsw_sp->ports[base_port + 1]) { 3782 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3783 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3784 return -EINVAL; 3785 } 3786 } else { 3787 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3788 if (mlxsw_sp->ports[base_port + 1] || 3789 mlxsw_sp->ports[base_port + 3]) { 3790 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3791 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3792 return -EINVAL; 3793 } 3794 } 3795 3796 for (i = 0; i < count; i++) 3797 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3798 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3799 3800 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count); 3801 if (err) { 3802 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 3803 goto err_port_split_create; 3804 } 3805 3806 return 0; 3807 3808 err_port_split_create: 3809 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3810 return err; 3811 } 3812 3813 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port, 3814 struct netlink_ext_ack *extack) 3815 { 3816 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3817 struct mlxsw_sp_port *mlxsw_sp_port; 3818 u8 cur_width, base_port; 3819 unsigned int count; 3820 int i; 3821 3822 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3823 if (!mlxsw_sp_port) { 3824 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3825 local_port); 3826 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3827 return -EINVAL; 3828 } 3829 3830 if (!mlxsw_sp_port->split) { 3831 netdev_err(mlxsw_sp_port->dev, "Port was not split\n"); 3832 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 3833 return -EINVAL; 3834 } 3835 3836 cur_width = mlxsw_sp_port->mapping.width; 3837 count = cur_width == 1 ? 4 : 2; 3838 3839 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3840 3841 /* Determine which ports to remove. */ 3842 if (count == 2 && local_port >= base_port + 2) 3843 base_port = base_port + 2; 3844 3845 for (i = 0; i < count; i++) 3846 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3847 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3848 3849 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3850 3851 return 0; 3852 } 3853 3854 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 3855 char *pude_pl, void *priv) 3856 { 3857 struct mlxsw_sp *mlxsw_sp = priv; 3858 struct mlxsw_sp_port *mlxsw_sp_port; 3859 enum mlxsw_reg_pude_oper_status status; 3860 u8 local_port; 3861 3862 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 3863 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3864 if (!mlxsw_sp_port) 3865 return; 3866 3867 status = mlxsw_reg_pude_oper_status_get(pude_pl); 3868 if (status == MLXSW_PORT_OPER_STATUS_UP) { 3869 netdev_info(mlxsw_sp_port->dev, "link up\n"); 3870 netif_carrier_on(mlxsw_sp_port->dev); 3871 } else { 3872 netdev_info(mlxsw_sp_port->dev, "link down\n"); 3873 netif_carrier_off(mlxsw_sp_port->dev); 3874 } 3875 } 3876 3877 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 3878 u8 local_port, void *priv) 3879 { 3880 struct mlxsw_sp *mlxsw_sp = priv; 3881 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3882 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 3883 3884 if (unlikely(!mlxsw_sp_port)) { 3885 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 3886 local_port); 3887 return; 3888 } 3889 3890 skb->dev = mlxsw_sp_port->dev; 3891 3892 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 3893 u64_stats_update_begin(&pcpu_stats->syncp); 3894 pcpu_stats->rx_packets++; 3895 pcpu_stats->rx_bytes += skb->len; 3896 u64_stats_update_end(&pcpu_stats->syncp); 3897 3898 skb->protocol = eth_type_trans(skb, skb->dev); 3899 netif_receive_skb(skb); 3900 } 3901 3902 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 3903 void *priv) 3904 { 3905 skb->offload_fwd_mark = 1; 3906 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3907 } 3908 3909 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb, 3910 u8 local_port, void *priv) 3911 { 3912 skb->offload_l3_fwd_mark = 1; 3913 skb->offload_fwd_mark = 1; 3914 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3915 } 3916 3917 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port, 3918 void *priv) 3919 { 3920 struct mlxsw_sp *mlxsw_sp = priv; 3921 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3922 struct psample_group *psample_group; 3923 u32 size; 3924 3925 if (unlikely(!mlxsw_sp_port)) { 3926 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n", 3927 local_port); 3928 goto out; 3929 } 3930 if (unlikely(!mlxsw_sp_port->sample)) { 3931 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n", 3932 local_port); 3933 goto out; 3934 } 3935 3936 size = mlxsw_sp_port->sample->truncate ? 3937 mlxsw_sp_port->sample->trunc_size : skb->len; 3938 3939 rcu_read_lock(); 3940 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group); 3941 if (!psample_group) 3942 goto out_unlock; 3943 psample_sample_packet(psample_group, skb, size, 3944 mlxsw_sp_port->dev->ifindex, 0, 3945 mlxsw_sp_port->sample->rate); 3946 out_unlock: 3947 rcu_read_unlock(); 3948 out: 3949 consume_skb(skb); 3950 } 3951 3952 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3953 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 3954 _is_ctrl, SP_##_trap_group, DISCARD) 3955 3956 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3957 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 3958 _is_ctrl, SP_##_trap_group, DISCARD) 3959 3960 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3961 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \ 3962 _is_ctrl, SP_##_trap_group, DISCARD) 3963 3964 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 3965 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 3966 3967 static const struct mlxsw_listener mlxsw_sp_listener[] = { 3968 /* Events */ 3969 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 3970 /* L2 traps */ 3971 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true), 3972 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true), 3973 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true), 3974 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false), 3975 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false), 3976 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false), 3977 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false), 3978 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false), 3979 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false), 3980 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false), 3981 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false), 3982 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false), 3983 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD, 3984 false), 3985 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3986 false), 3987 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD, 3988 false), 3989 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3990 false), 3991 /* L3 traps */ 3992 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3993 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3994 MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false), 3995 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false), 3996 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 3997 false), 3998 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false), 3999 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 4000 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false), 4001 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP, 4002 false), 4003 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false), 4004 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false), 4005 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false), 4006 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false), 4007 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false), 4008 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false), 4009 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 4010 false), 4011 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 4012 false), 4013 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 4014 false), 4015 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 4016 false), 4017 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false), 4018 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 4019 false), 4020 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false), 4021 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false), 4022 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false), 4023 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false), 4024 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false), 4025 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false), 4026 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 4027 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 4028 /* PKT Sample trap */ 4029 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU, 4030 false, SP_IP2ME, DISCARD), 4031 /* ACL trap */ 4032 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false), 4033 /* Multicast Router Traps */ 4034 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false), 4035 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false), 4036 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false), 4037 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 4038 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 4039 /* NVE traps */ 4040 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false), 4041 MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false), 4042 }; 4043 4044 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 4045 { 4046 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 4047 enum mlxsw_reg_qpcr_ir_units ir_units; 4048 int max_cpu_policers; 4049 bool is_bytes; 4050 u8 burst_size; 4051 u32 rate; 4052 int i, err; 4053 4054 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 4055 return -EIO; 4056 4057 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 4058 4059 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 4060 for (i = 0; i < max_cpu_policers; i++) { 4061 is_bytes = false; 4062 switch (i) { 4063 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 4064 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 4065 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 4066 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 4067 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 4068 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 4069 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR: 4070 rate = 128; 4071 burst_size = 7; 4072 break; 4073 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 4074 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 4075 rate = 16 * 1024; 4076 burst_size = 10; 4077 break; 4078 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 4079 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 4080 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 4081 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 4082 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 4083 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 4084 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 4085 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 4086 rate = 1024; 4087 burst_size = 7; 4088 break; 4089 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 4090 rate = 1024; 4091 burst_size = 7; 4092 break; 4093 default: 4094 continue; 4095 } 4096 4097 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 4098 burst_size); 4099 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 4100 if (err) 4101 return err; 4102 } 4103 4104 return 0; 4105 } 4106 4107 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 4108 { 4109 char htgt_pl[MLXSW_REG_HTGT_LEN]; 4110 enum mlxsw_reg_htgt_trap_group i; 4111 int max_cpu_policers; 4112 int max_trap_groups; 4113 u8 priority, tc; 4114 u16 policer_id; 4115 int err; 4116 4117 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 4118 return -EIO; 4119 4120 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 4121 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 4122 4123 for (i = 0; i < max_trap_groups; i++) { 4124 policer_id = i; 4125 switch (i) { 4126 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 4127 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 4128 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 4129 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 4130 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 4131 priority = 5; 4132 tc = 5; 4133 break; 4134 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 4135 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 4136 priority = 4; 4137 tc = 4; 4138 break; 4139 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 4140 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 4141 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 4142 priority = 3; 4143 tc = 3; 4144 break; 4145 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 4146 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 4147 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 4148 priority = 2; 4149 tc = 2; 4150 break; 4151 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 4152 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 4153 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 4154 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 4155 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR: 4156 priority = 1; 4157 tc = 1; 4158 break; 4159 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 4160 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 4161 tc = MLXSW_REG_HTGT_DEFAULT_TC; 4162 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 4163 break; 4164 default: 4165 continue; 4166 } 4167 4168 if (max_cpu_policers <= policer_id && 4169 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 4170 return -EIO; 4171 4172 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 4173 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 4174 if (err) 4175 return err; 4176 } 4177 4178 return 0; 4179 } 4180 4181 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 4182 { 4183 int i; 4184 int err; 4185 4186 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 4187 if (err) 4188 return err; 4189 4190 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 4191 if (err) 4192 return err; 4193 4194 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 4195 err = mlxsw_core_trap_register(mlxsw_sp->core, 4196 &mlxsw_sp_listener[i], 4197 mlxsw_sp); 4198 if (err) 4199 goto err_listener_register; 4200 4201 } 4202 return 0; 4203 4204 err_listener_register: 4205 for (i--; i >= 0; i--) { 4206 mlxsw_core_trap_unregister(mlxsw_sp->core, 4207 &mlxsw_sp_listener[i], 4208 mlxsw_sp); 4209 } 4210 return err; 4211 } 4212 4213 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 4214 { 4215 int i; 4216 4217 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 4218 mlxsw_core_trap_unregister(mlxsw_sp->core, 4219 &mlxsw_sp_listener[i], 4220 mlxsw_sp); 4221 } 4222 } 4223 4224 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 4225 { 4226 char slcr_pl[MLXSW_REG_SLCR_LEN]; 4227 u32 seed; 4228 int err; 4229 4230 get_random_bytes(&seed, sizeof(seed)); 4231 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 4232 MLXSW_REG_SLCR_LAG_HASH_DMAC | 4233 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 4234 MLXSW_REG_SLCR_LAG_HASH_VLANID | 4235 MLXSW_REG_SLCR_LAG_HASH_SIP | 4236 MLXSW_REG_SLCR_LAG_HASH_DIP | 4237 MLXSW_REG_SLCR_LAG_HASH_SPORT | 4238 MLXSW_REG_SLCR_LAG_HASH_DPORT | 4239 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 4240 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 4241 if (err) 4242 return err; 4243 4244 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 4245 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 4246 return -EIO; 4247 4248 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 4249 sizeof(struct mlxsw_sp_upper), 4250 GFP_KERNEL); 4251 if (!mlxsw_sp->lags) 4252 return -ENOMEM; 4253 4254 return 0; 4255 } 4256 4257 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 4258 { 4259 kfree(mlxsw_sp->lags); 4260 } 4261 4262 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 4263 { 4264 char htgt_pl[MLXSW_REG_HTGT_LEN]; 4265 4266 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 4267 MLXSW_REG_HTGT_INVALID_POLICER, 4268 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 4269 MLXSW_REG_HTGT_DEFAULT_TC); 4270 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 4271 } 4272 4273 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 4274 unsigned long event, void *ptr); 4275 4276 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 4277 const struct mlxsw_bus_info *mlxsw_bus_info) 4278 { 4279 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4280 int err; 4281 4282 mlxsw_sp->core = mlxsw_core; 4283 mlxsw_sp->bus_info = mlxsw_bus_info; 4284 4285 err = mlxsw_sp_fw_rev_validate(mlxsw_sp); 4286 if (err) 4287 return err; 4288 4289 err = mlxsw_sp_base_mac_get(mlxsw_sp); 4290 if (err) { 4291 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 4292 return err; 4293 } 4294 4295 err = mlxsw_sp_kvdl_init(mlxsw_sp); 4296 if (err) { 4297 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 4298 return err; 4299 } 4300 4301 err = mlxsw_sp_fids_init(mlxsw_sp); 4302 if (err) { 4303 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 4304 goto err_fids_init; 4305 } 4306 4307 err = mlxsw_sp_traps_init(mlxsw_sp); 4308 if (err) { 4309 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 4310 goto err_traps_init; 4311 } 4312 4313 err = mlxsw_sp_buffers_init(mlxsw_sp); 4314 if (err) { 4315 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 4316 goto err_buffers_init; 4317 } 4318 4319 err = mlxsw_sp_lag_init(mlxsw_sp); 4320 if (err) { 4321 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 4322 goto err_lag_init; 4323 } 4324 4325 /* Initialize SPAN before router and switchdev, so that those components 4326 * can call mlxsw_sp_span_respin(). 4327 */ 4328 err = mlxsw_sp_span_init(mlxsw_sp); 4329 if (err) { 4330 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 4331 goto err_span_init; 4332 } 4333 4334 err = mlxsw_sp_switchdev_init(mlxsw_sp); 4335 if (err) { 4336 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 4337 goto err_switchdev_init; 4338 } 4339 4340 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 4341 if (err) { 4342 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 4343 goto err_counter_pool_init; 4344 } 4345 4346 err = mlxsw_sp_afa_init(mlxsw_sp); 4347 if (err) { 4348 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 4349 goto err_afa_init; 4350 } 4351 4352 err = mlxsw_sp_nve_init(mlxsw_sp); 4353 if (err) { 4354 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 4355 goto err_nve_init; 4356 } 4357 4358 err = mlxsw_sp_acl_init(mlxsw_sp); 4359 if (err) { 4360 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 4361 goto err_acl_init; 4362 } 4363 4364 err = mlxsw_sp_router_init(mlxsw_sp); 4365 if (err) { 4366 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 4367 goto err_router_init; 4368 } 4369 4370 /* Initialize netdevice notifier after router and SPAN is initialized, 4371 * so that the event handler can use router structures and call SPAN 4372 * respin. 4373 */ 4374 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 4375 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb); 4376 if (err) { 4377 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 4378 goto err_netdev_notifier; 4379 } 4380 4381 err = mlxsw_sp_dpipe_init(mlxsw_sp); 4382 if (err) { 4383 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 4384 goto err_dpipe_init; 4385 } 4386 4387 err = mlxsw_sp_ports_create(mlxsw_sp); 4388 if (err) { 4389 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 4390 goto err_ports_create; 4391 } 4392 4393 return 0; 4394 4395 err_ports_create: 4396 mlxsw_sp_dpipe_fini(mlxsw_sp); 4397 err_dpipe_init: 4398 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 4399 err_netdev_notifier: 4400 mlxsw_sp_router_fini(mlxsw_sp); 4401 err_router_init: 4402 mlxsw_sp_acl_fini(mlxsw_sp); 4403 err_acl_init: 4404 mlxsw_sp_nve_fini(mlxsw_sp); 4405 err_nve_init: 4406 mlxsw_sp_afa_fini(mlxsw_sp); 4407 err_afa_init: 4408 mlxsw_sp_counter_pool_fini(mlxsw_sp); 4409 err_counter_pool_init: 4410 mlxsw_sp_switchdev_fini(mlxsw_sp); 4411 err_switchdev_init: 4412 mlxsw_sp_span_fini(mlxsw_sp); 4413 err_span_init: 4414 mlxsw_sp_lag_fini(mlxsw_sp); 4415 err_lag_init: 4416 mlxsw_sp_buffers_fini(mlxsw_sp); 4417 err_buffers_init: 4418 mlxsw_sp_traps_fini(mlxsw_sp); 4419 err_traps_init: 4420 mlxsw_sp_fids_fini(mlxsw_sp); 4421 err_fids_init: 4422 mlxsw_sp_kvdl_fini(mlxsw_sp); 4423 return err; 4424 } 4425 4426 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 4427 const struct mlxsw_bus_info *mlxsw_bus_info) 4428 { 4429 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4430 4431 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev; 4432 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME; 4433 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 4434 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 4435 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 4436 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 4437 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 4438 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 4439 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask; 4440 mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr; 4441 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals; 4442 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops; 4443 4444 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 4445 } 4446 4447 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 4448 const struct mlxsw_bus_info *mlxsw_bus_info) 4449 { 4450 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4451 4452 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 4453 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 4454 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 4455 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 4456 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 4457 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 4458 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 4459 mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr; 4460 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 4461 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 4462 4463 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 4464 } 4465 4466 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 4467 { 4468 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4469 4470 mlxsw_sp_ports_remove(mlxsw_sp); 4471 mlxsw_sp_dpipe_fini(mlxsw_sp); 4472 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 4473 mlxsw_sp_router_fini(mlxsw_sp); 4474 mlxsw_sp_acl_fini(mlxsw_sp); 4475 mlxsw_sp_nve_fini(mlxsw_sp); 4476 mlxsw_sp_afa_fini(mlxsw_sp); 4477 mlxsw_sp_counter_pool_fini(mlxsw_sp); 4478 mlxsw_sp_switchdev_fini(mlxsw_sp); 4479 mlxsw_sp_span_fini(mlxsw_sp); 4480 mlxsw_sp_lag_fini(mlxsw_sp); 4481 mlxsw_sp_buffers_fini(mlxsw_sp); 4482 mlxsw_sp_traps_fini(mlxsw_sp); 4483 mlxsw_sp_fids_fini(mlxsw_sp); 4484 mlxsw_sp_kvdl_fini(mlxsw_sp); 4485 } 4486 4487 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated 4488 * 802.1Q FIDs 4489 */ 4490 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE (MLXSW_SP_FID_8021D_MAX + \ 4491 VLAN_VID_MASK - 1) 4492 4493 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 4494 .used_max_mid = 1, 4495 .max_mid = MLXSW_SP_MID_MAX, 4496 .used_flood_tables = 1, 4497 .used_flood_mode = 1, 4498 .flood_mode = 3, 4499 .max_fid_flood_tables = 3, 4500 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE, 4501 .used_max_ib_mc = 1, 4502 .max_ib_mc = 0, 4503 .used_max_pkey = 1, 4504 .max_pkey = 0, 4505 .used_kvd_sizes = 1, 4506 .kvd_hash_single_parts = 59, 4507 .kvd_hash_double_parts = 41, 4508 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 4509 .swid_config = { 4510 { 4511 .used_type = 1, 4512 .type = MLXSW_PORT_SWID_TYPE_ETH, 4513 } 4514 }, 4515 }; 4516 4517 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 4518 .used_max_mid = 1, 4519 .max_mid = MLXSW_SP_MID_MAX, 4520 .used_flood_tables = 1, 4521 .used_flood_mode = 1, 4522 .flood_mode = 3, 4523 .max_fid_flood_tables = 3, 4524 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE, 4525 .used_max_ib_mc = 1, 4526 .max_ib_mc = 0, 4527 .used_max_pkey = 1, 4528 .max_pkey = 0, 4529 .swid_config = { 4530 { 4531 .used_type = 1, 4532 .type = MLXSW_PORT_SWID_TYPE_ETH, 4533 } 4534 }, 4535 }; 4536 4537 static void 4538 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 4539 struct devlink_resource_size_params *kvd_size_params, 4540 struct devlink_resource_size_params *linear_size_params, 4541 struct devlink_resource_size_params *hash_double_size_params, 4542 struct devlink_resource_size_params *hash_single_size_params) 4543 { 4544 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 4545 KVD_SINGLE_MIN_SIZE); 4546 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 4547 KVD_DOUBLE_MIN_SIZE); 4548 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 4549 u32 linear_size_min = 0; 4550 4551 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 4552 MLXSW_SP_KVD_GRANULARITY, 4553 DEVLINK_RESOURCE_UNIT_ENTRY); 4554 devlink_resource_size_params_init(linear_size_params, linear_size_min, 4555 kvd_size - single_size_min - 4556 double_size_min, 4557 MLXSW_SP_KVD_GRANULARITY, 4558 DEVLINK_RESOURCE_UNIT_ENTRY); 4559 devlink_resource_size_params_init(hash_double_size_params, 4560 double_size_min, 4561 kvd_size - single_size_min - 4562 linear_size_min, 4563 MLXSW_SP_KVD_GRANULARITY, 4564 DEVLINK_RESOURCE_UNIT_ENTRY); 4565 devlink_resource_size_params_init(hash_single_size_params, 4566 single_size_min, 4567 kvd_size - double_size_min - 4568 linear_size_min, 4569 MLXSW_SP_KVD_GRANULARITY, 4570 DEVLINK_RESOURCE_UNIT_ENTRY); 4571 } 4572 4573 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 4574 { 4575 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4576 struct devlink_resource_size_params hash_single_size_params; 4577 struct devlink_resource_size_params hash_double_size_params; 4578 struct devlink_resource_size_params linear_size_params; 4579 struct devlink_resource_size_params kvd_size_params; 4580 u32 kvd_size, single_size, double_size, linear_size; 4581 const struct mlxsw_config_profile *profile; 4582 int err; 4583 4584 profile = &mlxsw_sp1_config_profile; 4585 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 4586 return -EIO; 4587 4588 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 4589 &linear_size_params, 4590 &hash_double_size_params, 4591 &hash_single_size_params); 4592 4593 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 4594 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 4595 kvd_size, MLXSW_SP_RESOURCE_KVD, 4596 DEVLINK_RESOURCE_ID_PARENT_TOP, 4597 &kvd_size_params); 4598 if (err) 4599 return err; 4600 4601 linear_size = profile->kvd_linear_size; 4602 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 4603 linear_size, 4604 MLXSW_SP_RESOURCE_KVD_LINEAR, 4605 MLXSW_SP_RESOURCE_KVD, 4606 &linear_size_params); 4607 if (err) 4608 return err; 4609 4610 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 4611 if (err) 4612 return err; 4613 4614 double_size = kvd_size - linear_size; 4615 double_size *= profile->kvd_hash_double_parts; 4616 double_size /= profile->kvd_hash_double_parts + 4617 profile->kvd_hash_single_parts; 4618 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 4619 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 4620 double_size, 4621 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4622 MLXSW_SP_RESOURCE_KVD, 4623 &hash_double_size_params); 4624 if (err) 4625 return err; 4626 4627 single_size = kvd_size - double_size - linear_size; 4628 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 4629 single_size, 4630 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4631 MLXSW_SP_RESOURCE_KVD, 4632 &hash_single_size_params); 4633 if (err) 4634 return err; 4635 4636 return 0; 4637 } 4638 4639 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 4640 { 4641 return mlxsw_sp1_resources_kvd_register(mlxsw_core); 4642 } 4643 4644 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 4645 { 4646 return 0; 4647 } 4648 4649 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 4650 const struct mlxsw_config_profile *profile, 4651 u64 *p_single_size, u64 *p_double_size, 4652 u64 *p_linear_size) 4653 { 4654 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4655 u32 double_size; 4656 int err; 4657 4658 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4659 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 4660 return -EIO; 4661 4662 /* The hash part is what left of the kvd without the 4663 * linear part. It is split to the single size and 4664 * double size by the parts ratio from the profile. 4665 * Both sizes must be a multiplications of the 4666 * granularity from the profile. In case the user 4667 * provided the sizes they are obtained via devlink. 4668 */ 4669 err = devlink_resource_size_get(devlink, 4670 MLXSW_SP_RESOURCE_KVD_LINEAR, 4671 p_linear_size); 4672 if (err) 4673 *p_linear_size = profile->kvd_linear_size; 4674 4675 err = devlink_resource_size_get(devlink, 4676 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4677 p_double_size); 4678 if (err) { 4679 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4680 *p_linear_size; 4681 double_size *= profile->kvd_hash_double_parts; 4682 double_size /= profile->kvd_hash_double_parts + 4683 profile->kvd_hash_single_parts; 4684 *p_double_size = rounddown(double_size, 4685 MLXSW_SP_KVD_GRANULARITY); 4686 } 4687 4688 err = devlink_resource_size_get(devlink, 4689 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4690 p_single_size); 4691 if (err) 4692 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4693 *p_double_size - *p_linear_size; 4694 4695 /* Check results are legal. */ 4696 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4697 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 4698 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 4699 return -EIO; 4700 4701 return 0; 4702 } 4703 4704 static int 4705 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 4706 union devlink_param_value val, 4707 struct netlink_ext_ack *extack) 4708 { 4709 if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) && 4710 (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) { 4711 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 4712 return -EINVAL; 4713 } 4714 4715 return 0; 4716 } 4717 4718 static const struct devlink_param mlxsw_sp_devlink_params[] = { 4719 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, 4720 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 4721 NULL, NULL, 4722 mlxsw_sp_devlink_param_fw_load_policy_validate), 4723 }; 4724 4725 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core) 4726 { 4727 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4728 union devlink_param_value value; 4729 int err; 4730 4731 err = devlink_params_register(devlink, mlxsw_sp_devlink_params, 4732 ARRAY_SIZE(mlxsw_sp_devlink_params)); 4733 if (err) 4734 return err; 4735 4736 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 4737 devlink_param_driverinit_value_set(devlink, 4738 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 4739 value); 4740 return 0; 4741 } 4742 4743 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core) 4744 { 4745 devlink_params_unregister(priv_to_devlink(mlxsw_core), 4746 mlxsw_sp_devlink_params, 4747 ARRAY_SIZE(mlxsw_sp_devlink_params)); 4748 } 4749 4750 static int 4751 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id, 4752 struct devlink_param_gset_ctx *ctx) 4753 { 4754 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 4755 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4756 4757 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp); 4758 return 0; 4759 } 4760 4761 static int 4762 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id, 4763 struct devlink_param_gset_ctx *ctx) 4764 { 4765 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 4766 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 4767 4768 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32); 4769 } 4770 4771 static const struct devlink_param mlxsw_sp2_devlink_params[] = { 4772 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 4773 "acl_region_rehash_interval", 4774 DEVLINK_PARAM_TYPE_U32, 4775 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 4776 mlxsw_sp_params_acl_region_rehash_intrvl_get, 4777 mlxsw_sp_params_acl_region_rehash_intrvl_set, 4778 NULL), 4779 }; 4780 4781 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core) 4782 { 4783 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4784 union devlink_param_value value; 4785 int err; 4786 4787 err = mlxsw_sp_params_register(mlxsw_core); 4788 if (err) 4789 return err; 4790 4791 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params, 4792 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 4793 if (err) 4794 goto err_devlink_params_register; 4795 4796 value.vu32 = 0; 4797 devlink_param_driverinit_value_set(devlink, 4798 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 4799 value); 4800 return 0; 4801 4802 err_devlink_params_register: 4803 mlxsw_sp_params_unregister(mlxsw_core); 4804 return err; 4805 } 4806 4807 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core) 4808 { 4809 devlink_params_unregister(priv_to_devlink(mlxsw_core), 4810 mlxsw_sp2_devlink_params, 4811 ARRAY_SIZE(mlxsw_sp2_devlink_params)); 4812 mlxsw_sp_params_unregister(mlxsw_core); 4813 } 4814 4815 static struct mlxsw_driver mlxsw_sp1_driver = { 4816 .kind = mlxsw_sp1_driver_name, 4817 .priv_size = sizeof(struct mlxsw_sp), 4818 .init = mlxsw_sp1_init, 4819 .fini = mlxsw_sp_fini, 4820 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4821 .port_split = mlxsw_sp_port_split, 4822 .port_unsplit = mlxsw_sp_port_unsplit, 4823 .sb_pool_get = mlxsw_sp_sb_pool_get, 4824 .sb_pool_set = mlxsw_sp_sb_pool_set, 4825 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4826 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4827 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4828 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4829 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4830 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4831 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4832 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4833 .txhdr_construct = mlxsw_sp_txhdr_construct, 4834 .resources_register = mlxsw_sp1_resources_register, 4835 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 4836 .params_register = mlxsw_sp_params_register, 4837 .params_unregister = mlxsw_sp_params_unregister, 4838 .txhdr_len = MLXSW_TXHDR_LEN, 4839 .profile = &mlxsw_sp1_config_profile, 4840 .res_query_enabled = true, 4841 }; 4842 4843 static struct mlxsw_driver mlxsw_sp2_driver = { 4844 .kind = mlxsw_sp2_driver_name, 4845 .priv_size = sizeof(struct mlxsw_sp), 4846 .init = mlxsw_sp2_init, 4847 .fini = mlxsw_sp_fini, 4848 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4849 .port_split = mlxsw_sp_port_split, 4850 .port_unsplit = mlxsw_sp_port_unsplit, 4851 .sb_pool_get = mlxsw_sp_sb_pool_get, 4852 .sb_pool_set = mlxsw_sp_sb_pool_set, 4853 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4854 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4855 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4856 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4857 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4858 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4859 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4860 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4861 .txhdr_construct = mlxsw_sp_txhdr_construct, 4862 .resources_register = mlxsw_sp2_resources_register, 4863 .params_register = mlxsw_sp2_params_register, 4864 .params_unregister = mlxsw_sp2_params_unregister, 4865 .txhdr_len = MLXSW_TXHDR_LEN, 4866 .profile = &mlxsw_sp2_config_profile, 4867 .res_query_enabled = true, 4868 }; 4869 4870 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 4871 { 4872 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 4873 } 4874 4875 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data) 4876 { 4877 struct mlxsw_sp_port **p_mlxsw_sp_port = data; 4878 int ret = 0; 4879 4880 if (mlxsw_sp_port_dev_check(lower_dev)) { 4881 *p_mlxsw_sp_port = netdev_priv(lower_dev); 4882 ret = 1; 4883 } 4884 4885 return ret; 4886 } 4887 4888 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4889 { 4890 struct mlxsw_sp_port *mlxsw_sp_port; 4891 4892 if (mlxsw_sp_port_dev_check(dev)) 4893 return netdev_priv(dev); 4894 4895 mlxsw_sp_port = NULL; 4896 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port); 4897 4898 return mlxsw_sp_port; 4899 } 4900 4901 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4902 { 4903 struct mlxsw_sp_port *mlxsw_sp_port; 4904 4905 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4906 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4907 } 4908 4909 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4910 { 4911 struct mlxsw_sp_port *mlxsw_sp_port; 4912 4913 if (mlxsw_sp_port_dev_check(dev)) 4914 return netdev_priv(dev); 4915 4916 mlxsw_sp_port = NULL; 4917 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4918 &mlxsw_sp_port); 4919 4920 return mlxsw_sp_port; 4921 } 4922 4923 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4924 { 4925 struct mlxsw_sp_port *mlxsw_sp_port; 4926 4927 rcu_read_lock(); 4928 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4929 if (mlxsw_sp_port) 4930 dev_hold(mlxsw_sp_port->dev); 4931 rcu_read_unlock(); 4932 return mlxsw_sp_port; 4933 } 4934 4935 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4936 { 4937 dev_put(mlxsw_sp_port->dev); 4938 } 4939 4940 static void 4941 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port, 4942 struct net_device *lag_dev) 4943 { 4944 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev); 4945 struct net_device *upper_dev; 4946 struct list_head *iter; 4947 4948 if (netif_is_bridge_port(lag_dev)) 4949 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev); 4950 4951 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4952 if (!netif_is_bridge_port(upper_dev)) 4953 continue; 4954 br_dev = netdev_master_upper_dev_get(upper_dev); 4955 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev); 4956 } 4957 } 4958 4959 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4960 { 4961 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4962 4963 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4964 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4965 } 4966 4967 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4968 { 4969 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4970 4971 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4972 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4973 } 4974 4975 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4976 u16 lag_id, u8 port_index) 4977 { 4978 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4979 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4980 4981 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4982 lag_id, port_index); 4983 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4984 } 4985 4986 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4987 u16 lag_id) 4988 { 4989 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4990 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4991 4992 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4993 lag_id); 4994 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4995 } 4996 4997 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4998 u16 lag_id) 4999 { 5000 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5001 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 5002 5003 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 5004 lag_id); 5005 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 5006 } 5007 5008 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 5009 u16 lag_id) 5010 { 5011 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5012 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 5013 5014 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 5015 lag_id); 5016 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 5017 } 5018 5019 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 5020 struct net_device *lag_dev, 5021 u16 *p_lag_id) 5022 { 5023 struct mlxsw_sp_upper *lag; 5024 int free_lag_id = -1; 5025 u64 max_lag; 5026 int i; 5027 5028 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 5029 for (i = 0; i < max_lag; i++) { 5030 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 5031 if (lag->ref_count) { 5032 if (lag->dev == lag_dev) { 5033 *p_lag_id = i; 5034 return 0; 5035 } 5036 } else if (free_lag_id < 0) { 5037 free_lag_id = i; 5038 } 5039 } 5040 if (free_lag_id < 0) 5041 return -EBUSY; 5042 *p_lag_id = free_lag_id; 5043 return 0; 5044 } 5045 5046 static bool 5047 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 5048 struct net_device *lag_dev, 5049 struct netdev_lag_upper_info *lag_upper_info, 5050 struct netlink_ext_ack *extack) 5051 { 5052 u16 lag_id; 5053 5054 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 5055 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 5056 return false; 5057 } 5058 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 5059 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 5060 return false; 5061 } 5062 return true; 5063 } 5064 5065 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 5066 u16 lag_id, u8 *p_port_index) 5067 { 5068 u64 max_lag_members; 5069 int i; 5070 5071 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 5072 MAX_LAG_MEMBERS); 5073 for (i = 0; i < max_lag_members; i++) { 5074 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 5075 *p_port_index = i; 5076 return 0; 5077 } 5078 } 5079 return -EBUSY; 5080 } 5081 5082 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 5083 struct net_device *lag_dev) 5084 { 5085 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5086 struct mlxsw_sp_upper *lag; 5087 u16 lag_id; 5088 u8 port_index; 5089 int err; 5090 5091 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 5092 if (err) 5093 return err; 5094 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 5095 if (!lag->ref_count) { 5096 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 5097 if (err) 5098 return err; 5099 lag->dev = lag_dev; 5100 } 5101 5102 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 5103 if (err) 5104 return err; 5105 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 5106 if (err) 5107 goto err_col_port_add; 5108 5109 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 5110 mlxsw_sp_port->local_port); 5111 mlxsw_sp_port->lag_id = lag_id; 5112 mlxsw_sp_port->lagged = 1; 5113 lag->ref_count++; 5114 5115 /* Port is no longer usable as a router interface */ 5116 if (mlxsw_sp_port->default_vlan->fid) 5117 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan); 5118 5119 return 0; 5120 5121 err_col_port_add: 5122 if (!lag->ref_count) 5123 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 5124 return err; 5125 } 5126 5127 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 5128 struct net_device *lag_dev) 5129 { 5130 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5131 u16 lag_id = mlxsw_sp_port->lag_id; 5132 struct mlxsw_sp_upper *lag; 5133 5134 if (!mlxsw_sp_port->lagged) 5135 return; 5136 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 5137 WARN_ON(lag->ref_count == 0); 5138 5139 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 5140 5141 /* Any VLANs configured on the port are no longer valid */ 5142 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false); 5143 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan); 5144 /* Make the LAG and its directly linked uppers leave bridges they 5145 * are memeber in 5146 */ 5147 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev); 5148 5149 if (lag->ref_count == 1) 5150 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 5151 5152 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 5153 mlxsw_sp_port->local_port); 5154 mlxsw_sp_port->lagged = 0; 5155 lag->ref_count--; 5156 5157 /* Make sure untagged frames are allowed to ingress */ 5158 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID); 5159 } 5160 5161 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 5162 u16 lag_id) 5163 { 5164 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5165 char sldr_pl[MLXSW_REG_SLDR_LEN]; 5166 5167 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 5168 mlxsw_sp_port->local_port); 5169 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 5170 } 5171 5172 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 5173 u16 lag_id) 5174 { 5175 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5176 char sldr_pl[MLXSW_REG_SLDR_LEN]; 5177 5178 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 5179 mlxsw_sp_port->local_port); 5180 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 5181 } 5182 5183 static int 5184 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port) 5185 { 5186 int err; 5187 5188 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, 5189 mlxsw_sp_port->lag_id); 5190 if (err) 5191 return err; 5192 5193 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 5194 if (err) 5195 goto err_dist_port_add; 5196 5197 return 0; 5198 5199 err_dist_port_add: 5200 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id); 5201 return err; 5202 } 5203 5204 static int 5205 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port) 5206 { 5207 int err; 5208 5209 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 5210 mlxsw_sp_port->lag_id); 5211 if (err) 5212 return err; 5213 5214 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, 5215 mlxsw_sp_port->lag_id); 5216 if (err) 5217 goto err_col_port_disable; 5218 5219 return 0; 5220 5221 err_col_port_disable: 5222 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 5223 return err; 5224 } 5225 5226 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 5227 struct netdev_lag_lower_state_info *info) 5228 { 5229 if (info->tx_enabled) 5230 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port); 5231 else 5232 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 5233 } 5234 5235 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 5236 bool enable) 5237 { 5238 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5239 enum mlxsw_reg_spms_state spms_state; 5240 char *spms_pl; 5241 u16 vid; 5242 int err; 5243 5244 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 5245 MLXSW_REG_SPMS_STATE_DISCARDING; 5246 5247 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 5248 if (!spms_pl) 5249 return -ENOMEM; 5250 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 5251 5252 for (vid = 0; vid < VLAN_N_VID; vid++) 5253 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 5254 5255 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 5256 kfree(spms_pl); 5257 return err; 5258 } 5259 5260 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 5261 { 5262 u16 vid = 1; 5263 int err; 5264 5265 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 5266 if (err) 5267 return err; 5268 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 5269 if (err) 5270 goto err_port_stp_set; 5271 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 5272 true, false); 5273 if (err) 5274 goto err_port_vlan_set; 5275 5276 for (; vid <= VLAN_N_VID - 1; vid++) { 5277 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 5278 vid, false); 5279 if (err) 5280 goto err_vid_learning_set; 5281 } 5282 5283 return 0; 5284 5285 err_vid_learning_set: 5286 for (vid--; vid >= 1; vid--) 5287 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 5288 err_port_vlan_set: 5289 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 5290 err_port_stp_set: 5291 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 5292 return err; 5293 } 5294 5295 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 5296 { 5297 u16 vid; 5298 5299 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 5300 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 5301 vid, true); 5302 5303 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 5304 false, false); 5305 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 5306 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 5307 } 5308 5309 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 5310 { 5311 unsigned int num_vxlans = 0; 5312 struct net_device *dev; 5313 struct list_head *iter; 5314 5315 netdev_for_each_lower_dev(br_dev, dev, iter) { 5316 if (netif_is_vxlan(dev)) 5317 num_vxlans++; 5318 } 5319 5320 return num_vxlans > 1; 5321 } 5322 5323 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev) 5324 { 5325 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0}; 5326 struct net_device *dev; 5327 struct list_head *iter; 5328 5329 netdev_for_each_lower_dev(br_dev, dev, iter) { 5330 u16 pvid; 5331 int err; 5332 5333 if (!netif_is_vxlan(dev)) 5334 continue; 5335 5336 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid); 5337 if (err || !pvid) 5338 continue; 5339 5340 if (test_and_set_bit(pvid, vlans)) 5341 return false; 5342 } 5343 5344 return true; 5345 } 5346 5347 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 5348 struct netlink_ext_ack *extack) 5349 { 5350 if (br_multicast_enabled(br_dev)) { 5351 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 5352 return false; 5353 } 5354 5355 if (!br_vlan_enabled(br_dev) && 5356 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 5357 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 5358 return false; 5359 } 5360 5361 if (br_vlan_enabled(br_dev) && 5362 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) { 5363 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged"); 5364 return false; 5365 } 5366 5367 return true; 5368 } 5369 5370 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 5371 struct net_device *dev, 5372 unsigned long event, void *ptr) 5373 { 5374 struct netdev_notifier_changeupper_info *info; 5375 struct mlxsw_sp_port *mlxsw_sp_port; 5376 struct netlink_ext_ack *extack; 5377 struct net_device *upper_dev; 5378 struct mlxsw_sp *mlxsw_sp; 5379 int err = 0; 5380 5381 mlxsw_sp_port = netdev_priv(dev); 5382 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5383 info = ptr; 5384 extack = netdev_notifier_info_to_extack(&info->info); 5385 5386 switch (event) { 5387 case NETDEV_PRECHANGEUPPER: 5388 upper_dev = info->upper_dev; 5389 if (!is_vlan_dev(upper_dev) && 5390 !netif_is_lag_master(upper_dev) && 5391 !netif_is_bridge_master(upper_dev) && 5392 !netif_is_ovs_master(upper_dev) && 5393 !netif_is_macvlan(upper_dev)) { 5394 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5395 return -EINVAL; 5396 } 5397 if (!info->linking) 5398 break; 5399 if (netif_is_bridge_master(upper_dev) && 5400 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 5401 mlxsw_sp_bridge_has_vxlan(upper_dev) && 5402 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5403 return -EOPNOTSUPP; 5404 if (netdev_has_any_upper_dev(upper_dev) && 5405 (!netif_is_bridge_master(upper_dev) || 5406 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 5407 upper_dev))) { 5408 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 5409 return -EINVAL; 5410 } 5411 if (netif_is_lag_master(upper_dev) && 5412 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 5413 info->upper_info, extack)) 5414 return -EINVAL; 5415 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 5416 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 5417 return -EINVAL; 5418 } 5419 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 5420 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 5421 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 5422 return -EINVAL; 5423 } 5424 if (netif_is_macvlan(upper_dev) && 5425 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) { 5426 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 5427 return -EOPNOTSUPP; 5428 } 5429 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 5430 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 5431 return -EINVAL; 5432 } 5433 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 5434 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 5435 return -EINVAL; 5436 } 5437 break; 5438 case NETDEV_CHANGEUPPER: 5439 upper_dev = info->upper_dev; 5440 if (netif_is_bridge_master(upper_dev)) { 5441 if (info->linking) 5442 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 5443 lower_dev, 5444 upper_dev, 5445 extack); 5446 else 5447 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 5448 lower_dev, 5449 upper_dev); 5450 } else if (netif_is_lag_master(upper_dev)) { 5451 if (info->linking) { 5452 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 5453 upper_dev); 5454 } else { 5455 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 5456 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 5457 upper_dev); 5458 } 5459 } else if (netif_is_ovs_master(upper_dev)) { 5460 if (info->linking) 5461 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 5462 else 5463 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 5464 } else if (netif_is_macvlan(upper_dev)) { 5465 if (!info->linking) 5466 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5467 } else if (is_vlan_dev(upper_dev)) { 5468 struct net_device *br_dev; 5469 5470 if (!netif_is_bridge_port(upper_dev)) 5471 break; 5472 if (info->linking) 5473 break; 5474 br_dev = netdev_master_upper_dev_get(upper_dev); 5475 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, 5476 br_dev); 5477 } 5478 break; 5479 } 5480 5481 return err; 5482 } 5483 5484 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 5485 unsigned long event, void *ptr) 5486 { 5487 struct netdev_notifier_changelowerstate_info *info; 5488 struct mlxsw_sp_port *mlxsw_sp_port; 5489 int err; 5490 5491 mlxsw_sp_port = netdev_priv(dev); 5492 info = ptr; 5493 5494 switch (event) { 5495 case NETDEV_CHANGELOWERSTATE: 5496 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 5497 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 5498 info->lower_state_info); 5499 if (err) 5500 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 5501 } 5502 break; 5503 } 5504 5505 return 0; 5506 } 5507 5508 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 5509 struct net_device *port_dev, 5510 unsigned long event, void *ptr) 5511 { 5512 switch (event) { 5513 case NETDEV_PRECHANGEUPPER: 5514 case NETDEV_CHANGEUPPER: 5515 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 5516 event, ptr); 5517 case NETDEV_CHANGELOWERSTATE: 5518 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 5519 ptr); 5520 } 5521 5522 return 0; 5523 } 5524 5525 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 5526 unsigned long event, void *ptr) 5527 { 5528 struct net_device *dev; 5529 struct list_head *iter; 5530 int ret; 5531 5532 netdev_for_each_lower_dev(lag_dev, dev, iter) { 5533 if (mlxsw_sp_port_dev_check(dev)) { 5534 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 5535 ptr); 5536 if (ret) 5537 return ret; 5538 } 5539 } 5540 5541 return 0; 5542 } 5543 5544 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 5545 struct net_device *dev, 5546 unsigned long event, void *ptr, 5547 u16 vid) 5548 { 5549 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 5550 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 5551 struct netdev_notifier_changeupper_info *info = ptr; 5552 struct netlink_ext_ack *extack; 5553 struct net_device *upper_dev; 5554 int err = 0; 5555 5556 extack = netdev_notifier_info_to_extack(&info->info); 5557 5558 switch (event) { 5559 case NETDEV_PRECHANGEUPPER: 5560 upper_dev = info->upper_dev; 5561 if (!netif_is_bridge_master(upper_dev) && 5562 !netif_is_macvlan(upper_dev)) { 5563 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5564 return -EINVAL; 5565 } 5566 if (!info->linking) 5567 break; 5568 if (netif_is_bridge_master(upper_dev) && 5569 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 5570 mlxsw_sp_bridge_has_vxlan(upper_dev) && 5571 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5572 return -EOPNOTSUPP; 5573 if (netdev_has_any_upper_dev(upper_dev) && 5574 (!netif_is_bridge_master(upper_dev) || 5575 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 5576 upper_dev))) { 5577 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 5578 return -EINVAL; 5579 } 5580 if (netif_is_macvlan(upper_dev) && 5581 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) { 5582 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 5583 return -EOPNOTSUPP; 5584 } 5585 break; 5586 case NETDEV_CHANGEUPPER: 5587 upper_dev = info->upper_dev; 5588 if (netif_is_bridge_master(upper_dev)) { 5589 if (info->linking) 5590 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 5591 vlan_dev, 5592 upper_dev, 5593 extack); 5594 else 5595 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 5596 vlan_dev, 5597 upper_dev); 5598 } else if (netif_is_macvlan(upper_dev)) { 5599 if (!info->linking) 5600 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5601 } else { 5602 err = -EINVAL; 5603 WARN_ON(1); 5604 } 5605 break; 5606 } 5607 5608 return err; 5609 } 5610 5611 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 5612 struct net_device *lag_dev, 5613 unsigned long event, 5614 void *ptr, u16 vid) 5615 { 5616 struct net_device *dev; 5617 struct list_head *iter; 5618 int ret; 5619 5620 netdev_for_each_lower_dev(lag_dev, dev, iter) { 5621 if (mlxsw_sp_port_dev_check(dev)) { 5622 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 5623 event, ptr, 5624 vid); 5625 if (ret) 5626 return ret; 5627 } 5628 } 5629 5630 return 0; 5631 } 5632 5633 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev, 5634 struct net_device *br_dev, 5635 unsigned long event, void *ptr, 5636 u16 vid) 5637 { 5638 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev); 5639 struct netdev_notifier_changeupper_info *info = ptr; 5640 struct netlink_ext_ack *extack; 5641 struct net_device *upper_dev; 5642 5643 if (!mlxsw_sp) 5644 return 0; 5645 5646 extack = netdev_notifier_info_to_extack(&info->info); 5647 5648 switch (event) { 5649 case NETDEV_PRECHANGEUPPER: 5650 upper_dev = info->upper_dev; 5651 if (!netif_is_macvlan(upper_dev)) { 5652 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5653 return -EOPNOTSUPP; 5654 } 5655 if (!info->linking) 5656 break; 5657 if (netif_is_macvlan(upper_dev) && 5658 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) { 5659 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 5660 return -EOPNOTSUPP; 5661 } 5662 break; 5663 case NETDEV_CHANGEUPPER: 5664 upper_dev = info->upper_dev; 5665 if (info->linking) 5666 break; 5667 if (netif_is_macvlan(upper_dev)) 5668 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5669 break; 5670 } 5671 5672 return 0; 5673 } 5674 5675 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 5676 unsigned long event, void *ptr) 5677 { 5678 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 5679 u16 vid = vlan_dev_vlan_id(vlan_dev); 5680 5681 if (mlxsw_sp_port_dev_check(real_dev)) 5682 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 5683 event, ptr, vid); 5684 else if (netif_is_lag_master(real_dev)) 5685 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 5686 real_dev, event, 5687 ptr, vid); 5688 else if (netif_is_bridge_master(real_dev)) 5689 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev, 5690 event, ptr, vid); 5691 5692 return 0; 5693 } 5694 5695 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 5696 unsigned long event, void *ptr) 5697 { 5698 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 5699 struct netdev_notifier_changeupper_info *info = ptr; 5700 struct netlink_ext_ack *extack; 5701 struct net_device *upper_dev; 5702 5703 if (!mlxsw_sp) 5704 return 0; 5705 5706 extack = netdev_notifier_info_to_extack(&info->info); 5707 5708 switch (event) { 5709 case NETDEV_PRECHANGEUPPER: 5710 upper_dev = info->upper_dev; 5711 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) { 5712 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5713 return -EOPNOTSUPP; 5714 } 5715 if (!info->linking) 5716 break; 5717 if (netif_is_macvlan(upper_dev) && 5718 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) { 5719 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 5720 return -EOPNOTSUPP; 5721 } 5722 break; 5723 case NETDEV_CHANGEUPPER: 5724 upper_dev = info->upper_dev; 5725 if (info->linking) 5726 break; 5727 if (is_vlan_dev(upper_dev)) 5728 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 5729 if (netif_is_macvlan(upper_dev)) 5730 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5731 break; 5732 } 5733 5734 return 0; 5735 } 5736 5737 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 5738 unsigned long event, void *ptr) 5739 { 5740 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 5741 struct netdev_notifier_changeupper_info *info = ptr; 5742 struct netlink_ext_ack *extack; 5743 5744 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 5745 return 0; 5746 5747 extack = netdev_notifier_info_to_extack(&info->info); 5748 5749 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */ 5750 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5751 5752 return -EOPNOTSUPP; 5753 } 5754 5755 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 5756 { 5757 struct netdev_notifier_changeupper_info *info = ptr; 5758 5759 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 5760 return false; 5761 return netif_is_l3_master(info->upper_dev); 5762 } 5763 5764 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 5765 struct net_device *dev, 5766 unsigned long event, void *ptr) 5767 { 5768 struct netdev_notifier_changeupper_info *cu_info; 5769 struct netdev_notifier_info *info = ptr; 5770 struct netlink_ext_ack *extack; 5771 struct net_device *upper_dev; 5772 5773 extack = netdev_notifier_info_to_extack(info); 5774 5775 switch (event) { 5776 case NETDEV_CHANGEUPPER: 5777 cu_info = container_of(info, 5778 struct netdev_notifier_changeupper_info, 5779 info); 5780 upper_dev = cu_info->upper_dev; 5781 if (!netif_is_bridge_master(upper_dev)) 5782 return 0; 5783 if (!mlxsw_sp_lower_get(upper_dev)) 5784 return 0; 5785 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5786 return -EOPNOTSUPP; 5787 if (cu_info->linking) { 5788 if (!netif_running(dev)) 5789 return 0; 5790 /* When the bridge is VLAN-aware, the VNI of the VxLAN 5791 * device needs to be mapped to a VLAN, but at this 5792 * point no VLANs are configured on the VxLAN device 5793 */ 5794 if (br_vlan_enabled(upper_dev)) 5795 return 0; 5796 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 5797 dev, 0, extack); 5798 } else { 5799 /* VLANs were already flushed, which triggered the 5800 * necessary cleanup 5801 */ 5802 if (br_vlan_enabled(upper_dev)) 5803 return 0; 5804 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5805 } 5806 break; 5807 case NETDEV_PRE_UP: 5808 upper_dev = netdev_master_upper_dev_get(dev); 5809 if (!upper_dev) 5810 return 0; 5811 if (!netif_is_bridge_master(upper_dev)) 5812 return 0; 5813 if (!mlxsw_sp_lower_get(upper_dev)) 5814 return 0; 5815 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0, 5816 extack); 5817 case NETDEV_DOWN: 5818 upper_dev = netdev_master_upper_dev_get(dev); 5819 if (!upper_dev) 5820 return 0; 5821 if (!netif_is_bridge_master(upper_dev)) 5822 return 0; 5823 if (!mlxsw_sp_lower_get(upper_dev)) 5824 return 0; 5825 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5826 break; 5827 } 5828 5829 return 0; 5830 } 5831 5832 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 5833 unsigned long event, void *ptr) 5834 { 5835 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 5836 struct mlxsw_sp_span_entry *span_entry; 5837 struct mlxsw_sp *mlxsw_sp; 5838 int err = 0; 5839 5840 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 5841 if (event == NETDEV_UNREGISTER) { 5842 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 5843 if (span_entry) 5844 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 5845 } 5846 mlxsw_sp_span_respin(mlxsw_sp); 5847 5848 if (netif_is_vxlan(dev)) 5849 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 5850 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 5851 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 5852 event, ptr); 5853 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 5854 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 5855 event, ptr); 5856 else if (event == NETDEV_PRE_CHANGEADDR || 5857 event == NETDEV_CHANGEADDR || 5858 event == NETDEV_CHANGEMTU) 5859 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr); 5860 else if (mlxsw_sp_is_vrf_event(event, ptr)) 5861 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 5862 else if (mlxsw_sp_port_dev_check(dev)) 5863 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 5864 else if (netif_is_lag_master(dev)) 5865 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 5866 else if (is_vlan_dev(dev)) 5867 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 5868 else if (netif_is_bridge_master(dev)) 5869 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 5870 else if (netif_is_macvlan(dev)) 5871 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 5872 5873 return notifier_from_errno(err); 5874 } 5875 5876 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 5877 .notifier_call = mlxsw_sp_inetaddr_valid_event, 5878 }; 5879 5880 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 5881 .notifier_call = mlxsw_sp_inet6addr_valid_event, 5882 }; 5883 5884 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 5885 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 5886 {0, }, 5887 }; 5888 5889 static struct pci_driver mlxsw_sp1_pci_driver = { 5890 .name = mlxsw_sp1_driver_name, 5891 .id_table = mlxsw_sp1_pci_id_table, 5892 }; 5893 5894 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 5895 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 5896 {0, }, 5897 }; 5898 5899 static struct pci_driver mlxsw_sp2_pci_driver = { 5900 .name = mlxsw_sp2_driver_name, 5901 .id_table = mlxsw_sp2_pci_id_table, 5902 }; 5903 5904 static int __init mlxsw_sp_module_init(void) 5905 { 5906 int err; 5907 5908 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5909 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5910 5911 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5912 if (err) 5913 goto err_sp1_core_driver_register; 5914 5915 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5916 if (err) 5917 goto err_sp2_core_driver_register; 5918 5919 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5920 if (err) 5921 goto err_sp1_pci_driver_register; 5922 5923 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5924 if (err) 5925 goto err_sp2_pci_driver_register; 5926 5927 return 0; 5928 5929 err_sp2_pci_driver_register: 5930 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5931 err_sp1_pci_driver_register: 5932 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5933 err_sp2_core_driver_register: 5934 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5935 err_sp1_core_driver_register: 5936 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5937 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5938 return err; 5939 } 5940 5941 static void __exit mlxsw_sp_module_exit(void) 5942 { 5943 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5944 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5945 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5946 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5947 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5948 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5949 } 5950 5951 module_init(mlxsw_sp_module_init); 5952 module_exit(mlxsw_sp_module_exit); 5953 5954 MODULE_LICENSE("Dual BSD/GPL"); 5955 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5956 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5957 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5958 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5959 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5960