1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/resources.h 3 * Copyright (c) 2016-2017 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2016-2017 Jiri Pirko <jiri@mellanox.com> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the names of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") version 2 as published by the Free 20 * Software Foundation. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _MLXSW_RESOURCES_H 36 #define _MLXSW_RESOURCES_H 37 38 #include <linux/kernel.h> 39 #include <linux/types.h> 40 41 enum mlxsw_res_id { 42 MLXSW_RES_ID_KVD_SIZE, 43 MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE, 44 MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE, 45 MLXSW_RES_ID_MAX_TRAP_GROUPS, 46 MLXSW_RES_ID_CQE_V0, 47 MLXSW_RES_ID_CQE_V1, 48 MLXSW_RES_ID_CQE_V2, 49 MLXSW_RES_ID_COUNTER_POOL_SIZE, 50 MLXSW_RES_ID_MAX_SPAN, 51 MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES, 52 MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC, 53 MLXSW_RES_ID_MAX_SYSTEM_PORT, 54 MLXSW_RES_ID_MAX_LAG, 55 MLXSW_RES_ID_MAX_LAG_MEMBERS, 56 MLXSW_RES_ID_MAX_BUFFER_SIZE, 57 MLXSW_RES_ID_CELL_SIZE, 58 MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS, 59 MLXSW_RES_ID_ACL_MAX_TCAM_RULES, 60 MLXSW_RES_ID_ACL_MAX_REGIONS, 61 MLXSW_RES_ID_ACL_MAX_GROUPS, 62 MLXSW_RES_ID_ACL_MAX_GROUP_SIZE, 63 MLXSW_RES_ID_ACL_FLEX_KEYS, 64 MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE, 65 MLXSW_RES_ID_ACL_ACTIONS_PER_SET, 66 MLXSW_RES_ID_MAX_CPU_POLICERS, 67 MLXSW_RES_ID_MAX_VRS, 68 MLXSW_RES_ID_MAX_RIFS, 69 MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES, 70 MLXSW_RES_ID_MAX_LPM_TREES, 71 72 /* Internal resources. 73 * Determined by the SW, not queried from the HW. 74 */ 75 MLXSW_RES_ID_KVD_SINGLE_SIZE, 76 MLXSW_RES_ID_KVD_DOUBLE_SIZE, 77 MLXSW_RES_ID_KVD_LINEAR_SIZE, 78 79 __MLXSW_RES_ID_MAX, 80 }; 81 82 static u16 mlxsw_res_ids[] = { 83 [MLXSW_RES_ID_KVD_SIZE] = 0x1001, 84 [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002, 85 [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003, 86 [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201, 87 [MLXSW_RES_ID_CQE_V0] = 0x2210, 88 [MLXSW_RES_ID_CQE_V1] = 0x2211, 89 [MLXSW_RES_ID_CQE_V2] = 0x2212, 90 [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410, 91 [MLXSW_RES_ID_MAX_SPAN] = 0x2420, 92 [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443, 93 [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449, 94 [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502, 95 [MLXSW_RES_ID_MAX_LAG] = 0x2520, 96 [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521, 97 [MLXSW_RES_ID_MAX_BUFFER_SIZE] = 0x2802, /* Bytes */ 98 [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */ 99 [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901, 100 [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902, 101 [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903, 102 [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904, 103 [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905, 104 [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910, 105 [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911, 106 [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912, 107 [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13, 108 [MLXSW_RES_ID_MAX_VRS] = 0x2C01, 109 [MLXSW_RES_ID_MAX_RIFS] = 0x2C02, 110 [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10, 111 [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30, 112 }; 113 114 struct mlxsw_res { 115 bool valid[__MLXSW_RES_ID_MAX]; 116 u64 values[__MLXSW_RES_ID_MAX]; 117 }; 118 119 static inline bool mlxsw_res_valid(struct mlxsw_res *res, 120 enum mlxsw_res_id res_id) 121 { 122 return res->valid[res_id]; 123 } 124 125 #define MLXSW_RES_VALID(res, short_res_id) \ 126 mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id) 127 128 static inline u64 mlxsw_res_get(struct mlxsw_res *res, 129 enum mlxsw_res_id res_id) 130 { 131 if (WARN_ON(!res->valid[res_id])) 132 return 0; 133 return res->values[res_id]; 134 } 135 136 #define MLXSW_RES_GET(res, short_res_id) \ 137 mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id) 138 139 static inline void mlxsw_res_set(struct mlxsw_res *res, 140 enum mlxsw_res_id res_id, u64 value) 141 { 142 res->valid[res_id] = true; 143 res->values[res_id] = value; 144 } 145 146 #define MLXSW_RES_SET(res, short_res_id, value) \ 147 mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value) 148 149 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value) 150 { 151 int i; 152 153 for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) { 154 if (mlxsw_res_ids[i] == id) { 155 mlxsw_res_set(res, i, value); 156 return; 157 } 158 } 159 } 160 161 #endif 162