1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3 
4 #ifndef _MLXSW_RESOURCES_H
5 #define _MLXSW_RESOURCES_H
6 
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 
10 enum mlxsw_res_id {
11 	MLXSW_RES_ID_KVD_SIZE,
12 	MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
13 	MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
14 	MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
15 	MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
16 	MLXSW_RES_ID_MAX_TRAP_GROUPS,
17 	MLXSW_RES_ID_CQE_V0,
18 	MLXSW_RES_ID_CQE_V1,
19 	MLXSW_RES_ID_CQE_V2,
20 	MLXSW_RES_ID_COUNTER_POOL_SIZE,
21 	MLXSW_RES_ID_MAX_SPAN,
22 	MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
23 	MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
24 	MLXSW_RES_ID_MAX_SYSTEM_PORT,
25 	MLXSW_RES_ID_MAX_LAG,
26 	MLXSW_RES_ID_MAX_LAG_MEMBERS,
27 	MLXSW_RES_ID_MAX_BUFFER_SIZE,
28 	MLXSW_RES_ID_CELL_SIZE,
29 	MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
30 	MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
31 	MLXSW_RES_ID_ACL_MAX_REGIONS,
32 	MLXSW_RES_ID_ACL_MAX_GROUPS,
33 	MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
34 	MLXSW_RES_ID_ACL_FLEX_KEYS,
35 	MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
36 	MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
37 	MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
38 	MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
39 	MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
40 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
41 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
42 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
43 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
44 	MLXSW_RES_ID_MAX_CPU_POLICERS,
45 	MLXSW_RES_ID_MAX_VRS,
46 	MLXSW_RES_ID_MAX_RIFS,
47 	MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
48 	MLXSW_RES_ID_MAX_LPM_TREES,
49 	MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4,
50 	MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6,
51 
52 	/* Internal resources.
53 	 * Determined by the SW, not queried from the HW.
54 	 */
55 	MLXSW_RES_ID_KVD_SINGLE_SIZE,
56 	MLXSW_RES_ID_KVD_DOUBLE_SIZE,
57 	MLXSW_RES_ID_KVD_LINEAR_SIZE,
58 
59 	__MLXSW_RES_ID_MAX,
60 };
61 
62 static u16 mlxsw_res_ids[] = {
63 	[MLXSW_RES_ID_KVD_SIZE] = 0x1001,
64 	[MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
65 	[MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
66 	[MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
67 	[MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
68 	[MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
69 	[MLXSW_RES_ID_CQE_V0] = 0x2210,
70 	[MLXSW_RES_ID_CQE_V1] = 0x2211,
71 	[MLXSW_RES_ID_CQE_V2] = 0x2212,
72 	[MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
73 	[MLXSW_RES_ID_MAX_SPAN] = 0x2420,
74 	[MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
75 	[MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
76 	[MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
77 	[MLXSW_RES_ID_MAX_LAG] = 0x2520,
78 	[MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
79 	[MLXSW_RES_ID_MAX_BUFFER_SIZE] = 0x2802,	/* Bytes */
80 	[MLXSW_RES_ID_CELL_SIZE] = 0x2803,	/* Bytes */
81 	[MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
82 	[MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
83 	[MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
84 	[MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
85 	[MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
86 	[MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
87 	[MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
88 	[MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
89 	[MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
90 	[MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
91 	[MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
92 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
93 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
94 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
95 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
96 	[MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
97 	[MLXSW_RES_ID_MAX_VRS] = 0x2C01,
98 	[MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
99 	[MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
100 	[MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
101 	[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02,
102 	[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03,
103 };
104 
105 struct mlxsw_res {
106 	bool valid[__MLXSW_RES_ID_MAX];
107 	u64 values[__MLXSW_RES_ID_MAX];
108 };
109 
110 static inline bool mlxsw_res_valid(struct mlxsw_res *res,
111 				   enum mlxsw_res_id res_id)
112 {
113 	return res->valid[res_id];
114 }
115 
116 #define MLXSW_RES_VALID(res, short_res_id)			\
117 	mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
118 
119 static inline u64 mlxsw_res_get(struct mlxsw_res *res,
120 				enum mlxsw_res_id res_id)
121 {
122 	if (WARN_ON(!res->valid[res_id]))
123 		return 0;
124 	return res->values[res_id];
125 }
126 
127 #define MLXSW_RES_GET(res, short_res_id)			\
128 	mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
129 
130 static inline void mlxsw_res_set(struct mlxsw_res *res,
131 				 enum mlxsw_res_id res_id, u64 value)
132 {
133 	res->valid[res_id] = true;
134 	res->values[res_id] = value;
135 }
136 
137 #define MLXSW_RES_SET(res, short_res_id, value)			\
138 	mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
139 
140 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
141 {
142 	int i;
143 
144 	for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
145 		if (mlxsw_res_ids[i] == id) {
146 			mlxsw_res_set(res, i, value);
147 			return;
148 		}
149 	}
150 }
151 
152 #endif
153