1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 enum mlxsw_reg_tunnel_port { 585 MLXSW_REG_TUNNEL_PORT_NVE, 586 MLXSW_REG_TUNNEL_PORT_VPLS, 587 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 588 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 589 }; 590 591 /* SFN - Switch FDB Notification Register 592 * ------------------------------------------- 593 * The switch provides notifications on newly learned FDB entries and 594 * aged out entries. The notifications can be polled by software. 595 */ 596 #define MLXSW_REG_SFN_ID 0x200B 597 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 598 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 599 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 600 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 601 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 602 603 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 604 605 /* reg_sfn_swid 606 * Switch partition ID. 607 * Access: Index 608 */ 609 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 610 611 /* reg_sfn_end 612 * Forces the current session to end. 613 * Access: OP 614 */ 615 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 616 617 /* reg_sfn_num_rec 618 * Request: Number of learned notifications and aged-out notification 619 * records requested. 620 * Response: Number of notification records returned (must be smaller 621 * than or equal to the value requested) 622 * Ranges 0..64 623 * Access: OP 624 */ 625 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 626 627 static inline void mlxsw_reg_sfn_pack(char *payload) 628 { 629 MLXSW_REG_ZERO(sfn, payload); 630 mlxsw_reg_sfn_swid_set(payload, 0); 631 mlxsw_reg_sfn_end_set(payload, 0); 632 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 633 } 634 635 /* reg_sfn_rec_swid 636 * Switch partition ID. 637 * Access: RO 638 */ 639 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 640 MLXSW_REG_SFN_REC_LEN, 0x00, false); 641 642 enum mlxsw_reg_sfn_rec_type { 643 /* MAC addresses learned on a regular port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 645 /* MAC addresses learned on a LAG port. */ 646 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 647 /* Aged-out MAC address on a regular port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 649 /* Aged-out MAC address on a LAG port. */ 650 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 651 /* Learned unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 653 /* Aged-out unicast tunnel record. */ 654 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 655 }; 656 657 /* reg_sfn_rec_type 658 * Notification record type. 659 * Access: RO 660 */ 661 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 662 MLXSW_REG_SFN_REC_LEN, 0x00, false); 663 664 /* reg_sfn_rec_mac 665 * MAC address. 666 * Access: RO 667 */ 668 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 669 MLXSW_REG_SFN_REC_LEN, 0x02); 670 671 /* reg_sfn_mac_sub_port 672 * VEPA channel on the local port. 673 * 0 if multichannel VEPA is not enabled. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_fid 680 * Filtering identifier. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x08, false); 685 686 /* reg_sfn_mac_system_port 687 * Unique port identifier for the final destination of the packet. 688 * Access: RO 689 */ 690 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 691 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 692 693 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 694 char *mac, u16 *p_vid, 695 u8 *p_local_port) 696 { 697 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 698 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 699 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 700 } 701 702 /* reg_sfn_mac_lag_lag_id 703 * LAG ID (pointer into the LAG descriptor table). 704 * Access: RO 705 */ 706 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 707 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 708 709 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 710 char *mac, u16 *p_vid, 711 u16 *p_lag_id) 712 { 713 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 714 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 715 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 716 } 717 718 /* reg_sfn_uc_tunnel_uip_msb 719 * When protocol is IPv4, the most significant byte of the underlay IPv4 720 * address of the remote VTEP. 721 * When protocol is IPv6, reserved. 722 * Access: RO 723 */ 724 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 725 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 726 727 enum mlxsw_reg_sfn_uc_tunnel_protocol { 728 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 729 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 730 }; 731 732 /* reg_sfn_uc_tunnel_protocol 733 * IP protocol. 734 * Access: RO 735 */ 736 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 737 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 738 739 /* reg_sfn_uc_tunnel_uip_lsb 740 * When protocol is IPv4, the least significant bytes of the underlay 741 * IPv4 address of the remote VTEP. 742 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 743 * Access: RO 744 */ 745 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 746 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_tport 825 * Port is tunnel port. 826 * Reserved when SwitchX/-2 or Spectrum-1. 827 * Access: Index 828 */ 829 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 830 831 /* reg_spvid_local_port 832 * When tport = 0: Local port number. Not supported for CPU port. 833 * When tport = 1: Tunnel port. 834 * Access: Index 835 */ 836 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 837 838 /* reg_spvid_sub_port 839 * Virtual port within the physical port. 840 * Should be set to 0 when virtual ports are not enabled on the port. 841 * Access: Index 842 */ 843 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 844 845 /* reg_spvid_et_vlan 846 * EtherType used for when VLAN is pushed at ingress (for untagged 847 * packets or for QinQ push mode). 848 * 0: ether_type0 - (default) 849 * 1: ether_type1 850 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 851 * Ethertype IDs are configured by SVER. 852 * Access: RW 853 */ 854 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 855 856 /* reg_spvid_pvid 857 * Port default VID 858 * Access: RW 859 */ 860 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 861 862 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid, 863 u8 et_vlan) 864 { 865 MLXSW_REG_ZERO(spvid, payload); 866 mlxsw_reg_spvid_local_port_set(payload, local_port); 867 mlxsw_reg_spvid_pvid_set(payload, pvid); 868 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 869 } 870 871 /* SPVM - Switch Port VLAN Membership 872 * ---------------------------------- 873 * The Switch Port VLAN Membership register configures the VLAN membership 874 * of a port in a VLAN denoted by VID. VLAN membership is managed per 875 * virtual port. The register can be used to add and remove VID(s) from a port. 876 */ 877 #define MLXSW_REG_SPVM_ID 0x200F 878 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 879 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 880 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 881 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 882 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 883 884 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 885 886 /* reg_spvm_pt 887 * Priority tagged. If this bit is set, packets forwarded to the port with 888 * untagged VLAN membership (u bit is set) will be tagged with priority tag 889 * (VID=0) 890 * Access: RW 891 */ 892 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 893 894 /* reg_spvm_pte 895 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 896 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 897 * Access: WO 898 */ 899 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 900 901 /* reg_spvm_local_port 902 * Local port number. 903 * Access: Index 904 */ 905 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 906 907 /* reg_spvm_sub_port 908 * Virtual port within the physical port. 909 * Should be set to 0 when virtual ports are not enabled on the port. 910 * Access: Index 911 */ 912 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 913 914 /* reg_spvm_num_rec 915 * Number of records to update. Each record contains: i, e, u, vid. 916 * Access: OP 917 */ 918 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 919 920 /* reg_spvm_rec_i 921 * Ingress membership in VLAN ID. 922 * Access: Index 923 */ 924 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 925 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 926 MLXSW_REG_SPVM_REC_LEN, 0, false); 927 928 /* reg_spvm_rec_e 929 * Egress membership in VLAN ID. 930 * Access: Index 931 */ 932 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 933 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 934 MLXSW_REG_SPVM_REC_LEN, 0, false); 935 936 /* reg_spvm_rec_u 937 * Untagged - port is an untagged member - egress transmission uses untagged 938 * frames on VID<n> 939 * Access: Index 940 */ 941 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 942 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 943 MLXSW_REG_SPVM_REC_LEN, 0, false); 944 945 /* reg_spvm_rec_vid 946 * Egress membership in VLAN ID. 947 * Access: Index 948 */ 949 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 950 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 951 MLXSW_REG_SPVM_REC_LEN, 0, false); 952 953 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 954 u16 vid_begin, u16 vid_end, 955 bool is_member, bool untagged) 956 { 957 int size = vid_end - vid_begin + 1; 958 int i; 959 960 MLXSW_REG_ZERO(spvm, payload); 961 mlxsw_reg_spvm_local_port_set(payload, local_port); 962 mlxsw_reg_spvm_num_rec_set(payload, size); 963 964 for (i = 0; i < size; i++) { 965 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 966 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 967 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 968 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 969 } 970 } 971 972 /* SPAFT - Switch Port Acceptable Frame Types 973 * ------------------------------------------ 974 * The Switch Port Acceptable Frame Types register configures the frame 975 * admittance of the port. 976 */ 977 #define MLXSW_REG_SPAFT_ID 0x2010 978 #define MLXSW_REG_SPAFT_LEN 0x08 979 980 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 981 982 /* reg_spaft_local_port 983 * Local port number. 984 * Access: Index 985 * 986 * Note: CPU port is not supported (all tag types are allowed). 987 */ 988 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 989 990 /* reg_spaft_sub_port 991 * Virtual port within the physical port. 992 * Should be set to 0 when virtual ports are not enabled on the port. 993 * Access: RW 994 */ 995 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 996 997 /* reg_spaft_allow_untagged 998 * When set, untagged frames on the ingress are allowed (default). 999 * Access: RW 1000 */ 1001 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1002 1003 /* reg_spaft_allow_prio_tagged 1004 * When set, priority tagged frames on the ingress are allowed (default). 1005 * Access: RW 1006 */ 1007 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1008 1009 /* reg_spaft_allow_tagged 1010 * When set, tagged frames on the ingress are allowed (default). 1011 * Access: RW 1012 */ 1013 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1014 1015 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 1016 bool allow_untagged) 1017 { 1018 MLXSW_REG_ZERO(spaft, payload); 1019 mlxsw_reg_spaft_local_port_set(payload, local_port); 1020 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1021 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1022 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1023 } 1024 1025 /* SFGC - Switch Flooding Group Configuration 1026 * ------------------------------------------ 1027 * The following register controls the association of flooding tables and MIDs 1028 * to packet types used for flooding. 1029 */ 1030 #define MLXSW_REG_SFGC_ID 0x2011 1031 #define MLXSW_REG_SFGC_LEN 0x10 1032 1033 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1034 1035 enum mlxsw_reg_sfgc_type { 1036 MLXSW_REG_SFGC_TYPE_BROADCAST, 1037 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1038 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1039 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1040 MLXSW_REG_SFGC_TYPE_RESERVED, 1041 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1042 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1043 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1044 MLXSW_REG_SFGC_TYPE_MAX, 1045 }; 1046 1047 /* reg_sfgc_type 1048 * The traffic type to reach the flooding table. 1049 * Access: Index 1050 */ 1051 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1052 1053 enum mlxsw_reg_sfgc_bridge_type { 1054 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1055 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1056 }; 1057 1058 /* reg_sfgc_bridge_type 1059 * Access: Index 1060 * 1061 * Note: SwitchX-2 only supports 802.1Q mode. 1062 */ 1063 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1064 1065 enum mlxsw_flood_table_type { 1066 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1067 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1068 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1069 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1070 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1071 }; 1072 1073 /* reg_sfgc_table_type 1074 * See mlxsw_flood_table_type 1075 * Access: RW 1076 * 1077 * Note: FID offset and FID types are not supported in SwitchX-2. 1078 */ 1079 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1080 1081 /* reg_sfgc_flood_table 1082 * Flooding table index to associate with the specific type on the specific 1083 * switch partition. 1084 * Access: RW 1085 */ 1086 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1087 1088 /* reg_sfgc_mid 1089 * The multicast ID for the swid. Not supported for Spectrum 1090 * Access: RW 1091 */ 1092 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1093 1094 /* reg_sfgc_counter_set_type 1095 * Counter Set Type for flow counters. 1096 * Access: RW 1097 */ 1098 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1099 1100 /* reg_sfgc_counter_index 1101 * Counter Index for flow counters. 1102 * Access: RW 1103 */ 1104 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1105 1106 static inline void 1107 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1108 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1109 enum mlxsw_flood_table_type table_type, 1110 unsigned int flood_table) 1111 { 1112 MLXSW_REG_ZERO(sfgc, payload); 1113 mlxsw_reg_sfgc_type_set(payload, type); 1114 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1115 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1116 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1117 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1118 } 1119 1120 /* SFTR - Switch Flooding Table Register 1121 * ------------------------------------- 1122 * The switch flooding table is used for flooding packet replication. The table 1123 * defines a bit mask of ports for packet replication. 1124 */ 1125 #define MLXSW_REG_SFTR_ID 0x2012 1126 #define MLXSW_REG_SFTR_LEN 0x420 1127 1128 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1129 1130 /* reg_sftr_swid 1131 * Switch partition ID with which to associate the port. 1132 * Access: Index 1133 */ 1134 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1135 1136 /* reg_sftr_flood_table 1137 * Flooding table index to associate with the specific type on the specific 1138 * switch partition. 1139 * Access: Index 1140 */ 1141 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1142 1143 /* reg_sftr_index 1144 * Index. Used as an index into the Flooding Table in case the table is 1145 * configured to use VID / FID or FID Offset. 1146 * Access: Index 1147 */ 1148 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1149 1150 /* reg_sftr_table_type 1151 * See mlxsw_flood_table_type 1152 * Access: RW 1153 */ 1154 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1155 1156 /* reg_sftr_range 1157 * Range of entries to update 1158 * Access: Index 1159 */ 1160 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1161 1162 /* reg_sftr_port 1163 * Local port membership (1 bit per port). 1164 * Access: RW 1165 */ 1166 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1167 1168 /* reg_sftr_cpu_port_mask 1169 * CPU port mask (1 bit per port). 1170 * Access: W 1171 */ 1172 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1173 1174 static inline void mlxsw_reg_sftr_pack(char *payload, 1175 unsigned int flood_table, 1176 unsigned int index, 1177 enum mlxsw_flood_table_type table_type, 1178 unsigned int range, u8 port, bool set) 1179 { 1180 MLXSW_REG_ZERO(sftr, payload); 1181 mlxsw_reg_sftr_swid_set(payload, 0); 1182 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1183 mlxsw_reg_sftr_index_set(payload, index); 1184 mlxsw_reg_sftr_table_type_set(payload, table_type); 1185 mlxsw_reg_sftr_range_set(payload, range); 1186 mlxsw_reg_sftr_port_set(payload, port, set); 1187 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1188 } 1189 1190 /* SFDF - Switch Filtering DB Flush 1191 * -------------------------------- 1192 * The switch filtering DB flush register is used to flush the FDB. 1193 * Note that FDB notifications are flushed as well. 1194 */ 1195 #define MLXSW_REG_SFDF_ID 0x2013 1196 #define MLXSW_REG_SFDF_LEN 0x14 1197 1198 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1199 1200 /* reg_sfdf_swid 1201 * Switch partition ID. 1202 * Access: Index 1203 */ 1204 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1205 1206 enum mlxsw_reg_sfdf_flush_type { 1207 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1208 MLXSW_REG_SFDF_FLUSH_PER_FID, 1209 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1210 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1211 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1212 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1213 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1214 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1215 }; 1216 1217 /* reg_sfdf_flush_type 1218 * Flush type. 1219 * 0 - All SWID dynamic entries are flushed. 1220 * 1 - All FID dynamic entries are flushed. 1221 * 2 - All dynamic entries pointing to port are flushed. 1222 * 3 - All FID dynamic entries pointing to port are flushed. 1223 * 4 - All dynamic entries pointing to LAG are flushed. 1224 * 5 - All FID dynamic entries pointing to LAG are flushed. 1225 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1226 * flushed. 1227 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1228 * flushed, per FID. 1229 * Access: RW 1230 */ 1231 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1232 1233 /* reg_sfdf_flush_static 1234 * Static. 1235 * 0 - Flush only dynamic entries. 1236 * 1 - Flush both dynamic and static entries. 1237 * Access: RW 1238 */ 1239 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1240 1241 static inline void mlxsw_reg_sfdf_pack(char *payload, 1242 enum mlxsw_reg_sfdf_flush_type type) 1243 { 1244 MLXSW_REG_ZERO(sfdf, payload); 1245 mlxsw_reg_sfdf_flush_type_set(payload, type); 1246 mlxsw_reg_sfdf_flush_static_set(payload, true); 1247 } 1248 1249 /* reg_sfdf_fid 1250 * FID to flush. 1251 * Access: RW 1252 */ 1253 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1254 1255 /* reg_sfdf_system_port 1256 * Port to flush. 1257 * Access: RW 1258 */ 1259 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1260 1261 /* reg_sfdf_port_fid_system_port 1262 * Port to flush, pointed to by FID. 1263 * Access: RW 1264 */ 1265 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1266 1267 /* reg_sfdf_lag_id 1268 * LAG ID to flush. 1269 * Access: RW 1270 */ 1271 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1272 1273 /* reg_sfdf_lag_fid_lag_id 1274 * LAG ID to flush, pointed to by FID. 1275 * Access: RW 1276 */ 1277 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1278 1279 /* SLDR - Switch LAG Descriptor Register 1280 * ----------------------------------------- 1281 * The switch LAG descriptor register is populated by LAG descriptors. 1282 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1283 * max_lag-1. 1284 */ 1285 #define MLXSW_REG_SLDR_ID 0x2014 1286 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1287 1288 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1289 1290 enum mlxsw_reg_sldr_op { 1291 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1292 MLXSW_REG_SLDR_OP_LAG_CREATE, 1293 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1294 /* Ports that appear in the list have the Distributor enabled */ 1295 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1296 /* Removes ports from the disributor list */ 1297 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1298 }; 1299 1300 /* reg_sldr_op 1301 * Operation. 1302 * Access: RW 1303 */ 1304 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1305 1306 /* reg_sldr_lag_id 1307 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1308 * Access: Index 1309 */ 1310 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1311 1312 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1313 { 1314 MLXSW_REG_ZERO(sldr, payload); 1315 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1316 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1317 } 1318 1319 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1320 { 1321 MLXSW_REG_ZERO(sldr, payload); 1322 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1323 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1324 } 1325 1326 /* reg_sldr_num_ports 1327 * The number of member ports of the LAG. 1328 * Reserved for Create / Destroy operations 1329 * For Add / Remove operations - indicates the number of ports in the list. 1330 * Access: RW 1331 */ 1332 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1333 1334 /* reg_sldr_system_port 1335 * System port. 1336 * Access: RW 1337 */ 1338 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1339 1340 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1341 u8 local_port) 1342 { 1343 MLXSW_REG_ZERO(sldr, payload); 1344 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1345 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1346 mlxsw_reg_sldr_num_ports_set(payload, 1); 1347 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1348 } 1349 1350 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1351 u8 local_port) 1352 { 1353 MLXSW_REG_ZERO(sldr, payload); 1354 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1355 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1356 mlxsw_reg_sldr_num_ports_set(payload, 1); 1357 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1358 } 1359 1360 /* SLCR - Switch LAG Configuration 2 Register 1361 * ------------------------------------------- 1362 * The Switch LAG Configuration register is used for configuring the 1363 * LAG properties of the switch. 1364 */ 1365 #define MLXSW_REG_SLCR_ID 0x2015 1366 #define MLXSW_REG_SLCR_LEN 0x10 1367 1368 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1369 1370 enum mlxsw_reg_slcr_pp { 1371 /* Global Configuration (for all ports) */ 1372 MLXSW_REG_SLCR_PP_GLOBAL, 1373 /* Per port configuration, based on local_port field */ 1374 MLXSW_REG_SLCR_PP_PER_PORT, 1375 }; 1376 1377 /* reg_slcr_pp 1378 * Per Port Configuration 1379 * Note: Reading at Global mode results in reading port 1 configuration. 1380 * Access: Index 1381 */ 1382 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1383 1384 /* reg_slcr_local_port 1385 * Local port number 1386 * Supported from CPU port 1387 * Not supported from router port 1388 * Reserved when pp = Global Configuration 1389 * Access: Index 1390 */ 1391 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1392 1393 enum mlxsw_reg_slcr_type { 1394 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1395 MLXSW_REG_SLCR_TYPE_XOR, 1396 MLXSW_REG_SLCR_TYPE_RANDOM, 1397 }; 1398 1399 /* reg_slcr_type 1400 * Hash type 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1404 1405 /* Ingress port */ 1406 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1407 /* SMAC - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1409 /* SMAC - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1411 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1412 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1414 /* DMAC - for IPv4 and IPv6 packets */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1416 /* DMAC - for non-IP packets */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1418 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1419 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1420 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1421 /* Ethertype - for IPv4 and IPv6 packets */ 1422 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1423 /* Ethertype - for non-IP packets */ 1424 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1425 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1426 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1427 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1428 /* VLAN ID - for IPv4 and IPv6 packets */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1430 /* VLAN ID - for non-IP packets */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1432 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1433 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1434 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1435 /* Source IP address (can be IPv4 or IPv6) */ 1436 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1437 /* Destination IP address (can be IPv4 or IPv6) */ 1438 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1439 /* TCP/UDP source port */ 1440 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1441 /* TCP/UDP destination port*/ 1442 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1443 /* IPv4 Protocol/IPv6 Next Header */ 1444 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1445 /* IPv6 Flow label */ 1446 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1447 /* SID - FCoE source ID */ 1448 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1449 /* DID - FCoE destination ID */ 1450 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1451 /* OXID - FCoE originator exchange ID */ 1452 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1453 /* Destination QP number - for RoCE packets */ 1454 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1455 1456 /* reg_slcr_lag_hash 1457 * LAG hashing configuration. This is a bitmask, in which each set 1458 * bit includes the corresponding item in the LAG hash calculation. 1459 * The default lag_hash contains SMAC, DMAC, VLANID and 1460 * Ethertype (for all packet types). 1461 * Access: RW 1462 */ 1463 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1464 1465 /* reg_slcr_seed 1466 * LAG seed value. The seed is the same for all ports. 1467 * Access: RW 1468 */ 1469 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1470 1471 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1472 { 1473 MLXSW_REG_ZERO(slcr, payload); 1474 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1475 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1476 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1477 mlxsw_reg_slcr_seed_set(payload, seed); 1478 } 1479 1480 /* SLCOR - Switch LAG Collector Register 1481 * ------------------------------------- 1482 * The Switch LAG Collector register controls the Local Port membership 1483 * in a LAG and enablement of the collector. 1484 */ 1485 #define MLXSW_REG_SLCOR_ID 0x2016 1486 #define MLXSW_REG_SLCOR_LEN 0x10 1487 1488 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1489 1490 enum mlxsw_reg_slcor_col { 1491 /* Port is added with collector disabled */ 1492 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1493 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1495 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1496 }; 1497 1498 /* reg_slcor_col 1499 * Collector configuration 1500 * Access: RW 1501 */ 1502 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1503 1504 /* reg_slcor_local_port 1505 * Local port number 1506 * Not supported for CPU port 1507 * Access: Index 1508 */ 1509 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1510 1511 /* reg_slcor_lag_id 1512 * LAG Identifier. Index into the LAG descriptor table. 1513 * Access: Index 1514 */ 1515 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1516 1517 /* reg_slcor_port_index 1518 * Port index in the LAG list. Only valid on Add Port to LAG col. 1519 * Valid range is from 0 to cap_max_lag_members-1 1520 * Access: RW 1521 */ 1522 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1523 1524 static inline void mlxsw_reg_slcor_pack(char *payload, 1525 u8 local_port, u16 lag_id, 1526 enum mlxsw_reg_slcor_col col) 1527 { 1528 MLXSW_REG_ZERO(slcor, payload); 1529 mlxsw_reg_slcor_col_set(payload, col); 1530 mlxsw_reg_slcor_local_port_set(payload, local_port); 1531 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1532 } 1533 1534 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1535 u8 local_port, u16 lag_id, 1536 u8 port_index) 1537 { 1538 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1539 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1540 mlxsw_reg_slcor_port_index_set(payload, port_index); 1541 } 1542 1543 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1544 u8 local_port, u16 lag_id) 1545 { 1546 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1547 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1548 } 1549 1550 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1551 u8 local_port, u16 lag_id) 1552 { 1553 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1554 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1555 } 1556 1557 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1558 u8 local_port, u16 lag_id) 1559 { 1560 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1561 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1562 } 1563 1564 /* SPMLR - Switch Port MAC Learning Register 1565 * ----------------------------------------- 1566 * Controls the Switch MAC learning policy per port. 1567 */ 1568 #define MLXSW_REG_SPMLR_ID 0x2018 1569 #define MLXSW_REG_SPMLR_LEN 0x8 1570 1571 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1572 1573 /* reg_spmlr_local_port 1574 * Local port number. 1575 * Access: Index 1576 */ 1577 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1578 1579 /* reg_spmlr_sub_port 1580 * Virtual port within the physical port. 1581 * Should be set to 0 when virtual ports are not enabled on the port. 1582 * Access: Index 1583 */ 1584 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1585 1586 enum mlxsw_reg_spmlr_learn_mode { 1587 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1588 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1589 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1590 }; 1591 1592 /* reg_spmlr_learn_mode 1593 * Learning mode on the port. 1594 * 0 - Learning disabled. 1595 * 2 - Learning enabled. 1596 * 3 - Security mode. 1597 * 1598 * In security mode the switch does not learn MACs on the port, but uses the 1599 * SMAC to see if it exists on another ingress port. If so, the packet is 1600 * classified as a bad packet and is discarded unless the software registers 1601 * to receive port security error packets usign HPKT. 1602 */ 1603 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1604 1605 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1606 enum mlxsw_reg_spmlr_learn_mode mode) 1607 { 1608 MLXSW_REG_ZERO(spmlr, payload); 1609 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1610 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1611 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1612 } 1613 1614 /* SVFA - Switch VID to FID Allocation Register 1615 * -------------------------------------------- 1616 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1617 * virtualized ports. 1618 */ 1619 #define MLXSW_REG_SVFA_ID 0x201C 1620 #define MLXSW_REG_SVFA_LEN 0x10 1621 1622 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1623 1624 /* reg_svfa_swid 1625 * Switch partition ID. 1626 * Access: Index 1627 */ 1628 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1629 1630 /* reg_svfa_local_port 1631 * Local port number. 1632 * Access: Index 1633 * 1634 * Note: Reserved for 802.1Q FIDs. 1635 */ 1636 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1637 1638 enum mlxsw_reg_svfa_mt { 1639 MLXSW_REG_SVFA_MT_VID_TO_FID, 1640 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1641 }; 1642 1643 /* reg_svfa_mapping_table 1644 * Mapping table: 1645 * 0 - VID to FID 1646 * 1 - {Port, VID} to FID 1647 * Access: Index 1648 * 1649 * Note: Reserved for SwitchX-2. 1650 */ 1651 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1652 1653 /* reg_svfa_v 1654 * Valid. 1655 * Valid if set. 1656 * Access: RW 1657 * 1658 * Note: Reserved for SwitchX-2. 1659 */ 1660 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1661 1662 /* reg_svfa_fid 1663 * Filtering ID. 1664 * Access: RW 1665 */ 1666 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1667 1668 /* reg_svfa_vid 1669 * VLAN ID. 1670 * Access: Index 1671 */ 1672 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1673 1674 /* reg_svfa_counter_set_type 1675 * Counter set type for flow counters. 1676 * Access: RW 1677 * 1678 * Note: Reserved for SwitchX-2. 1679 */ 1680 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1681 1682 /* reg_svfa_counter_index 1683 * Counter index for flow counters. 1684 * Access: RW 1685 * 1686 * Note: Reserved for SwitchX-2. 1687 */ 1688 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1689 1690 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1691 enum mlxsw_reg_svfa_mt mt, bool valid, 1692 u16 fid, u16 vid) 1693 { 1694 MLXSW_REG_ZERO(svfa, payload); 1695 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1696 mlxsw_reg_svfa_swid_set(payload, 0); 1697 mlxsw_reg_svfa_local_port_set(payload, local_port); 1698 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1699 mlxsw_reg_svfa_v_set(payload, valid); 1700 mlxsw_reg_svfa_fid_set(payload, fid); 1701 mlxsw_reg_svfa_vid_set(payload, vid); 1702 } 1703 1704 /* SPVTR - Switch Port VLAN Stacking Register 1705 * ------------------------------------------ 1706 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1707 * to enable VLAN stacking. 1708 */ 1709 #define MLXSW_REG_SPVTR_ID 0x201D 1710 #define MLXSW_REG_SPVTR_LEN 0x10 1711 1712 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1713 1714 /* reg_spvtr_tport 1715 * Port is tunnel port. 1716 * Access: Index 1717 * 1718 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1719 */ 1720 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1721 1722 /* reg_spvtr_local_port 1723 * When tport = 0: local port number (Not supported from/to CPU). 1724 * When tport = 1: tunnel port. 1725 * Access: Index 1726 */ 1727 MLXSW_ITEM32(reg, spvtr, local_port, 0x00, 16, 8); 1728 1729 /* reg_spvtr_ippe 1730 * Ingress Port Prio Mode Update Enable. 1731 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1732 * Reserved on Get operations. 1733 * Access: OP 1734 */ 1735 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1736 1737 /* reg_spvtr_ipve 1738 * Ingress Port VID Mode Update Enable. 1739 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1740 * field. 1741 * Reserved on Get operations. 1742 * Access: OP 1743 */ 1744 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1745 1746 /* reg_spvtr_epve 1747 * Egress Port VID Mode Update Enable. 1748 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1749 * field. 1750 * Access: OP 1751 */ 1752 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1753 1754 /* reg_spvtr_ipprio_mode 1755 * Ingress Port Priority Mode. 1756 * This controls the PCP and DEI of the new outer VLAN 1757 * Note: for SwitchX/-2 the DEI is not affected. 1758 * 0: use port default PCP and DEI (configured by QPDPC). 1759 * 1: use C-VLAN PCP and DEI. 1760 * Has no effect when ipvid_mode = 0. 1761 * Reserved when tport = 1. 1762 * Access: RW 1763 */ 1764 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1765 1766 enum mlxsw_reg_spvtr_ipvid_mode { 1767 /* IEEE Compliant PVID (default) */ 1768 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1769 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1770 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1771 /* Always push VLAN (also for prio tagged packets) */ 1772 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1773 }; 1774 1775 /* reg_spvtr_ipvid_mode 1776 * Ingress Port VLAN-ID Mode. 1777 * For Spectrum family, this affects the values of SPVM.i 1778 * Access: RW 1779 */ 1780 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1781 1782 enum mlxsw_reg_spvtr_epvid_mode { 1783 /* IEEE Compliant VLAN membership */ 1784 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1785 /* Pop VLAN (for VLAN stacking) */ 1786 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1787 }; 1788 1789 /* reg_spvtr_epvid_mode 1790 * Egress Port VLAN-ID Mode. 1791 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1792 * Access: WO 1793 */ 1794 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1795 1796 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1797 u8 local_port, 1798 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1799 { 1800 MLXSW_REG_ZERO(spvtr, payload); 1801 mlxsw_reg_spvtr_tport_set(payload, tport); 1802 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1803 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1804 mlxsw_reg_spvtr_ipve_set(payload, true); 1805 } 1806 1807 /* SVPE - Switch Virtual-Port Enabling Register 1808 * -------------------------------------------- 1809 * Enables port virtualization. 1810 */ 1811 #define MLXSW_REG_SVPE_ID 0x201E 1812 #define MLXSW_REG_SVPE_LEN 0x4 1813 1814 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1815 1816 /* reg_svpe_local_port 1817 * Local port number 1818 * Access: Index 1819 * 1820 * Note: CPU port is not supported (uses VLAN mode only). 1821 */ 1822 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1823 1824 /* reg_svpe_vp_en 1825 * Virtual port enable. 1826 * 0 - Disable, VLAN mode (VID to FID). 1827 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1828 * Access: RW 1829 */ 1830 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1831 1832 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1833 bool enable) 1834 { 1835 MLXSW_REG_ZERO(svpe, payload); 1836 mlxsw_reg_svpe_local_port_set(payload, local_port); 1837 mlxsw_reg_svpe_vp_en_set(payload, enable); 1838 } 1839 1840 /* SFMR - Switch FID Management Register 1841 * ------------------------------------- 1842 * Creates and configures FIDs. 1843 */ 1844 #define MLXSW_REG_SFMR_ID 0x201F 1845 #define MLXSW_REG_SFMR_LEN 0x18 1846 1847 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1848 1849 enum mlxsw_reg_sfmr_op { 1850 MLXSW_REG_SFMR_OP_CREATE_FID, 1851 MLXSW_REG_SFMR_OP_DESTROY_FID, 1852 }; 1853 1854 /* reg_sfmr_op 1855 * Operation. 1856 * 0 - Create or edit FID. 1857 * 1 - Destroy FID. 1858 * Access: WO 1859 */ 1860 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1861 1862 /* reg_sfmr_fid 1863 * Filtering ID. 1864 * Access: Index 1865 */ 1866 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1867 1868 /* reg_sfmr_fid_offset 1869 * FID offset. 1870 * Used to point into the flooding table selected by SFGC register if 1871 * the table is of type FID-Offset. Otherwise, this field is reserved. 1872 * Access: RW 1873 */ 1874 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1875 1876 /* reg_sfmr_vtfp 1877 * Valid Tunnel Flood Pointer. 1878 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1879 * Access: RW 1880 * 1881 * Note: Reserved for 802.1Q FIDs. 1882 */ 1883 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1884 1885 /* reg_sfmr_nve_tunnel_flood_ptr 1886 * Underlay Flooding and BC Pointer. 1887 * Used as a pointer to the first entry of the group based link lists of 1888 * flooding or BC entries (for NVE tunnels). 1889 * Access: RW 1890 */ 1891 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1892 1893 /* reg_sfmr_vv 1894 * VNI Valid. 1895 * If not set, then vni is reserved. 1896 * Access: RW 1897 * 1898 * Note: Reserved for 802.1Q FIDs. 1899 */ 1900 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1901 1902 /* reg_sfmr_vni 1903 * Virtual Network Identifier. 1904 * Access: RW 1905 * 1906 * Note: A given VNI can only be assigned to one FID. 1907 */ 1908 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1909 1910 static inline void mlxsw_reg_sfmr_pack(char *payload, 1911 enum mlxsw_reg_sfmr_op op, u16 fid, 1912 u16 fid_offset) 1913 { 1914 MLXSW_REG_ZERO(sfmr, payload); 1915 mlxsw_reg_sfmr_op_set(payload, op); 1916 mlxsw_reg_sfmr_fid_set(payload, fid); 1917 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1918 mlxsw_reg_sfmr_vtfp_set(payload, false); 1919 mlxsw_reg_sfmr_vv_set(payload, false); 1920 } 1921 1922 /* SPVMLR - Switch Port VLAN MAC Learning Register 1923 * ----------------------------------------------- 1924 * Controls the switch MAC learning policy per {Port, VID}. 1925 */ 1926 #define MLXSW_REG_SPVMLR_ID 0x2020 1927 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1928 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1929 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1930 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1931 MLXSW_REG_SPVMLR_REC_LEN * \ 1932 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1933 1934 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1935 1936 /* reg_spvmlr_local_port 1937 * Local ingress port. 1938 * Access: Index 1939 * 1940 * Note: CPU port is not supported. 1941 */ 1942 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1943 1944 /* reg_spvmlr_num_rec 1945 * Number of records to update. 1946 * Access: OP 1947 */ 1948 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1949 1950 /* reg_spvmlr_rec_learn_enable 1951 * 0 - Disable learning for {Port, VID}. 1952 * 1 - Enable learning for {Port, VID}. 1953 * Access: RW 1954 */ 1955 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1956 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1957 1958 /* reg_spvmlr_rec_vid 1959 * VLAN ID to be added/removed from port or for querying. 1960 * Access: Index 1961 */ 1962 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1963 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1964 1965 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1966 u16 vid_begin, u16 vid_end, 1967 bool learn_enable) 1968 { 1969 int num_rec = vid_end - vid_begin + 1; 1970 int i; 1971 1972 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1973 1974 MLXSW_REG_ZERO(spvmlr, payload); 1975 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1976 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1977 1978 for (i = 0; i < num_rec; i++) { 1979 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1980 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1981 } 1982 } 1983 1984 /* SPVC - Switch Port VLAN Classification Register 1985 * ----------------------------------------------- 1986 * Configures the port to identify packets as untagged / single tagged / 1987 * double packets based on the packet EtherTypes. 1988 * Ethertype IDs are configured by SVER. 1989 */ 1990 #define MLXSW_REG_SPVC_ID 0x2026 1991 #define MLXSW_REG_SPVC_LEN 0x0C 1992 1993 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 1994 1995 /* reg_spvc_local_port 1996 * Local port. 1997 * Access: Index 1998 * 1999 * Note: applies both to Rx port and Tx port, so if a packet traverses 2000 * through Rx port i and a Tx port j then port i and port j must have the 2001 * same configuration. 2002 */ 2003 MLXSW_ITEM32(reg, spvc, local_port, 0x00, 16, 8); 2004 2005 /* reg_spvc_inner_et2 2006 * Vlan Tag1 EtherType2 enable. 2007 * Packet is initially classified as double VLAN Tag if in addition to 2008 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2009 * equal to ether_type2. 2010 * 0: disable (default) 2011 * 1: enable 2012 * Access: RW 2013 */ 2014 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2015 2016 /* reg_spvc_et2 2017 * Vlan Tag0 EtherType2 enable. 2018 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2019 * equal to ether_type2. 2020 * 0: disable (default) 2021 * 1: enable 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2025 2026 /* reg_spvc_inner_et1 2027 * Vlan Tag1 EtherType1 enable. 2028 * Packet is initially classified as double VLAN Tag if in addition to 2029 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2030 * equal to ether_type1. 2031 * 0: disable 2032 * 1: enable (default) 2033 * Access: RW 2034 */ 2035 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2036 2037 /* reg_spvc_et1 2038 * Vlan Tag0 EtherType1 enable. 2039 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2040 * equal to ether_type1. 2041 * 0: disable 2042 * 1: enable (default) 2043 * Access: RW 2044 */ 2045 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2046 2047 /* reg_inner_et0 2048 * Vlan Tag1 EtherType0 enable. 2049 * Packet is initially classified as double VLAN Tag if in addition to 2050 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2051 * equal to ether_type0. 2052 * 0: disable 2053 * 1: enable (default) 2054 * Access: RW 2055 */ 2056 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2057 2058 /* reg_et0 2059 * Vlan Tag0 EtherType0 enable. 2060 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2061 * equal to ether_type0. 2062 * 0: disable 2063 * 1: enable (default) 2064 * Access: RW 2065 */ 2066 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2067 2068 static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1, 2069 bool et0) 2070 { 2071 MLXSW_REG_ZERO(spvc, payload); 2072 mlxsw_reg_spvc_local_port_set(payload, local_port); 2073 /* Enable inner_et1 and inner_et0 to enable identification of double 2074 * tagged packets. 2075 */ 2076 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2077 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2078 mlxsw_reg_spvc_et1_set(payload, et1); 2079 mlxsw_reg_spvc_et0_set(payload, et0); 2080 } 2081 2082 /* CWTP - Congetion WRED ECN TClass Profile 2083 * ---------------------------------------- 2084 * Configures the profiles for queues of egress port and traffic class 2085 */ 2086 #define MLXSW_REG_CWTP_ID 0x2802 2087 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2088 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2089 #define MLXSW_REG_CWTP_LEN 0x40 2090 2091 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2092 2093 /* reg_cwtp_local_port 2094 * Local port number 2095 * Not supported for CPU port 2096 * Access: Index 2097 */ 2098 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 2099 2100 /* reg_cwtp_traffic_class 2101 * Traffic Class to configure 2102 * Access: Index 2103 */ 2104 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2105 2106 /* reg_cwtp_profile_min 2107 * Minimum Average Queue Size of the profile in cells. 2108 * Access: RW 2109 */ 2110 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2111 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2112 2113 /* reg_cwtp_profile_percent 2114 * Percentage of WRED and ECN marking for maximum Average Queue size 2115 * Range is 0 to 100, units of integer percentage 2116 * Access: RW 2117 */ 2118 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2119 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2120 2121 /* reg_cwtp_profile_max 2122 * Maximum Average Queue size of the profile in cells 2123 * Access: RW 2124 */ 2125 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2126 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2127 2128 #define MLXSW_REG_CWTP_MIN_VALUE 64 2129 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2130 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2131 2132 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 2133 u8 traffic_class) 2134 { 2135 int i; 2136 2137 MLXSW_REG_ZERO(cwtp, payload); 2138 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2139 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2140 2141 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2142 mlxsw_reg_cwtp_profile_min_set(payload, i, 2143 MLXSW_REG_CWTP_MIN_VALUE); 2144 mlxsw_reg_cwtp_profile_max_set(payload, i, 2145 MLXSW_REG_CWTP_MIN_VALUE); 2146 } 2147 } 2148 2149 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2150 2151 static inline void 2152 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2153 u32 probability) 2154 { 2155 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2156 2157 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2158 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2159 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2160 } 2161 2162 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2163 * --------------------------------------------------- 2164 * The CWTPM register maps each egress port and traffic class to profile num. 2165 */ 2166 #define MLXSW_REG_CWTPM_ID 0x2803 2167 #define MLXSW_REG_CWTPM_LEN 0x44 2168 2169 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2170 2171 /* reg_cwtpm_local_port 2172 * Local port number 2173 * Not supported for CPU port 2174 * Access: Index 2175 */ 2176 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 2177 2178 /* reg_cwtpm_traffic_class 2179 * Traffic Class to configure 2180 * Access: Index 2181 */ 2182 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2183 2184 /* reg_cwtpm_ew 2185 * Control enablement of WRED for traffic class: 2186 * 0 - Disable 2187 * 1 - Enable 2188 * Access: RW 2189 */ 2190 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2191 2192 /* reg_cwtpm_ee 2193 * Control enablement of ECN for traffic class: 2194 * 0 - Disable 2195 * 1 - Enable 2196 * Access: RW 2197 */ 2198 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2199 2200 /* reg_cwtpm_tcp_g 2201 * TCP Green Profile. 2202 * Index of the profile within {port, traffic class} to use. 2203 * 0 for disabling both WRED and ECN for this type of traffic. 2204 * Access: RW 2205 */ 2206 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2207 2208 /* reg_cwtpm_tcp_y 2209 * TCP Yellow Profile. 2210 * Index of the profile within {port, traffic class} to use. 2211 * 0 for disabling both WRED and ECN for this type of traffic. 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2215 2216 /* reg_cwtpm_tcp_r 2217 * TCP Red Profile. 2218 * Index of the profile within {port, traffic class} to use. 2219 * 0 for disabling both WRED and ECN for this type of traffic. 2220 * Access: RW 2221 */ 2222 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2223 2224 /* reg_cwtpm_ntcp_g 2225 * Non-TCP Green Profile. 2226 * Index of the profile within {port, traffic class} to use. 2227 * 0 for disabling both WRED and ECN for this type of traffic. 2228 * Access: RW 2229 */ 2230 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2231 2232 /* reg_cwtpm_ntcp_y 2233 * Non-TCP Yellow Profile. 2234 * Index of the profile within {port, traffic class} to use. 2235 * 0 for disabling both WRED and ECN for this type of traffic. 2236 * Access: RW 2237 */ 2238 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2239 2240 /* reg_cwtpm_ntcp_r 2241 * Non-TCP Red Profile. 2242 * Index of the profile within {port, traffic class} to use. 2243 * 0 for disabling both WRED and ECN for this type of traffic. 2244 * Access: RW 2245 */ 2246 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2247 2248 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2249 2250 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2251 u8 traffic_class, u8 profile, 2252 bool wred, bool ecn) 2253 { 2254 MLXSW_REG_ZERO(cwtpm, payload); 2255 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2256 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2257 mlxsw_reg_cwtpm_ew_set(payload, wred); 2258 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2259 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2260 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2261 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2262 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2263 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2264 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2265 } 2266 2267 /* PGCR - Policy-Engine General Configuration Register 2268 * --------------------------------------------------- 2269 * This register configures general Policy-Engine settings. 2270 */ 2271 #define MLXSW_REG_PGCR_ID 0x3001 2272 #define MLXSW_REG_PGCR_LEN 0x20 2273 2274 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2275 2276 /* reg_pgcr_default_action_pointer_base 2277 * Default action pointer base. Each region has a default action pointer 2278 * which is equal to default_action_pointer_base + region_id. 2279 * Access: RW 2280 */ 2281 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2282 2283 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2284 { 2285 MLXSW_REG_ZERO(pgcr, payload); 2286 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2287 } 2288 2289 /* PPBT - Policy-Engine Port Binding Table 2290 * --------------------------------------- 2291 * This register is used for configuration of the Port Binding Table. 2292 */ 2293 #define MLXSW_REG_PPBT_ID 0x3002 2294 #define MLXSW_REG_PPBT_LEN 0x14 2295 2296 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2297 2298 enum mlxsw_reg_pxbt_e { 2299 MLXSW_REG_PXBT_E_IACL, 2300 MLXSW_REG_PXBT_E_EACL, 2301 }; 2302 2303 /* reg_ppbt_e 2304 * Access: Index 2305 */ 2306 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2307 2308 enum mlxsw_reg_pxbt_op { 2309 MLXSW_REG_PXBT_OP_BIND, 2310 MLXSW_REG_PXBT_OP_UNBIND, 2311 }; 2312 2313 /* reg_ppbt_op 2314 * Access: RW 2315 */ 2316 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2317 2318 /* reg_ppbt_local_port 2319 * Local port. Not including CPU port. 2320 * Access: Index 2321 */ 2322 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2323 2324 /* reg_ppbt_g 2325 * group - When set, the binding is of an ACL group. When cleared, 2326 * the binding is of an ACL. 2327 * Must be set to 1 for Spectrum. 2328 * Access: RW 2329 */ 2330 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2331 2332 /* reg_ppbt_acl_info 2333 * ACL/ACL group identifier. If the g bit is set, this field should hold 2334 * the acl_group_id, else it should hold the acl_id. 2335 * Access: RW 2336 */ 2337 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2338 2339 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2340 enum mlxsw_reg_pxbt_op op, 2341 u8 local_port, u16 acl_info) 2342 { 2343 MLXSW_REG_ZERO(ppbt, payload); 2344 mlxsw_reg_ppbt_e_set(payload, e); 2345 mlxsw_reg_ppbt_op_set(payload, op); 2346 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2347 mlxsw_reg_ppbt_g_set(payload, true); 2348 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2349 } 2350 2351 /* PACL - Policy-Engine ACL Register 2352 * --------------------------------- 2353 * This register is used for configuration of the ACL. 2354 */ 2355 #define MLXSW_REG_PACL_ID 0x3004 2356 #define MLXSW_REG_PACL_LEN 0x70 2357 2358 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2359 2360 /* reg_pacl_v 2361 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2362 * while the ACL is bounded to either a port, VLAN or ACL rule. 2363 * Access: RW 2364 */ 2365 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2366 2367 /* reg_pacl_acl_id 2368 * An identifier representing the ACL (managed by software) 2369 * Range 0 .. cap_max_acl_regions - 1 2370 * Access: Index 2371 */ 2372 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2373 2374 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2375 2376 /* reg_pacl_tcam_region_info 2377 * Opaque object that represents a TCAM region. 2378 * Obtained through PTAR register. 2379 * Access: RW 2380 */ 2381 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2382 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2383 2384 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2385 bool valid, const char *tcam_region_info) 2386 { 2387 MLXSW_REG_ZERO(pacl, payload); 2388 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2389 mlxsw_reg_pacl_v_set(payload, valid); 2390 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2391 } 2392 2393 /* PAGT - Policy-Engine ACL Group Table 2394 * ------------------------------------ 2395 * This register is used for configuration of the ACL Group Table. 2396 */ 2397 #define MLXSW_REG_PAGT_ID 0x3005 2398 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2399 #define MLXSW_REG_PAGT_ACL_LEN 4 2400 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2401 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2402 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2403 2404 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2405 2406 /* reg_pagt_size 2407 * Number of ACLs in the group. 2408 * Size 0 invalidates a group. 2409 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2410 * Total number of ACLs in all groups must be lower or equal 2411 * to cap_max_acl_tot_groups 2412 * Note: a group which is binded must not be invalidated 2413 * Access: Index 2414 */ 2415 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2416 2417 /* reg_pagt_acl_group_id 2418 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2419 * the ACL Group identifier (managed by software). 2420 * Access: Index 2421 */ 2422 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2423 2424 /* reg_pagt_multi 2425 * Multi-ACL 2426 * 0 - This ACL is the last ACL in the multi-ACL 2427 * 1 - This ACL is part of a multi-ACL 2428 * Access: RW 2429 */ 2430 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2431 2432 /* reg_pagt_acl_id 2433 * ACL identifier 2434 * Access: RW 2435 */ 2436 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2437 2438 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2439 { 2440 MLXSW_REG_ZERO(pagt, payload); 2441 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2442 } 2443 2444 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2445 u16 acl_id, bool multi) 2446 { 2447 u8 size = mlxsw_reg_pagt_size_get(payload); 2448 2449 if (index >= size) 2450 mlxsw_reg_pagt_size_set(payload, index + 1); 2451 mlxsw_reg_pagt_multi_set(payload, index, multi); 2452 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2453 } 2454 2455 /* PTAR - Policy-Engine TCAM Allocation Register 2456 * --------------------------------------------- 2457 * This register is used for allocation of regions in the TCAM. 2458 * Note: Query method is not supported on this register. 2459 */ 2460 #define MLXSW_REG_PTAR_ID 0x3006 2461 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2462 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2463 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2464 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2465 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2466 2467 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2468 2469 enum mlxsw_reg_ptar_op { 2470 /* allocate a TCAM region */ 2471 MLXSW_REG_PTAR_OP_ALLOC, 2472 /* resize a TCAM region */ 2473 MLXSW_REG_PTAR_OP_RESIZE, 2474 /* deallocate TCAM region */ 2475 MLXSW_REG_PTAR_OP_FREE, 2476 /* test allocation */ 2477 MLXSW_REG_PTAR_OP_TEST, 2478 }; 2479 2480 /* reg_ptar_op 2481 * Access: OP 2482 */ 2483 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2484 2485 /* reg_ptar_action_set_type 2486 * Type of action set to be used on this region. 2487 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2488 * Access: WO 2489 */ 2490 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2491 2492 enum mlxsw_reg_ptar_key_type { 2493 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2494 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2495 }; 2496 2497 /* reg_ptar_key_type 2498 * TCAM key type for the region. 2499 * Access: WO 2500 */ 2501 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2502 2503 /* reg_ptar_region_size 2504 * TCAM region size. When allocating/resizing this is the requested size, 2505 * the response is the actual size. Note that actual size may be 2506 * larger than requested. 2507 * Allowed range 1 .. cap_max_rules-1 2508 * Reserved during op deallocate. 2509 * Access: WO 2510 */ 2511 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2512 2513 /* reg_ptar_region_id 2514 * Region identifier 2515 * Range 0 .. cap_max_regions-1 2516 * Access: Index 2517 */ 2518 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2519 2520 /* reg_ptar_tcam_region_info 2521 * Opaque object that represents the TCAM region. 2522 * Returned when allocating a region. 2523 * Provided by software for ACL generation and region deallocation and resize. 2524 * Access: RW 2525 */ 2526 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2527 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2528 2529 /* reg_ptar_flexible_key_id 2530 * Identifier of the Flexible Key. 2531 * Only valid if key_type == "FLEX_KEY" 2532 * The key size will be rounded up to one of the following values: 2533 * 9B, 18B, 36B, 54B. 2534 * This field is reserved for in resize operation. 2535 * Access: WO 2536 */ 2537 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2538 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2539 2540 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2541 enum mlxsw_reg_ptar_key_type key_type, 2542 u16 region_size, u16 region_id, 2543 const char *tcam_region_info) 2544 { 2545 MLXSW_REG_ZERO(ptar, payload); 2546 mlxsw_reg_ptar_op_set(payload, op); 2547 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2548 mlxsw_reg_ptar_key_type_set(payload, key_type); 2549 mlxsw_reg_ptar_region_size_set(payload, region_size); 2550 mlxsw_reg_ptar_region_id_set(payload, region_id); 2551 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2552 } 2553 2554 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2555 u16 key_id) 2556 { 2557 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2558 } 2559 2560 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2561 { 2562 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2563 } 2564 2565 /* PPBS - Policy-Engine Policy Based Switching Register 2566 * ---------------------------------------------------- 2567 * This register retrieves and sets Policy Based Switching Table entries. 2568 */ 2569 #define MLXSW_REG_PPBS_ID 0x300C 2570 #define MLXSW_REG_PPBS_LEN 0x14 2571 2572 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2573 2574 /* reg_ppbs_pbs_ptr 2575 * Index into the PBS table. 2576 * For Spectrum, the index points to the KVD Linear. 2577 * Access: Index 2578 */ 2579 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2580 2581 /* reg_ppbs_system_port 2582 * Unique port identifier for the final destination of the packet. 2583 * Access: RW 2584 */ 2585 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2586 2587 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2588 u16 system_port) 2589 { 2590 MLXSW_REG_ZERO(ppbs, payload); 2591 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2592 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2593 } 2594 2595 /* PRCR - Policy-Engine Rules Copy Register 2596 * ---------------------------------------- 2597 * This register is used for accessing rules within a TCAM region. 2598 */ 2599 #define MLXSW_REG_PRCR_ID 0x300D 2600 #define MLXSW_REG_PRCR_LEN 0x40 2601 2602 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2603 2604 enum mlxsw_reg_prcr_op { 2605 /* Move rules. Moves the rules from "tcam_region_info" starting 2606 * at offset "offset" to "dest_tcam_region_info" 2607 * at offset "dest_offset." 2608 */ 2609 MLXSW_REG_PRCR_OP_MOVE, 2610 /* Copy rules. Copies the rules from "tcam_region_info" starting 2611 * at offset "offset" to "dest_tcam_region_info" 2612 * at offset "dest_offset." 2613 */ 2614 MLXSW_REG_PRCR_OP_COPY, 2615 }; 2616 2617 /* reg_prcr_op 2618 * Access: OP 2619 */ 2620 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2621 2622 /* reg_prcr_offset 2623 * Offset within the source region to copy/move from. 2624 * Access: Index 2625 */ 2626 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2627 2628 /* reg_prcr_size 2629 * The number of rules to copy/move. 2630 * Access: WO 2631 */ 2632 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2633 2634 /* reg_prcr_tcam_region_info 2635 * Opaque object that represents the source TCAM region. 2636 * Access: Index 2637 */ 2638 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2639 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2640 2641 /* reg_prcr_dest_offset 2642 * Offset within the source region to copy/move to. 2643 * Access: Index 2644 */ 2645 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2646 2647 /* reg_prcr_dest_tcam_region_info 2648 * Opaque object that represents the destination TCAM region. 2649 * Access: Index 2650 */ 2651 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2652 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2653 2654 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2655 const char *src_tcam_region_info, 2656 u16 src_offset, 2657 const char *dest_tcam_region_info, 2658 u16 dest_offset, u16 size) 2659 { 2660 MLXSW_REG_ZERO(prcr, payload); 2661 mlxsw_reg_prcr_op_set(payload, op); 2662 mlxsw_reg_prcr_offset_set(payload, src_offset); 2663 mlxsw_reg_prcr_size_set(payload, size); 2664 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2665 src_tcam_region_info); 2666 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2667 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2668 dest_tcam_region_info); 2669 } 2670 2671 /* PEFA - Policy-Engine Extended Flexible Action Register 2672 * ------------------------------------------------------ 2673 * This register is used for accessing an extended flexible action entry 2674 * in the central KVD Linear Database. 2675 */ 2676 #define MLXSW_REG_PEFA_ID 0x300F 2677 #define MLXSW_REG_PEFA_LEN 0xB0 2678 2679 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2680 2681 /* reg_pefa_index 2682 * Index in the KVD Linear Centralized Database. 2683 * Access: Index 2684 */ 2685 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2686 2687 /* reg_pefa_a 2688 * Index in the KVD Linear Centralized Database. 2689 * Activity 2690 * For a new entry: set if ca=0, clear if ca=1 2691 * Set if a packet lookup has hit on the specific entry 2692 * Access: RO 2693 */ 2694 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2695 2696 /* reg_pefa_ca 2697 * Clear activity 2698 * When write: activity is according to this field 2699 * When read: after reading the activity is cleared according to ca 2700 * Access: OP 2701 */ 2702 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2703 2704 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2705 2706 /* reg_pefa_flex_action_set 2707 * Action-set to perform when rule is matched. 2708 * Must be zero padded if action set is shorter. 2709 * Access: RW 2710 */ 2711 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2712 2713 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2714 const char *flex_action_set) 2715 { 2716 MLXSW_REG_ZERO(pefa, payload); 2717 mlxsw_reg_pefa_index_set(payload, index); 2718 mlxsw_reg_pefa_ca_set(payload, ca); 2719 if (flex_action_set) 2720 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2721 flex_action_set); 2722 } 2723 2724 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2725 { 2726 *p_a = mlxsw_reg_pefa_a_get(payload); 2727 } 2728 2729 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2730 * -------------------------------------------------------------- 2731 * This register is used for binding Multicast router to an ACL group 2732 * that serves the MC router. 2733 * This register is not supported by SwitchX/-2 and Spectrum. 2734 */ 2735 #define MLXSW_REG_PEMRBT_ID 0x3014 2736 #define MLXSW_REG_PEMRBT_LEN 0x14 2737 2738 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2739 2740 enum mlxsw_reg_pemrbt_protocol { 2741 MLXSW_REG_PEMRBT_PROTO_IPV4, 2742 MLXSW_REG_PEMRBT_PROTO_IPV6, 2743 }; 2744 2745 /* reg_pemrbt_protocol 2746 * Access: Index 2747 */ 2748 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2749 2750 /* reg_pemrbt_group_id 2751 * ACL group identifier. 2752 * Range 0..cap_max_acl_groups-1 2753 * Access: RW 2754 */ 2755 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2756 2757 static inline void 2758 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2759 u16 group_id) 2760 { 2761 MLXSW_REG_ZERO(pemrbt, payload); 2762 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2763 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2764 } 2765 2766 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2767 * ----------------------------------------------------- 2768 * This register is used for accessing rules within a TCAM region. 2769 * It is a new version of PTCE in order to support wider key, 2770 * mask and action within a TCAM region. This register is not supported 2771 * by SwitchX and SwitchX-2. 2772 */ 2773 #define MLXSW_REG_PTCE2_ID 0x3017 2774 #define MLXSW_REG_PTCE2_LEN 0x1D8 2775 2776 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2777 2778 /* reg_ptce2_v 2779 * Valid. 2780 * Access: RW 2781 */ 2782 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2783 2784 /* reg_ptce2_a 2785 * Activity. Set if a packet lookup has hit on the specific entry. 2786 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2787 * Access: RO 2788 */ 2789 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2790 2791 enum mlxsw_reg_ptce2_op { 2792 /* Read operation. */ 2793 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2794 /* clear on read operation. Used to read entry 2795 * and clear Activity bit. 2796 */ 2797 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2798 /* Write operation. Used to write a new entry to the table. 2799 * All R/W fields are relevant for new entry. Activity bit is set 2800 * for new entries - Note write with v = 0 will delete the entry. 2801 */ 2802 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2803 /* Update action. Only action set will be updated. */ 2804 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2805 /* Clear activity. A bit is cleared for the entry. */ 2806 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2807 }; 2808 2809 /* reg_ptce2_op 2810 * Access: OP 2811 */ 2812 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2813 2814 /* reg_ptce2_offset 2815 * Access: Index 2816 */ 2817 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2818 2819 /* reg_ptce2_priority 2820 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2821 * Note: priority does not have to be unique per rule. 2822 * Within a region, higher priority should have lower offset (no limitation 2823 * between regions in a multi-region). 2824 * Access: RW 2825 */ 2826 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2827 2828 /* reg_ptce2_tcam_region_info 2829 * Opaque object that represents the TCAM region. 2830 * Access: Index 2831 */ 2832 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2833 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2834 2835 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2836 2837 /* reg_ptce2_flex_key_blocks 2838 * ACL Key. 2839 * Access: RW 2840 */ 2841 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2842 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2843 2844 /* reg_ptce2_mask 2845 * mask- in the same size as key. A bit that is set directs the TCAM 2846 * to compare the corresponding bit in key. A bit that is clear directs 2847 * the TCAM to ignore the corresponding bit in key. 2848 * Access: RW 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2851 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2852 2853 /* reg_ptce2_flex_action_set 2854 * ACL action set. 2855 * Access: RW 2856 */ 2857 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2858 MLXSW_REG_FLEX_ACTION_SET_LEN); 2859 2860 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2861 enum mlxsw_reg_ptce2_op op, 2862 const char *tcam_region_info, 2863 u16 offset, u32 priority) 2864 { 2865 MLXSW_REG_ZERO(ptce2, payload); 2866 mlxsw_reg_ptce2_v_set(payload, valid); 2867 mlxsw_reg_ptce2_op_set(payload, op); 2868 mlxsw_reg_ptce2_offset_set(payload, offset); 2869 mlxsw_reg_ptce2_priority_set(payload, priority); 2870 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2871 } 2872 2873 /* PERPT - Policy-Engine ERP Table Register 2874 * ---------------------------------------- 2875 * This register adds and removes eRPs from the eRP table. 2876 */ 2877 #define MLXSW_REG_PERPT_ID 0x3021 2878 #define MLXSW_REG_PERPT_LEN 0x80 2879 2880 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2881 2882 /* reg_perpt_erpt_bank 2883 * eRP table bank. 2884 * Range 0 .. cap_max_erp_table_banks - 1 2885 * Access: Index 2886 */ 2887 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2888 2889 /* reg_perpt_erpt_index 2890 * Index to eRP table within the eRP bank. 2891 * Range is 0 .. cap_max_erp_table_bank_size - 1 2892 * Access: Index 2893 */ 2894 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2895 2896 enum mlxsw_reg_perpt_key_size { 2897 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2898 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2899 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2900 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2901 }; 2902 2903 /* reg_perpt_key_size 2904 * Access: OP 2905 */ 2906 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2907 2908 /* reg_perpt_bf_bypass 2909 * 0 - The eRP is used only if bloom filter state is set for the given 2910 * rule. 2911 * 1 - The eRP is used regardless of bloom filter state. 2912 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2913 * Access: RW 2914 */ 2915 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2916 2917 /* reg_perpt_erp_id 2918 * eRP ID for use by the rules. 2919 * Access: RW 2920 */ 2921 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2922 2923 /* reg_perpt_erpt_base_bank 2924 * Base eRP table bank, points to head of erp_vector 2925 * Range is 0 .. cap_max_erp_table_banks - 1 2926 * Access: OP 2927 */ 2928 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2929 2930 /* reg_perpt_erpt_base_index 2931 * Base index to eRP table within the eRP bank 2932 * Range is 0 .. cap_max_erp_table_bank_size - 1 2933 * Access: OP 2934 */ 2935 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2936 2937 /* reg_perpt_erp_index_in_vector 2938 * eRP index in the vector. 2939 * Access: OP 2940 */ 2941 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2942 2943 /* reg_perpt_erp_vector 2944 * eRP vector. 2945 * Access: OP 2946 */ 2947 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2948 2949 /* reg_perpt_mask 2950 * Mask 2951 * 0 - A-TCAM will ignore the bit in key 2952 * 1 - A-TCAM will compare the bit in key 2953 * Access: RW 2954 */ 2955 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2956 2957 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2958 unsigned long *erp_vector, 2959 unsigned long size) 2960 { 2961 unsigned long bit; 2962 2963 for_each_set_bit(bit, erp_vector, size) 2964 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2965 } 2966 2967 static inline void 2968 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2969 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2970 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2971 char *mask) 2972 { 2973 MLXSW_REG_ZERO(perpt, payload); 2974 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2975 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2976 mlxsw_reg_perpt_key_size_set(payload, key_size); 2977 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2978 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2979 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2980 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2981 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2982 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2983 } 2984 2985 /* PERAR - Policy-Engine Region Association Register 2986 * ------------------------------------------------- 2987 * This register associates a hw region for region_id's. Changing on the fly 2988 * is supported by the device. 2989 */ 2990 #define MLXSW_REG_PERAR_ID 0x3026 2991 #define MLXSW_REG_PERAR_LEN 0x08 2992 2993 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2994 2995 /* reg_perar_region_id 2996 * Region identifier 2997 * Range 0 .. cap_max_regions-1 2998 * Access: Index 2999 */ 3000 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3001 3002 static inline unsigned int 3003 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3004 { 3005 return DIV_ROUND_UP(block_num, 4); 3006 } 3007 3008 /* reg_perar_hw_region 3009 * HW Region 3010 * Range 0 .. cap_max_regions-1 3011 * Default: hw_region = region_id 3012 * For a 8 key block region, 2 consecutive regions are used 3013 * For a 12 key block region, 3 consecutive regions are used 3014 * Access: RW 3015 */ 3016 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3017 3018 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3019 u16 hw_region) 3020 { 3021 MLXSW_REG_ZERO(perar, payload); 3022 mlxsw_reg_perar_region_id_set(payload, region_id); 3023 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3024 } 3025 3026 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3027 * ----------------------------------------------------- 3028 * This register is a new version of PTCE-V2 in order to support the 3029 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3030 */ 3031 #define MLXSW_REG_PTCE3_ID 0x3027 3032 #define MLXSW_REG_PTCE3_LEN 0xF0 3033 3034 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3035 3036 /* reg_ptce3_v 3037 * Valid. 3038 * Access: RW 3039 */ 3040 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3041 3042 enum mlxsw_reg_ptce3_op { 3043 /* Write operation. Used to write a new entry to the table. 3044 * All R/W fields are relevant for new entry. Activity bit is set 3045 * for new entries. Write with v = 0 will delete the entry. Must 3046 * not be used if an entry exists. 3047 */ 3048 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3049 /* Update operation */ 3050 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3051 /* Read operation */ 3052 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3053 }; 3054 3055 /* reg_ptce3_op 3056 * Access: OP 3057 */ 3058 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3059 3060 /* reg_ptce3_priority 3061 * Priority of the rule. Higher values win. 3062 * For Spectrum-2 range is 1..cap_kvd_size - 1 3063 * Note: Priority does not have to be unique per rule. 3064 * Access: RW 3065 */ 3066 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3067 3068 /* reg_ptce3_tcam_region_info 3069 * Opaque object that represents the TCAM region. 3070 * Access: Index 3071 */ 3072 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3073 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3074 3075 /* reg_ptce3_flex2_key_blocks 3076 * ACL key. The key must be masked according to eRP (if exists) or 3077 * according to master mask. 3078 * Access: Index 3079 */ 3080 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3081 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3082 3083 /* reg_ptce3_erp_id 3084 * eRP ID. 3085 * Access: Index 3086 */ 3087 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3088 3089 /* reg_ptce3_delta_start 3090 * Start point of delta_value and delta_mask, in bits. Must not exceed 3091 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3092 * Access: Index 3093 */ 3094 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3095 3096 /* reg_ptce3_delta_mask 3097 * Delta mask. 3098 * 0 - Ignore relevant bit in delta_value 3099 * 1 - Compare relevant bit in delta_value 3100 * Delta mask must not be set for reserved fields in the key blocks. 3101 * Note: No delta when no eRPs. Thus, for regions with 3102 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3103 * Access: Index 3104 */ 3105 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3106 3107 /* reg_ptce3_delta_value 3108 * Delta value. 3109 * Bits which are masked by delta_mask must be 0. 3110 * Access: Index 3111 */ 3112 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3113 3114 /* reg_ptce3_prune_vector 3115 * Pruning vector relative to the PERPT.erp_id. 3116 * Used for reducing lookups. 3117 * 0 - NEED: Do a lookup using the eRP. 3118 * 1 - PRUNE: Do not perform a lookup using the eRP. 3119 * Maybe be modified by PEAPBL and PEAPBM. 3120 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3121 * all 1's or all 0's. 3122 * Access: RW 3123 */ 3124 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3125 3126 /* reg_ptce3_prune_ctcam 3127 * Pruning on C-TCAM. Used for reducing lookups. 3128 * 0 - NEED: Do a lookup in the C-TCAM. 3129 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3130 * Access: RW 3131 */ 3132 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3133 3134 /* reg_ptce3_large_exists 3135 * Large entry key ID exists. 3136 * Within the region: 3137 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3138 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3139 * For rule delete: The MSB of the key will be removed. 3140 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3141 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3142 * For rule delete: The MSB of the key will not be removed. 3143 * Access: WO 3144 */ 3145 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3146 3147 /* reg_ptce3_large_entry_key_id 3148 * Large entry key ID. 3149 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3150 * blocks. Must be different for different keys which have the same common 3151 * 6 key blocks (MSB, blocks 6..11) key within a region. 3152 * Range is 0..cap_max_pe_large_key_id - 1 3153 * Access: RW 3154 */ 3155 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3156 3157 /* reg_ptce3_action_pointer 3158 * Pointer to action. 3159 * Range is 0..cap_max_kvd_action_sets - 1 3160 * Access: RW 3161 */ 3162 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3163 3164 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3165 enum mlxsw_reg_ptce3_op op, 3166 u32 priority, 3167 const char *tcam_region_info, 3168 const char *key, u8 erp_id, 3169 u16 delta_start, u8 delta_mask, 3170 u8 delta_value, bool large_exists, 3171 u32 lkey_id, u32 action_pointer) 3172 { 3173 MLXSW_REG_ZERO(ptce3, payload); 3174 mlxsw_reg_ptce3_v_set(payload, valid); 3175 mlxsw_reg_ptce3_op_set(payload, op); 3176 mlxsw_reg_ptce3_priority_set(payload, priority); 3177 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3178 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3179 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3180 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3181 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3182 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3183 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3184 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3185 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3186 } 3187 3188 /* PERCR - Policy-Engine Region Configuration Register 3189 * --------------------------------------------------- 3190 * This register configures the region parameters. The region_id must be 3191 * allocated. 3192 */ 3193 #define MLXSW_REG_PERCR_ID 0x302A 3194 #define MLXSW_REG_PERCR_LEN 0x80 3195 3196 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3197 3198 /* reg_percr_region_id 3199 * Region identifier. 3200 * Range 0..cap_max_regions-1 3201 * Access: Index 3202 */ 3203 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3204 3205 /* reg_percr_atcam_ignore_prune 3206 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3207 * Access: RW 3208 */ 3209 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3210 3211 /* reg_percr_ctcam_ignore_prune 3212 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3213 * Access: RW 3214 */ 3215 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3216 3217 /* reg_percr_bf_bypass 3218 * Bloom filter bypass. 3219 * 0 - Bloom filter is used (default) 3220 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3221 * region_id or eRP. See PERPT.bf_bypass 3222 * Access: RW 3223 */ 3224 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3225 3226 /* reg_percr_master_mask 3227 * Master mask. Logical OR mask of all masks of all rules of a region 3228 * (both A-TCAM and C-TCAM). When there are no eRPs 3229 * (erpt_pointer_valid = 0), then this provides the mask. 3230 * Access: RW 3231 */ 3232 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3233 3234 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3235 { 3236 MLXSW_REG_ZERO(percr, payload); 3237 mlxsw_reg_percr_region_id_set(payload, region_id); 3238 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3239 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3240 mlxsw_reg_percr_bf_bypass_set(payload, false); 3241 } 3242 3243 /* PERERP - Policy-Engine Region eRP Register 3244 * ------------------------------------------ 3245 * This register configures the region eRP. The region_id must be 3246 * allocated. 3247 */ 3248 #define MLXSW_REG_PERERP_ID 0x302B 3249 #define MLXSW_REG_PERERP_LEN 0x1C 3250 3251 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3252 3253 /* reg_pererp_region_id 3254 * Region identifier. 3255 * Range 0..cap_max_regions-1 3256 * Access: Index 3257 */ 3258 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3259 3260 /* reg_pererp_ctcam_le 3261 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3262 * Access: RW 3263 */ 3264 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3265 3266 /* reg_pererp_erpt_pointer_valid 3267 * erpt_pointer is valid. 3268 * Access: RW 3269 */ 3270 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3271 3272 /* reg_pererp_erpt_bank_pointer 3273 * Pointer to eRP table bank. May be modified at any time. 3274 * Range 0..cap_max_erp_table_banks-1 3275 * Reserved when erpt_pointer_valid = 0 3276 */ 3277 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3278 3279 /* reg_pererp_erpt_pointer 3280 * Pointer to eRP table within the eRP bank. Can be changed for an 3281 * existing region. 3282 * Range 0..cap_max_erp_table_size-1 3283 * Reserved when erpt_pointer_valid = 0 3284 * Access: RW 3285 */ 3286 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3287 3288 /* reg_pererp_erpt_vector 3289 * Vector of allowed eRP indexes starting from erpt_pointer within the 3290 * erpt_bank_pointer. Next entries will be in next bank. 3291 * Note that eRP index is used and not eRP ID. 3292 * Reserved when erpt_pointer_valid = 0 3293 * Access: RW 3294 */ 3295 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3296 3297 /* reg_pererp_master_rp_id 3298 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3299 * for the lookup. Can be changed for an existing region. 3300 * Reserved when erpt_pointer_valid = 1 3301 * Access: RW 3302 */ 3303 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3304 3305 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3306 unsigned long *erp_vector, 3307 unsigned long size) 3308 { 3309 unsigned long bit; 3310 3311 for_each_set_bit(bit, erp_vector, size) 3312 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3313 } 3314 3315 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3316 bool ctcam_le, bool erpt_pointer_valid, 3317 u8 erpt_bank_pointer, u8 erpt_pointer, 3318 u8 master_rp_id) 3319 { 3320 MLXSW_REG_ZERO(pererp, payload); 3321 mlxsw_reg_pererp_region_id_set(payload, region_id); 3322 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3323 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3324 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3325 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3326 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3327 } 3328 3329 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3330 * ---------------------------------------------------------------- 3331 * This register configures the Bloom filter entries. 3332 */ 3333 #define MLXSW_REG_PEABFE_ID 0x3022 3334 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3335 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3336 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3337 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3338 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3339 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3340 3341 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3342 3343 /* reg_peabfe_size 3344 * Number of BF entries to be updated. 3345 * Range 1..256 3346 * Access: Op 3347 */ 3348 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3349 3350 /* reg_peabfe_bf_entry_state 3351 * Bloom filter state 3352 * 0 - Clear 3353 * 1 - Set 3354 * Access: RW 3355 */ 3356 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3357 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3358 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3359 3360 /* reg_peabfe_bf_entry_bank 3361 * Bloom filter bank ID 3362 * Range 0..cap_max_erp_table_banks-1 3363 * Access: Index 3364 */ 3365 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3366 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3367 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3368 3369 /* reg_peabfe_bf_entry_index 3370 * Bloom filter entry index 3371 * Range 0..2^cap_max_bf_log-1 3372 * Access: Index 3373 */ 3374 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3375 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3376 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3377 3378 static inline void mlxsw_reg_peabfe_pack(char *payload) 3379 { 3380 MLXSW_REG_ZERO(peabfe, payload); 3381 } 3382 3383 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3384 u8 state, u8 bank, u32 bf_index) 3385 { 3386 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3387 3388 if (rec_index >= num_rec) 3389 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3390 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3391 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3392 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3393 } 3394 3395 /* IEDR - Infrastructure Entry Delete Register 3396 * ---------------------------------------------------- 3397 * This register is used for deleting entries from the entry tables. 3398 * It is legitimate to attempt to delete a nonexisting entry (the device will 3399 * respond as a good flow). 3400 */ 3401 #define MLXSW_REG_IEDR_ID 0x3804 3402 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3403 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3404 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3405 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3406 MLXSW_REG_IEDR_REC_LEN * \ 3407 MLXSW_REG_IEDR_REC_MAX_COUNT) 3408 3409 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3410 3411 /* reg_iedr_num_rec 3412 * Number of records. 3413 * Access: OP 3414 */ 3415 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3416 3417 /* reg_iedr_rec_type 3418 * Resource type. 3419 * Access: OP 3420 */ 3421 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3422 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3423 3424 /* reg_iedr_rec_size 3425 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3426 * Access: OP 3427 */ 3428 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3429 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3430 3431 /* reg_iedr_rec_index_start 3432 * Resource index start. 3433 * Access: OP 3434 */ 3435 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3436 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3437 3438 static inline void mlxsw_reg_iedr_pack(char *payload) 3439 { 3440 MLXSW_REG_ZERO(iedr, payload); 3441 } 3442 3443 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3444 u8 rec_type, u16 rec_size, 3445 u32 rec_index_start) 3446 { 3447 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3448 3449 if (rec_index >= num_rec) 3450 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3451 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3452 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3453 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3454 } 3455 3456 /* QPTS - QoS Priority Trust State Register 3457 * ---------------------------------------- 3458 * This register controls the port policy to calculate the switch priority and 3459 * packet color based on incoming packet fields. 3460 */ 3461 #define MLXSW_REG_QPTS_ID 0x4002 3462 #define MLXSW_REG_QPTS_LEN 0x8 3463 3464 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3465 3466 /* reg_qpts_local_port 3467 * Local port number. 3468 * Access: Index 3469 * 3470 * Note: CPU port is supported. 3471 */ 3472 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3473 3474 enum mlxsw_reg_qpts_trust_state { 3475 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3476 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3477 }; 3478 3479 /* reg_qpts_trust_state 3480 * Trust state for a given port. 3481 * Access: RW 3482 */ 3483 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3484 3485 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3486 enum mlxsw_reg_qpts_trust_state ts) 3487 { 3488 MLXSW_REG_ZERO(qpts, payload); 3489 3490 mlxsw_reg_qpts_local_port_set(payload, local_port); 3491 mlxsw_reg_qpts_trust_state_set(payload, ts); 3492 } 3493 3494 /* QPCR - QoS Policer Configuration Register 3495 * ----------------------------------------- 3496 * The QPCR register is used to create policers - that limit 3497 * the rate of bytes or packets via some trap group. 3498 */ 3499 #define MLXSW_REG_QPCR_ID 0x4004 3500 #define MLXSW_REG_QPCR_LEN 0x28 3501 3502 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3503 3504 enum mlxsw_reg_qpcr_g { 3505 MLXSW_REG_QPCR_G_GLOBAL = 2, 3506 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3507 }; 3508 3509 /* reg_qpcr_g 3510 * The policer type. 3511 * Access: Index 3512 */ 3513 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3514 3515 /* reg_qpcr_pid 3516 * Policer ID. 3517 * Access: Index 3518 */ 3519 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3520 3521 /* reg_qpcr_clear_counter 3522 * Clear counters. 3523 * Access: OP 3524 */ 3525 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3526 3527 /* reg_qpcr_color_aware 3528 * Is the policer aware of colors. 3529 * Must be 0 (unaware) for cpu port. 3530 * Access: RW for unbounded policer. RO for bounded policer. 3531 */ 3532 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3533 3534 /* reg_qpcr_bytes 3535 * Is policer limit is for bytes per sec or packets per sec. 3536 * 0 - packets 3537 * 1 - bytes 3538 * Access: RW for unbounded policer. RO for bounded policer. 3539 */ 3540 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3541 3542 enum mlxsw_reg_qpcr_ir_units { 3543 MLXSW_REG_QPCR_IR_UNITS_M, 3544 MLXSW_REG_QPCR_IR_UNITS_K, 3545 }; 3546 3547 /* reg_qpcr_ir_units 3548 * Policer's units for cir and eir fields (for bytes limits only) 3549 * 1 - 10^3 3550 * 0 - 10^6 3551 * Access: OP 3552 */ 3553 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3554 3555 enum mlxsw_reg_qpcr_rate_type { 3556 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3557 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3558 }; 3559 3560 /* reg_qpcr_rate_type 3561 * Policer can have one limit (single rate) or 2 limits with specific operation 3562 * for packets that exceed the lower rate but not the upper one. 3563 * (For cpu port must be single rate) 3564 * Access: RW for unbounded policer. RO for bounded policer. 3565 */ 3566 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3567 3568 /* reg_qpc_cbs 3569 * Policer's committed burst size. 3570 * The policer is working with time slices of 50 nano sec. By default every 3571 * slice is granted the proportionate share of the committed rate. If we want to 3572 * allow a slice to exceed that share (while still keeping the rate per sec) we 3573 * can allow burst. The burst size is between the default proportionate share 3574 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3575 * committed rate will result in exceeding the rate). The burst size must be a 3576 * log of 2 and will be determined by 2^cbs. 3577 * Access: RW 3578 */ 3579 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3580 3581 /* reg_qpcr_cir 3582 * Policer's committed rate. 3583 * The rate used for sungle rate, the lower rate for double rate. 3584 * For bytes limits, the rate will be this value * the unit from ir_units. 3585 * (Resolution error is up to 1%). 3586 * Access: RW 3587 */ 3588 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3589 3590 /* reg_qpcr_eir 3591 * Policer's exceed rate. 3592 * The higher rate for double rate, reserved for single rate. 3593 * Lower rate for double rate policer. 3594 * For bytes limits, the rate will be this value * the unit from ir_units. 3595 * (Resolution error is up to 1%). 3596 * Access: RW 3597 */ 3598 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3599 3600 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3601 3602 /* reg_qpcr_exceed_action. 3603 * What to do with packets between the 2 limits for double rate. 3604 * Access: RW for unbounded policer. RO for bounded policer. 3605 */ 3606 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3607 3608 enum mlxsw_reg_qpcr_action { 3609 /* Discard */ 3610 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3611 /* Forward and set color to red. 3612 * If the packet is intended to cpu port, it will be dropped. 3613 */ 3614 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3615 }; 3616 3617 /* reg_qpcr_violate_action 3618 * What to do with packets that cross the cir limit (for single rate) or the eir 3619 * limit (for double rate). 3620 * Access: RW for unbounded policer. RO for bounded policer. 3621 */ 3622 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3623 3624 /* reg_qpcr_violate_count 3625 * Counts the number of times violate_action happened on this PID. 3626 * Access: RW 3627 */ 3628 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3629 3630 /* Packets */ 3631 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3632 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3633 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3634 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3635 3636 /* Bandwidth */ 3637 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3638 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3639 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3640 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3641 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3642 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3643 3644 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3645 enum mlxsw_reg_qpcr_ir_units ir_units, 3646 bool bytes, u32 cir, u16 cbs) 3647 { 3648 MLXSW_REG_ZERO(qpcr, payload); 3649 mlxsw_reg_qpcr_pid_set(payload, pid); 3650 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3651 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3652 mlxsw_reg_qpcr_violate_action_set(payload, 3653 MLXSW_REG_QPCR_ACTION_DISCARD); 3654 mlxsw_reg_qpcr_cir_set(payload, cir); 3655 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3656 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3657 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3658 } 3659 3660 /* QTCT - QoS Switch Traffic Class Table 3661 * ------------------------------------- 3662 * Configures the mapping between the packet switch priority and the 3663 * traffic class on the transmit port. 3664 */ 3665 #define MLXSW_REG_QTCT_ID 0x400A 3666 #define MLXSW_REG_QTCT_LEN 0x08 3667 3668 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3669 3670 /* reg_qtct_local_port 3671 * Local port number. 3672 * Access: Index 3673 * 3674 * Note: CPU port is not supported. 3675 */ 3676 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3677 3678 /* reg_qtct_sub_port 3679 * Virtual port within the physical port. 3680 * Should be set to 0 when virtual ports are not enabled on the port. 3681 * Access: Index 3682 */ 3683 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3684 3685 /* reg_qtct_switch_prio 3686 * Switch priority. 3687 * Access: Index 3688 */ 3689 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3690 3691 /* reg_qtct_tclass 3692 * Traffic class. 3693 * Default values: 3694 * switch_prio 0 : tclass 1 3695 * switch_prio 1 : tclass 0 3696 * switch_prio i : tclass i, for i > 1 3697 * Access: RW 3698 */ 3699 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3700 3701 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3702 u8 switch_prio, u8 tclass) 3703 { 3704 MLXSW_REG_ZERO(qtct, payload); 3705 mlxsw_reg_qtct_local_port_set(payload, local_port); 3706 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3707 mlxsw_reg_qtct_tclass_set(payload, tclass); 3708 } 3709 3710 /* QEEC - QoS ETS Element Configuration Register 3711 * --------------------------------------------- 3712 * Configures the ETS elements. 3713 */ 3714 #define MLXSW_REG_QEEC_ID 0x400D 3715 #define MLXSW_REG_QEEC_LEN 0x20 3716 3717 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3718 3719 /* reg_qeec_local_port 3720 * Local port number. 3721 * Access: Index 3722 * 3723 * Note: CPU port is supported. 3724 */ 3725 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3726 3727 enum mlxsw_reg_qeec_hr { 3728 MLXSW_REG_QEEC_HR_PORT, 3729 MLXSW_REG_QEEC_HR_GROUP, 3730 MLXSW_REG_QEEC_HR_SUBGROUP, 3731 MLXSW_REG_QEEC_HR_TC, 3732 }; 3733 3734 /* reg_qeec_element_hierarchy 3735 * 0 - Port 3736 * 1 - Group 3737 * 2 - Subgroup 3738 * 3 - Traffic Class 3739 * Access: Index 3740 */ 3741 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3742 3743 /* reg_qeec_element_index 3744 * The index of the element in the hierarchy. 3745 * Access: Index 3746 */ 3747 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3748 3749 /* reg_qeec_next_element_index 3750 * The index of the next (lower) element in the hierarchy. 3751 * Access: RW 3752 * 3753 * Note: Reserved for element_hierarchy 0. 3754 */ 3755 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3756 3757 /* reg_qeec_mise 3758 * Min shaper configuration enable. Enables configuration of the min 3759 * shaper on this ETS element 3760 * 0 - Disable 3761 * 1 - Enable 3762 * Access: RW 3763 */ 3764 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3765 3766 /* reg_qeec_ptps 3767 * PTP shaper 3768 * 0: regular shaper mode 3769 * 1: PTP oriented shaper 3770 * Allowed only for hierarchy 0 3771 * Not supported for CPU port 3772 * Note that ptps mode may affect the shaper rates of all hierarchies 3773 * Supported only on Spectrum-1 3774 * Access: RW 3775 */ 3776 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3777 3778 enum { 3779 MLXSW_REG_QEEC_BYTES_MODE, 3780 MLXSW_REG_QEEC_PACKETS_MODE, 3781 }; 3782 3783 /* reg_qeec_pb 3784 * Packets or bytes mode. 3785 * 0 - Bytes mode 3786 * 1 - Packets mode 3787 * Access: RW 3788 * 3789 * Note: Used for max shaper configuration. For Spectrum, packets mode 3790 * is supported only for traffic classes of CPU port. 3791 */ 3792 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3793 3794 /* The smallest permitted min shaper rate. */ 3795 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3796 3797 /* reg_qeec_min_shaper_rate 3798 * Min shaper information rate. 3799 * For CPU port, can only be configured for port hierarchy. 3800 * When in bytes mode, value is specified in units of 1000bps. 3801 * Access: RW 3802 */ 3803 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3804 3805 /* reg_qeec_mase 3806 * Max shaper configuration enable. Enables configuration of the max 3807 * shaper on this ETS element. 3808 * 0 - Disable 3809 * 1 - Enable 3810 * Access: RW 3811 */ 3812 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3813 3814 /* The largest max shaper value possible to disable the shaper. */ 3815 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3816 3817 /* reg_qeec_max_shaper_rate 3818 * Max shaper information rate. 3819 * For CPU port, can only be configured for port hierarchy. 3820 * When in bytes mode, value is specified in units of 1000bps. 3821 * Access: RW 3822 */ 3823 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3824 3825 /* reg_qeec_de 3826 * DWRR configuration enable. Enables configuration of the dwrr and 3827 * dwrr_weight. 3828 * 0 - Disable 3829 * 1 - Enable 3830 * Access: RW 3831 */ 3832 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3833 3834 /* reg_qeec_dwrr 3835 * Transmission selection algorithm to use on the link going down from 3836 * the ETS element. 3837 * 0 - Strict priority 3838 * 1 - DWRR 3839 * Access: RW 3840 */ 3841 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3842 3843 /* reg_qeec_dwrr_weight 3844 * DWRR weight on the link going down from the ETS element. The 3845 * percentage of bandwidth guaranteed to an ETS element within 3846 * its hierarchy. The sum of all weights across all ETS elements 3847 * within one hierarchy should be equal to 100. Reserved when 3848 * transmission selection algorithm is strict priority. 3849 * Access: RW 3850 */ 3851 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3852 3853 /* reg_qeec_max_shaper_bs 3854 * Max shaper burst size 3855 * Burst size is 2^max_shaper_bs * 512 bits 3856 * For Spectrum-1: Range is: 5..25 3857 * For Spectrum-2: Range is: 11..25 3858 * Reserved when ptps = 1 3859 * Access: RW 3860 */ 3861 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3862 3863 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3864 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3865 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3866 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 5 3867 3868 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3869 enum mlxsw_reg_qeec_hr hr, u8 index, 3870 u8 next_index) 3871 { 3872 MLXSW_REG_ZERO(qeec, payload); 3873 mlxsw_reg_qeec_local_port_set(payload, local_port); 3874 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3875 mlxsw_reg_qeec_element_index_set(payload, index); 3876 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3877 } 3878 3879 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3880 bool ptps) 3881 { 3882 MLXSW_REG_ZERO(qeec, payload); 3883 mlxsw_reg_qeec_local_port_set(payload, local_port); 3884 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3885 mlxsw_reg_qeec_ptps_set(payload, ptps); 3886 } 3887 3888 /* QRWE - QoS ReWrite Enable 3889 * ------------------------- 3890 * This register configures the rewrite enable per receive port. 3891 */ 3892 #define MLXSW_REG_QRWE_ID 0x400F 3893 #define MLXSW_REG_QRWE_LEN 0x08 3894 3895 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3896 3897 /* reg_qrwe_local_port 3898 * Local port number. 3899 * Access: Index 3900 * 3901 * Note: CPU port is supported. No support for router port. 3902 */ 3903 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3904 3905 /* reg_qrwe_dscp 3906 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3907 * Access: RW 3908 */ 3909 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3910 3911 /* reg_qrwe_pcp 3912 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3913 * Access: RW 3914 */ 3915 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3916 3917 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3918 bool rewrite_pcp, bool rewrite_dscp) 3919 { 3920 MLXSW_REG_ZERO(qrwe, payload); 3921 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3922 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3923 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3924 } 3925 3926 /* QPDSM - QoS Priority to DSCP Mapping 3927 * ------------------------------------ 3928 * QoS Priority to DSCP Mapping Register 3929 */ 3930 #define MLXSW_REG_QPDSM_ID 0x4011 3931 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3932 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3933 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3934 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3935 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3936 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3937 3938 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3939 3940 /* reg_qpdsm_local_port 3941 * Local Port. Supported for data packets from CPU port. 3942 * Access: Index 3943 */ 3944 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3945 3946 /* reg_qpdsm_prio_entry_color0_e 3947 * Enable update of the entry for color 0 and a given port. 3948 * Access: WO 3949 */ 3950 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3951 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3952 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3953 3954 /* reg_qpdsm_prio_entry_color0_dscp 3955 * DSCP field in the outer label of the packet for color 0 and a given port. 3956 * Reserved when e=0. 3957 * Access: RW 3958 */ 3959 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3960 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3961 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3962 3963 /* reg_qpdsm_prio_entry_color1_e 3964 * Enable update of the entry for color 1 and a given port. 3965 * Access: WO 3966 */ 3967 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3968 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3969 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3970 3971 /* reg_qpdsm_prio_entry_color1_dscp 3972 * DSCP field in the outer label of the packet for color 1 and a given port. 3973 * Reserved when e=0. 3974 * Access: RW 3975 */ 3976 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3977 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3978 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3979 3980 /* reg_qpdsm_prio_entry_color2_e 3981 * Enable update of the entry for color 2 and a given port. 3982 * Access: WO 3983 */ 3984 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3985 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3986 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3987 3988 /* reg_qpdsm_prio_entry_color2_dscp 3989 * DSCP field in the outer label of the packet for color 2 and a given port. 3990 * Reserved when e=0. 3991 * Access: RW 3992 */ 3993 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3994 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3995 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3996 3997 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3998 { 3999 MLXSW_REG_ZERO(qpdsm, payload); 4000 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4001 } 4002 4003 static inline void 4004 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4005 { 4006 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4007 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4008 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4009 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4010 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4011 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4012 } 4013 4014 /* QPDP - QoS Port DSCP to Priority Mapping Register 4015 * ------------------------------------------------- 4016 * This register controls the port default Switch Priority and Color. The 4017 * default Switch Priority and Color are used for frames where the trust state 4018 * uses default values. All member ports of a LAG should be configured with the 4019 * same default values. 4020 */ 4021 #define MLXSW_REG_QPDP_ID 0x4007 4022 #define MLXSW_REG_QPDP_LEN 0x8 4023 4024 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4025 4026 /* reg_qpdp_local_port 4027 * Local Port. Supported for data packets from CPU port. 4028 * Access: Index 4029 */ 4030 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 4031 4032 /* reg_qpdp_switch_prio 4033 * Default port Switch Priority (default 0) 4034 * Access: RW 4035 */ 4036 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4037 4038 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 4039 u8 switch_prio) 4040 { 4041 MLXSW_REG_ZERO(qpdp, payload); 4042 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4043 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4044 } 4045 4046 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4047 * -------------------------------------------------- 4048 * This register controls the mapping from DSCP field to 4049 * Switch Priority for IP packets. 4050 */ 4051 #define MLXSW_REG_QPDPM_ID 0x4013 4052 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4053 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4054 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4055 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4056 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4057 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4058 4059 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4060 4061 /* reg_qpdpm_local_port 4062 * Local Port. Supported for data packets from CPU port. 4063 * Access: Index 4064 */ 4065 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 4066 4067 /* reg_qpdpm_dscp_e 4068 * Enable update of the specific entry. When cleared, the switch_prio and color 4069 * fields are ignored and the previous switch_prio and color values are 4070 * preserved. 4071 * Access: WO 4072 */ 4073 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4074 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4075 4076 /* reg_qpdpm_dscp_prio 4077 * The new Switch Priority value for the relevant DSCP value. 4078 * Access: RW 4079 */ 4080 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4081 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4082 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4083 4084 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 4085 { 4086 MLXSW_REG_ZERO(qpdpm, payload); 4087 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4088 } 4089 4090 static inline void 4091 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4092 { 4093 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4094 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4095 } 4096 4097 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4098 * ------------------------------------------------------------------ 4099 * This register configures if the Switch Priority to Traffic Class mapping is 4100 * based on Multicast packet indication. If so, then multicast packets will get 4101 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4102 * QTCT. 4103 * By default, Switch Priority to Traffic Class mapping is not based on 4104 * Multicast packet indication. 4105 */ 4106 #define MLXSW_REG_QTCTM_ID 0x401A 4107 #define MLXSW_REG_QTCTM_LEN 0x08 4108 4109 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4110 4111 /* reg_qtctm_local_port 4112 * Local port number. 4113 * No support for CPU port. 4114 * Access: Index 4115 */ 4116 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 4117 4118 /* reg_qtctm_mc 4119 * Multicast Mode 4120 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4121 * indication (default is 0, not based on Multicast packet indication). 4122 */ 4123 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4124 4125 static inline void 4126 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 4127 { 4128 MLXSW_REG_ZERO(qtctm, payload); 4129 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4130 mlxsw_reg_qtctm_mc_set(payload, mc); 4131 } 4132 4133 /* QPSC - QoS PTP Shaper Configuration Register 4134 * -------------------------------------------- 4135 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4136 * Supported only on Spectrum-1. 4137 */ 4138 #define MLXSW_REG_QPSC_ID 0x401B 4139 #define MLXSW_REG_QPSC_LEN 0x28 4140 4141 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4142 4143 enum mlxsw_reg_qpsc_port_speed { 4144 MLXSW_REG_QPSC_PORT_SPEED_100M, 4145 MLXSW_REG_QPSC_PORT_SPEED_1G, 4146 MLXSW_REG_QPSC_PORT_SPEED_10G, 4147 MLXSW_REG_QPSC_PORT_SPEED_25G, 4148 }; 4149 4150 /* reg_qpsc_port_speed 4151 * Port speed. 4152 * Access: Index 4153 */ 4154 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4155 4156 /* reg_qpsc_shaper_time_exp 4157 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4158 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4159 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4160 * Access: RW 4161 */ 4162 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4163 4164 /* reg_qpsc_shaper_time_mantissa 4165 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4166 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4167 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4168 * Access: RW 4169 */ 4170 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4171 4172 /* reg_qpsc_shaper_inc 4173 * Number of tokens added to shaper on each update. 4174 * Units of 8B. 4175 * Access: RW 4176 */ 4177 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4178 4179 /* reg_qpsc_shaper_bs 4180 * Max shaper Burst size. 4181 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4182 * Range is: 5..25 (from 2KB..2GB) 4183 * Access: RW 4184 */ 4185 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4186 4187 /* reg_qpsc_ptsc_we 4188 * Write enable to port_to_shaper_credits. 4189 * Access: WO 4190 */ 4191 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4192 4193 /* reg_qpsc_port_to_shaper_credits 4194 * For split ports: range 1..57 4195 * For non-split ports: range 1..112 4196 * Written only when ptsc_we is set. 4197 * Access: RW 4198 */ 4199 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4200 4201 /* reg_qpsc_ing_timestamp_inc 4202 * Ingress timestamp increment. 4203 * 2's complement. 4204 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4205 * value for all ports. 4206 * Same units as used by MTPPTR. 4207 * Access: RW 4208 */ 4209 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4210 4211 /* reg_qpsc_egr_timestamp_inc 4212 * Egress timestamp increment. 4213 * 2's complement. 4214 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4215 * value for all ports. 4216 * Same units as used by MTPPTR. 4217 * Access: RW 4218 */ 4219 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4220 4221 static inline void 4222 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4223 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4224 u8 shaper_bs, u8 port_to_shaper_credits, 4225 int ing_timestamp_inc, int egr_timestamp_inc) 4226 { 4227 MLXSW_REG_ZERO(qpsc, payload); 4228 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4229 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4230 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4231 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4232 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4233 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4234 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4235 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4236 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4237 } 4238 4239 /* PMLP - Ports Module to Local Port Register 4240 * ------------------------------------------ 4241 * Configures the assignment of modules to local ports. 4242 */ 4243 #define MLXSW_REG_PMLP_ID 0x5002 4244 #define MLXSW_REG_PMLP_LEN 0x40 4245 4246 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4247 4248 /* reg_pmlp_rxtx 4249 * 0 - Tx value is used for both Tx and Rx. 4250 * 1 - Rx value is taken from a separte field. 4251 * Access: RW 4252 */ 4253 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4254 4255 /* reg_pmlp_local_port 4256 * Local port number. 4257 * Access: Index 4258 */ 4259 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4260 4261 /* reg_pmlp_width 4262 * 0 - Unmap local port. 4263 * 1 - Lane 0 is used. 4264 * 2 - Lanes 0 and 1 are used. 4265 * 4 - Lanes 0, 1, 2 and 3 are used. 4266 * 8 - Lanes 0-7 are used. 4267 * Access: RW 4268 */ 4269 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4270 4271 /* reg_pmlp_module 4272 * Module number. 4273 * Access: RW 4274 */ 4275 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4276 4277 /* reg_pmlp_tx_lane 4278 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4279 * Access: RW 4280 */ 4281 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4282 4283 /* reg_pmlp_rx_lane 4284 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4285 * equal to Tx lane. 4286 * Access: RW 4287 */ 4288 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4289 4290 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4291 { 4292 MLXSW_REG_ZERO(pmlp, payload); 4293 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4294 } 4295 4296 /* PMTU - Port MTU Register 4297 * ------------------------ 4298 * Configures and reports the port MTU. 4299 */ 4300 #define MLXSW_REG_PMTU_ID 0x5003 4301 #define MLXSW_REG_PMTU_LEN 0x10 4302 4303 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4304 4305 /* reg_pmtu_local_port 4306 * Local port number. 4307 * Access: Index 4308 */ 4309 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4310 4311 /* reg_pmtu_max_mtu 4312 * Maximum MTU. 4313 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4314 * reported, otherwise the minimum between the max_mtu of the different 4315 * types is reported. 4316 * Access: RO 4317 */ 4318 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4319 4320 /* reg_pmtu_admin_mtu 4321 * MTU value to set port to. Must be smaller or equal to max_mtu. 4322 * Note: If port type is Infiniband, then port must be disabled, when its 4323 * MTU is set. 4324 * Access: RW 4325 */ 4326 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4327 4328 /* reg_pmtu_oper_mtu 4329 * The actual MTU configured on the port. Packets exceeding this size 4330 * will be dropped. 4331 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4332 * oper_mtu might be smaller than admin_mtu. 4333 * Access: RO 4334 */ 4335 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4336 4337 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4338 u16 new_mtu) 4339 { 4340 MLXSW_REG_ZERO(pmtu, payload); 4341 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4342 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4343 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4344 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4345 } 4346 4347 /* PTYS - Port Type and Speed Register 4348 * ----------------------------------- 4349 * Configures and reports the port speed type. 4350 * 4351 * Note: When set while the link is up, the changes will not take effect 4352 * until the port transitions from down to up state. 4353 */ 4354 #define MLXSW_REG_PTYS_ID 0x5004 4355 #define MLXSW_REG_PTYS_LEN 0x40 4356 4357 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4358 4359 /* an_disable_admin 4360 * Auto negotiation disable administrative configuration 4361 * 0 - Device doesn't support AN disable. 4362 * 1 - Device supports AN disable. 4363 * Access: RW 4364 */ 4365 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4366 4367 /* reg_ptys_local_port 4368 * Local port number. 4369 * Access: Index 4370 */ 4371 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4372 4373 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4374 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4375 4376 /* reg_ptys_proto_mask 4377 * Protocol mask. Indicates which protocol is used. 4378 * 0 - Infiniband. 4379 * 1 - Fibre Channel. 4380 * 2 - Ethernet. 4381 * Access: Index 4382 */ 4383 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4384 4385 enum { 4386 MLXSW_REG_PTYS_AN_STATUS_NA, 4387 MLXSW_REG_PTYS_AN_STATUS_OK, 4388 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4389 }; 4390 4391 /* reg_ptys_an_status 4392 * Autonegotiation status. 4393 * Access: RO 4394 */ 4395 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4396 4397 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4398 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4399 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4400 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4401 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4402 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4403 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4404 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4405 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4406 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4407 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4408 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4409 4410 /* reg_ptys_ext_eth_proto_cap 4411 * Extended Ethernet port supported speeds and protocols. 4412 * Access: RO 4413 */ 4414 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4415 4416 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4417 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4418 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4419 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4420 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4421 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4422 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4423 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4424 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4425 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4426 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4427 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4428 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4429 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4430 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4431 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4432 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4433 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4434 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4435 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4436 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4437 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4438 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4439 4440 /* reg_ptys_eth_proto_cap 4441 * Ethernet port supported speeds and protocols. 4442 * Access: RO 4443 */ 4444 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4445 4446 /* reg_ptys_ib_link_width_cap 4447 * IB port supported widths. 4448 * Access: RO 4449 */ 4450 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4451 4452 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4453 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4454 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4455 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4456 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4457 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4458 4459 /* reg_ptys_ib_proto_cap 4460 * IB port supported speeds and protocols. 4461 * Access: RO 4462 */ 4463 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4464 4465 /* reg_ptys_ext_eth_proto_admin 4466 * Extended speed and protocol to set port to. 4467 * Access: RW 4468 */ 4469 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4470 4471 /* reg_ptys_eth_proto_admin 4472 * Speed and protocol to set port to. 4473 * Access: RW 4474 */ 4475 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4476 4477 /* reg_ptys_ib_link_width_admin 4478 * IB width to set port to. 4479 * Access: RW 4480 */ 4481 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4482 4483 /* reg_ptys_ib_proto_admin 4484 * IB speeds and protocols to set port to. 4485 * Access: RW 4486 */ 4487 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4488 4489 /* reg_ptys_ext_eth_proto_oper 4490 * The extended current speed and protocol configured for the port. 4491 * Access: RO 4492 */ 4493 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4494 4495 /* reg_ptys_eth_proto_oper 4496 * The current speed and protocol configured for the port. 4497 * Access: RO 4498 */ 4499 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4500 4501 /* reg_ptys_ib_link_width_oper 4502 * The current IB width to set port to. 4503 * Access: RO 4504 */ 4505 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4506 4507 /* reg_ptys_ib_proto_oper 4508 * The current IB speed and protocol. 4509 * Access: RO 4510 */ 4511 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4512 4513 enum mlxsw_reg_ptys_connector_type { 4514 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4515 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4516 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4517 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4518 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4519 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4520 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4521 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4522 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4523 }; 4524 4525 /* reg_ptys_connector_type 4526 * Connector type indication. 4527 * Access: RO 4528 */ 4529 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4530 4531 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4532 u32 proto_admin, bool autoneg) 4533 { 4534 MLXSW_REG_ZERO(ptys, payload); 4535 mlxsw_reg_ptys_local_port_set(payload, local_port); 4536 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4537 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4538 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4539 } 4540 4541 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4542 u32 proto_admin, bool autoneg) 4543 { 4544 MLXSW_REG_ZERO(ptys, payload); 4545 mlxsw_reg_ptys_local_port_set(payload, local_port); 4546 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4547 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4548 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4549 } 4550 4551 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4552 u32 *p_eth_proto_cap, 4553 u32 *p_eth_proto_admin, 4554 u32 *p_eth_proto_oper) 4555 { 4556 if (p_eth_proto_cap) 4557 *p_eth_proto_cap = 4558 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4559 if (p_eth_proto_admin) 4560 *p_eth_proto_admin = 4561 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4562 if (p_eth_proto_oper) 4563 *p_eth_proto_oper = 4564 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4565 } 4566 4567 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4568 u32 *p_eth_proto_cap, 4569 u32 *p_eth_proto_admin, 4570 u32 *p_eth_proto_oper) 4571 { 4572 if (p_eth_proto_cap) 4573 *p_eth_proto_cap = 4574 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4575 if (p_eth_proto_admin) 4576 *p_eth_proto_admin = 4577 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4578 if (p_eth_proto_oper) 4579 *p_eth_proto_oper = 4580 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4581 } 4582 4583 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4584 u16 proto_admin, u16 link_width) 4585 { 4586 MLXSW_REG_ZERO(ptys, payload); 4587 mlxsw_reg_ptys_local_port_set(payload, local_port); 4588 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4589 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4590 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4591 } 4592 4593 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4594 u16 *p_ib_link_width_cap, 4595 u16 *p_ib_proto_oper, 4596 u16 *p_ib_link_width_oper) 4597 { 4598 if (p_ib_proto_cap) 4599 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4600 if (p_ib_link_width_cap) 4601 *p_ib_link_width_cap = 4602 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4603 if (p_ib_proto_oper) 4604 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4605 if (p_ib_link_width_oper) 4606 *p_ib_link_width_oper = 4607 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4608 } 4609 4610 /* PPAD - Port Physical Address Register 4611 * ------------------------------------- 4612 * The PPAD register configures the per port physical MAC address. 4613 */ 4614 #define MLXSW_REG_PPAD_ID 0x5005 4615 #define MLXSW_REG_PPAD_LEN 0x10 4616 4617 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4618 4619 /* reg_ppad_single_base_mac 4620 * 0: base_mac, local port should be 0 and mac[7:0] is 4621 * reserved. HW will set incremental 4622 * 1: single_mac - mac of the local_port 4623 * Access: RW 4624 */ 4625 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4626 4627 /* reg_ppad_local_port 4628 * port number, if single_base_mac = 0 then local_port is reserved 4629 * Access: RW 4630 */ 4631 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4632 4633 /* reg_ppad_mac 4634 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4635 * If single_base_mac = 1 - the per port MAC address 4636 * Access: RW 4637 */ 4638 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4639 4640 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4641 u8 local_port) 4642 { 4643 MLXSW_REG_ZERO(ppad, payload); 4644 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4645 mlxsw_reg_ppad_local_port_set(payload, local_port); 4646 } 4647 4648 /* PAOS - Ports Administrative and Operational Status Register 4649 * ----------------------------------------------------------- 4650 * Configures and retrieves per port administrative and operational status. 4651 */ 4652 #define MLXSW_REG_PAOS_ID 0x5006 4653 #define MLXSW_REG_PAOS_LEN 0x10 4654 4655 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4656 4657 /* reg_paos_swid 4658 * Switch partition ID with which to associate the port. 4659 * Note: while external ports uses unique local port numbers (and thus swid is 4660 * redundant), router ports use the same local port number where swid is the 4661 * only indication for the relevant port. 4662 * Access: Index 4663 */ 4664 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4665 4666 /* reg_paos_local_port 4667 * Local port number. 4668 * Access: Index 4669 */ 4670 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4671 4672 /* reg_paos_admin_status 4673 * Port administrative state (the desired state of the port): 4674 * 1 - Up. 4675 * 2 - Down. 4676 * 3 - Up once. This means that in case of link failure, the port won't go 4677 * into polling mode, but will wait to be re-enabled by software. 4678 * 4 - Disabled by system. Can only be set by hardware. 4679 * Access: RW 4680 */ 4681 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4682 4683 /* reg_paos_oper_status 4684 * Port operational state (the current state): 4685 * 1 - Up. 4686 * 2 - Down. 4687 * 3 - Down by port failure. This means that the device will not let the 4688 * port up again until explicitly specified by software. 4689 * Access: RO 4690 */ 4691 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4692 4693 /* reg_paos_ase 4694 * Admin state update enabled. 4695 * Access: WO 4696 */ 4697 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4698 4699 /* reg_paos_ee 4700 * Event update enable. If this bit is set, event generation will be 4701 * updated based on the e field. 4702 * Access: WO 4703 */ 4704 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4705 4706 /* reg_paos_e 4707 * Event generation on operational state change: 4708 * 0 - Do not generate event. 4709 * 1 - Generate Event. 4710 * 2 - Generate Single Event. 4711 * Access: RW 4712 */ 4713 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4714 4715 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4716 enum mlxsw_port_admin_status status) 4717 { 4718 MLXSW_REG_ZERO(paos, payload); 4719 mlxsw_reg_paos_swid_set(payload, 0); 4720 mlxsw_reg_paos_local_port_set(payload, local_port); 4721 mlxsw_reg_paos_admin_status_set(payload, status); 4722 mlxsw_reg_paos_oper_status_set(payload, 0); 4723 mlxsw_reg_paos_ase_set(payload, 1); 4724 mlxsw_reg_paos_ee_set(payload, 1); 4725 mlxsw_reg_paos_e_set(payload, 1); 4726 } 4727 4728 /* PFCC - Ports Flow Control Configuration Register 4729 * ------------------------------------------------ 4730 * Configures and retrieves the per port flow control configuration. 4731 */ 4732 #define MLXSW_REG_PFCC_ID 0x5007 4733 #define MLXSW_REG_PFCC_LEN 0x20 4734 4735 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4736 4737 /* reg_pfcc_local_port 4738 * Local port number. 4739 * Access: Index 4740 */ 4741 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4742 4743 /* reg_pfcc_pnat 4744 * Port number access type. Determines the way local_port is interpreted: 4745 * 0 - Local port number. 4746 * 1 - IB / label port number. 4747 * Access: Index 4748 */ 4749 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4750 4751 /* reg_pfcc_shl_cap 4752 * Send to higher layers capabilities: 4753 * 0 - No capability of sending Pause and PFC frames to higher layers. 4754 * 1 - Device has capability of sending Pause and PFC frames to higher 4755 * layers. 4756 * Access: RO 4757 */ 4758 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4759 4760 /* reg_pfcc_shl_opr 4761 * Send to higher layers operation: 4762 * 0 - Pause and PFC frames are handled by the port (default). 4763 * 1 - Pause and PFC frames are handled by the port and also sent to 4764 * higher layers. Only valid if shl_cap = 1. 4765 * Access: RW 4766 */ 4767 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4768 4769 /* reg_pfcc_ppan 4770 * Pause policy auto negotiation. 4771 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4772 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4773 * based on the auto-negotiation resolution. 4774 * Access: RW 4775 * 4776 * Note: The auto-negotiation advertisement is set according to pptx and 4777 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4778 */ 4779 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4780 4781 /* reg_pfcc_prio_mask_tx 4782 * Bit per priority indicating if Tx flow control policy should be 4783 * updated based on bit pfctx. 4784 * Access: WO 4785 */ 4786 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4787 4788 /* reg_pfcc_prio_mask_rx 4789 * Bit per priority indicating if Rx flow control policy should be 4790 * updated based on bit pfcrx. 4791 * Access: WO 4792 */ 4793 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4794 4795 /* reg_pfcc_pptx 4796 * Admin Pause policy on Tx. 4797 * 0 - Never generate Pause frames (default). 4798 * 1 - Generate Pause frames according to Rx buffer threshold. 4799 * Access: RW 4800 */ 4801 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4802 4803 /* reg_pfcc_aptx 4804 * Active (operational) Pause policy on Tx. 4805 * 0 - Never generate Pause frames. 4806 * 1 - Generate Pause frames according to Rx buffer threshold. 4807 * Access: RO 4808 */ 4809 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4810 4811 /* reg_pfcc_pfctx 4812 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4813 * 0 - Never generate priority Pause frames on the specified priority 4814 * (default). 4815 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4816 * the specified priority. 4817 * Access: RW 4818 * 4819 * Note: pfctx and pptx must be mutually exclusive. 4820 */ 4821 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4822 4823 /* reg_pfcc_pprx 4824 * Admin Pause policy on Rx. 4825 * 0 - Ignore received Pause frames (default). 4826 * 1 - Respect received Pause frames. 4827 * Access: RW 4828 */ 4829 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4830 4831 /* reg_pfcc_aprx 4832 * Active (operational) Pause policy on Rx. 4833 * 0 - Ignore received Pause frames. 4834 * 1 - Respect received Pause frames. 4835 * Access: RO 4836 */ 4837 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4838 4839 /* reg_pfcc_pfcrx 4840 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4841 * 0 - Ignore incoming priority Pause frames on the specified priority 4842 * (default). 4843 * 1 - Respect incoming priority Pause frames on the specified priority. 4844 * Access: RW 4845 */ 4846 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4847 4848 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4849 4850 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4851 { 4852 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4853 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4854 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4855 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4856 } 4857 4858 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4859 { 4860 MLXSW_REG_ZERO(pfcc, payload); 4861 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4862 } 4863 4864 /* PPCNT - Ports Performance Counters Register 4865 * ------------------------------------------- 4866 * The PPCNT register retrieves per port performance counters. 4867 */ 4868 #define MLXSW_REG_PPCNT_ID 0x5008 4869 #define MLXSW_REG_PPCNT_LEN 0x100 4870 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4871 4872 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4873 4874 /* reg_ppcnt_swid 4875 * For HCA: must be always 0. 4876 * Switch partition ID to associate port with. 4877 * Switch partitions are numbered from 0 to 7 inclusively. 4878 * Switch partition 254 indicates stacking ports. 4879 * Switch partition 255 indicates all switch partitions. 4880 * Only valid on Set() operation with local_port=255. 4881 * Access: Index 4882 */ 4883 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4884 4885 /* reg_ppcnt_local_port 4886 * Local port number. 4887 * 255 indicates all ports on the device, and is only allowed 4888 * for Set() operation. 4889 * Access: Index 4890 */ 4891 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4892 4893 /* reg_ppcnt_pnat 4894 * Port number access type: 4895 * 0 - Local port number 4896 * 1 - IB port number 4897 * Access: Index 4898 */ 4899 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4900 4901 enum mlxsw_reg_ppcnt_grp { 4902 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4903 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4904 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4905 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4906 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4907 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4908 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4909 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4910 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4911 }; 4912 4913 /* reg_ppcnt_grp 4914 * Performance counter group. 4915 * Group 63 indicates all groups. Only valid on Set() operation with 4916 * clr bit set. 4917 * 0x0: IEEE 802.3 Counters 4918 * 0x1: RFC 2863 Counters 4919 * 0x2: RFC 2819 Counters 4920 * 0x3: RFC 3635 Counters 4921 * 0x5: Ethernet Extended Counters 4922 * 0x6: Ethernet Discard Counters 4923 * 0x8: Link Level Retransmission Counters 4924 * 0x10: Per Priority Counters 4925 * 0x11: Per Traffic Class Counters 4926 * 0x12: Physical Layer Counters 4927 * 0x13: Per Traffic Class Congestion Counters 4928 * Access: Index 4929 */ 4930 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4931 4932 /* reg_ppcnt_clr 4933 * Clear counters. Setting the clr bit will reset the counter value 4934 * for all counters in the counter group. This bit can be set 4935 * for both Set() and Get() operation. 4936 * Access: OP 4937 */ 4938 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4939 4940 /* reg_ppcnt_prio_tc 4941 * Priority for counter set that support per priority, valid values: 0-7. 4942 * Traffic class for counter set that support per traffic class, 4943 * valid values: 0- cap_max_tclass-1 . 4944 * For HCA: cap_max_tclass is always 8. 4945 * Otherwise must be 0. 4946 * Access: Index 4947 */ 4948 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4949 4950 /* Ethernet IEEE 802.3 Counter Group */ 4951 4952 /* reg_ppcnt_a_frames_transmitted_ok 4953 * Access: RO 4954 */ 4955 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4956 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4957 4958 /* reg_ppcnt_a_frames_received_ok 4959 * Access: RO 4960 */ 4961 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4962 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4963 4964 /* reg_ppcnt_a_frame_check_sequence_errors 4965 * Access: RO 4966 */ 4967 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4968 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4969 4970 /* reg_ppcnt_a_alignment_errors 4971 * Access: RO 4972 */ 4973 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4974 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4975 4976 /* reg_ppcnt_a_octets_transmitted_ok 4977 * Access: RO 4978 */ 4979 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4980 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4981 4982 /* reg_ppcnt_a_octets_received_ok 4983 * Access: RO 4984 */ 4985 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4986 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4987 4988 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4989 * Access: RO 4990 */ 4991 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4992 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4993 4994 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4995 * Access: RO 4996 */ 4997 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4998 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4999 5000 /* reg_ppcnt_a_multicast_frames_received_ok 5001 * Access: RO 5002 */ 5003 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5004 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5005 5006 /* reg_ppcnt_a_broadcast_frames_received_ok 5007 * Access: RO 5008 */ 5009 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5010 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5011 5012 /* reg_ppcnt_a_in_range_length_errors 5013 * Access: RO 5014 */ 5015 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5016 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5017 5018 /* reg_ppcnt_a_out_of_range_length_field 5019 * Access: RO 5020 */ 5021 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5022 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5023 5024 /* reg_ppcnt_a_frame_too_long_errors 5025 * Access: RO 5026 */ 5027 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5028 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5029 5030 /* reg_ppcnt_a_symbol_error_during_carrier 5031 * Access: RO 5032 */ 5033 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5034 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5035 5036 /* reg_ppcnt_a_mac_control_frames_transmitted 5037 * Access: RO 5038 */ 5039 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5040 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5041 5042 /* reg_ppcnt_a_mac_control_frames_received 5043 * Access: RO 5044 */ 5045 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5046 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5047 5048 /* reg_ppcnt_a_unsupported_opcodes_received 5049 * Access: RO 5050 */ 5051 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5052 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5053 5054 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5055 * Access: RO 5056 */ 5057 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5058 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5059 5060 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5061 * Access: RO 5062 */ 5063 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5064 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5065 5066 /* Ethernet RFC 2863 Counter Group */ 5067 5068 /* reg_ppcnt_if_in_discards 5069 * Access: RO 5070 */ 5071 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5072 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5073 5074 /* reg_ppcnt_if_out_discards 5075 * Access: RO 5076 */ 5077 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5078 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5079 5080 /* reg_ppcnt_if_out_errors 5081 * Access: RO 5082 */ 5083 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5084 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5085 5086 /* Ethernet RFC 2819 Counter Group */ 5087 5088 /* reg_ppcnt_ether_stats_undersize_pkts 5089 * Access: RO 5090 */ 5091 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5092 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5093 5094 /* reg_ppcnt_ether_stats_oversize_pkts 5095 * Access: RO 5096 */ 5097 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5098 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5099 5100 /* reg_ppcnt_ether_stats_fragments 5101 * Access: RO 5102 */ 5103 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5104 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5105 5106 /* reg_ppcnt_ether_stats_pkts64octets 5107 * Access: RO 5108 */ 5109 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5110 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5111 5112 /* reg_ppcnt_ether_stats_pkts65to127octets 5113 * Access: RO 5114 */ 5115 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5116 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5117 5118 /* reg_ppcnt_ether_stats_pkts128to255octets 5119 * Access: RO 5120 */ 5121 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5122 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5123 5124 /* reg_ppcnt_ether_stats_pkts256to511octets 5125 * Access: RO 5126 */ 5127 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5128 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5129 5130 /* reg_ppcnt_ether_stats_pkts512to1023octets 5131 * Access: RO 5132 */ 5133 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5134 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5135 5136 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5137 * Access: RO 5138 */ 5139 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5140 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5141 5142 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5143 * Access: RO 5144 */ 5145 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5146 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5147 5148 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5149 * Access: RO 5150 */ 5151 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5152 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5153 5154 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5155 * Access: RO 5156 */ 5157 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5158 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5159 5160 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5161 * Access: RO 5162 */ 5163 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5164 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5165 5166 /* Ethernet RFC 3635 Counter Group */ 5167 5168 /* reg_ppcnt_dot3stats_fcs_errors 5169 * Access: RO 5170 */ 5171 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5172 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5173 5174 /* reg_ppcnt_dot3stats_symbol_errors 5175 * Access: RO 5176 */ 5177 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5178 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5179 5180 /* reg_ppcnt_dot3control_in_unknown_opcodes 5181 * Access: RO 5182 */ 5183 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5184 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5185 5186 /* reg_ppcnt_dot3in_pause_frames 5187 * Access: RO 5188 */ 5189 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5190 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5191 5192 /* Ethernet Extended Counter Group Counters */ 5193 5194 /* reg_ppcnt_ecn_marked 5195 * Access: RO 5196 */ 5197 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5198 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5199 5200 /* Ethernet Discard Counter Group Counters */ 5201 5202 /* reg_ppcnt_ingress_general 5203 * Access: RO 5204 */ 5205 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5206 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5207 5208 /* reg_ppcnt_ingress_policy_engine 5209 * Access: RO 5210 */ 5211 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5212 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5213 5214 /* reg_ppcnt_ingress_vlan_membership 5215 * Access: RO 5216 */ 5217 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5218 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5219 5220 /* reg_ppcnt_ingress_tag_frame_type 5221 * Access: RO 5222 */ 5223 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5224 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5225 5226 /* reg_ppcnt_egress_vlan_membership 5227 * Access: RO 5228 */ 5229 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5230 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5231 5232 /* reg_ppcnt_loopback_filter 5233 * Access: RO 5234 */ 5235 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5236 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5237 5238 /* reg_ppcnt_egress_general 5239 * Access: RO 5240 */ 5241 MLXSW_ITEM64(reg, ppcnt, egress_general, 5242 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5243 5244 /* reg_ppcnt_egress_hoq 5245 * Access: RO 5246 */ 5247 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5248 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5249 5250 /* reg_ppcnt_egress_policy_engine 5251 * Access: RO 5252 */ 5253 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5254 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5255 5256 /* reg_ppcnt_ingress_tx_link_down 5257 * Access: RO 5258 */ 5259 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5260 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5261 5262 /* reg_ppcnt_egress_stp_filter 5263 * Access: RO 5264 */ 5265 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5266 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5267 5268 /* reg_ppcnt_egress_sll 5269 * Access: RO 5270 */ 5271 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5272 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5273 5274 /* Ethernet Per Priority Group Counters */ 5275 5276 /* reg_ppcnt_rx_octets 5277 * Access: RO 5278 */ 5279 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5280 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5281 5282 /* reg_ppcnt_rx_frames 5283 * Access: RO 5284 */ 5285 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5286 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5287 5288 /* reg_ppcnt_tx_octets 5289 * Access: RO 5290 */ 5291 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5292 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5293 5294 /* reg_ppcnt_tx_frames 5295 * Access: RO 5296 */ 5297 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5298 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5299 5300 /* reg_ppcnt_rx_pause 5301 * Access: RO 5302 */ 5303 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5304 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5305 5306 /* reg_ppcnt_rx_pause_duration 5307 * Access: RO 5308 */ 5309 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5311 5312 /* reg_ppcnt_tx_pause 5313 * Access: RO 5314 */ 5315 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5317 5318 /* reg_ppcnt_tx_pause_duration 5319 * Access: RO 5320 */ 5321 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5322 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5323 5324 /* reg_ppcnt_rx_pause_transition 5325 * Access: RO 5326 */ 5327 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5328 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5329 5330 /* Ethernet Per Traffic Group Counters */ 5331 5332 /* reg_ppcnt_tc_transmit_queue 5333 * Contains the transmit queue depth in cells of traffic class 5334 * selected by prio_tc and the port selected by local_port. 5335 * The field cannot be cleared. 5336 * Access: RO 5337 */ 5338 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5339 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5340 5341 /* reg_ppcnt_tc_no_buffer_discard_uc 5342 * The number of unicast packets dropped due to lack of shared 5343 * buffer resources. 5344 * Access: RO 5345 */ 5346 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5347 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5348 5349 /* Ethernet Per Traffic Class Congestion Group Counters */ 5350 5351 /* reg_ppcnt_wred_discard 5352 * Access: RO 5353 */ 5354 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5356 5357 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5358 enum mlxsw_reg_ppcnt_grp grp, 5359 u8 prio_tc) 5360 { 5361 MLXSW_REG_ZERO(ppcnt, payload); 5362 mlxsw_reg_ppcnt_swid_set(payload, 0); 5363 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5364 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5365 mlxsw_reg_ppcnt_grp_set(payload, grp); 5366 mlxsw_reg_ppcnt_clr_set(payload, 0); 5367 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5368 } 5369 5370 /* PLIB - Port Local to InfiniBand Port 5371 * ------------------------------------ 5372 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5373 */ 5374 #define MLXSW_REG_PLIB_ID 0x500A 5375 #define MLXSW_REG_PLIB_LEN 0x10 5376 5377 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5378 5379 /* reg_plib_local_port 5380 * Local port number. 5381 * Access: Index 5382 */ 5383 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5384 5385 /* reg_plib_ib_port 5386 * InfiniBand port remapping for local_port. 5387 * Access: RW 5388 */ 5389 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5390 5391 /* PPTB - Port Prio To Buffer Register 5392 * ----------------------------------- 5393 * Configures the switch priority to buffer table. 5394 */ 5395 #define MLXSW_REG_PPTB_ID 0x500B 5396 #define MLXSW_REG_PPTB_LEN 0x10 5397 5398 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5399 5400 enum { 5401 MLXSW_REG_PPTB_MM_UM, 5402 MLXSW_REG_PPTB_MM_UNICAST, 5403 MLXSW_REG_PPTB_MM_MULTICAST, 5404 }; 5405 5406 /* reg_pptb_mm 5407 * Mapping mode. 5408 * 0 - Map both unicast and multicast packets to the same buffer. 5409 * 1 - Map only unicast packets. 5410 * 2 - Map only multicast packets. 5411 * Access: Index 5412 * 5413 * Note: SwitchX-2 only supports the first option. 5414 */ 5415 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5416 5417 /* reg_pptb_local_port 5418 * Local port number. 5419 * Access: Index 5420 */ 5421 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5422 5423 /* reg_pptb_um 5424 * Enables the update of the untagged_buf field. 5425 * Access: RW 5426 */ 5427 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5428 5429 /* reg_pptb_pm 5430 * Enables the update of the prio_to_buff field. 5431 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5432 * Access: RW 5433 */ 5434 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5435 5436 /* reg_pptb_prio_to_buff 5437 * Mapping of switch priority <i> to one of the allocated receive port 5438 * buffers. 5439 * Access: RW 5440 */ 5441 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5442 5443 /* reg_pptb_pm_msb 5444 * Enables the update of the prio_to_buff field. 5445 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5446 * Access: RW 5447 */ 5448 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5449 5450 /* reg_pptb_untagged_buff 5451 * Mapping of untagged frames to one of the allocated receive port buffers. 5452 * Access: RW 5453 * 5454 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5455 * Spectrum, as it maps untagged packets based on the default switch priority. 5456 */ 5457 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5458 5459 /* reg_pptb_prio_to_buff_msb 5460 * Mapping of switch priority <i+8> to one of the allocated receive port 5461 * buffers. 5462 * Access: RW 5463 */ 5464 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5465 5466 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5467 5468 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5469 { 5470 MLXSW_REG_ZERO(pptb, payload); 5471 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5472 mlxsw_reg_pptb_local_port_set(payload, local_port); 5473 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5474 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5475 } 5476 5477 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5478 u8 buff) 5479 { 5480 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5481 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5482 } 5483 5484 /* PBMC - Port Buffer Management Control Register 5485 * ---------------------------------------------- 5486 * The PBMC register configures and retrieves the port packet buffer 5487 * allocation for different Prios, and the Pause threshold management. 5488 */ 5489 #define MLXSW_REG_PBMC_ID 0x500C 5490 #define MLXSW_REG_PBMC_LEN 0x6C 5491 5492 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5493 5494 /* reg_pbmc_local_port 5495 * Local port number. 5496 * Access: Index 5497 */ 5498 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5499 5500 /* reg_pbmc_xoff_timer_value 5501 * When device generates a pause frame, it uses this value as the pause 5502 * timer (time for the peer port to pause in quota-512 bit time). 5503 * Access: RW 5504 */ 5505 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5506 5507 /* reg_pbmc_xoff_refresh 5508 * The time before a new pause frame should be sent to refresh the pause RW 5509 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5510 * time). 5511 * Access: RW 5512 */ 5513 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5514 5515 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5516 5517 /* reg_pbmc_buf_lossy 5518 * The field indicates if the buffer is lossy. 5519 * 0 - Lossless 5520 * 1 - Lossy 5521 * Access: RW 5522 */ 5523 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5524 5525 /* reg_pbmc_buf_epsb 5526 * Eligible for Port Shared buffer. 5527 * If epsb is set, packets assigned to buffer are allowed to insert the port 5528 * shared buffer. 5529 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5530 * Access: RW 5531 */ 5532 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5533 5534 /* reg_pbmc_buf_size 5535 * The part of the packet buffer array is allocated for the specific buffer. 5536 * Units are represented in cells. 5537 * Access: RW 5538 */ 5539 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5540 5541 /* reg_pbmc_buf_xoff_threshold 5542 * Once the amount of data in the buffer goes above this value, device 5543 * starts sending PFC frames for all priorities associated with the 5544 * buffer. Units are represented in cells. Reserved in case of lossy 5545 * buffer. 5546 * Access: RW 5547 * 5548 * Note: In Spectrum, reserved for buffer[9]. 5549 */ 5550 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5551 0x08, 0x04, false); 5552 5553 /* reg_pbmc_buf_xon_threshold 5554 * When the amount of data in the buffer goes below this value, device 5555 * stops sending PFC frames for the priorities associated with the 5556 * buffer. Units are represented in cells. Reserved in case of lossy 5557 * buffer. 5558 * Access: RW 5559 * 5560 * Note: In Spectrum, reserved for buffer[9]. 5561 */ 5562 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5563 0x08, 0x04, false); 5564 5565 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5566 u16 xoff_timer_value, u16 xoff_refresh) 5567 { 5568 MLXSW_REG_ZERO(pbmc, payload); 5569 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5570 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5571 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5572 } 5573 5574 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5575 int buf_index, 5576 u16 size) 5577 { 5578 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5579 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5580 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5581 } 5582 5583 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5584 int buf_index, u16 size, 5585 u16 threshold) 5586 { 5587 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5588 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5589 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5590 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5591 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5592 } 5593 5594 /* PSPA - Port Switch Partition Allocation 5595 * --------------------------------------- 5596 * Controls the association of a port with a switch partition and enables 5597 * configuring ports as stacking ports. 5598 */ 5599 #define MLXSW_REG_PSPA_ID 0x500D 5600 #define MLXSW_REG_PSPA_LEN 0x8 5601 5602 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5603 5604 /* reg_pspa_swid 5605 * Switch partition ID. 5606 * Access: RW 5607 */ 5608 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5609 5610 /* reg_pspa_local_port 5611 * Local port number. 5612 * Access: Index 5613 */ 5614 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5615 5616 /* reg_pspa_sub_port 5617 * Virtual port within the local port. Set to 0 when virtual ports are 5618 * disabled on the local port. 5619 * Access: Index 5620 */ 5621 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5622 5623 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5624 { 5625 MLXSW_REG_ZERO(pspa, payload); 5626 mlxsw_reg_pspa_swid_set(payload, swid); 5627 mlxsw_reg_pspa_local_port_set(payload, local_port); 5628 mlxsw_reg_pspa_sub_port_set(payload, 0); 5629 } 5630 5631 /* PMAOS - Ports Module Administrative and Operational Status 5632 * ---------------------------------------------------------- 5633 * This register configures and retrieves the per module status. 5634 */ 5635 #define MLXSW_REG_PMAOS_ID 0x5012 5636 #define MLXSW_REG_PMAOS_LEN 0x10 5637 5638 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5639 5640 /* reg_slot_index 5641 * Slot index. 5642 * Access: Index 5643 */ 5644 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5645 5646 /* reg_pmaos_module 5647 * Module number. 5648 * Access: Index 5649 */ 5650 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5651 5652 /* reg_pmaos_ase 5653 * Admin state update enable. 5654 * If this bit is set, admin state will be updated based on admin_state field. 5655 * Only relevant on Set() operations. 5656 * Access: WO 5657 */ 5658 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5659 5660 /* reg_pmaos_ee 5661 * Event update enable. 5662 * If this bit is set, event generation will be updated based on the e field. 5663 * Only relevant on Set operations. 5664 * Access: WO 5665 */ 5666 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5667 5668 enum mlxsw_reg_pmaos_e { 5669 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5670 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5671 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5672 }; 5673 5674 /* reg_pmaos_e 5675 * Event Generation on operational state change. 5676 * Access: RW 5677 */ 5678 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5679 5680 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module, 5681 enum mlxsw_reg_pmaos_e e) 5682 { 5683 MLXSW_REG_ZERO(pmaos, payload); 5684 mlxsw_reg_pmaos_module_set(payload, module); 5685 mlxsw_reg_pmaos_e_set(payload, e); 5686 mlxsw_reg_pmaos_ee_set(payload, true); 5687 } 5688 5689 /* PPLR - Port Physical Loopback Register 5690 * -------------------------------------- 5691 * This register allows configuration of the port's loopback mode. 5692 */ 5693 #define MLXSW_REG_PPLR_ID 0x5018 5694 #define MLXSW_REG_PPLR_LEN 0x8 5695 5696 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5697 5698 /* reg_pplr_local_port 5699 * Local port number. 5700 * Access: Index 5701 */ 5702 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5703 5704 /* Phy local loopback. When set the port's egress traffic is looped back 5705 * to the receiver and the port transmitter is disabled. 5706 */ 5707 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5708 5709 /* reg_pplr_lb_en 5710 * Loopback enable. 5711 * Access: RW 5712 */ 5713 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5714 5715 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5716 bool phy_local) 5717 { 5718 MLXSW_REG_ZERO(pplr, payload); 5719 mlxsw_reg_pplr_local_port_set(payload, local_port); 5720 mlxsw_reg_pplr_lb_en_set(payload, 5721 phy_local ? 5722 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5723 } 5724 5725 /* PMPE - Port Module Plug/Unplug Event Register 5726 * --------------------------------------------- 5727 * This register reports any operational status change of a module. 5728 * A change in the module’s state will generate an event only if the change 5729 * happens after arming the event mechanism. Any changes to the module state 5730 * while the event mechanism is not armed will not be reported. Software can 5731 * query the PMPE register for module status. 5732 */ 5733 #define MLXSW_REG_PMPE_ID 0x5024 5734 #define MLXSW_REG_PMPE_LEN 0x10 5735 5736 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 5737 5738 /* reg_pmpe_slot_index 5739 * Slot index. 5740 * Access: Index 5741 */ 5742 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 5743 5744 /* reg_pmpe_module 5745 * Module number. 5746 * Access: Index 5747 */ 5748 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 5749 5750 enum mlxsw_reg_pmpe_module_status { 5751 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 5752 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 5753 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 5754 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 5755 }; 5756 5757 /* reg_pmpe_module_status 5758 * Module status. 5759 * Access: RO 5760 */ 5761 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 5762 5763 /* reg_pmpe_error_type 5764 * Module error details. 5765 * Access: RO 5766 */ 5767 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 5768 5769 /* PDDR - Port Diagnostics Database Register 5770 * ----------------------------------------- 5771 * The PDDR enables to read the Phy debug database 5772 */ 5773 #define MLXSW_REG_PDDR_ID 0x5031 5774 #define MLXSW_REG_PDDR_LEN 0x100 5775 5776 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 5777 5778 /* reg_pddr_local_port 5779 * Local port number. 5780 * Access: Index 5781 */ 5782 MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8); 5783 5784 enum mlxsw_reg_pddr_page_select { 5785 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 5786 }; 5787 5788 /* reg_pddr_page_select 5789 * Page select index. 5790 * Access: Index 5791 */ 5792 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 5793 5794 enum mlxsw_reg_pddr_trblsh_group_opcode { 5795 /* Monitor opcodes */ 5796 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 5797 }; 5798 5799 /* reg_pddr_group_opcode 5800 * Group selector. 5801 * Access: Index 5802 */ 5803 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 5804 5805 /* reg_pddr_status_opcode 5806 * Group selector. 5807 * Access: RO 5808 */ 5809 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 5810 5811 static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port, 5812 u8 page_select) 5813 { 5814 MLXSW_REG_ZERO(pddr, payload); 5815 mlxsw_reg_pddr_local_port_set(payload, local_port); 5816 mlxsw_reg_pddr_page_select_set(payload, page_select); 5817 } 5818 5819 /* PMTM - Port Module Type Mapping Register 5820 * ---------------------------------------- 5821 * The PMTM allows query or configuration of module types. 5822 */ 5823 #define MLXSW_REG_PMTM_ID 0x5067 5824 #define MLXSW_REG_PMTM_LEN 0x10 5825 5826 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5827 5828 /* reg_pmtm_module 5829 * Module number. 5830 * Access: Index 5831 */ 5832 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5833 5834 enum mlxsw_reg_pmtm_module_type { 5835 /* Backplane with 4 lanes */ 5836 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5837 /* QSFP */ 5838 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5839 /* SFP */ 5840 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5841 /* Backplane with single lane */ 5842 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5843 /* Backplane with two lane */ 5844 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5845 /* Chip2Chip4x */ 5846 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5847 /* Chip2Chip2x */ 5848 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5849 /* Chip2Chip1x */ 5850 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5851 /* QSFP-DD */ 5852 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5853 /* OSFP */ 5854 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5855 /* SFP-DD */ 5856 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5857 /* DSFP */ 5858 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5859 /* Chip2Chip8x */ 5860 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5861 }; 5862 5863 /* reg_pmtm_module_type 5864 * Module type. 5865 * Access: RW 5866 */ 5867 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5868 5869 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5870 { 5871 MLXSW_REG_ZERO(pmtm, payload); 5872 mlxsw_reg_pmtm_module_set(payload, module); 5873 } 5874 5875 static inline void 5876 mlxsw_reg_pmtm_unpack(char *payload, 5877 enum mlxsw_reg_pmtm_module_type *module_type) 5878 { 5879 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5880 } 5881 5882 /* HTGT - Host Trap Group Table 5883 * ---------------------------- 5884 * Configures the properties for forwarding to CPU. 5885 */ 5886 #define MLXSW_REG_HTGT_ID 0x7002 5887 #define MLXSW_REG_HTGT_LEN 0x20 5888 5889 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5890 5891 /* reg_htgt_swid 5892 * Switch partition ID. 5893 * Access: Index 5894 */ 5895 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5896 5897 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5898 5899 /* reg_htgt_type 5900 * CPU path type. 5901 * Access: RW 5902 */ 5903 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5904 5905 enum mlxsw_reg_htgt_trap_group { 5906 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5907 MLXSW_REG_HTGT_TRAP_GROUP_MFDE, 5908 MLXSW_REG_HTGT_TRAP_GROUP_MTWE, 5909 MLXSW_REG_HTGT_TRAP_GROUP_PMPE, 5910 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5911 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5912 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5913 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5914 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5915 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5916 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5917 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5918 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5919 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5920 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 5921 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5922 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5923 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5924 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5925 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5926 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5927 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5928 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5929 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5930 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5931 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5932 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5933 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5934 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5935 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5936 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5937 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5938 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5939 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 5940 5941 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5942 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5943 }; 5944 5945 /* reg_htgt_trap_group 5946 * Trap group number. User defined number specifying which trap groups 5947 * should be forwarded to the CPU. The mapping between trap IDs and trap 5948 * groups is configured using HPKT register. 5949 * Access: Index 5950 */ 5951 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5952 5953 enum { 5954 MLXSW_REG_HTGT_POLICER_DISABLE, 5955 MLXSW_REG_HTGT_POLICER_ENABLE, 5956 }; 5957 5958 /* reg_htgt_pide 5959 * Enable policer ID specified using 'pid' field. 5960 * Access: RW 5961 */ 5962 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5963 5964 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5965 5966 /* reg_htgt_pid 5967 * Policer ID for the trap group. 5968 * Access: RW 5969 */ 5970 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5971 5972 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5973 5974 /* reg_htgt_mirror_action 5975 * Mirror action to use. 5976 * 0 - Trap to CPU. 5977 * 1 - Trap to CPU and mirror to a mirroring agent. 5978 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5979 * Access: RW 5980 * 5981 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5982 */ 5983 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5984 5985 /* reg_htgt_mirroring_agent 5986 * Mirroring agent. 5987 * Access: RW 5988 */ 5989 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5990 5991 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5992 5993 /* reg_htgt_priority 5994 * Trap group priority. 5995 * In case a packet matches multiple classification rules, the packet will 5996 * only be trapped once, based on the trap ID associated with the group (via 5997 * register HPKT) with the highest priority. 5998 * Supported values are 0-7, with 7 represnting the highest priority. 5999 * Access: RW 6000 * 6001 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6002 * by the 'trap_group' field. 6003 */ 6004 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6005 6006 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6007 6008 /* reg_htgt_local_path_cpu_tclass 6009 * CPU ingress traffic class for the trap group. 6010 * Access: RW 6011 */ 6012 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6013 6014 enum mlxsw_reg_htgt_local_path_rdq { 6015 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6016 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6017 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6018 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6019 }; 6020 /* reg_htgt_local_path_rdq 6021 * Receive descriptor queue (RDQ) to use for the trap group. 6022 * Access: RW 6023 */ 6024 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6025 6026 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6027 u8 priority, u8 tc) 6028 { 6029 MLXSW_REG_ZERO(htgt, payload); 6030 6031 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6032 mlxsw_reg_htgt_pide_set(payload, 6033 MLXSW_REG_HTGT_POLICER_DISABLE); 6034 } else { 6035 mlxsw_reg_htgt_pide_set(payload, 6036 MLXSW_REG_HTGT_POLICER_ENABLE); 6037 mlxsw_reg_htgt_pid_set(payload, policer_id); 6038 } 6039 6040 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6041 mlxsw_reg_htgt_trap_group_set(payload, group); 6042 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6043 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6044 mlxsw_reg_htgt_priority_set(payload, priority); 6045 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6046 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6047 } 6048 6049 /* HPKT - Host Packet Trap 6050 * ----------------------- 6051 * Configures trap IDs inside trap groups. 6052 */ 6053 #define MLXSW_REG_HPKT_ID 0x7003 6054 #define MLXSW_REG_HPKT_LEN 0x10 6055 6056 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6057 6058 enum { 6059 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6060 MLXSW_REG_HPKT_ACK_REQUIRED, 6061 }; 6062 6063 /* reg_hpkt_ack 6064 * Require acknowledgements from the host for events. 6065 * If set, then the device will wait for the event it sent to be acknowledged 6066 * by the host. This option is only relevant for event trap IDs. 6067 * Access: RW 6068 * 6069 * Note: Currently not supported by firmware. 6070 */ 6071 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6072 6073 enum mlxsw_reg_hpkt_action { 6074 MLXSW_REG_HPKT_ACTION_FORWARD, 6075 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6076 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6077 MLXSW_REG_HPKT_ACTION_DISCARD, 6078 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6079 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6080 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6081 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6082 }; 6083 6084 /* reg_hpkt_action 6085 * Action to perform on packet when trapped. 6086 * 0 - No action. Forward to CPU based on switching rules. 6087 * 1 - Trap to CPU (CPU receives sole copy). 6088 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6089 * 3 - Discard. 6090 * 4 - Soft discard (allow other traps to act on the packet). 6091 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6092 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6093 * 15 - Restore the firmware's default action. 6094 * Access: RW 6095 * 6096 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6097 * addressed to the CPU. 6098 */ 6099 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6100 6101 /* reg_hpkt_trap_group 6102 * Trap group to associate the trap with. 6103 * Access: RW 6104 */ 6105 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6106 6107 /* reg_hpkt_trap_id 6108 * Trap ID. 6109 * Access: Index 6110 * 6111 * Note: A trap ID can only be associated with a single trap group. The device 6112 * will associate the trap ID with the last trap group configured. 6113 */ 6114 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6115 6116 enum { 6117 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6118 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6119 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6120 }; 6121 6122 /* reg_hpkt_ctrl 6123 * Configure dedicated buffer resources for control packets. 6124 * Ignored by SwitchX-2. 6125 * 0 - Keep factory defaults. 6126 * 1 - Do not use control buffer for this trap ID. 6127 * 2 - Use control buffer for this trap ID. 6128 * Access: RW 6129 */ 6130 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6131 6132 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6133 enum mlxsw_reg_htgt_trap_group trap_group, 6134 bool is_ctrl) 6135 { 6136 MLXSW_REG_ZERO(hpkt, payload); 6137 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6138 mlxsw_reg_hpkt_action_set(payload, action); 6139 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6140 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6141 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6142 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6143 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6144 } 6145 6146 /* RGCR - Router General Configuration Register 6147 * -------------------------------------------- 6148 * The register is used for setting up the router configuration. 6149 */ 6150 #define MLXSW_REG_RGCR_ID 0x8001 6151 #define MLXSW_REG_RGCR_LEN 0x28 6152 6153 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6154 6155 /* reg_rgcr_ipv4_en 6156 * IPv4 router enable. 6157 * Access: RW 6158 */ 6159 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6160 6161 /* reg_rgcr_ipv6_en 6162 * IPv6 router enable. 6163 * Access: RW 6164 */ 6165 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6166 6167 /* reg_rgcr_max_router_interfaces 6168 * Defines the maximum number of active router interfaces for all virtual 6169 * routers. 6170 * Access: RW 6171 */ 6172 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6173 6174 /* reg_rgcr_usp 6175 * Update switch priority and packet color. 6176 * 0 - Preserve the value of Switch Priority and packet color. 6177 * 1 - Recalculate the value of Switch Priority and packet color. 6178 * Access: RW 6179 * 6180 * Note: Not supported by SwitchX and SwitchX-2. 6181 */ 6182 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6183 6184 /* reg_rgcr_pcp_rw 6185 * Indicates how to handle the pcp_rewrite_en value: 6186 * 0 - Preserve the value of pcp_rewrite_en. 6187 * 2 - Disable PCP rewrite. 6188 * 3 - Enable PCP rewrite. 6189 * Access: RW 6190 * 6191 * Note: Not supported by SwitchX and SwitchX-2. 6192 */ 6193 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6194 6195 /* reg_rgcr_activity_dis 6196 * Activity disable: 6197 * 0 - Activity will be set when an entry is hit (default). 6198 * 1 - Activity will not be set when an entry is hit. 6199 * 6200 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6201 * (RALUE). 6202 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6203 * Entry (RAUHT). 6204 * Bits 2:7 are reserved. 6205 * Access: RW 6206 * 6207 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6208 */ 6209 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6210 6211 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6212 bool ipv6_en) 6213 { 6214 MLXSW_REG_ZERO(rgcr, payload); 6215 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6216 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6217 } 6218 6219 /* RITR - Router Interface Table Register 6220 * -------------------------------------- 6221 * The register is used to configure the router interface table. 6222 */ 6223 #define MLXSW_REG_RITR_ID 0x8002 6224 #define MLXSW_REG_RITR_LEN 0x40 6225 6226 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6227 6228 /* reg_ritr_enable 6229 * Enables routing on the router interface. 6230 * Access: RW 6231 */ 6232 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6233 6234 /* reg_ritr_ipv4 6235 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6236 * interface. 6237 * Access: RW 6238 */ 6239 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6240 6241 /* reg_ritr_ipv6 6242 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6243 * interface. 6244 * Access: RW 6245 */ 6246 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6247 6248 /* reg_ritr_ipv4_mc 6249 * IPv4 multicast routing enable. 6250 * Access: RW 6251 */ 6252 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6253 6254 /* reg_ritr_ipv6_mc 6255 * IPv6 multicast routing enable. 6256 * Access: RW 6257 */ 6258 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6259 6260 enum mlxsw_reg_ritr_if_type { 6261 /* VLAN interface. */ 6262 MLXSW_REG_RITR_VLAN_IF, 6263 /* FID interface. */ 6264 MLXSW_REG_RITR_FID_IF, 6265 /* Sub-port interface. */ 6266 MLXSW_REG_RITR_SP_IF, 6267 /* Loopback Interface. */ 6268 MLXSW_REG_RITR_LOOPBACK_IF, 6269 }; 6270 6271 /* reg_ritr_type 6272 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6273 * Access: RW 6274 */ 6275 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6276 6277 enum { 6278 MLXSW_REG_RITR_RIF_CREATE, 6279 MLXSW_REG_RITR_RIF_DEL, 6280 }; 6281 6282 /* reg_ritr_op 6283 * Opcode: 6284 * 0 - Create or edit RIF. 6285 * 1 - Delete RIF. 6286 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6287 * is not supported. An interface must be deleted and re-created in order 6288 * to update properties. 6289 * Access: WO 6290 */ 6291 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6292 6293 /* reg_ritr_rif 6294 * Router interface index. A pointer to the Router Interface Table. 6295 * Access: Index 6296 */ 6297 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6298 6299 /* reg_ritr_ipv4_fe 6300 * IPv4 Forwarding Enable. 6301 * Enables routing of IPv4 traffic on the router interface. When disabled, 6302 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6303 * Not supported in SwitchX-2. 6304 * Access: RW 6305 */ 6306 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6307 6308 /* reg_ritr_ipv6_fe 6309 * IPv6 Forwarding Enable. 6310 * Enables routing of IPv6 traffic on the router interface. When disabled, 6311 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6312 * Not supported in SwitchX-2. 6313 * Access: RW 6314 */ 6315 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6316 6317 /* reg_ritr_ipv4_mc_fe 6318 * IPv4 Multicast Forwarding Enable. 6319 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6320 * will be enabled. 6321 * Access: RW 6322 */ 6323 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6324 6325 /* reg_ritr_ipv6_mc_fe 6326 * IPv6 Multicast Forwarding Enable. 6327 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6328 * will be enabled. 6329 * Access: RW 6330 */ 6331 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6332 6333 /* reg_ritr_lb_en 6334 * Loop-back filter enable for unicast packets. 6335 * If the flag is set then loop-back filter for unicast packets is 6336 * implemented on the RIF. Multicast packets are always subject to 6337 * loop-back filtering. 6338 * Access: RW 6339 */ 6340 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6341 6342 /* reg_ritr_virtual_router 6343 * Virtual router ID associated with the router interface. 6344 * Access: RW 6345 */ 6346 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6347 6348 /* reg_ritr_mtu 6349 * Router interface MTU. 6350 * Access: RW 6351 */ 6352 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6353 6354 /* reg_ritr_if_swid 6355 * Switch partition ID. 6356 * Access: RW 6357 */ 6358 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6359 6360 /* reg_ritr_if_mac 6361 * Router interface MAC address. 6362 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6363 * Access: RW 6364 */ 6365 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6366 6367 /* reg_ritr_if_vrrp_id_ipv6 6368 * VRRP ID for IPv6 6369 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6370 * Access: RW 6371 */ 6372 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6373 6374 /* reg_ritr_if_vrrp_id_ipv4 6375 * VRRP ID for IPv4 6376 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6377 * Access: RW 6378 */ 6379 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6380 6381 /* VLAN Interface */ 6382 6383 /* reg_ritr_vlan_if_vid 6384 * VLAN ID. 6385 * Access: RW 6386 */ 6387 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6388 6389 /* FID Interface */ 6390 6391 /* reg_ritr_fid_if_fid 6392 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6393 * the vFID range are supported. 6394 * Access: RW 6395 */ 6396 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6397 6398 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6399 enum mlxsw_reg_ritr_if_type rif_type, 6400 u16 fid) 6401 { 6402 if (rif_type == MLXSW_REG_RITR_FID_IF) 6403 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6404 else 6405 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6406 } 6407 6408 /* Sub-port Interface */ 6409 6410 /* reg_ritr_sp_if_lag 6411 * LAG indication. When this bit is set the system_port field holds the 6412 * LAG identifier. 6413 * Access: RW 6414 */ 6415 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6416 6417 /* reg_ritr_sp_system_port 6418 * Port unique indentifier. When lag bit is set, this field holds the 6419 * lag_id in bits 0:9. 6420 * Access: RW 6421 */ 6422 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6423 6424 /* reg_ritr_sp_if_vid 6425 * VLAN ID. 6426 * Access: RW 6427 */ 6428 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6429 6430 /* Loopback Interface */ 6431 6432 enum mlxsw_reg_ritr_loopback_protocol { 6433 /* IPinIP IPv4 underlay Unicast */ 6434 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6435 /* IPinIP IPv6 underlay Unicast */ 6436 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6437 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6438 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6439 }; 6440 6441 /* reg_ritr_loopback_protocol 6442 * Access: RW 6443 */ 6444 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6445 6446 enum mlxsw_reg_ritr_loopback_ipip_type { 6447 /* Tunnel is IPinIP. */ 6448 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6449 /* Tunnel is GRE, no key. */ 6450 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6451 /* Tunnel is GRE, with a key. */ 6452 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6453 }; 6454 6455 /* reg_ritr_loopback_ipip_type 6456 * Encapsulation type. 6457 * Access: RW 6458 */ 6459 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6460 6461 enum mlxsw_reg_ritr_loopback_ipip_options { 6462 /* The key is defined by gre_key. */ 6463 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6464 }; 6465 6466 /* reg_ritr_loopback_ipip_options 6467 * Access: RW 6468 */ 6469 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6470 6471 /* reg_ritr_loopback_ipip_uvr 6472 * Underlay Virtual Router ID. 6473 * Range is 0..cap_max_virtual_routers-1. 6474 * Reserved for Spectrum-2. 6475 * Access: RW 6476 */ 6477 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6478 6479 /* reg_ritr_loopback_ipip_underlay_rif 6480 * Underlay ingress router interface. 6481 * Reserved for Spectrum. 6482 * Access: RW 6483 */ 6484 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6485 6486 /* reg_ritr_loopback_ipip_usip* 6487 * Encapsulation Underlay source IP. 6488 * Access: RW 6489 */ 6490 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6491 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6492 6493 /* reg_ritr_loopback_ipip_gre_key 6494 * GRE Key. 6495 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6496 * Access: RW 6497 */ 6498 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6499 6500 /* Shared between ingress/egress */ 6501 enum mlxsw_reg_ritr_counter_set_type { 6502 /* No Count. */ 6503 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6504 /* Basic. Used for router interfaces, counting the following: 6505 * - Error and Discard counters. 6506 * - Unicast, Multicast and Broadcast counters. Sharing the 6507 * same set of counters for the different type of traffic 6508 * (IPv4, IPv6 and mpls). 6509 */ 6510 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6511 }; 6512 6513 /* reg_ritr_ingress_counter_index 6514 * Counter Index for flow counter. 6515 * Access: RW 6516 */ 6517 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6518 6519 /* reg_ritr_ingress_counter_set_type 6520 * Igress Counter Set Type for router interface counter. 6521 * Access: RW 6522 */ 6523 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6524 6525 /* reg_ritr_egress_counter_index 6526 * Counter Index for flow counter. 6527 * Access: RW 6528 */ 6529 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6530 6531 /* reg_ritr_egress_counter_set_type 6532 * Egress Counter Set Type for router interface counter. 6533 * Access: RW 6534 */ 6535 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6536 6537 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6538 bool enable, bool egress) 6539 { 6540 enum mlxsw_reg_ritr_counter_set_type set_type; 6541 6542 if (enable) 6543 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6544 else 6545 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6546 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6547 6548 if (egress) 6549 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6550 else 6551 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6552 } 6553 6554 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6555 { 6556 MLXSW_REG_ZERO(ritr, payload); 6557 mlxsw_reg_ritr_rif_set(payload, rif); 6558 } 6559 6560 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6561 u16 system_port, u16 vid) 6562 { 6563 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6564 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6565 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6566 } 6567 6568 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6569 enum mlxsw_reg_ritr_if_type type, 6570 u16 rif, u16 vr_id, u16 mtu) 6571 { 6572 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6573 6574 MLXSW_REG_ZERO(ritr, payload); 6575 mlxsw_reg_ritr_enable_set(payload, enable); 6576 mlxsw_reg_ritr_ipv4_set(payload, 1); 6577 mlxsw_reg_ritr_ipv6_set(payload, 1); 6578 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6579 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6580 mlxsw_reg_ritr_type_set(payload, type); 6581 mlxsw_reg_ritr_op_set(payload, op); 6582 mlxsw_reg_ritr_rif_set(payload, rif); 6583 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6584 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6585 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6586 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6587 mlxsw_reg_ritr_lb_en_set(payload, 1); 6588 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6589 mlxsw_reg_ritr_mtu_set(payload, mtu); 6590 } 6591 6592 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6593 { 6594 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6595 } 6596 6597 static inline void 6598 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6599 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6600 enum mlxsw_reg_ritr_loopback_ipip_options options, 6601 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6602 { 6603 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6604 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6605 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6606 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6607 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6608 } 6609 6610 static inline void 6611 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6612 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6613 enum mlxsw_reg_ritr_loopback_ipip_options options, 6614 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6615 { 6616 mlxsw_reg_ritr_loopback_protocol_set(payload, 6617 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6618 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6619 uvr_id, underlay_rif, gre_key); 6620 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6621 } 6622 6623 /* RTAR - Router TCAM Allocation Register 6624 * -------------------------------------- 6625 * This register is used for allocation of regions in the TCAM table. 6626 */ 6627 #define MLXSW_REG_RTAR_ID 0x8004 6628 #define MLXSW_REG_RTAR_LEN 0x20 6629 6630 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6631 6632 enum mlxsw_reg_rtar_op { 6633 MLXSW_REG_RTAR_OP_ALLOCATE, 6634 MLXSW_REG_RTAR_OP_RESIZE, 6635 MLXSW_REG_RTAR_OP_DEALLOCATE, 6636 }; 6637 6638 /* reg_rtar_op 6639 * Access: WO 6640 */ 6641 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6642 6643 enum mlxsw_reg_rtar_key_type { 6644 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6645 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6646 }; 6647 6648 /* reg_rtar_key_type 6649 * TCAM key type for the region. 6650 * Access: WO 6651 */ 6652 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6653 6654 /* reg_rtar_region_size 6655 * TCAM region size. When allocating/resizing this is the requested 6656 * size, the response is the actual size. 6657 * Note: Actual size may be larger than requested. 6658 * Reserved for op = Deallocate 6659 * Access: WO 6660 */ 6661 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6662 6663 static inline void mlxsw_reg_rtar_pack(char *payload, 6664 enum mlxsw_reg_rtar_op op, 6665 enum mlxsw_reg_rtar_key_type key_type, 6666 u16 region_size) 6667 { 6668 MLXSW_REG_ZERO(rtar, payload); 6669 mlxsw_reg_rtar_op_set(payload, op); 6670 mlxsw_reg_rtar_key_type_set(payload, key_type); 6671 mlxsw_reg_rtar_region_size_set(payload, region_size); 6672 } 6673 6674 /* RATR - Router Adjacency Table Register 6675 * -------------------------------------- 6676 * The RATR register is used to configure the Router Adjacency (next-hop) 6677 * Table. 6678 */ 6679 #define MLXSW_REG_RATR_ID 0x8008 6680 #define MLXSW_REG_RATR_LEN 0x2C 6681 6682 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6683 6684 enum mlxsw_reg_ratr_op { 6685 /* Read */ 6686 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6687 /* Read and clear activity */ 6688 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6689 /* Write Adjacency entry */ 6690 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6691 /* Write Adjacency entry only if the activity is cleared. 6692 * The write may not succeed if the activity is set. There is not 6693 * direct feedback if the write has succeeded or not, however 6694 * the get will reveal the actual entry (SW can compare the get 6695 * response to the set command). 6696 */ 6697 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6698 }; 6699 6700 /* reg_ratr_op 6701 * Note that Write operation may also be used for updating 6702 * counter_set_type and counter_index. In this case all other 6703 * fields must not be updated. 6704 * Access: OP 6705 */ 6706 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6707 6708 /* reg_ratr_v 6709 * Valid bit. Indicates if the adjacency entry is valid. 6710 * Note: the device may need some time before reusing an invalidated 6711 * entry. During this time the entry can not be reused. It is 6712 * recommended to use another entry before reusing an invalidated 6713 * entry (e.g. software can put it at the end of the list for 6714 * reusing). Trying to access an invalidated entry not yet cleared 6715 * by the device results with failure indicating "Try Again" status. 6716 * When valid is '0' then egress_router_interface,trap_action, 6717 * adjacency_parameters and counters are reserved 6718 * Access: RW 6719 */ 6720 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6721 6722 /* reg_ratr_a 6723 * Activity. Set for new entries. Set if a packet lookup has hit on 6724 * the specific entry. To clear the a bit, use "clear activity". 6725 * Access: RO 6726 */ 6727 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6728 6729 enum mlxsw_reg_ratr_type { 6730 /* Ethernet */ 6731 MLXSW_REG_RATR_TYPE_ETHERNET, 6732 /* IPoIB Unicast without GRH. 6733 * Reserved for Spectrum. 6734 */ 6735 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6736 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6737 * adjacency). 6738 * Reserved for Spectrum. 6739 */ 6740 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6741 /* IPoIB Multicast. 6742 * Reserved for Spectrum. 6743 */ 6744 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6745 /* MPLS. 6746 * Reserved for SwitchX/-2. 6747 */ 6748 MLXSW_REG_RATR_TYPE_MPLS, 6749 /* IPinIP Encap. 6750 * Reserved for SwitchX/-2. 6751 */ 6752 MLXSW_REG_RATR_TYPE_IPIP, 6753 }; 6754 6755 /* reg_ratr_type 6756 * Adjacency entry type. 6757 * Access: RW 6758 */ 6759 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6760 6761 /* reg_ratr_adjacency_index_low 6762 * Bits 15:0 of index into the adjacency table. 6763 * For SwitchX and SwitchX-2, the adjacency table is linear and 6764 * used for adjacency entries only. 6765 * For Spectrum, the index is to the KVD linear. 6766 * Access: Index 6767 */ 6768 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6769 6770 /* reg_ratr_egress_router_interface 6771 * Range is 0 .. cap_max_router_interfaces - 1 6772 * Access: RW 6773 */ 6774 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6775 6776 enum mlxsw_reg_ratr_trap_action { 6777 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6778 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6779 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6780 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6781 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6782 }; 6783 6784 /* reg_ratr_trap_action 6785 * see mlxsw_reg_ratr_trap_action 6786 * Access: RW 6787 */ 6788 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6789 6790 /* reg_ratr_adjacency_index_high 6791 * Bits 23:16 of the adjacency_index. 6792 * Access: Index 6793 */ 6794 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6795 6796 enum mlxsw_reg_ratr_trap_id { 6797 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6798 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6799 }; 6800 6801 /* reg_ratr_trap_id 6802 * Trap ID to be reported to CPU. 6803 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6804 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6805 * Access: RW 6806 */ 6807 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6808 6809 /* reg_ratr_eth_destination_mac 6810 * MAC address of the destination next-hop. 6811 * Access: RW 6812 */ 6813 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6814 6815 enum mlxsw_reg_ratr_ipip_type { 6816 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6817 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6818 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6819 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6820 }; 6821 6822 /* reg_ratr_ipip_type 6823 * Underlay destination ip type. 6824 * Note: the type field must match the protocol of the router interface. 6825 * Access: RW 6826 */ 6827 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6828 6829 /* reg_ratr_ipip_ipv4_udip 6830 * Underlay ipv4 dip. 6831 * Reserved when ipip_type is IPv6. 6832 * Access: RW 6833 */ 6834 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6835 6836 /* reg_ratr_ipip_ipv6_ptr 6837 * Pointer to IPv6 underlay destination ip address. 6838 * For Spectrum: Pointer to KVD linear space. 6839 * Access: RW 6840 */ 6841 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6842 6843 enum mlxsw_reg_flow_counter_set_type { 6844 /* No count */ 6845 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6846 /* Count packets and bytes */ 6847 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6848 /* Count only packets */ 6849 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6850 }; 6851 6852 /* reg_ratr_counter_set_type 6853 * Counter set type for flow counters 6854 * Access: RW 6855 */ 6856 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6857 6858 /* reg_ratr_counter_index 6859 * Counter index for flow counters 6860 * Access: RW 6861 */ 6862 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6863 6864 static inline void 6865 mlxsw_reg_ratr_pack(char *payload, 6866 enum mlxsw_reg_ratr_op op, bool valid, 6867 enum mlxsw_reg_ratr_type type, 6868 u32 adjacency_index, u16 egress_rif) 6869 { 6870 MLXSW_REG_ZERO(ratr, payload); 6871 mlxsw_reg_ratr_op_set(payload, op); 6872 mlxsw_reg_ratr_v_set(payload, valid); 6873 mlxsw_reg_ratr_type_set(payload, type); 6874 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6875 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6876 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6877 } 6878 6879 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6880 const char *dest_mac) 6881 { 6882 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6883 } 6884 6885 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6886 { 6887 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6888 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6889 } 6890 6891 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6892 bool counter_enable) 6893 { 6894 enum mlxsw_reg_flow_counter_set_type set_type; 6895 6896 if (counter_enable) 6897 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6898 else 6899 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6900 6901 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6902 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6903 } 6904 6905 /* RDPM - Router DSCP to Priority Mapping 6906 * -------------------------------------- 6907 * Controls the mapping from DSCP field to switch priority on routed packets 6908 */ 6909 #define MLXSW_REG_RDPM_ID 0x8009 6910 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6911 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6912 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6913 #define MLXSW_REG_RDPM_LEN 0x40 6914 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6915 MLXSW_REG_RDPM_LEN - \ 6916 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6917 6918 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6919 6920 /* reg_dscp_entry_e 6921 * Enable update of the specific entry 6922 * Access: Index 6923 */ 6924 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6925 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6926 6927 /* reg_dscp_entry_prio 6928 * Switch Priority 6929 * Access: RW 6930 */ 6931 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6932 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6933 6934 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6935 u8 prio) 6936 { 6937 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6938 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6939 } 6940 6941 /* RICNT - Router Interface Counter Register 6942 * ----------------------------------------- 6943 * The RICNT register retrieves per port performance counters 6944 */ 6945 #define MLXSW_REG_RICNT_ID 0x800B 6946 #define MLXSW_REG_RICNT_LEN 0x100 6947 6948 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6949 6950 /* reg_ricnt_counter_index 6951 * Counter index 6952 * Access: RW 6953 */ 6954 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6955 6956 enum mlxsw_reg_ricnt_counter_set_type { 6957 /* No Count. */ 6958 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6959 /* Basic. Used for router interfaces, counting the following: 6960 * - Error and Discard counters. 6961 * - Unicast, Multicast and Broadcast counters. Sharing the 6962 * same set of counters for the different type of traffic 6963 * (IPv4, IPv6 and mpls). 6964 */ 6965 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6966 }; 6967 6968 /* reg_ricnt_counter_set_type 6969 * Counter Set Type for router interface counter 6970 * Access: RW 6971 */ 6972 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6973 6974 enum mlxsw_reg_ricnt_opcode { 6975 /* Nop. Supported only for read access*/ 6976 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6977 /* Clear. Setting the clr bit will reset the counter value for 6978 * all counters of the specified Router Interface. 6979 */ 6980 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6981 }; 6982 6983 /* reg_ricnt_opcode 6984 * Opcode 6985 * Access: RW 6986 */ 6987 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6988 6989 /* reg_ricnt_good_unicast_packets 6990 * good unicast packets. 6991 * Access: RW 6992 */ 6993 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6994 6995 /* reg_ricnt_good_multicast_packets 6996 * good multicast packets. 6997 * Access: RW 6998 */ 6999 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7000 7001 /* reg_ricnt_good_broadcast_packets 7002 * good broadcast packets 7003 * Access: RW 7004 */ 7005 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7006 7007 /* reg_ricnt_good_unicast_bytes 7008 * A count of L3 data and padding octets not including L2 headers 7009 * for good unicast frames. 7010 * Access: RW 7011 */ 7012 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7013 7014 /* reg_ricnt_good_multicast_bytes 7015 * A count of L3 data and padding octets not including L2 headers 7016 * for good multicast frames. 7017 * Access: RW 7018 */ 7019 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7020 7021 /* reg_ritr_good_broadcast_bytes 7022 * A count of L3 data and padding octets not including L2 headers 7023 * for good broadcast frames. 7024 * Access: RW 7025 */ 7026 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7027 7028 /* reg_ricnt_error_packets 7029 * A count of errored frames that do not pass the router checks. 7030 * Access: RW 7031 */ 7032 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7033 7034 /* reg_ricnt_discrad_packets 7035 * A count of non-errored frames that do not pass the router checks. 7036 * Access: RW 7037 */ 7038 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7039 7040 /* reg_ricnt_error_bytes 7041 * A count of L3 data and padding octets not including L2 headers 7042 * for errored frames. 7043 * Access: RW 7044 */ 7045 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7046 7047 /* reg_ricnt_discard_bytes 7048 * A count of L3 data and padding octets not including L2 headers 7049 * for non-errored frames that do not pass the router checks. 7050 * Access: RW 7051 */ 7052 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7053 7054 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7055 enum mlxsw_reg_ricnt_opcode op) 7056 { 7057 MLXSW_REG_ZERO(ricnt, payload); 7058 mlxsw_reg_ricnt_op_set(payload, op); 7059 mlxsw_reg_ricnt_counter_index_set(payload, index); 7060 mlxsw_reg_ricnt_counter_set_type_set(payload, 7061 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7062 } 7063 7064 /* RRCR - Router Rules Copy Register Layout 7065 * ---------------------------------------- 7066 * This register is used for moving and copying route entry rules. 7067 */ 7068 #define MLXSW_REG_RRCR_ID 0x800F 7069 #define MLXSW_REG_RRCR_LEN 0x24 7070 7071 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7072 7073 enum mlxsw_reg_rrcr_op { 7074 /* Move rules */ 7075 MLXSW_REG_RRCR_OP_MOVE, 7076 /* Copy rules */ 7077 MLXSW_REG_RRCR_OP_COPY, 7078 }; 7079 7080 /* reg_rrcr_op 7081 * Access: WO 7082 */ 7083 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7084 7085 /* reg_rrcr_offset 7086 * Offset within the region from which to copy/move. 7087 * Access: Index 7088 */ 7089 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7090 7091 /* reg_rrcr_size 7092 * The number of rules to copy/move. 7093 * Access: WO 7094 */ 7095 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7096 7097 /* reg_rrcr_table_id 7098 * Identifier of the table on which to perform the operation. Encoding is the 7099 * same as in RTAR.key_type 7100 * Access: Index 7101 */ 7102 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7103 7104 /* reg_rrcr_dest_offset 7105 * Offset within the region to which to copy/move 7106 * Access: Index 7107 */ 7108 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7109 7110 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7111 u16 offset, u16 size, 7112 enum mlxsw_reg_rtar_key_type table_id, 7113 u16 dest_offset) 7114 { 7115 MLXSW_REG_ZERO(rrcr, payload); 7116 mlxsw_reg_rrcr_op_set(payload, op); 7117 mlxsw_reg_rrcr_offset_set(payload, offset); 7118 mlxsw_reg_rrcr_size_set(payload, size); 7119 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7120 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7121 } 7122 7123 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7124 * ------------------------------------------------------- 7125 * RALTA is used to allocate the LPM trees of the SHSPM method. 7126 */ 7127 #define MLXSW_REG_RALTA_ID 0x8010 7128 #define MLXSW_REG_RALTA_LEN 0x04 7129 7130 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7131 7132 /* reg_ralta_op 7133 * opcode (valid for Write, must be 0 on Read) 7134 * 0 - allocate a tree 7135 * 1 - deallocate a tree 7136 * Access: OP 7137 */ 7138 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7139 7140 enum mlxsw_reg_ralxx_protocol { 7141 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7142 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7143 }; 7144 7145 /* reg_ralta_protocol 7146 * Protocol. 7147 * Deallocation opcode: Reserved. 7148 * Access: RW 7149 */ 7150 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7151 7152 /* reg_ralta_tree_id 7153 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7154 * the tree identifier (managed by software). 7155 * Note that tree_id 0 is allocated for a default-route tree. 7156 * Access: Index 7157 */ 7158 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7159 7160 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7161 enum mlxsw_reg_ralxx_protocol protocol, 7162 u8 tree_id) 7163 { 7164 MLXSW_REG_ZERO(ralta, payload); 7165 mlxsw_reg_ralta_op_set(payload, !alloc); 7166 mlxsw_reg_ralta_protocol_set(payload, protocol); 7167 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7168 } 7169 7170 /* RALST - Router Algorithmic LPM Structure Tree Register 7171 * ------------------------------------------------------ 7172 * RALST is used to set and query the structure of an LPM tree. 7173 * The structure of the tree must be sorted as a sorted binary tree, while 7174 * each node is a bin that is tagged as the length of the prefixes the lookup 7175 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7176 * of X bits to match with the destination address. The bin 0 indicates 7177 * the default action, when there is no match of any prefix. 7178 */ 7179 #define MLXSW_REG_RALST_ID 0x8011 7180 #define MLXSW_REG_RALST_LEN 0x104 7181 7182 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7183 7184 /* reg_ralst_root_bin 7185 * The bin number of the root bin. 7186 * 0<root_bin=<(length of IP address) 7187 * For a default-route tree configure 0xff 7188 * Access: RW 7189 */ 7190 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7191 7192 /* reg_ralst_tree_id 7193 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7194 * Access: Index 7195 */ 7196 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7197 7198 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7199 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7200 #define MLXSW_REG_RALST_BIN_COUNT 128 7201 7202 /* reg_ralst_left_child_bin 7203 * Holding the children of the bin according to the stored tree's structure. 7204 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7205 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7206 * Access: RW 7207 */ 7208 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7209 7210 /* reg_ralst_right_child_bin 7211 * Holding the children of the bin according to the stored tree's structure. 7212 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7213 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7214 * Access: RW 7215 */ 7216 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7217 false); 7218 7219 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7220 { 7221 MLXSW_REG_ZERO(ralst, payload); 7222 7223 /* Initialize all bins to have no left or right child */ 7224 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7225 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7226 7227 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7228 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7229 } 7230 7231 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7232 u8 left_child_bin, 7233 u8 right_child_bin) 7234 { 7235 int bin_index = bin_number - 1; 7236 7237 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7238 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7239 right_child_bin); 7240 } 7241 7242 /* RALTB - Router Algorithmic LPM Tree Binding Register 7243 * ---------------------------------------------------- 7244 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7245 */ 7246 #define MLXSW_REG_RALTB_ID 0x8012 7247 #define MLXSW_REG_RALTB_LEN 0x04 7248 7249 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7250 7251 /* reg_raltb_virtual_router 7252 * Virtual Router ID 7253 * Range is 0..cap_max_virtual_routers-1 7254 * Access: Index 7255 */ 7256 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7257 7258 /* reg_raltb_protocol 7259 * Protocol. 7260 * Access: Index 7261 */ 7262 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7263 7264 /* reg_raltb_tree_id 7265 * Tree to be used for the {virtual_router, protocol} 7266 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7267 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7268 * Access: RW 7269 */ 7270 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7271 7272 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7273 enum mlxsw_reg_ralxx_protocol protocol, 7274 u8 tree_id) 7275 { 7276 MLXSW_REG_ZERO(raltb, payload); 7277 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7278 mlxsw_reg_raltb_protocol_set(payload, protocol); 7279 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7280 } 7281 7282 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7283 * ----------------------------------------------------- 7284 * RALUE is used to configure and query LPM entries that serve 7285 * the Unicast protocols. 7286 */ 7287 #define MLXSW_REG_RALUE_ID 0x8013 7288 #define MLXSW_REG_RALUE_LEN 0x38 7289 7290 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7291 7292 /* reg_ralue_protocol 7293 * Protocol. 7294 * Access: Index 7295 */ 7296 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7297 7298 enum mlxsw_reg_ralue_op { 7299 /* Read operation. If entry doesn't exist, the operation fails. */ 7300 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7301 /* Clear on read operation. Used to read entry and 7302 * clear Activity bit. 7303 */ 7304 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7305 /* Write operation. Used to write a new entry to the table. All RW 7306 * fields are written for new entry. Activity bit is set 7307 * for new entries. 7308 */ 7309 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7310 /* Update operation. Used to update an existing route entry and 7311 * only update the RW fields that are detailed in the field 7312 * op_u_mask. If entry doesn't exist, the operation fails. 7313 */ 7314 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7315 /* Clear activity. The Activity bit (the field a) is cleared 7316 * for the entry. 7317 */ 7318 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7319 /* Delete operation. Used to delete an existing entry. If entry 7320 * doesn't exist, the operation fails. 7321 */ 7322 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7323 }; 7324 7325 /* reg_ralue_op 7326 * Operation. 7327 * Access: OP 7328 */ 7329 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7330 7331 /* reg_ralue_a 7332 * Activity. Set for new entries. Set if a packet lookup has hit on the 7333 * specific entry, only if the entry is a route. To clear the a bit, use 7334 * "clear activity" op. 7335 * Enabled by activity_dis in RGCR 7336 * Access: RO 7337 */ 7338 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7339 7340 /* reg_ralue_virtual_router 7341 * Virtual Router ID 7342 * Range is 0..cap_max_virtual_routers-1 7343 * Access: Index 7344 */ 7345 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7346 7347 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7348 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7349 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7350 7351 /* reg_ralue_op_u_mask 7352 * opcode update mask. 7353 * On read operation, this field is reserved. 7354 * This field is valid for update opcode, otherwise - reserved. 7355 * This field is a bitmask of the fields that should be updated. 7356 * Access: WO 7357 */ 7358 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7359 7360 /* reg_ralue_prefix_len 7361 * Number of bits in the prefix of the LPM route. 7362 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7363 * two entries in the physical HW table. 7364 * Access: Index 7365 */ 7366 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7367 7368 /* reg_ralue_dip* 7369 * The prefix of the route or of the marker that the object of the LPM 7370 * is compared with. The most significant bits of the dip are the prefix. 7371 * The least significant bits must be '0' if the prefix_len is smaller 7372 * than 128 for IPv6 or smaller than 32 for IPv4. 7373 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7374 * Access: Index 7375 */ 7376 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7377 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7378 7379 enum mlxsw_reg_ralue_entry_type { 7380 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7381 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7382 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7383 }; 7384 7385 /* reg_ralue_entry_type 7386 * Entry type. 7387 * Note - for Marker entries, the action_type and action fields are reserved. 7388 * Access: RW 7389 */ 7390 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7391 7392 /* reg_ralue_bmp_len 7393 * The best match prefix length in the case that there is no match for 7394 * longer prefixes. 7395 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7396 * Note for any update operation with entry_type modification this 7397 * field must be set. 7398 * Access: RW 7399 */ 7400 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7401 7402 enum mlxsw_reg_ralue_action_type { 7403 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7404 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7405 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7406 }; 7407 7408 /* reg_ralue_action_type 7409 * Action Type 7410 * Indicates how the IP address is connected. 7411 * It can be connected to a local subnet through local_erif or can be 7412 * on a remote subnet connected through a next-hop router, 7413 * or transmitted to the CPU. 7414 * Reserved when entry_type = MARKER_ENTRY 7415 * Access: RW 7416 */ 7417 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7418 7419 enum mlxsw_reg_ralue_trap_action { 7420 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7421 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7422 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7423 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7424 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7425 }; 7426 7427 /* reg_ralue_trap_action 7428 * Trap action. 7429 * For IP2ME action, only NOP and MIRROR are possible. 7430 * Access: RW 7431 */ 7432 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7433 7434 /* reg_ralue_trap_id 7435 * Trap ID to be reported to CPU. 7436 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7437 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7438 * Access: RW 7439 */ 7440 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7441 7442 /* reg_ralue_adjacency_index 7443 * Points to the first entry of the group-based ECMP. 7444 * Only relevant in case of REMOTE action. 7445 * Access: RW 7446 */ 7447 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7448 7449 /* reg_ralue_ecmp_size 7450 * Amount of sequential entries starting 7451 * from the adjacency_index (the number of ECMPs). 7452 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7453 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7454 * Only relevant in case of REMOTE action. 7455 * Access: RW 7456 */ 7457 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7458 7459 /* reg_ralue_local_erif 7460 * Egress Router Interface. 7461 * Only relevant in case of LOCAL action. 7462 * Access: RW 7463 */ 7464 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7465 7466 /* reg_ralue_ip2me_v 7467 * Valid bit for the tunnel_ptr field. 7468 * If valid = 0 then trap to CPU as IP2ME trap ID. 7469 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7470 * decapsulation then tunnel decapsulation is done. 7471 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7472 * decapsulation then trap as IP2ME trap ID. 7473 * Only relevant in case of IP2ME action. 7474 * Access: RW 7475 */ 7476 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7477 7478 /* reg_ralue_ip2me_tunnel_ptr 7479 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7480 * For Spectrum, pointer to KVD Linear. 7481 * Only relevant in case of IP2ME action. 7482 * Access: RW 7483 */ 7484 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7485 7486 static inline void mlxsw_reg_ralue_pack(char *payload, 7487 enum mlxsw_reg_ralxx_protocol protocol, 7488 enum mlxsw_reg_ralue_op op, 7489 u16 virtual_router, u8 prefix_len) 7490 { 7491 MLXSW_REG_ZERO(ralue, payload); 7492 mlxsw_reg_ralue_protocol_set(payload, protocol); 7493 mlxsw_reg_ralue_op_set(payload, op); 7494 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7495 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7496 mlxsw_reg_ralue_entry_type_set(payload, 7497 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7498 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7499 } 7500 7501 static inline void mlxsw_reg_ralue_pack4(char *payload, 7502 enum mlxsw_reg_ralxx_protocol protocol, 7503 enum mlxsw_reg_ralue_op op, 7504 u16 virtual_router, u8 prefix_len, 7505 u32 *dip) 7506 { 7507 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7508 if (dip) 7509 mlxsw_reg_ralue_dip4_set(payload, *dip); 7510 } 7511 7512 static inline void mlxsw_reg_ralue_pack6(char *payload, 7513 enum mlxsw_reg_ralxx_protocol protocol, 7514 enum mlxsw_reg_ralue_op op, 7515 u16 virtual_router, u8 prefix_len, 7516 const void *dip) 7517 { 7518 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7519 if (dip) 7520 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7521 } 7522 7523 static inline void 7524 mlxsw_reg_ralue_act_remote_pack(char *payload, 7525 enum mlxsw_reg_ralue_trap_action trap_action, 7526 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7527 { 7528 mlxsw_reg_ralue_action_type_set(payload, 7529 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7530 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7531 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7532 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7533 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7534 } 7535 7536 static inline void 7537 mlxsw_reg_ralue_act_local_pack(char *payload, 7538 enum mlxsw_reg_ralue_trap_action trap_action, 7539 u16 trap_id, u16 local_erif) 7540 { 7541 mlxsw_reg_ralue_action_type_set(payload, 7542 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7543 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7544 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7545 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7546 } 7547 7548 static inline void 7549 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7550 { 7551 mlxsw_reg_ralue_action_type_set(payload, 7552 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7553 } 7554 7555 static inline void 7556 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7557 { 7558 mlxsw_reg_ralue_action_type_set(payload, 7559 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7560 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7561 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7562 } 7563 7564 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7565 * ---------------------------------------------------------- 7566 * The RAUHT register is used to configure and query the Unicast Host table in 7567 * devices that implement the Algorithmic LPM. 7568 */ 7569 #define MLXSW_REG_RAUHT_ID 0x8014 7570 #define MLXSW_REG_RAUHT_LEN 0x74 7571 7572 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7573 7574 enum mlxsw_reg_rauht_type { 7575 MLXSW_REG_RAUHT_TYPE_IPV4, 7576 MLXSW_REG_RAUHT_TYPE_IPV6, 7577 }; 7578 7579 /* reg_rauht_type 7580 * Access: Index 7581 */ 7582 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7583 7584 enum mlxsw_reg_rauht_op { 7585 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7586 /* Read operation */ 7587 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7588 /* Clear on read operation. Used to read entry and clear 7589 * activity bit. 7590 */ 7591 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7592 /* Add. Used to write a new entry to the table. All R/W fields are 7593 * relevant for new entry. Activity bit is set for new entries. 7594 */ 7595 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7596 /* Update action. Used to update an existing route entry and 7597 * only update the following fields: 7598 * trap_action, trap_id, mac, counter_set_type, counter_index 7599 */ 7600 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7601 /* Clear activity. A bit is cleared for the entry. */ 7602 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7603 /* Delete entry */ 7604 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7605 /* Delete all host entries on a RIF. In this command, dip 7606 * field is reserved. 7607 */ 7608 }; 7609 7610 /* reg_rauht_op 7611 * Access: OP 7612 */ 7613 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7614 7615 /* reg_rauht_a 7616 * Activity. Set for new entries. Set if a packet lookup has hit on 7617 * the specific entry. 7618 * To clear the a bit, use "clear activity" op. 7619 * Enabled by activity_dis in RGCR 7620 * Access: RO 7621 */ 7622 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7623 7624 /* reg_rauht_rif 7625 * Router Interface 7626 * Access: Index 7627 */ 7628 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7629 7630 /* reg_rauht_dip* 7631 * Destination address. 7632 * Access: Index 7633 */ 7634 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7635 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7636 7637 enum mlxsw_reg_rauht_trap_action { 7638 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7639 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7640 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7641 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7642 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7643 }; 7644 7645 /* reg_rauht_trap_action 7646 * Access: RW 7647 */ 7648 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7649 7650 enum mlxsw_reg_rauht_trap_id { 7651 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7652 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7653 }; 7654 7655 /* reg_rauht_trap_id 7656 * Trap ID to be reported to CPU. 7657 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7658 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7659 * trap_id is reserved. 7660 * Access: RW 7661 */ 7662 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7663 7664 /* reg_rauht_counter_set_type 7665 * Counter set type for flow counters 7666 * Access: RW 7667 */ 7668 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7669 7670 /* reg_rauht_counter_index 7671 * Counter index for flow counters 7672 * Access: RW 7673 */ 7674 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7675 7676 /* reg_rauht_mac 7677 * MAC address. 7678 * Access: RW 7679 */ 7680 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7681 7682 static inline void mlxsw_reg_rauht_pack(char *payload, 7683 enum mlxsw_reg_rauht_op op, u16 rif, 7684 const char *mac) 7685 { 7686 MLXSW_REG_ZERO(rauht, payload); 7687 mlxsw_reg_rauht_op_set(payload, op); 7688 mlxsw_reg_rauht_rif_set(payload, rif); 7689 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7690 } 7691 7692 static inline void mlxsw_reg_rauht_pack4(char *payload, 7693 enum mlxsw_reg_rauht_op op, u16 rif, 7694 const char *mac, u32 dip) 7695 { 7696 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7697 mlxsw_reg_rauht_dip4_set(payload, dip); 7698 } 7699 7700 static inline void mlxsw_reg_rauht_pack6(char *payload, 7701 enum mlxsw_reg_rauht_op op, u16 rif, 7702 const char *mac, const char *dip) 7703 { 7704 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7705 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7706 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7707 } 7708 7709 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7710 u64 counter_index) 7711 { 7712 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7713 mlxsw_reg_rauht_counter_set_type_set(payload, 7714 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7715 } 7716 7717 /* RALEU - Router Algorithmic LPM ECMP Update Register 7718 * --------------------------------------------------- 7719 * The register enables updating the ECMP section in the action for multiple 7720 * LPM Unicast entries in a single operation. The update is executed to 7721 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7722 */ 7723 #define MLXSW_REG_RALEU_ID 0x8015 7724 #define MLXSW_REG_RALEU_LEN 0x28 7725 7726 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7727 7728 /* reg_raleu_protocol 7729 * Protocol. 7730 * Access: Index 7731 */ 7732 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7733 7734 /* reg_raleu_virtual_router 7735 * Virtual Router ID 7736 * Range is 0..cap_max_virtual_routers-1 7737 * Access: Index 7738 */ 7739 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7740 7741 /* reg_raleu_adjacency_index 7742 * Adjacency Index used for matching on the existing entries. 7743 * Access: Index 7744 */ 7745 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7746 7747 /* reg_raleu_ecmp_size 7748 * ECMP Size used for matching on the existing entries. 7749 * Access: Index 7750 */ 7751 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7752 7753 /* reg_raleu_new_adjacency_index 7754 * New Adjacency Index. 7755 * Access: WO 7756 */ 7757 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7758 7759 /* reg_raleu_new_ecmp_size 7760 * New ECMP Size. 7761 * Access: WO 7762 */ 7763 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7764 7765 static inline void mlxsw_reg_raleu_pack(char *payload, 7766 enum mlxsw_reg_ralxx_protocol protocol, 7767 u16 virtual_router, 7768 u32 adjacency_index, u16 ecmp_size, 7769 u32 new_adjacency_index, 7770 u16 new_ecmp_size) 7771 { 7772 MLXSW_REG_ZERO(raleu, payload); 7773 mlxsw_reg_raleu_protocol_set(payload, protocol); 7774 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7775 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7776 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7777 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7778 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7779 } 7780 7781 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7782 * ---------------------------------------------------------------- 7783 * The RAUHTD register allows dumping entries from the Router Unicast Host 7784 * Table. For a given session an entry is dumped no more than one time. The 7785 * first RAUHTD access after reset is a new session. A session ends when the 7786 * num_rec response is smaller than num_rec request or for IPv4 when the 7787 * num_entries is smaller than 4. The clear activity affect the current session 7788 * or the last session if a new session has not started. 7789 */ 7790 #define MLXSW_REG_RAUHTD_ID 0x8018 7791 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7792 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7793 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7794 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7795 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7796 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7797 7798 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7799 7800 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7801 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7802 7803 /* reg_rauhtd_filter_fields 7804 * if a bit is '0' then the relevant field is ignored and dump is done 7805 * regardless of the field value 7806 * Bit0 - filter by activity: entry_a 7807 * Bit3 - filter by entry rip: entry_rif 7808 * Access: Index 7809 */ 7810 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7811 7812 enum mlxsw_reg_rauhtd_op { 7813 MLXSW_REG_RAUHTD_OP_DUMP, 7814 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7815 }; 7816 7817 /* reg_rauhtd_op 7818 * Access: OP 7819 */ 7820 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7821 7822 /* reg_rauhtd_num_rec 7823 * At request: number of records requested 7824 * At response: number of records dumped 7825 * For IPv4, each record has 4 entries at request and up to 4 entries 7826 * at response 7827 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7828 * Access: Index 7829 */ 7830 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7831 7832 /* reg_rauhtd_entry_a 7833 * Dump only if activity has value of entry_a 7834 * Reserved if filter_fields bit0 is '0' 7835 * Access: Index 7836 */ 7837 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7838 7839 enum mlxsw_reg_rauhtd_type { 7840 MLXSW_REG_RAUHTD_TYPE_IPV4, 7841 MLXSW_REG_RAUHTD_TYPE_IPV6, 7842 }; 7843 7844 /* reg_rauhtd_type 7845 * Dump only if record type is: 7846 * 0 - IPv4 7847 * 1 - IPv6 7848 * Access: Index 7849 */ 7850 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7851 7852 /* reg_rauhtd_entry_rif 7853 * Dump only if RIF has value of entry_rif 7854 * Reserved if filter_fields bit3 is '0' 7855 * Access: Index 7856 */ 7857 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7858 7859 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7860 enum mlxsw_reg_rauhtd_type type) 7861 { 7862 MLXSW_REG_ZERO(rauhtd, payload); 7863 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7864 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7865 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7866 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7867 mlxsw_reg_rauhtd_type_set(payload, type); 7868 } 7869 7870 /* reg_rauhtd_ipv4_rec_num_entries 7871 * Number of valid entries in this record: 7872 * 0 - 1 valid entry 7873 * 1 - 2 valid entries 7874 * 2 - 3 valid entries 7875 * 3 - 4 valid entries 7876 * Access: RO 7877 */ 7878 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7879 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7880 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7881 7882 /* reg_rauhtd_rec_type 7883 * Record type. 7884 * 0 - IPv4 7885 * 1 - IPv6 7886 * Access: RO 7887 */ 7888 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7889 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7890 7891 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7892 7893 /* reg_rauhtd_ipv4_ent_a 7894 * Activity. Set for new entries. Set if a packet lookup has hit on the 7895 * specific entry. 7896 * Access: RO 7897 */ 7898 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7899 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7900 7901 /* reg_rauhtd_ipv4_ent_rif 7902 * Router interface. 7903 * Access: RO 7904 */ 7905 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7906 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7907 7908 /* reg_rauhtd_ipv4_ent_dip 7909 * Destination IPv4 address. 7910 * Access: RO 7911 */ 7912 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7913 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7914 7915 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7916 7917 /* reg_rauhtd_ipv6_ent_a 7918 * Activity. Set for new entries. Set if a packet lookup has hit on the 7919 * specific entry. 7920 * Access: RO 7921 */ 7922 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7923 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7924 7925 /* reg_rauhtd_ipv6_ent_rif 7926 * Router interface. 7927 * Access: RO 7928 */ 7929 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7930 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7931 7932 /* reg_rauhtd_ipv6_ent_dip 7933 * Destination IPv6 address. 7934 * Access: RO 7935 */ 7936 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7937 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7938 7939 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7940 int ent_index, u16 *p_rif, 7941 u32 *p_dip) 7942 { 7943 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7944 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7945 } 7946 7947 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7948 int rec_index, u16 *p_rif, 7949 char *p_dip) 7950 { 7951 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7952 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7953 } 7954 7955 /* RTDP - Routing Tunnel Decap Properties Register 7956 * ----------------------------------------------- 7957 * The RTDP register is used for configuring the tunnel decap properties of NVE 7958 * and IPinIP. 7959 */ 7960 #define MLXSW_REG_RTDP_ID 0x8020 7961 #define MLXSW_REG_RTDP_LEN 0x44 7962 7963 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7964 7965 enum mlxsw_reg_rtdp_type { 7966 MLXSW_REG_RTDP_TYPE_NVE, 7967 MLXSW_REG_RTDP_TYPE_IPIP, 7968 }; 7969 7970 /* reg_rtdp_type 7971 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7972 * Access: RW 7973 */ 7974 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7975 7976 /* reg_rtdp_tunnel_index 7977 * Index to the Decap entry. 7978 * For Spectrum, Index to KVD Linear. 7979 * Access: Index 7980 */ 7981 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7982 7983 /* reg_rtdp_egress_router_interface 7984 * Underlay egress router interface. 7985 * Valid range is from 0 to cap_max_router_interfaces - 1 7986 * Access: RW 7987 */ 7988 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7989 7990 /* IPinIP */ 7991 7992 /* reg_rtdp_ipip_irif 7993 * Ingress Router Interface for the overlay router 7994 * Access: RW 7995 */ 7996 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7997 7998 enum mlxsw_reg_rtdp_ipip_sip_check { 7999 /* No sip checks. */ 8000 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8001 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8002 * equal ipv4_usip. 8003 */ 8004 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8005 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8006 * equal ipv6_usip. 8007 */ 8008 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8009 }; 8010 8011 /* reg_rtdp_ipip_sip_check 8012 * SIP check to perform. If decapsulation failed due to these configurations 8013 * then trap_id is IPIP_DECAP_ERROR. 8014 * Access: RW 8015 */ 8016 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8017 8018 /* If set, allow decapsulation of IPinIP (without GRE). */ 8019 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8020 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8021 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8022 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8023 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8024 8025 /* reg_rtdp_ipip_type_check 8026 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8027 * these configurations then trap_id is IPIP_DECAP_ERROR. 8028 * Access: RW 8029 */ 8030 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8031 8032 /* reg_rtdp_ipip_gre_key_check 8033 * Whether GRE key should be checked. When check is enabled: 8034 * - A packet received as IPinIP (without GRE) will always pass. 8035 * - A packet received as IPinGREinIP without a key will not pass the check. 8036 * - A packet received as IPinGREinIP with a key will pass the check only if the 8037 * key in the packet is equal to expected_gre_key. 8038 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8039 * Access: RW 8040 */ 8041 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8042 8043 /* reg_rtdp_ipip_ipv4_usip 8044 * Underlay IPv4 address for ipv4 source address check. 8045 * Reserved when sip_check is not '1'. 8046 * Access: RW 8047 */ 8048 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8049 8050 /* reg_rtdp_ipip_ipv6_usip_ptr 8051 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8052 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8053 * is to the KVD linear. 8054 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8055 * Access: RW 8056 */ 8057 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8058 8059 /* reg_rtdp_ipip_expected_gre_key 8060 * GRE key for checking. 8061 * Reserved when gre_key_check is '0'. 8062 * Access: RW 8063 */ 8064 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8065 8066 static inline void mlxsw_reg_rtdp_pack(char *payload, 8067 enum mlxsw_reg_rtdp_type type, 8068 u32 tunnel_index) 8069 { 8070 MLXSW_REG_ZERO(rtdp, payload); 8071 mlxsw_reg_rtdp_type_set(payload, type); 8072 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8073 } 8074 8075 static inline void 8076 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8077 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8078 unsigned int type_check, bool gre_key_check, 8079 u32 ipv4_usip, u32 expected_gre_key) 8080 { 8081 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8082 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8083 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8084 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8085 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8086 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8087 } 8088 8089 /* RIGR-V2 - Router Interface Group Register Version 2 8090 * --------------------------------------------------- 8091 * The RIGR_V2 register is used to add, remove and query egress interface list 8092 * of a multicast forwarding entry. 8093 */ 8094 #define MLXSW_REG_RIGR2_ID 0x8023 8095 #define MLXSW_REG_RIGR2_LEN 0xB0 8096 8097 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8098 8099 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8100 8101 /* reg_rigr2_rigr_index 8102 * KVD Linear index. 8103 * Access: Index 8104 */ 8105 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8106 8107 /* reg_rigr2_vnext 8108 * Next RIGR Index is valid. 8109 * Access: RW 8110 */ 8111 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8112 8113 /* reg_rigr2_next_rigr_index 8114 * Next RIGR Index. The index is to the KVD linear. 8115 * Reserved when vnxet = '0'. 8116 * Access: RW 8117 */ 8118 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8119 8120 /* reg_rigr2_vrmid 8121 * RMID Index is valid. 8122 * Access: RW 8123 */ 8124 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8125 8126 /* reg_rigr2_rmid_index 8127 * RMID Index. 8128 * Range 0 .. max_mid - 1 8129 * Reserved when vrmid = '0'. 8130 * The index is to the Port Group Table (PGT) 8131 * Access: RW 8132 */ 8133 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8134 8135 /* reg_rigr2_erif_entry_v 8136 * Egress Router Interface is valid. 8137 * Note that low-entries must be set if high-entries are set. For 8138 * example: if erif_entry[2].v is set then erif_entry[1].v and 8139 * erif_entry[0].v must be set. 8140 * Index can be from 0 to cap_mc_erif_list_entries-1 8141 * Access: RW 8142 */ 8143 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8144 8145 /* reg_rigr2_erif_entry_erif 8146 * Egress Router Interface. 8147 * Valid range is from 0 to cap_max_router_interfaces - 1 8148 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8149 * Access: RW 8150 */ 8151 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8152 8153 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8154 bool vnext, u32 next_rigr_index) 8155 { 8156 MLXSW_REG_ZERO(rigr2, payload); 8157 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8158 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8159 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8160 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8161 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8162 } 8163 8164 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8165 bool v, u16 erif) 8166 { 8167 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8168 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8169 } 8170 8171 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8172 * ------------------------------------------------------ 8173 */ 8174 #define MLXSW_REG_RECR2_ID 0x8025 8175 #define MLXSW_REG_RECR2_LEN 0x38 8176 8177 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8178 8179 /* reg_recr2_pp 8180 * Per-port configuration 8181 * Access: Index 8182 */ 8183 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8184 8185 /* reg_recr2_sh 8186 * Symmetric hash 8187 * Access: RW 8188 */ 8189 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8190 8191 /* reg_recr2_seed 8192 * Seed 8193 * Access: RW 8194 */ 8195 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8196 8197 enum { 8198 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8199 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8200 /* Enable IPv4 fields if packet is TCP or UDP */ 8201 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8202 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8203 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8204 /* Enable IPv6 fields if packet is TCP or UDP */ 8205 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8206 /* Enable TCP/UDP header fields if packet is IPv4 */ 8207 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8208 /* Enable TCP/UDP header fields if packet is IPv6 */ 8209 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8210 }; 8211 8212 /* reg_recr2_outer_header_enables 8213 * Bit mask where each bit enables a specific layer to be included in 8214 * the hash calculation. 8215 * Access: RW 8216 */ 8217 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8218 8219 enum { 8220 /* IPv4 Source IP */ 8221 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8222 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8223 /* IPv4 Destination IP */ 8224 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8225 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8226 /* IP Protocol */ 8227 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8228 /* IPv6 Source IP */ 8229 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8230 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8231 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8232 /* IPv6 Destination IP */ 8233 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8234 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8235 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8236 /* IPv6 Next Header */ 8237 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8238 /* IPv6 Flow Label */ 8239 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8240 /* TCP/UDP Source Port */ 8241 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8242 /* TCP/UDP Destination Port */ 8243 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8244 }; 8245 8246 /* reg_recr2_outer_header_fields_enable 8247 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8248 * Access: RW 8249 */ 8250 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8251 8252 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 8253 { 8254 int i; 8255 8256 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 8257 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8258 true); 8259 } 8260 8261 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 8262 { 8263 int i; 8264 8265 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 8266 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8267 true); 8268 } 8269 8270 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 8271 { 8272 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 8273 8274 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8275 8276 i = MLXSW_REG_RECR2_IPV6_SIP8; 8277 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 8278 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8279 true); 8280 } 8281 8282 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 8283 { 8284 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 8285 8286 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8287 8288 i = MLXSW_REG_RECR2_IPV6_DIP8; 8289 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 8290 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8291 true); 8292 } 8293 8294 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8295 { 8296 MLXSW_REG_ZERO(recr2, payload); 8297 mlxsw_reg_recr2_pp_set(payload, false); 8298 mlxsw_reg_recr2_sh_set(payload, true); 8299 mlxsw_reg_recr2_seed_set(payload, seed); 8300 } 8301 8302 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8303 * -------------------------------------------------------------- 8304 * The RMFT_V2 register is used to configure and query the multicast table. 8305 */ 8306 #define MLXSW_REG_RMFT2_ID 0x8027 8307 #define MLXSW_REG_RMFT2_LEN 0x174 8308 8309 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8310 8311 /* reg_rmft2_v 8312 * Valid 8313 * Access: RW 8314 */ 8315 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8316 8317 enum mlxsw_reg_rmft2_type { 8318 MLXSW_REG_RMFT2_TYPE_IPV4, 8319 MLXSW_REG_RMFT2_TYPE_IPV6 8320 }; 8321 8322 /* reg_rmft2_type 8323 * Access: Index 8324 */ 8325 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8326 8327 enum mlxsw_sp_reg_rmft2_op { 8328 /* For Write: 8329 * Write operation. Used to write a new entry to the table. All RW 8330 * fields are relevant for new entry. Activity bit is set for new 8331 * entries - Note write with v (Valid) 0 will delete the entry. 8332 * For Query: 8333 * Read operation 8334 */ 8335 MLXSW_REG_RMFT2_OP_READ_WRITE, 8336 }; 8337 8338 /* reg_rmft2_op 8339 * Operation. 8340 * Access: OP 8341 */ 8342 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8343 8344 /* reg_rmft2_a 8345 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8346 * entry. 8347 * Access: RO 8348 */ 8349 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8350 8351 /* reg_rmft2_offset 8352 * Offset within the multicast forwarding table to write to. 8353 * Access: Index 8354 */ 8355 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8356 8357 /* reg_rmft2_virtual_router 8358 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8359 * Access: RW 8360 */ 8361 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8362 8363 enum mlxsw_reg_rmft2_irif_mask { 8364 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8365 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8366 }; 8367 8368 /* reg_rmft2_irif_mask 8369 * Ingress RIF mask. 8370 * Access: RW 8371 */ 8372 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8373 8374 /* reg_rmft2_irif 8375 * Ingress RIF index. 8376 * Access: RW 8377 */ 8378 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8379 8380 /* reg_rmft2_dip{4,6} 8381 * Destination IPv4/6 address 8382 * Access: RW 8383 */ 8384 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8385 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8386 8387 /* reg_rmft2_dip{4,6}_mask 8388 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8389 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8390 * Access: RW 8391 */ 8392 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8393 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8394 8395 /* reg_rmft2_sip{4,6} 8396 * Source IPv4/6 address 8397 * Access: RW 8398 */ 8399 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8400 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8401 8402 /* reg_rmft2_sip{4,6}_mask 8403 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8404 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8405 * Access: RW 8406 */ 8407 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8408 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8409 8410 /* reg_rmft2_flexible_action_set 8411 * ACL action set. The only supported action types in this field and in any 8412 * action-set pointed from here are as follows: 8413 * 00h: ACTION_NULL 8414 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8415 * 03h: ACTION_TRAP 8416 * 06h: ACTION_QOS 8417 * 08h: ACTION_POLICING_MONITORING 8418 * 10h: ACTION_ROUTER_MC 8419 * Access: RW 8420 */ 8421 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8422 MLXSW_REG_FLEX_ACTION_SET_LEN); 8423 8424 static inline void 8425 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8426 u16 virtual_router, 8427 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8428 const char *flex_action_set) 8429 { 8430 MLXSW_REG_ZERO(rmft2, payload); 8431 mlxsw_reg_rmft2_v_set(payload, v); 8432 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8433 mlxsw_reg_rmft2_offset_set(payload, offset); 8434 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8435 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8436 mlxsw_reg_rmft2_irif_set(payload, irif); 8437 if (flex_action_set) 8438 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8439 flex_action_set); 8440 } 8441 8442 static inline void 8443 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8444 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8445 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8446 const char *flexible_action_set) 8447 { 8448 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8449 irif_mask, irif, flexible_action_set); 8450 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8451 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8452 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8453 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8454 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8455 } 8456 8457 static inline void 8458 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8459 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8460 struct in6_addr dip6, struct in6_addr dip6_mask, 8461 struct in6_addr sip6, struct in6_addr sip6_mask, 8462 const char *flexible_action_set) 8463 { 8464 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8465 irif_mask, irif, flexible_action_set); 8466 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8467 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8468 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8469 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8470 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8471 } 8472 8473 /* RXLTE - Router XLT Enable Register 8474 * ---------------------------------- 8475 * The RXLTE enables XLT (eXtended Lookup Table) LPM lookups if a capable 8476 * XM is present on the system. 8477 */ 8478 8479 #define MLXSW_REG_RXLTE_ID 0x8050 8480 #define MLXSW_REG_RXLTE_LEN 0x0C 8481 8482 MLXSW_REG_DEFINE(rxlte, MLXSW_REG_RXLTE_ID, MLXSW_REG_RXLTE_LEN); 8483 8484 /* reg_rxlte_virtual_router 8485 * Virtual router ID associated with the router interface. 8486 * Range is 0..cap_max_virtual_routers-1 8487 * Access: Index 8488 */ 8489 MLXSW_ITEM32(reg, rxlte, virtual_router, 0x00, 0, 16); 8490 8491 enum mlxsw_reg_rxlte_protocol { 8492 MLXSW_REG_RXLTE_PROTOCOL_IPV4, 8493 MLXSW_REG_RXLTE_PROTOCOL_IPV6, 8494 }; 8495 8496 /* reg_rxlte_protocol 8497 * Access: Index 8498 */ 8499 MLXSW_ITEM32(reg, rxlte, protocol, 0x04, 0, 4); 8500 8501 /* reg_rxlte_lpm_xlt_en 8502 * Access: RW 8503 */ 8504 MLXSW_ITEM32(reg, rxlte, lpm_xlt_en, 0x08, 0, 1); 8505 8506 static inline void mlxsw_reg_rxlte_pack(char *payload, u16 virtual_router, 8507 enum mlxsw_reg_rxlte_protocol protocol, 8508 bool lpm_xlt_en) 8509 { 8510 MLXSW_REG_ZERO(rxlte, payload); 8511 mlxsw_reg_rxlte_virtual_router_set(payload, virtual_router); 8512 mlxsw_reg_rxlte_protocol_set(payload, protocol); 8513 mlxsw_reg_rxlte_lpm_xlt_en_set(payload, lpm_xlt_en); 8514 } 8515 8516 /* RXLTM - Router XLT M select Register 8517 * ------------------------------------ 8518 * The RXLTM configures and selects the M for the XM lookups. 8519 */ 8520 8521 #define MLXSW_REG_RXLTM_ID 0x8051 8522 #define MLXSW_REG_RXLTM_LEN 0x14 8523 8524 MLXSW_REG_DEFINE(rxltm, MLXSW_REG_RXLTM_ID, MLXSW_REG_RXLTM_LEN); 8525 8526 /* reg_rxltm_m0_val_v6 8527 * Global M0 value For IPv6. 8528 * Range 0..128 8529 * Access: RW 8530 */ 8531 MLXSW_ITEM32(reg, rxltm, m0_val_v6, 0x10, 16, 8); 8532 8533 /* reg_rxltm_m0_val_v4 8534 * Global M0 value For IPv4. 8535 * Range 0..32 8536 * Access: RW 8537 */ 8538 MLXSW_ITEM32(reg, rxltm, m0_val_v4, 0x10, 0, 6); 8539 8540 static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v6) 8541 { 8542 MLXSW_REG_ZERO(rxltm, payload); 8543 mlxsw_reg_rxltm_m0_val_v6_set(payload, m0_val_v6); 8544 mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4); 8545 } 8546 8547 /* RLCMLD - Router LPM Cache ML Delete Register 8548 * -------------------------------------------- 8549 * The RLCMLD register is used to bulk delete the XLT-LPM cache ML entries. 8550 * This can be used by SW when L is increased or decreased, thus need to 8551 * remove entries with old ML values. 8552 */ 8553 8554 #define MLXSW_REG_RLCMLD_ID 0x8055 8555 #define MLXSW_REG_RLCMLD_LEN 0x30 8556 8557 MLXSW_REG_DEFINE(rlcmld, MLXSW_REG_RLCMLD_ID, MLXSW_REG_RLCMLD_LEN); 8558 8559 enum mlxsw_reg_rlcmld_select { 8560 MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES, 8561 MLXSW_REG_RLCMLD_SELECT_M_ENTRIES, 8562 MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES, 8563 }; 8564 8565 /* reg_rlcmld_select 8566 * Which entries to delete. 8567 * Access: Index 8568 */ 8569 MLXSW_ITEM32(reg, rlcmld, select, 0x00, 16, 2); 8570 8571 enum mlxsw_reg_rlcmld_filter_fields { 8572 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL = 0x04, 8573 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER = 0x08, 8574 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP = 0x10, 8575 }; 8576 8577 /* reg_rlcmld_filter_fields 8578 * If a bit is '0' then the relevant field is ignored. 8579 * Access: Index 8580 */ 8581 MLXSW_ITEM32(reg, rlcmld, filter_fields, 0x00, 0, 8); 8582 8583 enum mlxsw_reg_rlcmld_protocol { 8584 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, 8585 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, 8586 }; 8587 8588 /* reg_rlcmld_protocol 8589 * Access: Index 8590 */ 8591 MLXSW_ITEM32(reg, rlcmld, protocol, 0x08, 0, 4); 8592 8593 /* reg_rlcmld_virtual_router 8594 * Virtual router ID. 8595 * Range is 0..cap_max_virtual_routers-1 8596 * Access: Index 8597 */ 8598 MLXSW_ITEM32(reg, rlcmld, virtual_router, 0x0C, 0, 16); 8599 8600 /* reg_rlcmld_dip 8601 * The prefix of the route or of the marker that the object of the LPM 8602 * is compared with. The most significant bits of the dip are the prefix. 8603 * Access: Index 8604 */ 8605 MLXSW_ITEM32(reg, rlcmld, dip4, 0x1C, 0, 32); 8606 MLXSW_ITEM_BUF(reg, rlcmld, dip6, 0x10, 16); 8607 8608 /* reg_rlcmld_dip_mask 8609 * per bit: 8610 * 0: no match 8611 * 1: match 8612 * Access: Index 8613 */ 8614 MLXSW_ITEM32(reg, rlcmld, dip_mask4, 0x2C, 0, 32); 8615 MLXSW_ITEM_BUF(reg, rlcmld, dip_mask6, 0x20, 16); 8616 8617 static inline void __mlxsw_reg_rlcmld_pack(char *payload, 8618 enum mlxsw_reg_rlcmld_select select, 8619 enum mlxsw_reg_rlcmld_protocol protocol, 8620 u16 virtual_router) 8621 { 8622 u8 filter_fields = MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL | 8623 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER | 8624 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP; 8625 8626 MLXSW_REG_ZERO(rlcmld, payload); 8627 mlxsw_reg_rlcmld_select_set(payload, select); 8628 mlxsw_reg_rlcmld_filter_fields_set(payload, filter_fields); 8629 mlxsw_reg_rlcmld_protocol_set(payload, protocol); 8630 mlxsw_reg_rlcmld_virtual_router_set(payload, virtual_router); 8631 } 8632 8633 static inline void mlxsw_reg_rlcmld_pack4(char *payload, 8634 enum mlxsw_reg_rlcmld_select select, 8635 u16 virtual_router, 8636 u32 dip, u32 dip_mask) 8637 { 8638 __mlxsw_reg_rlcmld_pack(payload, select, 8639 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, 8640 virtual_router); 8641 mlxsw_reg_rlcmld_dip4_set(payload, dip); 8642 mlxsw_reg_rlcmld_dip_mask4_set(payload, dip_mask); 8643 } 8644 8645 static inline void mlxsw_reg_rlcmld_pack6(char *payload, 8646 enum mlxsw_reg_rlcmld_select select, 8647 u16 virtual_router, 8648 const void *dip, const void *dip_mask) 8649 { 8650 __mlxsw_reg_rlcmld_pack(payload, select, 8651 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, 8652 virtual_router); 8653 mlxsw_reg_rlcmld_dip6_memcpy_to(payload, dip); 8654 mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask); 8655 } 8656 8657 /* RLPMCE - Router LPM Cache Enable Register 8658 * ----------------------------------------- 8659 * Allows disabling the LPM cache. Can be changed on the fly. 8660 */ 8661 8662 #define MLXSW_REG_RLPMCE_ID 0x8056 8663 #define MLXSW_REG_RLPMCE_LEN 0x4 8664 8665 MLXSW_REG_DEFINE(rlpmce, MLXSW_REG_RLPMCE_ID, MLXSW_REG_RLPMCE_LEN); 8666 8667 /* reg_rlpmce_flush 8668 * Flush: 8669 * 0: do not flush the cache (default) 8670 * 1: flush (clear) the cache 8671 * Access: WO 8672 */ 8673 MLXSW_ITEM32(reg, rlpmce, flush, 0x00, 4, 1); 8674 8675 /* reg_rlpmce_disable 8676 * LPM cache: 8677 * 0: enabled (default) 8678 * 1: disabled 8679 * Access: RW 8680 */ 8681 MLXSW_ITEM32(reg, rlpmce, disable, 0x00, 0, 1); 8682 8683 static inline void mlxsw_reg_rlpmce_pack(char *payload, bool flush, 8684 bool disable) 8685 { 8686 MLXSW_REG_ZERO(rlpmce, payload); 8687 mlxsw_reg_rlpmce_flush_set(payload, flush); 8688 mlxsw_reg_rlpmce_disable_set(payload, disable); 8689 } 8690 8691 /* Note that XLTQ, XMDR, XRMT and XRALXX register positions violate the rule 8692 * of ordering register definitions by the ID. However, XRALXX pack helpers are 8693 * using RALXX pack helpers, RALXX registers have higher IDs. 8694 * Also XMDR is using RALUE enums. XLRQ and XRMT are just put alongside with the 8695 * related registers. 8696 */ 8697 8698 /* XLTQ - XM Lookup Table Query Register 8699 * ------------------------------------- 8700 */ 8701 #define MLXSW_REG_XLTQ_ID 0x7802 8702 #define MLXSW_REG_XLTQ_LEN 0x2C 8703 8704 MLXSW_REG_DEFINE(xltq, MLXSW_REG_XLTQ_ID, MLXSW_REG_XLTQ_LEN); 8705 8706 enum mlxsw_reg_xltq_xm_device_id { 8707 MLXSW_REG_XLTQ_XM_DEVICE_ID_UNKNOWN, 8708 MLXSW_REG_XLTQ_XM_DEVICE_ID_XLT = 0xCF71, 8709 }; 8710 8711 /* reg_xltq_xm_device_id 8712 * XM device ID. 8713 * Access: RO 8714 */ 8715 MLXSW_ITEM32(reg, xltq, xm_device_id, 0x04, 0, 16); 8716 8717 /* reg_xltq_xlt_cap_ipv4_lpm 8718 * Access: RO 8719 */ 8720 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv4_lpm, 0x10, 0, 1); 8721 8722 /* reg_xltq_xlt_cap_ipv6_lpm 8723 * Access: RO 8724 */ 8725 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv6_lpm, 0x10, 1, 1); 8726 8727 /* reg_xltq_cap_xlt_entries 8728 * Number of XLT entries 8729 * Note: SW must not fill more than 80% in order to avoid overflow 8730 * Access: RO 8731 */ 8732 MLXSW_ITEM32(reg, xltq, cap_xlt_entries, 0x20, 0, 32); 8733 8734 /* reg_xltq_cap_xlt_mtable 8735 * XLT M-Table max size 8736 * Access: RO 8737 */ 8738 MLXSW_ITEM32(reg, xltq, cap_xlt_mtable, 0x24, 0, 32); 8739 8740 static inline void mlxsw_reg_xltq_pack(char *payload) 8741 { 8742 MLXSW_REG_ZERO(xltq, payload); 8743 } 8744 8745 static inline void mlxsw_reg_xltq_unpack(char *payload, u16 *xm_device_id, bool *xlt_cap_ipv4_lpm, 8746 bool *xlt_cap_ipv6_lpm, u32 *cap_xlt_entries, 8747 u32 *cap_xlt_mtable) 8748 { 8749 *xm_device_id = mlxsw_reg_xltq_xm_device_id_get(payload); 8750 *xlt_cap_ipv4_lpm = mlxsw_reg_xltq_xlt_cap_ipv4_lpm_get(payload); 8751 *xlt_cap_ipv6_lpm = mlxsw_reg_xltq_xlt_cap_ipv6_lpm_get(payload); 8752 *cap_xlt_entries = mlxsw_reg_xltq_cap_xlt_entries_get(payload); 8753 *cap_xlt_mtable = mlxsw_reg_xltq_cap_xlt_mtable_get(payload); 8754 } 8755 8756 /* XMDR - XM Direct Register 8757 * ------------------------- 8758 * The XMDR allows direct access to the XM device via the switch. 8759 * Working in synchronous mode. FW waits for response from the XLT 8760 * for each command. FW acks the XMDR accordingly. 8761 */ 8762 #define MLXSW_REG_XMDR_ID 0x7803 8763 #define MLXSW_REG_XMDR_BASE_LEN 0x20 8764 #define MLXSW_REG_XMDR_TRANS_LEN 0x80 8765 #define MLXSW_REG_XMDR_LEN (MLXSW_REG_XMDR_BASE_LEN + \ 8766 MLXSW_REG_XMDR_TRANS_LEN) 8767 8768 MLXSW_REG_DEFINE(xmdr, MLXSW_REG_XMDR_ID, MLXSW_REG_XMDR_LEN); 8769 8770 /* reg_xmdr_bulk_entry 8771 * Bulk_entry 8772 * 0: Last entry - immediate flush of XRT-cache 8773 * 1: Bulk entry - do not flush the XRT-cache 8774 * Access: OP 8775 */ 8776 MLXSW_ITEM32(reg, xmdr, bulk_entry, 0x04, 8, 1); 8777 8778 /* reg_xmdr_num_rec 8779 * Number of records for Direct access to XM 8780 * Supported: 0..4 commands (except NOP which is a filler) 8781 * 0 commands is reserved when bulk_entry = 1. 8782 * 0 commands is allowed when bulk_entry = 0 for immediate XRT-cache flush. 8783 * Access: OP 8784 */ 8785 MLXSW_ITEM32(reg, xmdr, num_rec, 0x04, 0, 4); 8786 8787 /* reg_xmdr_reply_vect 8788 * Reply Vector 8789 * Bit i for command index i+1 8790 * values per bit: 8791 * 0: failed 8792 * 1: succeeded 8793 * e.g. if commands 1, 2, 4 succeeded and command 3 failed then binary 8794 * value will be 0b1011 8795 * Access: RO 8796 */ 8797 MLXSW_ITEM_BIT_ARRAY(reg, xmdr, reply_vect, 0x08, 4, 1); 8798 8799 static inline void mlxsw_reg_xmdr_pack(char *payload, bool bulk_entry) 8800 { 8801 MLXSW_REG_ZERO(xmdr, payload); 8802 mlxsw_reg_xmdr_bulk_entry_set(payload, bulk_entry); 8803 } 8804 8805 enum mlxsw_reg_xmdr_c_cmd_id { 8806 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4 = 0x30, 8807 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6 = 0x31, 8808 }; 8809 8810 #define MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN 32 8811 #define MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN 48 8812 8813 /* reg_xmdr_c_cmd_id 8814 */ 8815 MLXSW_ITEM32(reg, xmdr_c, cmd_id, 0x00, 24, 8); 8816 8817 /* reg_xmdr_c_seq_number 8818 */ 8819 MLXSW_ITEM32(reg, xmdr_c, seq_number, 0x00, 12, 12); 8820 8821 enum mlxsw_reg_xmdr_c_ltr_op { 8822 /* Activity is set */ 8823 MLXSW_REG_XMDR_C_LTR_OP_WRITE = 0, 8824 /* There is no update mask. All fields are updated. */ 8825 MLXSW_REG_XMDR_C_LTR_OP_UPDATE = 1, 8826 MLXSW_REG_XMDR_C_LTR_OP_DELETE = 2, 8827 }; 8828 8829 /* reg_xmdr_c_ltr_op 8830 * Operation. 8831 */ 8832 MLXSW_ITEM32(reg, xmdr_c, ltr_op, 0x04, 24, 8); 8833 8834 /* reg_xmdr_c_ltr_trap_action 8835 * Trap action. 8836 * Values are defined in enum mlxsw_reg_ralue_trap_action. 8837 */ 8838 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_action, 0x04, 20, 4); 8839 8840 enum mlxsw_reg_xmdr_c_ltr_trap_id_num { 8841 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS0, 8842 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS1, 8843 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS2, 8844 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS3, 8845 }; 8846 8847 /* reg_xmdr_c_ltr_trap_id_num 8848 * Trap-ID number. 8849 */ 8850 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_id_num, 0x04, 16, 4); 8851 8852 /* reg_xmdr_c_ltr_virtual_router 8853 * Virtual Router ID. 8854 * Range is 0..cap_max_virtual_routers-1 8855 */ 8856 MLXSW_ITEM32(reg, xmdr_c, ltr_virtual_router, 0x04, 0, 16); 8857 8858 /* reg_xmdr_c_ltr_prefix_len 8859 * Number of bits in the prefix of the LPM route. 8860 */ 8861 MLXSW_ITEM32(reg, xmdr_c, ltr_prefix_len, 0x08, 24, 8); 8862 8863 /* reg_xmdr_c_ltr_bmp_len 8864 * The best match prefix length in the case that there is no match for 8865 * longer prefixes. 8866 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 8867 */ 8868 MLXSW_ITEM32(reg, xmdr_c, ltr_bmp_len, 0x08, 16, 8); 8869 8870 /* reg_xmdr_c_ltr_entry_type 8871 * Entry type. 8872 * Values are defined in enum mlxsw_reg_ralue_entry_type. 8873 */ 8874 MLXSW_ITEM32(reg, xmdr_c, ltr_entry_type, 0x08, 4, 4); 8875 8876 enum mlxsw_reg_xmdr_c_ltr_action_type { 8877 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL, 8878 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE, 8879 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME, 8880 }; 8881 8882 /* reg_xmdr_c_ltr_action_type 8883 * Action Type. 8884 */ 8885 MLXSW_ITEM32(reg, xmdr_c, ltr_action_type, 0x08, 0, 4); 8886 8887 /* reg_xmdr_c_ltr_erif 8888 * Egress Router Interface. 8889 * Only relevant in case of LOCAL action. 8890 */ 8891 MLXSW_ITEM32(reg, xmdr_c, ltr_erif, 0x10, 0, 16); 8892 8893 /* reg_xmdr_c_ltr_adjacency_index 8894 * Points to the first entry of the group-based ECMP. 8895 * Only relevant in case of REMOTE action. 8896 */ 8897 MLXSW_ITEM32(reg, xmdr_c, ltr_adjacency_index, 0x10, 0, 24); 8898 8899 #define MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC 0xFFFFFF 8900 8901 /* reg_xmdr_c_ltr_pointer_to_tunnel 8902 * Only relevant in case of IP2ME action. 8903 */ 8904 MLXSW_ITEM32(reg, xmdr_c, ltr_pointer_to_tunnel, 0x10, 0, 24); 8905 8906 /* reg_xmdr_c_ltr_ecmp_size 8907 * Amount of sequential entries starting 8908 * from the adjacency_index (the number of ECMPs). 8909 * The valid range is 1-64, 512, 1024, 2048 and 4096. 8910 * Only relevant in case of REMOTE action. 8911 */ 8912 MLXSW_ITEM32(reg, xmdr_c, ltr_ecmp_size, 0x14, 0, 32); 8913 8914 /* reg_xmdr_c_ltr_dip* 8915 * The prefix of the route or of the marker that the object of the LPM 8916 * is compared with. The most significant bits of the dip are the prefix. 8917 * The least significant bits must be '0' if the prefix_len is smaller 8918 * than 128 for IPv6 or smaller than 32 for IPv4. 8919 */ 8920 MLXSW_ITEM32(reg, xmdr_c, ltr_dip4, 0x1C, 0, 32); 8921 MLXSW_ITEM_BUF(reg, xmdr_c, ltr_dip6, 0x1C, 16); 8922 8923 static inline void 8924 mlxsw_reg_xmdr_c_ltr_pack(char *xmdr_payload, unsigned int trans_offset, 8925 enum mlxsw_reg_xmdr_c_cmd_id cmd_id, u16 seq_number, 8926 enum mlxsw_reg_xmdr_c_ltr_op op, u16 virtual_router, 8927 u8 prefix_len) 8928 { 8929 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 8930 u8 num_rec = mlxsw_reg_xmdr_num_rec_get(xmdr_payload); 8931 8932 mlxsw_reg_xmdr_num_rec_set(xmdr_payload, num_rec + 1); 8933 8934 mlxsw_reg_xmdr_c_cmd_id_set(payload, cmd_id); 8935 mlxsw_reg_xmdr_c_seq_number_set(payload, seq_number); 8936 mlxsw_reg_xmdr_c_ltr_op_set(payload, op); 8937 mlxsw_reg_xmdr_c_ltr_virtual_router_set(payload, virtual_router); 8938 mlxsw_reg_xmdr_c_ltr_prefix_len_set(payload, prefix_len); 8939 mlxsw_reg_xmdr_c_ltr_entry_type_set(payload, 8940 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 8941 mlxsw_reg_xmdr_c_ltr_bmp_len_set(payload, prefix_len); 8942 } 8943 8944 static inline unsigned int 8945 mlxsw_reg_xmdr_c_ltr_pack4(char *xmdr_payload, unsigned int trans_offset, 8946 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op, 8947 u16 virtual_router, u8 prefix_len, u32 *dip) 8948 { 8949 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 8950 8951 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset, 8952 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4, 8953 seq_number, op, virtual_router, prefix_len); 8954 if (dip) 8955 mlxsw_reg_xmdr_c_ltr_dip4_set(payload, *dip); 8956 return MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN; 8957 } 8958 8959 static inline unsigned int 8960 mlxsw_reg_xmdr_c_ltr_pack6(char *xmdr_payload, unsigned int trans_offset, 8961 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op, 8962 u16 virtual_router, u8 prefix_len, const void *dip) 8963 { 8964 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 8965 8966 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset, 8967 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6, 8968 seq_number, op, virtual_router, prefix_len); 8969 if (dip) 8970 mlxsw_reg_xmdr_c_ltr_dip6_memcpy_to(payload, dip); 8971 return MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN; 8972 } 8973 8974 static inline void 8975 mlxsw_reg_xmdr_c_ltr_act_remote_pack(char *xmdr_payload, unsigned int trans_offset, 8976 enum mlxsw_reg_ralue_trap_action trap_action, 8977 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, 8978 u32 adjacency_index, u16 ecmp_size) 8979 { 8980 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 8981 8982 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE); 8983 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action); 8984 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num); 8985 mlxsw_reg_xmdr_c_ltr_adjacency_index_set(payload, adjacency_index); 8986 mlxsw_reg_xmdr_c_ltr_ecmp_size_set(payload, ecmp_size); 8987 } 8988 8989 static inline void 8990 mlxsw_reg_xmdr_c_ltr_act_local_pack(char *xmdr_payload, unsigned int trans_offset, 8991 enum mlxsw_reg_ralue_trap_action trap_action, 8992 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, u16 erif) 8993 { 8994 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 8995 8996 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL); 8997 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action); 8998 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num); 8999 mlxsw_reg_xmdr_c_ltr_erif_set(payload, erif); 9000 } 9001 9002 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char *xmdr_payload, 9003 unsigned int trans_offset) 9004 { 9005 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9006 9007 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME); 9008 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, 9009 MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC); 9010 } 9011 9012 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload, 9013 unsigned int trans_offset, 9014 u32 pointer_to_tunnel) 9015 { 9016 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9017 9018 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME); 9019 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel); 9020 } 9021 9022 /* XRMT - XM Router M Table Register 9023 * --------------------------------- 9024 * The XRMT configures the M-Table for the XLT-LPM. 9025 */ 9026 #define MLXSW_REG_XRMT_ID 0x7810 9027 #define MLXSW_REG_XRMT_LEN 0x14 9028 9029 MLXSW_REG_DEFINE(xrmt, MLXSW_REG_XRMT_ID, MLXSW_REG_XRMT_LEN); 9030 9031 /* reg_xrmt_index 9032 * Index in M-Table. 9033 * Range 0..cap_xlt_mtable-1 9034 * Access: Index 9035 */ 9036 MLXSW_ITEM32(reg, xrmt, index, 0x04, 0, 20); 9037 9038 /* reg_xrmt_l0_val 9039 * Access: RW 9040 */ 9041 MLXSW_ITEM32(reg, xrmt, l0_val, 0x10, 24, 8); 9042 9043 static inline void mlxsw_reg_xrmt_pack(char *payload, u32 index, u8 l0_val) 9044 { 9045 MLXSW_REG_ZERO(xrmt, payload); 9046 mlxsw_reg_xrmt_index_set(payload, index); 9047 mlxsw_reg_xrmt_l0_val_set(payload, l0_val); 9048 } 9049 9050 /* XRALTA - XM Router Algorithmic LPM Tree Allocation Register 9051 * ----------------------------------------------------------- 9052 * The XRALTA is used to allocate the XLT LPM trees. 9053 * 9054 * This register embeds original RALTA register. 9055 */ 9056 #define MLXSW_REG_XRALTA_ID 0x7811 9057 #define MLXSW_REG_XRALTA_LEN 0x08 9058 #define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04 9059 9060 MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN); 9061 9062 static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc, 9063 enum mlxsw_reg_ralxx_protocol protocol, 9064 u8 tree_id) 9065 { 9066 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET; 9067 9068 MLXSW_REG_ZERO(xralta, payload); 9069 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id); 9070 } 9071 9072 /* XRALST - XM Router Algorithmic LPM Structure Tree Register 9073 * ---------------------------------------------------------- 9074 * The XRALST is used to set and query the structure of an XLT LPM tree. 9075 * 9076 * This register embeds original RALST register. 9077 */ 9078 #define MLXSW_REG_XRALST_ID 0x7812 9079 #define MLXSW_REG_XRALST_LEN 0x108 9080 #define MLXSW_REG_XRALST_RALST_OFFSET 0x04 9081 9082 MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN); 9083 9084 static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id) 9085 { 9086 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 9087 9088 MLXSW_REG_ZERO(xralst, payload); 9089 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id); 9090 } 9091 9092 static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number, 9093 u8 left_child_bin, 9094 u8 right_child_bin) 9095 { 9096 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 9097 9098 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin, 9099 right_child_bin); 9100 } 9101 9102 /* XRALTB - XM Router Algorithmic LPM Tree Binding Register 9103 * -------------------------------------------------------- 9104 * The XRALTB register is used to bind virtual router and protocol 9105 * to an allocated LPM tree. 9106 * 9107 * This register embeds original RALTB register. 9108 */ 9109 #define MLXSW_REG_XRALTB_ID 0x7813 9110 #define MLXSW_REG_XRALTB_LEN 0x08 9111 #define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04 9112 9113 MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN); 9114 9115 static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router, 9116 enum mlxsw_reg_ralxx_protocol protocol, 9117 u8 tree_id) 9118 { 9119 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET; 9120 9121 MLXSW_REG_ZERO(xraltb, payload); 9122 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id); 9123 } 9124 9125 /* MFCR - Management Fan Control Register 9126 * -------------------------------------- 9127 * This register controls the settings of the Fan Speed PWM mechanism. 9128 */ 9129 #define MLXSW_REG_MFCR_ID 0x9001 9130 #define MLXSW_REG_MFCR_LEN 0x08 9131 9132 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9133 9134 enum mlxsw_reg_mfcr_pwm_frequency { 9135 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9136 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9137 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9138 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9139 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9140 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9141 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9142 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9143 }; 9144 9145 /* reg_mfcr_pwm_frequency 9146 * Controls the frequency of the PWM signal. 9147 * Access: RW 9148 */ 9149 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9150 9151 #define MLXSW_MFCR_TACHOS_MAX 10 9152 9153 /* reg_mfcr_tacho_active 9154 * Indicates which of the tachometer is active (bit per tachometer). 9155 * Access: RO 9156 */ 9157 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9158 9159 #define MLXSW_MFCR_PWMS_MAX 5 9160 9161 /* reg_mfcr_pwm_active 9162 * Indicates which of the PWM control is active (bit per PWM). 9163 * Access: RO 9164 */ 9165 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9166 9167 static inline void 9168 mlxsw_reg_mfcr_pack(char *payload, 9169 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9170 { 9171 MLXSW_REG_ZERO(mfcr, payload); 9172 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9173 } 9174 9175 static inline void 9176 mlxsw_reg_mfcr_unpack(char *payload, 9177 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9178 u16 *p_tacho_active, u8 *p_pwm_active) 9179 { 9180 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9181 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9182 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9183 } 9184 9185 /* MFSC - Management Fan Speed Control Register 9186 * -------------------------------------------- 9187 * This register controls the settings of the Fan Speed PWM mechanism. 9188 */ 9189 #define MLXSW_REG_MFSC_ID 0x9002 9190 #define MLXSW_REG_MFSC_LEN 0x08 9191 9192 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9193 9194 /* reg_mfsc_pwm 9195 * Fan pwm to control / monitor. 9196 * Access: Index 9197 */ 9198 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9199 9200 /* reg_mfsc_pwm_duty_cycle 9201 * Controls the duty cycle of the PWM. Value range from 0..255 to 9202 * represent duty cycle of 0%...100%. 9203 * Access: RW 9204 */ 9205 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9206 9207 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9208 u8 pwm_duty_cycle) 9209 { 9210 MLXSW_REG_ZERO(mfsc, payload); 9211 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9212 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9213 } 9214 9215 /* MFSM - Management Fan Speed Measurement 9216 * --------------------------------------- 9217 * This register controls the settings of the Tacho measurements and 9218 * enables reading the Tachometer measurements. 9219 */ 9220 #define MLXSW_REG_MFSM_ID 0x9003 9221 #define MLXSW_REG_MFSM_LEN 0x08 9222 9223 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9224 9225 /* reg_mfsm_tacho 9226 * Fan tachometer index. 9227 * Access: Index 9228 */ 9229 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9230 9231 /* reg_mfsm_rpm 9232 * Fan speed (round per minute). 9233 * Access: RO 9234 */ 9235 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9236 9237 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9238 { 9239 MLXSW_REG_ZERO(mfsm, payload); 9240 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9241 } 9242 9243 /* MFSL - Management Fan Speed Limit Register 9244 * ------------------------------------------ 9245 * The Fan Speed Limit register is used to configure the fan speed 9246 * event / interrupt notification mechanism. Fan speed threshold are 9247 * defined for both under-speed and over-speed. 9248 */ 9249 #define MLXSW_REG_MFSL_ID 0x9004 9250 #define MLXSW_REG_MFSL_LEN 0x0C 9251 9252 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9253 9254 /* reg_mfsl_tacho 9255 * Fan tachometer index. 9256 * Access: Index 9257 */ 9258 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9259 9260 /* reg_mfsl_tach_min 9261 * Tachometer minimum value (minimum RPM). 9262 * Access: RW 9263 */ 9264 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9265 9266 /* reg_mfsl_tach_max 9267 * Tachometer maximum value (maximum RPM). 9268 * Access: RW 9269 */ 9270 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9271 9272 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9273 u16 tach_min, u16 tach_max) 9274 { 9275 MLXSW_REG_ZERO(mfsl, payload); 9276 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9277 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9278 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9279 } 9280 9281 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9282 u16 *p_tach_min, u16 *p_tach_max) 9283 { 9284 if (p_tach_min) 9285 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9286 9287 if (p_tach_max) 9288 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9289 } 9290 9291 /* FORE - Fan Out of Range Event Register 9292 * -------------------------------------- 9293 * This register reports the status of the controlled fans compared to the 9294 * range defined by the MFSL register. 9295 */ 9296 #define MLXSW_REG_FORE_ID 0x9007 9297 #define MLXSW_REG_FORE_LEN 0x0C 9298 9299 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9300 9301 /* fan_under_limit 9302 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9303 * to a single tachometer and indicates the specific tachometer reading is 9304 * below the threshold. 9305 * Access: RO 9306 */ 9307 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9308 9309 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9310 bool *fault) 9311 { 9312 u16 limit; 9313 9314 if (fault) { 9315 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9316 *fault = limit & BIT(tacho); 9317 } 9318 } 9319 9320 /* MTCAP - Management Temperature Capabilities 9321 * ------------------------------------------- 9322 * This register exposes the capabilities of the device and 9323 * system temperature sensing. 9324 */ 9325 #define MLXSW_REG_MTCAP_ID 0x9009 9326 #define MLXSW_REG_MTCAP_LEN 0x08 9327 9328 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9329 9330 /* reg_mtcap_sensor_count 9331 * Number of sensors supported by the device. 9332 * This includes the QSFP module sensors (if exists in the QSFP module). 9333 * Access: RO 9334 */ 9335 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9336 9337 /* MTMP - Management Temperature 9338 * ----------------------------- 9339 * This register controls the settings of the temperature measurements 9340 * and enables reading the temperature measurements. Note that temperature 9341 * is in 0.125 degrees Celsius. 9342 */ 9343 #define MLXSW_REG_MTMP_ID 0x900A 9344 #define MLXSW_REG_MTMP_LEN 0x20 9345 9346 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9347 9348 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9349 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9350 /* reg_mtmp_sensor_index 9351 * Sensors index to access. 9352 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9353 * (module 0 is mapped to sensor_index 64). 9354 * Access: Index 9355 */ 9356 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9357 9358 /* Convert to milli degrees Celsius */ 9359 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9360 ((v_) >= 0) ? ((v_) * 125) : \ 9361 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9362 * 125)); }) 9363 9364 /* reg_mtmp_temperature 9365 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9366 * degrees units. 9367 * Access: RO 9368 */ 9369 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9370 9371 /* reg_mtmp_mte 9372 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9373 * Access: RW 9374 */ 9375 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9376 9377 /* reg_mtmp_mtr 9378 * Max Temperature Reset - clears the value of the max temperature register. 9379 * Access: WO 9380 */ 9381 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9382 9383 /* reg_mtmp_max_temperature 9384 * The highest measured temperature from the sensor. 9385 * When the bit mte is cleared, the field max_temperature is reserved. 9386 * Access: RO 9387 */ 9388 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9389 9390 /* reg_mtmp_tee 9391 * Temperature Event Enable. 9392 * 0 - Do not generate event 9393 * 1 - Generate event 9394 * 2 - Generate single event 9395 * Access: RW 9396 */ 9397 9398 enum mlxsw_reg_mtmp_tee { 9399 MLXSW_REG_MTMP_TEE_NO_EVENT, 9400 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9401 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9402 }; 9403 9404 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9405 9406 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9407 9408 /* reg_mtmp_temperature_threshold_hi 9409 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9410 * Access: RW 9411 */ 9412 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9413 9414 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9415 /* reg_mtmp_temperature_threshold_lo 9416 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9417 * Access: RW 9418 */ 9419 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9420 9421 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9422 9423 /* reg_mtmp_sensor_name 9424 * Sensor Name 9425 * Access: RO 9426 */ 9427 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9428 9429 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 9430 bool max_temp_enable, 9431 bool max_temp_reset) 9432 { 9433 MLXSW_REG_ZERO(mtmp, payload); 9434 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9435 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9436 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9437 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9438 MLXSW_REG_MTMP_THRESH_HI); 9439 } 9440 9441 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9442 int *p_max_temp, char *sensor_name) 9443 { 9444 s16 temp; 9445 9446 if (p_temp) { 9447 temp = mlxsw_reg_mtmp_temperature_get(payload); 9448 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9449 } 9450 if (p_max_temp) { 9451 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9452 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9453 } 9454 if (sensor_name) 9455 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9456 } 9457 9458 /* MTWE - Management Temperature Warning Event 9459 * ------------------------------------------- 9460 * This register is used for over temperature warning. 9461 */ 9462 #define MLXSW_REG_MTWE_ID 0x900B 9463 #define MLXSW_REG_MTWE_LEN 0x10 9464 9465 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9466 9467 /* reg_mtwe_sensor_warning 9468 * Bit vector indicating which of the sensor reading is above threshold. 9469 * Address 00h bit31 is sensor_warning[127]. 9470 * Address 0Ch bit0 is sensor_warning[0]. 9471 * Access: RO 9472 */ 9473 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9474 9475 /* MTBR - Management Temperature Bulk Register 9476 * ------------------------------------------- 9477 * This register is used for bulk temperature reading. 9478 */ 9479 #define MLXSW_REG_MTBR_ID 0x900F 9480 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9481 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9482 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9483 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9484 MLXSW_REG_MTBR_REC_LEN * \ 9485 MLXSW_REG_MTBR_REC_MAX_COUNT) 9486 9487 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9488 9489 /* reg_mtbr_base_sensor_index 9490 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9491 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9492 * Access: Index 9493 */ 9494 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9495 9496 /* reg_mtbr_num_rec 9497 * Request: Number of records to read 9498 * Response: Number of records read 9499 * See above description for more details. 9500 * Range 1..255 9501 * Access: RW 9502 */ 9503 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9504 9505 /* reg_mtbr_rec_max_temp 9506 * The highest measured temperature from the sensor. 9507 * When the bit mte is cleared, the field max_temperature is reserved. 9508 * Access: RO 9509 */ 9510 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9511 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9512 9513 /* reg_mtbr_rec_temp 9514 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9515 * degrees units. 9516 * Access: RO 9517 */ 9518 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9519 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9520 9521 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 9522 u8 num_rec) 9523 { 9524 MLXSW_REG_ZERO(mtbr, payload); 9525 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9526 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9527 } 9528 9529 /* Error codes from temperatute reading */ 9530 enum mlxsw_reg_mtbr_temp_status { 9531 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9532 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9533 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9534 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9535 }; 9536 9537 /* Base index for reading modules temperature */ 9538 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9539 9540 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9541 u16 *p_temp, u16 *p_max_temp) 9542 { 9543 if (p_temp) 9544 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9545 if (p_max_temp) 9546 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9547 } 9548 9549 /* MCIA - Management Cable Info Access 9550 * ----------------------------------- 9551 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9552 */ 9553 9554 #define MLXSW_REG_MCIA_ID 0x9014 9555 #define MLXSW_REG_MCIA_LEN 0x40 9556 9557 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9558 9559 /* reg_mcia_l 9560 * Lock bit. Setting this bit will lock the access to the specific 9561 * cable. Used for updating a full page in a cable EPROM. Any access 9562 * other then subsequence writes will fail while the port is locked. 9563 * Access: RW 9564 */ 9565 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9566 9567 /* reg_mcia_module 9568 * Module number. 9569 * Access: Index 9570 */ 9571 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9572 9573 /* reg_mcia_status 9574 * Module status. 9575 * Access: RO 9576 */ 9577 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9578 9579 /* reg_mcia_i2c_device_address 9580 * I2C device address. 9581 * Access: RW 9582 */ 9583 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9584 9585 /* reg_mcia_page_number 9586 * Page number. 9587 * Access: RW 9588 */ 9589 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9590 9591 /* reg_mcia_device_address 9592 * Device address. 9593 * Access: RW 9594 */ 9595 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9596 9597 /* reg_mcia_size 9598 * Number of bytes to read/write (up to 48 bytes). 9599 * Access: RW 9600 */ 9601 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9602 9603 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9604 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9605 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9606 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9607 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9608 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9609 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9610 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9611 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9612 #define MLXSW_REG_MCIA_PAGE0_LO 0 9613 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9614 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9615 9616 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9617 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9618 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9619 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9620 }; 9621 9622 enum mlxsw_reg_mcia_eeprom_module_info_id { 9623 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9624 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9625 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9626 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9627 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9628 }; 9629 9630 enum mlxsw_reg_mcia_eeprom_module_info { 9631 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9632 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9633 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9634 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9635 }; 9636 9637 /* reg_mcia_eeprom 9638 * Bytes to read/write. 9639 * Access: RW 9640 */ 9641 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9642 9643 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9644 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9645 * on offset 384 through 511, page 3 - on offset 512 through 639. 9646 */ 9647 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9648 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9649 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9650 9651 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 9652 u8 page_number, u16 device_addr, 9653 u8 size, u8 i2c_device_addr) 9654 { 9655 MLXSW_REG_ZERO(mcia, payload); 9656 mlxsw_reg_mcia_module_set(payload, module); 9657 mlxsw_reg_mcia_l_set(payload, lock); 9658 mlxsw_reg_mcia_page_number_set(payload, page_number); 9659 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9660 mlxsw_reg_mcia_size_set(payload, size); 9661 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9662 } 9663 9664 /* MPAT - Monitoring Port Analyzer Table 9665 * ------------------------------------- 9666 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9667 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9668 */ 9669 #define MLXSW_REG_MPAT_ID 0x901A 9670 #define MLXSW_REG_MPAT_LEN 0x78 9671 9672 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9673 9674 /* reg_mpat_pa_id 9675 * Port Analyzer ID. 9676 * Access: Index 9677 */ 9678 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9679 9680 /* reg_mpat_session_id 9681 * Mirror Session ID. 9682 * Used for MIRROR_SESSION<i> trap. 9683 * Access: RW 9684 */ 9685 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9686 9687 /* reg_mpat_system_port 9688 * A unique port identifier for the final destination of the packet. 9689 * Access: RW 9690 */ 9691 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9692 9693 /* reg_mpat_e 9694 * Enable. Indicating the Port Analyzer is enabled. 9695 * Access: RW 9696 */ 9697 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9698 9699 /* reg_mpat_qos 9700 * Quality Of Service Mode. 9701 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9702 * PCP, DEI, DSCP or VL) are configured. 9703 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9704 * same as in the original packet that has triggered the mirroring. For 9705 * SPAN also the pcp,dei are maintained. 9706 * Access: RW 9707 */ 9708 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9709 9710 /* reg_mpat_be 9711 * Best effort mode. Indicates mirroring traffic should not cause packet 9712 * drop or back pressure, but will discard the mirrored packets. Mirrored 9713 * packets will be forwarded on a best effort manner. 9714 * 0: Do not discard mirrored packets 9715 * 1: Discard mirrored packets if causing congestion 9716 * Access: RW 9717 */ 9718 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9719 9720 enum mlxsw_reg_mpat_span_type { 9721 /* Local SPAN Ethernet. 9722 * The original packet is not encapsulated. 9723 */ 9724 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9725 9726 /* Remote SPAN Ethernet VLAN. 9727 * The packet is forwarded to the monitoring port on the monitoring 9728 * VLAN. 9729 */ 9730 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9731 9732 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9733 * The packet is encapsulated with GRE header. 9734 */ 9735 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9736 }; 9737 9738 /* reg_mpat_span_type 9739 * SPAN type. 9740 * Access: RW 9741 */ 9742 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9743 9744 /* reg_mpat_pide 9745 * Policer enable. 9746 * Access: RW 9747 */ 9748 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9749 9750 /* reg_mpat_pid 9751 * Policer ID. 9752 * Access: RW 9753 */ 9754 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9755 9756 /* Remote SPAN - Ethernet VLAN 9757 * - - - - - - - - - - - - - - 9758 */ 9759 9760 /* reg_mpat_eth_rspan_vid 9761 * Encapsulation header VLAN ID. 9762 * Access: RW 9763 */ 9764 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9765 9766 /* Encapsulated Remote SPAN - Ethernet L2 9767 * - - - - - - - - - - - - - - - - - - - 9768 */ 9769 9770 enum mlxsw_reg_mpat_eth_rspan_version { 9771 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9772 }; 9773 9774 /* reg_mpat_eth_rspan_version 9775 * RSPAN mirror header version. 9776 * Access: RW 9777 */ 9778 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9779 9780 /* reg_mpat_eth_rspan_mac 9781 * Destination MAC address. 9782 * Access: RW 9783 */ 9784 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9785 9786 /* reg_mpat_eth_rspan_tp 9787 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9788 * Access: RW 9789 */ 9790 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9791 9792 /* Encapsulated Remote SPAN - Ethernet L3 9793 * - - - - - - - - - - - - - - - - - - - 9794 */ 9795 9796 enum mlxsw_reg_mpat_eth_rspan_protocol { 9797 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9798 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9799 }; 9800 9801 /* reg_mpat_eth_rspan_protocol 9802 * SPAN encapsulation protocol. 9803 * Access: RW 9804 */ 9805 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9806 9807 /* reg_mpat_eth_rspan_ttl 9808 * Encapsulation header Time-to-Live/HopLimit. 9809 * Access: RW 9810 */ 9811 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9812 9813 /* reg_mpat_eth_rspan_smac 9814 * Source MAC address 9815 * Access: RW 9816 */ 9817 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9818 9819 /* reg_mpat_eth_rspan_dip* 9820 * Destination IP address. The IP version is configured by protocol. 9821 * Access: RW 9822 */ 9823 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9824 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9825 9826 /* reg_mpat_eth_rspan_sip* 9827 * Source IP address. The IP version is configured by protocol. 9828 * Access: RW 9829 */ 9830 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9831 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9832 9833 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9834 u16 system_port, bool e, 9835 enum mlxsw_reg_mpat_span_type span_type) 9836 { 9837 MLXSW_REG_ZERO(mpat, payload); 9838 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9839 mlxsw_reg_mpat_system_port_set(payload, system_port); 9840 mlxsw_reg_mpat_e_set(payload, e); 9841 mlxsw_reg_mpat_qos_set(payload, 1); 9842 mlxsw_reg_mpat_be_set(payload, 1); 9843 mlxsw_reg_mpat_span_type_set(payload, span_type); 9844 } 9845 9846 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9847 { 9848 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9849 } 9850 9851 static inline void 9852 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9853 enum mlxsw_reg_mpat_eth_rspan_version version, 9854 const char *mac, 9855 bool tp) 9856 { 9857 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9858 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9859 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9860 } 9861 9862 static inline void 9863 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9864 const char *smac, 9865 u32 sip, u32 dip) 9866 { 9867 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9868 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9869 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9870 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9871 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9872 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9873 } 9874 9875 static inline void 9876 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9877 const char *smac, 9878 struct in6_addr sip, struct in6_addr dip) 9879 { 9880 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9881 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9882 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9883 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9884 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9885 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9886 } 9887 9888 /* MPAR - Monitoring Port Analyzer Register 9889 * ---------------------------------------- 9890 * MPAR register is used to query and configure the port analyzer port mirroring 9891 * properties. 9892 */ 9893 #define MLXSW_REG_MPAR_ID 0x901B 9894 #define MLXSW_REG_MPAR_LEN 0x0C 9895 9896 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9897 9898 /* reg_mpar_local_port 9899 * The local port to mirror the packets from. 9900 * Access: Index 9901 */ 9902 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 9903 9904 enum mlxsw_reg_mpar_i_e { 9905 MLXSW_REG_MPAR_TYPE_EGRESS, 9906 MLXSW_REG_MPAR_TYPE_INGRESS, 9907 }; 9908 9909 /* reg_mpar_i_e 9910 * Ingress/Egress 9911 * Access: Index 9912 */ 9913 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9914 9915 /* reg_mpar_enable 9916 * Enable mirroring 9917 * By default, port mirroring is disabled for all ports. 9918 * Access: RW 9919 */ 9920 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9921 9922 /* reg_mpar_pa_id 9923 * Port Analyzer ID. 9924 * Access: RW 9925 */ 9926 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9927 9928 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 9929 enum mlxsw_reg_mpar_i_e i_e, 9930 bool enable, u8 pa_id) 9931 { 9932 MLXSW_REG_ZERO(mpar, payload); 9933 mlxsw_reg_mpar_local_port_set(payload, local_port); 9934 mlxsw_reg_mpar_enable_set(payload, enable); 9935 mlxsw_reg_mpar_i_e_set(payload, i_e); 9936 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9937 } 9938 9939 /* MGIR - Management General Information Register 9940 * ---------------------------------------------- 9941 * MGIR register allows software to query the hardware and firmware general 9942 * information. 9943 */ 9944 #define MLXSW_REG_MGIR_ID 0x9020 9945 #define MLXSW_REG_MGIR_LEN 0x9C 9946 9947 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 9948 9949 /* reg_mgir_hw_info_device_hw_revision 9950 * Access: RO 9951 */ 9952 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 9953 9954 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 9955 9956 /* reg_mgir_fw_info_psid 9957 * PSID (ASCII string). 9958 * Access: RO 9959 */ 9960 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 9961 9962 /* reg_mgir_fw_info_extended_major 9963 * Access: RO 9964 */ 9965 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 9966 9967 /* reg_mgir_fw_info_extended_minor 9968 * Access: RO 9969 */ 9970 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 9971 9972 /* reg_mgir_fw_info_extended_sub_minor 9973 * Access: RO 9974 */ 9975 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 9976 9977 static inline void mlxsw_reg_mgir_pack(char *payload) 9978 { 9979 MLXSW_REG_ZERO(mgir, payload); 9980 } 9981 9982 static inline void 9983 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 9984 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 9985 { 9986 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 9987 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 9988 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 9989 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 9990 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 9991 } 9992 9993 /* MRSR - Management Reset and Shutdown Register 9994 * --------------------------------------------- 9995 * MRSR register is used to reset or shutdown the switch or 9996 * the entire system (when applicable). 9997 */ 9998 #define MLXSW_REG_MRSR_ID 0x9023 9999 #define MLXSW_REG_MRSR_LEN 0x08 10000 10001 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10002 10003 /* reg_mrsr_command 10004 * Reset/shutdown command 10005 * 0 - do nothing 10006 * 1 - software reset 10007 * Access: WO 10008 */ 10009 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10010 10011 static inline void mlxsw_reg_mrsr_pack(char *payload) 10012 { 10013 MLXSW_REG_ZERO(mrsr, payload); 10014 mlxsw_reg_mrsr_command_set(payload, 1); 10015 } 10016 10017 /* MLCR - Management LED Control Register 10018 * -------------------------------------- 10019 * Controls the system LEDs. 10020 */ 10021 #define MLXSW_REG_MLCR_ID 0x902B 10022 #define MLXSW_REG_MLCR_LEN 0x0C 10023 10024 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10025 10026 /* reg_mlcr_local_port 10027 * Local port number. 10028 * Access: RW 10029 */ 10030 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 10031 10032 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10033 10034 /* reg_mlcr_beacon_duration 10035 * Duration of the beacon to be active, in seconds. 10036 * 0x0 - Will turn off the beacon. 10037 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10038 * Access: RW 10039 */ 10040 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10041 10042 /* reg_mlcr_beacon_remain 10043 * Remaining duration of the beacon, in seconds. 10044 * 0xFFFF indicates an infinite amount of time. 10045 * Access: RO 10046 */ 10047 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10048 10049 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 10050 bool active) 10051 { 10052 MLXSW_REG_ZERO(mlcr, payload); 10053 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10054 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10055 MLXSW_REG_MLCR_DURATION_MAX : 0); 10056 } 10057 10058 /* MTPPS - Management Pulse Per Second Register 10059 * -------------------------------------------- 10060 * This register provides the device PPS capabilities, configure the PPS in and 10061 * out modules and holds the PPS in time stamp. 10062 */ 10063 #define MLXSW_REG_MTPPS_ID 0x9053 10064 #define MLXSW_REG_MTPPS_LEN 0x3C 10065 10066 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10067 10068 /* reg_mtpps_enable 10069 * Enables the PPS functionality the specific pin. 10070 * A boolean variable. 10071 * Access: RW 10072 */ 10073 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10074 10075 enum mlxsw_reg_mtpps_pin_mode { 10076 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10077 }; 10078 10079 /* reg_mtpps_pin_mode 10080 * Pin mode to be used. The mode must comply with the supported modes of the 10081 * requested pin. 10082 * Access: RW 10083 */ 10084 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10085 10086 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10087 10088 /* reg_mtpps_pin 10089 * Pin to be configured or queried out of the supported pins. 10090 * Access: Index 10091 */ 10092 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10093 10094 /* reg_mtpps_time_stamp 10095 * When pin_mode = pps_in, the latched device time when it was triggered from 10096 * the external GPIO pin. 10097 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10098 * time to generate next output signal. 10099 * Time is in units of device clock. 10100 * Access: RW 10101 */ 10102 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10103 10104 static inline void 10105 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10106 { 10107 MLXSW_REG_ZERO(mtpps, payload); 10108 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10109 mlxsw_reg_mtpps_pin_mode_set(payload, 10110 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10111 mlxsw_reg_mtpps_enable_set(payload, true); 10112 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10113 } 10114 10115 /* MTUTC - Management UTC Register 10116 * ------------------------------- 10117 * Configures the HW UTC counter. 10118 */ 10119 #define MLXSW_REG_MTUTC_ID 0x9055 10120 #define MLXSW_REG_MTUTC_LEN 0x1C 10121 10122 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10123 10124 enum mlxsw_reg_mtutc_operation { 10125 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10126 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10127 }; 10128 10129 /* reg_mtutc_operation 10130 * Operation. 10131 * Access: OP 10132 */ 10133 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10134 10135 /* reg_mtutc_freq_adjustment 10136 * Frequency adjustment: Every PPS the HW frequency will be 10137 * adjusted by this value. Units of HW clock, where HW counts 10138 * 10^9 HW clocks for 1 HW second. 10139 * Access: RW 10140 */ 10141 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10142 10143 /* reg_mtutc_utc_sec 10144 * UTC seconds. 10145 * Access: WO 10146 */ 10147 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10148 10149 static inline void 10150 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10151 u32 freq_adj, u32 utc_sec) 10152 { 10153 MLXSW_REG_ZERO(mtutc, payload); 10154 mlxsw_reg_mtutc_operation_set(payload, oper); 10155 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10156 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10157 } 10158 10159 /* MCQI - Management Component Query Information 10160 * --------------------------------------------- 10161 * This register allows querying information about firmware components. 10162 */ 10163 #define MLXSW_REG_MCQI_ID 0x9061 10164 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10165 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10166 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10167 10168 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10169 10170 /* reg_mcqi_component_index 10171 * Index of the accessed component. 10172 * Access: Index 10173 */ 10174 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10175 10176 enum mlxfw_reg_mcqi_info_type { 10177 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10178 }; 10179 10180 /* reg_mcqi_info_type 10181 * Component properties set. 10182 * Access: RW 10183 */ 10184 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10185 10186 /* reg_mcqi_offset 10187 * The requested/returned data offset from the section start, given in bytes. 10188 * Must be DWORD aligned. 10189 * Access: RW 10190 */ 10191 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10192 10193 /* reg_mcqi_data_size 10194 * The requested/returned data size, given in bytes. If data_size is not DWORD 10195 * aligned, the last bytes are zero padded. 10196 * Access: RW 10197 */ 10198 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10199 10200 /* reg_mcqi_cap_max_component_size 10201 * Maximum size for this component, given in bytes. 10202 * Access: RO 10203 */ 10204 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10205 10206 /* reg_mcqi_cap_log_mcda_word_size 10207 * Log 2 of the access word size in bytes. Read and write access must be aligned 10208 * to the word size. Write access must be done for an integer number of words. 10209 * Access: RO 10210 */ 10211 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10212 10213 /* reg_mcqi_cap_mcda_max_write_size 10214 * Maximal write size for MCDA register 10215 * Access: RO 10216 */ 10217 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10218 10219 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10220 { 10221 MLXSW_REG_ZERO(mcqi, payload); 10222 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10223 mlxsw_reg_mcqi_info_type_set(payload, 10224 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10225 mlxsw_reg_mcqi_offset_set(payload, 0); 10226 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10227 } 10228 10229 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10230 u32 *p_cap_max_component_size, 10231 u8 *p_cap_log_mcda_word_size, 10232 u16 *p_cap_mcda_max_write_size) 10233 { 10234 *p_cap_max_component_size = 10235 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10236 *p_cap_log_mcda_word_size = 10237 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10238 *p_cap_mcda_max_write_size = 10239 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10240 } 10241 10242 /* MCC - Management Component Control 10243 * ---------------------------------- 10244 * Controls the firmware component and updates the FSM. 10245 */ 10246 #define MLXSW_REG_MCC_ID 0x9062 10247 #define MLXSW_REG_MCC_LEN 0x1C 10248 10249 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10250 10251 enum mlxsw_reg_mcc_instruction { 10252 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10253 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10254 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10255 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10256 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10257 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10258 }; 10259 10260 /* reg_mcc_instruction 10261 * Command to be executed by the FSM. 10262 * Applicable for write operation only. 10263 * Access: RW 10264 */ 10265 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10266 10267 /* reg_mcc_component_index 10268 * Index of the accessed component. Applicable only for commands that 10269 * refer to components. Otherwise, this field is reserved. 10270 * Access: Index 10271 */ 10272 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10273 10274 /* reg_mcc_update_handle 10275 * Token representing the current flow executed by the FSM. 10276 * Access: WO 10277 */ 10278 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10279 10280 /* reg_mcc_error_code 10281 * Indicates the successful completion of the instruction, or the reason it 10282 * failed 10283 * Access: RO 10284 */ 10285 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10286 10287 /* reg_mcc_control_state 10288 * Current FSM state 10289 * Access: RO 10290 */ 10291 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10292 10293 /* reg_mcc_component_size 10294 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10295 * the size may shorten the update time. Value 0x0 means that size is 10296 * unspecified. 10297 * Access: WO 10298 */ 10299 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10300 10301 static inline void mlxsw_reg_mcc_pack(char *payload, 10302 enum mlxsw_reg_mcc_instruction instr, 10303 u16 component_index, u32 update_handle, 10304 u32 component_size) 10305 { 10306 MLXSW_REG_ZERO(mcc, payload); 10307 mlxsw_reg_mcc_instruction_set(payload, instr); 10308 mlxsw_reg_mcc_component_index_set(payload, component_index); 10309 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10310 mlxsw_reg_mcc_component_size_set(payload, component_size); 10311 } 10312 10313 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10314 u8 *p_error_code, u8 *p_control_state) 10315 { 10316 if (p_update_handle) 10317 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10318 if (p_error_code) 10319 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10320 if (p_control_state) 10321 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10322 } 10323 10324 /* MCDA - Management Component Data Access 10325 * --------------------------------------- 10326 * This register allows reading and writing a firmware component. 10327 */ 10328 #define MLXSW_REG_MCDA_ID 0x9063 10329 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10330 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10331 #define MLXSW_REG_MCDA_LEN \ 10332 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10333 10334 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10335 10336 /* reg_mcda_update_handle 10337 * Token representing the current flow executed by the FSM. 10338 * Access: RW 10339 */ 10340 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10341 10342 /* reg_mcda_offset 10343 * Offset of accessed address relative to component start. Accesses must be in 10344 * accordance to log_mcda_word_size in MCQI reg. 10345 * Access: RW 10346 */ 10347 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10348 10349 /* reg_mcda_size 10350 * Size of the data accessed, given in bytes. 10351 * Access: RW 10352 */ 10353 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10354 10355 /* reg_mcda_data 10356 * Data block accessed. 10357 * Access: RW 10358 */ 10359 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10360 10361 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10362 u32 offset, u16 size, u8 *data) 10363 { 10364 int i; 10365 10366 MLXSW_REG_ZERO(mcda, payload); 10367 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10368 mlxsw_reg_mcda_offset_set(payload, offset); 10369 mlxsw_reg_mcda_size_set(payload, size); 10370 10371 for (i = 0; i < size / 4; i++) 10372 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10373 } 10374 10375 /* MPSC - Monitoring Packet Sampling Configuration Register 10376 * -------------------------------------------------------- 10377 * MPSC Register is used to configure the Packet Sampling mechanism. 10378 */ 10379 #define MLXSW_REG_MPSC_ID 0x9080 10380 #define MLXSW_REG_MPSC_LEN 0x1C 10381 10382 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10383 10384 /* reg_mpsc_local_port 10385 * Local port number 10386 * Not supported for CPU port 10387 * Access: Index 10388 */ 10389 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 10390 10391 /* reg_mpsc_e 10392 * Enable sampling on port local_port 10393 * Access: RW 10394 */ 10395 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10396 10397 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10398 10399 /* reg_mpsc_rate 10400 * Sampling rate = 1 out of rate packets (with randomization around 10401 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10402 * Access: RW 10403 */ 10404 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10405 10406 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 10407 u32 rate) 10408 { 10409 MLXSW_REG_ZERO(mpsc, payload); 10410 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10411 mlxsw_reg_mpsc_e_set(payload, e); 10412 mlxsw_reg_mpsc_rate_set(payload, rate); 10413 } 10414 10415 /* MGPC - Monitoring General Purpose Counter Set Register 10416 * The MGPC register retrieves and sets the General Purpose Counter Set. 10417 */ 10418 #define MLXSW_REG_MGPC_ID 0x9081 10419 #define MLXSW_REG_MGPC_LEN 0x18 10420 10421 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10422 10423 /* reg_mgpc_counter_set_type 10424 * Counter set type. 10425 * Access: OP 10426 */ 10427 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10428 10429 /* reg_mgpc_counter_index 10430 * Counter index. 10431 * Access: Index 10432 */ 10433 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10434 10435 enum mlxsw_reg_mgpc_opcode { 10436 /* Nop */ 10437 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10438 /* Clear counters */ 10439 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10440 }; 10441 10442 /* reg_mgpc_opcode 10443 * Opcode. 10444 * Access: OP 10445 */ 10446 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10447 10448 /* reg_mgpc_byte_counter 10449 * Byte counter value. 10450 * Access: RW 10451 */ 10452 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10453 10454 /* reg_mgpc_packet_counter 10455 * Packet counter value. 10456 * Access: RW 10457 */ 10458 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10459 10460 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10461 enum mlxsw_reg_mgpc_opcode opcode, 10462 enum mlxsw_reg_flow_counter_set_type set_type) 10463 { 10464 MLXSW_REG_ZERO(mgpc, payload); 10465 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10466 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10467 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10468 } 10469 10470 /* MPRS - Monitoring Parsing State Register 10471 * ---------------------------------------- 10472 * The MPRS register is used for setting up the parsing for hash, 10473 * policy-engine and routing. 10474 */ 10475 #define MLXSW_REG_MPRS_ID 0x9083 10476 #define MLXSW_REG_MPRS_LEN 0x14 10477 10478 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10479 10480 /* reg_mprs_parsing_depth 10481 * Minimum parsing depth. 10482 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10483 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10484 * Access: RW 10485 */ 10486 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10487 10488 /* reg_mprs_parsing_en 10489 * Parsing enable. 10490 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10491 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10492 * Access: RW 10493 */ 10494 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10495 10496 /* reg_mprs_vxlan_udp_dport 10497 * VxLAN UDP destination port. 10498 * Used for identifying VxLAN packets and for dport field in 10499 * encapsulation. Default is 4789. 10500 * Access: RW 10501 */ 10502 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10503 10504 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10505 u16 vxlan_udp_dport) 10506 { 10507 MLXSW_REG_ZERO(mprs, payload); 10508 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10509 mlxsw_reg_mprs_parsing_en_set(payload, true); 10510 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10511 } 10512 10513 /* MOGCR - Monitoring Global Configuration Register 10514 * ------------------------------------------------ 10515 */ 10516 #define MLXSW_REG_MOGCR_ID 0x9086 10517 #define MLXSW_REG_MOGCR_LEN 0x20 10518 10519 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10520 10521 /* reg_mogcr_ptp_iftc 10522 * PTP Ingress FIFO Trap Clear 10523 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10524 * to this value. Default 0. 10525 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10526 * Access: RW 10527 */ 10528 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10529 10530 /* reg_mogcr_ptp_eftc 10531 * PTP Egress FIFO Trap Clear 10532 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10533 * to this value. Default 0. 10534 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10535 * Access: RW 10536 */ 10537 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10538 10539 /* reg_mogcr_mirroring_pid_base 10540 * Base policer id for mirroring policers. 10541 * Must have an even value (e.g. 1000, not 1001). 10542 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10543 * Access: RW 10544 */ 10545 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10546 10547 /* MPAGR - Monitoring Port Analyzer Global Register 10548 * ------------------------------------------------ 10549 * This register is used for global port analyzer configurations. 10550 * Note: This register is not supported by current FW versions for Spectrum-1. 10551 */ 10552 #define MLXSW_REG_MPAGR_ID 0x9089 10553 #define MLXSW_REG_MPAGR_LEN 0x0C 10554 10555 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10556 10557 enum mlxsw_reg_mpagr_trigger { 10558 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10559 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10560 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10561 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10562 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10563 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10564 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10565 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10566 }; 10567 10568 /* reg_mpagr_trigger 10569 * Mirror trigger. 10570 * Access: Index 10571 */ 10572 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10573 10574 /* reg_mpagr_pa_id 10575 * Port analyzer ID. 10576 * Access: RW 10577 */ 10578 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10579 10580 /* reg_mpagr_probability_rate 10581 * Sampling rate. 10582 * Valid values are: 1 to 3.5*10^9 10583 * Value of 1 means "sample all". Default is 1. 10584 * Access: RW 10585 */ 10586 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10587 10588 static inline void mlxsw_reg_mpagr_pack(char *payload, 10589 enum mlxsw_reg_mpagr_trigger trigger, 10590 u8 pa_id, u32 probability_rate) 10591 { 10592 MLXSW_REG_ZERO(mpagr, payload); 10593 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10594 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10595 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10596 } 10597 10598 /* MOMTE - Monitoring Mirror Trigger Enable Register 10599 * ------------------------------------------------- 10600 * This register is used to configure the mirror enable for different mirror 10601 * reasons. 10602 */ 10603 #define MLXSW_REG_MOMTE_ID 0x908D 10604 #define MLXSW_REG_MOMTE_LEN 0x10 10605 10606 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10607 10608 /* reg_momte_local_port 10609 * Local port number. 10610 * Access: Index 10611 */ 10612 MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8); 10613 10614 enum mlxsw_reg_momte_type { 10615 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10616 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10617 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10618 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10619 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10620 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10621 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10622 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10623 }; 10624 10625 /* reg_momte_type 10626 * Type of mirroring. 10627 * Access: Index 10628 */ 10629 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10630 10631 /* reg_momte_tclass_en 10632 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10633 * 0: disable (default) 10634 * 1: enable 10635 * Access: RW 10636 */ 10637 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10638 10639 static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port, 10640 enum mlxsw_reg_momte_type type) 10641 { 10642 MLXSW_REG_ZERO(momte, payload); 10643 mlxsw_reg_momte_local_port_set(payload, local_port); 10644 mlxsw_reg_momte_type_set(payload, type); 10645 } 10646 10647 /* MTPPPC - Time Precision Packet Port Configuration 10648 * ------------------------------------------------- 10649 * This register serves for configuration of which PTP messages should be 10650 * timestamped. This is a global configuration, despite the register name. 10651 * 10652 * Reserved when Spectrum-2. 10653 */ 10654 #define MLXSW_REG_MTPPPC_ID 0x9090 10655 #define MLXSW_REG_MTPPPC_LEN 0x28 10656 10657 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10658 10659 /* reg_mtpppc_ing_timestamp_message_type 10660 * Bitwise vector of PTP message types to timestamp at ingress. 10661 * MessageType field as defined by IEEE 1588 10662 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10663 * Default all 0 10664 * Access: RW 10665 */ 10666 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10667 10668 /* reg_mtpppc_egr_timestamp_message_type 10669 * Bitwise vector of PTP message types to timestamp at egress. 10670 * MessageType field as defined by IEEE 1588 10671 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10672 * Default all 0 10673 * Access: RW 10674 */ 10675 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10676 10677 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10678 { 10679 MLXSW_REG_ZERO(mtpppc, payload); 10680 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10681 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10682 } 10683 10684 /* MTPPTR - Time Precision Packet Timestamping Reading 10685 * --------------------------------------------------- 10686 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10687 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10688 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10689 * trapped. The sequence number is used to synchronize the timestamp FIFO 10690 * entries and the trapped packets. 10691 * Reserved when Spectrum-2. 10692 */ 10693 10694 #define MLXSW_REG_MTPPTR_ID 0x9091 10695 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10696 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10697 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10698 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10699 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10700 10701 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10702 10703 /* reg_mtpptr_local_port 10704 * Not supported for CPU port. 10705 * Access: Index 10706 */ 10707 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 10708 10709 enum mlxsw_reg_mtpptr_dir { 10710 MLXSW_REG_MTPPTR_DIR_INGRESS, 10711 MLXSW_REG_MTPPTR_DIR_EGRESS, 10712 }; 10713 10714 /* reg_mtpptr_dir 10715 * Direction. 10716 * Access: Index 10717 */ 10718 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10719 10720 /* reg_mtpptr_clr 10721 * Clear the records. 10722 * Access: OP 10723 */ 10724 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10725 10726 /* reg_mtpptr_num_rec 10727 * Number of valid records in the response 10728 * Range 0.. cap_ptp_timestamp_fifo 10729 * Access: RO 10730 */ 10731 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10732 10733 /* reg_mtpptr_rec_message_type 10734 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10735 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10736 * Access: RO 10737 */ 10738 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10739 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10740 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10741 10742 /* reg_mtpptr_rec_domain_number 10743 * DomainNumber field as defined by IEEE 1588 10744 * Access: RO 10745 */ 10746 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10747 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10748 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10749 10750 /* reg_mtpptr_rec_sequence_id 10751 * SequenceId field as defined by IEEE 1588 10752 * Access: RO 10753 */ 10754 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10755 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10756 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10757 10758 /* reg_mtpptr_rec_timestamp_high 10759 * Timestamp of when the PTP packet has passed through the port Units of PLL 10760 * clock time. 10761 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10762 * Access: RO 10763 */ 10764 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10765 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10766 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10767 10768 /* reg_mtpptr_rec_timestamp_low 10769 * See rec_timestamp_high. 10770 * Access: RO 10771 */ 10772 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10773 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10774 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10775 10776 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10777 unsigned int rec, 10778 u8 *p_message_type, 10779 u8 *p_domain_number, 10780 u16 *p_sequence_id, 10781 u64 *p_timestamp) 10782 { 10783 u32 timestamp_high, timestamp_low; 10784 10785 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10786 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10787 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10788 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10789 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10790 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10791 } 10792 10793 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10794 * --------------------------------------------------------- 10795 * This register is used for configuring under which trap to deliver PTP 10796 * packets depending on type of the packet. 10797 */ 10798 #define MLXSW_REG_MTPTPT_ID 0x9092 10799 #define MLXSW_REG_MTPTPT_LEN 0x08 10800 10801 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10802 10803 enum mlxsw_reg_mtptpt_trap_id { 10804 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10805 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10806 }; 10807 10808 /* reg_mtptpt_trap_id 10809 * Trap id. 10810 * Access: Index 10811 */ 10812 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10813 10814 /* reg_mtptpt_message_type 10815 * Bitwise vector of PTP message types to trap. This is a necessary but 10816 * non-sufficient condition since need to enable also per port. See MTPPPC. 10817 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10818 * Bit0: Sync, Bit1: Delay_Req) 10819 */ 10820 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10821 10822 static inline void mlxsw_reg_mtptptp_pack(char *payload, 10823 enum mlxsw_reg_mtptpt_trap_id trap_id, 10824 u16 message_type) 10825 { 10826 MLXSW_REG_ZERO(mtptpt, payload); 10827 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10828 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10829 } 10830 10831 /* MFGD - Monitoring FW General Debug Register 10832 * ------------------------------------------- 10833 */ 10834 #define MLXSW_REG_MFGD_ID 0x90F0 10835 #define MLXSW_REG_MFGD_LEN 0x0C 10836 10837 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 10838 10839 /* reg_mfgd_fw_fatal_event_mode 10840 * 0 - don't check FW fatal (default) 10841 * 1 - check FW fatal - enable MFDE trap 10842 * Access: RW 10843 */ 10844 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 10845 10846 /* reg_mfgd_trigger_test 10847 * Access: WO 10848 */ 10849 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 10850 10851 /* MGPIR - Management General Peripheral Information Register 10852 * ---------------------------------------------------------- 10853 * MGPIR register allows software to query the hardware and 10854 * firmware general information of peripheral entities. 10855 */ 10856 #define MLXSW_REG_MGPIR_ID 0x9100 10857 #define MLXSW_REG_MGPIR_LEN 0xA0 10858 10859 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 10860 10861 enum mlxsw_reg_mgpir_device_type { 10862 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 10863 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 10864 }; 10865 10866 /* device_type 10867 * Access: RO 10868 */ 10869 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 10870 10871 /* devices_per_flash 10872 * Number of devices of device_type per flash (can be shared by few devices). 10873 * Access: RO 10874 */ 10875 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 10876 10877 /* num_of_devices 10878 * Number of devices of device_type. 10879 * Access: RO 10880 */ 10881 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 10882 10883 /* num_of_modules 10884 * Number of modules. 10885 * Access: RO 10886 */ 10887 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 10888 10889 static inline void mlxsw_reg_mgpir_pack(char *payload) 10890 { 10891 MLXSW_REG_ZERO(mgpir, payload); 10892 } 10893 10894 static inline void 10895 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 10896 enum mlxsw_reg_mgpir_device_type *device_type, 10897 u8 *devices_per_flash, u8 *num_of_modules) 10898 { 10899 if (num_of_devices) 10900 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 10901 if (device_type) 10902 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 10903 if (devices_per_flash) 10904 *devices_per_flash = 10905 mlxsw_reg_mgpir_devices_per_flash_get(payload); 10906 if (num_of_modules) 10907 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 10908 } 10909 10910 /* MFDE - Monitoring FW Debug Register 10911 * ----------------------------------- 10912 */ 10913 #define MLXSW_REG_MFDE_ID 0x9200 10914 #define MLXSW_REG_MFDE_LEN 0x18 10915 10916 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 10917 10918 /* reg_mfde_irisc_id 10919 * Which irisc triggered the event 10920 * Access: RO 10921 */ 10922 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 8, 4); 10923 10924 enum mlxsw_reg_mfde_event_id { 10925 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 10926 /* KVD insertion machine stopped */ 10927 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 10928 }; 10929 10930 /* reg_mfde_event_id 10931 * Access: RO 10932 */ 10933 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 8); 10934 10935 enum mlxsw_reg_mfde_method { 10936 MLXSW_REG_MFDE_METHOD_QUERY, 10937 MLXSW_REG_MFDE_METHOD_WRITE, 10938 }; 10939 10940 /* reg_mfde_method 10941 * Access: RO 10942 */ 10943 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 10944 10945 /* reg_mfde_long_process 10946 * Indicates if the command is in long_process mode. 10947 * Access: RO 10948 */ 10949 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 10950 10951 enum mlxsw_reg_mfde_command_type { 10952 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 10953 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 10954 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 10955 }; 10956 10957 /* reg_mfde_command_type 10958 * Access: RO 10959 */ 10960 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 10961 10962 /* reg_mfde_reg_attr_id 10963 * EMAD - register id, MAD - attibute id 10964 * Access: RO 10965 */ 10966 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 10967 10968 /* reg_mfde_log_address 10969 * crspace address accessed, which resulted in timeout. 10970 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10971 * Access: RO 10972 */ 10973 MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32); 10974 10975 /* reg_mfde_log_id 10976 * Which irisc triggered the timeout. 10977 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10978 * Access: RO 10979 */ 10980 MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4); 10981 10982 /* reg_mfde_pipes_mask 10983 * Bit per kvh pipe. 10984 * Access: RO 10985 */ 10986 MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16); 10987 10988 /* TNGCR - Tunneling NVE General Configuration Register 10989 * ---------------------------------------------------- 10990 * The TNGCR register is used for setting up the NVE Tunneling configuration. 10991 */ 10992 #define MLXSW_REG_TNGCR_ID 0xA001 10993 #define MLXSW_REG_TNGCR_LEN 0x44 10994 10995 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 10996 10997 enum mlxsw_reg_tngcr_type { 10998 MLXSW_REG_TNGCR_TYPE_VXLAN, 10999 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11000 MLXSW_REG_TNGCR_TYPE_GENEVE, 11001 MLXSW_REG_TNGCR_TYPE_NVGRE, 11002 }; 11003 11004 /* reg_tngcr_type 11005 * Tunnel type for encapsulation and decapsulation. The types are mutually 11006 * exclusive. 11007 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11008 * Access: RW 11009 */ 11010 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11011 11012 /* reg_tngcr_nve_valid 11013 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11014 * Access: RW 11015 */ 11016 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11017 11018 /* reg_tngcr_nve_ttl_uc 11019 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11020 * Access: RW 11021 */ 11022 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11023 11024 /* reg_tngcr_nve_ttl_mc 11025 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11026 * Access: RW 11027 */ 11028 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11029 11030 enum { 11031 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11032 MLXSW_REG_TNGCR_FL_NO_COPY, 11033 /* Copy flow label from inner packet if packet is IPv6 and 11034 * encapsulation is by IPv6. Otherwise, calculate flow label using 11035 * nve_flh. 11036 */ 11037 MLXSW_REG_TNGCR_FL_COPY, 11038 }; 11039 11040 /* reg_tngcr_nve_flc 11041 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11042 * Access: RW 11043 */ 11044 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11045 11046 enum { 11047 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11048 * uses {nve_fl_prefix, nve_fl_suffix}. 11049 */ 11050 MLXSW_REG_TNGCR_FL_NO_HASH, 11051 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11052 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11053 */ 11054 MLXSW_REG_TNGCR_FL_HASH, 11055 }; 11056 11057 /* reg_tngcr_nve_flh 11058 * NVE flow label hash. 11059 * Access: RW 11060 */ 11061 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11062 11063 /* reg_tngcr_nve_fl_prefix 11064 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11065 * Access: RW 11066 */ 11067 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11068 11069 /* reg_tngcr_nve_fl_suffix 11070 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11071 * Reserved when nve_flh=1 and for Spectrum. 11072 * Access: RW 11073 */ 11074 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11075 11076 enum { 11077 /* Source UDP port is fixed (default '0') */ 11078 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11079 /* Source UDP port is calculated based on hash */ 11080 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11081 }; 11082 11083 /* reg_tngcr_nve_udp_sport_type 11084 * NVE UDP source port type. 11085 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11086 * When the source UDP port is calculated based on hash, then the 8 LSBs 11087 * are calculated from hash the 8 MSBs are configured by 11088 * nve_udp_sport_prefix. 11089 * Access: RW 11090 */ 11091 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11092 11093 /* reg_tngcr_nve_udp_sport_prefix 11094 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11095 * Reserved when NVE type is NVGRE. 11096 * Access: RW 11097 */ 11098 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11099 11100 /* reg_tngcr_nve_group_size_mc 11101 * The amount of sequential linked lists of MC entries. The first linked 11102 * list is configured by SFD.underlay_mc_ptr. 11103 * Valid values: 1, 2, 4, 8, 16, 32, 64 11104 * The linked list are configured by TNUMT. 11105 * The hash is set by LAG hash. 11106 * Access: RW 11107 */ 11108 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11109 11110 /* reg_tngcr_nve_group_size_flood 11111 * The amount of sequential linked lists of flooding entries. The first 11112 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11113 * Valid values: 1, 2, 4, 8, 16, 32, 64 11114 * The linked list are configured by TNUMT. 11115 * The hash is set by LAG hash. 11116 * Access: RW 11117 */ 11118 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11119 11120 /* reg_tngcr_learn_enable 11121 * During decapsulation, whether to learn from NVE port. 11122 * Reserved when Spectrum-2. See TNPC. 11123 * Access: RW 11124 */ 11125 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11126 11127 /* reg_tngcr_underlay_virtual_router 11128 * Underlay virtual router. 11129 * Reserved when Spectrum-2. 11130 * Access: RW 11131 */ 11132 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11133 11134 /* reg_tngcr_underlay_rif 11135 * Underlay ingress router interface. RIF type should be loopback generic. 11136 * Reserved when Spectrum. 11137 * Access: RW 11138 */ 11139 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11140 11141 /* reg_tngcr_usipv4 11142 * Underlay source IPv4 address of the NVE. 11143 * Access: RW 11144 */ 11145 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11146 11147 /* reg_tngcr_usipv6 11148 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11149 * modified under traffic of NVE tunneling encapsulation. 11150 * Access: RW 11151 */ 11152 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11153 11154 static inline void mlxsw_reg_tngcr_pack(char *payload, 11155 enum mlxsw_reg_tngcr_type type, 11156 bool valid, u8 ttl) 11157 { 11158 MLXSW_REG_ZERO(tngcr, payload); 11159 mlxsw_reg_tngcr_type_set(payload, type); 11160 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11161 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11162 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11163 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11164 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11165 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11166 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11167 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11168 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11169 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11170 } 11171 11172 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11173 * ------------------------------------------------------- 11174 * The TNUMT register is for building the underlay MC table. It is used 11175 * for MC, flooding and BC traffic into the NVE tunnel. 11176 */ 11177 #define MLXSW_REG_TNUMT_ID 0xA003 11178 #define MLXSW_REG_TNUMT_LEN 0x20 11179 11180 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11181 11182 enum mlxsw_reg_tnumt_record_type { 11183 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11184 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11185 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11186 }; 11187 11188 /* reg_tnumt_record_type 11189 * Record type. 11190 * Access: RW 11191 */ 11192 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11193 11194 /* reg_tnumt_tunnel_port 11195 * Tunnel port. 11196 * Access: RW 11197 */ 11198 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11199 11200 /* reg_tnumt_underlay_mc_ptr 11201 * Index to the underlay multicast table. 11202 * For Spectrum the index is to the KVD linear. 11203 * Access: Index 11204 */ 11205 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11206 11207 /* reg_tnumt_vnext 11208 * The next_underlay_mc_ptr is valid. 11209 * Access: RW 11210 */ 11211 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11212 11213 /* reg_tnumt_next_underlay_mc_ptr 11214 * The next index to the underlay multicast table. 11215 * Access: RW 11216 */ 11217 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11218 11219 /* reg_tnumt_record_size 11220 * Number of IP addresses in the record. 11221 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11222 * Access: RW 11223 */ 11224 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11225 11226 /* reg_tnumt_udip 11227 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11228 * Access: RW 11229 */ 11230 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11231 11232 /* reg_tnumt_udip_ptr 11233 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11234 * i >= size. The IPv6 addresses are configured by RIPS. 11235 * Access: RW 11236 */ 11237 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11238 11239 static inline void mlxsw_reg_tnumt_pack(char *payload, 11240 enum mlxsw_reg_tnumt_record_type type, 11241 enum mlxsw_reg_tunnel_port tport, 11242 u32 underlay_mc_ptr, bool vnext, 11243 u32 next_underlay_mc_ptr, 11244 u8 record_size) 11245 { 11246 MLXSW_REG_ZERO(tnumt, payload); 11247 mlxsw_reg_tnumt_record_type_set(payload, type); 11248 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 11249 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 11250 mlxsw_reg_tnumt_vnext_set(payload, vnext); 11251 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 11252 mlxsw_reg_tnumt_record_size_set(payload, record_size); 11253 } 11254 11255 /* TNQCR - Tunneling NVE QoS Configuration Register 11256 * ------------------------------------------------ 11257 * The TNQCR register configures how QoS is set in encapsulation into the 11258 * underlay network. 11259 */ 11260 #define MLXSW_REG_TNQCR_ID 0xA010 11261 #define MLXSW_REG_TNQCR_LEN 0x0C 11262 11263 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 11264 11265 /* reg_tnqcr_enc_set_dscp 11266 * For encapsulation: How to set DSCP field: 11267 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 11268 * (outer) IP header. If there is no IP header, use TNQDR.dscp 11269 * 1 - Set the DSCP field as TNQDR.dscp 11270 * Access: RW 11271 */ 11272 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 11273 11274 static inline void mlxsw_reg_tnqcr_pack(char *payload) 11275 { 11276 MLXSW_REG_ZERO(tnqcr, payload); 11277 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 11278 } 11279 11280 /* TNQDR - Tunneling NVE QoS Default Register 11281 * ------------------------------------------ 11282 * The TNQDR register configures the default QoS settings for NVE 11283 * encapsulation. 11284 */ 11285 #define MLXSW_REG_TNQDR_ID 0xA011 11286 #define MLXSW_REG_TNQDR_LEN 0x08 11287 11288 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 11289 11290 /* reg_tnqdr_local_port 11291 * Local port number (receive port). CPU port is supported. 11292 * Access: Index 11293 */ 11294 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 11295 11296 /* reg_tnqdr_dscp 11297 * For encapsulation, the default DSCP. 11298 * Access: RW 11299 */ 11300 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 11301 11302 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 11303 { 11304 MLXSW_REG_ZERO(tnqdr, payload); 11305 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 11306 mlxsw_reg_tnqdr_dscp_set(payload, 0); 11307 } 11308 11309 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 11310 * -------------------------------------------------------- 11311 * The TNEEM register maps ECN of the IP header at the ingress to the 11312 * encapsulation to the ECN of the underlay network. 11313 */ 11314 #define MLXSW_REG_TNEEM_ID 0xA012 11315 #define MLXSW_REG_TNEEM_LEN 0x0C 11316 11317 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 11318 11319 /* reg_tneem_overlay_ecn 11320 * ECN of the IP header in the overlay network. 11321 * Access: Index 11322 */ 11323 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 11324 11325 /* reg_tneem_underlay_ecn 11326 * ECN of the IP header in the underlay network. 11327 * Access: RW 11328 */ 11329 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 11330 11331 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 11332 u8 underlay_ecn) 11333 { 11334 MLXSW_REG_ZERO(tneem, payload); 11335 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 11336 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 11337 } 11338 11339 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 11340 * -------------------------------------------------------- 11341 * The TNDEM register configures the actions that are done in the 11342 * decapsulation. 11343 */ 11344 #define MLXSW_REG_TNDEM_ID 0xA013 11345 #define MLXSW_REG_TNDEM_LEN 0x0C 11346 11347 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 11348 11349 /* reg_tndem_underlay_ecn 11350 * ECN field of the IP header in the underlay network. 11351 * Access: Index 11352 */ 11353 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 11354 11355 /* reg_tndem_overlay_ecn 11356 * ECN field of the IP header in the overlay network. 11357 * Access: Index 11358 */ 11359 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 11360 11361 /* reg_tndem_eip_ecn 11362 * Egress IP ECN. ECN field of the IP header of the packet which goes out 11363 * from the decapsulation. 11364 * Access: RW 11365 */ 11366 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 11367 11368 /* reg_tndem_trap_en 11369 * Trap enable: 11370 * 0 - No trap due to decap ECN 11371 * 1 - Trap enable with trap_id 11372 * Access: RW 11373 */ 11374 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 11375 11376 /* reg_tndem_trap_id 11377 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 11378 * Reserved when trap_en is '0'. 11379 * Access: RW 11380 */ 11381 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 11382 11383 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 11384 u8 overlay_ecn, u8 ecn, bool trap_en, 11385 u16 trap_id) 11386 { 11387 MLXSW_REG_ZERO(tndem, payload); 11388 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 11389 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 11390 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 11391 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 11392 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 11393 } 11394 11395 /* TNPC - Tunnel Port Configuration Register 11396 * ----------------------------------------- 11397 * The TNPC register is used for tunnel port configuration. 11398 * Reserved when Spectrum. 11399 */ 11400 #define MLXSW_REG_TNPC_ID 0xA020 11401 #define MLXSW_REG_TNPC_LEN 0x18 11402 11403 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 11404 11405 /* reg_tnpc_tunnel_port 11406 * Tunnel port. 11407 * Access: Index 11408 */ 11409 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 11410 11411 /* reg_tnpc_learn_enable_v6 11412 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 11413 * Access: RW 11414 */ 11415 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 11416 11417 /* reg_tnpc_learn_enable_v4 11418 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 11419 * Access: RW 11420 */ 11421 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 11422 11423 static inline void mlxsw_reg_tnpc_pack(char *payload, 11424 enum mlxsw_reg_tunnel_port tport, 11425 bool learn_enable) 11426 { 11427 MLXSW_REG_ZERO(tnpc, payload); 11428 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 11429 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 11430 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 11431 } 11432 11433 /* TIGCR - Tunneling IPinIP General Configuration Register 11434 * ------------------------------------------------------- 11435 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 11436 */ 11437 #define MLXSW_REG_TIGCR_ID 0xA801 11438 #define MLXSW_REG_TIGCR_LEN 0x10 11439 11440 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 11441 11442 /* reg_tigcr_ipip_ttlc 11443 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 11444 * header. 11445 * Access: RW 11446 */ 11447 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 11448 11449 /* reg_tigcr_ipip_ttl_uc 11450 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 11451 * reg_tigcr_ipip_ttlc is unset. 11452 * Access: RW 11453 */ 11454 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 11455 11456 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 11457 { 11458 MLXSW_REG_ZERO(tigcr, payload); 11459 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 11460 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 11461 } 11462 11463 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 11464 * ----------------------------------------------------------- 11465 * The TIEEM register maps ECN of the IP header at the ingress to the 11466 * encapsulation to the ECN of the underlay network. 11467 */ 11468 #define MLXSW_REG_TIEEM_ID 0xA812 11469 #define MLXSW_REG_TIEEM_LEN 0x0C 11470 11471 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 11472 11473 /* reg_tieem_overlay_ecn 11474 * ECN of the IP header in the overlay network. 11475 * Access: Index 11476 */ 11477 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 11478 11479 /* reg_tineem_underlay_ecn 11480 * ECN of the IP header in the underlay network. 11481 * Access: RW 11482 */ 11483 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 11484 11485 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 11486 u8 underlay_ecn) 11487 { 11488 MLXSW_REG_ZERO(tieem, payload); 11489 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 11490 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 11491 } 11492 11493 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 11494 * ----------------------------------------------------------- 11495 * The TIDEM register configures the actions that are done in the 11496 * decapsulation. 11497 */ 11498 #define MLXSW_REG_TIDEM_ID 0xA813 11499 #define MLXSW_REG_TIDEM_LEN 0x0C 11500 11501 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 11502 11503 /* reg_tidem_underlay_ecn 11504 * ECN field of the IP header in the underlay network. 11505 * Access: Index 11506 */ 11507 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 11508 11509 /* reg_tidem_overlay_ecn 11510 * ECN field of the IP header in the overlay network. 11511 * Access: Index 11512 */ 11513 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 11514 11515 /* reg_tidem_eip_ecn 11516 * Egress IP ECN. ECN field of the IP header of the packet which goes out 11517 * from the decapsulation. 11518 * Access: RW 11519 */ 11520 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 11521 11522 /* reg_tidem_trap_en 11523 * Trap enable: 11524 * 0 - No trap due to decap ECN 11525 * 1 - Trap enable with trap_id 11526 * Access: RW 11527 */ 11528 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 11529 11530 /* reg_tidem_trap_id 11531 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 11532 * Reserved when trap_en is '0'. 11533 * Access: RW 11534 */ 11535 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 11536 11537 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 11538 u8 overlay_ecn, u8 eip_ecn, 11539 bool trap_en, u16 trap_id) 11540 { 11541 MLXSW_REG_ZERO(tidem, payload); 11542 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 11543 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 11544 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 11545 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 11546 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 11547 } 11548 11549 /* SBPR - Shared Buffer Pools Register 11550 * ----------------------------------- 11551 * The SBPR configures and retrieves the shared buffer pools and configuration. 11552 */ 11553 #define MLXSW_REG_SBPR_ID 0xB001 11554 #define MLXSW_REG_SBPR_LEN 0x14 11555 11556 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 11557 11558 /* shared direstion enum for SBPR, SBCM, SBPM */ 11559 enum mlxsw_reg_sbxx_dir { 11560 MLXSW_REG_SBXX_DIR_INGRESS, 11561 MLXSW_REG_SBXX_DIR_EGRESS, 11562 }; 11563 11564 /* reg_sbpr_dir 11565 * Direction. 11566 * Access: Index 11567 */ 11568 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 11569 11570 /* reg_sbpr_pool 11571 * Pool index. 11572 * Access: Index 11573 */ 11574 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 11575 11576 /* reg_sbpr_infi_size 11577 * Size is infinite. 11578 * Access: RW 11579 */ 11580 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 11581 11582 /* reg_sbpr_size 11583 * Pool size in buffer cells. 11584 * Reserved when infi_size = 1. 11585 * Access: RW 11586 */ 11587 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 11588 11589 enum mlxsw_reg_sbpr_mode { 11590 MLXSW_REG_SBPR_MODE_STATIC, 11591 MLXSW_REG_SBPR_MODE_DYNAMIC, 11592 }; 11593 11594 /* reg_sbpr_mode 11595 * Pool quota calculation mode. 11596 * Access: RW 11597 */ 11598 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 11599 11600 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 11601 enum mlxsw_reg_sbxx_dir dir, 11602 enum mlxsw_reg_sbpr_mode mode, u32 size, 11603 bool infi_size) 11604 { 11605 MLXSW_REG_ZERO(sbpr, payload); 11606 mlxsw_reg_sbpr_pool_set(payload, pool); 11607 mlxsw_reg_sbpr_dir_set(payload, dir); 11608 mlxsw_reg_sbpr_mode_set(payload, mode); 11609 mlxsw_reg_sbpr_size_set(payload, size); 11610 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 11611 } 11612 11613 /* SBCM - Shared Buffer Class Management Register 11614 * ---------------------------------------------- 11615 * The SBCM register configures and retrieves the shared buffer allocation 11616 * and configuration according to Port-PG, including the binding to pool 11617 * and definition of the associated quota. 11618 */ 11619 #define MLXSW_REG_SBCM_ID 0xB002 11620 #define MLXSW_REG_SBCM_LEN 0x28 11621 11622 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 11623 11624 /* reg_sbcm_local_port 11625 * Local port number. 11626 * For Ingress: excludes CPU port and Router port 11627 * For Egress: excludes IP Router 11628 * Access: Index 11629 */ 11630 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 11631 11632 /* reg_sbcm_pg_buff 11633 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 11634 * For PG buffer: range is 0..cap_max_pg_buffers - 1 11635 * For traffic class: range is 0..cap_max_tclass - 1 11636 * Note that when traffic class is in MC aware mode then the traffic 11637 * classes which are MC aware cannot be configured. 11638 * Access: Index 11639 */ 11640 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 11641 11642 /* reg_sbcm_dir 11643 * Direction. 11644 * Access: Index 11645 */ 11646 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 11647 11648 /* reg_sbcm_min_buff 11649 * Minimum buffer size for the limiter, in cells. 11650 * Access: RW 11651 */ 11652 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 11653 11654 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 11655 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 11656 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 11657 11658 /* reg_sbcm_infi_max 11659 * Max buffer is infinite. 11660 * Access: RW 11661 */ 11662 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 11663 11664 /* reg_sbcm_max_buff 11665 * When the pool associated to the port-pg/tclass is configured to 11666 * static, Maximum buffer size for the limiter configured in cells. 11667 * When the pool associated to the port-pg/tclass is configured to 11668 * dynamic, the max_buff holds the "alpha" parameter, supporting 11669 * the following values: 11670 * 0: 0 11671 * i: (1/128)*2^(i-1), for i=1..14 11672 * 0xFF: Infinity 11673 * Reserved when infi_max = 1. 11674 * Access: RW 11675 */ 11676 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 11677 11678 /* reg_sbcm_pool 11679 * Association of the port-priority to a pool. 11680 * Access: RW 11681 */ 11682 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 11683 11684 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 11685 enum mlxsw_reg_sbxx_dir dir, 11686 u32 min_buff, u32 max_buff, 11687 bool infi_max, u8 pool) 11688 { 11689 MLXSW_REG_ZERO(sbcm, payload); 11690 mlxsw_reg_sbcm_local_port_set(payload, local_port); 11691 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 11692 mlxsw_reg_sbcm_dir_set(payload, dir); 11693 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 11694 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 11695 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 11696 mlxsw_reg_sbcm_pool_set(payload, pool); 11697 } 11698 11699 /* SBPM - Shared Buffer Port Management Register 11700 * --------------------------------------------- 11701 * The SBPM register configures and retrieves the shared buffer allocation 11702 * and configuration according to Port-Pool, including the definition 11703 * of the associated quota. 11704 */ 11705 #define MLXSW_REG_SBPM_ID 0xB003 11706 #define MLXSW_REG_SBPM_LEN 0x28 11707 11708 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 11709 11710 /* reg_sbpm_local_port 11711 * Local port number. 11712 * For Ingress: excludes CPU port and Router port 11713 * For Egress: excludes IP Router 11714 * Access: Index 11715 */ 11716 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 11717 11718 /* reg_sbpm_pool 11719 * The pool associated to quota counting on the local_port. 11720 * Access: Index 11721 */ 11722 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 11723 11724 /* reg_sbpm_dir 11725 * Direction. 11726 * Access: Index 11727 */ 11728 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 11729 11730 /* reg_sbpm_buff_occupancy 11731 * Current buffer occupancy in cells. 11732 * Access: RO 11733 */ 11734 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 11735 11736 /* reg_sbpm_clr 11737 * Clear Max Buffer Occupancy 11738 * When this bit is set, max_buff_occupancy field is cleared (and a 11739 * new max value is tracked from the time the clear was performed). 11740 * Access: OP 11741 */ 11742 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 11743 11744 /* reg_sbpm_max_buff_occupancy 11745 * Maximum value of buffer occupancy in cells monitored. Cleared by 11746 * writing to the clr field. 11747 * Access: RO 11748 */ 11749 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 11750 11751 /* reg_sbpm_min_buff 11752 * Minimum buffer size for the limiter, in cells. 11753 * Access: RW 11754 */ 11755 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 11756 11757 /* reg_sbpm_max_buff 11758 * When the pool associated to the port-pg/tclass is configured to 11759 * static, Maximum buffer size for the limiter configured in cells. 11760 * When the pool associated to the port-pg/tclass is configured to 11761 * dynamic, the max_buff holds the "alpha" parameter, supporting 11762 * the following values: 11763 * 0: 0 11764 * i: (1/128)*2^(i-1), for i=1..14 11765 * 0xFF: Infinity 11766 * Access: RW 11767 */ 11768 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 11769 11770 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 11771 enum mlxsw_reg_sbxx_dir dir, bool clr, 11772 u32 min_buff, u32 max_buff) 11773 { 11774 MLXSW_REG_ZERO(sbpm, payload); 11775 mlxsw_reg_sbpm_local_port_set(payload, local_port); 11776 mlxsw_reg_sbpm_pool_set(payload, pool); 11777 mlxsw_reg_sbpm_dir_set(payload, dir); 11778 mlxsw_reg_sbpm_clr_set(payload, clr); 11779 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 11780 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 11781 } 11782 11783 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 11784 u32 *p_max_buff_occupancy) 11785 { 11786 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 11787 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 11788 } 11789 11790 /* SBMM - Shared Buffer Multicast Management Register 11791 * -------------------------------------------------- 11792 * The SBMM register configures and retrieves the shared buffer allocation 11793 * and configuration for MC packets according to Switch-Priority, including 11794 * the binding to pool and definition of the associated quota. 11795 */ 11796 #define MLXSW_REG_SBMM_ID 0xB004 11797 #define MLXSW_REG_SBMM_LEN 0x28 11798 11799 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 11800 11801 /* reg_sbmm_prio 11802 * Switch Priority. 11803 * Access: Index 11804 */ 11805 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 11806 11807 /* reg_sbmm_min_buff 11808 * Minimum buffer size for the limiter, in cells. 11809 * Access: RW 11810 */ 11811 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 11812 11813 /* reg_sbmm_max_buff 11814 * When the pool associated to the port-pg/tclass is configured to 11815 * static, Maximum buffer size for the limiter configured in cells. 11816 * When the pool associated to the port-pg/tclass is configured to 11817 * dynamic, the max_buff holds the "alpha" parameter, supporting 11818 * the following values: 11819 * 0: 0 11820 * i: (1/128)*2^(i-1), for i=1..14 11821 * 0xFF: Infinity 11822 * Access: RW 11823 */ 11824 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 11825 11826 /* reg_sbmm_pool 11827 * Association of the port-priority to a pool. 11828 * Access: RW 11829 */ 11830 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 11831 11832 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 11833 u32 max_buff, u8 pool) 11834 { 11835 MLXSW_REG_ZERO(sbmm, payload); 11836 mlxsw_reg_sbmm_prio_set(payload, prio); 11837 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 11838 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 11839 mlxsw_reg_sbmm_pool_set(payload, pool); 11840 } 11841 11842 /* SBSR - Shared Buffer Status Register 11843 * ------------------------------------ 11844 * The SBSR register retrieves the shared buffer occupancy according to 11845 * Port-Pool. Note that this register enables reading a large amount of data. 11846 * It is the user's responsibility to limit the amount of data to ensure the 11847 * response can match the maximum transfer unit. In case the response exceeds 11848 * the maximum transport unit, it will be truncated with no special notice. 11849 */ 11850 #define MLXSW_REG_SBSR_ID 0xB005 11851 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 11852 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 11853 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 11854 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 11855 MLXSW_REG_SBSR_REC_LEN * \ 11856 MLXSW_REG_SBSR_REC_MAX_COUNT) 11857 11858 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 11859 11860 /* reg_sbsr_clr 11861 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 11862 * field is cleared (and a new max value is tracked from the time the clear 11863 * was performed). 11864 * Access: OP 11865 */ 11866 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 11867 11868 /* reg_sbsr_ingress_port_mask 11869 * Bit vector for all ingress network ports. 11870 * Indicates which of the ports (for which the relevant bit is set) 11871 * are affected by the set operation. Configuration of any other port 11872 * does not change. 11873 * Access: Index 11874 */ 11875 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 11876 11877 /* reg_sbsr_pg_buff_mask 11878 * Bit vector for all switch priority groups. 11879 * Indicates which of the priorities (for which the relevant bit is set) 11880 * are affected by the set operation. Configuration of any other priority 11881 * does not change. 11882 * Range is 0..cap_max_pg_buffers - 1 11883 * Access: Index 11884 */ 11885 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 11886 11887 /* reg_sbsr_egress_port_mask 11888 * Bit vector for all egress network ports. 11889 * Indicates which of the ports (for which the relevant bit is set) 11890 * are affected by the set operation. Configuration of any other port 11891 * does not change. 11892 * Access: Index 11893 */ 11894 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 11895 11896 /* reg_sbsr_tclass_mask 11897 * Bit vector for all traffic classes. 11898 * Indicates which of the traffic classes (for which the relevant bit is 11899 * set) are affected by the set operation. Configuration of any other 11900 * traffic class does not change. 11901 * Range is 0..cap_max_tclass - 1 11902 * Access: Index 11903 */ 11904 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 11905 11906 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 11907 { 11908 MLXSW_REG_ZERO(sbsr, payload); 11909 mlxsw_reg_sbsr_clr_set(payload, clr); 11910 } 11911 11912 /* reg_sbsr_rec_buff_occupancy 11913 * Current buffer occupancy in cells. 11914 * Access: RO 11915 */ 11916 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11917 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 11918 11919 /* reg_sbsr_rec_max_buff_occupancy 11920 * Maximum value of buffer occupancy in cells monitored. Cleared by 11921 * writing to the clr field. 11922 * Access: RO 11923 */ 11924 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11925 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 11926 11927 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 11928 u32 *p_buff_occupancy, 11929 u32 *p_max_buff_occupancy) 11930 { 11931 *p_buff_occupancy = 11932 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 11933 *p_max_buff_occupancy = 11934 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 11935 } 11936 11937 /* SBIB - Shared Buffer Internal Buffer Register 11938 * --------------------------------------------- 11939 * The SBIB register configures per port buffers for internal use. The internal 11940 * buffers consume memory on the port buffers (note that the port buffers are 11941 * used also by PBMC). 11942 * 11943 * For Spectrum this is used for egress mirroring. 11944 */ 11945 #define MLXSW_REG_SBIB_ID 0xB006 11946 #define MLXSW_REG_SBIB_LEN 0x10 11947 11948 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 11949 11950 /* reg_sbib_local_port 11951 * Local port number 11952 * Not supported for CPU port and router port 11953 * Access: Index 11954 */ 11955 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 11956 11957 /* reg_sbib_buff_size 11958 * Units represented in cells 11959 * Allowed range is 0 to (cap_max_headroom_size - 1) 11960 * Default is 0 11961 * Access: RW 11962 */ 11963 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 11964 11965 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 11966 u32 buff_size) 11967 { 11968 MLXSW_REG_ZERO(sbib, payload); 11969 mlxsw_reg_sbib_local_port_set(payload, local_port); 11970 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 11971 } 11972 11973 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 11974 MLXSW_REG(sgcr), 11975 MLXSW_REG(spad), 11976 MLXSW_REG(smid), 11977 MLXSW_REG(sspr), 11978 MLXSW_REG(sfdat), 11979 MLXSW_REG(sfd), 11980 MLXSW_REG(sfn), 11981 MLXSW_REG(spms), 11982 MLXSW_REG(spvid), 11983 MLXSW_REG(spvm), 11984 MLXSW_REG(spaft), 11985 MLXSW_REG(sfgc), 11986 MLXSW_REG(sftr), 11987 MLXSW_REG(sfdf), 11988 MLXSW_REG(sldr), 11989 MLXSW_REG(slcr), 11990 MLXSW_REG(slcor), 11991 MLXSW_REG(spmlr), 11992 MLXSW_REG(svfa), 11993 MLXSW_REG(spvtr), 11994 MLXSW_REG(svpe), 11995 MLXSW_REG(sfmr), 11996 MLXSW_REG(spvmlr), 11997 MLXSW_REG(spvc), 11998 MLXSW_REG(cwtp), 11999 MLXSW_REG(cwtpm), 12000 MLXSW_REG(pgcr), 12001 MLXSW_REG(ppbt), 12002 MLXSW_REG(pacl), 12003 MLXSW_REG(pagt), 12004 MLXSW_REG(ptar), 12005 MLXSW_REG(ppbs), 12006 MLXSW_REG(prcr), 12007 MLXSW_REG(pefa), 12008 MLXSW_REG(pemrbt), 12009 MLXSW_REG(ptce2), 12010 MLXSW_REG(perpt), 12011 MLXSW_REG(peabfe), 12012 MLXSW_REG(perar), 12013 MLXSW_REG(ptce3), 12014 MLXSW_REG(percr), 12015 MLXSW_REG(pererp), 12016 MLXSW_REG(iedr), 12017 MLXSW_REG(qpts), 12018 MLXSW_REG(qpcr), 12019 MLXSW_REG(qtct), 12020 MLXSW_REG(qeec), 12021 MLXSW_REG(qrwe), 12022 MLXSW_REG(qpdsm), 12023 MLXSW_REG(qpdp), 12024 MLXSW_REG(qpdpm), 12025 MLXSW_REG(qtctm), 12026 MLXSW_REG(qpsc), 12027 MLXSW_REG(pmlp), 12028 MLXSW_REG(pmtu), 12029 MLXSW_REG(ptys), 12030 MLXSW_REG(ppad), 12031 MLXSW_REG(paos), 12032 MLXSW_REG(pfcc), 12033 MLXSW_REG(ppcnt), 12034 MLXSW_REG(plib), 12035 MLXSW_REG(pptb), 12036 MLXSW_REG(pbmc), 12037 MLXSW_REG(pspa), 12038 MLXSW_REG(pmaos), 12039 MLXSW_REG(pplr), 12040 MLXSW_REG(pmpe), 12041 MLXSW_REG(pddr), 12042 MLXSW_REG(pmtm), 12043 MLXSW_REG(htgt), 12044 MLXSW_REG(hpkt), 12045 MLXSW_REG(rgcr), 12046 MLXSW_REG(ritr), 12047 MLXSW_REG(rtar), 12048 MLXSW_REG(ratr), 12049 MLXSW_REG(rtdp), 12050 MLXSW_REG(rdpm), 12051 MLXSW_REG(ricnt), 12052 MLXSW_REG(rrcr), 12053 MLXSW_REG(ralta), 12054 MLXSW_REG(ralst), 12055 MLXSW_REG(raltb), 12056 MLXSW_REG(ralue), 12057 MLXSW_REG(rauht), 12058 MLXSW_REG(raleu), 12059 MLXSW_REG(rauhtd), 12060 MLXSW_REG(rigr2), 12061 MLXSW_REG(recr2), 12062 MLXSW_REG(rmft2), 12063 MLXSW_REG(rxlte), 12064 MLXSW_REG(rxltm), 12065 MLXSW_REG(rlcmld), 12066 MLXSW_REG(rlpmce), 12067 MLXSW_REG(xltq), 12068 MLXSW_REG(xmdr), 12069 MLXSW_REG(xrmt), 12070 MLXSW_REG(xralta), 12071 MLXSW_REG(xralst), 12072 MLXSW_REG(xraltb), 12073 MLXSW_REG(mfcr), 12074 MLXSW_REG(mfsc), 12075 MLXSW_REG(mfsm), 12076 MLXSW_REG(mfsl), 12077 MLXSW_REG(fore), 12078 MLXSW_REG(mtcap), 12079 MLXSW_REG(mtmp), 12080 MLXSW_REG(mtwe), 12081 MLXSW_REG(mtbr), 12082 MLXSW_REG(mcia), 12083 MLXSW_REG(mpat), 12084 MLXSW_REG(mpar), 12085 MLXSW_REG(mgir), 12086 MLXSW_REG(mrsr), 12087 MLXSW_REG(mlcr), 12088 MLXSW_REG(mtpps), 12089 MLXSW_REG(mtutc), 12090 MLXSW_REG(mpsc), 12091 MLXSW_REG(mcqi), 12092 MLXSW_REG(mcc), 12093 MLXSW_REG(mcda), 12094 MLXSW_REG(mgpc), 12095 MLXSW_REG(mprs), 12096 MLXSW_REG(mogcr), 12097 MLXSW_REG(mpagr), 12098 MLXSW_REG(momte), 12099 MLXSW_REG(mtpppc), 12100 MLXSW_REG(mtpptr), 12101 MLXSW_REG(mtptpt), 12102 MLXSW_REG(mfgd), 12103 MLXSW_REG(mgpir), 12104 MLXSW_REG(mfde), 12105 MLXSW_REG(tngcr), 12106 MLXSW_REG(tnumt), 12107 MLXSW_REG(tnqcr), 12108 MLXSW_REG(tnqdr), 12109 MLXSW_REG(tneem), 12110 MLXSW_REG(tndem), 12111 MLXSW_REG(tnpc), 12112 MLXSW_REG(tigcr), 12113 MLXSW_REG(tieem), 12114 MLXSW_REG(tidem), 12115 MLXSW_REG(sbpr), 12116 MLXSW_REG(sbcm), 12117 MLXSW_REG(sbpm), 12118 MLXSW_REG(sbmm), 12119 MLXSW_REG(sbsr), 12120 MLXSW_REG(sbib), 12121 }; 12122 12123 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12124 { 12125 const struct mlxsw_reg_info *reg_info; 12126 int i; 12127 12128 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12129 reg_info = mlxsw_reg_infos[i]; 12130 if (reg_info->id == reg_id) 12131 return reg_info->name; 12132 } 12133 return "*UNKNOWN*"; 12134 } 12135 12136 /* PUDE - Port Up / Down Event 12137 * --------------------------- 12138 * Reports the operational state change of a port. 12139 */ 12140 #define MLXSW_REG_PUDE_LEN 0x10 12141 12142 /* reg_pude_swid 12143 * Switch partition ID with which to associate the port. 12144 * Access: Index 12145 */ 12146 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12147 12148 /* reg_pude_local_port 12149 * Local port number. 12150 * Access: Index 12151 */ 12152 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 12153 12154 /* reg_pude_admin_status 12155 * Port administrative state (the desired state). 12156 * 1 - Up. 12157 * 2 - Down. 12158 * 3 - Up once. This means that in case of link failure, the port won't go 12159 * into polling mode, but will wait to be re-enabled by software. 12160 * 4 - Disabled by system. Can only be set by hardware. 12161 * Access: RO 12162 */ 12163 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12164 12165 /* reg_pude_oper_status 12166 * Port operatioanl state. 12167 * 1 - Up. 12168 * 2 - Down. 12169 * 3 - Down by port failure. This means that the device will not let the 12170 * port up again until explicitly specified by software. 12171 * Access: RO 12172 */ 12173 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12174 12175 #endif 12176