1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_set_vid 326 * Set VID. 327 * 0 - Do not update VID. 328 * 1 - Set VID. 329 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 330 * Access: RW 331 * 332 * Note: Reserved when legacy bridge model is used. 333 */ 334 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 335 MLXSW_REG_SFD_REC_LEN, 0x08, false); 336 337 /* reg_sfd_uc_fid_vid 338 * Filtering ID or VLAN ID 339 * For SwitchX and SwitchX-2: 340 * - Dynamic entries (policy 2,3) use FID 341 * - Static entries (policy 0) use VID 342 * - When independent learning is configured, VID=FID 343 * For Spectrum: use FID for both Dynamic and Static entries. 344 * VID should not be used. 345 * Access: Index 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 348 MLXSW_REG_SFD_REC_LEN, 0x08, false); 349 350 /* reg_sfd_uc_vid 351 * New VID when set_vid=1. 352 * Access: RW 353 * 354 * Note: Reserved when legacy bridge model is used and when set_vid=0. 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 357 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 358 359 /* reg_sfd_uc_system_port 360 * Unique port identifier for the final destination of the packet. 361 * Access: RW 362 */ 363 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 364 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 365 366 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 367 enum mlxsw_reg_sfd_rec_type rec_type, 368 const char *mac, 369 enum mlxsw_reg_sfd_rec_action action) 370 { 371 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 372 373 if (rec_index >= num_rec) 374 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 375 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 376 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 377 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 378 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 379 } 380 381 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 382 enum mlxsw_reg_sfd_rec_policy policy, 383 const char *mac, u16 fid_vid, 384 enum mlxsw_reg_sfd_rec_action action, 385 u16 local_port) 386 { 387 mlxsw_reg_sfd_rec_pack(payload, rec_index, 388 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 389 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 390 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 391 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 392 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 393 } 394 395 /* reg_sfd_uc_lag_sub_port 396 * LAG sub port. 397 * Must be 0 if multichannel VEPA is not enabled. 398 * Access: RW 399 */ 400 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 401 MLXSW_REG_SFD_REC_LEN, 0x08, false); 402 403 /* reg_sfd_uc_lag_set_vid 404 * Set VID. 405 * 0 - Do not update VID. 406 * 1 - Set VID. 407 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 408 * Access: RW 409 * 410 * Note: Reserved when legacy bridge model is used. 411 */ 412 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 413 MLXSW_REG_SFD_REC_LEN, 0x08, false); 414 415 /* reg_sfd_uc_lag_fid_vid 416 * Filtering ID or VLAN ID 417 * For SwitchX and SwitchX-2: 418 * - Dynamic entries (policy 2,3) use FID 419 * - Static entries (policy 0) use VID 420 * - When independent learning is configured, VID=FID 421 * For Spectrum: use FID for both Dynamic and Static entries. 422 * VID should not be used. 423 * Access: Index 424 */ 425 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 426 MLXSW_REG_SFD_REC_LEN, 0x08, false); 427 428 /* reg_sfd_uc_lag_lag_vid 429 * New vlan ID. 430 * Access: RW 431 * 432 * Note: Reserved when legacy bridge model is used and set_vid=0. 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 435 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 436 437 /* reg_sfd_uc_lag_lag_id 438 * LAG Identifier - pointer into the LAG descriptor table. 439 * Access: RW 440 */ 441 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 442 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 443 444 static inline void 445 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 446 enum mlxsw_reg_sfd_rec_policy policy, 447 const char *mac, u16 fid_vid, 448 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 449 u16 lag_id) 450 { 451 mlxsw_reg_sfd_rec_pack(payload, rec_index, 452 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 453 mac, action); 454 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 455 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 456 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 457 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 458 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 459 } 460 461 /* reg_sfd_mc_pgi 462 * 463 * Multicast port group index - index into the port group table. 464 * Value 0x1FFF indicates the pgi should point to the MID entry. 465 * For Spectrum this value must be set to 0x1FFF 466 * Access: RW 467 */ 468 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 469 MLXSW_REG_SFD_REC_LEN, 0x08, false); 470 471 /* reg_sfd_mc_fid_vid 472 * 473 * Filtering ID or VLAN ID 474 * Access: Index 475 */ 476 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 477 MLXSW_REG_SFD_REC_LEN, 0x08, false); 478 479 /* reg_sfd_mc_mid 480 * 481 * Multicast identifier - global identifier that represents the multicast 482 * group across all devices. 483 * Access: RW 484 */ 485 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 486 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 487 488 static inline void 489 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 490 const char *mac, u16 fid_vid, 491 enum mlxsw_reg_sfd_rec_action action, u16 mid) 492 { 493 mlxsw_reg_sfd_rec_pack(payload, rec_index, 494 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 495 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 496 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 497 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 498 } 499 500 /* reg_sfd_uc_tunnel_uip_msb 501 * When protocol is IPv4, the most significant byte of the underlay IPv4 502 * destination IP. 503 * When protocol is IPv6, reserved. 504 * Access: RW 505 */ 506 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 507 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 508 509 /* reg_sfd_uc_tunnel_fid 510 * Filtering ID. 511 * Access: Index 512 */ 513 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 514 MLXSW_REG_SFD_REC_LEN, 0x08, false); 515 516 enum mlxsw_reg_sfd_uc_tunnel_protocol { 517 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 518 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 519 }; 520 521 /* reg_sfd_uc_tunnel_protocol 522 * IP protocol. 523 * Access: RW 524 */ 525 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 526 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 527 528 /* reg_sfd_uc_tunnel_uip_lsb 529 * When protocol is IPv4, the least significant bytes of the underlay 530 * IPv4 destination IP. 531 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 532 * which is configured by RIPS. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 536 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 537 538 static inline void 539 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 540 enum mlxsw_reg_sfd_rec_policy policy, 541 const char *mac, u16 fid, 542 enum mlxsw_reg_sfd_rec_action action, 543 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 544 { 545 mlxsw_reg_sfd_rec_pack(payload, rec_index, 546 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 547 action); 548 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 549 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 550 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 551 } 552 553 static inline void 554 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 555 enum mlxsw_reg_sfd_rec_policy policy, 556 const char *mac, u16 fid, 557 enum mlxsw_reg_sfd_rec_action action, u32 uip) 558 { 559 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 560 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 561 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 562 action, 563 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 564 } 565 566 static inline void 567 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 568 u16 fid, enum mlxsw_reg_sfd_rec_action action, 569 u32 uip_ptr) 570 { 571 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 572 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 573 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 574 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 575 mac, fid, action, 576 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 577 } 578 579 enum mlxsw_reg_tunnel_port { 580 MLXSW_REG_TUNNEL_PORT_NVE, 581 MLXSW_REG_TUNNEL_PORT_VPLS, 582 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 583 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 584 }; 585 586 /* SFN - Switch FDB Notification Register 587 * ------------------------------------------- 588 * The switch provides notifications on newly learned FDB entries and 589 * aged out entries. The notifications can be polled by software. 590 */ 591 #define MLXSW_REG_SFN_ID 0x200B 592 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 593 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 594 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 595 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 596 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 597 598 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 599 600 /* reg_sfn_swid 601 * Switch partition ID. 602 * Access: Index 603 */ 604 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 605 606 /* reg_sfn_end 607 * Forces the current session to end. 608 * Access: OP 609 */ 610 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 611 612 /* reg_sfn_num_rec 613 * Request: Number of learned notifications and aged-out notification 614 * records requested. 615 * Response: Number of notification records returned (must be smaller 616 * than or equal to the value requested) 617 * Ranges 0..64 618 * Access: OP 619 */ 620 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 621 622 static inline void mlxsw_reg_sfn_pack(char *payload) 623 { 624 MLXSW_REG_ZERO(sfn, payload); 625 mlxsw_reg_sfn_swid_set(payload, 0); 626 mlxsw_reg_sfn_end_set(payload, 0); 627 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 628 } 629 630 /* reg_sfn_rec_swid 631 * Switch partition ID. 632 * Access: RO 633 */ 634 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 635 MLXSW_REG_SFN_REC_LEN, 0x00, false); 636 637 enum mlxsw_reg_sfn_rec_type { 638 /* MAC addresses learned on a regular port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 640 /* MAC addresses learned on a LAG port. */ 641 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 642 /* Aged-out MAC address on a regular port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 644 /* Aged-out MAC address on a LAG port. */ 645 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 646 /* Learned unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 648 /* Aged-out unicast tunnel record. */ 649 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 650 }; 651 652 /* reg_sfn_rec_type 653 * Notification record type. 654 * Access: RO 655 */ 656 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 657 MLXSW_REG_SFN_REC_LEN, 0x00, false); 658 659 /* reg_sfn_rec_mac 660 * MAC address. 661 * Access: RO 662 */ 663 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 664 MLXSW_REG_SFN_REC_LEN, 0x02); 665 666 /* reg_sfn_mac_sub_port 667 * VEPA channel on the local port. 668 * 0 if multichannel VEPA is not enabled. 669 * Access: RO 670 */ 671 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 672 MLXSW_REG_SFN_REC_LEN, 0x08, false); 673 674 /* reg_sfn_mac_fid 675 * Filtering identifier. 676 * Access: RO 677 */ 678 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 679 MLXSW_REG_SFN_REC_LEN, 0x08, false); 680 681 /* reg_sfn_mac_system_port 682 * Unique port identifier for the final destination of the packet. 683 * Access: RO 684 */ 685 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 686 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 687 688 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 689 char *mac, u16 *p_vid, 690 u16 *p_local_port) 691 { 692 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 693 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 694 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 695 } 696 697 /* reg_sfn_mac_lag_lag_id 698 * LAG ID (pointer into the LAG descriptor table). 699 * Access: RO 700 */ 701 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 702 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 703 704 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 705 char *mac, u16 *p_vid, 706 u16 *p_lag_id) 707 { 708 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 709 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 710 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 711 } 712 713 /* reg_sfn_uc_tunnel_uip_msb 714 * When protocol is IPv4, the most significant byte of the underlay IPv4 715 * address of the remote VTEP. 716 * When protocol is IPv6, reserved. 717 * Access: RO 718 */ 719 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 720 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 721 722 enum mlxsw_reg_sfn_uc_tunnel_protocol { 723 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 724 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 725 }; 726 727 /* reg_sfn_uc_tunnel_protocol 728 * IP protocol. 729 * Access: RO 730 */ 731 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 732 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 733 734 /* reg_sfn_uc_tunnel_uip_lsb 735 * When protocol is IPv4, the least significant bytes of the underlay 736 * IPv4 address of the remote VTEP. 737 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 738 * Access: RO 739 */ 740 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 741 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 742 743 /* reg_sfn_uc_tunnel_port 744 * Tunnel port. 745 * Reserved on Spectrum. 746 * Access: RO 747 */ 748 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 749 MLXSW_REG_SFN_REC_LEN, 0x10, false); 750 751 static inline void 752 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 753 u16 *p_fid, u32 *p_uip, 754 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 755 { 756 u32 uip_msb, uip_lsb; 757 758 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 759 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 760 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 761 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 762 *p_uip = uip_msb << 24 | uip_lsb; 763 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 764 } 765 766 /* SPMS - Switch Port MSTP/RSTP State Register 767 * ------------------------------------------- 768 * Configures the spanning tree state of a physical port. 769 */ 770 #define MLXSW_REG_SPMS_ID 0x200D 771 #define MLXSW_REG_SPMS_LEN 0x404 772 773 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 774 775 /* reg_spms_local_port 776 * Local port number. 777 * Access: Index 778 */ 779 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 780 781 enum mlxsw_reg_spms_state { 782 MLXSW_REG_SPMS_STATE_NO_CHANGE, 783 MLXSW_REG_SPMS_STATE_DISCARDING, 784 MLXSW_REG_SPMS_STATE_LEARNING, 785 MLXSW_REG_SPMS_STATE_FORWARDING, 786 }; 787 788 /* reg_spms_state 789 * Spanning tree state of each VLAN ID (VID) of the local port. 790 * 0 - Do not change spanning tree state (used only when writing). 791 * 1 - Discarding. No learning or forwarding to/from this port (default). 792 * 2 - Learning. Port is learning, but not forwarding. 793 * 3 - Forwarding. Port is learning and forwarding. 794 * Access: RW 795 */ 796 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 797 798 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 799 { 800 MLXSW_REG_ZERO(spms, payload); 801 mlxsw_reg_spms_local_port_set(payload, local_port); 802 } 803 804 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 805 enum mlxsw_reg_spms_state state) 806 { 807 mlxsw_reg_spms_state_set(payload, vid, state); 808 } 809 810 /* SPVID - Switch Port VID 811 * ----------------------- 812 * The switch port VID configures the default VID for a port. 813 */ 814 #define MLXSW_REG_SPVID_ID 0x200E 815 #define MLXSW_REG_SPVID_LEN 0x08 816 817 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 818 819 /* reg_spvid_tport 820 * Port is tunnel port. 821 * Reserved when SwitchX/-2 or Spectrum-1. 822 * Access: Index 823 */ 824 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 825 826 /* reg_spvid_local_port 827 * When tport = 0: Local port number. Not supported for CPU port. 828 * When tport = 1: Tunnel port. 829 * Access: Index 830 */ 831 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 832 833 /* reg_spvid_sub_port 834 * Virtual port within the physical port. 835 * Should be set to 0 when virtual ports are not enabled on the port. 836 * Access: Index 837 */ 838 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 839 840 /* reg_spvid_egr_et_set 841 * When VLAN is pushed at ingress (for untagged packets or for 842 * QinQ push mode) then the EtherType is decided at the egress port. 843 * Reserved when Spectrum-1. 844 * Access: RW 845 */ 846 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 847 848 /* reg_spvid_et_vlan 849 * EtherType used for when VLAN is pushed at ingress (for untagged 850 * packets or for QinQ push mode). 851 * 0: ether_type0 - (default) 852 * 1: ether_type1 853 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 854 * Ethertype IDs are configured by SVER. 855 * Reserved when egr_et_set = 1. 856 * Access: RW 857 */ 858 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 859 860 /* reg_spvid_pvid 861 * Port default VID 862 * Access: RW 863 */ 864 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 865 866 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 867 u8 et_vlan) 868 { 869 MLXSW_REG_ZERO(spvid, payload); 870 mlxsw_reg_spvid_local_port_set(payload, local_port); 871 mlxsw_reg_spvid_pvid_set(payload, pvid); 872 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 873 } 874 875 /* SPVM - Switch Port VLAN Membership 876 * ---------------------------------- 877 * The Switch Port VLAN Membership register configures the VLAN membership 878 * of a port in a VLAN denoted by VID. VLAN membership is managed per 879 * virtual port. The register can be used to add and remove VID(s) from a port. 880 */ 881 #define MLXSW_REG_SPVM_ID 0x200F 882 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 883 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 884 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 885 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 886 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 887 888 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 889 890 /* reg_spvm_pt 891 * Priority tagged. If this bit is set, packets forwarded to the port with 892 * untagged VLAN membership (u bit is set) will be tagged with priority tag 893 * (VID=0) 894 * Access: RW 895 */ 896 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 897 898 /* reg_spvm_pte 899 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 900 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 901 * Access: WO 902 */ 903 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 904 905 /* reg_spvm_local_port 906 * Local port number. 907 * Access: Index 908 */ 909 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 910 911 /* reg_spvm_sub_port 912 * Virtual port within the physical port. 913 * Should be set to 0 when virtual ports are not enabled on the port. 914 * Access: Index 915 */ 916 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 917 918 /* reg_spvm_num_rec 919 * Number of records to update. Each record contains: i, e, u, vid. 920 * Access: OP 921 */ 922 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 923 924 /* reg_spvm_rec_i 925 * Ingress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 929 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 /* reg_spvm_rec_e 933 * Egress membership in VLAN ID. 934 * Access: Index 935 */ 936 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 937 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 938 MLXSW_REG_SPVM_REC_LEN, 0, false); 939 940 /* reg_spvm_rec_u 941 * Untagged - port is an untagged member - egress transmission uses untagged 942 * frames on VID<n> 943 * Access: Index 944 */ 945 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 946 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 947 MLXSW_REG_SPVM_REC_LEN, 0, false); 948 949 /* reg_spvm_rec_vid 950 * Egress membership in VLAN ID. 951 * Access: Index 952 */ 953 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 954 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 955 MLXSW_REG_SPVM_REC_LEN, 0, false); 956 957 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 958 u16 vid_begin, u16 vid_end, 959 bool is_member, bool untagged) 960 { 961 int size = vid_end - vid_begin + 1; 962 int i; 963 964 MLXSW_REG_ZERO(spvm, payload); 965 mlxsw_reg_spvm_local_port_set(payload, local_port); 966 mlxsw_reg_spvm_num_rec_set(payload, size); 967 968 for (i = 0; i < size; i++) { 969 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 970 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 971 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 972 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 973 } 974 } 975 976 /* SPAFT - Switch Port Acceptable Frame Types 977 * ------------------------------------------ 978 * The Switch Port Acceptable Frame Types register configures the frame 979 * admittance of the port. 980 */ 981 #define MLXSW_REG_SPAFT_ID 0x2010 982 #define MLXSW_REG_SPAFT_LEN 0x08 983 984 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 985 986 /* reg_spaft_local_port 987 * Local port number. 988 * Access: Index 989 * 990 * Note: CPU port is not supported (all tag types are allowed). 991 */ 992 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 993 994 /* reg_spaft_sub_port 995 * Virtual port within the physical port. 996 * Should be set to 0 when virtual ports are not enabled on the port. 997 * Access: RW 998 */ 999 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1000 1001 /* reg_spaft_allow_untagged 1002 * When set, untagged frames on the ingress are allowed (default). 1003 * Access: RW 1004 */ 1005 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1006 1007 /* reg_spaft_allow_prio_tagged 1008 * When set, priority tagged frames on the ingress are allowed (default). 1009 * Access: RW 1010 */ 1011 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1012 1013 /* reg_spaft_allow_tagged 1014 * When set, tagged frames on the ingress are allowed (default). 1015 * Access: RW 1016 */ 1017 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1018 1019 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1020 bool allow_untagged) 1021 { 1022 MLXSW_REG_ZERO(spaft, payload); 1023 mlxsw_reg_spaft_local_port_set(payload, local_port); 1024 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1025 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1026 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1027 } 1028 1029 /* SFGC - Switch Flooding Group Configuration 1030 * ------------------------------------------ 1031 * The following register controls the association of flooding tables and MIDs 1032 * to packet types used for flooding. 1033 */ 1034 #define MLXSW_REG_SFGC_ID 0x2011 1035 #define MLXSW_REG_SFGC_LEN 0x14 1036 1037 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1038 1039 enum mlxsw_reg_sfgc_type { 1040 MLXSW_REG_SFGC_TYPE_BROADCAST, 1041 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1042 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1043 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1044 MLXSW_REG_SFGC_TYPE_RESERVED, 1045 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1046 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1047 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1048 MLXSW_REG_SFGC_TYPE_MAX, 1049 }; 1050 1051 /* reg_sfgc_type 1052 * The traffic type to reach the flooding table. 1053 * Access: Index 1054 */ 1055 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1056 1057 /* bridge_type is used in SFGC and SFMR. */ 1058 enum mlxsw_reg_bridge_type { 1059 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1060 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1061 }; 1062 1063 /* reg_sfgc_bridge_type 1064 * Access: Index 1065 * 1066 * Note: SwitchX-2 only supports 802.1Q mode. 1067 */ 1068 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1069 1070 enum mlxsw_flood_table_type { 1071 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1072 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1073 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1074 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1075 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1076 }; 1077 1078 /* reg_sfgc_table_type 1079 * See mlxsw_flood_table_type 1080 * Access: RW 1081 * 1082 * Note: FID offset and FID types are not supported in SwitchX-2. 1083 */ 1084 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1085 1086 /* reg_sfgc_flood_table 1087 * Flooding table index to associate with the specific type on the specific 1088 * switch partition. 1089 * Access: RW 1090 */ 1091 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1092 1093 /* reg_sfgc_counter_set_type 1094 * Counter Set Type for flow counters. 1095 * Access: RW 1096 */ 1097 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1098 1099 /* reg_sfgc_counter_index 1100 * Counter Index for flow counters. 1101 * Access: RW 1102 */ 1103 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1104 1105 /* reg_sfgc_mid_base 1106 * MID Base. 1107 * Access: RW 1108 * 1109 * Note: Reserved when legacy bridge model is used. 1110 */ 1111 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1112 1113 static inline void 1114 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1115 enum mlxsw_reg_bridge_type bridge_type, 1116 enum mlxsw_flood_table_type table_type, 1117 unsigned int flood_table, u16 mid_base) 1118 { 1119 MLXSW_REG_ZERO(sfgc, payload); 1120 mlxsw_reg_sfgc_type_set(payload, type); 1121 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1122 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1123 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1124 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1125 } 1126 1127 /* SFDF - Switch Filtering DB Flush 1128 * -------------------------------- 1129 * The switch filtering DB flush register is used to flush the FDB. 1130 * Note that FDB notifications are flushed as well. 1131 */ 1132 #define MLXSW_REG_SFDF_ID 0x2013 1133 #define MLXSW_REG_SFDF_LEN 0x14 1134 1135 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1136 1137 /* reg_sfdf_swid 1138 * Switch partition ID. 1139 * Access: Index 1140 */ 1141 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1142 1143 enum mlxsw_reg_sfdf_flush_type { 1144 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1145 MLXSW_REG_SFDF_FLUSH_PER_FID, 1146 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1147 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1148 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1149 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1150 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1151 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1152 }; 1153 1154 /* reg_sfdf_flush_type 1155 * Flush type. 1156 * 0 - All SWID dynamic entries are flushed. 1157 * 1 - All FID dynamic entries are flushed. 1158 * 2 - All dynamic entries pointing to port are flushed. 1159 * 3 - All FID dynamic entries pointing to port are flushed. 1160 * 4 - All dynamic entries pointing to LAG are flushed. 1161 * 5 - All FID dynamic entries pointing to LAG are flushed. 1162 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1163 * flushed. 1164 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1165 * flushed, per FID. 1166 * Access: RW 1167 */ 1168 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1169 1170 /* reg_sfdf_flush_static 1171 * Static. 1172 * 0 - Flush only dynamic entries. 1173 * 1 - Flush both dynamic and static entries. 1174 * Access: RW 1175 */ 1176 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1177 1178 static inline void mlxsw_reg_sfdf_pack(char *payload, 1179 enum mlxsw_reg_sfdf_flush_type type) 1180 { 1181 MLXSW_REG_ZERO(sfdf, payload); 1182 mlxsw_reg_sfdf_flush_type_set(payload, type); 1183 mlxsw_reg_sfdf_flush_static_set(payload, true); 1184 } 1185 1186 /* reg_sfdf_fid 1187 * FID to flush. 1188 * Access: RW 1189 */ 1190 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1191 1192 /* reg_sfdf_system_port 1193 * Port to flush. 1194 * Access: RW 1195 */ 1196 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1197 1198 /* reg_sfdf_port_fid_system_port 1199 * Port to flush, pointed to by FID. 1200 * Access: RW 1201 */ 1202 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1203 1204 /* reg_sfdf_lag_id 1205 * LAG ID to flush. 1206 * Access: RW 1207 */ 1208 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1209 1210 /* reg_sfdf_lag_fid_lag_id 1211 * LAG ID to flush, pointed to by FID. 1212 * Access: RW 1213 */ 1214 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1215 1216 /* SLDR - Switch LAG Descriptor Register 1217 * ----------------------------------------- 1218 * The switch LAG descriptor register is populated by LAG descriptors. 1219 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1220 * max_lag-1. 1221 */ 1222 #define MLXSW_REG_SLDR_ID 0x2014 1223 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1224 1225 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1226 1227 enum mlxsw_reg_sldr_op { 1228 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1229 MLXSW_REG_SLDR_OP_LAG_CREATE, 1230 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1231 /* Ports that appear in the list have the Distributor enabled */ 1232 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1233 /* Removes ports from the disributor list */ 1234 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1235 }; 1236 1237 /* reg_sldr_op 1238 * Operation. 1239 * Access: RW 1240 */ 1241 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1242 1243 /* reg_sldr_lag_id 1244 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1245 * Access: Index 1246 */ 1247 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1248 1249 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1250 { 1251 MLXSW_REG_ZERO(sldr, payload); 1252 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1253 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1254 } 1255 1256 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1257 { 1258 MLXSW_REG_ZERO(sldr, payload); 1259 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1260 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1261 } 1262 1263 /* reg_sldr_num_ports 1264 * The number of member ports of the LAG. 1265 * Reserved for Create / Destroy operations 1266 * For Add / Remove operations - indicates the number of ports in the list. 1267 * Access: RW 1268 */ 1269 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1270 1271 /* reg_sldr_system_port 1272 * System port. 1273 * Access: RW 1274 */ 1275 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1276 1277 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1278 u16 local_port) 1279 { 1280 MLXSW_REG_ZERO(sldr, payload); 1281 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1282 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1283 mlxsw_reg_sldr_num_ports_set(payload, 1); 1284 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1285 } 1286 1287 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1288 u16 local_port) 1289 { 1290 MLXSW_REG_ZERO(sldr, payload); 1291 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1292 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1293 mlxsw_reg_sldr_num_ports_set(payload, 1); 1294 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1295 } 1296 1297 /* SLCR - Switch LAG Configuration 2 Register 1298 * ------------------------------------------- 1299 * The Switch LAG Configuration register is used for configuring the 1300 * LAG properties of the switch. 1301 */ 1302 #define MLXSW_REG_SLCR_ID 0x2015 1303 #define MLXSW_REG_SLCR_LEN 0x10 1304 1305 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1306 1307 enum mlxsw_reg_slcr_pp { 1308 /* Global Configuration (for all ports) */ 1309 MLXSW_REG_SLCR_PP_GLOBAL, 1310 /* Per port configuration, based on local_port field */ 1311 MLXSW_REG_SLCR_PP_PER_PORT, 1312 }; 1313 1314 /* reg_slcr_pp 1315 * Per Port Configuration 1316 * Note: Reading at Global mode results in reading port 1 configuration. 1317 * Access: Index 1318 */ 1319 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1320 1321 /* reg_slcr_local_port 1322 * Local port number 1323 * Supported from CPU port 1324 * Not supported from router port 1325 * Reserved when pp = Global Configuration 1326 * Access: Index 1327 */ 1328 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1329 1330 enum mlxsw_reg_slcr_type { 1331 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1332 MLXSW_REG_SLCR_TYPE_XOR, 1333 MLXSW_REG_SLCR_TYPE_RANDOM, 1334 }; 1335 1336 /* reg_slcr_type 1337 * Hash type 1338 * Access: RW 1339 */ 1340 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1341 1342 /* Ingress port */ 1343 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1344 /* SMAC - for IPv4 and IPv6 packets */ 1345 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1346 /* SMAC - for non-IP packets */ 1347 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1348 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1349 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1350 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1351 /* DMAC - for IPv4 and IPv6 packets */ 1352 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1353 /* DMAC - for non-IP packets */ 1354 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1355 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1356 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1357 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1358 /* Ethertype - for IPv4 and IPv6 packets */ 1359 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1360 /* Ethertype - for non-IP packets */ 1361 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1362 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1363 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1364 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1365 /* VLAN ID - for IPv4 and IPv6 packets */ 1366 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1367 /* VLAN ID - for non-IP packets */ 1368 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1369 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1370 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1371 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1372 /* Source IP address (can be IPv4 or IPv6) */ 1373 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1374 /* Destination IP address (can be IPv4 or IPv6) */ 1375 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1376 /* TCP/UDP source port */ 1377 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1378 /* TCP/UDP destination port*/ 1379 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1380 /* IPv4 Protocol/IPv6 Next Header */ 1381 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1382 /* IPv6 Flow label */ 1383 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1384 /* SID - FCoE source ID */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1386 /* DID - FCoE destination ID */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1388 /* OXID - FCoE originator exchange ID */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1390 /* Destination QP number - for RoCE packets */ 1391 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1392 1393 /* reg_slcr_lag_hash 1394 * LAG hashing configuration. This is a bitmask, in which each set 1395 * bit includes the corresponding item in the LAG hash calculation. 1396 * The default lag_hash contains SMAC, DMAC, VLANID and 1397 * Ethertype (for all packet types). 1398 * Access: RW 1399 */ 1400 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1401 1402 /* reg_slcr_seed 1403 * LAG seed value. The seed is the same for all ports. 1404 * Access: RW 1405 */ 1406 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1407 1408 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1409 { 1410 MLXSW_REG_ZERO(slcr, payload); 1411 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1412 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1413 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1414 mlxsw_reg_slcr_seed_set(payload, seed); 1415 } 1416 1417 /* SLCOR - Switch LAG Collector Register 1418 * ------------------------------------- 1419 * The Switch LAG Collector register controls the Local Port membership 1420 * in a LAG and enablement of the collector. 1421 */ 1422 #define MLXSW_REG_SLCOR_ID 0x2016 1423 #define MLXSW_REG_SLCOR_LEN 0x10 1424 1425 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1426 1427 enum mlxsw_reg_slcor_col { 1428 /* Port is added with collector disabled */ 1429 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1430 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1431 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1432 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1433 }; 1434 1435 /* reg_slcor_col 1436 * Collector configuration 1437 * Access: RW 1438 */ 1439 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1440 1441 /* reg_slcor_local_port 1442 * Local port number 1443 * Not supported for CPU port 1444 * Access: Index 1445 */ 1446 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1447 1448 /* reg_slcor_lag_id 1449 * LAG Identifier. Index into the LAG descriptor table. 1450 * Access: Index 1451 */ 1452 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1453 1454 /* reg_slcor_port_index 1455 * Port index in the LAG list. Only valid on Add Port to LAG col. 1456 * Valid range is from 0 to cap_max_lag_members-1 1457 * Access: RW 1458 */ 1459 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1460 1461 static inline void mlxsw_reg_slcor_pack(char *payload, 1462 u16 local_port, u16 lag_id, 1463 enum mlxsw_reg_slcor_col col) 1464 { 1465 MLXSW_REG_ZERO(slcor, payload); 1466 mlxsw_reg_slcor_col_set(payload, col); 1467 mlxsw_reg_slcor_local_port_set(payload, local_port); 1468 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1469 } 1470 1471 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1472 u16 local_port, u16 lag_id, 1473 u8 port_index) 1474 { 1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1476 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1477 mlxsw_reg_slcor_port_index_set(payload, port_index); 1478 } 1479 1480 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1481 u16 local_port, u16 lag_id) 1482 { 1483 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1484 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1485 } 1486 1487 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1488 u16 local_port, u16 lag_id) 1489 { 1490 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1491 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1492 } 1493 1494 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1495 u16 local_port, u16 lag_id) 1496 { 1497 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1498 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1499 } 1500 1501 /* SPMLR - Switch Port MAC Learning Register 1502 * ----------------------------------------- 1503 * Controls the Switch MAC learning policy per port. 1504 */ 1505 #define MLXSW_REG_SPMLR_ID 0x2018 1506 #define MLXSW_REG_SPMLR_LEN 0x8 1507 1508 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1509 1510 /* reg_spmlr_local_port 1511 * Local port number. 1512 * Access: Index 1513 */ 1514 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1515 1516 /* reg_spmlr_sub_port 1517 * Virtual port within the physical port. 1518 * Should be set to 0 when virtual ports are not enabled on the port. 1519 * Access: Index 1520 */ 1521 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1522 1523 enum mlxsw_reg_spmlr_learn_mode { 1524 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1525 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1526 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1527 }; 1528 1529 /* reg_spmlr_learn_mode 1530 * Learning mode on the port. 1531 * 0 - Learning disabled. 1532 * 2 - Learning enabled. 1533 * 3 - Security mode. 1534 * 1535 * In security mode the switch does not learn MACs on the port, but uses the 1536 * SMAC to see if it exists on another ingress port. If so, the packet is 1537 * classified as a bad packet and is discarded unless the software registers 1538 * to receive port security error packets usign HPKT. 1539 */ 1540 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1541 1542 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1543 enum mlxsw_reg_spmlr_learn_mode mode) 1544 { 1545 MLXSW_REG_ZERO(spmlr, payload); 1546 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1547 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1548 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1549 } 1550 1551 /* SVFA - Switch VID to FID Allocation Register 1552 * -------------------------------------------- 1553 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1554 * virtualized ports. 1555 */ 1556 #define MLXSW_REG_SVFA_ID 0x201C 1557 #define MLXSW_REG_SVFA_LEN 0x18 1558 1559 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1560 1561 /* reg_svfa_swid 1562 * Switch partition ID. 1563 * Access: Index 1564 */ 1565 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1566 1567 /* reg_svfa_local_port 1568 * Local port number. 1569 * Access: Index 1570 * 1571 * Note: Reserved for 802.1Q FIDs. 1572 */ 1573 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1574 1575 enum mlxsw_reg_svfa_mt { 1576 MLXSW_REG_SVFA_MT_VID_TO_FID, 1577 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1578 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1579 }; 1580 1581 /* reg_svfa_mapping_table 1582 * Mapping table: 1583 * 0 - VID to FID 1584 * 1 - {Port, VID} to FID 1585 * Access: Index 1586 * 1587 * Note: Reserved for SwitchX-2. 1588 */ 1589 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1590 1591 /* reg_svfa_v 1592 * Valid. 1593 * Valid if set. 1594 * Access: RW 1595 * 1596 * Note: Reserved for SwitchX-2. 1597 */ 1598 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1599 1600 /* reg_svfa_fid 1601 * Filtering ID. 1602 * Access: RW 1603 */ 1604 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1605 1606 /* reg_svfa_vid 1607 * VLAN ID. 1608 * Access: Index 1609 */ 1610 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1611 1612 /* reg_svfa_counter_set_type 1613 * Counter set type for flow counters. 1614 * Access: RW 1615 * 1616 * Note: Reserved for SwitchX-2. 1617 */ 1618 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1619 1620 /* reg_svfa_counter_index 1621 * Counter index for flow counters. 1622 * Access: RW 1623 * 1624 * Note: Reserved for SwitchX-2. 1625 */ 1626 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1627 1628 /* reg_svfa_vni 1629 * Virtual Network Identifier. 1630 * Access: Index 1631 * 1632 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1633 */ 1634 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1635 1636 /* reg_svfa_irif_v 1637 * Ingress RIF valid. 1638 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1639 * 1 - Ingress RIF valid. 1640 * Must not be set for a non enabled RIF. 1641 * Access: RW 1642 * 1643 * Note: Reserved when legacy bridge model is used. 1644 */ 1645 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1646 1647 /* reg_svfa_irif 1648 * Ingress RIF (Router Interface). 1649 * Range is 0..cap_max_router_interfaces-1. 1650 * Access: RW 1651 * 1652 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1653 */ 1654 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1655 1656 static inline void __mlxsw_reg_svfa_pack(char *payload, 1657 enum mlxsw_reg_svfa_mt mt, bool valid, 1658 u16 fid) 1659 { 1660 MLXSW_REG_ZERO(svfa, payload); 1661 mlxsw_reg_svfa_swid_set(payload, 0); 1662 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1663 mlxsw_reg_svfa_v_set(payload, valid); 1664 mlxsw_reg_svfa_fid_set(payload, fid); 1665 } 1666 1667 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1668 bool valid, u16 fid, u16 vid) 1669 { 1670 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1671 1672 __mlxsw_reg_svfa_pack(payload, mt, valid, fid); 1673 mlxsw_reg_svfa_local_port_set(payload, local_port); 1674 mlxsw_reg_svfa_vid_set(payload, vid); 1675 } 1676 1677 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1678 u16 vid) 1679 { 1680 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1681 1682 __mlxsw_reg_svfa_pack(payload, mt, valid, fid); 1683 mlxsw_reg_svfa_vid_set(payload, vid); 1684 } 1685 1686 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1687 u32 vni) 1688 { 1689 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1690 1691 __mlxsw_reg_svfa_pack(payload, mt, valid, fid); 1692 mlxsw_reg_svfa_vni_set(payload, vni); 1693 } 1694 1695 /* SPVTR - Switch Port VLAN Stacking Register 1696 * ------------------------------------------ 1697 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1698 * to enable VLAN stacking. 1699 */ 1700 #define MLXSW_REG_SPVTR_ID 0x201D 1701 #define MLXSW_REG_SPVTR_LEN 0x10 1702 1703 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1704 1705 /* reg_spvtr_tport 1706 * Port is tunnel port. 1707 * Access: Index 1708 * 1709 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1710 */ 1711 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1712 1713 /* reg_spvtr_local_port 1714 * When tport = 0: local port number (Not supported from/to CPU). 1715 * When tport = 1: tunnel port. 1716 * Access: Index 1717 */ 1718 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1719 1720 /* reg_spvtr_ippe 1721 * Ingress Port Prio Mode Update Enable. 1722 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1723 * Reserved on Get operations. 1724 * Access: OP 1725 */ 1726 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1727 1728 /* reg_spvtr_ipve 1729 * Ingress Port VID Mode Update Enable. 1730 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1731 * field. 1732 * Reserved on Get operations. 1733 * Access: OP 1734 */ 1735 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1736 1737 /* reg_spvtr_epve 1738 * Egress Port VID Mode Update Enable. 1739 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1740 * field. 1741 * Access: OP 1742 */ 1743 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1744 1745 /* reg_spvtr_ipprio_mode 1746 * Ingress Port Priority Mode. 1747 * This controls the PCP and DEI of the new outer VLAN 1748 * Note: for SwitchX/-2 the DEI is not affected. 1749 * 0: use port default PCP and DEI (configured by QPDPC). 1750 * 1: use C-VLAN PCP and DEI. 1751 * Has no effect when ipvid_mode = 0. 1752 * Reserved when tport = 1. 1753 * Access: RW 1754 */ 1755 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1756 1757 enum mlxsw_reg_spvtr_ipvid_mode { 1758 /* IEEE Compliant PVID (default) */ 1759 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1760 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1761 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1762 /* Always push VLAN (also for prio tagged packets) */ 1763 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1764 }; 1765 1766 /* reg_spvtr_ipvid_mode 1767 * Ingress Port VLAN-ID Mode. 1768 * For Spectrum family, this affects the values of SPVM.i 1769 * Access: RW 1770 */ 1771 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1772 1773 enum mlxsw_reg_spvtr_epvid_mode { 1774 /* IEEE Compliant VLAN membership */ 1775 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1776 /* Pop VLAN (for VLAN stacking) */ 1777 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1778 }; 1779 1780 /* reg_spvtr_epvid_mode 1781 * Egress Port VLAN-ID Mode. 1782 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1783 * Access: WO 1784 */ 1785 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1786 1787 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1788 u16 local_port, 1789 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1790 { 1791 MLXSW_REG_ZERO(spvtr, payload); 1792 mlxsw_reg_spvtr_tport_set(payload, tport); 1793 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1794 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1795 mlxsw_reg_spvtr_ipve_set(payload, true); 1796 } 1797 1798 /* SVPE - Switch Virtual-Port Enabling Register 1799 * -------------------------------------------- 1800 * Enables port virtualization. 1801 */ 1802 #define MLXSW_REG_SVPE_ID 0x201E 1803 #define MLXSW_REG_SVPE_LEN 0x4 1804 1805 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1806 1807 /* reg_svpe_local_port 1808 * Local port number 1809 * Access: Index 1810 * 1811 * Note: CPU port is not supported (uses VLAN mode only). 1812 */ 1813 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1814 1815 /* reg_svpe_vp_en 1816 * Virtual port enable. 1817 * 0 - Disable, VLAN mode (VID to FID). 1818 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1819 * Access: RW 1820 */ 1821 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1822 1823 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1824 bool enable) 1825 { 1826 MLXSW_REG_ZERO(svpe, payload); 1827 mlxsw_reg_svpe_local_port_set(payload, local_port); 1828 mlxsw_reg_svpe_vp_en_set(payload, enable); 1829 } 1830 1831 /* SFMR - Switch FID Management Register 1832 * ------------------------------------- 1833 * Creates and configures FIDs. 1834 */ 1835 #define MLXSW_REG_SFMR_ID 0x201F 1836 #define MLXSW_REG_SFMR_LEN 0x30 1837 1838 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1839 1840 enum mlxsw_reg_sfmr_op { 1841 MLXSW_REG_SFMR_OP_CREATE_FID, 1842 MLXSW_REG_SFMR_OP_DESTROY_FID, 1843 }; 1844 1845 /* reg_sfmr_op 1846 * Operation. 1847 * 0 - Create or edit FID. 1848 * 1 - Destroy FID. 1849 * Access: WO 1850 */ 1851 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1852 1853 /* reg_sfmr_fid 1854 * Filtering ID. 1855 * Access: Index 1856 */ 1857 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1858 1859 /* reg_sfmr_flood_rsp 1860 * Router sub-port flooding table. 1861 * 0 - Regular flooding table. 1862 * 1 - Router sub-port flooding table. For this FID the flooding is per 1863 * router-sub-port local_port. Must not be set for a FID which is not a 1864 * router-sub-port and must be set prior to enabling the relevant RIF. 1865 * Access: RW 1866 * 1867 * Note: Reserved when legacy bridge model is used. 1868 */ 1869 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1870 1871 /* reg_sfmr_flood_bridge_type 1872 * Flood bridge type (see SFGC.bridge_type). 1873 * 0 - type_0. 1874 * 1 - type_1. 1875 * Access: RW 1876 * 1877 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1878 */ 1879 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1880 1881 /* reg_sfmr_fid_offset 1882 * FID offset. 1883 * Used to point into the flooding table selected by SFGC register if 1884 * the table is of type FID-Offset. Otherwise, this field is reserved. 1885 * Access: RW 1886 */ 1887 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1888 1889 /* reg_sfmr_vtfp 1890 * Valid Tunnel Flood Pointer. 1891 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1892 * Access: RW 1893 * 1894 * Note: Reserved for 802.1Q FIDs. 1895 */ 1896 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1897 1898 /* reg_sfmr_nve_tunnel_flood_ptr 1899 * Underlay Flooding and BC Pointer. 1900 * Used as a pointer to the first entry of the group based link lists of 1901 * flooding or BC entries (for NVE tunnels). 1902 * Access: RW 1903 */ 1904 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1905 1906 /* reg_sfmr_vv 1907 * VNI Valid. 1908 * If not set, then vni is reserved. 1909 * Access: RW 1910 * 1911 * Note: Reserved for 802.1Q FIDs. 1912 */ 1913 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1914 1915 /* reg_sfmr_vni 1916 * Virtual Network Identifier. 1917 * When legacy bridge model is used, a given VNI can only be assigned to one 1918 * FID. When unified bridge model is used, it configures only the FID->VNI, 1919 * the VNI->FID is done by SVFA. 1920 * Access: RW 1921 */ 1922 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1923 1924 /* reg_sfmr_irif_v 1925 * Ingress RIF valid. 1926 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1927 * 1 - Ingress RIF valid. 1928 * Must not be set for a non valid RIF. 1929 * Access: RW 1930 * 1931 * Note: Reserved when legacy bridge model is used. 1932 */ 1933 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1934 1935 /* reg_sfmr_irif 1936 * Ingress RIF (Router Interface). 1937 * Range is 0..cap_max_router_interfaces-1. 1938 * Access: RW 1939 * 1940 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1941 */ 1942 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1943 1944 /* reg_sfmr_smpe_valid 1945 * SMPE is valid. 1946 * Access: RW 1947 * 1948 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1949 * Spectrum-1. 1950 */ 1951 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1952 1953 /* reg_sfmr_smpe 1954 * Switch multicast port to egress VID. 1955 * Range is 0..cap_max_rmpe-1 1956 * Access: RW 1957 * 1958 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1959 * Spectrum-1. 1960 */ 1961 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1962 1963 static inline void mlxsw_reg_sfmr_pack(char *payload, 1964 enum mlxsw_reg_sfmr_op op, u16 fid, 1965 u16 fid_offset, bool flood_rsp, 1966 enum mlxsw_reg_bridge_type bridge_type) 1967 { 1968 MLXSW_REG_ZERO(sfmr, payload); 1969 mlxsw_reg_sfmr_op_set(payload, op); 1970 mlxsw_reg_sfmr_fid_set(payload, fid); 1971 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1972 mlxsw_reg_sfmr_vtfp_set(payload, false); 1973 mlxsw_reg_sfmr_vv_set(payload, false); 1974 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1975 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1976 } 1977 1978 /* SPVMLR - Switch Port VLAN MAC Learning Register 1979 * ----------------------------------------------- 1980 * Controls the switch MAC learning policy per {Port, VID}. 1981 */ 1982 #define MLXSW_REG_SPVMLR_ID 0x2020 1983 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1984 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1985 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1986 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1987 MLXSW_REG_SPVMLR_REC_LEN * \ 1988 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1989 1990 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1991 1992 /* reg_spvmlr_local_port 1993 * Local ingress port. 1994 * Access: Index 1995 * 1996 * Note: CPU port is not supported. 1997 */ 1998 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 1999 2000 /* reg_spvmlr_num_rec 2001 * Number of records to update. 2002 * Access: OP 2003 */ 2004 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2005 2006 /* reg_spvmlr_rec_learn_enable 2007 * 0 - Disable learning for {Port, VID}. 2008 * 1 - Enable learning for {Port, VID}. 2009 * Access: RW 2010 */ 2011 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2012 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2013 2014 /* reg_spvmlr_rec_vid 2015 * VLAN ID to be added/removed from port or for querying. 2016 * Access: Index 2017 */ 2018 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2019 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2020 2021 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2022 u16 vid_begin, u16 vid_end, 2023 bool learn_enable) 2024 { 2025 int num_rec = vid_end - vid_begin + 1; 2026 int i; 2027 2028 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2029 2030 MLXSW_REG_ZERO(spvmlr, payload); 2031 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2032 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2033 2034 for (i = 0; i < num_rec; i++) { 2035 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2036 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2037 } 2038 } 2039 2040 /* SPVC - Switch Port VLAN Classification Register 2041 * ----------------------------------------------- 2042 * Configures the port to identify packets as untagged / single tagged / 2043 * double packets based on the packet EtherTypes. 2044 * Ethertype IDs are configured by SVER. 2045 */ 2046 #define MLXSW_REG_SPVC_ID 0x2026 2047 #define MLXSW_REG_SPVC_LEN 0x0C 2048 2049 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2050 2051 /* reg_spvc_local_port 2052 * Local port. 2053 * Access: Index 2054 * 2055 * Note: applies both to Rx port and Tx port, so if a packet traverses 2056 * through Rx port i and a Tx port j then port i and port j must have the 2057 * same configuration. 2058 */ 2059 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2060 2061 /* reg_spvc_inner_et2 2062 * Vlan Tag1 EtherType2 enable. 2063 * Packet is initially classified as double VLAN Tag if in addition to 2064 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2065 * equal to ether_type2. 2066 * 0: disable (default) 2067 * 1: enable 2068 * Access: RW 2069 */ 2070 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2071 2072 /* reg_spvc_et2 2073 * Vlan Tag0 EtherType2 enable. 2074 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2075 * equal to ether_type2. 2076 * 0: disable (default) 2077 * 1: enable 2078 * Access: RW 2079 */ 2080 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2081 2082 /* reg_spvc_inner_et1 2083 * Vlan Tag1 EtherType1 enable. 2084 * Packet is initially classified as double VLAN Tag if in addition to 2085 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2086 * equal to ether_type1. 2087 * 0: disable 2088 * 1: enable (default) 2089 * Access: RW 2090 */ 2091 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2092 2093 /* reg_spvc_et1 2094 * Vlan Tag0 EtherType1 enable. 2095 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2096 * equal to ether_type1. 2097 * 0: disable 2098 * 1: enable (default) 2099 * Access: RW 2100 */ 2101 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2102 2103 /* reg_inner_et0 2104 * Vlan Tag1 EtherType0 enable. 2105 * Packet is initially classified as double VLAN Tag if in addition to 2106 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2107 * equal to ether_type0. 2108 * 0: disable 2109 * 1: enable (default) 2110 * Access: RW 2111 */ 2112 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2113 2114 /* reg_et0 2115 * Vlan Tag0 EtherType0 enable. 2116 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2117 * equal to ether_type0. 2118 * 0: disable 2119 * 1: enable (default) 2120 * Access: RW 2121 */ 2122 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2123 2124 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2125 bool et0) 2126 { 2127 MLXSW_REG_ZERO(spvc, payload); 2128 mlxsw_reg_spvc_local_port_set(payload, local_port); 2129 /* Enable inner_et1 and inner_et0 to enable identification of double 2130 * tagged packets. 2131 */ 2132 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2133 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2134 mlxsw_reg_spvc_et1_set(payload, et1); 2135 mlxsw_reg_spvc_et0_set(payload, et0); 2136 } 2137 2138 /* SPEVET - Switch Port Egress VLAN EtherType 2139 * ------------------------------------------ 2140 * The switch port egress VLAN EtherType configures which EtherType to push at 2141 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2142 * is set. 2143 */ 2144 #define MLXSW_REG_SPEVET_ID 0x202A 2145 #define MLXSW_REG_SPEVET_LEN 0x08 2146 2147 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2148 2149 /* reg_spevet_local_port 2150 * Egress Local port number. 2151 * Not supported to CPU port. 2152 * Access: Index 2153 */ 2154 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2155 2156 /* reg_spevet_et_vlan 2157 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2158 * 0: ether_type0 - (default) 2159 * 1: ether_type1 2160 * 2: ether_type2 2161 * Access: RW 2162 */ 2163 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2164 2165 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2166 u8 et_vlan) 2167 { 2168 MLXSW_REG_ZERO(spevet, payload); 2169 mlxsw_reg_spevet_local_port_set(payload, local_port); 2170 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2171 } 2172 2173 /* SMPE - Switch Multicast Port to Egress VID 2174 * ------------------------------------------ 2175 * The switch multicast port to egress VID maps 2176 * {egress_port, SMPE index} -> {VID}. 2177 */ 2178 #define MLXSW_REG_SMPE_ID 0x202B 2179 #define MLXSW_REG_SMPE_LEN 0x0C 2180 2181 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2182 2183 /* reg_smpe_local_port 2184 * Local port number. 2185 * CPU port is not supported. 2186 * Access: Index 2187 */ 2188 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2189 2190 /* reg_smpe_smpe_index 2191 * Switch multicast port to egress VID. 2192 * Range is 0..cap_max_rmpe-1. 2193 * Access: Index 2194 */ 2195 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2196 2197 /* reg_smpe_evid 2198 * Egress VID. 2199 * Access: RW 2200 */ 2201 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2202 2203 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2204 u16 smpe_index, u16 evid) 2205 { 2206 MLXSW_REG_ZERO(smpe, payload); 2207 mlxsw_reg_smpe_local_port_set(payload, local_port); 2208 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2209 mlxsw_reg_smpe_evid_set(payload, evid); 2210 } 2211 2212 /* SFTR-V2 - Switch Flooding Table Version 2 Register 2213 * -------------------------------------------------- 2214 * The switch flooding table is used for flooding packet replication. The table 2215 * defines a bit mask of ports for packet replication. 2216 */ 2217 #define MLXSW_REG_SFTR2_ID 0x202F 2218 #define MLXSW_REG_SFTR2_LEN 0x120 2219 2220 MLXSW_REG_DEFINE(sftr2, MLXSW_REG_SFTR2_ID, MLXSW_REG_SFTR2_LEN); 2221 2222 /* reg_sftr2_swid 2223 * Switch partition ID with which to associate the port. 2224 * Access: Index 2225 */ 2226 MLXSW_ITEM32(reg, sftr2, swid, 0x00, 24, 8); 2227 2228 /* reg_sftr2_flood_table 2229 * Flooding table index to associate with the specific type on the specific 2230 * switch partition. 2231 * Access: Index 2232 */ 2233 MLXSW_ITEM32(reg, sftr2, flood_table, 0x00, 16, 6); 2234 2235 /* reg_sftr2_index 2236 * Index. Used as an index into the Flooding Table in case the table is 2237 * configured to use VID / FID or FID Offset. 2238 * Access: Index 2239 */ 2240 MLXSW_ITEM32(reg, sftr2, index, 0x00, 0, 16); 2241 2242 /* reg_sftr2_table_type 2243 * See mlxsw_flood_table_type 2244 * Access: RW 2245 */ 2246 MLXSW_ITEM32(reg, sftr2, table_type, 0x04, 16, 3); 2247 2248 /* reg_sftr2_range 2249 * Range of entries to update 2250 * Access: Index 2251 */ 2252 MLXSW_ITEM32(reg, sftr2, range, 0x04, 0, 16); 2253 2254 /* reg_sftr2_port 2255 * Local port membership (1 bit per port). 2256 * Access: RW 2257 */ 2258 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port, 0x20, 0x80, 1); 2259 2260 /* reg_sftr2_port_mask 2261 * Local port mask (1 bit per port). 2262 * Access: WO 2263 */ 2264 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port_mask, 0xA0, 0x80, 1); 2265 2266 static inline void mlxsw_reg_sftr2_pack(char *payload, 2267 unsigned int flood_table, 2268 unsigned int index, 2269 enum mlxsw_flood_table_type table_type, 2270 unsigned int range, u16 port, bool set) 2271 { 2272 MLXSW_REG_ZERO(sftr2, payload); 2273 mlxsw_reg_sftr2_swid_set(payload, 0); 2274 mlxsw_reg_sftr2_flood_table_set(payload, flood_table); 2275 mlxsw_reg_sftr2_index_set(payload, index); 2276 mlxsw_reg_sftr2_table_type_set(payload, table_type); 2277 mlxsw_reg_sftr2_range_set(payload, range); 2278 mlxsw_reg_sftr2_port_set(payload, port, set); 2279 mlxsw_reg_sftr2_port_mask_set(payload, port, 1); 2280 } 2281 2282 /* SMID-V2 - Switch Multicast ID Version 2 Register 2283 * ------------------------------------------------ 2284 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2285 * of the multicast group within the stacking domain, into a list of local 2286 * ports into which the packet is replicated. 2287 */ 2288 #define MLXSW_REG_SMID2_ID 0x2034 2289 #define MLXSW_REG_SMID2_LEN 0x120 2290 2291 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2292 2293 /* reg_smid2_swid 2294 * Switch partition ID. 2295 * Access: Index 2296 */ 2297 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2298 2299 /* reg_smid2_mid 2300 * Multicast identifier - global identifier that represents the multicast group 2301 * across all devices. 2302 * Access: Index 2303 */ 2304 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2305 2306 /* reg_smid2_smpe_valid 2307 * SMPE is valid. 2308 * When not valid, the egress VID will not be modified by the SMPE table. 2309 * Access: RW 2310 * 2311 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2312 */ 2313 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2314 2315 /* reg_smid2_smpe 2316 * Switch multicast port to egress VID. 2317 * Access: RW 2318 * 2319 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2320 */ 2321 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2322 2323 /* reg_smid2_port 2324 * Local port memebership (1 bit per port). 2325 * Access: RW 2326 */ 2327 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2328 2329 /* reg_smid2_port_mask 2330 * Local port mask (1 bit per port). 2331 * Access: WO 2332 */ 2333 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2334 2335 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2336 bool set, bool smpe_valid, u16 smpe) 2337 { 2338 MLXSW_REG_ZERO(smid2, payload); 2339 mlxsw_reg_smid2_swid_set(payload, 0); 2340 mlxsw_reg_smid2_mid_set(payload, mid); 2341 mlxsw_reg_smid2_port_set(payload, port, set); 2342 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2343 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2344 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2345 } 2346 2347 /* CWTP - Congetion WRED ECN TClass Profile 2348 * ---------------------------------------- 2349 * Configures the profiles for queues of egress port and traffic class 2350 */ 2351 #define MLXSW_REG_CWTP_ID 0x2802 2352 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2353 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2354 #define MLXSW_REG_CWTP_LEN 0x40 2355 2356 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2357 2358 /* reg_cwtp_local_port 2359 * Local port number 2360 * Not supported for CPU port 2361 * Access: Index 2362 */ 2363 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2364 2365 /* reg_cwtp_traffic_class 2366 * Traffic Class to configure 2367 * Access: Index 2368 */ 2369 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2370 2371 /* reg_cwtp_profile_min 2372 * Minimum Average Queue Size of the profile in cells. 2373 * Access: RW 2374 */ 2375 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2376 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2377 2378 /* reg_cwtp_profile_percent 2379 * Percentage of WRED and ECN marking for maximum Average Queue size 2380 * Range is 0 to 100, units of integer percentage 2381 * Access: RW 2382 */ 2383 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2384 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2385 2386 /* reg_cwtp_profile_max 2387 * Maximum Average Queue size of the profile in cells 2388 * Access: RW 2389 */ 2390 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2391 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2392 2393 #define MLXSW_REG_CWTP_MIN_VALUE 64 2394 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2395 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2396 2397 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2398 u8 traffic_class) 2399 { 2400 int i; 2401 2402 MLXSW_REG_ZERO(cwtp, payload); 2403 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2404 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2405 2406 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2407 mlxsw_reg_cwtp_profile_min_set(payload, i, 2408 MLXSW_REG_CWTP_MIN_VALUE); 2409 mlxsw_reg_cwtp_profile_max_set(payload, i, 2410 MLXSW_REG_CWTP_MIN_VALUE); 2411 } 2412 } 2413 2414 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2415 2416 static inline void 2417 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2418 u32 probability) 2419 { 2420 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2421 2422 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2423 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2424 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2425 } 2426 2427 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2428 * --------------------------------------------------- 2429 * The CWTPM register maps each egress port and traffic class to profile num. 2430 */ 2431 #define MLXSW_REG_CWTPM_ID 0x2803 2432 #define MLXSW_REG_CWTPM_LEN 0x44 2433 2434 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2435 2436 /* reg_cwtpm_local_port 2437 * Local port number 2438 * Not supported for CPU port 2439 * Access: Index 2440 */ 2441 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2442 2443 /* reg_cwtpm_traffic_class 2444 * Traffic Class to configure 2445 * Access: Index 2446 */ 2447 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2448 2449 /* reg_cwtpm_ew 2450 * Control enablement of WRED for traffic class: 2451 * 0 - Disable 2452 * 1 - Enable 2453 * Access: RW 2454 */ 2455 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2456 2457 /* reg_cwtpm_ee 2458 * Control enablement of ECN for traffic class: 2459 * 0 - Disable 2460 * 1 - Enable 2461 * Access: RW 2462 */ 2463 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2464 2465 /* reg_cwtpm_tcp_g 2466 * TCP Green Profile. 2467 * Index of the profile within {port, traffic class} to use. 2468 * 0 for disabling both WRED and ECN for this type of traffic. 2469 * Access: RW 2470 */ 2471 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2472 2473 /* reg_cwtpm_tcp_y 2474 * TCP Yellow Profile. 2475 * Index of the profile within {port, traffic class} to use. 2476 * 0 for disabling both WRED and ECN for this type of traffic. 2477 * Access: RW 2478 */ 2479 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2480 2481 /* reg_cwtpm_tcp_r 2482 * TCP Red Profile. 2483 * Index of the profile within {port, traffic class} to use. 2484 * 0 for disabling both WRED and ECN for this type of traffic. 2485 * Access: RW 2486 */ 2487 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2488 2489 /* reg_cwtpm_ntcp_g 2490 * Non-TCP Green Profile. 2491 * Index of the profile within {port, traffic class} to use. 2492 * 0 for disabling both WRED and ECN for this type of traffic. 2493 * Access: RW 2494 */ 2495 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2496 2497 /* reg_cwtpm_ntcp_y 2498 * Non-TCP Yellow Profile. 2499 * Index of the profile within {port, traffic class} to use. 2500 * 0 for disabling both WRED and ECN for this type of traffic. 2501 * Access: RW 2502 */ 2503 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2504 2505 /* reg_cwtpm_ntcp_r 2506 * Non-TCP Red Profile. 2507 * Index of the profile within {port, traffic class} to use. 2508 * 0 for disabling both WRED and ECN for this type of traffic. 2509 * Access: RW 2510 */ 2511 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2512 2513 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2514 2515 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2516 u8 traffic_class, u8 profile, 2517 bool wred, bool ecn) 2518 { 2519 MLXSW_REG_ZERO(cwtpm, payload); 2520 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2521 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2522 mlxsw_reg_cwtpm_ew_set(payload, wred); 2523 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2524 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2525 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2526 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2527 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2528 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2529 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2530 } 2531 2532 /* PGCR - Policy-Engine General Configuration Register 2533 * --------------------------------------------------- 2534 * This register configures general Policy-Engine settings. 2535 */ 2536 #define MLXSW_REG_PGCR_ID 0x3001 2537 #define MLXSW_REG_PGCR_LEN 0x20 2538 2539 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2540 2541 /* reg_pgcr_default_action_pointer_base 2542 * Default action pointer base. Each region has a default action pointer 2543 * which is equal to default_action_pointer_base + region_id. 2544 * Access: RW 2545 */ 2546 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2547 2548 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2549 { 2550 MLXSW_REG_ZERO(pgcr, payload); 2551 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2552 } 2553 2554 /* PPBT - Policy-Engine Port Binding Table 2555 * --------------------------------------- 2556 * This register is used for configuration of the Port Binding Table. 2557 */ 2558 #define MLXSW_REG_PPBT_ID 0x3002 2559 #define MLXSW_REG_PPBT_LEN 0x14 2560 2561 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2562 2563 enum mlxsw_reg_pxbt_e { 2564 MLXSW_REG_PXBT_E_IACL, 2565 MLXSW_REG_PXBT_E_EACL, 2566 }; 2567 2568 /* reg_ppbt_e 2569 * Access: Index 2570 */ 2571 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2572 2573 enum mlxsw_reg_pxbt_op { 2574 MLXSW_REG_PXBT_OP_BIND, 2575 MLXSW_REG_PXBT_OP_UNBIND, 2576 }; 2577 2578 /* reg_ppbt_op 2579 * Access: RW 2580 */ 2581 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2582 2583 /* reg_ppbt_local_port 2584 * Local port. Not including CPU port. 2585 * Access: Index 2586 */ 2587 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2588 2589 /* reg_ppbt_g 2590 * group - When set, the binding is of an ACL group. When cleared, 2591 * the binding is of an ACL. 2592 * Must be set to 1 for Spectrum. 2593 * Access: RW 2594 */ 2595 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2596 2597 /* reg_ppbt_acl_info 2598 * ACL/ACL group identifier. If the g bit is set, this field should hold 2599 * the acl_group_id, else it should hold the acl_id. 2600 * Access: RW 2601 */ 2602 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2603 2604 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2605 enum mlxsw_reg_pxbt_op op, 2606 u16 local_port, u16 acl_info) 2607 { 2608 MLXSW_REG_ZERO(ppbt, payload); 2609 mlxsw_reg_ppbt_e_set(payload, e); 2610 mlxsw_reg_ppbt_op_set(payload, op); 2611 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2612 mlxsw_reg_ppbt_g_set(payload, true); 2613 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2614 } 2615 2616 /* PACL - Policy-Engine ACL Register 2617 * --------------------------------- 2618 * This register is used for configuration of the ACL. 2619 */ 2620 #define MLXSW_REG_PACL_ID 0x3004 2621 #define MLXSW_REG_PACL_LEN 0x70 2622 2623 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2624 2625 /* reg_pacl_v 2626 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2627 * while the ACL is bounded to either a port, VLAN or ACL rule. 2628 * Access: RW 2629 */ 2630 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2631 2632 /* reg_pacl_acl_id 2633 * An identifier representing the ACL (managed by software) 2634 * Range 0 .. cap_max_acl_regions - 1 2635 * Access: Index 2636 */ 2637 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2638 2639 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2640 2641 /* reg_pacl_tcam_region_info 2642 * Opaque object that represents a TCAM region. 2643 * Obtained through PTAR register. 2644 * Access: RW 2645 */ 2646 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2647 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2648 2649 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2650 bool valid, const char *tcam_region_info) 2651 { 2652 MLXSW_REG_ZERO(pacl, payload); 2653 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2654 mlxsw_reg_pacl_v_set(payload, valid); 2655 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2656 } 2657 2658 /* PAGT - Policy-Engine ACL Group Table 2659 * ------------------------------------ 2660 * This register is used for configuration of the ACL Group Table. 2661 */ 2662 #define MLXSW_REG_PAGT_ID 0x3005 2663 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2664 #define MLXSW_REG_PAGT_ACL_LEN 4 2665 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2666 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2667 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2668 2669 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2670 2671 /* reg_pagt_size 2672 * Number of ACLs in the group. 2673 * Size 0 invalidates a group. 2674 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2675 * Total number of ACLs in all groups must be lower or equal 2676 * to cap_max_acl_tot_groups 2677 * Note: a group which is binded must not be invalidated 2678 * Access: Index 2679 */ 2680 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2681 2682 /* reg_pagt_acl_group_id 2683 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2684 * the ACL Group identifier (managed by software). 2685 * Access: Index 2686 */ 2687 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2688 2689 /* reg_pagt_multi 2690 * Multi-ACL 2691 * 0 - This ACL is the last ACL in the multi-ACL 2692 * 1 - This ACL is part of a multi-ACL 2693 * Access: RW 2694 */ 2695 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2696 2697 /* reg_pagt_acl_id 2698 * ACL identifier 2699 * Access: RW 2700 */ 2701 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2702 2703 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2704 { 2705 MLXSW_REG_ZERO(pagt, payload); 2706 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2707 } 2708 2709 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2710 u16 acl_id, bool multi) 2711 { 2712 u8 size = mlxsw_reg_pagt_size_get(payload); 2713 2714 if (index >= size) 2715 mlxsw_reg_pagt_size_set(payload, index + 1); 2716 mlxsw_reg_pagt_multi_set(payload, index, multi); 2717 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2718 } 2719 2720 /* PTAR - Policy-Engine TCAM Allocation Register 2721 * --------------------------------------------- 2722 * This register is used for allocation of regions in the TCAM. 2723 * Note: Query method is not supported on this register. 2724 */ 2725 #define MLXSW_REG_PTAR_ID 0x3006 2726 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2727 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2728 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2729 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2730 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2731 2732 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2733 2734 enum mlxsw_reg_ptar_op { 2735 /* allocate a TCAM region */ 2736 MLXSW_REG_PTAR_OP_ALLOC, 2737 /* resize a TCAM region */ 2738 MLXSW_REG_PTAR_OP_RESIZE, 2739 /* deallocate TCAM region */ 2740 MLXSW_REG_PTAR_OP_FREE, 2741 /* test allocation */ 2742 MLXSW_REG_PTAR_OP_TEST, 2743 }; 2744 2745 /* reg_ptar_op 2746 * Access: OP 2747 */ 2748 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2749 2750 /* reg_ptar_action_set_type 2751 * Type of action set to be used on this region. 2752 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2753 * Access: WO 2754 */ 2755 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2756 2757 enum mlxsw_reg_ptar_key_type { 2758 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2759 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2760 }; 2761 2762 /* reg_ptar_key_type 2763 * TCAM key type for the region. 2764 * Access: WO 2765 */ 2766 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2767 2768 /* reg_ptar_region_size 2769 * TCAM region size. When allocating/resizing this is the requested size, 2770 * the response is the actual size. Note that actual size may be 2771 * larger than requested. 2772 * Allowed range 1 .. cap_max_rules-1 2773 * Reserved during op deallocate. 2774 * Access: WO 2775 */ 2776 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2777 2778 /* reg_ptar_region_id 2779 * Region identifier 2780 * Range 0 .. cap_max_regions-1 2781 * Access: Index 2782 */ 2783 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2784 2785 /* reg_ptar_tcam_region_info 2786 * Opaque object that represents the TCAM region. 2787 * Returned when allocating a region. 2788 * Provided by software for ACL generation and region deallocation and resize. 2789 * Access: RW 2790 */ 2791 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2792 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2793 2794 /* reg_ptar_flexible_key_id 2795 * Identifier of the Flexible Key. 2796 * Only valid if key_type == "FLEX_KEY" 2797 * The key size will be rounded up to one of the following values: 2798 * 9B, 18B, 36B, 54B. 2799 * This field is reserved for in resize operation. 2800 * Access: WO 2801 */ 2802 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2803 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2804 2805 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2806 enum mlxsw_reg_ptar_key_type key_type, 2807 u16 region_size, u16 region_id, 2808 const char *tcam_region_info) 2809 { 2810 MLXSW_REG_ZERO(ptar, payload); 2811 mlxsw_reg_ptar_op_set(payload, op); 2812 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2813 mlxsw_reg_ptar_key_type_set(payload, key_type); 2814 mlxsw_reg_ptar_region_size_set(payload, region_size); 2815 mlxsw_reg_ptar_region_id_set(payload, region_id); 2816 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2817 } 2818 2819 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2820 u16 key_id) 2821 { 2822 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2823 } 2824 2825 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2826 { 2827 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2828 } 2829 2830 /* PPBS - Policy-Engine Policy Based Switching Register 2831 * ---------------------------------------------------- 2832 * This register retrieves and sets Policy Based Switching Table entries. 2833 */ 2834 #define MLXSW_REG_PPBS_ID 0x300C 2835 #define MLXSW_REG_PPBS_LEN 0x14 2836 2837 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2838 2839 /* reg_ppbs_pbs_ptr 2840 * Index into the PBS table. 2841 * For Spectrum, the index points to the KVD Linear. 2842 * Access: Index 2843 */ 2844 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2845 2846 /* reg_ppbs_system_port 2847 * Unique port identifier for the final destination of the packet. 2848 * Access: RW 2849 */ 2850 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2851 2852 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2853 u16 system_port) 2854 { 2855 MLXSW_REG_ZERO(ppbs, payload); 2856 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2857 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2858 } 2859 2860 /* PRCR - Policy-Engine Rules Copy Register 2861 * ---------------------------------------- 2862 * This register is used for accessing rules within a TCAM region. 2863 */ 2864 #define MLXSW_REG_PRCR_ID 0x300D 2865 #define MLXSW_REG_PRCR_LEN 0x40 2866 2867 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2868 2869 enum mlxsw_reg_prcr_op { 2870 /* Move rules. Moves the rules from "tcam_region_info" starting 2871 * at offset "offset" to "dest_tcam_region_info" 2872 * at offset "dest_offset." 2873 */ 2874 MLXSW_REG_PRCR_OP_MOVE, 2875 /* Copy rules. Copies the rules from "tcam_region_info" starting 2876 * at offset "offset" to "dest_tcam_region_info" 2877 * at offset "dest_offset." 2878 */ 2879 MLXSW_REG_PRCR_OP_COPY, 2880 }; 2881 2882 /* reg_prcr_op 2883 * Access: OP 2884 */ 2885 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2886 2887 /* reg_prcr_offset 2888 * Offset within the source region to copy/move from. 2889 * Access: Index 2890 */ 2891 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2892 2893 /* reg_prcr_size 2894 * The number of rules to copy/move. 2895 * Access: WO 2896 */ 2897 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2898 2899 /* reg_prcr_tcam_region_info 2900 * Opaque object that represents the source TCAM region. 2901 * Access: Index 2902 */ 2903 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2904 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2905 2906 /* reg_prcr_dest_offset 2907 * Offset within the source region to copy/move to. 2908 * Access: Index 2909 */ 2910 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2911 2912 /* reg_prcr_dest_tcam_region_info 2913 * Opaque object that represents the destination TCAM region. 2914 * Access: Index 2915 */ 2916 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2917 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2918 2919 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2920 const char *src_tcam_region_info, 2921 u16 src_offset, 2922 const char *dest_tcam_region_info, 2923 u16 dest_offset, u16 size) 2924 { 2925 MLXSW_REG_ZERO(prcr, payload); 2926 mlxsw_reg_prcr_op_set(payload, op); 2927 mlxsw_reg_prcr_offset_set(payload, src_offset); 2928 mlxsw_reg_prcr_size_set(payload, size); 2929 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2930 src_tcam_region_info); 2931 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2932 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2933 dest_tcam_region_info); 2934 } 2935 2936 /* PEFA - Policy-Engine Extended Flexible Action Register 2937 * ------------------------------------------------------ 2938 * This register is used for accessing an extended flexible action entry 2939 * in the central KVD Linear Database. 2940 */ 2941 #define MLXSW_REG_PEFA_ID 0x300F 2942 #define MLXSW_REG_PEFA_LEN 0xB0 2943 2944 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2945 2946 /* reg_pefa_index 2947 * Index in the KVD Linear Centralized Database. 2948 * Access: Index 2949 */ 2950 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2951 2952 /* reg_pefa_a 2953 * Index in the KVD Linear Centralized Database. 2954 * Activity 2955 * For a new entry: set if ca=0, clear if ca=1 2956 * Set if a packet lookup has hit on the specific entry 2957 * Access: RO 2958 */ 2959 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2960 2961 /* reg_pefa_ca 2962 * Clear activity 2963 * When write: activity is according to this field 2964 * When read: after reading the activity is cleared according to ca 2965 * Access: OP 2966 */ 2967 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2968 2969 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2970 2971 /* reg_pefa_flex_action_set 2972 * Action-set to perform when rule is matched. 2973 * Must be zero padded if action set is shorter. 2974 * Access: RW 2975 */ 2976 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2977 2978 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2979 const char *flex_action_set) 2980 { 2981 MLXSW_REG_ZERO(pefa, payload); 2982 mlxsw_reg_pefa_index_set(payload, index); 2983 mlxsw_reg_pefa_ca_set(payload, ca); 2984 if (flex_action_set) 2985 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2986 flex_action_set); 2987 } 2988 2989 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2990 { 2991 *p_a = mlxsw_reg_pefa_a_get(payload); 2992 } 2993 2994 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2995 * -------------------------------------------------------------- 2996 * This register is used for binding Multicast router to an ACL group 2997 * that serves the MC router. 2998 * This register is not supported by SwitchX/-2 and Spectrum. 2999 */ 3000 #define MLXSW_REG_PEMRBT_ID 0x3014 3001 #define MLXSW_REG_PEMRBT_LEN 0x14 3002 3003 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 3004 3005 enum mlxsw_reg_pemrbt_protocol { 3006 MLXSW_REG_PEMRBT_PROTO_IPV4, 3007 MLXSW_REG_PEMRBT_PROTO_IPV6, 3008 }; 3009 3010 /* reg_pemrbt_protocol 3011 * Access: Index 3012 */ 3013 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 3014 3015 /* reg_pemrbt_group_id 3016 * ACL group identifier. 3017 * Range 0..cap_max_acl_groups-1 3018 * Access: RW 3019 */ 3020 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 3021 3022 static inline void 3023 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 3024 u16 group_id) 3025 { 3026 MLXSW_REG_ZERO(pemrbt, payload); 3027 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 3028 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 3029 } 3030 3031 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 3032 * ----------------------------------------------------- 3033 * This register is used for accessing rules within a TCAM region. 3034 * It is a new version of PTCE in order to support wider key, 3035 * mask and action within a TCAM region. This register is not supported 3036 * by SwitchX and SwitchX-2. 3037 */ 3038 #define MLXSW_REG_PTCE2_ID 0x3017 3039 #define MLXSW_REG_PTCE2_LEN 0x1D8 3040 3041 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3042 3043 /* reg_ptce2_v 3044 * Valid. 3045 * Access: RW 3046 */ 3047 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3048 3049 /* reg_ptce2_a 3050 * Activity. Set if a packet lookup has hit on the specific entry. 3051 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3052 * Access: RO 3053 */ 3054 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3055 3056 enum mlxsw_reg_ptce2_op { 3057 /* Read operation. */ 3058 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3059 /* clear on read operation. Used to read entry 3060 * and clear Activity bit. 3061 */ 3062 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3063 /* Write operation. Used to write a new entry to the table. 3064 * All R/W fields are relevant for new entry. Activity bit is set 3065 * for new entries - Note write with v = 0 will delete the entry. 3066 */ 3067 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3068 /* Update action. Only action set will be updated. */ 3069 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3070 /* Clear activity. A bit is cleared for the entry. */ 3071 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3072 }; 3073 3074 /* reg_ptce2_op 3075 * Access: OP 3076 */ 3077 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3078 3079 /* reg_ptce2_offset 3080 * Access: Index 3081 */ 3082 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3083 3084 /* reg_ptce2_priority 3085 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3086 * Note: priority does not have to be unique per rule. 3087 * Within a region, higher priority should have lower offset (no limitation 3088 * between regions in a multi-region). 3089 * Access: RW 3090 */ 3091 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3092 3093 /* reg_ptce2_tcam_region_info 3094 * Opaque object that represents the TCAM region. 3095 * Access: Index 3096 */ 3097 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3098 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3099 3100 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3101 3102 /* reg_ptce2_flex_key_blocks 3103 * ACL Key. 3104 * Access: RW 3105 */ 3106 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3107 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3108 3109 /* reg_ptce2_mask 3110 * mask- in the same size as key. A bit that is set directs the TCAM 3111 * to compare the corresponding bit in key. A bit that is clear directs 3112 * the TCAM to ignore the corresponding bit in key. 3113 * Access: RW 3114 */ 3115 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3116 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3117 3118 /* reg_ptce2_flex_action_set 3119 * ACL action set. 3120 * Access: RW 3121 */ 3122 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3123 MLXSW_REG_FLEX_ACTION_SET_LEN); 3124 3125 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3126 enum mlxsw_reg_ptce2_op op, 3127 const char *tcam_region_info, 3128 u16 offset, u32 priority) 3129 { 3130 MLXSW_REG_ZERO(ptce2, payload); 3131 mlxsw_reg_ptce2_v_set(payload, valid); 3132 mlxsw_reg_ptce2_op_set(payload, op); 3133 mlxsw_reg_ptce2_offset_set(payload, offset); 3134 mlxsw_reg_ptce2_priority_set(payload, priority); 3135 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3136 } 3137 3138 /* PERPT - Policy-Engine ERP Table Register 3139 * ---------------------------------------- 3140 * This register adds and removes eRPs from the eRP table. 3141 */ 3142 #define MLXSW_REG_PERPT_ID 0x3021 3143 #define MLXSW_REG_PERPT_LEN 0x80 3144 3145 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3146 3147 /* reg_perpt_erpt_bank 3148 * eRP table bank. 3149 * Range 0 .. cap_max_erp_table_banks - 1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3153 3154 /* reg_perpt_erpt_index 3155 * Index to eRP table within the eRP bank. 3156 * Range is 0 .. cap_max_erp_table_bank_size - 1 3157 * Access: Index 3158 */ 3159 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3160 3161 enum mlxsw_reg_perpt_key_size { 3162 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3163 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3164 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3165 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3166 }; 3167 3168 /* reg_perpt_key_size 3169 * Access: OP 3170 */ 3171 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3172 3173 /* reg_perpt_bf_bypass 3174 * 0 - The eRP is used only if bloom filter state is set for the given 3175 * rule. 3176 * 1 - The eRP is used regardless of bloom filter state. 3177 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3178 * Access: RW 3179 */ 3180 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3181 3182 /* reg_perpt_erp_id 3183 * eRP ID for use by the rules. 3184 * Access: RW 3185 */ 3186 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3187 3188 /* reg_perpt_erpt_base_bank 3189 * Base eRP table bank, points to head of erp_vector 3190 * Range is 0 .. cap_max_erp_table_banks - 1 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3194 3195 /* reg_perpt_erpt_base_index 3196 * Base index to eRP table within the eRP bank 3197 * Range is 0 .. cap_max_erp_table_bank_size - 1 3198 * Access: OP 3199 */ 3200 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3201 3202 /* reg_perpt_erp_index_in_vector 3203 * eRP index in the vector. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3207 3208 /* reg_perpt_erp_vector 3209 * eRP vector. 3210 * Access: OP 3211 */ 3212 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3213 3214 /* reg_perpt_mask 3215 * Mask 3216 * 0 - A-TCAM will ignore the bit in key 3217 * 1 - A-TCAM will compare the bit in key 3218 * Access: RW 3219 */ 3220 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3221 3222 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3223 unsigned long *erp_vector, 3224 unsigned long size) 3225 { 3226 unsigned long bit; 3227 3228 for_each_set_bit(bit, erp_vector, size) 3229 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3230 } 3231 3232 static inline void 3233 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3234 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3235 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3236 char *mask) 3237 { 3238 MLXSW_REG_ZERO(perpt, payload); 3239 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3240 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3241 mlxsw_reg_perpt_key_size_set(payload, key_size); 3242 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3243 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3244 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3245 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3246 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3247 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3248 } 3249 3250 /* PERAR - Policy-Engine Region Association Register 3251 * ------------------------------------------------- 3252 * This register associates a hw region for region_id's. Changing on the fly 3253 * is supported by the device. 3254 */ 3255 #define MLXSW_REG_PERAR_ID 0x3026 3256 #define MLXSW_REG_PERAR_LEN 0x08 3257 3258 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3259 3260 /* reg_perar_region_id 3261 * Region identifier 3262 * Range 0 .. cap_max_regions-1 3263 * Access: Index 3264 */ 3265 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3266 3267 static inline unsigned int 3268 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3269 { 3270 return DIV_ROUND_UP(block_num, 4); 3271 } 3272 3273 /* reg_perar_hw_region 3274 * HW Region 3275 * Range 0 .. cap_max_regions-1 3276 * Default: hw_region = region_id 3277 * For a 8 key block region, 2 consecutive regions are used 3278 * For a 12 key block region, 3 consecutive regions are used 3279 * Access: RW 3280 */ 3281 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3282 3283 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3284 u16 hw_region) 3285 { 3286 MLXSW_REG_ZERO(perar, payload); 3287 mlxsw_reg_perar_region_id_set(payload, region_id); 3288 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3289 } 3290 3291 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3292 * ----------------------------------------------------- 3293 * This register is a new version of PTCE-V2 in order to support the 3294 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3295 */ 3296 #define MLXSW_REG_PTCE3_ID 0x3027 3297 #define MLXSW_REG_PTCE3_LEN 0xF0 3298 3299 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3300 3301 /* reg_ptce3_v 3302 * Valid. 3303 * Access: RW 3304 */ 3305 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3306 3307 enum mlxsw_reg_ptce3_op { 3308 /* Write operation. Used to write a new entry to the table. 3309 * All R/W fields are relevant for new entry. Activity bit is set 3310 * for new entries. Write with v = 0 will delete the entry. Must 3311 * not be used if an entry exists. 3312 */ 3313 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3314 /* Update operation */ 3315 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3316 /* Read operation */ 3317 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3318 }; 3319 3320 /* reg_ptce3_op 3321 * Access: OP 3322 */ 3323 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3324 3325 /* reg_ptce3_priority 3326 * Priority of the rule. Higher values win. 3327 * For Spectrum-2 range is 1..cap_kvd_size - 1 3328 * Note: Priority does not have to be unique per rule. 3329 * Access: RW 3330 */ 3331 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3332 3333 /* reg_ptce3_tcam_region_info 3334 * Opaque object that represents the TCAM region. 3335 * Access: Index 3336 */ 3337 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3338 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3339 3340 /* reg_ptce3_flex2_key_blocks 3341 * ACL key. The key must be masked according to eRP (if exists) or 3342 * according to master mask. 3343 * Access: Index 3344 */ 3345 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3346 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3347 3348 /* reg_ptce3_erp_id 3349 * eRP ID. 3350 * Access: Index 3351 */ 3352 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3353 3354 /* reg_ptce3_delta_start 3355 * Start point of delta_value and delta_mask, in bits. Must not exceed 3356 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3357 * Access: Index 3358 */ 3359 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3360 3361 /* reg_ptce3_delta_mask 3362 * Delta mask. 3363 * 0 - Ignore relevant bit in delta_value 3364 * 1 - Compare relevant bit in delta_value 3365 * Delta mask must not be set for reserved fields in the key blocks. 3366 * Note: No delta when no eRPs. Thus, for regions with 3367 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3368 * Access: Index 3369 */ 3370 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3371 3372 /* reg_ptce3_delta_value 3373 * Delta value. 3374 * Bits which are masked by delta_mask must be 0. 3375 * Access: Index 3376 */ 3377 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3378 3379 /* reg_ptce3_prune_vector 3380 * Pruning vector relative to the PERPT.erp_id. 3381 * Used for reducing lookups. 3382 * 0 - NEED: Do a lookup using the eRP. 3383 * 1 - PRUNE: Do not perform a lookup using the eRP. 3384 * Maybe be modified by PEAPBL and PEAPBM. 3385 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3386 * all 1's or all 0's. 3387 * Access: RW 3388 */ 3389 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3390 3391 /* reg_ptce3_prune_ctcam 3392 * Pruning on C-TCAM. Used for reducing lookups. 3393 * 0 - NEED: Do a lookup in the C-TCAM. 3394 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3395 * Access: RW 3396 */ 3397 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3398 3399 /* reg_ptce3_large_exists 3400 * Large entry key ID exists. 3401 * Within the region: 3402 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3403 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3404 * For rule delete: The MSB of the key will be removed. 3405 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3406 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3407 * For rule delete: The MSB of the key will not be removed. 3408 * Access: WO 3409 */ 3410 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3411 3412 /* reg_ptce3_large_entry_key_id 3413 * Large entry key ID. 3414 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3415 * blocks. Must be different for different keys which have the same common 3416 * 6 key blocks (MSB, blocks 6..11) key within a region. 3417 * Range is 0..cap_max_pe_large_key_id - 1 3418 * Access: RW 3419 */ 3420 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3421 3422 /* reg_ptce3_action_pointer 3423 * Pointer to action. 3424 * Range is 0..cap_max_kvd_action_sets - 1 3425 * Access: RW 3426 */ 3427 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3428 3429 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3430 enum mlxsw_reg_ptce3_op op, 3431 u32 priority, 3432 const char *tcam_region_info, 3433 const char *key, u8 erp_id, 3434 u16 delta_start, u8 delta_mask, 3435 u8 delta_value, bool large_exists, 3436 u32 lkey_id, u32 action_pointer) 3437 { 3438 MLXSW_REG_ZERO(ptce3, payload); 3439 mlxsw_reg_ptce3_v_set(payload, valid); 3440 mlxsw_reg_ptce3_op_set(payload, op); 3441 mlxsw_reg_ptce3_priority_set(payload, priority); 3442 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3443 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3444 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3445 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3446 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3447 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3448 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3449 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3450 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3451 } 3452 3453 /* PERCR - Policy-Engine Region Configuration Register 3454 * --------------------------------------------------- 3455 * This register configures the region parameters. The region_id must be 3456 * allocated. 3457 */ 3458 #define MLXSW_REG_PERCR_ID 0x302A 3459 #define MLXSW_REG_PERCR_LEN 0x80 3460 3461 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3462 3463 /* reg_percr_region_id 3464 * Region identifier. 3465 * Range 0..cap_max_regions-1 3466 * Access: Index 3467 */ 3468 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3469 3470 /* reg_percr_atcam_ignore_prune 3471 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3472 * Access: RW 3473 */ 3474 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3475 3476 /* reg_percr_ctcam_ignore_prune 3477 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3478 * Access: RW 3479 */ 3480 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3481 3482 /* reg_percr_bf_bypass 3483 * Bloom filter bypass. 3484 * 0 - Bloom filter is used (default) 3485 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3486 * region_id or eRP. See PERPT.bf_bypass 3487 * Access: RW 3488 */ 3489 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3490 3491 /* reg_percr_master_mask 3492 * Master mask. Logical OR mask of all masks of all rules of a region 3493 * (both A-TCAM and C-TCAM). When there are no eRPs 3494 * (erpt_pointer_valid = 0), then this provides the mask. 3495 * Access: RW 3496 */ 3497 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3498 3499 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3500 { 3501 MLXSW_REG_ZERO(percr, payload); 3502 mlxsw_reg_percr_region_id_set(payload, region_id); 3503 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3504 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3505 mlxsw_reg_percr_bf_bypass_set(payload, false); 3506 } 3507 3508 /* PERERP - Policy-Engine Region eRP Register 3509 * ------------------------------------------ 3510 * This register configures the region eRP. The region_id must be 3511 * allocated. 3512 */ 3513 #define MLXSW_REG_PERERP_ID 0x302B 3514 #define MLXSW_REG_PERERP_LEN 0x1C 3515 3516 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3517 3518 /* reg_pererp_region_id 3519 * Region identifier. 3520 * Range 0..cap_max_regions-1 3521 * Access: Index 3522 */ 3523 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3524 3525 /* reg_pererp_ctcam_le 3526 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3527 * Access: RW 3528 */ 3529 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3530 3531 /* reg_pererp_erpt_pointer_valid 3532 * erpt_pointer is valid. 3533 * Access: RW 3534 */ 3535 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3536 3537 /* reg_pererp_erpt_bank_pointer 3538 * Pointer to eRP table bank. May be modified at any time. 3539 * Range 0..cap_max_erp_table_banks-1 3540 * Reserved when erpt_pointer_valid = 0 3541 */ 3542 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3543 3544 /* reg_pererp_erpt_pointer 3545 * Pointer to eRP table within the eRP bank. Can be changed for an 3546 * existing region. 3547 * Range 0..cap_max_erp_table_size-1 3548 * Reserved when erpt_pointer_valid = 0 3549 * Access: RW 3550 */ 3551 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3552 3553 /* reg_pererp_erpt_vector 3554 * Vector of allowed eRP indexes starting from erpt_pointer within the 3555 * erpt_bank_pointer. Next entries will be in next bank. 3556 * Note that eRP index is used and not eRP ID. 3557 * Reserved when erpt_pointer_valid = 0 3558 * Access: RW 3559 */ 3560 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3561 3562 /* reg_pererp_master_rp_id 3563 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3564 * for the lookup. Can be changed for an existing region. 3565 * Reserved when erpt_pointer_valid = 1 3566 * Access: RW 3567 */ 3568 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3569 3570 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3571 unsigned long *erp_vector, 3572 unsigned long size) 3573 { 3574 unsigned long bit; 3575 3576 for_each_set_bit(bit, erp_vector, size) 3577 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3578 } 3579 3580 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3581 bool ctcam_le, bool erpt_pointer_valid, 3582 u8 erpt_bank_pointer, u8 erpt_pointer, 3583 u8 master_rp_id) 3584 { 3585 MLXSW_REG_ZERO(pererp, payload); 3586 mlxsw_reg_pererp_region_id_set(payload, region_id); 3587 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3588 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3589 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3590 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3591 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3592 } 3593 3594 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3595 * ---------------------------------------------------------------- 3596 * This register configures the Bloom filter entries. 3597 */ 3598 #define MLXSW_REG_PEABFE_ID 0x3022 3599 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3600 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3601 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3602 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3603 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3604 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3605 3606 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3607 3608 /* reg_peabfe_size 3609 * Number of BF entries to be updated. 3610 * Range 1..256 3611 * Access: Op 3612 */ 3613 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3614 3615 /* reg_peabfe_bf_entry_state 3616 * Bloom filter state 3617 * 0 - Clear 3618 * 1 - Set 3619 * Access: RW 3620 */ 3621 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3622 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3623 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3624 3625 /* reg_peabfe_bf_entry_bank 3626 * Bloom filter bank ID 3627 * Range 0..cap_max_erp_table_banks-1 3628 * Access: Index 3629 */ 3630 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3631 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3632 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3633 3634 /* reg_peabfe_bf_entry_index 3635 * Bloom filter entry index 3636 * Range 0..2^cap_max_bf_log-1 3637 * Access: Index 3638 */ 3639 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3640 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3641 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3642 3643 static inline void mlxsw_reg_peabfe_pack(char *payload) 3644 { 3645 MLXSW_REG_ZERO(peabfe, payload); 3646 } 3647 3648 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3649 u8 state, u8 bank, u32 bf_index) 3650 { 3651 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3652 3653 if (rec_index >= num_rec) 3654 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3655 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3656 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3657 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3658 } 3659 3660 /* IEDR - Infrastructure Entry Delete Register 3661 * ---------------------------------------------------- 3662 * This register is used for deleting entries from the entry tables. 3663 * It is legitimate to attempt to delete a nonexisting entry (the device will 3664 * respond as a good flow). 3665 */ 3666 #define MLXSW_REG_IEDR_ID 0x3804 3667 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3668 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3669 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3670 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3671 MLXSW_REG_IEDR_REC_LEN * \ 3672 MLXSW_REG_IEDR_REC_MAX_COUNT) 3673 3674 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3675 3676 /* reg_iedr_num_rec 3677 * Number of records. 3678 * Access: OP 3679 */ 3680 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3681 3682 /* reg_iedr_rec_type 3683 * Resource type. 3684 * Access: OP 3685 */ 3686 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3687 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3688 3689 /* reg_iedr_rec_size 3690 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3691 * Access: OP 3692 */ 3693 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3694 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3695 3696 /* reg_iedr_rec_index_start 3697 * Resource index start. 3698 * Access: OP 3699 */ 3700 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3701 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3702 3703 static inline void mlxsw_reg_iedr_pack(char *payload) 3704 { 3705 MLXSW_REG_ZERO(iedr, payload); 3706 } 3707 3708 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3709 u8 rec_type, u16 rec_size, 3710 u32 rec_index_start) 3711 { 3712 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3713 3714 if (rec_index >= num_rec) 3715 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3716 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3717 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3718 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3719 } 3720 3721 /* QPTS - QoS Priority Trust State Register 3722 * ---------------------------------------- 3723 * This register controls the port policy to calculate the switch priority and 3724 * packet color based on incoming packet fields. 3725 */ 3726 #define MLXSW_REG_QPTS_ID 0x4002 3727 #define MLXSW_REG_QPTS_LEN 0x8 3728 3729 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3730 3731 /* reg_qpts_local_port 3732 * Local port number. 3733 * Access: Index 3734 * 3735 * Note: CPU port is supported. 3736 */ 3737 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3738 3739 enum mlxsw_reg_qpts_trust_state { 3740 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3741 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3742 }; 3743 3744 /* reg_qpts_trust_state 3745 * Trust state for a given port. 3746 * Access: RW 3747 */ 3748 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3749 3750 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3751 enum mlxsw_reg_qpts_trust_state ts) 3752 { 3753 MLXSW_REG_ZERO(qpts, payload); 3754 3755 mlxsw_reg_qpts_local_port_set(payload, local_port); 3756 mlxsw_reg_qpts_trust_state_set(payload, ts); 3757 } 3758 3759 /* QPCR - QoS Policer Configuration Register 3760 * ----------------------------------------- 3761 * The QPCR register is used to create policers - that limit 3762 * the rate of bytes or packets via some trap group. 3763 */ 3764 #define MLXSW_REG_QPCR_ID 0x4004 3765 #define MLXSW_REG_QPCR_LEN 0x28 3766 3767 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3768 3769 enum mlxsw_reg_qpcr_g { 3770 MLXSW_REG_QPCR_G_GLOBAL = 2, 3771 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3772 }; 3773 3774 /* reg_qpcr_g 3775 * The policer type. 3776 * Access: Index 3777 */ 3778 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3779 3780 /* reg_qpcr_pid 3781 * Policer ID. 3782 * Access: Index 3783 */ 3784 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3785 3786 /* reg_qpcr_clear_counter 3787 * Clear counters. 3788 * Access: OP 3789 */ 3790 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3791 3792 /* reg_qpcr_color_aware 3793 * Is the policer aware of colors. 3794 * Must be 0 (unaware) for cpu port. 3795 * Access: RW for unbounded policer. RO for bounded policer. 3796 */ 3797 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3798 3799 /* reg_qpcr_bytes 3800 * Is policer limit is for bytes per sec or packets per sec. 3801 * 0 - packets 3802 * 1 - bytes 3803 * Access: RW for unbounded policer. RO for bounded policer. 3804 */ 3805 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3806 3807 enum mlxsw_reg_qpcr_ir_units { 3808 MLXSW_REG_QPCR_IR_UNITS_M, 3809 MLXSW_REG_QPCR_IR_UNITS_K, 3810 }; 3811 3812 /* reg_qpcr_ir_units 3813 * Policer's units for cir and eir fields (for bytes limits only) 3814 * 1 - 10^3 3815 * 0 - 10^6 3816 * Access: OP 3817 */ 3818 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3819 3820 enum mlxsw_reg_qpcr_rate_type { 3821 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3822 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3823 }; 3824 3825 /* reg_qpcr_rate_type 3826 * Policer can have one limit (single rate) or 2 limits with specific operation 3827 * for packets that exceed the lower rate but not the upper one. 3828 * (For cpu port must be single rate) 3829 * Access: RW for unbounded policer. RO for bounded policer. 3830 */ 3831 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3832 3833 /* reg_qpc_cbs 3834 * Policer's committed burst size. 3835 * The policer is working with time slices of 50 nano sec. By default every 3836 * slice is granted the proportionate share of the committed rate. If we want to 3837 * allow a slice to exceed that share (while still keeping the rate per sec) we 3838 * can allow burst. The burst size is between the default proportionate share 3839 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3840 * committed rate will result in exceeding the rate). The burst size must be a 3841 * log of 2 and will be determined by 2^cbs. 3842 * Access: RW 3843 */ 3844 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3845 3846 /* reg_qpcr_cir 3847 * Policer's committed rate. 3848 * The rate used for sungle rate, the lower rate for double rate. 3849 * For bytes limits, the rate will be this value * the unit from ir_units. 3850 * (Resolution error is up to 1%). 3851 * Access: RW 3852 */ 3853 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3854 3855 /* reg_qpcr_eir 3856 * Policer's exceed rate. 3857 * The higher rate for double rate, reserved for single rate. 3858 * Lower rate for double rate policer. 3859 * For bytes limits, the rate will be this value * the unit from ir_units. 3860 * (Resolution error is up to 1%). 3861 * Access: RW 3862 */ 3863 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3864 3865 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3866 3867 /* reg_qpcr_exceed_action. 3868 * What to do with packets between the 2 limits for double rate. 3869 * Access: RW for unbounded policer. RO for bounded policer. 3870 */ 3871 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3872 3873 enum mlxsw_reg_qpcr_action { 3874 /* Discard */ 3875 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3876 /* Forward and set color to red. 3877 * If the packet is intended to cpu port, it will be dropped. 3878 */ 3879 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3880 }; 3881 3882 /* reg_qpcr_violate_action 3883 * What to do with packets that cross the cir limit (for single rate) or the eir 3884 * limit (for double rate). 3885 * Access: RW for unbounded policer. RO for bounded policer. 3886 */ 3887 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3888 3889 /* reg_qpcr_violate_count 3890 * Counts the number of times violate_action happened on this PID. 3891 * Access: RW 3892 */ 3893 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3894 3895 /* Packets */ 3896 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3897 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3898 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3899 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3900 3901 /* Bandwidth */ 3902 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3903 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3904 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3905 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3906 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3907 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3908 3909 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3910 enum mlxsw_reg_qpcr_ir_units ir_units, 3911 bool bytes, u32 cir, u16 cbs) 3912 { 3913 MLXSW_REG_ZERO(qpcr, payload); 3914 mlxsw_reg_qpcr_pid_set(payload, pid); 3915 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3916 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3917 mlxsw_reg_qpcr_violate_action_set(payload, 3918 MLXSW_REG_QPCR_ACTION_DISCARD); 3919 mlxsw_reg_qpcr_cir_set(payload, cir); 3920 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3921 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3922 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3923 } 3924 3925 /* QTCT - QoS Switch Traffic Class Table 3926 * ------------------------------------- 3927 * Configures the mapping between the packet switch priority and the 3928 * traffic class on the transmit port. 3929 */ 3930 #define MLXSW_REG_QTCT_ID 0x400A 3931 #define MLXSW_REG_QTCT_LEN 0x08 3932 3933 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3934 3935 /* reg_qtct_local_port 3936 * Local port number. 3937 * Access: Index 3938 * 3939 * Note: CPU port is not supported. 3940 */ 3941 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3942 3943 /* reg_qtct_sub_port 3944 * Virtual port within the physical port. 3945 * Should be set to 0 when virtual ports are not enabled on the port. 3946 * Access: Index 3947 */ 3948 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3949 3950 /* reg_qtct_switch_prio 3951 * Switch priority. 3952 * Access: Index 3953 */ 3954 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3955 3956 /* reg_qtct_tclass 3957 * Traffic class. 3958 * Default values: 3959 * switch_prio 0 : tclass 1 3960 * switch_prio 1 : tclass 0 3961 * switch_prio i : tclass i, for i > 1 3962 * Access: RW 3963 */ 3964 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3965 3966 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3967 u8 switch_prio, u8 tclass) 3968 { 3969 MLXSW_REG_ZERO(qtct, payload); 3970 mlxsw_reg_qtct_local_port_set(payload, local_port); 3971 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3972 mlxsw_reg_qtct_tclass_set(payload, tclass); 3973 } 3974 3975 /* QEEC - QoS ETS Element Configuration Register 3976 * --------------------------------------------- 3977 * Configures the ETS elements. 3978 */ 3979 #define MLXSW_REG_QEEC_ID 0x400D 3980 #define MLXSW_REG_QEEC_LEN 0x20 3981 3982 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3983 3984 /* reg_qeec_local_port 3985 * Local port number. 3986 * Access: Index 3987 * 3988 * Note: CPU port is supported. 3989 */ 3990 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 3991 3992 enum mlxsw_reg_qeec_hr { 3993 MLXSW_REG_QEEC_HR_PORT, 3994 MLXSW_REG_QEEC_HR_GROUP, 3995 MLXSW_REG_QEEC_HR_SUBGROUP, 3996 MLXSW_REG_QEEC_HR_TC, 3997 }; 3998 3999 /* reg_qeec_element_hierarchy 4000 * 0 - Port 4001 * 1 - Group 4002 * 2 - Subgroup 4003 * 3 - Traffic Class 4004 * Access: Index 4005 */ 4006 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 4007 4008 /* reg_qeec_element_index 4009 * The index of the element in the hierarchy. 4010 * Access: Index 4011 */ 4012 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 4013 4014 /* reg_qeec_next_element_index 4015 * The index of the next (lower) element in the hierarchy. 4016 * Access: RW 4017 * 4018 * Note: Reserved for element_hierarchy 0. 4019 */ 4020 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 4021 4022 /* reg_qeec_mise 4023 * Min shaper configuration enable. Enables configuration of the min 4024 * shaper on this ETS element 4025 * 0 - Disable 4026 * 1 - Enable 4027 * Access: RW 4028 */ 4029 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 4030 4031 /* reg_qeec_ptps 4032 * PTP shaper 4033 * 0: regular shaper mode 4034 * 1: PTP oriented shaper 4035 * Allowed only for hierarchy 0 4036 * Not supported for CPU port 4037 * Note that ptps mode may affect the shaper rates of all hierarchies 4038 * Supported only on Spectrum-1 4039 * Access: RW 4040 */ 4041 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4042 4043 enum { 4044 MLXSW_REG_QEEC_BYTES_MODE, 4045 MLXSW_REG_QEEC_PACKETS_MODE, 4046 }; 4047 4048 /* reg_qeec_pb 4049 * Packets or bytes mode. 4050 * 0 - Bytes mode 4051 * 1 - Packets mode 4052 * Access: RW 4053 * 4054 * Note: Used for max shaper configuration. For Spectrum, packets mode 4055 * is supported only for traffic classes of CPU port. 4056 */ 4057 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4058 4059 /* The smallest permitted min shaper rate. */ 4060 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4061 4062 /* reg_qeec_min_shaper_rate 4063 * Min shaper information rate. 4064 * For CPU port, can only be configured for port hierarchy. 4065 * When in bytes mode, value is specified in units of 1000bps. 4066 * Access: RW 4067 */ 4068 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4069 4070 /* reg_qeec_mase 4071 * Max shaper configuration enable. Enables configuration of the max 4072 * shaper on this ETS element. 4073 * 0 - Disable 4074 * 1 - Enable 4075 * Access: RW 4076 */ 4077 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4078 4079 /* The largest max shaper value possible to disable the shaper. */ 4080 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4081 4082 /* reg_qeec_max_shaper_rate 4083 * Max shaper information rate. 4084 * For CPU port, can only be configured for port hierarchy. 4085 * When in bytes mode, value is specified in units of 1000bps. 4086 * Access: RW 4087 */ 4088 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4089 4090 /* reg_qeec_de 4091 * DWRR configuration enable. Enables configuration of the dwrr and 4092 * dwrr_weight. 4093 * 0 - Disable 4094 * 1 - Enable 4095 * Access: RW 4096 */ 4097 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4098 4099 /* reg_qeec_dwrr 4100 * Transmission selection algorithm to use on the link going down from 4101 * the ETS element. 4102 * 0 - Strict priority 4103 * 1 - DWRR 4104 * Access: RW 4105 */ 4106 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4107 4108 /* reg_qeec_dwrr_weight 4109 * DWRR weight on the link going down from the ETS element. The 4110 * percentage of bandwidth guaranteed to an ETS element within 4111 * its hierarchy. The sum of all weights across all ETS elements 4112 * within one hierarchy should be equal to 100. Reserved when 4113 * transmission selection algorithm is strict priority. 4114 * Access: RW 4115 */ 4116 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4117 4118 /* reg_qeec_max_shaper_bs 4119 * Max shaper burst size 4120 * Burst size is 2^max_shaper_bs * 512 bits 4121 * For Spectrum-1: Range is: 5..25 4122 * For Spectrum-2: Range is: 11..25 4123 * Reserved when ptps = 1 4124 * Access: RW 4125 */ 4126 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4127 4128 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4129 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4130 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4131 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4132 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4133 4134 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4135 enum mlxsw_reg_qeec_hr hr, u8 index, 4136 u8 next_index) 4137 { 4138 MLXSW_REG_ZERO(qeec, payload); 4139 mlxsw_reg_qeec_local_port_set(payload, local_port); 4140 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4141 mlxsw_reg_qeec_element_index_set(payload, index); 4142 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4143 } 4144 4145 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4146 bool ptps) 4147 { 4148 MLXSW_REG_ZERO(qeec, payload); 4149 mlxsw_reg_qeec_local_port_set(payload, local_port); 4150 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4151 mlxsw_reg_qeec_ptps_set(payload, ptps); 4152 } 4153 4154 /* QRWE - QoS ReWrite Enable 4155 * ------------------------- 4156 * This register configures the rewrite enable per receive port. 4157 */ 4158 #define MLXSW_REG_QRWE_ID 0x400F 4159 #define MLXSW_REG_QRWE_LEN 0x08 4160 4161 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4162 4163 /* reg_qrwe_local_port 4164 * Local port number. 4165 * Access: Index 4166 * 4167 * Note: CPU port is supported. No support for router port. 4168 */ 4169 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4170 4171 /* reg_qrwe_dscp 4172 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4173 * Access: RW 4174 */ 4175 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4176 4177 /* reg_qrwe_pcp 4178 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4179 * Access: RW 4180 */ 4181 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4182 4183 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4184 bool rewrite_pcp, bool rewrite_dscp) 4185 { 4186 MLXSW_REG_ZERO(qrwe, payload); 4187 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4188 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4189 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4190 } 4191 4192 /* QPDSM - QoS Priority to DSCP Mapping 4193 * ------------------------------------ 4194 * QoS Priority to DSCP Mapping Register 4195 */ 4196 #define MLXSW_REG_QPDSM_ID 0x4011 4197 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4198 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4199 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4200 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4201 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4202 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4203 4204 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4205 4206 /* reg_qpdsm_local_port 4207 * Local Port. Supported for data packets from CPU port. 4208 * Access: Index 4209 */ 4210 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4211 4212 /* reg_qpdsm_prio_entry_color0_e 4213 * Enable update of the entry for color 0 and a given port. 4214 * Access: WO 4215 */ 4216 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4217 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4218 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4219 4220 /* reg_qpdsm_prio_entry_color0_dscp 4221 * DSCP field in the outer label of the packet for color 0 and a given port. 4222 * Reserved when e=0. 4223 * Access: RW 4224 */ 4225 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4226 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4227 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4228 4229 /* reg_qpdsm_prio_entry_color1_e 4230 * Enable update of the entry for color 1 and a given port. 4231 * Access: WO 4232 */ 4233 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4234 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4235 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4236 4237 /* reg_qpdsm_prio_entry_color1_dscp 4238 * DSCP field in the outer label of the packet for color 1 and a given port. 4239 * Reserved when e=0. 4240 * Access: RW 4241 */ 4242 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4243 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4244 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4245 4246 /* reg_qpdsm_prio_entry_color2_e 4247 * Enable update of the entry for color 2 and a given port. 4248 * Access: WO 4249 */ 4250 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4251 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4252 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4253 4254 /* reg_qpdsm_prio_entry_color2_dscp 4255 * DSCP field in the outer label of the packet for color 2 and a given port. 4256 * Reserved when e=0. 4257 * Access: RW 4258 */ 4259 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4260 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4261 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4262 4263 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4264 { 4265 MLXSW_REG_ZERO(qpdsm, payload); 4266 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4267 } 4268 4269 static inline void 4270 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4271 { 4272 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4273 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4274 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4275 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4276 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4277 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4278 } 4279 4280 /* QPDP - QoS Port DSCP to Priority Mapping Register 4281 * ------------------------------------------------- 4282 * This register controls the port default Switch Priority and Color. The 4283 * default Switch Priority and Color are used for frames where the trust state 4284 * uses default values. All member ports of a LAG should be configured with the 4285 * same default values. 4286 */ 4287 #define MLXSW_REG_QPDP_ID 0x4007 4288 #define MLXSW_REG_QPDP_LEN 0x8 4289 4290 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4291 4292 /* reg_qpdp_local_port 4293 * Local Port. Supported for data packets from CPU port. 4294 * Access: Index 4295 */ 4296 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4297 4298 /* reg_qpdp_switch_prio 4299 * Default port Switch Priority (default 0) 4300 * Access: RW 4301 */ 4302 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4303 4304 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4305 u8 switch_prio) 4306 { 4307 MLXSW_REG_ZERO(qpdp, payload); 4308 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4309 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4310 } 4311 4312 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4313 * -------------------------------------------------- 4314 * This register controls the mapping from DSCP field to 4315 * Switch Priority for IP packets. 4316 */ 4317 #define MLXSW_REG_QPDPM_ID 0x4013 4318 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4319 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4320 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4321 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4322 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4323 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4324 4325 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4326 4327 /* reg_qpdpm_local_port 4328 * Local Port. Supported for data packets from CPU port. 4329 * Access: Index 4330 */ 4331 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4332 4333 /* reg_qpdpm_dscp_e 4334 * Enable update of the specific entry. When cleared, the switch_prio and color 4335 * fields are ignored and the previous switch_prio and color values are 4336 * preserved. 4337 * Access: WO 4338 */ 4339 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4340 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4341 4342 /* reg_qpdpm_dscp_prio 4343 * The new Switch Priority value for the relevant DSCP value. 4344 * Access: RW 4345 */ 4346 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4347 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4348 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4349 4350 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4351 { 4352 MLXSW_REG_ZERO(qpdpm, payload); 4353 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4354 } 4355 4356 static inline void 4357 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4358 { 4359 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4360 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4361 } 4362 4363 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4364 * ------------------------------------------------------------------ 4365 * This register configures if the Switch Priority to Traffic Class mapping is 4366 * based on Multicast packet indication. If so, then multicast packets will get 4367 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4368 * QTCT. 4369 * By default, Switch Priority to Traffic Class mapping is not based on 4370 * Multicast packet indication. 4371 */ 4372 #define MLXSW_REG_QTCTM_ID 0x401A 4373 #define MLXSW_REG_QTCTM_LEN 0x08 4374 4375 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4376 4377 /* reg_qtctm_local_port 4378 * Local port number. 4379 * No support for CPU port. 4380 * Access: Index 4381 */ 4382 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4383 4384 /* reg_qtctm_mc 4385 * Multicast Mode 4386 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4387 * indication (default is 0, not based on Multicast packet indication). 4388 */ 4389 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4390 4391 static inline void 4392 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4393 { 4394 MLXSW_REG_ZERO(qtctm, payload); 4395 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4396 mlxsw_reg_qtctm_mc_set(payload, mc); 4397 } 4398 4399 /* QPSC - QoS PTP Shaper Configuration Register 4400 * -------------------------------------------- 4401 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4402 * Supported only on Spectrum-1. 4403 */ 4404 #define MLXSW_REG_QPSC_ID 0x401B 4405 #define MLXSW_REG_QPSC_LEN 0x28 4406 4407 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4408 4409 enum mlxsw_reg_qpsc_port_speed { 4410 MLXSW_REG_QPSC_PORT_SPEED_100M, 4411 MLXSW_REG_QPSC_PORT_SPEED_1G, 4412 MLXSW_REG_QPSC_PORT_SPEED_10G, 4413 MLXSW_REG_QPSC_PORT_SPEED_25G, 4414 }; 4415 4416 /* reg_qpsc_port_speed 4417 * Port speed. 4418 * Access: Index 4419 */ 4420 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4421 4422 /* reg_qpsc_shaper_time_exp 4423 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4424 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4425 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4426 * Access: RW 4427 */ 4428 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4429 4430 /* reg_qpsc_shaper_time_mantissa 4431 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4432 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4433 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4434 * Access: RW 4435 */ 4436 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4437 4438 /* reg_qpsc_shaper_inc 4439 * Number of tokens added to shaper on each update. 4440 * Units of 8B. 4441 * Access: RW 4442 */ 4443 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4444 4445 /* reg_qpsc_shaper_bs 4446 * Max shaper Burst size. 4447 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4448 * Range is: 5..25 (from 2KB..2GB) 4449 * Access: RW 4450 */ 4451 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4452 4453 /* reg_qpsc_ptsc_we 4454 * Write enable to port_to_shaper_credits. 4455 * Access: WO 4456 */ 4457 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4458 4459 /* reg_qpsc_port_to_shaper_credits 4460 * For split ports: range 1..57 4461 * For non-split ports: range 1..112 4462 * Written only when ptsc_we is set. 4463 * Access: RW 4464 */ 4465 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4466 4467 /* reg_qpsc_ing_timestamp_inc 4468 * Ingress timestamp increment. 4469 * 2's complement. 4470 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4471 * value for all ports. 4472 * Same units as used by MTPPTR. 4473 * Access: RW 4474 */ 4475 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4476 4477 /* reg_qpsc_egr_timestamp_inc 4478 * Egress timestamp increment. 4479 * 2's complement. 4480 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4481 * value for all ports. 4482 * Same units as used by MTPPTR. 4483 * Access: RW 4484 */ 4485 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4486 4487 static inline void 4488 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4489 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4490 u8 shaper_bs, u8 port_to_shaper_credits, 4491 int ing_timestamp_inc, int egr_timestamp_inc) 4492 { 4493 MLXSW_REG_ZERO(qpsc, payload); 4494 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4495 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4496 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4497 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4498 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4499 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4500 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4501 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4502 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4503 } 4504 4505 /* PMLP - Ports Module to Local Port Register 4506 * ------------------------------------------ 4507 * Configures the assignment of modules to local ports. 4508 */ 4509 #define MLXSW_REG_PMLP_ID 0x5002 4510 #define MLXSW_REG_PMLP_LEN 0x40 4511 4512 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4513 4514 /* reg_pmlp_rxtx 4515 * 0 - Tx value is used for both Tx and Rx. 4516 * 1 - Rx value is taken from a separte field. 4517 * Access: RW 4518 */ 4519 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4520 4521 /* reg_pmlp_local_port 4522 * Local port number. 4523 * Access: Index 4524 */ 4525 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4526 4527 /* reg_pmlp_width 4528 * 0 - Unmap local port. 4529 * 1 - Lane 0 is used. 4530 * 2 - Lanes 0 and 1 are used. 4531 * 4 - Lanes 0, 1, 2 and 3 are used. 4532 * 8 - Lanes 0-7 are used. 4533 * Access: RW 4534 */ 4535 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4536 4537 /* reg_pmlp_module 4538 * Module number. 4539 * Access: RW 4540 */ 4541 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4542 4543 /* reg_pmlp_slot_index 4544 * Module number. 4545 * Slot_index 4546 * Slot_index = 0 represent the onboard (motherboard). 4547 * In case of non-modular system only slot_index = 0 is available. 4548 * Access: RW 4549 */ 4550 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4551 4552 /* reg_pmlp_tx_lane 4553 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4554 * Access: RW 4555 */ 4556 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4557 4558 /* reg_pmlp_rx_lane 4559 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4560 * equal to Tx lane. 4561 * Access: RW 4562 */ 4563 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4564 4565 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4566 { 4567 MLXSW_REG_ZERO(pmlp, payload); 4568 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4569 } 4570 4571 /* PMTU - Port MTU Register 4572 * ------------------------ 4573 * Configures and reports the port MTU. 4574 */ 4575 #define MLXSW_REG_PMTU_ID 0x5003 4576 #define MLXSW_REG_PMTU_LEN 0x10 4577 4578 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4579 4580 /* reg_pmtu_local_port 4581 * Local port number. 4582 * Access: Index 4583 */ 4584 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4585 4586 /* reg_pmtu_max_mtu 4587 * Maximum MTU. 4588 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4589 * reported, otherwise the minimum between the max_mtu of the different 4590 * types is reported. 4591 * Access: RO 4592 */ 4593 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4594 4595 /* reg_pmtu_admin_mtu 4596 * MTU value to set port to. Must be smaller or equal to max_mtu. 4597 * Note: If port type is Infiniband, then port must be disabled, when its 4598 * MTU is set. 4599 * Access: RW 4600 */ 4601 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4602 4603 /* reg_pmtu_oper_mtu 4604 * The actual MTU configured on the port. Packets exceeding this size 4605 * will be dropped. 4606 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4607 * oper_mtu might be smaller than admin_mtu. 4608 * Access: RO 4609 */ 4610 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4611 4612 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4613 u16 new_mtu) 4614 { 4615 MLXSW_REG_ZERO(pmtu, payload); 4616 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4617 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4618 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4619 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4620 } 4621 4622 /* PTYS - Port Type and Speed Register 4623 * ----------------------------------- 4624 * Configures and reports the port speed type. 4625 * 4626 * Note: When set while the link is up, the changes will not take effect 4627 * until the port transitions from down to up state. 4628 */ 4629 #define MLXSW_REG_PTYS_ID 0x5004 4630 #define MLXSW_REG_PTYS_LEN 0x40 4631 4632 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4633 4634 /* an_disable_admin 4635 * Auto negotiation disable administrative configuration 4636 * 0 - Device doesn't support AN disable. 4637 * 1 - Device supports AN disable. 4638 * Access: RW 4639 */ 4640 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4641 4642 /* reg_ptys_local_port 4643 * Local port number. 4644 * Access: Index 4645 */ 4646 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4647 4648 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4649 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4650 4651 /* reg_ptys_proto_mask 4652 * Protocol mask. Indicates which protocol is used. 4653 * 0 - Infiniband. 4654 * 1 - Fibre Channel. 4655 * 2 - Ethernet. 4656 * Access: Index 4657 */ 4658 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4659 4660 enum { 4661 MLXSW_REG_PTYS_AN_STATUS_NA, 4662 MLXSW_REG_PTYS_AN_STATUS_OK, 4663 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4664 }; 4665 4666 /* reg_ptys_an_status 4667 * Autonegotiation status. 4668 * Access: RO 4669 */ 4670 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4671 4672 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4673 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4674 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4675 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4676 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4677 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4678 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4679 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4680 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4681 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4682 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4683 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4684 4685 /* reg_ptys_ext_eth_proto_cap 4686 * Extended Ethernet port supported speeds and protocols. 4687 * Access: RO 4688 */ 4689 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4690 4691 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4692 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4693 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4694 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4695 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4696 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4697 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4698 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4699 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4700 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4701 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4702 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4703 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4704 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4705 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4706 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4707 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4708 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4709 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4710 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4711 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4712 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4713 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4714 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4715 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4716 4717 /* reg_ptys_eth_proto_cap 4718 * Ethernet port supported speeds and protocols. 4719 * Access: RO 4720 */ 4721 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4722 4723 /* reg_ptys_ib_link_width_cap 4724 * IB port supported widths. 4725 * Access: RO 4726 */ 4727 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4728 4729 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4730 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4731 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4732 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4733 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4734 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4735 4736 /* reg_ptys_ib_proto_cap 4737 * IB port supported speeds and protocols. 4738 * Access: RO 4739 */ 4740 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4741 4742 /* reg_ptys_ext_eth_proto_admin 4743 * Extended speed and protocol to set port to. 4744 * Access: RW 4745 */ 4746 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4747 4748 /* reg_ptys_eth_proto_admin 4749 * Speed and protocol to set port to. 4750 * Access: RW 4751 */ 4752 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4753 4754 /* reg_ptys_ib_link_width_admin 4755 * IB width to set port to. 4756 * Access: RW 4757 */ 4758 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4759 4760 /* reg_ptys_ib_proto_admin 4761 * IB speeds and protocols to set port to. 4762 * Access: RW 4763 */ 4764 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4765 4766 /* reg_ptys_ext_eth_proto_oper 4767 * The extended current speed and protocol configured for the port. 4768 * Access: RO 4769 */ 4770 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4771 4772 /* reg_ptys_eth_proto_oper 4773 * The current speed and protocol configured for the port. 4774 * Access: RO 4775 */ 4776 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4777 4778 /* reg_ptys_ib_link_width_oper 4779 * The current IB width to set port to. 4780 * Access: RO 4781 */ 4782 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4783 4784 /* reg_ptys_ib_proto_oper 4785 * The current IB speed and protocol. 4786 * Access: RO 4787 */ 4788 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4789 4790 enum mlxsw_reg_ptys_connector_type { 4791 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4792 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4793 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4794 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4795 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4796 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4797 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4798 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4799 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4800 }; 4801 4802 /* reg_ptys_connector_type 4803 * Connector type indication. 4804 * Access: RO 4805 */ 4806 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4807 4808 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4809 u32 proto_admin, bool autoneg) 4810 { 4811 MLXSW_REG_ZERO(ptys, payload); 4812 mlxsw_reg_ptys_local_port_set(payload, local_port); 4813 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4814 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4815 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4816 } 4817 4818 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4819 u32 proto_admin, bool autoneg) 4820 { 4821 MLXSW_REG_ZERO(ptys, payload); 4822 mlxsw_reg_ptys_local_port_set(payload, local_port); 4823 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4824 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4825 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4826 } 4827 4828 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4829 u32 *p_eth_proto_cap, 4830 u32 *p_eth_proto_admin, 4831 u32 *p_eth_proto_oper) 4832 { 4833 if (p_eth_proto_cap) 4834 *p_eth_proto_cap = 4835 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4836 if (p_eth_proto_admin) 4837 *p_eth_proto_admin = 4838 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4839 if (p_eth_proto_oper) 4840 *p_eth_proto_oper = 4841 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4842 } 4843 4844 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4845 u32 *p_eth_proto_cap, 4846 u32 *p_eth_proto_admin, 4847 u32 *p_eth_proto_oper) 4848 { 4849 if (p_eth_proto_cap) 4850 *p_eth_proto_cap = 4851 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4852 if (p_eth_proto_admin) 4853 *p_eth_proto_admin = 4854 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4855 if (p_eth_proto_oper) 4856 *p_eth_proto_oper = 4857 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4858 } 4859 4860 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port, 4861 u16 proto_admin, u16 link_width) 4862 { 4863 MLXSW_REG_ZERO(ptys, payload); 4864 mlxsw_reg_ptys_local_port_set(payload, local_port); 4865 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4866 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4867 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4868 } 4869 4870 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4871 u16 *p_ib_link_width_cap, 4872 u16 *p_ib_proto_oper, 4873 u16 *p_ib_link_width_oper) 4874 { 4875 if (p_ib_proto_cap) 4876 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4877 if (p_ib_link_width_cap) 4878 *p_ib_link_width_cap = 4879 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4880 if (p_ib_proto_oper) 4881 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4882 if (p_ib_link_width_oper) 4883 *p_ib_link_width_oper = 4884 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4885 } 4886 4887 /* PPAD - Port Physical Address Register 4888 * ------------------------------------- 4889 * The PPAD register configures the per port physical MAC address. 4890 */ 4891 #define MLXSW_REG_PPAD_ID 0x5005 4892 #define MLXSW_REG_PPAD_LEN 0x10 4893 4894 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4895 4896 /* reg_ppad_single_base_mac 4897 * 0: base_mac, local port should be 0 and mac[7:0] is 4898 * reserved. HW will set incremental 4899 * 1: single_mac - mac of the local_port 4900 * Access: RW 4901 */ 4902 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4903 4904 /* reg_ppad_local_port 4905 * port number, if single_base_mac = 0 then local_port is reserved 4906 * Access: RW 4907 */ 4908 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4909 4910 /* reg_ppad_mac 4911 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4912 * If single_base_mac = 1 - the per port MAC address 4913 * Access: RW 4914 */ 4915 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4916 4917 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4918 u16 local_port) 4919 { 4920 MLXSW_REG_ZERO(ppad, payload); 4921 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4922 mlxsw_reg_ppad_local_port_set(payload, local_port); 4923 } 4924 4925 /* PAOS - Ports Administrative and Operational Status Register 4926 * ----------------------------------------------------------- 4927 * Configures and retrieves per port administrative and operational status. 4928 */ 4929 #define MLXSW_REG_PAOS_ID 0x5006 4930 #define MLXSW_REG_PAOS_LEN 0x10 4931 4932 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4933 4934 /* reg_paos_swid 4935 * Switch partition ID with which to associate the port. 4936 * Note: while external ports uses unique local port numbers (and thus swid is 4937 * redundant), router ports use the same local port number where swid is the 4938 * only indication for the relevant port. 4939 * Access: Index 4940 */ 4941 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4942 4943 /* reg_paos_local_port 4944 * Local port number. 4945 * Access: Index 4946 */ 4947 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4948 4949 /* reg_paos_admin_status 4950 * Port administrative state (the desired state of the port): 4951 * 1 - Up. 4952 * 2 - Down. 4953 * 3 - Up once. This means that in case of link failure, the port won't go 4954 * into polling mode, but will wait to be re-enabled by software. 4955 * 4 - Disabled by system. Can only be set by hardware. 4956 * Access: RW 4957 */ 4958 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4959 4960 /* reg_paos_oper_status 4961 * Port operational state (the current state): 4962 * 1 - Up. 4963 * 2 - Down. 4964 * 3 - Down by port failure. This means that the device will not let the 4965 * port up again until explicitly specified by software. 4966 * Access: RO 4967 */ 4968 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4969 4970 /* reg_paos_ase 4971 * Admin state update enabled. 4972 * Access: WO 4973 */ 4974 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4975 4976 /* reg_paos_ee 4977 * Event update enable. If this bit is set, event generation will be 4978 * updated based on the e field. 4979 * Access: WO 4980 */ 4981 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4982 4983 /* reg_paos_e 4984 * Event generation on operational state change: 4985 * 0 - Do not generate event. 4986 * 1 - Generate Event. 4987 * 2 - Generate Single Event. 4988 * Access: RW 4989 */ 4990 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4991 4992 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4993 enum mlxsw_port_admin_status status) 4994 { 4995 MLXSW_REG_ZERO(paos, payload); 4996 mlxsw_reg_paos_swid_set(payload, 0); 4997 mlxsw_reg_paos_local_port_set(payload, local_port); 4998 mlxsw_reg_paos_admin_status_set(payload, status); 4999 mlxsw_reg_paos_oper_status_set(payload, 0); 5000 mlxsw_reg_paos_ase_set(payload, 1); 5001 mlxsw_reg_paos_ee_set(payload, 1); 5002 mlxsw_reg_paos_e_set(payload, 1); 5003 } 5004 5005 /* PFCC - Ports Flow Control Configuration Register 5006 * ------------------------------------------------ 5007 * Configures and retrieves the per port flow control configuration. 5008 */ 5009 #define MLXSW_REG_PFCC_ID 0x5007 5010 #define MLXSW_REG_PFCC_LEN 0x20 5011 5012 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 5013 5014 /* reg_pfcc_local_port 5015 * Local port number. 5016 * Access: Index 5017 */ 5018 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 5019 5020 /* reg_pfcc_pnat 5021 * Port number access type. Determines the way local_port is interpreted: 5022 * 0 - Local port number. 5023 * 1 - IB / label port number. 5024 * Access: Index 5025 */ 5026 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 5027 5028 /* reg_pfcc_shl_cap 5029 * Send to higher layers capabilities: 5030 * 0 - No capability of sending Pause and PFC frames to higher layers. 5031 * 1 - Device has capability of sending Pause and PFC frames to higher 5032 * layers. 5033 * Access: RO 5034 */ 5035 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 5036 5037 /* reg_pfcc_shl_opr 5038 * Send to higher layers operation: 5039 * 0 - Pause and PFC frames are handled by the port (default). 5040 * 1 - Pause and PFC frames are handled by the port and also sent to 5041 * higher layers. Only valid if shl_cap = 1. 5042 * Access: RW 5043 */ 5044 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 5045 5046 /* reg_pfcc_ppan 5047 * Pause policy auto negotiation. 5048 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 5049 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 5050 * based on the auto-negotiation resolution. 5051 * Access: RW 5052 * 5053 * Note: The auto-negotiation advertisement is set according to pptx and 5054 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 5055 */ 5056 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 5057 5058 /* reg_pfcc_prio_mask_tx 5059 * Bit per priority indicating if Tx flow control policy should be 5060 * updated based on bit pfctx. 5061 * Access: WO 5062 */ 5063 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 5064 5065 /* reg_pfcc_prio_mask_rx 5066 * Bit per priority indicating if Rx flow control policy should be 5067 * updated based on bit pfcrx. 5068 * Access: WO 5069 */ 5070 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 5071 5072 /* reg_pfcc_pptx 5073 * Admin Pause policy on Tx. 5074 * 0 - Never generate Pause frames (default). 5075 * 1 - Generate Pause frames according to Rx buffer threshold. 5076 * Access: RW 5077 */ 5078 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 5079 5080 /* reg_pfcc_aptx 5081 * Active (operational) Pause policy on Tx. 5082 * 0 - Never generate Pause frames. 5083 * 1 - Generate Pause frames according to Rx buffer threshold. 5084 * Access: RO 5085 */ 5086 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 5087 5088 /* reg_pfcc_pfctx 5089 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 5090 * 0 - Never generate priority Pause frames on the specified priority 5091 * (default). 5092 * 1 - Generate priority Pause frames according to Rx buffer threshold on 5093 * the specified priority. 5094 * Access: RW 5095 * 5096 * Note: pfctx and pptx must be mutually exclusive. 5097 */ 5098 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 5099 5100 /* reg_pfcc_pprx 5101 * Admin Pause policy on Rx. 5102 * 0 - Ignore received Pause frames (default). 5103 * 1 - Respect received Pause frames. 5104 * Access: RW 5105 */ 5106 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5107 5108 /* reg_pfcc_aprx 5109 * Active (operational) Pause policy on Rx. 5110 * 0 - Ignore received Pause frames. 5111 * 1 - Respect received Pause frames. 5112 * Access: RO 5113 */ 5114 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5115 5116 /* reg_pfcc_pfcrx 5117 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5118 * 0 - Ignore incoming priority Pause frames on the specified priority 5119 * (default). 5120 * 1 - Respect incoming priority Pause frames on the specified priority. 5121 * Access: RW 5122 */ 5123 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5124 5125 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5126 5127 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5128 { 5129 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5130 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5131 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5132 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5133 } 5134 5135 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5136 { 5137 MLXSW_REG_ZERO(pfcc, payload); 5138 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5139 } 5140 5141 /* PPCNT - Ports Performance Counters Register 5142 * ------------------------------------------- 5143 * The PPCNT register retrieves per port performance counters. 5144 */ 5145 #define MLXSW_REG_PPCNT_ID 0x5008 5146 #define MLXSW_REG_PPCNT_LEN 0x100 5147 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5148 5149 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5150 5151 /* reg_ppcnt_swid 5152 * For HCA: must be always 0. 5153 * Switch partition ID to associate port with. 5154 * Switch partitions are numbered from 0 to 7 inclusively. 5155 * Switch partition 254 indicates stacking ports. 5156 * Switch partition 255 indicates all switch partitions. 5157 * Only valid on Set() operation with local_port=255. 5158 * Access: Index 5159 */ 5160 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5161 5162 /* reg_ppcnt_local_port 5163 * Local port number. 5164 * Access: Index 5165 */ 5166 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5167 5168 /* reg_ppcnt_pnat 5169 * Port number access type: 5170 * 0 - Local port number 5171 * 1 - IB port number 5172 * Access: Index 5173 */ 5174 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5175 5176 enum mlxsw_reg_ppcnt_grp { 5177 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5178 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5179 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5180 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5181 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5182 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5183 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5184 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5185 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5186 }; 5187 5188 /* reg_ppcnt_grp 5189 * Performance counter group. 5190 * Group 63 indicates all groups. Only valid on Set() operation with 5191 * clr bit set. 5192 * 0x0: IEEE 802.3 Counters 5193 * 0x1: RFC 2863 Counters 5194 * 0x2: RFC 2819 Counters 5195 * 0x3: RFC 3635 Counters 5196 * 0x5: Ethernet Extended Counters 5197 * 0x6: Ethernet Discard Counters 5198 * 0x8: Link Level Retransmission Counters 5199 * 0x10: Per Priority Counters 5200 * 0x11: Per Traffic Class Counters 5201 * 0x12: Physical Layer Counters 5202 * 0x13: Per Traffic Class Congestion Counters 5203 * Access: Index 5204 */ 5205 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5206 5207 /* reg_ppcnt_clr 5208 * Clear counters. Setting the clr bit will reset the counter value 5209 * for all counters in the counter group. This bit can be set 5210 * for both Set() and Get() operation. 5211 * Access: OP 5212 */ 5213 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5214 5215 /* reg_ppcnt_lp_gl 5216 * Local port global variable. 5217 * 0: local_port 255 = all ports of the device. 5218 * 1: local_port indicates local port number for all ports. 5219 * Access: OP 5220 */ 5221 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5222 5223 /* reg_ppcnt_prio_tc 5224 * Priority for counter set that support per priority, valid values: 0-7. 5225 * Traffic class for counter set that support per traffic class, 5226 * valid values: 0- cap_max_tclass-1 . 5227 * For HCA: cap_max_tclass is always 8. 5228 * Otherwise must be 0. 5229 * Access: Index 5230 */ 5231 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5232 5233 /* Ethernet IEEE 802.3 Counter Group */ 5234 5235 /* reg_ppcnt_a_frames_transmitted_ok 5236 * Access: RO 5237 */ 5238 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5239 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5240 5241 /* reg_ppcnt_a_frames_received_ok 5242 * Access: RO 5243 */ 5244 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5245 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5246 5247 /* reg_ppcnt_a_frame_check_sequence_errors 5248 * Access: RO 5249 */ 5250 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5251 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5252 5253 /* reg_ppcnt_a_alignment_errors 5254 * Access: RO 5255 */ 5256 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5257 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5258 5259 /* reg_ppcnt_a_octets_transmitted_ok 5260 * Access: RO 5261 */ 5262 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5263 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5264 5265 /* reg_ppcnt_a_octets_received_ok 5266 * Access: RO 5267 */ 5268 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5269 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5270 5271 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5272 * Access: RO 5273 */ 5274 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5275 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5276 5277 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5278 * Access: RO 5279 */ 5280 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5281 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5282 5283 /* reg_ppcnt_a_multicast_frames_received_ok 5284 * Access: RO 5285 */ 5286 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5287 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5288 5289 /* reg_ppcnt_a_broadcast_frames_received_ok 5290 * Access: RO 5291 */ 5292 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5293 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5294 5295 /* reg_ppcnt_a_in_range_length_errors 5296 * Access: RO 5297 */ 5298 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5299 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5300 5301 /* reg_ppcnt_a_out_of_range_length_field 5302 * Access: RO 5303 */ 5304 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5305 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5306 5307 /* reg_ppcnt_a_frame_too_long_errors 5308 * Access: RO 5309 */ 5310 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5311 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5312 5313 /* reg_ppcnt_a_symbol_error_during_carrier 5314 * Access: RO 5315 */ 5316 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5317 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5318 5319 /* reg_ppcnt_a_mac_control_frames_transmitted 5320 * Access: RO 5321 */ 5322 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5323 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5324 5325 /* reg_ppcnt_a_mac_control_frames_received 5326 * Access: RO 5327 */ 5328 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5329 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5330 5331 /* reg_ppcnt_a_unsupported_opcodes_received 5332 * Access: RO 5333 */ 5334 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5335 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5336 5337 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5338 * Access: RO 5339 */ 5340 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5341 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5342 5343 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5344 * Access: RO 5345 */ 5346 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5347 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5348 5349 /* Ethernet RFC 2863 Counter Group */ 5350 5351 /* reg_ppcnt_if_in_discards 5352 * Access: RO 5353 */ 5354 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5356 5357 /* reg_ppcnt_if_out_discards 5358 * Access: RO 5359 */ 5360 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5361 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5362 5363 /* reg_ppcnt_if_out_errors 5364 * Access: RO 5365 */ 5366 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5367 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5368 5369 /* Ethernet RFC 2819 Counter Group */ 5370 5371 /* reg_ppcnt_ether_stats_undersize_pkts 5372 * Access: RO 5373 */ 5374 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5375 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5376 5377 /* reg_ppcnt_ether_stats_oversize_pkts 5378 * Access: RO 5379 */ 5380 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5381 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5382 5383 /* reg_ppcnt_ether_stats_fragments 5384 * Access: RO 5385 */ 5386 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5387 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5388 5389 /* reg_ppcnt_ether_stats_pkts64octets 5390 * Access: RO 5391 */ 5392 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5393 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5394 5395 /* reg_ppcnt_ether_stats_pkts65to127octets 5396 * Access: RO 5397 */ 5398 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5399 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5400 5401 /* reg_ppcnt_ether_stats_pkts128to255octets 5402 * Access: RO 5403 */ 5404 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5405 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5406 5407 /* reg_ppcnt_ether_stats_pkts256to511octets 5408 * Access: RO 5409 */ 5410 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5411 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5412 5413 /* reg_ppcnt_ether_stats_pkts512to1023octets 5414 * Access: RO 5415 */ 5416 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5417 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5418 5419 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5420 * Access: RO 5421 */ 5422 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5423 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5424 5425 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5426 * Access: RO 5427 */ 5428 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5429 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5430 5431 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5432 * Access: RO 5433 */ 5434 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5435 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5436 5437 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5438 * Access: RO 5439 */ 5440 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5441 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5442 5443 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5444 * Access: RO 5445 */ 5446 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5447 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5448 5449 /* Ethernet RFC 3635 Counter Group */ 5450 5451 /* reg_ppcnt_dot3stats_fcs_errors 5452 * Access: RO 5453 */ 5454 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5455 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5456 5457 /* reg_ppcnt_dot3stats_symbol_errors 5458 * Access: RO 5459 */ 5460 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5462 5463 /* reg_ppcnt_dot3control_in_unknown_opcodes 5464 * Access: RO 5465 */ 5466 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5468 5469 /* reg_ppcnt_dot3in_pause_frames 5470 * Access: RO 5471 */ 5472 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5473 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5474 5475 /* Ethernet Extended Counter Group Counters */ 5476 5477 /* reg_ppcnt_ecn_marked 5478 * Access: RO 5479 */ 5480 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5481 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5482 5483 /* Ethernet Discard Counter Group Counters */ 5484 5485 /* reg_ppcnt_ingress_general 5486 * Access: RO 5487 */ 5488 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5489 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5490 5491 /* reg_ppcnt_ingress_policy_engine 5492 * Access: RO 5493 */ 5494 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5495 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5496 5497 /* reg_ppcnt_ingress_vlan_membership 5498 * Access: RO 5499 */ 5500 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5501 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5502 5503 /* reg_ppcnt_ingress_tag_frame_type 5504 * Access: RO 5505 */ 5506 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5507 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5508 5509 /* reg_ppcnt_egress_vlan_membership 5510 * Access: RO 5511 */ 5512 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5513 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5514 5515 /* reg_ppcnt_loopback_filter 5516 * Access: RO 5517 */ 5518 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5519 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5520 5521 /* reg_ppcnt_egress_general 5522 * Access: RO 5523 */ 5524 MLXSW_ITEM64(reg, ppcnt, egress_general, 5525 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5526 5527 /* reg_ppcnt_egress_hoq 5528 * Access: RO 5529 */ 5530 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5531 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5532 5533 /* reg_ppcnt_egress_policy_engine 5534 * Access: RO 5535 */ 5536 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5537 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5538 5539 /* reg_ppcnt_ingress_tx_link_down 5540 * Access: RO 5541 */ 5542 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5543 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5544 5545 /* reg_ppcnt_egress_stp_filter 5546 * Access: RO 5547 */ 5548 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5549 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5550 5551 /* reg_ppcnt_egress_sll 5552 * Access: RO 5553 */ 5554 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5555 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5556 5557 /* Ethernet Per Priority Group Counters */ 5558 5559 /* reg_ppcnt_rx_octets 5560 * Access: RO 5561 */ 5562 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5563 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5564 5565 /* reg_ppcnt_rx_frames 5566 * Access: RO 5567 */ 5568 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5569 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5570 5571 /* reg_ppcnt_tx_octets 5572 * Access: RO 5573 */ 5574 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5575 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5576 5577 /* reg_ppcnt_tx_frames 5578 * Access: RO 5579 */ 5580 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5581 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5582 5583 /* reg_ppcnt_rx_pause 5584 * Access: RO 5585 */ 5586 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5587 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5588 5589 /* reg_ppcnt_rx_pause_duration 5590 * Access: RO 5591 */ 5592 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5593 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5594 5595 /* reg_ppcnt_tx_pause 5596 * Access: RO 5597 */ 5598 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5599 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5600 5601 /* reg_ppcnt_tx_pause_duration 5602 * Access: RO 5603 */ 5604 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5605 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5606 5607 /* reg_ppcnt_rx_pause_transition 5608 * Access: RO 5609 */ 5610 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5611 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5612 5613 /* Ethernet Per Traffic Class Counters */ 5614 5615 /* reg_ppcnt_tc_transmit_queue 5616 * Contains the transmit queue depth in cells of traffic class 5617 * selected by prio_tc and the port selected by local_port. 5618 * The field cannot be cleared. 5619 * Access: RO 5620 */ 5621 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5622 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5623 5624 /* reg_ppcnt_tc_no_buffer_discard_uc 5625 * The number of unicast packets dropped due to lack of shared 5626 * buffer resources. 5627 * Access: RO 5628 */ 5629 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5630 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5631 5632 /* Ethernet Per Traffic Class Congestion Group Counters */ 5633 5634 /* reg_ppcnt_wred_discard 5635 * Access: RO 5636 */ 5637 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5638 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5639 5640 /* reg_ppcnt_ecn_marked_tc 5641 * Access: RO 5642 */ 5643 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5644 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5645 5646 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5647 enum mlxsw_reg_ppcnt_grp grp, 5648 u8 prio_tc) 5649 { 5650 MLXSW_REG_ZERO(ppcnt, payload); 5651 mlxsw_reg_ppcnt_swid_set(payload, 0); 5652 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5653 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5654 mlxsw_reg_ppcnt_grp_set(payload, grp); 5655 mlxsw_reg_ppcnt_clr_set(payload, 0); 5656 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5657 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5658 } 5659 5660 /* PLIB - Port Local to InfiniBand Port 5661 * ------------------------------------ 5662 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5663 */ 5664 #define MLXSW_REG_PLIB_ID 0x500A 5665 #define MLXSW_REG_PLIB_LEN 0x10 5666 5667 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5668 5669 /* reg_plib_local_port 5670 * Local port number. 5671 * Access: Index 5672 */ 5673 MLXSW_ITEM32_LP(reg, plib, 0x00, 16, 0x00, 12); 5674 5675 /* reg_plib_ib_port 5676 * InfiniBand port remapping for local_port. 5677 * Access: RW 5678 */ 5679 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5680 5681 /* PPTB - Port Prio To Buffer Register 5682 * ----------------------------------- 5683 * Configures the switch priority to buffer table. 5684 */ 5685 #define MLXSW_REG_PPTB_ID 0x500B 5686 #define MLXSW_REG_PPTB_LEN 0x10 5687 5688 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5689 5690 enum { 5691 MLXSW_REG_PPTB_MM_UM, 5692 MLXSW_REG_PPTB_MM_UNICAST, 5693 MLXSW_REG_PPTB_MM_MULTICAST, 5694 }; 5695 5696 /* reg_pptb_mm 5697 * Mapping mode. 5698 * 0 - Map both unicast and multicast packets to the same buffer. 5699 * 1 - Map only unicast packets. 5700 * 2 - Map only multicast packets. 5701 * Access: Index 5702 * 5703 * Note: SwitchX-2 only supports the first option. 5704 */ 5705 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5706 5707 /* reg_pptb_local_port 5708 * Local port number. 5709 * Access: Index 5710 */ 5711 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5712 5713 /* reg_pptb_um 5714 * Enables the update of the untagged_buf field. 5715 * Access: RW 5716 */ 5717 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5718 5719 /* reg_pptb_pm 5720 * Enables the update of the prio_to_buff field. 5721 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5722 * Access: RW 5723 */ 5724 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5725 5726 /* reg_pptb_prio_to_buff 5727 * Mapping of switch priority <i> to one of the allocated receive port 5728 * buffers. 5729 * Access: RW 5730 */ 5731 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5732 5733 /* reg_pptb_pm_msb 5734 * Enables the update of the prio_to_buff field. 5735 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5736 * Access: RW 5737 */ 5738 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5739 5740 /* reg_pptb_untagged_buff 5741 * Mapping of untagged frames to one of the allocated receive port buffers. 5742 * Access: RW 5743 * 5744 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5745 * Spectrum, as it maps untagged packets based on the default switch priority. 5746 */ 5747 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5748 5749 /* reg_pptb_prio_to_buff_msb 5750 * Mapping of switch priority <i+8> to one of the allocated receive port 5751 * buffers. 5752 * Access: RW 5753 */ 5754 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5755 5756 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5757 5758 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5759 { 5760 MLXSW_REG_ZERO(pptb, payload); 5761 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5762 mlxsw_reg_pptb_local_port_set(payload, local_port); 5763 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5764 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5765 } 5766 5767 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5768 u8 buff) 5769 { 5770 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5771 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5772 } 5773 5774 /* PBMC - Port Buffer Management Control Register 5775 * ---------------------------------------------- 5776 * The PBMC register configures and retrieves the port packet buffer 5777 * allocation for different Prios, and the Pause threshold management. 5778 */ 5779 #define MLXSW_REG_PBMC_ID 0x500C 5780 #define MLXSW_REG_PBMC_LEN 0x6C 5781 5782 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5783 5784 /* reg_pbmc_local_port 5785 * Local port number. 5786 * Access: Index 5787 */ 5788 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5789 5790 /* reg_pbmc_xoff_timer_value 5791 * When device generates a pause frame, it uses this value as the pause 5792 * timer (time for the peer port to pause in quota-512 bit time). 5793 * Access: RW 5794 */ 5795 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5796 5797 /* reg_pbmc_xoff_refresh 5798 * The time before a new pause frame should be sent to refresh the pause RW 5799 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5800 * time). 5801 * Access: RW 5802 */ 5803 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5804 5805 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5806 5807 /* reg_pbmc_buf_lossy 5808 * The field indicates if the buffer is lossy. 5809 * 0 - Lossless 5810 * 1 - Lossy 5811 * Access: RW 5812 */ 5813 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5814 5815 /* reg_pbmc_buf_epsb 5816 * Eligible for Port Shared buffer. 5817 * If epsb is set, packets assigned to buffer are allowed to insert the port 5818 * shared buffer. 5819 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5820 * Access: RW 5821 */ 5822 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5823 5824 /* reg_pbmc_buf_size 5825 * The part of the packet buffer array is allocated for the specific buffer. 5826 * Units are represented in cells. 5827 * Access: RW 5828 */ 5829 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5830 5831 /* reg_pbmc_buf_xoff_threshold 5832 * Once the amount of data in the buffer goes above this value, device 5833 * starts sending PFC frames for all priorities associated with the 5834 * buffer. Units are represented in cells. Reserved in case of lossy 5835 * buffer. 5836 * Access: RW 5837 * 5838 * Note: In Spectrum, reserved for buffer[9]. 5839 */ 5840 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5841 0x08, 0x04, false); 5842 5843 /* reg_pbmc_buf_xon_threshold 5844 * When the amount of data in the buffer goes below this value, device 5845 * stops sending PFC frames for the priorities associated with the 5846 * buffer. Units are represented in cells. Reserved in case of lossy 5847 * buffer. 5848 * Access: RW 5849 * 5850 * Note: In Spectrum, reserved for buffer[9]. 5851 */ 5852 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5853 0x08, 0x04, false); 5854 5855 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5856 u16 xoff_timer_value, u16 xoff_refresh) 5857 { 5858 MLXSW_REG_ZERO(pbmc, payload); 5859 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5860 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5861 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5862 } 5863 5864 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5865 int buf_index, 5866 u16 size) 5867 { 5868 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5869 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5870 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5871 } 5872 5873 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5874 int buf_index, u16 size, 5875 u16 threshold) 5876 { 5877 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5878 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5879 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5880 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5881 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5882 } 5883 5884 /* PSPA - Port Switch Partition Allocation 5885 * --------------------------------------- 5886 * Controls the association of a port with a switch partition and enables 5887 * configuring ports as stacking ports. 5888 */ 5889 #define MLXSW_REG_PSPA_ID 0x500D 5890 #define MLXSW_REG_PSPA_LEN 0x8 5891 5892 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5893 5894 /* reg_pspa_swid 5895 * Switch partition ID. 5896 * Access: RW 5897 */ 5898 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5899 5900 /* reg_pspa_local_port 5901 * Local port number. 5902 * Access: Index 5903 */ 5904 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5905 5906 /* reg_pspa_sub_port 5907 * Virtual port within the local port. Set to 0 when virtual ports are 5908 * disabled on the local port. 5909 * Access: Index 5910 */ 5911 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5912 5913 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5914 { 5915 MLXSW_REG_ZERO(pspa, payload); 5916 mlxsw_reg_pspa_swid_set(payload, swid); 5917 mlxsw_reg_pspa_local_port_set(payload, local_port); 5918 mlxsw_reg_pspa_sub_port_set(payload, 0); 5919 } 5920 5921 /* PMAOS - Ports Module Administrative and Operational Status 5922 * ---------------------------------------------------------- 5923 * This register configures and retrieves the per module status. 5924 */ 5925 #define MLXSW_REG_PMAOS_ID 0x5012 5926 #define MLXSW_REG_PMAOS_LEN 0x10 5927 5928 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5929 5930 /* reg_pmaos_rst 5931 * Module reset toggle. 5932 * Note: Setting reset while module is plugged-in will result in transition to 5933 * "initializing" operational state. 5934 * Access: OP 5935 */ 5936 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5937 5938 /* reg_pmaos_slot_index 5939 * Slot index. 5940 * Access: Index 5941 */ 5942 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5943 5944 /* reg_pmaos_module 5945 * Module number. 5946 * Access: Index 5947 */ 5948 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5949 5950 enum mlxsw_reg_pmaos_admin_status { 5951 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5952 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5953 /* If the module is active and then unplugged, or experienced an error 5954 * event, the operational status should go to "disabled" and can only 5955 * be enabled upon explicit enable command. 5956 */ 5957 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5958 }; 5959 5960 /* reg_pmaos_admin_status 5961 * Module administrative state (the desired state of the module). 5962 * Note: To disable a module, all ports associated with the port must be 5963 * administatively down first. 5964 * Access: RW 5965 */ 5966 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5967 5968 /* reg_pmaos_ase 5969 * Admin state update enable. 5970 * If this bit is set, admin state will be updated based on admin_state field. 5971 * Only relevant on Set() operations. 5972 * Access: WO 5973 */ 5974 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5975 5976 /* reg_pmaos_ee 5977 * Event update enable. 5978 * If this bit is set, event generation will be updated based on the e field. 5979 * Only relevant on Set operations. 5980 * Access: WO 5981 */ 5982 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5983 5984 enum mlxsw_reg_pmaos_e { 5985 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5986 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5987 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5988 }; 5989 5990 /* reg_pmaos_e 5991 * Event Generation on operational state change. 5992 * Access: RW 5993 */ 5994 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5995 5996 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5997 { 5998 MLXSW_REG_ZERO(pmaos, payload); 5999 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 6000 mlxsw_reg_pmaos_module_set(payload, module); 6001 } 6002 6003 /* PPLR - Port Physical Loopback Register 6004 * -------------------------------------- 6005 * This register allows configuration of the port's loopback mode. 6006 */ 6007 #define MLXSW_REG_PPLR_ID 0x5018 6008 #define MLXSW_REG_PPLR_LEN 0x8 6009 6010 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 6011 6012 /* reg_pplr_local_port 6013 * Local port number. 6014 * Access: Index 6015 */ 6016 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 6017 6018 /* Phy local loopback. When set the port's egress traffic is looped back 6019 * to the receiver and the port transmitter is disabled. 6020 */ 6021 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 6022 6023 /* reg_pplr_lb_en 6024 * Loopback enable. 6025 * Access: RW 6026 */ 6027 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 6028 6029 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 6030 bool phy_local) 6031 { 6032 MLXSW_REG_ZERO(pplr, payload); 6033 mlxsw_reg_pplr_local_port_set(payload, local_port); 6034 mlxsw_reg_pplr_lb_en_set(payload, 6035 phy_local ? 6036 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 6037 } 6038 6039 /* PMTDB - Port Module To local DataBase Register 6040 * ---------------------------------------------- 6041 * The PMTDB register allows to query the possible module<->local port 6042 * mapping than can be used in PMLP. It does not represent the actual/current 6043 * mapping of the local to module. Actual mapping is only defined by PMLP. 6044 */ 6045 #define MLXSW_REG_PMTDB_ID 0x501A 6046 #define MLXSW_REG_PMTDB_LEN 0x40 6047 6048 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 6049 6050 /* reg_pmtdb_slot_index 6051 * Slot index (0: Main board). 6052 * Access: Index 6053 */ 6054 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 6055 6056 /* reg_pmtdb_module 6057 * Module number. 6058 * Access: Index 6059 */ 6060 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 6061 6062 /* reg_pmtdb_ports_width 6063 * Port's width 6064 * Access: Index 6065 */ 6066 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 6067 6068 /* reg_pmtdb_num_ports 6069 * Number of ports in a single module (split/breakout) 6070 * Access: Index 6071 */ 6072 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 6073 6074 enum mlxsw_reg_pmtdb_status { 6075 MLXSW_REG_PMTDB_STATUS_SUCCESS, 6076 }; 6077 6078 /* reg_pmtdb_status 6079 * Status 6080 * Access: RO 6081 */ 6082 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 6083 6084 /* reg_pmtdb_port_num 6085 * The local_port value which can be assigned to the module. 6086 * In case of more than one port, port<x> represent the /<x> port of 6087 * the module. 6088 * Access: RO 6089 */ 6090 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 6091 6092 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 6093 u8 ports_width, u8 num_ports) 6094 { 6095 MLXSW_REG_ZERO(pmtdb, payload); 6096 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 6097 mlxsw_reg_pmtdb_module_set(payload, module); 6098 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 6099 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 6100 } 6101 6102 /* PMECR - Ports Mapping Event Configuration Register 6103 * -------------------------------------------------- 6104 * The PMECR register is used to enable/disable event triggering 6105 * in case of local port mapping change. 6106 */ 6107 #define MLXSW_REG_PMECR_ID 0x501B 6108 #define MLXSW_REG_PMECR_LEN 0x20 6109 6110 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 6111 6112 /* reg_pmecr_local_port 6113 * Local port number. 6114 * Access: Index 6115 */ 6116 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 6117 6118 /* reg_pmecr_ee 6119 * Event update enable. If this bit is set, event generation will be updated 6120 * based on the e field. Only relevant on Set operations. 6121 * Access: WO 6122 */ 6123 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 6124 6125 /* reg_pmecr_eswi 6126 * Software ignore enable bit. If this bit is set, the value of swi is used. 6127 * If this bit is clear, the value of swi is ignored. 6128 * Only relevant on Set operations. 6129 * Access: WO 6130 */ 6131 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6132 6133 /* reg_pmecr_swi 6134 * Software ignore. If this bit is set, the device shouldn't generate events 6135 * in case of PMLP SET operation but only upon self local port mapping change 6136 * (if applicable according to e configuration). This is supplementary 6137 * configuration on top of e value. 6138 * Access: RW 6139 */ 6140 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6141 6142 enum mlxsw_reg_pmecr_e { 6143 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6144 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6145 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6146 }; 6147 6148 /* reg_pmecr_e 6149 * Event generation on local port mapping change. 6150 * Access: RW 6151 */ 6152 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6153 6154 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6155 enum mlxsw_reg_pmecr_e e) 6156 { 6157 MLXSW_REG_ZERO(pmecr, payload); 6158 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6159 mlxsw_reg_pmecr_e_set(payload, e); 6160 mlxsw_reg_pmecr_ee_set(payload, true); 6161 mlxsw_reg_pmecr_swi_set(payload, true); 6162 mlxsw_reg_pmecr_eswi_set(payload, true); 6163 } 6164 6165 /* PMPE - Port Module Plug/Unplug Event Register 6166 * --------------------------------------------- 6167 * This register reports any operational status change of a module. 6168 * A change in the module’s state will generate an event only if the change 6169 * happens after arming the event mechanism. Any changes to the module state 6170 * while the event mechanism is not armed will not be reported. Software can 6171 * query the PMPE register for module status. 6172 */ 6173 #define MLXSW_REG_PMPE_ID 0x5024 6174 #define MLXSW_REG_PMPE_LEN 0x10 6175 6176 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6177 6178 /* reg_pmpe_slot_index 6179 * Slot index. 6180 * Access: Index 6181 */ 6182 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6183 6184 /* reg_pmpe_module 6185 * Module number. 6186 * Access: Index 6187 */ 6188 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6189 6190 enum mlxsw_reg_pmpe_module_status { 6191 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6192 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6193 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6194 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6195 }; 6196 6197 /* reg_pmpe_module_status 6198 * Module status. 6199 * Access: RO 6200 */ 6201 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6202 6203 /* reg_pmpe_error_type 6204 * Module error details. 6205 * Access: RO 6206 */ 6207 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6208 6209 /* PDDR - Port Diagnostics Database Register 6210 * ----------------------------------------- 6211 * The PDDR enables to read the Phy debug database 6212 */ 6213 #define MLXSW_REG_PDDR_ID 0x5031 6214 #define MLXSW_REG_PDDR_LEN 0x100 6215 6216 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6217 6218 /* reg_pddr_local_port 6219 * Local port number. 6220 * Access: Index 6221 */ 6222 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6223 6224 enum mlxsw_reg_pddr_page_select { 6225 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6226 }; 6227 6228 /* reg_pddr_page_select 6229 * Page select index. 6230 * Access: Index 6231 */ 6232 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6233 6234 enum mlxsw_reg_pddr_trblsh_group_opcode { 6235 /* Monitor opcodes */ 6236 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6237 }; 6238 6239 /* reg_pddr_group_opcode 6240 * Group selector. 6241 * Access: Index 6242 */ 6243 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6244 6245 /* reg_pddr_status_opcode 6246 * Group selector. 6247 * Access: RO 6248 */ 6249 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6250 6251 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6252 u8 page_select) 6253 { 6254 MLXSW_REG_ZERO(pddr, payload); 6255 mlxsw_reg_pddr_local_port_set(payload, local_port); 6256 mlxsw_reg_pddr_page_select_set(payload, page_select); 6257 } 6258 6259 /* PMMP - Port Module Memory Map Properties Register 6260 * ------------------------------------------------- 6261 * The PMMP register allows to override the module memory map advertisement. 6262 * The register can only be set when the module is disabled by PMAOS register. 6263 */ 6264 #define MLXSW_REG_PMMP_ID 0x5044 6265 #define MLXSW_REG_PMMP_LEN 0x2C 6266 6267 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6268 6269 /* reg_pmmp_module 6270 * Module number. 6271 * Access: Index 6272 */ 6273 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6274 6275 /* reg_pmmp_slot_index 6276 * Slot index. 6277 * Access: Index 6278 */ 6279 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6280 6281 /* reg_pmmp_sticky 6282 * When set, will keep eeprom_override values after plug-out event. 6283 * Access: OP 6284 */ 6285 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6286 6287 /* reg_pmmp_eeprom_override_mask 6288 * Write mask bit (negative polarity). 6289 * 0 - Allow write 6290 * 1 - Ignore write 6291 * On write, indicates which of the bits from eeprom_override field are 6292 * updated. 6293 * Access: WO 6294 */ 6295 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6296 6297 enum { 6298 /* Set module to low power mode */ 6299 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6300 }; 6301 6302 /* reg_pmmp_eeprom_override 6303 * Override / ignore EEPROM advertisement properties bitmask 6304 * Access: RW 6305 */ 6306 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6307 6308 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6309 { 6310 MLXSW_REG_ZERO(pmmp, payload); 6311 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6312 mlxsw_reg_pmmp_module_set(payload, module); 6313 } 6314 6315 /* PLLP - Port Local port to Label Port mapping Register 6316 * ----------------------------------------------------- 6317 * The PLLP register returns the mapping from Local Port into Label Port. 6318 */ 6319 #define MLXSW_REG_PLLP_ID 0x504A 6320 #define MLXSW_REG_PLLP_LEN 0x10 6321 6322 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6323 6324 /* reg_pllp_local_port 6325 * Local port number. 6326 * Access: Index 6327 */ 6328 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6329 6330 /* reg_pllp_label_port 6331 * Front panel label of the port. 6332 * Access: RO 6333 */ 6334 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6335 6336 /* reg_pllp_split_num 6337 * Label split mapping for local_port. 6338 * Access: RO 6339 */ 6340 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6341 6342 /* reg_pllp_slot_index 6343 * Slot index (0: Main board). 6344 * Access: RO 6345 */ 6346 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6347 6348 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6349 { 6350 MLXSW_REG_ZERO(pllp, payload); 6351 mlxsw_reg_pllp_local_port_set(payload, local_port); 6352 } 6353 6354 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6355 u8 *split_num, u8 *slot_index) 6356 { 6357 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6358 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6359 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6360 } 6361 6362 /* PMTM - Port Module Type Mapping Register 6363 * ---------------------------------------- 6364 * The PMTM register allows query or configuration of module types. 6365 * The register can only be set when the module is disabled by PMAOS register 6366 */ 6367 #define MLXSW_REG_PMTM_ID 0x5067 6368 #define MLXSW_REG_PMTM_LEN 0x10 6369 6370 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6371 6372 /* reg_pmtm_slot_index 6373 * Slot index. 6374 * Access: Index 6375 */ 6376 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6377 6378 /* reg_pmtm_module 6379 * Module number. 6380 * Access: Index 6381 */ 6382 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6383 6384 enum mlxsw_reg_pmtm_module_type { 6385 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6386 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6387 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6388 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6389 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6390 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6391 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6392 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6393 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6394 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6395 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6396 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6397 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6398 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6399 }; 6400 6401 /* reg_pmtm_module_type 6402 * Module type. 6403 * Access: RW 6404 */ 6405 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6406 6407 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6408 { 6409 MLXSW_REG_ZERO(pmtm, payload); 6410 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6411 mlxsw_reg_pmtm_module_set(payload, module); 6412 } 6413 6414 /* HTGT - Host Trap Group Table 6415 * ---------------------------- 6416 * Configures the properties for forwarding to CPU. 6417 */ 6418 #define MLXSW_REG_HTGT_ID 0x7002 6419 #define MLXSW_REG_HTGT_LEN 0x20 6420 6421 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6422 6423 /* reg_htgt_swid 6424 * Switch partition ID. 6425 * Access: Index 6426 */ 6427 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6428 6429 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6430 6431 /* reg_htgt_type 6432 * CPU path type. 6433 * Access: RW 6434 */ 6435 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6436 6437 enum mlxsw_reg_htgt_trap_group { 6438 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6439 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6440 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6441 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6442 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6443 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6444 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6445 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6446 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6447 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6448 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6449 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6450 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6451 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6452 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6453 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6454 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6455 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6456 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6457 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6458 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6459 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6460 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6461 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6462 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6463 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6464 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6465 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6466 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6467 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6468 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6469 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6470 6471 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6472 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6473 }; 6474 6475 /* reg_htgt_trap_group 6476 * Trap group number. User defined number specifying which trap groups 6477 * should be forwarded to the CPU. The mapping between trap IDs and trap 6478 * groups is configured using HPKT register. 6479 * Access: Index 6480 */ 6481 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6482 6483 enum { 6484 MLXSW_REG_HTGT_POLICER_DISABLE, 6485 MLXSW_REG_HTGT_POLICER_ENABLE, 6486 }; 6487 6488 /* reg_htgt_pide 6489 * Enable policer ID specified using 'pid' field. 6490 * Access: RW 6491 */ 6492 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6493 6494 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6495 6496 /* reg_htgt_pid 6497 * Policer ID for the trap group. 6498 * Access: RW 6499 */ 6500 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6501 6502 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6503 6504 /* reg_htgt_mirror_action 6505 * Mirror action to use. 6506 * 0 - Trap to CPU. 6507 * 1 - Trap to CPU and mirror to a mirroring agent. 6508 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6509 * Access: RW 6510 * 6511 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6512 */ 6513 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6514 6515 /* reg_htgt_mirroring_agent 6516 * Mirroring agent. 6517 * Access: RW 6518 */ 6519 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6520 6521 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6522 6523 /* reg_htgt_priority 6524 * Trap group priority. 6525 * In case a packet matches multiple classification rules, the packet will 6526 * only be trapped once, based on the trap ID associated with the group (via 6527 * register HPKT) with the highest priority. 6528 * Supported values are 0-7, with 7 represnting the highest priority. 6529 * Access: RW 6530 * 6531 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6532 * by the 'trap_group' field. 6533 */ 6534 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6535 6536 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6537 6538 /* reg_htgt_local_path_cpu_tclass 6539 * CPU ingress traffic class for the trap group. 6540 * Access: RW 6541 */ 6542 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6543 6544 enum mlxsw_reg_htgt_local_path_rdq { 6545 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6546 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6547 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6548 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6549 }; 6550 /* reg_htgt_local_path_rdq 6551 * Receive descriptor queue (RDQ) to use for the trap group. 6552 * Access: RW 6553 */ 6554 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6555 6556 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6557 u8 priority, u8 tc) 6558 { 6559 MLXSW_REG_ZERO(htgt, payload); 6560 6561 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6562 mlxsw_reg_htgt_pide_set(payload, 6563 MLXSW_REG_HTGT_POLICER_DISABLE); 6564 } else { 6565 mlxsw_reg_htgt_pide_set(payload, 6566 MLXSW_REG_HTGT_POLICER_ENABLE); 6567 mlxsw_reg_htgt_pid_set(payload, policer_id); 6568 } 6569 6570 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6571 mlxsw_reg_htgt_trap_group_set(payload, group); 6572 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6573 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6574 mlxsw_reg_htgt_priority_set(payload, priority); 6575 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6576 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6577 } 6578 6579 /* HPKT - Host Packet Trap 6580 * ----------------------- 6581 * Configures trap IDs inside trap groups. 6582 */ 6583 #define MLXSW_REG_HPKT_ID 0x7003 6584 #define MLXSW_REG_HPKT_LEN 0x10 6585 6586 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6587 6588 enum { 6589 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6590 MLXSW_REG_HPKT_ACK_REQUIRED, 6591 }; 6592 6593 /* reg_hpkt_ack 6594 * Require acknowledgements from the host for events. 6595 * If set, then the device will wait for the event it sent to be acknowledged 6596 * by the host. This option is only relevant for event trap IDs. 6597 * Access: RW 6598 * 6599 * Note: Currently not supported by firmware. 6600 */ 6601 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6602 6603 enum mlxsw_reg_hpkt_action { 6604 MLXSW_REG_HPKT_ACTION_FORWARD, 6605 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6606 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6607 MLXSW_REG_HPKT_ACTION_DISCARD, 6608 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6609 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6610 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6611 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6612 }; 6613 6614 /* reg_hpkt_action 6615 * Action to perform on packet when trapped. 6616 * 0 - No action. Forward to CPU based on switching rules. 6617 * 1 - Trap to CPU (CPU receives sole copy). 6618 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6619 * 3 - Discard. 6620 * 4 - Soft discard (allow other traps to act on the packet). 6621 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6622 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6623 * 15 - Restore the firmware's default action. 6624 * Access: RW 6625 * 6626 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6627 * addressed to the CPU. 6628 */ 6629 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6630 6631 /* reg_hpkt_trap_group 6632 * Trap group to associate the trap with. 6633 * Access: RW 6634 */ 6635 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6636 6637 /* reg_hpkt_trap_id 6638 * Trap ID. 6639 * Access: Index 6640 * 6641 * Note: A trap ID can only be associated with a single trap group. The device 6642 * will associate the trap ID with the last trap group configured. 6643 */ 6644 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6645 6646 enum { 6647 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6648 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6649 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6650 }; 6651 6652 /* reg_hpkt_ctrl 6653 * Configure dedicated buffer resources for control packets. 6654 * Ignored by SwitchX-2. 6655 * 0 - Keep factory defaults. 6656 * 1 - Do not use control buffer for this trap ID. 6657 * 2 - Use control buffer for this trap ID. 6658 * Access: RW 6659 */ 6660 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6661 6662 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6663 enum mlxsw_reg_htgt_trap_group trap_group, 6664 bool is_ctrl) 6665 { 6666 MLXSW_REG_ZERO(hpkt, payload); 6667 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6668 mlxsw_reg_hpkt_action_set(payload, action); 6669 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6670 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6671 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6672 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6673 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6674 } 6675 6676 /* RGCR - Router General Configuration Register 6677 * -------------------------------------------- 6678 * The register is used for setting up the router configuration. 6679 */ 6680 #define MLXSW_REG_RGCR_ID 0x8001 6681 #define MLXSW_REG_RGCR_LEN 0x28 6682 6683 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6684 6685 /* reg_rgcr_ipv4_en 6686 * IPv4 router enable. 6687 * Access: RW 6688 */ 6689 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6690 6691 /* reg_rgcr_ipv6_en 6692 * IPv6 router enable. 6693 * Access: RW 6694 */ 6695 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6696 6697 /* reg_rgcr_max_router_interfaces 6698 * Defines the maximum number of active router interfaces for all virtual 6699 * routers. 6700 * Access: RW 6701 */ 6702 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6703 6704 /* reg_rgcr_usp 6705 * Update switch priority and packet color. 6706 * 0 - Preserve the value of Switch Priority and packet color. 6707 * 1 - Recalculate the value of Switch Priority and packet color. 6708 * Access: RW 6709 * 6710 * Note: Not supported by SwitchX and SwitchX-2. 6711 */ 6712 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6713 6714 /* reg_rgcr_pcp_rw 6715 * Indicates how to handle the pcp_rewrite_en value: 6716 * 0 - Preserve the value of pcp_rewrite_en. 6717 * 2 - Disable PCP rewrite. 6718 * 3 - Enable PCP rewrite. 6719 * Access: RW 6720 * 6721 * Note: Not supported by SwitchX and SwitchX-2. 6722 */ 6723 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6724 6725 /* reg_rgcr_activity_dis 6726 * Activity disable: 6727 * 0 - Activity will be set when an entry is hit (default). 6728 * 1 - Activity will not be set when an entry is hit. 6729 * 6730 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6731 * (RALUE). 6732 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6733 * Entry (RAUHT). 6734 * Bits 2:7 are reserved. 6735 * Access: RW 6736 * 6737 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6738 */ 6739 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6740 6741 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6742 bool ipv6_en) 6743 { 6744 MLXSW_REG_ZERO(rgcr, payload); 6745 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6746 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6747 } 6748 6749 /* RITR - Router Interface Table Register 6750 * -------------------------------------- 6751 * The register is used to configure the router interface table. 6752 */ 6753 #define MLXSW_REG_RITR_ID 0x8002 6754 #define MLXSW_REG_RITR_LEN 0x40 6755 6756 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6757 6758 /* reg_ritr_enable 6759 * Enables routing on the router interface. 6760 * Access: RW 6761 */ 6762 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6763 6764 /* reg_ritr_ipv4 6765 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6766 * interface. 6767 * Access: RW 6768 */ 6769 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6770 6771 /* reg_ritr_ipv6 6772 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6773 * interface. 6774 * Access: RW 6775 */ 6776 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6777 6778 /* reg_ritr_ipv4_mc 6779 * IPv4 multicast routing enable. 6780 * Access: RW 6781 */ 6782 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6783 6784 /* reg_ritr_ipv6_mc 6785 * IPv6 multicast routing enable. 6786 * Access: RW 6787 */ 6788 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6789 6790 enum mlxsw_reg_ritr_if_type { 6791 /* VLAN interface. */ 6792 MLXSW_REG_RITR_VLAN_IF, 6793 /* FID interface. */ 6794 MLXSW_REG_RITR_FID_IF, 6795 /* Sub-port interface. */ 6796 MLXSW_REG_RITR_SP_IF, 6797 /* Loopback Interface. */ 6798 MLXSW_REG_RITR_LOOPBACK_IF, 6799 }; 6800 6801 /* reg_ritr_type 6802 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6803 * Access: RW 6804 */ 6805 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6806 6807 enum { 6808 MLXSW_REG_RITR_RIF_CREATE, 6809 MLXSW_REG_RITR_RIF_DEL, 6810 }; 6811 6812 /* reg_ritr_op 6813 * Opcode: 6814 * 0 - Create or edit RIF. 6815 * 1 - Delete RIF. 6816 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6817 * is not supported. An interface must be deleted and re-created in order 6818 * to update properties. 6819 * Access: WO 6820 */ 6821 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6822 6823 /* reg_ritr_rif 6824 * Router interface index. A pointer to the Router Interface Table. 6825 * Access: Index 6826 */ 6827 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6828 6829 /* reg_ritr_ipv4_fe 6830 * IPv4 Forwarding Enable. 6831 * Enables routing of IPv4 traffic on the router interface. When disabled, 6832 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6833 * Not supported in SwitchX-2. 6834 * Access: RW 6835 */ 6836 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6837 6838 /* reg_ritr_ipv6_fe 6839 * IPv6 Forwarding Enable. 6840 * Enables routing of IPv6 traffic on the router interface. When disabled, 6841 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6842 * Not supported in SwitchX-2. 6843 * Access: RW 6844 */ 6845 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6846 6847 /* reg_ritr_ipv4_mc_fe 6848 * IPv4 Multicast Forwarding Enable. 6849 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6850 * will be enabled. 6851 * Access: RW 6852 */ 6853 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6854 6855 /* reg_ritr_ipv6_mc_fe 6856 * IPv6 Multicast Forwarding Enable. 6857 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6858 * will be enabled. 6859 * Access: RW 6860 */ 6861 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6862 6863 /* reg_ritr_lb_en 6864 * Loop-back filter enable for unicast packets. 6865 * If the flag is set then loop-back filter for unicast packets is 6866 * implemented on the RIF. Multicast packets are always subject to 6867 * loop-back filtering. 6868 * Access: RW 6869 */ 6870 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6871 6872 /* reg_ritr_virtual_router 6873 * Virtual router ID associated with the router interface. 6874 * Access: RW 6875 */ 6876 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6877 6878 /* reg_ritr_mtu 6879 * Router interface MTU. 6880 * Access: RW 6881 */ 6882 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6883 6884 /* reg_ritr_if_swid 6885 * Switch partition ID. 6886 * Access: RW 6887 */ 6888 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6889 6890 /* reg_ritr_if_mac_profile_id 6891 * MAC msb profile ID. 6892 * Access: RW 6893 */ 6894 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6895 6896 /* reg_ritr_if_mac 6897 * Router interface MAC address. 6898 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6899 * Access: RW 6900 */ 6901 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6902 6903 /* reg_ritr_if_vrrp_id_ipv6 6904 * VRRP ID for IPv6 6905 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6906 * Access: RW 6907 */ 6908 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6909 6910 /* reg_ritr_if_vrrp_id_ipv4 6911 * VRRP ID for IPv4 6912 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6913 * Access: RW 6914 */ 6915 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6916 6917 /* VLAN Interface */ 6918 6919 /* reg_ritr_vlan_if_vlan_id 6920 * VLAN ID. 6921 * Access: RW 6922 */ 6923 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6924 6925 /* reg_ritr_vlan_if_efid 6926 * Egress FID. 6927 * Used to connect the RIF to a bridge. 6928 * Access: RW 6929 * 6930 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6931 */ 6932 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6933 6934 /* FID Interface */ 6935 6936 /* reg_ritr_fid_if_fid 6937 * Filtering ID. Used to connect a bridge to the router. 6938 * When legacy bridge model is used, only FIDs from the vFID range are 6939 * supported. When unified bridge model is used, this is the egress FID for 6940 * router to bridge. 6941 * Access: RW 6942 */ 6943 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6944 6945 /* Sub-port Interface */ 6946 6947 /* reg_ritr_sp_if_lag 6948 * LAG indication. When this bit is set the system_port field holds the 6949 * LAG identifier. 6950 * Access: RW 6951 */ 6952 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6953 6954 /* reg_ritr_sp_system_port 6955 * Port unique indentifier. When lag bit is set, this field holds the 6956 * lag_id in bits 0:9. 6957 * Access: RW 6958 */ 6959 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6960 6961 /* reg_ritr_sp_if_efid 6962 * Egress filtering ID. 6963 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6964 * the VID. 6965 * Access: RW 6966 * 6967 * Note: Reserved when legacy bridge model is used. 6968 */ 6969 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6970 6971 /* reg_ritr_sp_if_vid 6972 * VLAN ID. 6973 * Access: RW 6974 */ 6975 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6976 6977 /* Loopback Interface */ 6978 6979 enum mlxsw_reg_ritr_loopback_protocol { 6980 /* IPinIP IPv4 underlay Unicast */ 6981 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6982 /* IPinIP IPv6 underlay Unicast */ 6983 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6984 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6985 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6986 }; 6987 6988 /* reg_ritr_loopback_protocol 6989 * Access: RW 6990 */ 6991 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6992 6993 enum mlxsw_reg_ritr_loopback_ipip_type { 6994 /* Tunnel is IPinIP. */ 6995 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6996 /* Tunnel is GRE, no key. */ 6997 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6998 /* Tunnel is GRE, with a key. */ 6999 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 7000 }; 7001 7002 /* reg_ritr_loopback_ipip_type 7003 * Encapsulation type. 7004 * Access: RW 7005 */ 7006 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 7007 7008 enum mlxsw_reg_ritr_loopback_ipip_options { 7009 /* The key is defined by gre_key. */ 7010 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 7011 }; 7012 7013 /* reg_ritr_loopback_ipip_options 7014 * Access: RW 7015 */ 7016 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 7017 7018 /* reg_ritr_loopback_ipip_uvr 7019 * Underlay Virtual Router ID. 7020 * Range is 0..cap_max_virtual_routers-1. 7021 * Reserved for Spectrum-2. 7022 * Access: RW 7023 */ 7024 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 7025 7026 /* reg_ritr_loopback_ipip_underlay_rif 7027 * Underlay ingress router interface. 7028 * Reserved for Spectrum. 7029 * Access: RW 7030 */ 7031 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 7032 7033 /* reg_ritr_loopback_ipip_usip* 7034 * Encapsulation Underlay source IP. 7035 * Access: RW 7036 */ 7037 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 7038 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 7039 7040 /* reg_ritr_loopback_ipip_gre_key 7041 * GRE Key. 7042 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 7043 * Access: RW 7044 */ 7045 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 7046 7047 /* Shared between ingress/egress */ 7048 enum mlxsw_reg_ritr_counter_set_type { 7049 /* No Count. */ 7050 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 7051 /* Basic. Used for router interfaces, counting the following: 7052 * - Error and Discard counters. 7053 * - Unicast, Multicast and Broadcast counters. Sharing the 7054 * same set of counters for the different type of traffic 7055 * (IPv4, IPv6 and mpls). 7056 */ 7057 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 7058 }; 7059 7060 /* reg_ritr_ingress_counter_index 7061 * Counter Index for flow counter. 7062 * Access: RW 7063 */ 7064 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 7065 7066 /* reg_ritr_ingress_counter_set_type 7067 * Igress Counter Set Type for router interface counter. 7068 * Access: RW 7069 */ 7070 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 7071 7072 /* reg_ritr_egress_counter_index 7073 * Counter Index for flow counter. 7074 * Access: RW 7075 */ 7076 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 7077 7078 /* reg_ritr_egress_counter_set_type 7079 * Egress Counter Set Type for router interface counter. 7080 * Access: RW 7081 */ 7082 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 7083 7084 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 7085 bool enable, bool egress) 7086 { 7087 enum mlxsw_reg_ritr_counter_set_type set_type; 7088 7089 if (enable) 7090 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 7091 else 7092 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 7093 7094 if (egress) { 7095 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 7096 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 7097 } else { 7098 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 7099 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 7100 } 7101 } 7102 7103 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 7104 { 7105 MLXSW_REG_ZERO(ritr, payload); 7106 mlxsw_reg_ritr_rif_set(payload, rif); 7107 } 7108 7109 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 7110 u16 system_port, u16 vid) 7111 { 7112 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 7113 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 7114 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 7115 } 7116 7117 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 7118 enum mlxsw_reg_ritr_if_type type, 7119 u16 rif, u16 vr_id, u16 mtu) 7120 { 7121 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 7122 7123 MLXSW_REG_ZERO(ritr, payload); 7124 mlxsw_reg_ritr_enable_set(payload, enable); 7125 mlxsw_reg_ritr_ipv4_set(payload, 1); 7126 mlxsw_reg_ritr_ipv6_set(payload, 1); 7127 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7128 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7129 mlxsw_reg_ritr_type_set(payload, type); 7130 mlxsw_reg_ritr_op_set(payload, op); 7131 mlxsw_reg_ritr_rif_set(payload, rif); 7132 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7133 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7134 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7135 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7136 mlxsw_reg_ritr_lb_en_set(payload, 1); 7137 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7138 mlxsw_reg_ritr_mtu_set(payload, mtu); 7139 } 7140 7141 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7142 { 7143 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7144 } 7145 7146 static inline void 7147 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7148 u16 mtu, const char *mac, u8 mac_profile_id, 7149 u16 vlan_id, u16 efid) 7150 { 7151 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7152 7153 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7154 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7155 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7156 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7157 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7158 } 7159 7160 static inline void 7161 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7162 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7163 enum mlxsw_reg_ritr_loopback_ipip_options options, 7164 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7165 { 7166 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7167 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7168 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7169 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7170 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7171 } 7172 7173 static inline void 7174 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7175 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7176 enum mlxsw_reg_ritr_loopback_ipip_options options, 7177 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7178 { 7179 mlxsw_reg_ritr_loopback_protocol_set(payload, 7180 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7181 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7182 uvr_id, underlay_rif, gre_key); 7183 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7184 } 7185 7186 static inline void 7187 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7188 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7189 enum mlxsw_reg_ritr_loopback_ipip_options options, 7190 u16 uvr_id, u16 underlay_rif, 7191 const struct in6_addr *usip, u32 gre_key) 7192 { 7193 enum mlxsw_reg_ritr_loopback_protocol protocol = 7194 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7195 7196 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7197 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7198 uvr_id, underlay_rif, gre_key); 7199 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7200 (const char *)usip); 7201 } 7202 7203 /* RTAR - Router TCAM Allocation Register 7204 * -------------------------------------- 7205 * This register is used for allocation of regions in the TCAM table. 7206 */ 7207 #define MLXSW_REG_RTAR_ID 0x8004 7208 #define MLXSW_REG_RTAR_LEN 0x20 7209 7210 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7211 7212 enum mlxsw_reg_rtar_op { 7213 MLXSW_REG_RTAR_OP_ALLOCATE, 7214 MLXSW_REG_RTAR_OP_RESIZE, 7215 MLXSW_REG_RTAR_OP_DEALLOCATE, 7216 }; 7217 7218 /* reg_rtar_op 7219 * Access: WO 7220 */ 7221 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7222 7223 enum mlxsw_reg_rtar_key_type { 7224 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7225 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7226 }; 7227 7228 /* reg_rtar_key_type 7229 * TCAM key type for the region. 7230 * Access: WO 7231 */ 7232 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7233 7234 /* reg_rtar_region_size 7235 * TCAM region size. When allocating/resizing this is the requested 7236 * size, the response is the actual size. 7237 * Note: Actual size may be larger than requested. 7238 * Reserved for op = Deallocate 7239 * Access: WO 7240 */ 7241 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7242 7243 static inline void mlxsw_reg_rtar_pack(char *payload, 7244 enum mlxsw_reg_rtar_op op, 7245 enum mlxsw_reg_rtar_key_type key_type, 7246 u16 region_size) 7247 { 7248 MLXSW_REG_ZERO(rtar, payload); 7249 mlxsw_reg_rtar_op_set(payload, op); 7250 mlxsw_reg_rtar_key_type_set(payload, key_type); 7251 mlxsw_reg_rtar_region_size_set(payload, region_size); 7252 } 7253 7254 /* RATR - Router Adjacency Table Register 7255 * -------------------------------------- 7256 * The RATR register is used to configure the Router Adjacency (next-hop) 7257 * Table. 7258 */ 7259 #define MLXSW_REG_RATR_ID 0x8008 7260 #define MLXSW_REG_RATR_LEN 0x2C 7261 7262 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7263 7264 enum mlxsw_reg_ratr_op { 7265 /* Read */ 7266 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7267 /* Read and clear activity */ 7268 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7269 /* Write Adjacency entry */ 7270 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7271 /* Write Adjacency entry only if the activity is cleared. 7272 * The write may not succeed if the activity is set. There is not 7273 * direct feedback if the write has succeeded or not, however 7274 * the get will reveal the actual entry (SW can compare the get 7275 * response to the set command). 7276 */ 7277 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7278 }; 7279 7280 /* reg_ratr_op 7281 * Note that Write operation may also be used for updating 7282 * counter_set_type and counter_index. In this case all other 7283 * fields must not be updated. 7284 * Access: OP 7285 */ 7286 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7287 7288 /* reg_ratr_v 7289 * Valid bit. Indicates if the adjacency entry is valid. 7290 * Note: the device may need some time before reusing an invalidated 7291 * entry. During this time the entry can not be reused. It is 7292 * recommended to use another entry before reusing an invalidated 7293 * entry (e.g. software can put it at the end of the list for 7294 * reusing). Trying to access an invalidated entry not yet cleared 7295 * by the device results with failure indicating "Try Again" status. 7296 * When valid is '0' then egress_router_interface,trap_action, 7297 * adjacency_parameters and counters are reserved 7298 * Access: RW 7299 */ 7300 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7301 7302 /* reg_ratr_a 7303 * Activity. Set for new entries. Set if a packet lookup has hit on 7304 * the specific entry. To clear the a bit, use "clear activity". 7305 * Access: RO 7306 */ 7307 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7308 7309 enum mlxsw_reg_ratr_type { 7310 /* Ethernet */ 7311 MLXSW_REG_RATR_TYPE_ETHERNET, 7312 /* IPoIB Unicast without GRH. 7313 * Reserved for Spectrum. 7314 */ 7315 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7316 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7317 * adjacency). 7318 * Reserved for Spectrum. 7319 */ 7320 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7321 /* IPoIB Multicast. 7322 * Reserved for Spectrum. 7323 */ 7324 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7325 /* MPLS. 7326 * Reserved for SwitchX/-2. 7327 */ 7328 MLXSW_REG_RATR_TYPE_MPLS, 7329 /* IPinIP Encap. 7330 * Reserved for SwitchX/-2. 7331 */ 7332 MLXSW_REG_RATR_TYPE_IPIP, 7333 }; 7334 7335 /* reg_ratr_type 7336 * Adjacency entry type. 7337 * Access: RW 7338 */ 7339 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7340 7341 /* reg_ratr_adjacency_index_low 7342 * Bits 15:0 of index into the adjacency table. 7343 * For SwitchX and SwitchX-2, the adjacency table is linear and 7344 * used for adjacency entries only. 7345 * For Spectrum, the index is to the KVD linear. 7346 * Access: Index 7347 */ 7348 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7349 7350 /* reg_ratr_egress_router_interface 7351 * Range is 0 .. cap_max_router_interfaces - 1 7352 * Access: RW 7353 */ 7354 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7355 7356 enum mlxsw_reg_ratr_trap_action { 7357 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7358 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7359 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7360 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7361 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7362 }; 7363 7364 /* reg_ratr_trap_action 7365 * see mlxsw_reg_ratr_trap_action 7366 * Access: RW 7367 */ 7368 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7369 7370 /* reg_ratr_adjacency_index_high 7371 * Bits 23:16 of the adjacency_index. 7372 * Access: Index 7373 */ 7374 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7375 7376 enum mlxsw_reg_ratr_trap_id { 7377 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7378 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7379 }; 7380 7381 /* reg_ratr_trap_id 7382 * Trap ID to be reported to CPU. 7383 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7384 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7385 * Access: RW 7386 */ 7387 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7388 7389 /* reg_ratr_eth_destination_mac 7390 * MAC address of the destination next-hop. 7391 * Access: RW 7392 */ 7393 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7394 7395 enum mlxsw_reg_ratr_ipip_type { 7396 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7397 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7398 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7399 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7400 }; 7401 7402 /* reg_ratr_ipip_type 7403 * Underlay destination ip type. 7404 * Note: the type field must match the protocol of the router interface. 7405 * Access: RW 7406 */ 7407 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7408 7409 /* reg_ratr_ipip_ipv4_udip 7410 * Underlay ipv4 dip. 7411 * Reserved when ipip_type is IPv6. 7412 * Access: RW 7413 */ 7414 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7415 7416 /* reg_ratr_ipip_ipv6_ptr 7417 * Pointer to IPv6 underlay destination ip address. 7418 * For Spectrum: Pointer to KVD linear space. 7419 * Access: RW 7420 */ 7421 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7422 7423 enum mlxsw_reg_flow_counter_set_type { 7424 /* No count */ 7425 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7426 /* Count packets and bytes */ 7427 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7428 /* Count only packets */ 7429 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7430 }; 7431 7432 /* reg_ratr_counter_set_type 7433 * Counter set type for flow counters 7434 * Access: RW 7435 */ 7436 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7437 7438 /* reg_ratr_counter_index 7439 * Counter index for flow counters 7440 * Access: RW 7441 */ 7442 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7443 7444 static inline void 7445 mlxsw_reg_ratr_pack(char *payload, 7446 enum mlxsw_reg_ratr_op op, bool valid, 7447 enum mlxsw_reg_ratr_type type, 7448 u32 adjacency_index, u16 egress_rif) 7449 { 7450 MLXSW_REG_ZERO(ratr, payload); 7451 mlxsw_reg_ratr_op_set(payload, op); 7452 mlxsw_reg_ratr_v_set(payload, valid); 7453 mlxsw_reg_ratr_type_set(payload, type); 7454 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7455 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7456 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7457 } 7458 7459 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7460 const char *dest_mac) 7461 { 7462 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7463 } 7464 7465 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7466 { 7467 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7468 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7469 } 7470 7471 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7472 { 7473 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7474 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7475 } 7476 7477 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7478 bool counter_enable) 7479 { 7480 enum mlxsw_reg_flow_counter_set_type set_type; 7481 7482 if (counter_enable) 7483 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7484 else 7485 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7486 7487 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7488 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7489 } 7490 7491 /* RDPM - Router DSCP to Priority Mapping 7492 * -------------------------------------- 7493 * Controls the mapping from DSCP field to switch priority on routed packets 7494 */ 7495 #define MLXSW_REG_RDPM_ID 0x8009 7496 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7497 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7498 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7499 #define MLXSW_REG_RDPM_LEN 0x40 7500 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7501 MLXSW_REG_RDPM_LEN - \ 7502 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7503 7504 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7505 7506 /* reg_dscp_entry_e 7507 * Enable update of the specific entry 7508 * Access: Index 7509 */ 7510 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7511 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7512 7513 /* reg_dscp_entry_prio 7514 * Switch Priority 7515 * Access: RW 7516 */ 7517 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7518 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7519 7520 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7521 u8 prio) 7522 { 7523 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7524 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7525 } 7526 7527 /* RICNT - Router Interface Counter Register 7528 * ----------------------------------------- 7529 * The RICNT register retrieves per port performance counters 7530 */ 7531 #define MLXSW_REG_RICNT_ID 0x800B 7532 #define MLXSW_REG_RICNT_LEN 0x100 7533 7534 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7535 7536 /* reg_ricnt_counter_index 7537 * Counter index 7538 * Access: RW 7539 */ 7540 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7541 7542 enum mlxsw_reg_ricnt_counter_set_type { 7543 /* No Count. */ 7544 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7545 /* Basic. Used for router interfaces, counting the following: 7546 * - Error and Discard counters. 7547 * - Unicast, Multicast and Broadcast counters. Sharing the 7548 * same set of counters for the different type of traffic 7549 * (IPv4, IPv6 and mpls). 7550 */ 7551 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7552 }; 7553 7554 /* reg_ricnt_counter_set_type 7555 * Counter Set Type for router interface counter 7556 * Access: RW 7557 */ 7558 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7559 7560 enum mlxsw_reg_ricnt_opcode { 7561 /* Nop. Supported only for read access*/ 7562 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7563 /* Clear. Setting the clr bit will reset the counter value for 7564 * all counters of the specified Router Interface. 7565 */ 7566 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7567 }; 7568 7569 /* reg_ricnt_opcode 7570 * Opcode 7571 * Access: RW 7572 */ 7573 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7574 7575 /* reg_ricnt_good_unicast_packets 7576 * good unicast packets. 7577 * Access: RW 7578 */ 7579 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7580 7581 /* reg_ricnt_good_multicast_packets 7582 * good multicast packets. 7583 * Access: RW 7584 */ 7585 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7586 7587 /* reg_ricnt_good_broadcast_packets 7588 * good broadcast packets 7589 * Access: RW 7590 */ 7591 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7592 7593 /* reg_ricnt_good_unicast_bytes 7594 * A count of L3 data and padding octets not including L2 headers 7595 * for good unicast frames. 7596 * Access: RW 7597 */ 7598 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7599 7600 /* reg_ricnt_good_multicast_bytes 7601 * A count of L3 data and padding octets not including L2 headers 7602 * for good multicast frames. 7603 * Access: RW 7604 */ 7605 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7606 7607 /* reg_ritr_good_broadcast_bytes 7608 * A count of L3 data and padding octets not including L2 headers 7609 * for good broadcast frames. 7610 * Access: RW 7611 */ 7612 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7613 7614 /* reg_ricnt_error_packets 7615 * A count of errored frames that do not pass the router checks. 7616 * Access: RW 7617 */ 7618 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7619 7620 /* reg_ricnt_discrad_packets 7621 * A count of non-errored frames that do not pass the router checks. 7622 * Access: RW 7623 */ 7624 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7625 7626 /* reg_ricnt_error_bytes 7627 * A count of L3 data and padding octets not including L2 headers 7628 * for errored frames. 7629 * Access: RW 7630 */ 7631 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7632 7633 /* reg_ricnt_discard_bytes 7634 * A count of L3 data and padding octets not including L2 headers 7635 * for non-errored frames that do not pass the router checks. 7636 * Access: RW 7637 */ 7638 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7639 7640 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7641 enum mlxsw_reg_ricnt_opcode op) 7642 { 7643 MLXSW_REG_ZERO(ricnt, payload); 7644 mlxsw_reg_ricnt_op_set(payload, op); 7645 mlxsw_reg_ricnt_counter_index_set(payload, index); 7646 mlxsw_reg_ricnt_counter_set_type_set(payload, 7647 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7648 } 7649 7650 /* RRCR - Router Rules Copy Register Layout 7651 * ---------------------------------------- 7652 * This register is used for moving and copying route entry rules. 7653 */ 7654 #define MLXSW_REG_RRCR_ID 0x800F 7655 #define MLXSW_REG_RRCR_LEN 0x24 7656 7657 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7658 7659 enum mlxsw_reg_rrcr_op { 7660 /* Move rules */ 7661 MLXSW_REG_RRCR_OP_MOVE, 7662 /* Copy rules */ 7663 MLXSW_REG_RRCR_OP_COPY, 7664 }; 7665 7666 /* reg_rrcr_op 7667 * Access: WO 7668 */ 7669 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7670 7671 /* reg_rrcr_offset 7672 * Offset within the region from which to copy/move. 7673 * Access: Index 7674 */ 7675 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7676 7677 /* reg_rrcr_size 7678 * The number of rules to copy/move. 7679 * Access: WO 7680 */ 7681 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7682 7683 /* reg_rrcr_table_id 7684 * Identifier of the table on which to perform the operation. Encoding is the 7685 * same as in RTAR.key_type 7686 * Access: Index 7687 */ 7688 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7689 7690 /* reg_rrcr_dest_offset 7691 * Offset within the region to which to copy/move 7692 * Access: Index 7693 */ 7694 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7695 7696 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7697 u16 offset, u16 size, 7698 enum mlxsw_reg_rtar_key_type table_id, 7699 u16 dest_offset) 7700 { 7701 MLXSW_REG_ZERO(rrcr, payload); 7702 mlxsw_reg_rrcr_op_set(payload, op); 7703 mlxsw_reg_rrcr_offset_set(payload, offset); 7704 mlxsw_reg_rrcr_size_set(payload, size); 7705 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7706 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7707 } 7708 7709 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7710 * ------------------------------------------------------- 7711 * RALTA is used to allocate the LPM trees of the SHSPM method. 7712 */ 7713 #define MLXSW_REG_RALTA_ID 0x8010 7714 #define MLXSW_REG_RALTA_LEN 0x04 7715 7716 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7717 7718 /* reg_ralta_op 7719 * opcode (valid for Write, must be 0 on Read) 7720 * 0 - allocate a tree 7721 * 1 - deallocate a tree 7722 * Access: OP 7723 */ 7724 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7725 7726 enum mlxsw_reg_ralxx_protocol { 7727 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7728 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7729 }; 7730 7731 /* reg_ralta_protocol 7732 * Protocol. 7733 * Deallocation opcode: Reserved. 7734 * Access: RW 7735 */ 7736 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7737 7738 /* reg_ralta_tree_id 7739 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7740 * the tree identifier (managed by software). 7741 * Note that tree_id 0 is allocated for a default-route tree. 7742 * Access: Index 7743 */ 7744 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7745 7746 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7747 enum mlxsw_reg_ralxx_protocol protocol, 7748 u8 tree_id) 7749 { 7750 MLXSW_REG_ZERO(ralta, payload); 7751 mlxsw_reg_ralta_op_set(payload, !alloc); 7752 mlxsw_reg_ralta_protocol_set(payload, protocol); 7753 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7754 } 7755 7756 /* RALST - Router Algorithmic LPM Structure Tree Register 7757 * ------------------------------------------------------ 7758 * RALST is used to set and query the structure of an LPM tree. 7759 * The structure of the tree must be sorted as a sorted binary tree, while 7760 * each node is a bin that is tagged as the length of the prefixes the lookup 7761 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7762 * of X bits to match with the destination address. The bin 0 indicates 7763 * the default action, when there is no match of any prefix. 7764 */ 7765 #define MLXSW_REG_RALST_ID 0x8011 7766 #define MLXSW_REG_RALST_LEN 0x104 7767 7768 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7769 7770 /* reg_ralst_root_bin 7771 * The bin number of the root bin. 7772 * 0<root_bin=<(length of IP address) 7773 * For a default-route tree configure 0xff 7774 * Access: RW 7775 */ 7776 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7777 7778 /* reg_ralst_tree_id 7779 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7780 * Access: Index 7781 */ 7782 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7783 7784 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7785 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7786 #define MLXSW_REG_RALST_BIN_COUNT 128 7787 7788 /* reg_ralst_left_child_bin 7789 * Holding the children of the bin according to the stored tree's structure. 7790 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7791 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7792 * Access: RW 7793 */ 7794 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7795 7796 /* reg_ralst_right_child_bin 7797 * Holding the children of the bin according to the stored tree's structure. 7798 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7799 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7800 * Access: RW 7801 */ 7802 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7803 false); 7804 7805 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7806 { 7807 MLXSW_REG_ZERO(ralst, payload); 7808 7809 /* Initialize all bins to have no left or right child */ 7810 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7811 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7812 7813 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7814 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7815 } 7816 7817 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7818 u8 left_child_bin, 7819 u8 right_child_bin) 7820 { 7821 int bin_index = bin_number - 1; 7822 7823 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7824 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7825 right_child_bin); 7826 } 7827 7828 /* RALTB - Router Algorithmic LPM Tree Binding Register 7829 * ---------------------------------------------------- 7830 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7831 */ 7832 #define MLXSW_REG_RALTB_ID 0x8012 7833 #define MLXSW_REG_RALTB_LEN 0x04 7834 7835 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7836 7837 /* reg_raltb_virtual_router 7838 * Virtual Router ID 7839 * Range is 0..cap_max_virtual_routers-1 7840 * Access: Index 7841 */ 7842 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7843 7844 /* reg_raltb_protocol 7845 * Protocol. 7846 * Access: Index 7847 */ 7848 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7849 7850 /* reg_raltb_tree_id 7851 * Tree to be used for the {virtual_router, protocol} 7852 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7853 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7854 * Access: RW 7855 */ 7856 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7857 7858 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7859 enum mlxsw_reg_ralxx_protocol protocol, 7860 u8 tree_id) 7861 { 7862 MLXSW_REG_ZERO(raltb, payload); 7863 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7864 mlxsw_reg_raltb_protocol_set(payload, protocol); 7865 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7866 } 7867 7868 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7869 * ----------------------------------------------------- 7870 * RALUE is used to configure and query LPM entries that serve 7871 * the Unicast protocols. 7872 */ 7873 #define MLXSW_REG_RALUE_ID 0x8013 7874 #define MLXSW_REG_RALUE_LEN 0x38 7875 7876 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7877 7878 /* reg_ralue_protocol 7879 * Protocol. 7880 * Access: Index 7881 */ 7882 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7883 7884 enum mlxsw_reg_ralue_op { 7885 /* Read operation. If entry doesn't exist, the operation fails. */ 7886 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7887 /* Clear on read operation. Used to read entry and 7888 * clear Activity bit. 7889 */ 7890 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7891 /* Write operation. Used to write a new entry to the table. All RW 7892 * fields are written for new entry. Activity bit is set 7893 * for new entries. 7894 */ 7895 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7896 /* Update operation. Used to update an existing route entry and 7897 * only update the RW fields that are detailed in the field 7898 * op_u_mask. If entry doesn't exist, the operation fails. 7899 */ 7900 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7901 /* Clear activity. The Activity bit (the field a) is cleared 7902 * for the entry. 7903 */ 7904 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7905 /* Delete operation. Used to delete an existing entry. If entry 7906 * doesn't exist, the operation fails. 7907 */ 7908 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7909 }; 7910 7911 /* reg_ralue_op 7912 * Operation. 7913 * Access: OP 7914 */ 7915 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7916 7917 /* reg_ralue_a 7918 * Activity. Set for new entries. Set if a packet lookup has hit on the 7919 * specific entry, only if the entry is a route. To clear the a bit, use 7920 * "clear activity" op. 7921 * Enabled by activity_dis in RGCR 7922 * Access: RO 7923 */ 7924 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7925 7926 /* reg_ralue_virtual_router 7927 * Virtual Router ID 7928 * Range is 0..cap_max_virtual_routers-1 7929 * Access: Index 7930 */ 7931 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7932 7933 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7934 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7935 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7936 7937 /* reg_ralue_op_u_mask 7938 * opcode update mask. 7939 * On read operation, this field is reserved. 7940 * This field is valid for update opcode, otherwise - reserved. 7941 * This field is a bitmask of the fields that should be updated. 7942 * Access: WO 7943 */ 7944 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7945 7946 /* reg_ralue_prefix_len 7947 * Number of bits in the prefix of the LPM route. 7948 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7949 * two entries in the physical HW table. 7950 * Access: Index 7951 */ 7952 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7953 7954 /* reg_ralue_dip* 7955 * The prefix of the route or of the marker that the object of the LPM 7956 * is compared with. The most significant bits of the dip are the prefix. 7957 * The least significant bits must be '0' if the prefix_len is smaller 7958 * than 128 for IPv6 or smaller than 32 for IPv4. 7959 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7960 * Access: Index 7961 */ 7962 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7963 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7964 7965 enum mlxsw_reg_ralue_entry_type { 7966 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7967 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7968 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7969 }; 7970 7971 /* reg_ralue_entry_type 7972 * Entry type. 7973 * Note - for Marker entries, the action_type and action fields are reserved. 7974 * Access: RW 7975 */ 7976 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7977 7978 /* reg_ralue_bmp_len 7979 * The best match prefix length in the case that there is no match for 7980 * longer prefixes. 7981 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7982 * Note for any update operation with entry_type modification this 7983 * field must be set. 7984 * Access: RW 7985 */ 7986 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7987 7988 enum mlxsw_reg_ralue_action_type { 7989 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7990 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7991 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7992 }; 7993 7994 /* reg_ralue_action_type 7995 * Action Type 7996 * Indicates how the IP address is connected. 7997 * It can be connected to a local subnet through local_erif or can be 7998 * on a remote subnet connected through a next-hop router, 7999 * or transmitted to the CPU. 8000 * Reserved when entry_type = MARKER_ENTRY 8001 * Access: RW 8002 */ 8003 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 8004 8005 enum mlxsw_reg_ralue_trap_action { 8006 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 8007 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 8008 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 8009 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 8010 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 8011 }; 8012 8013 /* reg_ralue_trap_action 8014 * Trap action. 8015 * For IP2ME action, only NOP and MIRROR are possible. 8016 * Access: RW 8017 */ 8018 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 8019 8020 /* reg_ralue_trap_id 8021 * Trap ID to be reported to CPU. 8022 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 8023 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 8024 * Access: RW 8025 */ 8026 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 8027 8028 /* reg_ralue_adjacency_index 8029 * Points to the first entry of the group-based ECMP. 8030 * Only relevant in case of REMOTE action. 8031 * Access: RW 8032 */ 8033 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 8034 8035 /* reg_ralue_ecmp_size 8036 * Amount of sequential entries starting 8037 * from the adjacency_index (the number of ECMPs). 8038 * The valid range is 1-64, 512, 1024, 2048 and 4096. 8039 * Reserved when trap_action is TRAP or DISCARD_ERROR. 8040 * Only relevant in case of REMOTE action. 8041 * Access: RW 8042 */ 8043 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 8044 8045 /* reg_ralue_local_erif 8046 * Egress Router Interface. 8047 * Only relevant in case of LOCAL action. 8048 * Access: RW 8049 */ 8050 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 8051 8052 /* reg_ralue_ip2me_v 8053 * Valid bit for the tunnel_ptr field. 8054 * If valid = 0 then trap to CPU as IP2ME trap ID. 8055 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 8056 * decapsulation then tunnel decapsulation is done. 8057 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 8058 * decapsulation then trap as IP2ME trap ID. 8059 * Only relevant in case of IP2ME action. 8060 * Access: RW 8061 */ 8062 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 8063 8064 /* reg_ralue_ip2me_tunnel_ptr 8065 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 8066 * For Spectrum, pointer to KVD Linear. 8067 * Only relevant in case of IP2ME action. 8068 * Access: RW 8069 */ 8070 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 8071 8072 static inline void mlxsw_reg_ralue_pack(char *payload, 8073 enum mlxsw_reg_ralxx_protocol protocol, 8074 enum mlxsw_reg_ralue_op op, 8075 u16 virtual_router, u8 prefix_len) 8076 { 8077 MLXSW_REG_ZERO(ralue, payload); 8078 mlxsw_reg_ralue_protocol_set(payload, protocol); 8079 mlxsw_reg_ralue_op_set(payload, op); 8080 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 8081 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 8082 mlxsw_reg_ralue_entry_type_set(payload, 8083 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 8084 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 8085 } 8086 8087 static inline void mlxsw_reg_ralue_pack4(char *payload, 8088 enum mlxsw_reg_ralxx_protocol protocol, 8089 enum mlxsw_reg_ralue_op op, 8090 u16 virtual_router, u8 prefix_len, 8091 u32 dip) 8092 { 8093 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8094 mlxsw_reg_ralue_dip4_set(payload, dip); 8095 } 8096 8097 static inline void mlxsw_reg_ralue_pack6(char *payload, 8098 enum mlxsw_reg_ralxx_protocol protocol, 8099 enum mlxsw_reg_ralue_op op, 8100 u16 virtual_router, u8 prefix_len, 8101 const void *dip) 8102 { 8103 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8104 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 8105 } 8106 8107 static inline void 8108 mlxsw_reg_ralue_act_remote_pack(char *payload, 8109 enum mlxsw_reg_ralue_trap_action trap_action, 8110 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 8111 { 8112 mlxsw_reg_ralue_action_type_set(payload, 8113 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 8114 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8115 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8116 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 8117 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 8118 } 8119 8120 static inline void 8121 mlxsw_reg_ralue_act_local_pack(char *payload, 8122 enum mlxsw_reg_ralue_trap_action trap_action, 8123 u16 trap_id, u16 local_erif) 8124 { 8125 mlxsw_reg_ralue_action_type_set(payload, 8126 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8127 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8128 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8129 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8130 } 8131 8132 static inline void 8133 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8134 { 8135 mlxsw_reg_ralue_action_type_set(payload, 8136 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8137 } 8138 8139 static inline void 8140 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8141 { 8142 mlxsw_reg_ralue_action_type_set(payload, 8143 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8144 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8145 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8146 } 8147 8148 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8149 * ---------------------------------------------------------- 8150 * The RAUHT register is used to configure and query the Unicast Host table in 8151 * devices that implement the Algorithmic LPM. 8152 */ 8153 #define MLXSW_REG_RAUHT_ID 0x8014 8154 #define MLXSW_REG_RAUHT_LEN 0x74 8155 8156 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8157 8158 enum mlxsw_reg_rauht_type { 8159 MLXSW_REG_RAUHT_TYPE_IPV4, 8160 MLXSW_REG_RAUHT_TYPE_IPV6, 8161 }; 8162 8163 /* reg_rauht_type 8164 * Access: Index 8165 */ 8166 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8167 8168 enum mlxsw_reg_rauht_op { 8169 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8170 /* Read operation */ 8171 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8172 /* Clear on read operation. Used to read entry and clear 8173 * activity bit. 8174 */ 8175 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8176 /* Add. Used to write a new entry to the table. All R/W fields are 8177 * relevant for new entry. Activity bit is set for new entries. 8178 */ 8179 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8180 /* Update action. Used to update an existing route entry and 8181 * only update the following fields: 8182 * trap_action, trap_id, mac, counter_set_type, counter_index 8183 */ 8184 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8185 /* Clear activity. A bit is cleared for the entry. */ 8186 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8187 /* Delete entry */ 8188 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8189 /* Delete all host entries on a RIF. In this command, dip 8190 * field is reserved. 8191 */ 8192 }; 8193 8194 /* reg_rauht_op 8195 * Access: OP 8196 */ 8197 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8198 8199 /* reg_rauht_a 8200 * Activity. Set for new entries. Set if a packet lookup has hit on 8201 * the specific entry. 8202 * To clear the a bit, use "clear activity" op. 8203 * Enabled by activity_dis in RGCR 8204 * Access: RO 8205 */ 8206 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8207 8208 /* reg_rauht_rif 8209 * Router Interface 8210 * Access: Index 8211 */ 8212 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8213 8214 /* reg_rauht_dip* 8215 * Destination address. 8216 * Access: Index 8217 */ 8218 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8219 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8220 8221 enum mlxsw_reg_rauht_trap_action { 8222 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8223 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8224 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8225 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8226 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8227 }; 8228 8229 /* reg_rauht_trap_action 8230 * Access: RW 8231 */ 8232 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8233 8234 enum mlxsw_reg_rauht_trap_id { 8235 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8236 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8237 }; 8238 8239 /* reg_rauht_trap_id 8240 * Trap ID to be reported to CPU. 8241 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8242 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8243 * trap_id is reserved. 8244 * Access: RW 8245 */ 8246 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8247 8248 /* reg_rauht_counter_set_type 8249 * Counter set type for flow counters 8250 * Access: RW 8251 */ 8252 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8253 8254 /* reg_rauht_counter_index 8255 * Counter index for flow counters 8256 * Access: RW 8257 */ 8258 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8259 8260 /* reg_rauht_mac 8261 * MAC address. 8262 * Access: RW 8263 */ 8264 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8265 8266 static inline void mlxsw_reg_rauht_pack(char *payload, 8267 enum mlxsw_reg_rauht_op op, u16 rif, 8268 const char *mac) 8269 { 8270 MLXSW_REG_ZERO(rauht, payload); 8271 mlxsw_reg_rauht_op_set(payload, op); 8272 mlxsw_reg_rauht_rif_set(payload, rif); 8273 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8274 } 8275 8276 static inline void mlxsw_reg_rauht_pack4(char *payload, 8277 enum mlxsw_reg_rauht_op op, u16 rif, 8278 const char *mac, u32 dip) 8279 { 8280 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8281 mlxsw_reg_rauht_dip4_set(payload, dip); 8282 } 8283 8284 static inline void mlxsw_reg_rauht_pack6(char *payload, 8285 enum mlxsw_reg_rauht_op op, u16 rif, 8286 const char *mac, const char *dip) 8287 { 8288 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8289 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8290 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8291 } 8292 8293 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8294 u64 counter_index) 8295 { 8296 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8297 mlxsw_reg_rauht_counter_set_type_set(payload, 8298 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8299 } 8300 8301 /* RALEU - Router Algorithmic LPM ECMP Update Register 8302 * --------------------------------------------------- 8303 * The register enables updating the ECMP section in the action for multiple 8304 * LPM Unicast entries in a single operation. The update is executed to 8305 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8306 */ 8307 #define MLXSW_REG_RALEU_ID 0x8015 8308 #define MLXSW_REG_RALEU_LEN 0x28 8309 8310 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8311 8312 /* reg_raleu_protocol 8313 * Protocol. 8314 * Access: Index 8315 */ 8316 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8317 8318 /* reg_raleu_virtual_router 8319 * Virtual Router ID 8320 * Range is 0..cap_max_virtual_routers-1 8321 * Access: Index 8322 */ 8323 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8324 8325 /* reg_raleu_adjacency_index 8326 * Adjacency Index used for matching on the existing entries. 8327 * Access: Index 8328 */ 8329 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8330 8331 /* reg_raleu_ecmp_size 8332 * ECMP Size used for matching on the existing entries. 8333 * Access: Index 8334 */ 8335 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8336 8337 /* reg_raleu_new_adjacency_index 8338 * New Adjacency Index. 8339 * Access: WO 8340 */ 8341 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8342 8343 /* reg_raleu_new_ecmp_size 8344 * New ECMP Size. 8345 * Access: WO 8346 */ 8347 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8348 8349 static inline void mlxsw_reg_raleu_pack(char *payload, 8350 enum mlxsw_reg_ralxx_protocol protocol, 8351 u16 virtual_router, 8352 u32 adjacency_index, u16 ecmp_size, 8353 u32 new_adjacency_index, 8354 u16 new_ecmp_size) 8355 { 8356 MLXSW_REG_ZERO(raleu, payload); 8357 mlxsw_reg_raleu_protocol_set(payload, protocol); 8358 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8359 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8360 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8361 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8362 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8363 } 8364 8365 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8366 * ---------------------------------------------------------------- 8367 * The RAUHTD register allows dumping entries from the Router Unicast Host 8368 * Table. For a given session an entry is dumped no more than one time. The 8369 * first RAUHTD access after reset is a new session. A session ends when the 8370 * num_rec response is smaller than num_rec request or for IPv4 when the 8371 * num_entries is smaller than 4. The clear activity affect the current session 8372 * or the last session if a new session has not started. 8373 */ 8374 #define MLXSW_REG_RAUHTD_ID 0x8018 8375 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8376 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8377 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8378 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8379 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8380 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8381 8382 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8383 8384 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8385 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8386 8387 /* reg_rauhtd_filter_fields 8388 * if a bit is '0' then the relevant field is ignored and dump is done 8389 * regardless of the field value 8390 * Bit0 - filter by activity: entry_a 8391 * Bit3 - filter by entry rip: entry_rif 8392 * Access: Index 8393 */ 8394 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8395 8396 enum mlxsw_reg_rauhtd_op { 8397 MLXSW_REG_RAUHTD_OP_DUMP, 8398 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8399 }; 8400 8401 /* reg_rauhtd_op 8402 * Access: OP 8403 */ 8404 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8405 8406 /* reg_rauhtd_num_rec 8407 * At request: number of records requested 8408 * At response: number of records dumped 8409 * For IPv4, each record has 4 entries at request and up to 4 entries 8410 * at response 8411 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8412 * Access: Index 8413 */ 8414 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8415 8416 /* reg_rauhtd_entry_a 8417 * Dump only if activity has value of entry_a 8418 * Reserved if filter_fields bit0 is '0' 8419 * Access: Index 8420 */ 8421 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8422 8423 enum mlxsw_reg_rauhtd_type { 8424 MLXSW_REG_RAUHTD_TYPE_IPV4, 8425 MLXSW_REG_RAUHTD_TYPE_IPV6, 8426 }; 8427 8428 /* reg_rauhtd_type 8429 * Dump only if record type is: 8430 * 0 - IPv4 8431 * 1 - IPv6 8432 * Access: Index 8433 */ 8434 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8435 8436 /* reg_rauhtd_entry_rif 8437 * Dump only if RIF has value of entry_rif 8438 * Reserved if filter_fields bit3 is '0' 8439 * Access: Index 8440 */ 8441 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8442 8443 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8444 enum mlxsw_reg_rauhtd_type type) 8445 { 8446 MLXSW_REG_ZERO(rauhtd, payload); 8447 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8448 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8449 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8450 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8451 mlxsw_reg_rauhtd_type_set(payload, type); 8452 } 8453 8454 /* reg_rauhtd_ipv4_rec_num_entries 8455 * Number of valid entries in this record: 8456 * 0 - 1 valid entry 8457 * 1 - 2 valid entries 8458 * 2 - 3 valid entries 8459 * 3 - 4 valid entries 8460 * Access: RO 8461 */ 8462 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8463 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8464 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8465 8466 /* reg_rauhtd_rec_type 8467 * Record type. 8468 * 0 - IPv4 8469 * 1 - IPv6 8470 * Access: RO 8471 */ 8472 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8473 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8474 8475 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8476 8477 /* reg_rauhtd_ipv4_ent_a 8478 * Activity. Set for new entries. Set if a packet lookup has hit on the 8479 * specific entry. 8480 * Access: RO 8481 */ 8482 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8483 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8484 8485 /* reg_rauhtd_ipv4_ent_rif 8486 * Router interface. 8487 * Access: RO 8488 */ 8489 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8490 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8491 8492 /* reg_rauhtd_ipv4_ent_dip 8493 * Destination IPv4 address. 8494 * Access: RO 8495 */ 8496 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8497 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8498 8499 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8500 8501 /* reg_rauhtd_ipv6_ent_a 8502 * Activity. Set for new entries. Set if a packet lookup has hit on the 8503 * specific entry. 8504 * Access: RO 8505 */ 8506 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8507 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8508 8509 /* reg_rauhtd_ipv6_ent_rif 8510 * Router interface. 8511 * Access: RO 8512 */ 8513 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8514 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8515 8516 /* reg_rauhtd_ipv6_ent_dip 8517 * Destination IPv6 address. 8518 * Access: RO 8519 */ 8520 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8521 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8522 8523 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8524 int ent_index, u16 *p_rif, 8525 u32 *p_dip) 8526 { 8527 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8528 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8529 } 8530 8531 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8532 int rec_index, u16 *p_rif, 8533 char *p_dip) 8534 { 8535 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8536 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8537 } 8538 8539 /* RTDP - Routing Tunnel Decap Properties Register 8540 * ----------------------------------------------- 8541 * The RTDP register is used for configuring the tunnel decap properties of NVE 8542 * and IPinIP. 8543 */ 8544 #define MLXSW_REG_RTDP_ID 0x8020 8545 #define MLXSW_REG_RTDP_LEN 0x44 8546 8547 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8548 8549 enum mlxsw_reg_rtdp_type { 8550 MLXSW_REG_RTDP_TYPE_NVE, 8551 MLXSW_REG_RTDP_TYPE_IPIP, 8552 }; 8553 8554 /* reg_rtdp_type 8555 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8556 * Access: RW 8557 */ 8558 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8559 8560 /* reg_rtdp_tunnel_index 8561 * Index to the Decap entry. 8562 * For Spectrum, Index to KVD Linear. 8563 * Access: Index 8564 */ 8565 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8566 8567 /* reg_rtdp_egress_router_interface 8568 * Underlay egress router interface. 8569 * Valid range is from 0 to cap_max_router_interfaces - 1 8570 * Access: RW 8571 */ 8572 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8573 8574 /* IPinIP */ 8575 8576 /* reg_rtdp_ipip_irif 8577 * Ingress Router Interface for the overlay router 8578 * Access: RW 8579 */ 8580 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8581 8582 enum mlxsw_reg_rtdp_ipip_sip_check { 8583 /* No sip checks. */ 8584 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8585 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8586 * equal ipv4_usip. 8587 */ 8588 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8589 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8590 * equal ipv6_usip. 8591 */ 8592 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8593 }; 8594 8595 /* reg_rtdp_ipip_sip_check 8596 * SIP check to perform. If decapsulation failed due to these configurations 8597 * then trap_id is IPIP_DECAP_ERROR. 8598 * Access: RW 8599 */ 8600 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8601 8602 /* If set, allow decapsulation of IPinIP (without GRE). */ 8603 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8604 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8605 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8606 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8607 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8608 8609 /* reg_rtdp_ipip_type_check 8610 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8611 * these configurations then trap_id is IPIP_DECAP_ERROR. 8612 * Access: RW 8613 */ 8614 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8615 8616 /* reg_rtdp_ipip_gre_key_check 8617 * Whether GRE key should be checked. When check is enabled: 8618 * - A packet received as IPinIP (without GRE) will always pass. 8619 * - A packet received as IPinGREinIP without a key will not pass the check. 8620 * - A packet received as IPinGREinIP with a key will pass the check only if the 8621 * key in the packet is equal to expected_gre_key. 8622 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8623 * Access: RW 8624 */ 8625 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8626 8627 /* reg_rtdp_ipip_ipv4_usip 8628 * Underlay IPv4 address for ipv4 source address check. 8629 * Reserved when sip_check is not '1'. 8630 * Access: RW 8631 */ 8632 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8633 8634 /* reg_rtdp_ipip_ipv6_usip_ptr 8635 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8636 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8637 * is to the KVD linear. 8638 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8639 * Access: RW 8640 */ 8641 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8642 8643 /* reg_rtdp_ipip_expected_gre_key 8644 * GRE key for checking. 8645 * Reserved when gre_key_check is '0'. 8646 * Access: RW 8647 */ 8648 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8649 8650 static inline void mlxsw_reg_rtdp_pack(char *payload, 8651 enum mlxsw_reg_rtdp_type type, 8652 u32 tunnel_index) 8653 { 8654 MLXSW_REG_ZERO(rtdp, payload); 8655 mlxsw_reg_rtdp_type_set(payload, type); 8656 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8657 } 8658 8659 static inline void 8660 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8661 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8662 unsigned int type_check, bool gre_key_check, 8663 u32 expected_gre_key) 8664 { 8665 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8666 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8667 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8668 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8669 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8670 } 8671 8672 static inline void 8673 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8674 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8675 unsigned int type_check, bool gre_key_check, 8676 u32 ipv4_usip, u32 expected_gre_key) 8677 { 8678 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8679 gre_key_check, expected_gre_key); 8680 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8681 } 8682 8683 static inline void 8684 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8685 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8686 unsigned int type_check, bool gre_key_check, 8687 u32 ipv6_usip_ptr, u32 expected_gre_key) 8688 { 8689 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8690 gre_key_check, expected_gre_key); 8691 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8692 } 8693 8694 /* RIPS - Router IP version Six Register 8695 * ------------------------------------- 8696 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8697 * IPinIP 8698 */ 8699 #define MLXSW_REG_RIPS_ID 0x8021 8700 #define MLXSW_REG_RIPS_LEN 0x14 8701 8702 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8703 8704 /* reg_rips_index 8705 * Index to IPv6 address. 8706 * For Spectrum, the index is to the KVD linear. 8707 * Access: Index 8708 */ 8709 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8710 8711 /* reg_rips_ipv6 8712 * IPv6 address 8713 * Access: RW 8714 */ 8715 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8716 8717 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8718 const struct in6_addr *ipv6) 8719 { 8720 MLXSW_REG_ZERO(rips, payload); 8721 mlxsw_reg_rips_index_set(payload, index); 8722 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8723 } 8724 8725 /* RATRAD - Router Adjacency Table Activity Dump Register 8726 * ------------------------------------------------------ 8727 * The RATRAD register is used to dump and optionally clear activity bits of 8728 * router adjacency table entries. 8729 */ 8730 #define MLXSW_REG_RATRAD_ID 0x8022 8731 #define MLXSW_REG_RATRAD_LEN 0x210 8732 8733 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8734 8735 enum { 8736 /* Read activity */ 8737 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8738 /* Read and clear activity */ 8739 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8740 }; 8741 8742 /* reg_ratrad_op 8743 * Access: Operation 8744 */ 8745 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8746 8747 /* reg_ratrad_ecmp_size 8748 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8749 * ranges: 8750 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8751 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8752 * Access: Index 8753 */ 8754 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8755 8756 /* reg_ratrad_adjacency_index 8757 * Index into the adjacency table. 8758 * Access: Index 8759 */ 8760 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8761 8762 /* reg_ratrad_activity_vector 8763 * Activity bit per adjacency index. 8764 * Bits higher than ecmp_size are reserved. 8765 * Access: RO 8766 */ 8767 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8768 8769 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8770 u16 ecmp_size) 8771 { 8772 MLXSW_REG_ZERO(ratrad, payload); 8773 mlxsw_reg_ratrad_op_set(payload, 8774 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8775 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8776 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8777 } 8778 8779 /* RIGR-V2 - Router Interface Group Register Version 2 8780 * --------------------------------------------------- 8781 * The RIGR_V2 register is used to add, remove and query egress interface list 8782 * of a multicast forwarding entry. 8783 */ 8784 #define MLXSW_REG_RIGR2_ID 0x8023 8785 #define MLXSW_REG_RIGR2_LEN 0xB0 8786 8787 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8788 8789 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8790 8791 /* reg_rigr2_rigr_index 8792 * KVD Linear index. 8793 * Access: Index 8794 */ 8795 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8796 8797 /* reg_rigr2_vnext 8798 * Next RIGR Index is valid. 8799 * Access: RW 8800 */ 8801 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8802 8803 /* reg_rigr2_next_rigr_index 8804 * Next RIGR Index. The index is to the KVD linear. 8805 * Reserved when vnxet = '0'. 8806 * Access: RW 8807 */ 8808 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8809 8810 /* reg_rigr2_vrmid 8811 * RMID Index is valid. 8812 * Access: RW 8813 */ 8814 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8815 8816 /* reg_rigr2_rmid_index 8817 * RMID Index. 8818 * Range 0 .. max_mid - 1 8819 * Reserved when vrmid = '0'. 8820 * The index is to the Port Group Table (PGT) 8821 * Access: RW 8822 */ 8823 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8824 8825 /* reg_rigr2_erif_entry_v 8826 * Egress Router Interface is valid. 8827 * Note that low-entries must be set if high-entries are set. For 8828 * example: if erif_entry[2].v is set then erif_entry[1].v and 8829 * erif_entry[0].v must be set. 8830 * Index can be from 0 to cap_mc_erif_list_entries-1 8831 * Access: RW 8832 */ 8833 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8834 8835 /* reg_rigr2_erif_entry_erif 8836 * Egress Router Interface. 8837 * Valid range is from 0 to cap_max_router_interfaces - 1 8838 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8839 * Access: RW 8840 */ 8841 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8842 8843 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8844 bool vnext, u32 next_rigr_index) 8845 { 8846 MLXSW_REG_ZERO(rigr2, payload); 8847 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8848 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8849 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8850 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8851 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8852 } 8853 8854 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8855 bool v, u16 erif) 8856 { 8857 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8858 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8859 } 8860 8861 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8862 * ------------------------------------------------------ 8863 */ 8864 #define MLXSW_REG_RECR2_ID 0x8025 8865 #define MLXSW_REG_RECR2_LEN 0x38 8866 8867 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8868 8869 /* reg_recr2_pp 8870 * Per-port configuration 8871 * Access: Index 8872 */ 8873 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8874 8875 /* reg_recr2_sh 8876 * Symmetric hash 8877 * Access: RW 8878 */ 8879 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8880 8881 /* reg_recr2_seed 8882 * Seed 8883 * Access: RW 8884 */ 8885 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8886 8887 enum { 8888 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8889 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8890 /* Enable IPv4 fields if packet is TCP or UDP */ 8891 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8892 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8893 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8894 /* Enable IPv6 fields if packet is TCP or UDP */ 8895 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8896 /* Enable TCP/UDP header fields if packet is IPv4 */ 8897 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8898 /* Enable TCP/UDP header fields if packet is IPv6 */ 8899 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8900 8901 __MLXSW_REG_RECR2_HEADER_CNT, 8902 }; 8903 8904 /* reg_recr2_outer_header_enables 8905 * Bit mask where each bit enables a specific layer to be included in 8906 * the hash calculation. 8907 * Access: RW 8908 */ 8909 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8910 8911 enum { 8912 /* IPv4 Source IP */ 8913 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8914 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8915 /* IPv4 Destination IP */ 8916 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8917 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8918 /* IP Protocol */ 8919 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8920 /* IPv6 Source IP */ 8921 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8922 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8923 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8924 /* IPv6 Destination IP */ 8925 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8926 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8927 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8928 /* IPv6 Next Header */ 8929 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8930 /* IPv6 Flow Label */ 8931 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8932 /* TCP/UDP Source Port */ 8933 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8934 /* TCP/UDP Destination Port */ 8935 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8936 8937 __MLXSW_REG_RECR2_FIELD_CNT, 8938 }; 8939 8940 /* reg_recr2_outer_header_fields_enable 8941 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8942 * Access: RW 8943 */ 8944 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8945 8946 /* reg_recr2_inner_header_enables 8947 * Bit mask where each bit enables a specific inner layer to be included in the 8948 * hash calculation. Same values as reg_recr2_outer_header_enables. 8949 * Access: RW 8950 */ 8951 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8952 8953 enum { 8954 /* Inner IPv4 Source IP */ 8955 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8956 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8957 /* Inner IPv4 Destination IP */ 8958 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8959 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8960 /* Inner IP Protocol */ 8961 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8962 /* Inner IPv6 Source IP */ 8963 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8964 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8965 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8966 /* Inner IPv6 Destination IP */ 8967 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8968 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8969 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8970 /* Inner IPv6 Next Header */ 8971 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8972 /* Inner IPv6 Flow Label */ 8973 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8974 /* Inner TCP/UDP Source Port */ 8975 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8976 /* Inner TCP/UDP Destination Port */ 8977 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8978 8979 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8980 }; 8981 8982 /* reg_recr2_inner_header_fields_enable 8983 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8984 * Access: RW 8985 */ 8986 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8987 8988 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8989 { 8990 MLXSW_REG_ZERO(recr2, payload); 8991 mlxsw_reg_recr2_pp_set(payload, false); 8992 mlxsw_reg_recr2_sh_set(payload, true); 8993 mlxsw_reg_recr2_seed_set(payload, seed); 8994 } 8995 8996 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8997 * -------------------------------------------------------------- 8998 * The RMFT_V2 register is used to configure and query the multicast table. 8999 */ 9000 #define MLXSW_REG_RMFT2_ID 0x8027 9001 #define MLXSW_REG_RMFT2_LEN 0x174 9002 9003 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 9004 9005 /* reg_rmft2_v 9006 * Valid 9007 * Access: RW 9008 */ 9009 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 9010 9011 enum mlxsw_reg_rmft2_type { 9012 MLXSW_REG_RMFT2_TYPE_IPV4, 9013 MLXSW_REG_RMFT2_TYPE_IPV6 9014 }; 9015 9016 /* reg_rmft2_type 9017 * Access: Index 9018 */ 9019 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 9020 9021 enum mlxsw_sp_reg_rmft2_op { 9022 /* For Write: 9023 * Write operation. Used to write a new entry to the table. All RW 9024 * fields are relevant for new entry. Activity bit is set for new 9025 * entries - Note write with v (Valid) 0 will delete the entry. 9026 * For Query: 9027 * Read operation 9028 */ 9029 MLXSW_REG_RMFT2_OP_READ_WRITE, 9030 }; 9031 9032 /* reg_rmft2_op 9033 * Operation. 9034 * Access: OP 9035 */ 9036 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 9037 9038 /* reg_rmft2_a 9039 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 9040 * entry. 9041 * Access: RO 9042 */ 9043 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 9044 9045 /* reg_rmft2_offset 9046 * Offset within the multicast forwarding table to write to. 9047 * Access: Index 9048 */ 9049 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 9050 9051 /* reg_rmft2_virtual_router 9052 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 9053 * Access: RW 9054 */ 9055 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 9056 9057 enum mlxsw_reg_rmft2_irif_mask { 9058 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 9059 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 9060 }; 9061 9062 /* reg_rmft2_irif_mask 9063 * Ingress RIF mask. 9064 * Access: RW 9065 */ 9066 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 9067 9068 /* reg_rmft2_irif 9069 * Ingress RIF index. 9070 * Access: RW 9071 */ 9072 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 9073 9074 /* reg_rmft2_dip{4,6} 9075 * Destination IPv4/6 address 9076 * Access: RW 9077 */ 9078 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 9079 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 9080 9081 /* reg_rmft2_dip{4,6}_mask 9082 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9083 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9084 * Access: RW 9085 */ 9086 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 9087 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 9088 9089 /* reg_rmft2_sip{4,6} 9090 * Source IPv4/6 address 9091 * Access: RW 9092 */ 9093 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 9094 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 9095 9096 /* reg_rmft2_sip{4,6}_mask 9097 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9098 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9099 * Access: RW 9100 */ 9101 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 9102 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 9103 9104 /* reg_rmft2_flexible_action_set 9105 * ACL action set. The only supported action types in this field and in any 9106 * action-set pointed from here are as follows: 9107 * 00h: ACTION_NULL 9108 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 9109 * 03h: ACTION_TRAP 9110 * 06h: ACTION_QOS 9111 * 08h: ACTION_POLICING_MONITORING 9112 * 10h: ACTION_ROUTER_MC 9113 * Access: RW 9114 */ 9115 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 9116 MLXSW_REG_FLEX_ACTION_SET_LEN); 9117 9118 static inline void 9119 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 9120 u16 virtual_router, 9121 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9122 const char *flex_action_set) 9123 { 9124 MLXSW_REG_ZERO(rmft2, payload); 9125 mlxsw_reg_rmft2_v_set(payload, v); 9126 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9127 mlxsw_reg_rmft2_offset_set(payload, offset); 9128 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9129 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9130 mlxsw_reg_rmft2_irif_set(payload, irif); 9131 if (flex_action_set) 9132 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9133 flex_action_set); 9134 } 9135 9136 static inline void 9137 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9138 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9139 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9140 const char *flexible_action_set) 9141 { 9142 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9143 irif_mask, irif, flexible_action_set); 9144 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9145 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9146 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9147 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9148 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9149 } 9150 9151 static inline void 9152 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9153 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9154 struct in6_addr dip6, struct in6_addr dip6_mask, 9155 struct in6_addr sip6, struct in6_addr sip6_mask, 9156 const char *flexible_action_set) 9157 { 9158 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9159 irif_mask, irif, flexible_action_set); 9160 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9161 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9162 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9163 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9164 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9165 } 9166 9167 /* REIV - Router Egress Interface to VID Register 9168 * ---------------------------------------------- 9169 * The REIV register maps {eRIF, egress_port} -> VID. 9170 * This mapping is done at the egress, after the ACLs. 9171 * This mapping always takes effect after router, regardless of cast 9172 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9173 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9174 * Reserved when the RIF is a loopback RIF. 9175 * 9176 * Note: Reserved when legacy bridge model is used. 9177 */ 9178 #define MLXSW_REG_REIV_ID 0x8034 9179 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9180 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9181 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9182 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9183 MLXSW_REG_REIV_REC_LEN * \ 9184 MLXSW_REG_REIV_REC_MAX_COUNT) 9185 9186 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9187 9188 /* reg_reiv_port_page 9189 * Port page - elport_record[0] is 256*port_page. 9190 * Access: Index 9191 */ 9192 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9193 9194 /* reg_reiv_erif 9195 * Egress RIF. 9196 * Range is 0..cap_max_router_interfaces-1. 9197 * Access: Index 9198 */ 9199 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9200 9201 /* reg_reiv_rec_update 9202 * Update enable (when write): 9203 * 0 - Do not update the entry. 9204 * 1 - Update the entry. 9205 * Access: OP 9206 */ 9207 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9208 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9209 9210 /* reg_reiv_rec_evid 9211 * Egress VID. 9212 * Range is 0..4095. 9213 * Access: RW 9214 */ 9215 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9216 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9217 9218 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9219 { 9220 MLXSW_REG_ZERO(reiv, payload); 9221 mlxsw_reg_reiv_port_page_set(payload, port_page); 9222 mlxsw_reg_reiv_erif_set(payload, erif); 9223 } 9224 9225 /* MFCR - Management Fan Control Register 9226 * -------------------------------------- 9227 * This register controls the settings of the Fan Speed PWM mechanism. 9228 */ 9229 #define MLXSW_REG_MFCR_ID 0x9001 9230 #define MLXSW_REG_MFCR_LEN 0x08 9231 9232 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9233 9234 enum mlxsw_reg_mfcr_pwm_frequency { 9235 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9236 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9237 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9238 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9239 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9240 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9241 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9242 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9243 }; 9244 9245 /* reg_mfcr_pwm_frequency 9246 * Controls the frequency of the PWM signal. 9247 * Access: RW 9248 */ 9249 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9250 9251 #define MLXSW_MFCR_TACHOS_MAX 10 9252 9253 /* reg_mfcr_tacho_active 9254 * Indicates which of the tachometer is active (bit per tachometer). 9255 * Access: RO 9256 */ 9257 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9258 9259 #define MLXSW_MFCR_PWMS_MAX 5 9260 9261 /* reg_mfcr_pwm_active 9262 * Indicates which of the PWM control is active (bit per PWM). 9263 * Access: RO 9264 */ 9265 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9266 9267 static inline void 9268 mlxsw_reg_mfcr_pack(char *payload, 9269 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9270 { 9271 MLXSW_REG_ZERO(mfcr, payload); 9272 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9273 } 9274 9275 static inline void 9276 mlxsw_reg_mfcr_unpack(char *payload, 9277 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9278 u16 *p_tacho_active, u8 *p_pwm_active) 9279 { 9280 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9281 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9282 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9283 } 9284 9285 /* MFSC - Management Fan Speed Control Register 9286 * -------------------------------------------- 9287 * This register controls the settings of the Fan Speed PWM mechanism. 9288 */ 9289 #define MLXSW_REG_MFSC_ID 0x9002 9290 #define MLXSW_REG_MFSC_LEN 0x08 9291 9292 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9293 9294 /* reg_mfsc_pwm 9295 * Fan pwm to control / monitor. 9296 * Access: Index 9297 */ 9298 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9299 9300 /* reg_mfsc_pwm_duty_cycle 9301 * Controls the duty cycle of the PWM. Value range from 0..255 to 9302 * represent duty cycle of 0%...100%. 9303 * Access: RW 9304 */ 9305 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9306 9307 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9308 u8 pwm_duty_cycle) 9309 { 9310 MLXSW_REG_ZERO(mfsc, payload); 9311 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9312 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9313 } 9314 9315 /* MFSM - Management Fan Speed Measurement 9316 * --------------------------------------- 9317 * This register controls the settings of the Tacho measurements and 9318 * enables reading the Tachometer measurements. 9319 */ 9320 #define MLXSW_REG_MFSM_ID 0x9003 9321 #define MLXSW_REG_MFSM_LEN 0x08 9322 9323 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9324 9325 /* reg_mfsm_tacho 9326 * Fan tachometer index. 9327 * Access: Index 9328 */ 9329 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9330 9331 /* reg_mfsm_rpm 9332 * Fan speed (round per minute). 9333 * Access: RO 9334 */ 9335 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9336 9337 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9338 { 9339 MLXSW_REG_ZERO(mfsm, payload); 9340 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9341 } 9342 9343 /* MFSL - Management Fan Speed Limit Register 9344 * ------------------------------------------ 9345 * The Fan Speed Limit register is used to configure the fan speed 9346 * event / interrupt notification mechanism. Fan speed threshold are 9347 * defined for both under-speed and over-speed. 9348 */ 9349 #define MLXSW_REG_MFSL_ID 0x9004 9350 #define MLXSW_REG_MFSL_LEN 0x0C 9351 9352 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9353 9354 /* reg_mfsl_tacho 9355 * Fan tachometer index. 9356 * Access: Index 9357 */ 9358 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9359 9360 /* reg_mfsl_tach_min 9361 * Tachometer minimum value (minimum RPM). 9362 * Access: RW 9363 */ 9364 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9365 9366 /* reg_mfsl_tach_max 9367 * Tachometer maximum value (maximum RPM). 9368 * Access: RW 9369 */ 9370 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9371 9372 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9373 u16 tach_min, u16 tach_max) 9374 { 9375 MLXSW_REG_ZERO(mfsl, payload); 9376 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9377 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9378 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9379 } 9380 9381 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9382 u16 *p_tach_min, u16 *p_tach_max) 9383 { 9384 if (p_tach_min) 9385 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9386 9387 if (p_tach_max) 9388 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9389 } 9390 9391 /* FORE - Fan Out of Range Event Register 9392 * -------------------------------------- 9393 * This register reports the status of the controlled fans compared to the 9394 * range defined by the MFSL register. 9395 */ 9396 #define MLXSW_REG_FORE_ID 0x9007 9397 #define MLXSW_REG_FORE_LEN 0x0C 9398 9399 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9400 9401 /* fan_under_limit 9402 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9403 * to a single tachometer and indicates the specific tachometer reading is 9404 * below the threshold. 9405 * Access: RO 9406 */ 9407 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9408 9409 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9410 bool *fault) 9411 { 9412 u16 limit; 9413 9414 if (fault) { 9415 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9416 *fault = limit & BIT(tacho); 9417 } 9418 } 9419 9420 /* MTCAP - Management Temperature Capabilities 9421 * ------------------------------------------- 9422 * This register exposes the capabilities of the device and 9423 * system temperature sensing. 9424 */ 9425 #define MLXSW_REG_MTCAP_ID 0x9009 9426 #define MLXSW_REG_MTCAP_LEN 0x08 9427 9428 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9429 9430 /* reg_mtcap_sensor_count 9431 * Number of sensors supported by the device. 9432 * This includes the QSFP module sensors (if exists in the QSFP module). 9433 * Access: RO 9434 */ 9435 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9436 9437 /* MTMP - Management Temperature 9438 * ----------------------------- 9439 * This register controls the settings of the temperature measurements 9440 * and enables reading the temperature measurements. Note that temperature 9441 * is in 0.125 degrees Celsius. 9442 */ 9443 #define MLXSW_REG_MTMP_ID 0x900A 9444 #define MLXSW_REG_MTMP_LEN 0x20 9445 9446 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9447 9448 /* reg_mtmp_slot_index 9449 * Slot index (0: Main board). 9450 * Access: Index 9451 */ 9452 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9453 9454 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9455 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9456 /* reg_mtmp_sensor_index 9457 * Sensors index to access. 9458 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9459 * (module 0 is mapped to sensor_index 64). 9460 * Access: Index 9461 */ 9462 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9463 9464 /* Convert to milli degrees Celsius */ 9465 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9466 ((v_) >= 0) ? ((v_) * 125) : \ 9467 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9468 * 125)); }) 9469 9470 /* reg_mtmp_max_operational_temperature 9471 * The highest temperature in the nominal operational range. Reading is in 9472 * 0.125 Celsius degrees units. 9473 * In case of module this is SFF critical temperature threshold. 9474 * Access: RO 9475 */ 9476 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9477 9478 /* reg_mtmp_temperature 9479 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9480 * degrees units. 9481 * Access: RO 9482 */ 9483 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9484 9485 /* reg_mtmp_mte 9486 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9487 * Access: RW 9488 */ 9489 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9490 9491 /* reg_mtmp_mtr 9492 * Max Temperature Reset - clears the value of the max temperature register. 9493 * Access: WO 9494 */ 9495 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9496 9497 /* reg_mtmp_max_temperature 9498 * The highest measured temperature from the sensor. 9499 * When the bit mte is cleared, the field max_temperature is reserved. 9500 * Access: RO 9501 */ 9502 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9503 9504 /* reg_mtmp_tee 9505 * Temperature Event Enable. 9506 * 0 - Do not generate event 9507 * 1 - Generate event 9508 * 2 - Generate single event 9509 * Access: RW 9510 */ 9511 9512 enum mlxsw_reg_mtmp_tee { 9513 MLXSW_REG_MTMP_TEE_NO_EVENT, 9514 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9515 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9516 }; 9517 9518 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9519 9520 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9521 9522 /* reg_mtmp_temperature_threshold_hi 9523 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9524 * Access: RW 9525 */ 9526 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9527 9528 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9529 /* reg_mtmp_temperature_threshold_lo 9530 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9531 * Access: RW 9532 */ 9533 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9534 9535 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9536 9537 /* reg_mtmp_sensor_name 9538 * Sensor Name 9539 * Access: RO 9540 */ 9541 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9542 9543 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9544 u16 sensor_index, bool max_temp_enable, 9545 bool max_temp_reset) 9546 { 9547 MLXSW_REG_ZERO(mtmp, payload); 9548 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9549 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9550 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9551 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9552 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9553 MLXSW_REG_MTMP_THRESH_HI); 9554 } 9555 9556 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9557 int *p_max_temp, int *p_temp_hi, 9558 int *p_max_oper_temp, 9559 char *sensor_name) 9560 { 9561 s16 temp; 9562 9563 if (p_temp) { 9564 temp = mlxsw_reg_mtmp_temperature_get(payload); 9565 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9566 } 9567 if (p_max_temp) { 9568 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9569 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9570 } 9571 if (p_temp_hi) { 9572 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9573 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9574 } 9575 if (p_max_oper_temp) { 9576 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9577 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9578 } 9579 if (sensor_name) 9580 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9581 } 9582 9583 /* MTWE - Management Temperature Warning Event 9584 * ------------------------------------------- 9585 * This register is used for over temperature warning. 9586 */ 9587 #define MLXSW_REG_MTWE_ID 0x900B 9588 #define MLXSW_REG_MTWE_LEN 0x10 9589 9590 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9591 9592 /* reg_mtwe_sensor_warning 9593 * Bit vector indicating which of the sensor reading is above threshold. 9594 * Address 00h bit31 is sensor_warning[127]. 9595 * Address 0Ch bit0 is sensor_warning[0]. 9596 * Access: RO 9597 */ 9598 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9599 9600 /* MTBR - Management Temperature Bulk Register 9601 * ------------------------------------------- 9602 * This register is used for bulk temperature reading. 9603 */ 9604 #define MLXSW_REG_MTBR_ID 0x900F 9605 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9606 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9607 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9608 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9609 MLXSW_REG_MTBR_REC_LEN * \ 9610 MLXSW_REG_MTBR_REC_MAX_COUNT) 9611 9612 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9613 9614 /* reg_mtbr_slot_index 9615 * Slot index (0: Main board). 9616 * Access: Index 9617 */ 9618 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9619 9620 /* reg_mtbr_base_sensor_index 9621 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9622 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9623 * Access: Index 9624 */ 9625 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9626 9627 /* reg_mtbr_num_rec 9628 * Request: Number of records to read 9629 * Response: Number of records read 9630 * See above description for more details. 9631 * Range 1..255 9632 * Access: RW 9633 */ 9634 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9635 9636 /* reg_mtbr_rec_max_temp 9637 * The highest measured temperature from the sensor. 9638 * When the bit mte is cleared, the field max_temperature is reserved. 9639 * Access: RO 9640 */ 9641 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9642 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9643 9644 /* reg_mtbr_rec_temp 9645 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9646 * degrees units. 9647 * Access: RO 9648 */ 9649 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9650 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9651 9652 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9653 u16 base_sensor_index, u8 num_rec) 9654 { 9655 MLXSW_REG_ZERO(mtbr, payload); 9656 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9657 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9658 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9659 } 9660 9661 /* Error codes from temperatute reading */ 9662 enum mlxsw_reg_mtbr_temp_status { 9663 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9664 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9665 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9666 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9667 }; 9668 9669 /* Base index for reading modules temperature */ 9670 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9671 9672 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9673 u16 *p_temp, u16 *p_max_temp) 9674 { 9675 if (p_temp) 9676 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9677 if (p_max_temp) 9678 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9679 } 9680 9681 /* MCIA - Management Cable Info Access 9682 * ----------------------------------- 9683 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9684 */ 9685 9686 #define MLXSW_REG_MCIA_ID 0x9014 9687 #define MLXSW_REG_MCIA_LEN 0x40 9688 9689 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9690 9691 /* reg_mcia_l 9692 * Lock bit. Setting this bit will lock the access to the specific 9693 * cable. Used for updating a full page in a cable EPROM. Any access 9694 * other then subsequence writes will fail while the port is locked. 9695 * Access: RW 9696 */ 9697 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9698 9699 /* reg_mcia_module 9700 * Module number. 9701 * Access: Index 9702 */ 9703 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9704 9705 /* reg_mcia_slot_index 9706 * Slot index (0: Main board) 9707 * Access: Index 9708 */ 9709 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9710 9711 enum { 9712 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9713 /* No response from module's EEPROM. */ 9714 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9715 /* Module type not supported by the device. */ 9716 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9717 /* No module present indication. */ 9718 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9719 /* Error occurred while trying to access module's EEPROM using I2C. */ 9720 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9721 /* Module is disabled. */ 9722 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9723 }; 9724 9725 /* reg_mcia_status 9726 * Module status. 9727 * Access: RO 9728 */ 9729 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9730 9731 /* reg_mcia_i2c_device_address 9732 * I2C device address. 9733 * Access: RW 9734 */ 9735 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9736 9737 /* reg_mcia_page_number 9738 * Page number. 9739 * Access: RW 9740 */ 9741 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9742 9743 /* reg_mcia_device_address 9744 * Device address. 9745 * Access: RW 9746 */ 9747 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9748 9749 /* reg_mcia_bank_number 9750 * Bank number. 9751 * Access: Index 9752 */ 9753 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9754 9755 /* reg_mcia_size 9756 * Number of bytes to read/write (up to 48 bytes). 9757 * Access: RW 9758 */ 9759 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9760 9761 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9762 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9763 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9764 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9765 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9766 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9767 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9768 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9769 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9770 #define MLXSW_REG_MCIA_PAGE0_LO 0 9771 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9772 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9773 9774 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9775 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9776 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9777 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9778 }; 9779 9780 enum mlxsw_reg_mcia_eeprom_module_info_id { 9781 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9782 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9783 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9784 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9785 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9786 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9787 }; 9788 9789 enum mlxsw_reg_mcia_eeprom_module_info { 9790 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9791 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9792 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9793 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9794 }; 9795 9796 /* reg_mcia_eeprom 9797 * Bytes to read/write. 9798 * Access: RW 9799 */ 9800 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9801 9802 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9803 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9804 * on offset 384 through 511, page 3 - on offset 512 through 639. 9805 */ 9806 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9807 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9808 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9809 9810 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9811 u8 lock, u8 page_number, 9812 u16 device_addr, u8 size, 9813 u8 i2c_device_addr) 9814 { 9815 MLXSW_REG_ZERO(mcia, payload); 9816 mlxsw_reg_mcia_slot_set(payload, slot_index); 9817 mlxsw_reg_mcia_module_set(payload, module); 9818 mlxsw_reg_mcia_l_set(payload, lock); 9819 mlxsw_reg_mcia_page_number_set(payload, page_number); 9820 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9821 mlxsw_reg_mcia_size_set(payload, size); 9822 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9823 } 9824 9825 /* MPAT - Monitoring Port Analyzer Table 9826 * ------------------------------------- 9827 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9828 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9829 */ 9830 #define MLXSW_REG_MPAT_ID 0x901A 9831 #define MLXSW_REG_MPAT_LEN 0x78 9832 9833 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9834 9835 /* reg_mpat_pa_id 9836 * Port Analyzer ID. 9837 * Access: Index 9838 */ 9839 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9840 9841 /* reg_mpat_session_id 9842 * Mirror Session ID. 9843 * Used for MIRROR_SESSION<i> trap. 9844 * Access: RW 9845 */ 9846 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9847 9848 /* reg_mpat_system_port 9849 * A unique port identifier for the final destination of the packet. 9850 * Access: RW 9851 */ 9852 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9853 9854 /* reg_mpat_e 9855 * Enable. Indicating the Port Analyzer is enabled. 9856 * Access: RW 9857 */ 9858 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9859 9860 /* reg_mpat_qos 9861 * Quality Of Service Mode. 9862 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9863 * PCP, DEI, DSCP or VL) are configured. 9864 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9865 * same as in the original packet that has triggered the mirroring. For 9866 * SPAN also the pcp,dei are maintained. 9867 * Access: RW 9868 */ 9869 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9870 9871 /* reg_mpat_be 9872 * Best effort mode. Indicates mirroring traffic should not cause packet 9873 * drop or back pressure, but will discard the mirrored packets. Mirrored 9874 * packets will be forwarded on a best effort manner. 9875 * 0: Do not discard mirrored packets 9876 * 1: Discard mirrored packets if causing congestion 9877 * Access: RW 9878 */ 9879 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9880 9881 enum mlxsw_reg_mpat_span_type { 9882 /* Local SPAN Ethernet. 9883 * The original packet is not encapsulated. 9884 */ 9885 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9886 9887 /* Remote SPAN Ethernet VLAN. 9888 * The packet is forwarded to the monitoring port on the monitoring 9889 * VLAN. 9890 */ 9891 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9892 9893 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9894 * The packet is encapsulated with GRE header. 9895 */ 9896 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9897 }; 9898 9899 /* reg_mpat_span_type 9900 * SPAN type. 9901 * Access: RW 9902 */ 9903 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9904 9905 /* reg_mpat_pide 9906 * Policer enable. 9907 * Access: RW 9908 */ 9909 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9910 9911 /* reg_mpat_pid 9912 * Policer ID. 9913 * Access: RW 9914 */ 9915 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9916 9917 /* Remote SPAN - Ethernet VLAN 9918 * - - - - - - - - - - - - - - 9919 */ 9920 9921 /* reg_mpat_eth_rspan_vid 9922 * Encapsulation header VLAN ID. 9923 * Access: RW 9924 */ 9925 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9926 9927 /* Encapsulated Remote SPAN - Ethernet L2 9928 * - - - - - - - - - - - - - - - - - - - 9929 */ 9930 9931 enum mlxsw_reg_mpat_eth_rspan_version { 9932 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9933 }; 9934 9935 /* reg_mpat_eth_rspan_version 9936 * RSPAN mirror header version. 9937 * Access: RW 9938 */ 9939 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9940 9941 /* reg_mpat_eth_rspan_mac 9942 * Destination MAC address. 9943 * Access: RW 9944 */ 9945 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9946 9947 /* reg_mpat_eth_rspan_tp 9948 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9949 * Access: RW 9950 */ 9951 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9952 9953 /* Encapsulated Remote SPAN - Ethernet L3 9954 * - - - - - - - - - - - - - - - - - - - 9955 */ 9956 9957 enum mlxsw_reg_mpat_eth_rspan_protocol { 9958 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9959 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9960 }; 9961 9962 /* reg_mpat_eth_rspan_protocol 9963 * SPAN encapsulation protocol. 9964 * Access: RW 9965 */ 9966 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9967 9968 /* reg_mpat_eth_rspan_ttl 9969 * Encapsulation header Time-to-Live/HopLimit. 9970 * Access: RW 9971 */ 9972 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9973 9974 /* reg_mpat_eth_rspan_smac 9975 * Source MAC address 9976 * Access: RW 9977 */ 9978 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9979 9980 /* reg_mpat_eth_rspan_dip* 9981 * Destination IP address. The IP version is configured by protocol. 9982 * Access: RW 9983 */ 9984 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9985 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9986 9987 /* reg_mpat_eth_rspan_sip* 9988 * Source IP address. The IP version is configured by protocol. 9989 * Access: RW 9990 */ 9991 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9992 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9993 9994 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9995 u16 system_port, bool e, 9996 enum mlxsw_reg_mpat_span_type span_type) 9997 { 9998 MLXSW_REG_ZERO(mpat, payload); 9999 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 10000 mlxsw_reg_mpat_system_port_set(payload, system_port); 10001 mlxsw_reg_mpat_e_set(payload, e); 10002 mlxsw_reg_mpat_qos_set(payload, 1); 10003 mlxsw_reg_mpat_be_set(payload, 1); 10004 mlxsw_reg_mpat_span_type_set(payload, span_type); 10005 } 10006 10007 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 10008 { 10009 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 10010 } 10011 10012 static inline void 10013 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 10014 enum mlxsw_reg_mpat_eth_rspan_version version, 10015 const char *mac, 10016 bool tp) 10017 { 10018 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 10019 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 10020 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 10021 } 10022 10023 static inline void 10024 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 10025 const char *smac, 10026 u32 sip, u32 dip) 10027 { 10028 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10029 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10030 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10031 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 10032 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 10033 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 10034 } 10035 10036 static inline void 10037 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 10038 const char *smac, 10039 struct in6_addr sip, struct in6_addr dip) 10040 { 10041 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10042 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10043 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10044 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 10045 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 10046 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 10047 } 10048 10049 /* MPAR - Monitoring Port Analyzer Register 10050 * ---------------------------------------- 10051 * MPAR register is used to query and configure the port analyzer port mirroring 10052 * properties. 10053 */ 10054 #define MLXSW_REG_MPAR_ID 0x901B 10055 #define MLXSW_REG_MPAR_LEN 0x0C 10056 10057 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 10058 10059 /* reg_mpar_local_port 10060 * The local port to mirror the packets from. 10061 * Access: Index 10062 */ 10063 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 10064 10065 enum mlxsw_reg_mpar_i_e { 10066 MLXSW_REG_MPAR_TYPE_EGRESS, 10067 MLXSW_REG_MPAR_TYPE_INGRESS, 10068 }; 10069 10070 /* reg_mpar_i_e 10071 * Ingress/Egress 10072 * Access: Index 10073 */ 10074 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10075 10076 /* reg_mpar_enable 10077 * Enable mirroring 10078 * By default, port mirroring is disabled for all ports. 10079 * Access: RW 10080 */ 10081 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10082 10083 /* reg_mpar_pa_id 10084 * Port Analyzer ID. 10085 * Access: RW 10086 */ 10087 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10088 10089 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10090 10091 /* reg_mpar_probability_rate 10092 * Sampling rate. 10093 * Valid values are: 1 to 3.5*10^9 10094 * Value of 1 means "sample all". Default is 1. 10095 * Reserved when Spectrum-1. 10096 * Access: RW 10097 */ 10098 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10099 10100 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 10101 enum mlxsw_reg_mpar_i_e i_e, 10102 bool enable, u8 pa_id, 10103 u32 probability_rate) 10104 { 10105 MLXSW_REG_ZERO(mpar, payload); 10106 mlxsw_reg_mpar_local_port_set(payload, local_port); 10107 mlxsw_reg_mpar_enable_set(payload, enable); 10108 mlxsw_reg_mpar_i_e_set(payload, i_e); 10109 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10110 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10111 } 10112 10113 /* MGIR - Management General Information Register 10114 * ---------------------------------------------- 10115 * MGIR register allows software to query the hardware and firmware general 10116 * information. 10117 */ 10118 #define MLXSW_REG_MGIR_ID 0x9020 10119 #define MLXSW_REG_MGIR_LEN 0x9C 10120 10121 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10122 10123 /* reg_mgir_hw_info_device_hw_revision 10124 * Access: RO 10125 */ 10126 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10127 10128 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10129 10130 /* reg_mgir_fw_info_psid 10131 * PSID (ASCII string). 10132 * Access: RO 10133 */ 10134 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10135 10136 /* reg_mgir_fw_info_extended_major 10137 * Access: RO 10138 */ 10139 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10140 10141 /* reg_mgir_fw_info_extended_minor 10142 * Access: RO 10143 */ 10144 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10145 10146 /* reg_mgir_fw_info_extended_sub_minor 10147 * Access: RO 10148 */ 10149 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10150 10151 static inline void mlxsw_reg_mgir_pack(char *payload) 10152 { 10153 MLXSW_REG_ZERO(mgir, payload); 10154 } 10155 10156 static inline void 10157 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10158 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10159 { 10160 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10161 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10162 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10163 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10164 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10165 } 10166 10167 /* MRSR - Management Reset and Shutdown Register 10168 * --------------------------------------------- 10169 * MRSR register is used to reset or shutdown the switch or 10170 * the entire system (when applicable). 10171 */ 10172 #define MLXSW_REG_MRSR_ID 0x9023 10173 #define MLXSW_REG_MRSR_LEN 0x08 10174 10175 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10176 10177 /* reg_mrsr_command 10178 * Reset/shutdown command 10179 * 0 - do nothing 10180 * 1 - software reset 10181 * Access: WO 10182 */ 10183 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10184 10185 static inline void mlxsw_reg_mrsr_pack(char *payload) 10186 { 10187 MLXSW_REG_ZERO(mrsr, payload); 10188 mlxsw_reg_mrsr_command_set(payload, 1); 10189 } 10190 10191 /* MLCR - Management LED Control Register 10192 * -------------------------------------- 10193 * Controls the system LEDs. 10194 */ 10195 #define MLXSW_REG_MLCR_ID 0x902B 10196 #define MLXSW_REG_MLCR_LEN 0x0C 10197 10198 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10199 10200 /* reg_mlcr_local_port 10201 * Local port number. 10202 * Access: RW 10203 */ 10204 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10205 10206 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10207 10208 /* reg_mlcr_beacon_duration 10209 * Duration of the beacon to be active, in seconds. 10210 * 0x0 - Will turn off the beacon. 10211 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10212 * Access: RW 10213 */ 10214 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10215 10216 /* reg_mlcr_beacon_remain 10217 * Remaining duration of the beacon, in seconds. 10218 * 0xFFFF indicates an infinite amount of time. 10219 * Access: RO 10220 */ 10221 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10222 10223 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10224 bool active) 10225 { 10226 MLXSW_REG_ZERO(mlcr, payload); 10227 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10228 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10229 MLXSW_REG_MLCR_DURATION_MAX : 0); 10230 } 10231 10232 /* MCION - Management Cable IO and Notifications Register 10233 * ------------------------------------------------------ 10234 * The MCION register is used to query transceiver modules' IO pins and other 10235 * notifications. 10236 */ 10237 #define MLXSW_REG_MCION_ID 0x9052 10238 #define MLXSW_REG_MCION_LEN 0x18 10239 10240 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10241 10242 /* reg_mcion_module 10243 * Module number. 10244 * Access: Index 10245 */ 10246 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10247 10248 /* reg_mcion_slot_index 10249 * Slot index. 10250 * Access: Index 10251 */ 10252 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10253 10254 enum { 10255 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10256 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10257 }; 10258 10259 /* reg_mcion_module_status_bits 10260 * Module IO status as defined by SFF. 10261 * Access: RO 10262 */ 10263 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10264 10265 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10266 { 10267 MLXSW_REG_ZERO(mcion, payload); 10268 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10269 mlxsw_reg_mcion_module_set(payload, module); 10270 } 10271 10272 /* MTPPS - Management Pulse Per Second Register 10273 * -------------------------------------------- 10274 * This register provides the device PPS capabilities, configure the PPS in and 10275 * out modules and holds the PPS in time stamp. 10276 */ 10277 #define MLXSW_REG_MTPPS_ID 0x9053 10278 #define MLXSW_REG_MTPPS_LEN 0x3C 10279 10280 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10281 10282 /* reg_mtpps_enable 10283 * Enables the PPS functionality the specific pin. 10284 * A boolean variable. 10285 * Access: RW 10286 */ 10287 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10288 10289 enum mlxsw_reg_mtpps_pin_mode { 10290 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10291 }; 10292 10293 /* reg_mtpps_pin_mode 10294 * Pin mode to be used. The mode must comply with the supported modes of the 10295 * requested pin. 10296 * Access: RW 10297 */ 10298 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10299 10300 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10301 10302 /* reg_mtpps_pin 10303 * Pin to be configured or queried out of the supported pins. 10304 * Access: Index 10305 */ 10306 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10307 10308 /* reg_mtpps_time_stamp 10309 * When pin_mode = pps_in, the latched device time when it was triggered from 10310 * the external GPIO pin. 10311 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10312 * time to generate next output signal. 10313 * Time is in units of device clock. 10314 * Access: RW 10315 */ 10316 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10317 10318 static inline void 10319 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10320 { 10321 MLXSW_REG_ZERO(mtpps, payload); 10322 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10323 mlxsw_reg_mtpps_pin_mode_set(payload, 10324 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10325 mlxsw_reg_mtpps_enable_set(payload, true); 10326 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10327 } 10328 10329 /* MTUTC - Management UTC Register 10330 * ------------------------------- 10331 * Configures the HW UTC counter. 10332 */ 10333 #define MLXSW_REG_MTUTC_ID 0x9055 10334 #define MLXSW_REG_MTUTC_LEN 0x1C 10335 10336 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10337 10338 enum mlxsw_reg_mtutc_operation { 10339 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10340 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10341 }; 10342 10343 /* reg_mtutc_operation 10344 * Operation. 10345 * Access: OP 10346 */ 10347 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10348 10349 /* reg_mtutc_freq_adjustment 10350 * Frequency adjustment: Every PPS the HW frequency will be 10351 * adjusted by this value. Units of HW clock, where HW counts 10352 * 10^9 HW clocks for 1 HW second. 10353 * Access: RW 10354 */ 10355 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10356 10357 /* reg_mtutc_utc_sec 10358 * UTC seconds. 10359 * Access: WO 10360 */ 10361 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10362 10363 static inline void 10364 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10365 u32 freq_adj, u32 utc_sec) 10366 { 10367 MLXSW_REG_ZERO(mtutc, payload); 10368 mlxsw_reg_mtutc_operation_set(payload, oper); 10369 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10370 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10371 } 10372 10373 /* MCQI - Management Component Query Information 10374 * --------------------------------------------- 10375 * This register allows querying information about firmware components. 10376 */ 10377 #define MLXSW_REG_MCQI_ID 0x9061 10378 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10379 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10380 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10381 10382 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10383 10384 /* reg_mcqi_component_index 10385 * Index of the accessed component. 10386 * Access: Index 10387 */ 10388 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10389 10390 enum mlxfw_reg_mcqi_info_type { 10391 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10392 }; 10393 10394 /* reg_mcqi_info_type 10395 * Component properties set. 10396 * Access: RW 10397 */ 10398 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10399 10400 /* reg_mcqi_offset 10401 * The requested/returned data offset from the section start, given in bytes. 10402 * Must be DWORD aligned. 10403 * Access: RW 10404 */ 10405 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10406 10407 /* reg_mcqi_data_size 10408 * The requested/returned data size, given in bytes. If data_size is not DWORD 10409 * aligned, the last bytes are zero padded. 10410 * Access: RW 10411 */ 10412 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10413 10414 /* reg_mcqi_cap_max_component_size 10415 * Maximum size for this component, given in bytes. 10416 * Access: RO 10417 */ 10418 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10419 10420 /* reg_mcqi_cap_log_mcda_word_size 10421 * Log 2 of the access word size in bytes. Read and write access must be aligned 10422 * to the word size. Write access must be done for an integer number of words. 10423 * Access: RO 10424 */ 10425 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10426 10427 /* reg_mcqi_cap_mcda_max_write_size 10428 * Maximal write size for MCDA register 10429 * Access: RO 10430 */ 10431 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10432 10433 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10434 { 10435 MLXSW_REG_ZERO(mcqi, payload); 10436 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10437 mlxsw_reg_mcqi_info_type_set(payload, 10438 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10439 mlxsw_reg_mcqi_offset_set(payload, 0); 10440 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10441 } 10442 10443 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10444 u32 *p_cap_max_component_size, 10445 u8 *p_cap_log_mcda_word_size, 10446 u16 *p_cap_mcda_max_write_size) 10447 { 10448 *p_cap_max_component_size = 10449 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10450 *p_cap_log_mcda_word_size = 10451 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10452 *p_cap_mcda_max_write_size = 10453 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10454 } 10455 10456 /* MCC - Management Component Control 10457 * ---------------------------------- 10458 * Controls the firmware component and updates the FSM. 10459 */ 10460 #define MLXSW_REG_MCC_ID 0x9062 10461 #define MLXSW_REG_MCC_LEN 0x1C 10462 10463 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10464 10465 enum mlxsw_reg_mcc_instruction { 10466 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10467 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10468 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10469 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10470 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10471 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10472 }; 10473 10474 /* reg_mcc_instruction 10475 * Command to be executed by the FSM. 10476 * Applicable for write operation only. 10477 * Access: RW 10478 */ 10479 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10480 10481 /* reg_mcc_component_index 10482 * Index of the accessed component. Applicable only for commands that 10483 * refer to components. Otherwise, this field is reserved. 10484 * Access: Index 10485 */ 10486 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10487 10488 /* reg_mcc_update_handle 10489 * Token representing the current flow executed by the FSM. 10490 * Access: WO 10491 */ 10492 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10493 10494 /* reg_mcc_error_code 10495 * Indicates the successful completion of the instruction, or the reason it 10496 * failed 10497 * Access: RO 10498 */ 10499 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10500 10501 /* reg_mcc_control_state 10502 * Current FSM state 10503 * Access: RO 10504 */ 10505 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10506 10507 /* reg_mcc_component_size 10508 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10509 * the size may shorten the update time. Value 0x0 means that size is 10510 * unspecified. 10511 * Access: WO 10512 */ 10513 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10514 10515 static inline void mlxsw_reg_mcc_pack(char *payload, 10516 enum mlxsw_reg_mcc_instruction instr, 10517 u16 component_index, u32 update_handle, 10518 u32 component_size) 10519 { 10520 MLXSW_REG_ZERO(mcc, payload); 10521 mlxsw_reg_mcc_instruction_set(payload, instr); 10522 mlxsw_reg_mcc_component_index_set(payload, component_index); 10523 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10524 mlxsw_reg_mcc_component_size_set(payload, component_size); 10525 } 10526 10527 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10528 u8 *p_error_code, u8 *p_control_state) 10529 { 10530 if (p_update_handle) 10531 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10532 if (p_error_code) 10533 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10534 if (p_control_state) 10535 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10536 } 10537 10538 /* MCDA - Management Component Data Access 10539 * --------------------------------------- 10540 * This register allows reading and writing a firmware component. 10541 */ 10542 #define MLXSW_REG_MCDA_ID 0x9063 10543 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10544 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10545 #define MLXSW_REG_MCDA_LEN \ 10546 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10547 10548 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10549 10550 /* reg_mcda_update_handle 10551 * Token representing the current flow executed by the FSM. 10552 * Access: RW 10553 */ 10554 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10555 10556 /* reg_mcda_offset 10557 * Offset of accessed address relative to component start. Accesses must be in 10558 * accordance to log_mcda_word_size in MCQI reg. 10559 * Access: RW 10560 */ 10561 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10562 10563 /* reg_mcda_size 10564 * Size of the data accessed, given in bytes. 10565 * Access: RW 10566 */ 10567 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10568 10569 /* reg_mcda_data 10570 * Data block accessed. 10571 * Access: RW 10572 */ 10573 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10574 10575 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10576 u32 offset, u16 size, u8 *data) 10577 { 10578 int i; 10579 10580 MLXSW_REG_ZERO(mcda, payload); 10581 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10582 mlxsw_reg_mcda_offset_set(payload, offset); 10583 mlxsw_reg_mcda_size_set(payload, size); 10584 10585 for (i = 0; i < size / 4; i++) 10586 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10587 } 10588 10589 /* MPSC - Monitoring Packet Sampling Configuration Register 10590 * -------------------------------------------------------- 10591 * MPSC Register is used to configure the Packet Sampling mechanism. 10592 */ 10593 #define MLXSW_REG_MPSC_ID 0x9080 10594 #define MLXSW_REG_MPSC_LEN 0x1C 10595 10596 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10597 10598 /* reg_mpsc_local_port 10599 * Local port number 10600 * Not supported for CPU port 10601 * Access: Index 10602 */ 10603 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10604 10605 /* reg_mpsc_e 10606 * Enable sampling on port local_port 10607 * Access: RW 10608 */ 10609 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10610 10611 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10612 10613 /* reg_mpsc_rate 10614 * Sampling rate = 1 out of rate packets (with randomization around 10615 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10616 * Access: RW 10617 */ 10618 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10619 10620 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10621 u32 rate) 10622 { 10623 MLXSW_REG_ZERO(mpsc, payload); 10624 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10625 mlxsw_reg_mpsc_e_set(payload, e); 10626 mlxsw_reg_mpsc_rate_set(payload, rate); 10627 } 10628 10629 /* MGPC - Monitoring General Purpose Counter Set Register 10630 * The MGPC register retrieves and sets the General Purpose Counter Set. 10631 */ 10632 #define MLXSW_REG_MGPC_ID 0x9081 10633 #define MLXSW_REG_MGPC_LEN 0x18 10634 10635 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10636 10637 /* reg_mgpc_counter_set_type 10638 * Counter set type. 10639 * Access: OP 10640 */ 10641 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10642 10643 /* reg_mgpc_counter_index 10644 * Counter index. 10645 * Access: Index 10646 */ 10647 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10648 10649 enum mlxsw_reg_mgpc_opcode { 10650 /* Nop */ 10651 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10652 /* Clear counters */ 10653 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10654 }; 10655 10656 /* reg_mgpc_opcode 10657 * Opcode. 10658 * Access: OP 10659 */ 10660 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10661 10662 /* reg_mgpc_byte_counter 10663 * Byte counter value. 10664 * Access: RW 10665 */ 10666 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10667 10668 /* reg_mgpc_packet_counter 10669 * Packet counter value. 10670 * Access: RW 10671 */ 10672 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10673 10674 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10675 enum mlxsw_reg_mgpc_opcode opcode, 10676 enum mlxsw_reg_flow_counter_set_type set_type) 10677 { 10678 MLXSW_REG_ZERO(mgpc, payload); 10679 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10680 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10681 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10682 } 10683 10684 /* MPRS - Monitoring Parsing State Register 10685 * ---------------------------------------- 10686 * The MPRS register is used for setting up the parsing for hash, 10687 * policy-engine and routing. 10688 */ 10689 #define MLXSW_REG_MPRS_ID 0x9083 10690 #define MLXSW_REG_MPRS_LEN 0x14 10691 10692 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10693 10694 /* reg_mprs_parsing_depth 10695 * Minimum parsing depth. 10696 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10697 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10698 * Access: RW 10699 */ 10700 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10701 10702 /* reg_mprs_parsing_en 10703 * Parsing enable. 10704 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10705 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10706 * Access: RW 10707 */ 10708 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10709 10710 /* reg_mprs_vxlan_udp_dport 10711 * VxLAN UDP destination port. 10712 * Used for identifying VxLAN packets and for dport field in 10713 * encapsulation. Default is 4789. 10714 * Access: RW 10715 */ 10716 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10717 10718 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10719 u16 vxlan_udp_dport) 10720 { 10721 MLXSW_REG_ZERO(mprs, payload); 10722 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10723 mlxsw_reg_mprs_parsing_en_set(payload, true); 10724 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10725 } 10726 10727 /* MOGCR - Monitoring Global Configuration Register 10728 * ------------------------------------------------ 10729 */ 10730 #define MLXSW_REG_MOGCR_ID 0x9086 10731 #define MLXSW_REG_MOGCR_LEN 0x20 10732 10733 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10734 10735 /* reg_mogcr_ptp_iftc 10736 * PTP Ingress FIFO Trap Clear 10737 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10738 * to this value. Default 0. 10739 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10740 * Access: RW 10741 */ 10742 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10743 10744 /* reg_mogcr_ptp_eftc 10745 * PTP Egress FIFO Trap Clear 10746 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10747 * to this value. Default 0. 10748 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10749 * Access: RW 10750 */ 10751 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10752 10753 /* reg_mogcr_mirroring_pid_base 10754 * Base policer id for mirroring policers. 10755 * Must have an even value (e.g. 1000, not 1001). 10756 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10757 * Access: RW 10758 */ 10759 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10760 10761 /* MPAGR - Monitoring Port Analyzer Global Register 10762 * ------------------------------------------------ 10763 * This register is used for global port analyzer configurations. 10764 * Note: This register is not supported by current FW versions for Spectrum-1. 10765 */ 10766 #define MLXSW_REG_MPAGR_ID 0x9089 10767 #define MLXSW_REG_MPAGR_LEN 0x0C 10768 10769 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10770 10771 enum mlxsw_reg_mpagr_trigger { 10772 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10773 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10774 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10775 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10776 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10777 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10778 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10779 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10780 }; 10781 10782 /* reg_mpagr_trigger 10783 * Mirror trigger. 10784 * Access: Index 10785 */ 10786 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10787 10788 /* reg_mpagr_pa_id 10789 * Port analyzer ID. 10790 * Access: RW 10791 */ 10792 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10793 10794 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10795 10796 /* reg_mpagr_probability_rate 10797 * Sampling rate. 10798 * Valid values are: 1 to 3.5*10^9 10799 * Value of 1 means "sample all". Default is 1. 10800 * Access: RW 10801 */ 10802 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10803 10804 static inline void mlxsw_reg_mpagr_pack(char *payload, 10805 enum mlxsw_reg_mpagr_trigger trigger, 10806 u8 pa_id, u32 probability_rate) 10807 { 10808 MLXSW_REG_ZERO(mpagr, payload); 10809 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10810 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10811 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10812 } 10813 10814 /* MOMTE - Monitoring Mirror Trigger Enable Register 10815 * ------------------------------------------------- 10816 * This register is used to configure the mirror enable for different mirror 10817 * reasons. 10818 */ 10819 #define MLXSW_REG_MOMTE_ID 0x908D 10820 #define MLXSW_REG_MOMTE_LEN 0x10 10821 10822 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10823 10824 /* reg_momte_local_port 10825 * Local port number. 10826 * Access: Index 10827 */ 10828 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10829 10830 enum mlxsw_reg_momte_type { 10831 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10832 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10833 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10834 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10835 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10836 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10837 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10838 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10839 }; 10840 10841 /* reg_momte_type 10842 * Type of mirroring. 10843 * Access: Index 10844 */ 10845 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10846 10847 /* reg_momte_tclass_en 10848 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10849 * 0: disable (default) 10850 * 1: enable 10851 * Access: RW 10852 */ 10853 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10854 10855 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10856 enum mlxsw_reg_momte_type type) 10857 { 10858 MLXSW_REG_ZERO(momte, payload); 10859 mlxsw_reg_momte_local_port_set(payload, local_port); 10860 mlxsw_reg_momte_type_set(payload, type); 10861 } 10862 10863 /* MTPPPC - Time Precision Packet Port Configuration 10864 * ------------------------------------------------- 10865 * This register serves for configuration of which PTP messages should be 10866 * timestamped. This is a global configuration, despite the register name. 10867 * 10868 * Reserved when Spectrum-2. 10869 */ 10870 #define MLXSW_REG_MTPPPC_ID 0x9090 10871 #define MLXSW_REG_MTPPPC_LEN 0x28 10872 10873 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10874 10875 /* reg_mtpppc_ing_timestamp_message_type 10876 * Bitwise vector of PTP message types to timestamp at ingress. 10877 * MessageType field as defined by IEEE 1588 10878 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10879 * Default all 0 10880 * Access: RW 10881 */ 10882 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10883 10884 /* reg_mtpppc_egr_timestamp_message_type 10885 * Bitwise vector of PTP message types to timestamp at egress. 10886 * MessageType field as defined by IEEE 1588 10887 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10888 * Default all 0 10889 * Access: RW 10890 */ 10891 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10892 10893 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10894 { 10895 MLXSW_REG_ZERO(mtpppc, payload); 10896 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10897 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10898 } 10899 10900 /* MTPPTR - Time Precision Packet Timestamping Reading 10901 * --------------------------------------------------- 10902 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10903 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10904 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10905 * trapped. The sequence number is used to synchronize the timestamp FIFO 10906 * entries and the trapped packets. 10907 * Reserved when Spectrum-2. 10908 */ 10909 10910 #define MLXSW_REG_MTPPTR_ID 0x9091 10911 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10912 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10913 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10914 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10915 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10916 10917 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10918 10919 /* reg_mtpptr_local_port 10920 * Not supported for CPU port. 10921 * Access: Index 10922 */ 10923 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10924 10925 enum mlxsw_reg_mtpptr_dir { 10926 MLXSW_REG_MTPPTR_DIR_INGRESS, 10927 MLXSW_REG_MTPPTR_DIR_EGRESS, 10928 }; 10929 10930 /* reg_mtpptr_dir 10931 * Direction. 10932 * Access: Index 10933 */ 10934 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10935 10936 /* reg_mtpptr_clr 10937 * Clear the records. 10938 * Access: OP 10939 */ 10940 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10941 10942 /* reg_mtpptr_num_rec 10943 * Number of valid records in the response 10944 * Range 0.. cap_ptp_timestamp_fifo 10945 * Access: RO 10946 */ 10947 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10948 10949 /* reg_mtpptr_rec_message_type 10950 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10951 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10952 * Access: RO 10953 */ 10954 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10955 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10956 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10957 10958 /* reg_mtpptr_rec_domain_number 10959 * DomainNumber field as defined by IEEE 1588 10960 * Access: RO 10961 */ 10962 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10963 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10964 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10965 10966 /* reg_mtpptr_rec_sequence_id 10967 * SequenceId field as defined by IEEE 1588 10968 * Access: RO 10969 */ 10970 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10971 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10972 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10973 10974 /* reg_mtpptr_rec_timestamp_high 10975 * Timestamp of when the PTP packet has passed through the port Units of PLL 10976 * clock time. 10977 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10978 * Access: RO 10979 */ 10980 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10981 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10982 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10983 10984 /* reg_mtpptr_rec_timestamp_low 10985 * See rec_timestamp_high. 10986 * Access: RO 10987 */ 10988 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10989 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10990 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10991 10992 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10993 unsigned int rec, 10994 u8 *p_message_type, 10995 u8 *p_domain_number, 10996 u16 *p_sequence_id, 10997 u64 *p_timestamp) 10998 { 10999 u32 timestamp_high, timestamp_low; 11000 11001 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 11002 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 11003 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 11004 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 11005 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 11006 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 11007 } 11008 11009 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 11010 * --------------------------------------------------------- 11011 * This register is used for configuring under which trap to deliver PTP 11012 * packets depending on type of the packet. 11013 */ 11014 #define MLXSW_REG_MTPTPT_ID 0x9092 11015 #define MLXSW_REG_MTPTPT_LEN 0x08 11016 11017 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 11018 11019 enum mlxsw_reg_mtptpt_trap_id { 11020 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 11021 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 11022 }; 11023 11024 /* reg_mtptpt_trap_id 11025 * Trap id. 11026 * Access: Index 11027 */ 11028 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 11029 11030 /* reg_mtptpt_message_type 11031 * Bitwise vector of PTP message types to trap. This is a necessary but 11032 * non-sufficient condition since need to enable also per port. See MTPPPC. 11033 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 11034 * Bit0: Sync, Bit1: Delay_Req) 11035 */ 11036 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 11037 11038 static inline void mlxsw_reg_mtptptp_pack(char *payload, 11039 enum mlxsw_reg_mtptpt_trap_id trap_id, 11040 u16 message_type) 11041 { 11042 MLXSW_REG_ZERO(mtptpt, payload); 11043 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 11044 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 11045 } 11046 11047 /* MFGD - Monitoring FW General Debug Register 11048 * ------------------------------------------- 11049 */ 11050 #define MLXSW_REG_MFGD_ID 0x90F0 11051 #define MLXSW_REG_MFGD_LEN 0x0C 11052 11053 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11054 11055 /* reg_mfgd_fw_fatal_event_mode 11056 * 0 - don't check FW fatal (default) 11057 * 1 - check FW fatal - enable MFDE trap 11058 * Access: RW 11059 */ 11060 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11061 11062 /* reg_mfgd_trigger_test 11063 * Access: WO 11064 */ 11065 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11066 11067 /* MGPIR - Management General Peripheral Information Register 11068 * ---------------------------------------------------------- 11069 * MGPIR register allows software to query the hardware and 11070 * firmware general information of peripheral entities. 11071 */ 11072 #define MLXSW_REG_MGPIR_ID 0x9100 11073 #define MLXSW_REG_MGPIR_LEN 0xA0 11074 11075 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11076 11077 enum mlxsw_reg_mgpir_device_type { 11078 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11079 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11080 }; 11081 11082 /* mgpir_slot_index 11083 * Slot index (0: Main board). 11084 * Access: Index 11085 */ 11086 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11087 11088 /* mgpir_device_type 11089 * Access: RO 11090 */ 11091 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11092 11093 /* mgpir_devices_per_flash 11094 * Number of devices of device_type per flash (can be shared by few devices). 11095 * Access: RO 11096 */ 11097 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11098 11099 /* mgpir_num_of_devices 11100 * Number of devices of device_type. 11101 * Access: RO 11102 */ 11103 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11104 11105 /* max_modules_per_slot 11106 * Maximum number of modules that can be connected per slot. 11107 * Access: RO 11108 */ 11109 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11110 11111 /* mgpir_num_of_slots 11112 * Number of slots in the system. 11113 * Access: RO 11114 */ 11115 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11116 11117 /* mgpir_num_of_modules 11118 * Number of modules. 11119 * Access: RO 11120 */ 11121 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11122 11123 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11124 { 11125 MLXSW_REG_ZERO(mgpir, payload); 11126 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11127 } 11128 11129 static inline void 11130 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11131 enum mlxsw_reg_mgpir_device_type *device_type, 11132 u8 *devices_per_flash, u8 *num_of_modules, 11133 u8 *num_of_slots) 11134 { 11135 if (num_of_devices) 11136 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11137 if (device_type) 11138 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11139 if (devices_per_flash) 11140 *devices_per_flash = 11141 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11142 if (num_of_modules) 11143 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11144 if (num_of_slots) 11145 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11146 } 11147 11148 /* MBCT - Management Binary Code Transfer Register 11149 * ----------------------------------------------- 11150 * This register allows to transfer binary codes from the host to 11151 * the management FW by transferring it by chunks of maximum 1KB. 11152 */ 11153 #define MLXSW_REG_MBCT_ID 0x9120 11154 #define MLXSW_REG_MBCT_LEN 0x420 11155 11156 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11157 11158 /* reg_mbct_slot_index 11159 * Slot index. 0 is reserved. 11160 * Access: Index 11161 */ 11162 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11163 11164 /* reg_mbct_data_size 11165 * Actual data field size in bytes for the current data transfer. 11166 * Access: WO 11167 */ 11168 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11169 11170 enum mlxsw_reg_mbct_op { 11171 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11172 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11173 MLXSW_REG_MBCT_OP_ACTIVATE, 11174 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11175 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11176 }; 11177 11178 /* reg_mbct_op 11179 * Access: WO 11180 */ 11181 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11182 11183 /* reg_mbct_last 11184 * Indicates that the current data field is the last chunk of the INI. 11185 * Access: WO 11186 */ 11187 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11188 11189 /* reg_mbct_oee 11190 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11191 * was executed and the fsm_state has changed. 11192 * Access: WO 11193 */ 11194 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11195 11196 enum mlxsw_reg_mbct_status { 11197 /* Partial data transfer completed successfully and ready for next 11198 * data transfer. 11199 */ 11200 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11201 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11202 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11203 /* Error - trying to erase INI while it being used. */ 11204 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11205 /* Last data transfer completed, applying magic pattern. */ 11206 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11207 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11208 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11209 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11210 }; 11211 11212 /* reg_mbct_status 11213 * Status. 11214 * Access: RO 11215 */ 11216 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11217 11218 enum mlxsw_reg_mbct_fsm_state { 11219 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11220 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11221 }; 11222 11223 /* reg_mbct_fsm_state 11224 * FSM state. 11225 * Access: RO 11226 */ 11227 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11228 11229 #define MLXSW_REG_MBCT_DATA_LEN 1024 11230 11231 /* reg_mbct_data 11232 * Up to 1KB of data. 11233 * Access: WO 11234 */ 11235 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11236 11237 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11238 enum mlxsw_reg_mbct_op op, bool oee) 11239 { 11240 MLXSW_REG_ZERO(mbct, payload); 11241 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11242 mlxsw_reg_mbct_op_set(payload, op); 11243 mlxsw_reg_mbct_oee_set(payload, oee); 11244 } 11245 11246 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11247 u16 data_size, bool last, 11248 const char *data) 11249 { 11250 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11251 return; 11252 mlxsw_reg_mbct_data_size_set(payload, data_size); 11253 mlxsw_reg_mbct_last_set(payload, last); 11254 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11255 } 11256 11257 static inline void 11258 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11259 enum mlxsw_reg_mbct_status *p_status, 11260 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11261 { 11262 if (p_slot_index) 11263 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11264 *p_status = mlxsw_reg_mbct_status_get(payload); 11265 if (p_fsm_state) 11266 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11267 } 11268 11269 /* MDDQ - Management DownStream Device Query Register 11270 * -------------------------------------------------- 11271 * This register allows to query the DownStream device properties. The desired 11272 * information is chosen upon the query_type field and is delivered by 32B 11273 * of data blocks. 11274 */ 11275 #define MLXSW_REG_MDDQ_ID 0x9161 11276 #define MLXSW_REG_MDDQ_LEN 0x30 11277 11278 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11279 11280 /* reg_mddq_sie 11281 * Slot info event enable. 11282 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11283 * active / ready will generate a DSDSC event. 11284 * Access: RW 11285 */ 11286 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11287 11288 enum mlxsw_reg_mddq_query_type { 11289 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11290 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME = 3, 11291 }; 11292 11293 /* reg_mddq_query_type 11294 * Access: Index 11295 */ 11296 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11297 11298 /* reg_mddq_slot_index 11299 * Slot index. 0 is reserved. 11300 * Access: Index 11301 */ 11302 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11303 11304 /* reg_mddq_slot_info_provisioned 11305 * If set, the INI file is applied and the card is provisioned. 11306 * Access: RO 11307 */ 11308 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11309 11310 /* reg_mddq_slot_info_sr_valid 11311 * If set, Shift Register is valid (after being provisioned) and data 11312 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11313 * Access: RO 11314 */ 11315 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11316 11317 enum mlxsw_reg_mddq_slot_info_ready { 11318 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11319 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11320 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11321 }; 11322 11323 /* reg_mddq_slot_info_lc_ready 11324 * If set, the LC is powered on, matching the INI version and a new FW 11325 * version can be burnt (if necessary). 11326 * Access: RO 11327 */ 11328 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11329 11330 /* reg_mddq_slot_info_active 11331 * If set, the FW has completed the MDDC.device_enable command. 11332 * Access: RO 11333 */ 11334 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11335 11336 /* reg_mddq_slot_info_hw_revision 11337 * Major user-configured version number of the current INI file. 11338 * Valid only when active or ready are '1'. 11339 * Access: RO 11340 */ 11341 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11342 11343 /* reg_mddq_slot_info_ini_file_version 11344 * User-configured version number of the current INI file. 11345 * Valid only when active or lc_ready are '1'. 11346 * Access: RO 11347 */ 11348 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11349 11350 /* reg_mddq_slot_info_card_type 11351 * Access: RO 11352 */ 11353 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11354 11355 static inline void 11356 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11357 enum mlxsw_reg_mddq_query_type query_type) 11358 { 11359 MLXSW_REG_ZERO(mddq, payload); 11360 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11361 mlxsw_reg_mddq_query_type_set(payload, query_type); 11362 } 11363 11364 static inline void 11365 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11366 { 11367 __mlxsw_reg_mddq_pack(payload, slot_index, 11368 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11369 mlxsw_reg_mddq_sie_set(payload, sie); 11370 } 11371 11372 static inline void 11373 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11374 bool *p_provisioned, bool *p_sr_valid, 11375 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11376 bool *p_active, u16 *p_hw_revision, 11377 u16 *p_ini_file_version, 11378 u8 *p_card_type) 11379 { 11380 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11381 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11382 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11383 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11384 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11385 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11386 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11387 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11388 } 11389 11390 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11391 11392 /* reg_mddq_slot_ascii_name 11393 * Slot's ASCII name. 11394 * Access: RO 11395 */ 11396 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11397 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11398 11399 static inline void 11400 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11401 { 11402 __mlxsw_reg_mddq_pack(payload, slot_index, 11403 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11404 } 11405 11406 static inline void 11407 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11408 { 11409 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11410 } 11411 11412 /* MDDC - Management DownStream Device Control Register 11413 * ---------------------------------------------------- 11414 * This register allows to control downstream devices and line cards. 11415 */ 11416 #define MLXSW_REG_MDDC_ID 0x9163 11417 #define MLXSW_REG_MDDC_LEN 0x30 11418 11419 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11420 11421 /* reg_mddc_slot_index 11422 * Slot index. 0 is reserved. 11423 * Access: Index 11424 */ 11425 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11426 11427 /* reg_mddc_rst 11428 * Reset request. 11429 * Access: OP 11430 */ 11431 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11432 11433 /* reg_mddc_device_enable 11434 * When set, FW is the manager and allowed to program the downstream device. 11435 * Access: RW 11436 */ 11437 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11438 11439 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11440 bool device_enable) 11441 { 11442 MLXSW_REG_ZERO(mddc, payload); 11443 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11444 mlxsw_reg_mddc_rst_set(payload, rst); 11445 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11446 } 11447 11448 /* MFDE - Monitoring FW Debug Register 11449 * ----------------------------------- 11450 */ 11451 #define MLXSW_REG_MFDE_ID 0x9200 11452 #define MLXSW_REG_MFDE_LEN 0x30 11453 11454 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11455 11456 /* reg_mfde_irisc_id 11457 * Which irisc triggered the event 11458 * Access: RO 11459 */ 11460 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11461 11462 enum mlxsw_reg_mfde_severity { 11463 /* Unrecoverable switch behavior */ 11464 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11465 /* Unexpected state with possible systemic failure */ 11466 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11467 /* Unexpected state without systemic failure */ 11468 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11469 }; 11470 11471 /* reg_mfde_severity 11472 * The severity of the event. 11473 * Access: RO 11474 */ 11475 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11476 11477 enum mlxsw_reg_mfde_event_id { 11478 /* CRspace timeout */ 11479 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11480 /* KVD insertion machine stopped */ 11481 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11482 /* Triggered by MFGD.trigger_test */ 11483 MLXSW_REG_MFDE_EVENT_ID_TEST, 11484 /* Triggered when firmware hits an assert */ 11485 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11486 /* Fatal error interrupt from hardware */ 11487 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11488 }; 11489 11490 /* reg_mfde_event_id 11491 * Access: RO 11492 */ 11493 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11494 11495 enum mlxsw_reg_mfde_method { 11496 MLXSW_REG_MFDE_METHOD_QUERY, 11497 MLXSW_REG_MFDE_METHOD_WRITE, 11498 }; 11499 11500 /* reg_mfde_method 11501 * Access: RO 11502 */ 11503 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11504 11505 /* reg_mfde_long_process 11506 * Indicates if the command is in long_process mode. 11507 * Access: RO 11508 */ 11509 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11510 11511 enum mlxsw_reg_mfde_command_type { 11512 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11513 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11514 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11515 }; 11516 11517 /* reg_mfde_command_type 11518 * Access: RO 11519 */ 11520 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11521 11522 /* reg_mfde_reg_attr_id 11523 * EMAD - register id, MAD - attibute id 11524 * Access: RO 11525 */ 11526 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11527 11528 /* reg_mfde_crspace_to_log_address 11529 * crspace address accessed, which resulted in timeout. 11530 * Access: RO 11531 */ 11532 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11533 11534 /* reg_mfde_crspace_to_oe 11535 * 0 - New event 11536 * 1 - Old event, occurred before MFGD activation. 11537 * Access: RO 11538 */ 11539 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11540 11541 /* reg_mfde_crspace_to_log_id 11542 * Which irisc triggered the timeout. 11543 * Access: RO 11544 */ 11545 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11546 11547 /* reg_mfde_crspace_to_log_ip 11548 * IP (instruction pointer) that triggered the timeout. 11549 * Access: RO 11550 */ 11551 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11552 11553 /* reg_mfde_kvd_im_stop_oe 11554 * 0 - New event 11555 * 1 - Old event, occurred before MFGD activation. 11556 * Access: RO 11557 */ 11558 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11559 11560 /* reg_mfde_kvd_im_stop_pipes_mask 11561 * Bit per kvh pipe. 11562 * Access: RO 11563 */ 11564 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11565 11566 /* reg_mfde_fw_assert_var0-4 11567 * Variables passed to assert. 11568 * Access: RO 11569 */ 11570 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11571 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11572 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11573 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11574 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11575 11576 /* reg_mfde_fw_assert_existptr 11577 * The instruction pointer when assert was triggered. 11578 * Access: RO 11579 */ 11580 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11581 11582 /* reg_mfde_fw_assert_callra 11583 * The return address after triggering assert. 11584 * Access: RO 11585 */ 11586 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11587 11588 /* reg_mfde_fw_assert_oe 11589 * 0 - New event 11590 * 1 - Old event, occurred before MFGD activation. 11591 * Access: RO 11592 */ 11593 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11594 11595 /* reg_mfde_fw_assert_tile_v 11596 * 0: The assert was from main 11597 * 1: The assert was from a tile 11598 * Access: RO 11599 */ 11600 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11601 11602 /* reg_mfde_fw_assert_tile_index 11603 * When tile_v=1, the tile_index that caused the assert. 11604 * Access: RO 11605 */ 11606 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11607 11608 /* reg_mfde_fw_assert_ext_synd 11609 * A generated one-to-one identifier which is specific per-assert. 11610 * Access: RO 11611 */ 11612 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11613 11614 /* reg_mfde_fatal_cause_id 11615 * HW interrupt cause id. 11616 * Access: RO 11617 */ 11618 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11619 11620 /* reg_mfde_fatal_cause_tile_v 11621 * 0: The assert was from main 11622 * 1: The assert was from a tile 11623 * Access: RO 11624 */ 11625 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11626 11627 /* reg_mfde_fatal_cause_tile_index 11628 * When tile_v=1, the tile_index that caused the assert. 11629 * Access: RO 11630 */ 11631 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11632 11633 /* TNGCR - Tunneling NVE General Configuration Register 11634 * ---------------------------------------------------- 11635 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11636 */ 11637 #define MLXSW_REG_TNGCR_ID 0xA001 11638 #define MLXSW_REG_TNGCR_LEN 0x44 11639 11640 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11641 11642 enum mlxsw_reg_tngcr_type { 11643 MLXSW_REG_TNGCR_TYPE_VXLAN, 11644 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11645 MLXSW_REG_TNGCR_TYPE_GENEVE, 11646 MLXSW_REG_TNGCR_TYPE_NVGRE, 11647 }; 11648 11649 /* reg_tngcr_type 11650 * Tunnel type for encapsulation and decapsulation. The types are mutually 11651 * exclusive. 11652 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11653 * Access: RW 11654 */ 11655 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11656 11657 /* reg_tngcr_nve_valid 11658 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11659 * Access: RW 11660 */ 11661 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11662 11663 /* reg_tngcr_nve_ttl_uc 11664 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11665 * Access: RW 11666 */ 11667 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11668 11669 /* reg_tngcr_nve_ttl_mc 11670 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11671 * Access: RW 11672 */ 11673 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11674 11675 enum { 11676 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11677 MLXSW_REG_TNGCR_FL_NO_COPY, 11678 /* Copy flow label from inner packet if packet is IPv6 and 11679 * encapsulation is by IPv6. Otherwise, calculate flow label using 11680 * nve_flh. 11681 */ 11682 MLXSW_REG_TNGCR_FL_COPY, 11683 }; 11684 11685 /* reg_tngcr_nve_flc 11686 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11687 * Access: RW 11688 */ 11689 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11690 11691 enum { 11692 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11693 * uses {nve_fl_prefix, nve_fl_suffix}. 11694 */ 11695 MLXSW_REG_TNGCR_FL_NO_HASH, 11696 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11697 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11698 */ 11699 MLXSW_REG_TNGCR_FL_HASH, 11700 }; 11701 11702 /* reg_tngcr_nve_flh 11703 * NVE flow label hash. 11704 * Access: RW 11705 */ 11706 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11707 11708 /* reg_tngcr_nve_fl_prefix 11709 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11710 * Access: RW 11711 */ 11712 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11713 11714 /* reg_tngcr_nve_fl_suffix 11715 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11716 * Reserved when nve_flh=1 and for Spectrum. 11717 * Access: RW 11718 */ 11719 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11720 11721 enum { 11722 /* Source UDP port is fixed (default '0') */ 11723 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11724 /* Source UDP port is calculated based on hash */ 11725 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11726 }; 11727 11728 /* reg_tngcr_nve_udp_sport_type 11729 * NVE UDP source port type. 11730 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11731 * When the source UDP port is calculated based on hash, then the 8 LSBs 11732 * are calculated from hash the 8 MSBs are configured by 11733 * nve_udp_sport_prefix. 11734 * Access: RW 11735 */ 11736 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11737 11738 /* reg_tngcr_nve_udp_sport_prefix 11739 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11740 * Reserved when NVE type is NVGRE. 11741 * Access: RW 11742 */ 11743 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11744 11745 /* reg_tngcr_nve_group_size_mc 11746 * The amount of sequential linked lists of MC entries. The first linked 11747 * list is configured by SFD.underlay_mc_ptr. 11748 * Valid values: 1, 2, 4, 8, 16, 32, 64 11749 * The linked list are configured by TNUMT. 11750 * The hash is set by LAG hash. 11751 * Access: RW 11752 */ 11753 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11754 11755 /* reg_tngcr_nve_group_size_flood 11756 * The amount of sequential linked lists of flooding entries. The first 11757 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11758 * Valid values: 1, 2, 4, 8, 16, 32, 64 11759 * The linked list are configured by TNUMT. 11760 * The hash is set by LAG hash. 11761 * Access: RW 11762 */ 11763 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11764 11765 /* reg_tngcr_learn_enable 11766 * During decapsulation, whether to learn from NVE port. 11767 * Reserved when Spectrum-2. See TNPC. 11768 * Access: RW 11769 */ 11770 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11771 11772 /* reg_tngcr_underlay_virtual_router 11773 * Underlay virtual router. 11774 * Reserved when Spectrum-2. 11775 * Access: RW 11776 */ 11777 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11778 11779 /* reg_tngcr_underlay_rif 11780 * Underlay ingress router interface. RIF type should be loopback generic. 11781 * Reserved when Spectrum. 11782 * Access: RW 11783 */ 11784 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11785 11786 /* reg_tngcr_usipv4 11787 * Underlay source IPv4 address of the NVE. 11788 * Access: RW 11789 */ 11790 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11791 11792 /* reg_tngcr_usipv6 11793 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11794 * modified under traffic of NVE tunneling encapsulation. 11795 * Access: RW 11796 */ 11797 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11798 11799 static inline void mlxsw_reg_tngcr_pack(char *payload, 11800 enum mlxsw_reg_tngcr_type type, 11801 bool valid, u8 ttl) 11802 { 11803 MLXSW_REG_ZERO(tngcr, payload); 11804 mlxsw_reg_tngcr_type_set(payload, type); 11805 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11806 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11807 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11808 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11809 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11810 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11811 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11812 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11813 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11814 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11815 } 11816 11817 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11818 * ------------------------------------------------------- 11819 * The TNUMT register is for building the underlay MC table. It is used 11820 * for MC, flooding and BC traffic into the NVE tunnel. 11821 */ 11822 #define MLXSW_REG_TNUMT_ID 0xA003 11823 #define MLXSW_REG_TNUMT_LEN 0x20 11824 11825 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11826 11827 enum mlxsw_reg_tnumt_record_type { 11828 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11829 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11830 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11831 }; 11832 11833 /* reg_tnumt_record_type 11834 * Record type. 11835 * Access: RW 11836 */ 11837 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11838 11839 /* reg_tnumt_tunnel_port 11840 * Tunnel port. 11841 * Access: RW 11842 */ 11843 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11844 11845 /* reg_tnumt_underlay_mc_ptr 11846 * Index to the underlay multicast table. 11847 * For Spectrum the index is to the KVD linear. 11848 * Access: Index 11849 */ 11850 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11851 11852 /* reg_tnumt_vnext 11853 * The next_underlay_mc_ptr is valid. 11854 * Access: RW 11855 */ 11856 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11857 11858 /* reg_tnumt_next_underlay_mc_ptr 11859 * The next index to the underlay multicast table. 11860 * Access: RW 11861 */ 11862 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11863 11864 /* reg_tnumt_record_size 11865 * Number of IP addresses in the record. 11866 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11867 * Access: RW 11868 */ 11869 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11870 11871 /* reg_tnumt_udip 11872 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11873 * Access: RW 11874 */ 11875 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11876 11877 /* reg_tnumt_udip_ptr 11878 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11879 * i >= size. The IPv6 addresses are configured by RIPS. 11880 * Access: RW 11881 */ 11882 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11883 11884 static inline void mlxsw_reg_tnumt_pack(char *payload, 11885 enum mlxsw_reg_tnumt_record_type type, 11886 enum mlxsw_reg_tunnel_port tport, 11887 u32 underlay_mc_ptr, bool vnext, 11888 u32 next_underlay_mc_ptr, 11889 u8 record_size) 11890 { 11891 MLXSW_REG_ZERO(tnumt, payload); 11892 mlxsw_reg_tnumt_record_type_set(payload, type); 11893 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 11894 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 11895 mlxsw_reg_tnumt_vnext_set(payload, vnext); 11896 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 11897 mlxsw_reg_tnumt_record_size_set(payload, record_size); 11898 } 11899 11900 /* TNQCR - Tunneling NVE QoS Configuration Register 11901 * ------------------------------------------------ 11902 * The TNQCR register configures how QoS is set in encapsulation into the 11903 * underlay network. 11904 */ 11905 #define MLXSW_REG_TNQCR_ID 0xA010 11906 #define MLXSW_REG_TNQCR_LEN 0x0C 11907 11908 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 11909 11910 /* reg_tnqcr_enc_set_dscp 11911 * For encapsulation: How to set DSCP field: 11912 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 11913 * (outer) IP header. If there is no IP header, use TNQDR.dscp 11914 * 1 - Set the DSCP field as TNQDR.dscp 11915 * Access: RW 11916 */ 11917 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 11918 11919 static inline void mlxsw_reg_tnqcr_pack(char *payload) 11920 { 11921 MLXSW_REG_ZERO(tnqcr, payload); 11922 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 11923 } 11924 11925 /* TNQDR - Tunneling NVE QoS Default Register 11926 * ------------------------------------------ 11927 * The TNQDR register configures the default QoS settings for NVE 11928 * encapsulation. 11929 */ 11930 #define MLXSW_REG_TNQDR_ID 0xA011 11931 #define MLXSW_REG_TNQDR_LEN 0x08 11932 11933 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 11934 11935 /* reg_tnqdr_local_port 11936 * Local port number (receive port). CPU port is supported. 11937 * Access: Index 11938 */ 11939 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 11940 11941 /* reg_tnqdr_dscp 11942 * For encapsulation, the default DSCP. 11943 * Access: RW 11944 */ 11945 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 11946 11947 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 11948 { 11949 MLXSW_REG_ZERO(tnqdr, payload); 11950 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 11951 mlxsw_reg_tnqdr_dscp_set(payload, 0); 11952 } 11953 11954 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 11955 * -------------------------------------------------------- 11956 * The TNEEM register maps ECN of the IP header at the ingress to the 11957 * encapsulation to the ECN of the underlay network. 11958 */ 11959 #define MLXSW_REG_TNEEM_ID 0xA012 11960 #define MLXSW_REG_TNEEM_LEN 0x0C 11961 11962 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 11963 11964 /* reg_tneem_overlay_ecn 11965 * ECN of the IP header in the overlay network. 11966 * Access: Index 11967 */ 11968 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 11969 11970 /* reg_tneem_underlay_ecn 11971 * ECN of the IP header in the underlay network. 11972 * Access: RW 11973 */ 11974 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 11975 11976 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 11977 u8 underlay_ecn) 11978 { 11979 MLXSW_REG_ZERO(tneem, payload); 11980 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 11981 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 11982 } 11983 11984 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 11985 * -------------------------------------------------------- 11986 * The TNDEM register configures the actions that are done in the 11987 * decapsulation. 11988 */ 11989 #define MLXSW_REG_TNDEM_ID 0xA013 11990 #define MLXSW_REG_TNDEM_LEN 0x0C 11991 11992 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 11993 11994 /* reg_tndem_underlay_ecn 11995 * ECN field of the IP header in the underlay network. 11996 * Access: Index 11997 */ 11998 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 11999 12000 /* reg_tndem_overlay_ecn 12001 * ECN field of the IP header in the overlay network. 12002 * Access: Index 12003 */ 12004 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12005 12006 /* reg_tndem_eip_ecn 12007 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12008 * from the decapsulation. 12009 * Access: RW 12010 */ 12011 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12012 12013 /* reg_tndem_trap_en 12014 * Trap enable: 12015 * 0 - No trap due to decap ECN 12016 * 1 - Trap enable with trap_id 12017 * Access: RW 12018 */ 12019 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12020 12021 /* reg_tndem_trap_id 12022 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12023 * Reserved when trap_en is '0'. 12024 * Access: RW 12025 */ 12026 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12027 12028 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12029 u8 overlay_ecn, u8 ecn, bool trap_en, 12030 u16 trap_id) 12031 { 12032 MLXSW_REG_ZERO(tndem, payload); 12033 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12034 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12035 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12036 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12037 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12038 } 12039 12040 /* TNPC - Tunnel Port Configuration Register 12041 * ----------------------------------------- 12042 * The TNPC register is used for tunnel port configuration. 12043 * Reserved when Spectrum. 12044 */ 12045 #define MLXSW_REG_TNPC_ID 0xA020 12046 #define MLXSW_REG_TNPC_LEN 0x18 12047 12048 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12049 12050 /* reg_tnpc_tunnel_port 12051 * Tunnel port. 12052 * Access: Index 12053 */ 12054 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12055 12056 /* reg_tnpc_learn_enable_v6 12057 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12058 * Access: RW 12059 */ 12060 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12061 12062 /* reg_tnpc_learn_enable_v4 12063 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12064 * Access: RW 12065 */ 12066 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12067 12068 static inline void mlxsw_reg_tnpc_pack(char *payload, 12069 enum mlxsw_reg_tunnel_port tport, 12070 bool learn_enable) 12071 { 12072 MLXSW_REG_ZERO(tnpc, payload); 12073 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12074 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12075 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12076 } 12077 12078 /* TIGCR - Tunneling IPinIP General Configuration Register 12079 * ------------------------------------------------------- 12080 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12081 */ 12082 #define MLXSW_REG_TIGCR_ID 0xA801 12083 #define MLXSW_REG_TIGCR_LEN 0x10 12084 12085 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12086 12087 /* reg_tigcr_ipip_ttlc 12088 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12089 * header. 12090 * Access: RW 12091 */ 12092 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12093 12094 /* reg_tigcr_ipip_ttl_uc 12095 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12096 * reg_tigcr_ipip_ttlc is unset. 12097 * Access: RW 12098 */ 12099 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12100 12101 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12102 { 12103 MLXSW_REG_ZERO(tigcr, payload); 12104 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12105 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12106 } 12107 12108 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12109 * ----------------------------------------------------------- 12110 * The TIEEM register maps ECN of the IP header at the ingress to the 12111 * encapsulation to the ECN of the underlay network. 12112 */ 12113 #define MLXSW_REG_TIEEM_ID 0xA812 12114 #define MLXSW_REG_TIEEM_LEN 0x0C 12115 12116 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12117 12118 /* reg_tieem_overlay_ecn 12119 * ECN of the IP header in the overlay network. 12120 * Access: Index 12121 */ 12122 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12123 12124 /* reg_tineem_underlay_ecn 12125 * ECN of the IP header in the underlay network. 12126 * Access: RW 12127 */ 12128 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12129 12130 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12131 u8 underlay_ecn) 12132 { 12133 MLXSW_REG_ZERO(tieem, payload); 12134 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12135 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12136 } 12137 12138 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12139 * ----------------------------------------------------------- 12140 * The TIDEM register configures the actions that are done in the 12141 * decapsulation. 12142 */ 12143 #define MLXSW_REG_TIDEM_ID 0xA813 12144 #define MLXSW_REG_TIDEM_LEN 0x0C 12145 12146 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12147 12148 /* reg_tidem_underlay_ecn 12149 * ECN field of the IP header in the underlay network. 12150 * Access: Index 12151 */ 12152 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12153 12154 /* reg_tidem_overlay_ecn 12155 * ECN field of the IP header in the overlay network. 12156 * Access: Index 12157 */ 12158 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12159 12160 /* reg_tidem_eip_ecn 12161 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12162 * from the decapsulation. 12163 * Access: RW 12164 */ 12165 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12166 12167 /* reg_tidem_trap_en 12168 * Trap enable: 12169 * 0 - No trap due to decap ECN 12170 * 1 - Trap enable with trap_id 12171 * Access: RW 12172 */ 12173 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12174 12175 /* reg_tidem_trap_id 12176 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12177 * Reserved when trap_en is '0'. 12178 * Access: RW 12179 */ 12180 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12181 12182 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12183 u8 overlay_ecn, u8 eip_ecn, 12184 bool trap_en, u16 trap_id) 12185 { 12186 MLXSW_REG_ZERO(tidem, payload); 12187 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12188 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12189 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12190 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12191 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12192 } 12193 12194 /* SBPR - Shared Buffer Pools Register 12195 * ----------------------------------- 12196 * The SBPR configures and retrieves the shared buffer pools and configuration. 12197 */ 12198 #define MLXSW_REG_SBPR_ID 0xB001 12199 #define MLXSW_REG_SBPR_LEN 0x14 12200 12201 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12202 12203 /* reg_sbpr_desc 12204 * When set, configures descriptor buffer. 12205 * Access: Index 12206 */ 12207 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12208 12209 /* shared direstion enum for SBPR, SBCM, SBPM */ 12210 enum mlxsw_reg_sbxx_dir { 12211 MLXSW_REG_SBXX_DIR_INGRESS, 12212 MLXSW_REG_SBXX_DIR_EGRESS, 12213 }; 12214 12215 /* reg_sbpr_dir 12216 * Direction. 12217 * Access: Index 12218 */ 12219 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12220 12221 /* reg_sbpr_pool 12222 * Pool index. 12223 * Access: Index 12224 */ 12225 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12226 12227 /* reg_sbpr_infi_size 12228 * Size is infinite. 12229 * Access: RW 12230 */ 12231 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12232 12233 /* reg_sbpr_size 12234 * Pool size in buffer cells. 12235 * Reserved when infi_size = 1. 12236 * Access: RW 12237 */ 12238 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12239 12240 enum mlxsw_reg_sbpr_mode { 12241 MLXSW_REG_SBPR_MODE_STATIC, 12242 MLXSW_REG_SBPR_MODE_DYNAMIC, 12243 }; 12244 12245 /* reg_sbpr_mode 12246 * Pool quota calculation mode. 12247 * Access: RW 12248 */ 12249 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12250 12251 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12252 enum mlxsw_reg_sbxx_dir dir, 12253 enum mlxsw_reg_sbpr_mode mode, u32 size, 12254 bool infi_size) 12255 { 12256 MLXSW_REG_ZERO(sbpr, payload); 12257 mlxsw_reg_sbpr_pool_set(payload, pool); 12258 mlxsw_reg_sbpr_dir_set(payload, dir); 12259 mlxsw_reg_sbpr_mode_set(payload, mode); 12260 mlxsw_reg_sbpr_size_set(payload, size); 12261 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12262 } 12263 12264 /* SBCM - Shared Buffer Class Management Register 12265 * ---------------------------------------------- 12266 * The SBCM register configures and retrieves the shared buffer allocation 12267 * and configuration according to Port-PG, including the binding to pool 12268 * and definition of the associated quota. 12269 */ 12270 #define MLXSW_REG_SBCM_ID 0xB002 12271 #define MLXSW_REG_SBCM_LEN 0x28 12272 12273 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12274 12275 /* reg_sbcm_local_port 12276 * Local port number. 12277 * For Ingress: excludes CPU port and Router port 12278 * For Egress: excludes IP Router 12279 * Access: Index 12280 */ 12281 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12282 12283 /* reg_sbcm_pg_buff 12284 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12285 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12286 * For traffic class: range is 0..cap_max_tclass - 1 12287 * Note that when traffic class is in MC aware mode then the traffic 12288 * classes which are MC aware cannot be configured. 12289 * Access: Index 12290 */ 12291 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12292 12293 /* reg_sbcm_dir 12294 * Direction. 12295 * Access: Index 12296 */ 12297 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12298 12299 /* reg_sbcm_min_buff 12300 * Minimum buffer size for the limiter, in cells. 12301 * Access: RW 12302 */ 12303 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12304 12305 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12306 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12307 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12308 12309 /* reg_sbcm_infi_max 12310 * Max buffer is infinite. 12311 * Access: RW 12312 */ 12313 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12314 12315 /* reg_sbcm_max_buff 12316 * When the pool associated to the port-pg/tclass is configured to 12317 * static, Maximum buffer size for the limiter configured in cells. 12318 * When the pool associated to the port-pg/tclass is configured to 12319 * dynamic, the max_buff holds the "alpha" parameter, supporting 12320 * the following values: 12321 * 0: 0 12322 * i: (1/128)*2^(i-1), for i=1..14 12323 * 0xFF: Infinity 12324 * Reserved when infi_max = 1. 12325 * Access: RW 12326 */ 12327 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12328 12329 /* reg_sbcm_pool 12330 * Association of the port-priority to a pool. 12331 * Access: RW 12332 */ 12333 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12334 12335 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12336 enum mlxsw_reg_sbxx_dir dir, 12337 u32 min_buff, u32 max_buff, 12338 bool infi_max, u8 pool) 12339 { 12340 MLXSW_REG_ZERO(sbcm, payload); 12341 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12342 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12343 mlxsw_reg_sbcm_dir_set(payload, dir); 12344 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12345 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12346 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12347 mlxsw_reg_sbcm_pool_set(payload, pool); 12348 } 12349 12350 /* SBPM - Shared Buffer Port Management Register 12351 * --------------------------------------------- 12352 * The SBPM register configures and retrieves the shared buffer allocation 12353 * and configuration according to Port-Pool, including the definition 12354 * of the associated quota. 12355 */ 12356 #define MLXSW_REG_SBPM_ID 0xB003 12357 #define MLXSW_REG_SBPM_LEN 0x28 12358 12359 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12360 12361 /* reg_sbpm_local_port 12362 * Local port number. 12363 * For Ingress: excludes CPU port and Router port 12364 * For Egress: excludes IP Router 12365 * Access: Index 12366 */ 12367 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12368 12369 /* reg_sbpm_pool 12370 * The pool associated to quota counting on the local_port. 12371 * Access: Index 12372 */ 12373 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12374 12375 /* reg_sbpm_dir 12376 * Direction. 12377 * Access: Index 12378 */ 12379 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12380 12381 /* reg_sbpm_buff_occupancy 12382 * Current buffer occupancy in cells. 12383 * Access: RO 12384 */ 12385 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12386 12387 /* reg_sbpm_clr 12388 * Clear Max Buffer Occupancy 12389 * When this bit is set, max_buff_occupancy field is cleared (and a 12390 * new max value is tracked from the time the clear was performed). 12391 * Access: OP 12392 */ 12393 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12394 12395 /* reg_sbpm_max_buff_occupancy 12396 * Maximum value of buffer occupancy in cells monitored. Cleared by 12397 * writing to the clr field. 12398 * Access: RO 12399 */ 12400 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12401 12402 /* reg_sbpm_min_buff 12403 * Minimum buffer size for the limiter, in cells. 12404 * Access: RW 12405 */ 12406 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12407 12408 /* reg_sbpm_max_buff 12409 * When the pool associated to the port-pg/tclass is configured to 12410 * static, Maximum buffer size for the limiter configured in cells. 12411 * When the pool associated to the port-pg/tclass is configured to 12412 * dynamic, the max_buff holds the "alpha" parameter, supporting 12413 * the following values: 12414 * 0: 0 12415 * i: (1/128)*2^(i-1), for i=1..14 12416 * 0xFF: Infinity 12417 * Access: RW 12418 */ 12419 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12420 12421 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12422 enum mlxsw_reg_sbxx_dir dir, bool clr, 12423 u32 min_buff, u32 max_buff) 12424 { 12425 MLXSW_REG_ZERO(sbpm, payload); 12426 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12427 mlxsw_reg_sbpm_pool_set(payload, pool); 12428 mlxsw_reg_sbpm_dir_set(payload, dir); 12429 mlxsw_reg_sbpm_clr_set(payload, clr); 12430 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12431 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12432 } 12433 12434 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12435 u32 *p_max_buff_occupancy) 12436 { 12437 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12438 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12439 } 12440 12441 /* SBMM - Shared Buffer Multicast Management Register 12442 * -------------------------------------------------- 12443 * The SBMM register configures and retrieves the shared buffer allocation 12444 * and configuration for MC packets according to Switch-Priority, including 12445 * the binding to pool and definition of the associated quota. 12446 */ 12447 #define MLXSW_REG_SBMM_ID 0xB004 12448 #define MLXSW_REG_SBMM_LEN 0x28 12449 12450 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12451 12452 /* reg_sbmm_prio 12453 * Switch Priority. 12454 * Access: Index 12455 */ 12456 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12457 12458 /* reg_sbmm_min_buff 12459 * Minimum buffer size for the limiter, in cells. 12460 * Access: RW 12461 */ 12462 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12463 12464 /* reg_sbmm_max_buff 12465 * When the pool associated to the port-pg/tclass is configured to 12466 * static, Maximum buffer size for the limiter configured in cells. 12467 * When the pool associated to the port-pg/tclass is configured to 12468 * dynamic, the max_buff holds the "alpha" parameter, supporting 12469 * the following values: 12470 * 0: 0 12471 * i: (1/128)*2^(i-1), for i=1..14 12472 * 0xFF: Infinity 12473 * Access: RW 12474 */ 12475 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12476 12477 /* reg_sbmm_pool 12478 * Association of the port-priority to a pool. 12479 * Access: RW 12480 */ 12481 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12482 12483 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12484 u32 max_buff, u8 pool) 12485 { 12486 MLXSW_REG_ZERO(sbmm, payload); 12487 mlxsw_reg_sbmm_prio_set(payload, prio); 12488 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12489 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12490 mlxsw_reg_sbmm_pool_set(payload, pool); 12491 } 12492 12493 /* SBSR - Shared Buffer Status Register 12494 * ------------------------------------ 12495 * The SBSR register retrieves the shared buffer occupancy according to 12496 * Port-Pool. Note that this register enables reading a large amount of data. 12497 * It is the user's responsibility to limit the amount of data to ensure the 12498 * response can match the maximum transfer unit. In case the response exceeds 12499 * the maximum transport unit, it will be truncated with no special notice. 12500 */ 12501 #define MLXSW_REG_SBSR_ID 0xB005 12502 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12503 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12504 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12505 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12506 MLXSW_REG_SBSR_REC_LEN * \ 12507 MLXSW_REG_SBSR_REC_MAX_COUNT) 12508 12509 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12510 12511 /* reg_sbsr_clr 12512 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12513 * field is cleared (and a new max value is tracked from the time the clear 12514 * was performed). 12515 * Access: OP 12516 */ 12517 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12518 12519 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12520 12521 /* reg_sbsr_port_page 12522 * Determines the range of the ports specified in the 'ingress_port_mask' 12523 * and 'egress_port_mask' bit masks. 12524 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12525 * Access: Index 12526 */ 12527 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12528 12529 /* reg_sbsr_ingress_port_mask 12530 * Bit vector for all ingress network ports. 12531 * Indicates which of the ports (for which the relevant bit is set) 12532 * are affected by the set operation. Configuration of any other port 12533 * does not change. 12534 * Access: Index 12535 */ 12536 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12537 12538 /* reg_sbsr_pg_buff_mask 12539 * Bit vector for all switch priority groups. 12540 * Indicates which of the priorities (for which the relevant bit is set) 12541 * are affected by the set operation. Configuration of any other priority 12542 * does not change. 12543 * Range is 0..cap_max_pg_buffers - 1 12544 * Access: Index 12545 */ 12546 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12547 12548 /* reg_sbsr_egress_port_mask 12549 * Bit vector for all egress network ports. 12550 * Indicates which of the ports (for which the relevant bit is set) 12551 * are affected by the set operation. Configuration of any other port 12552 * does not change. 12553 * Access: Index 12554 */ 12555 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12556 12557 /* reg_sbsr_tclass_mask 12558 * Bit vector for all traffic classes. 12559 * Indicates which of the traffic classes (for which the relevant bit is 12560 * set) are affected by the set operation. Configuration of any other 12561 * traffic class does not change. 12562 * Range is 0..cap_max_tclass - 1 12563 * Access: Index 12564 */ 12565 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12566 12567 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12568 { 12569 MLXSW_REG_ZERO(sbsr, payload); 12570 mlxsw_reg_sbsr_clr_set(payload, clr); 12571 } 12572 12573 /* reg_sbsr_rec_buff_occupancy 12574 * Current buffer occupancy in cells. 12575 * Access: RO 12576 */ 12577 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12578 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12579 12580 /* reg_sbsr_rec_max_buff_occupancy 12581 * Maximum value of buffer occupancy in cells monitored. Cleared by 12582 * writing to the clr field. 12583 * Access: RO 12584 */ 12585 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12586 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12587 12588 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12589 u32 *p_buff_occupancy, 12590 u32 *p_max_buff_occupancy) 12591 { 12592 *p_buff_occupancy = 12593 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12594 *p_max_buff_occupancy = 12595 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12596 } 12597 12598 /* SBIB - Shared Buffer Internal Buffer Register 12599 * --------------------------------------------- 12600 * The SBIB register configures per port buffers for internal use. The internal 12601 * buffers consume memory on the port buffers (note that the port buffers are 12602 * used also by PBMC). 12603 * 12604 * For Spectrum this is used for egress mirroring. 12605 */ 12606 #define MLXSW_REG_SBIB_ID 0xB006 12607 #define MLXSW_REG_SBIB_LEN 0x10 12608 12609 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12610 12611 /* reg_sbib_local_port 12612 * Local port number 12613 * Not supported for CPU port and router port 12614 * Access: Index 12615 */ 12616 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12617 12618 /* reg_sbib_buff_size 12619 * Units represented in cells 12620 * Allowed range is 0 to (cap_max_headroom_size - 1) 12621 * Default is 0 12622 * Access: RW 12623 */ 12624 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12625 12626 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12627 u32 buff_size) 12628 { 12629 MLXSW_REG_ZERO(sbib, payload); 12630 mlxsw_reg_sbib_local_port_set(payload, local_port); 12631 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12632 } 12633 12634 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12635 MLXSW_REG(sgcr), 12636 MLXSW_REG(spad), 12637 MLXSW_REG(sspr), 12638 MLXSW_REG(sfdat), 12639 MLXSW_REG(sfd), 12640 MLXSW_REG(sfn), 12641 MLXSW_REG(spms), 12642 MLXSW_REG(spvid), 12643 MLXSW_REG(spvm), 12644 MLXSW_REG(spaft), 12645 MLXSW_REG(sfgc), 12646 MLXSW_REG(sfdf), 12647 MLXSW_REG(sldr), 12648 MLXSW_REG(slcr), 12649 MLXSW_REG(slcor), 12650 MLXSW_REG(spmlr), 12651 MLXSW_REG(svfa), 12652 MLXSW_REG(spvtr), 12653 MLXSW_REG(svpe), 12654 MLXSW_REG(sfmr), 12655 MLXSW_REG(spvmlr), 12656 MLXSW_REG(spvc), 12657 MLXSW_REG(spevet), 12658 MLXSW_REG(smpe), 12659 MLXSW_REG(sftr2), 12660 MLXSW_REG(smid2), 12661 MLXSW_REG(cwtp), 12662 MLXSW_REG(cwtpm), 12663 MLXSW_REG(pgcr), 12664 MLXSW_REG(ppbt), 12665 MLXSW_REG(pacl), 12666 MLXSW_REG(pagt), 12667 MLXSW_REG(ptar), 12668 MLXSW_REG(ppbs), 12669 MLXSW_REG(prcr), 12670 MLXSW_REG(pefa), 12671 MLXSW_REG(pemrbt), 12672 MLXSW_REG(ptce2), 12673 MLXSW_REG(perpt), 12674 MLXSW_REG(peabfe), 12675 MLXSW_REG(perar), 12676 MLXSW_REG(ptce3), 12677 MLXSW_REG(percr), 12678 MLXSW_REG(pererp), 12679 MLXSW_REG(iedr), 12680 MLXSW_REG(qpts), 12681 MLXSW_REG(qpcr), 12682 MLXSW_REG(qtct), 12683 MLXSW_REG(qeec), 12684 MLXSW_REG(qrwe), 12685 MLXSW_REG(qpdsm), 12686 MLXSW_REG(qpdp), 12687 MLXSW_REG(qpdpm), 12688 MLXSW_REG(qtctm), 12689 MLXSW_REG(qpsc), 12690 MLXSW_REG(pmlp), 12691 MLXSW_REG(pmtu), 12692 MLXSW_REG(ptys), 12693 MLXSW_REG(ppad), 12694 MLXSW_REG(paos), 12695 MLXSW_REG(pfcc), 12696 MLXSW_REG(ppcnt), 12697 MLXSW_REG(plib), 12698 MLXSW_REG(pptb), 12699 MLXSW_REG(pbmc), 12700 MLXSW_REG(pspa), 12701 MLXSW_REG(pmaos), 12702 MLXSW_REG(pplr), 12703 MLXSW_REG(pmtdb), 12704 MLXSW_REG(pmecr), 12705 MLXSW_REG(pmpe), 12706 MLXSW_REG(pddr), 12707 MLXSW_REG(pmmp), 12708 MLXSW_REG(pllp), 12709 MLXSW_REG(pmtm), 12710 MLXSW_REG(htgt), 12711 MLXSW_REG(hpkt), 12712 MLXSW_REG(rgcr), 12713 MLXSW_REG(ritr), 12714 MLXSW_REG(rtar), 12715 MLXSW_REG(ratr), 12716 MLXSW_REG(rtdp), 12717 MLXSW_REG(rips), 12718 MLXSW_REG(ratrad), 12719 MLXSW_REG(rdpm), 12720 MLXSW_REG(ricnt), 12721 MLXSW_REG(rrcr), 12722 MLXSW_REG(ralta), 12723 MLXSW_REG(ralst), 12724 MLXSW_REG(raltb), 12725 MLXSW_REG(ralue), 12726 MLXSW_REG(rauht), 12727 MLXSW_REG(raleu), 12728 MLXSW_REG(rauhtd), 12729 MLXSW_REG(rigr2), 12730 MLXSW_REG(recr2), 12731 MLXSW_REG(rmft2), 12732 MLXSW_REG(reiv), 12733 MLXSW_REG(mfcr), 12734 MLXSW_REG(mfsc), 12735 MLXSW_REG(mfsm), 12736 MLXSW_REG(mfsl), 12737 MLXSW_REG(fore), 12738 MLXSW_REG(mtcap), 12739 MLXSW_REG(mtmp), 12740 MLXSW_REG(mtwe), 12741 MLXSW_REG(mtbr), 12742 MLXSW_REG(mcia), 12743 MLXSW_REG(mpat), 12744 MLXSW_REG(mpar), 12745 MLXSW_REG(mgir), 12746 MLXSW_REG(mrsr), 12747 MLXSW_REG(mlcr), 12748 MLXSW_REG(mcion), 12749 MLXSW_REG(mtpps), 12750 MLXSW_REG(mtutc), 12751 MLXSW_REG(mpsc), 12752 MLXSW_REG(mcqi), 12753 MLXSW_REG(mcc), 12754 MLXSW_REG(mcda), 12755 MLXSW_REG(mgpc), 12756 MLXSW_REG(mprs), 12757 MLXSW_REG(mogcr), 12758 MLXSW_REG(mpagr), 12759 MLXSW_REG(momte), 12760 MLXSW_REG(mtpppc), 12761 MLXSW_REG(mtpptr), 12762 MLXSW_REG(mtptpt), 12763 MLXSW_REG(mfgd), 12764 MLXSW_REG(mgpir), 12765 MLXSW_REG(mbct), 12766 MLXSW_REG(mddq), 12767 MLXSW_REG(mddc), 12768 MLXSW_REG(mfde), 12769 MLXSW_REG(tngcr), 12770 MLXSW_REG(tnumt), 12771 MLXSW_REG(tnqcr), 12772 MLXSW_REG(tnqdr), 12773 MLXSW_REG(tneem), 12774 MLXSW_REG(tndem), 12775 MLXSW_REG(tnpc), 12776 MLXSW_REG(tigcr), 12777 MLXSW_REG(tieem), 12778 MLXSW_REG(tidem), 12779 MLXSW_REG(sbpr), 12780 MLXSW_REG(sbcm), 12781 MLXSW_REG(sbpm), 12782 MLXSW_REG(sbmm), 12783 MLXSW_REG(sbsr), 12784 MLXSW_REG(sbib), 12785 }; 12786 12787 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12788 { 12789 const struct mlxsw_reg_info *reg_info; 12790 int i; 12791 12792 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12793 reg_info = mlxsw_reg_infos[i]; 12794 if (reg_info->id == reg_id) 12795 return reg_info->name; 12796 } 12797 return "*UNKNOWN*"; 12798 } 12799 12800 /* PUDE - Port Up / Down Event 12801 * --------------------------- 12802 * Reports the operational state change of a port. 12803 */ 12804 #define MLXSW_REG_PUDE_LEN 0x10 12805 12806 /* reg_pude_swid 12807 * Switch partition ID with which to associate the port. 12808 * Access: Index 12809 */ 12810 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12811 12812 /* reg_pude_local_port 12813 * Local port number. 12814 * Access: Index 12815 */ 12816 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12817 12818 /* reg_pude_admin_status 12819 * Port administrative state (the desired state). 12820 * 1 - Up. 12821 * 2 - Down. 12822 * 3 - Up once. This means that in case of link failure, the port won't go 12823 * into polling mode, but will wait to be re-enabled by software. 12824 * 4 - Disabled by system. Can only be set by hardware. 12825 * Access: RO 12826 */ 12827 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12828 12829 /* reg_pude_oper_status 12830 * Port operatioanl state. 12831 * 1 - Up. 12832 * 2 - Down. 12833 * 3 - Down by port failure. This means that the device will not let the 12834 * port up again until explicitly specified by software. 12835 * Access: RO 12836 */ 12837 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12838 12839 #endif 12840