1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 enum mlxsw_reg_tunnel_port { 585 MLXSW_REG_TUNNEL_PORT_NVE, 586 MLXSW_REG_TUNNEL_PORT_VPLS, 587 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 588 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 589 }; 590 591 /* SFN - Switch FDB Notification Register 592 * ------------------------------------------- 593 * The switch provides notifications on newly learned FDB entries and 594 * aged out entries. The notifications can be polled by software. 595 */ 596 #define MLXSW_REG_SFN_ID 0x200B 597 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 598 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 599 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 600 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 601 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 602 603 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 604 605 /* reg_sfn_swid 606 * Switch partition ID. 607 * Access: Index 608 */ 609 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 610 611 /* reg_sfn_end 612 * Forces the current session to end. 613 * Access: OP 614 */ 615 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 616 617 /* reg_sfn_num_rec 618 * Request: Number of learned notifications and aged-out notification 619 * records requested. 620 * Response: Number of notification records returned (must be smaller 621 * than or equal to the value requested) 622 * Ranges 0..64 623 * Access: OP 624 */ 625 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 626 627 static inline void mlxsw_reg_sfn_pack(char *payload) 628 { 629 MLXSW_REG_ZERO(sfn, payload); 630 mlxsw_reg_sfn_swid_set(payload, 0); 631 mlxsw_reg_sfn_end_set(payload, 0); 632 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 633 } 634 635 /* reg_sfn_rec_swid 636 * Switch partition ID. 637 * Access: RO 638 */ 639 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 640 MLXSW_REG_SFN_REC_LEN, 0x00, false); 641 642 enum mlxsw_reg_sfn_rec_type { 643 /* MAC addresses learned on a regular port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 645 /* MAC addresses learned on a LAG port. */ 646 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 647 /* Aged-out MAC address on a regular port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 649 /* Aged-out MAC address on a LAG port. */ 650 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 651 /* Learned unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 653 /* Aged-out unicast tunnel record. */ 654 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 655 }; 656 657 /* reg_sfn_rec_type 658 * Notification record type. 659 * Access: RO 660 */ 661 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 662 MLXSW_REG_SFN_REC_LEN, 0x00, false); 663 664 /* reg_sfn_rec_mac 665 * MAC address. 666 * Access: RO 667 */ 668 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 669 MLXSW_REG_SFN_REC_LEN, 0x02); 670 671 /* reg_sfn_mac_sub_port 672 * VEPA channel on the local port. 673 * 0 if multichannel VEPA is not enabled. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_fid 680 * Filtering identifier. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x08, false); 685 686 /* reg_sfn_mac_system_port 687 * Unique port identifier for the final destination of the packet. 688 * Access: RO 689 */ 690 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 691 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 692 693 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 694 char *mac, u16 *p_vid, 695 u8 *p_local_port) 696 { 697 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 698 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 699 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 700 } 701 702 /* reg_sfn_mac_lag_lag_id 703 * LAG ID (pointer into the LAG descriptor table). 704 * Access: RO 705 */ 706 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 707 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 708 709 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 710 char *mac, u16 *p_vid, 711 u16 *p_lag_id) 712 { 713 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 714 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 715 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 716 } 717 718 /* reg_sfn_uc_tunnel_uip_msb 719 * When protocol is IPv4, the most significant byte of the underlay IPv4 720 * address of the remote VTEP. 721 * When protocol is IPv6, reserved. 722 * Access: RO 723 */ 724 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 725 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 726 727 enum mlxsw_reg_sfn_uc_tunnel_protocol { 728 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 729 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 730 }; 731 732 /* reg_sfn_uc_tunnel_protocol 733 * IP protocol. 734 * Access: RO 735 */ 736 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 737 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 738 739 /* reg_sfn_uc_tunnel_uip_lsb 740 * When protocol is IPv4, the least significant bytes of the underlay 741 * IPv4 address of the remote VTEP. 742 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 743 * Access: RO 744 */ 745 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 746 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_tport 825 * Port is tunnel port. 826 * Reserved when SwitchX/-2 or Spectrum-1. 827 * Access: Index 828 */ 829 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 830 831 /* reg_spvid_local_port 832 * When tport = 0: Local port number. Not supported for CPU port. 833 * When tport = 1: Tunnel port. 834 * Access: Index 835 */ 836 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 837 838 /* reg_spvid_sub_port 839 * Virtual port within the physical port. 840 * Should be set to 0 when virtual ports are not enabled on the port. 841 * Access: Index 842 */ 843 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 844 845 /* reg_spvid_egr_et_set 846 * When VLAN is pushed at ingress (for untagged packets or for 847 * QinQ push mode) then the EtherType is decided at the egress port. 848 * Reserved when Spectrum-1. 849 * Access: RW 850 */ 851 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 852 853 /* reg_spvid_et_vlan 854 * EtherType used for when VLAN is pushed at ingress (for untagged 855 * packets or for QinQ push mode). 856 * 0: ether_type0 - (default) 857 * 1: ether_type1 858 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 859 * Ethertype IDs are configured by SVER. 860 * Reserved when egr_et_set = 1. 861 * Access: RW 862 */ 863 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 864 865 /* reg_spvid_pvid 866 * Port default VID 867 * Access: RW 868 */ 869 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 870 871 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid, 872 u8 et_vlan) 873 { 874 MLXSW_REG_ZERO(spvid, payload); 875 mlxsw_reg_spvid_local_port_set(payload, local_port); 876 mlxsw_reg_spvid_pvid_set(payload, pvid); 877 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 878 } 879 880 /* SPVM - Switch Port VLAN Membership 881 * ---------------------------------- 882 * The Switch Port VLAN Membership register configures the VLAN membership 883 * of a port in a VLAN denoted by VID. VLAN membership is managed per 884 * virtual port. The register can be used to add and remove VID(s) from a port. 885 */ 886 #define MLXSW_REG_SPVM_ID 0x200F 887 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 888 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 889 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 890 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 891 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 892 893 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 894 895 /* reg_spvm_pt 896 * Priority tagged. If this bit is set, packets forwarded to the port with 897 * untagged VLAN membership (u bit is set) will be tagged with priority tag 898 * (VID=0) 899 * Access: RW 900 */ 901 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 902 903 /* reg_spvm_pte 904 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 905 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 906 * Access: WO 907 */ 908 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 909 910 /* reg_spvm_local_port 911 * Local port number. 912 * Access: Index 913 */ 914 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 915 916 /* reg_spvm_sub_port 917 * Virtual port within the physical port. 918 * Should be set to 0 when virtual ports are not enabled on the port. 919 * Access: Index 920 */ 921 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 922 923 /* reg_spvm_num_rec 924 * Number of records to update. Each record contains: i, e, u, vid. 925 * Access: OP 926 */ 927 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 928 929 /* reg_spvm_rec_i 930 * Ingress membership in VLAN ID. 931 * Access: Index 932 */ 933 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 934 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 935 MLXSW_REG_SPVM_REC_LEN, 0, false); 936 937 /* reg_spvm_rec_e 938 * Egress membership in VLAN ID. 939 * Access: Index 940 */ 941 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 942 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 943 MLXSW_REG_SPVM_REC_LEN, 0, false); 944 945 /* reg_spvm_rec_u 946 * Untagged - port is an untagged member - egress transmission uses untagged 947 * frames on VID<n> 948 * Access: Index 949 */ 950 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 951 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 952 MLXSW_REG_SPVM_REC_LEN, 0, false); 953 954 /* reg_spvm_rec_vid 955 * Egress membership in VLAN ID. 956 * Access: Index 957 */ 958 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 959 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 960 MLXSW_REG_SPVM_REC_LEN, 0, false); 961 962 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 963 u16 vid_begin, u16 vid_end, 964 bool is_member, bool untagged) 965 { 966 int size = vid_end - vid_begin + 1; 967 int i; 968 969 MLXSW_REG_ZERO(spvm, payload); 970 mlxsw_reg_spvm_local_port_set(payload, local_port); 971 mlxsw_reg_spvm_num_rec_set(payload, size); 972 973 for (i = 0; i < size; i++) { 974 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 975 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 976 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 977 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 978 } 979 } 980 981 /* SPAFT - Switch Port Acceptable Frame Types 982 * ------------------------------------------ 983 * The Switch Port Acceptable Frame Types register configures the frame 984 * admittance of the port. 985 */ 986 #define MLXSW_REG_SPAFT_ID 0x2010 987 #define MLXSW_REG_SPAFT_LEN 0x08 988 989 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 990 991 /* reg_spaft_local_port 992 * Local port number. 993 * Access: Index 994 * 995 * Note: CPU port is not supported (all tag types are allowed). 996 */ 997 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 998 999 /* reg_spaft_sub_port 1000 * Virtual port within the physical port. 1001 * Should be set to 0 when virtual ports are not enabled on the port. 1002 * Access: RW 1003 */ 1004 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1005 1006 /* reg_spaft_allow_untagged 1007 * When set, untagged frames on the ingress are allowed (default). 1008 * Access: RW 1009 */ 1010 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1011 1012 /* reg_spaft_allow_prio_tagged 1013 * When set, priority tagged frames on the ingress are allowed (default). 1014 * Access: RW 1015 */ 1016 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1017 1018 /* reg_spaft_allow_tagged 1019 * When set, tagged frames on the ingress are allowed (default). 1020 * Access: RW 1021 */ 1022 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1023 1024 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 1025 bool allow_untagged) 1026 { 1027 MLXSW_REG_ZERO(spaft, payload); 1028 mlxsw_reg_spaft_local_port_set(payload, local_port); 1029 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1030 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1031 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1032 } 1033 1034 /* SFGC - Switch Flooding Group Configuration 1035 * ------------------------------------------ 1036 * The following register controls the association of flooding tables and MIDs 1037 * to packet types used for flooding. 1038 */ 1039 #define MLXSW_REG_SFGC_ID 0x2011 1040 #define MLXSW_REG_SFGC_LEN 0x10 1041 1042 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1043 1044 enum mlxsw_reg_sfgc_type { 1045 MLXSW_REG_SFGC_TYPE_BROADCAST, 1046 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1047 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1048 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1049 MLXSW_REG_SFGC_TYPE_RESERVED, 1050 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1051 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1052 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1053 MLXSW_REG_SFGC_TYPE_MAX, 1054 }; 1055 1056 /* reg_sfgc_type 1057 * The traffic type to reach the flooding table. 1058 * Access: Index 1059 */ 1060 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1061 1062 enum mlxsw_reg_sfgc_bridge_type { 1063 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1064 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1065 }; 1066 1067 /* reg_sfgc_bridge_type 1068 * Access: Index 1069 * 1070 * Note: SwitchX-2 only supports 802.1Q mode. 1071 */ 1072 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1073 1074 enum mlxsw_flood_table_type { 1075 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1076 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1077 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1078 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1079 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1080 }; 1081 1082 /* reg_sfgc_table_type 1083 * See mlxsw_flood_table_type 1084 * Access: RW 1085 * 1086 * Note: FID offset and FID types are not supported in SwitchX-2. 1087 */ 1088 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1089 1090 /* reg_sfgc_flood_table 1091 * Flooding table index to associate with the specific type on the specific 1092 * switch partition. 1093 * Access: RW 1094 */ 1095 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1096 1097 /* reg_sfgc_mid 1098 * The multicast ID for the swid. Not supported for Spectrum 1099 * Access: RW 1100 */ 1101 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1102 1103 /* reg_sfgc_counter_set_type 1104 * Counter Set Type for flow counters. 1105 * Access: RW 1106 */ 1107 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1108 1109 /* reg_sfgc_counter_index 1110 * Counter Index for flow counters. 1111 * Access: RW 1112 */ 1113 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1114 1115 static inline void 1116 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1117 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1118 enum mlxsw_flood_table_type table_type, 1119 unsigned int flood_table) 1120 { 1121 MLXSW_REG_ZERO(sfgc, payload); 1122 mlxsw_reg_sfgc_type_set(payload, type); 1123 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1124 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1125 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1126 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1127 } 1128 1129 /* SFTR - Switch Flooding Table Register 1130 * ------------------------------------- 1131 * The switch flooding table is used for flooding packet replication. The table 1132 * defines a bit mask of ports for packet replication. 1133 */ 1134 #define MLXSW_REG_SFTR_ID 0x2012 1135 #define MLXSW_REG_SFTR_LEN 0x420 1136 1137 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1138 1139 /* reg_sftr_swid 1140 * Switch partition ID with which to associate the port. 1141 * Access: Index 1142 */ 1143 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1144 1145 /* reg_sftr_flood_table 1146 * Flooding table index to associate with the specific type on the specific 1147 * switch partition. 1148 * Access: Index 1149 */ 1150 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1151 1152 /* reg_sftr_index 1153 * Index. Used as an index into the Flooding Table in case the table is 1154 * configured to use VID / FID or FID Offset. 1155 * Access: Index 1156 */ 1157 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1158 1159 /* reg_sftr_table_type 1160 * See mlxsw_flood_table_type 1161 * Access: RW 1162 */ 1163 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1164 1165 /* reg_sftr_range 1166 * Range of entries to update 1167 * Access: Index 1168 */ 1169 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1170 1171 /* reg_sftr_port 1172 * Local port membership (1 bit per port). 1173 * Access: RW 1174 */ 1175 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1176 1177 /* reg_sftr_cpu_port_mask 1178 * CPU port mask (1 bit per port). 1179 * Access: W 1180 */ 1181 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1182 1183 static inline void mlxsw_reg_sftr_pack(char *payload, 1184 unsigned int flood_table, 1185 unsigned int index, 1186 enum mlxsw_flood_table_type table_type, 1187 unsigned int range, u8 port, bool set) 1188 { 1189 MLXSW_REG_ZERO(sftr, payload); 1190 mlxsw_reg_sftr_swid_set(payload, 0); 1191 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1192 mlxsw_reg_sftr_index_set(payload, index); 1193 mlxsw_reg_sftr_table_type_set(payload, table_type); 1194 mlxsw_reg_sftr_range_set(payload, range); 1195 mlxsw_reg_sftr_port_set(payload, port, set); 1196 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1197 } 1198 1199 /* SFDF - Switch Filtering DB Flush 1200 * -------------------------------- 1201 * The switch filtering DB flush register is used to flush the FDB. 1202 * Note that FDB notifications are flushed as well. 1203 */ 1204 #define MLXSW_REG_SFDF_ID 0x2013 1205 #define MLXSW_REG_SFDF_LEN 0x14 1206 1207 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1208 1209 /* reg_sfdf_swid 1210 * Switch partition ID. 1211 * Access: Index 1212 */ 1213 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1214 1215 enum mlxsw_reg_sfdf_flush_type { 1216 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1217 MLXSW_REG_SFDF_FLUSH_PER_FID, 1218 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1219 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1220 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1221 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1222 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1223 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1224 }; 1225 1226 /* reg_sfdf_flush_type 1227 * Flush type. 1228 * 0 - All SWID dynamic entries are flushed. 1229 * 1 - All FID dynamic entries are flushed. 1230 * 2 - All dynamic entries pointing to port are flushed. 1231 * 3 - All FID dynamic entries pointing to port are flushed. 1232 * 4 - All dynamic entries pointing to LAG are flushed. 1233 * 5 - All FID dynamic entries pointing to LAG are flushed. 1234 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1235 * flushed. 1236 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1237 * flushed, per FID. 1238 * Access: RW 1239 */ 1240 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1241 1242 /* reg_sfdf_flush_static 1243 * Static. 1244 * 0 - Flush only dynamic entries. 1245 * 1 - Flush both dynamic and static entries. 1246 * Access: RW 1247 */ 1248 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1249 1250 static inline void mlxsw_reg_sfdf_pack(char *payload, 1251 enum mlxsw_reg_sfdf_flush_type type) 1252 { 1253 MLXSW_REG_ZERO(sfdf, payload); 1254 mlxsw_reg_sfdf_flush_type_set(payload, type); 1255 mlxsw_reg_sfdf_flush_static_set(payload, true); 1256 } 1257 1258 /* reg_sfdf_fid 1259 * FID to flush. 1260 * Access: RW 1261 */ 1262 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1263 1264 /* reg_sfdf_system_port 1265 * Port to flush. 1266 * Access: RW 1267 */ 1268 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1269 1270 /* reg_sfdf_port_fid_system_port 1271 * Port to flush, pointed to by FID. 1272 * Access: RW 1273 */ 1274 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1275 1276 /* reg_sfdf_lag_id 1277 * LAG ID to flush. 1278 * Access: RW 1279 */ 1280 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1281 1282 /* reg_sfdf_lag_fid_lag_id 1283 * LAG ID to flush, pointed to by FID. 1284 * Access: RW 1285 */ 1286 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1287 1288 /* SLDR - Switch LAG Descriptor Register 1289 * ----------------------------------------- 1290 * The switch LAG descriptor register is populated by LAG descriptors. 1291 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1292 * max_lag-1. 1293 */ 1294 #define MLXSW_REG_SLDR_ID 0x2014 1295 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1296 1297 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1298 1299 enum mlxsw_reg_sldr_op { 1300 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1301 MLXSW_REG_SLDR_OP_LAG_CREATE, 1302 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1303 /* Ports that appear in the list have the Distributor enabled */ 1304 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1305 /* Removes ports from the disributor list */ 1306 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1307 }; 1308 1309 /* reg_sldr_op 1310 * Operation. 1311 * Access: RW 1312 */ 1313 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1314 1315 /* reg_sldr_lag_id 1316 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1317 * Access: Index 1318 */ 1319 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1320 1321 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1322 { 1323 MLXSW_REG_ZERO(sldr, payload); 1324 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1325 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1326 } 1327 1328 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1329 { 1330 MLXSW_REG_ZERO(sldr, payload); 1331 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1332 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1333 } 1334 1335 /* reg_sldr_num_ports 1336 * The number of member ports of the LAG. 1337 * Reserved for Create / Destroy operations 1338 * For Add / Remove operations - indicates the number of ports in the list. 1339 * Access: RW 1340 */ 1341 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1342 1343 /* reg_sldr_system_port 1344 * System port. 1345 * Access: RW 1346 */ 1347 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1348 1349 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1350 u8 local_port) 1351 { 1352 MLXSW_REG_ZERO(sldr, payload); 1353 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1354 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1355 mlxsw_reg_sldr_num_ports_set(payload, 1); 1356 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1357 } 1358 1359 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1360 u8 local_port) 1361 { 1362 MLXSW_REG_ZERO(sldr, payload); 1363 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1364 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1365 mlxsw_reg_sldr_num_ports_set(payload, 1); 1366 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1367 } 1368 1369 /* SLCR - Switch LAG Configuration 2 Register 1370 * ------------------------------------------- 1371 * The Switch LAG Configuration register is used for configuring the 1372 * LAG properties of the switch. 1373 */ 1374 #define MLXSW_REG_SLCR_ID 0x2015 1375 #define MLXSW_REG_SLCR_LEN 0x10 1376 1377 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1378 1379 enum mlxsw_reg_slcr_pp { 1380 /* Global Configuration (for all ports) */ 1381 MLXSW_REG_SLCR_PP_GLOBAL, 1382 /* Per port configuration, based on local_port field */ 1383 MLXSW_REG_SLCR_PP_PER_PORT, 1384 }; 1385 1386 /* reg_slcr_pp 1387 * Per Port Configuration 1388 * Note: Reading at Global mode results in reading port 1 configuration. 1389 * Access: Index 1390 */ 1391 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1392 1393 /* reg_slcr_local_port 1394 * Local port number 1395 * Supported from CPU port 1396 * Not supported from router port 1397 * Reserved when pp = Global Configuration 1398 * Access: Index 1399 */ 1400 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1401 1402 enum mlxsw_reg_slcr_type { 1403 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1404 MLXSW_REG_SLCR_TYPE_XOR, 1405 MLXSW_REG_SLCR_TYPE_RANDOM, 1406 }; 1407 1408 /* reg_slcr_type 1409 * Hash type 1410 * Access: RW 1411 */ 1412 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1413 1414 /* Ingress port */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1416 /* SMAC - for IPv4 and IPv6 packets */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1418 /* SMAC - for non-IP packets */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1420 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1421 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1422 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1423 /* DMAC - for IPv4 and IPv6 packets */ 1424 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1425 /* DMAC - for non-IP packets */ 1426 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1427 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1428 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1429 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1430 /* Ethertype - for IPv4 and IPv6 packets */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1432 /* Ethertype - for non-IP packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1434 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1435 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1436 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1437 /* VLAN ID - for IPv4 and IPv6 packets */ 1438 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1439 /* VLAN ID - for non-IP packets */ 1440 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1441 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1442 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1443 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1444 /* Source IP address (can be IPv4 or IPv6) */ 1445 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1446 /* Destination IP address (can be IPv4 or IPv6) */ 1447 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1448 /* TCP/UDP source port */ 1449 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1450 /* TCP/UDP destination port*/ 1451 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1452 /* IPv4 Protocol/IPv6 Next Header */ 1453 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1454 /* IPv6 Flow label */ 1455 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1456 /* SID - FCoE source ID */ 1457 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1458 /* DID - FCoE destination ID */ 1459 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1460 /* OXID - FCoE originator exchange ID */ 1461 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1462 /* Destination QP number - for RoCE packets */ 1463 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1464 1465 /* reg_slcr_lag_hash 1466 * LAG hashing configuration. This is a bitmask, in which each set 1467 * bit includes the corresponding item in the LAG hash calculation. 1468 * The default lag_hash contains SMAC, DMAC, VLANID and 1469 * Ethertype (for all packet types). 1470 * Access: RW 1471 */ 1472 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1473 1474 /* reg_slcr_seed 1475 * LAG seed value. The seed is the same for all ports. 1476 * Access: RW 1477 */ 1478 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1479 1480 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1481 { 1482 MLXSW_REG_ZERO(slcr, payload); 1483 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1484 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1485 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1486 mlxsw_reg_slcr_seed_set(payload, seed); 1487 } 1488 1489 /* SLCOR - Switch LAG Collector Register 1490 * ------------------------------------- 1491 * The Switch LAG Collector register controls the Local Port membership 1492 * in a LAG and enablement of the collector. 1493 */ 1494 #define MLXSW_REG_SLCOR_ID 0x2016 1495 #define MLXSW_REG_SLCOR_LEN 0x10 1496 1497 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1498 1499 enum mlxsw_reg_slcor_col { 1500 /* Port is added with collector disabled */ 1501 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1502 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1503 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1504 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1505 }; 1506 1507 /* reg_slcor_col 1508 * Collector configuration 1509 * Access: RW 1510 */ 1511 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1512 1513 /* reg_slcor_local_port 1514 * Local port number 1515 * Not supported for CPU port 1516 * Access: Index 1517 */ 1518 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1519 1520 /* reg_slcor_lag_id 1521 * LAG Identifier. Index into the LAG descriptor table. 1522 * Access: Index 1523 */ 1524 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1525 1526 /* reg_slcor_port_index 1527 * Port index in the LAG list. Only valid on Add Port to LAG col. 1528 * Valid range is from 0 to cap_max_lag_members-1 1529 * Access: RW 1530 */ 1531 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1532 1533 static inline void mlxsw_reg_slcor_pack(char *payload, 1534 u8 local_port, u16 lag_id, 1535 enum mlxsw_reg_slcor_col col) 1536 { 1537 MLXSW_REG_ZERO(slcor, payload); 1538 mlxsw_reg_slcor_col_set(payload, col); 1539 mlxsw_reg_slcor_local_port_set(payload, local_port); 1540 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1541 } 1542 1543 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1544 u8 local_port, u16 lag_id, 1545 u8 port_index) 1546 { 1547 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1548 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1549 mlxsw_reg_slcor_port_index_set(payload, port_index); 1550 } 1551 1552 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1553 u8 local_port, u16 lag_id) 1554 { 1555 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1556 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1557 } 1558 1559 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1560 u8 local_port, u16 lag_id) 1561 { 1562 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1563 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1564 } 1565 1566 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1567 u8 local_port, u16 lag_id) 1568 { 1569 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1570 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1571 } 1572 1573 /* SPMLR - Switch Port MAC Learning Register 1574 * ----------------------------------------- 1575 * Controls the Switch MAC learning policy per port. 1576 */ 1577 #define MLXSW_REG_SPMLR_ID 0x2018 1578 #define MLXSW_REG_SPMLR_LEN 0x8 1579 1580 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1581 1582 /* reg_spmlr_local_port 1583 * Local port number. 1584 * Access: Index 1585 */ 1586 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1587 1588 /* reg_spmlr_sub_port 1589 * Virtual port within the physical port. 1590 * Should be set to 0 when virtual ports are not enabled on the port. 1591 * Access: Index 1592 */ 1593 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1594 1595 enum mlxsw_reg_spmlr_learn_mode { 1596 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1597 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1598 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1599 }; 1600 1601 /* reg_spmlr_learn_mode 1602 * Learning mode on the port. 1603 * 0 - Learning disabled. 1604 * 2 - Learning enabled. 1605 * 3 - Security mode. 1606 * 1607 * In security mode the switch does not learn MACs on the port, but uses the 1608 * SMAC to see if it exists on another ingress port. If so, the packet is 1609 * classified as a bad packet and is discarded unless the software registers 1610 * to receive port security error packets usign HPKT. 1611 */ 1612 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1613 1614 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1615 enum mlxsw_reg_spmlr_learn_mode mode) 1616 { 1617 MLXSW_REG_ZERO(spmlr, payload); 1618 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1619 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1620 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1621 } 1622 1623 /* SVFA - Switch VID to FID Allocation Register 1624 * -------------------------------------------- 1625 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1626 * virtualized ports. 1627 */ 1628 #define MLXSW_REG_SVFA_ID 0x201C 1629 #define MLXSW_REG_SVFA_LEN 0x10 1630 1631 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1632 1633 /* reg_svfa_swid 1634 * Switch partition ID. 1635 * Access: Index 1636 */ 1637 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1638 1639 /* reg_svfa_local_port 1640 * Local port number. 1641 * Access: Index 1642 * 1643 * Note: Reserved for 802.1Q FIDs. 1644 */ 1645 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1646 1647 enum mlxsw_reg_svfa_mt { 1648 MLXSW_REG_SVFA_MT_VID_TO_FID, 1649 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1650 }; 1651 1652 /* reg_svfa_mapping_table 1653 * Mapping table: 1654 * 0 - VID to FID 1655 * 1 - {Port, VID} to FID 1656 * Access: Index 1657 * 1658 * Note: Reserved for SwitchX-2. 1659 */ 1660 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1661 1662 /* reg_svfa_v 1663 * Valid. 1664 * Valid if set. 1665 * Access: RW 1666 * 1667 * Note: Reserved for SwitchX-2. 1668 */ 1669 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1670 1671 /* reg_svfa_fid 1672 * Filtering ID. 1673 * Access: RW 1674 */ 1675 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1676 1677 /* reg_svfa_vid 1678 * VLAN ID. 1679 * Access: Index 1680 */ 1681 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1682 1683 /* reg_svfa_counter_set_type 1684 * Counter set type for flow counters. 1685 * Access: RW 1686 * 1687 * Note: Reserved for SwitchX-2. 1688 */ 1689 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1690 1691 /* reg_svfa_counter_index 1692 * Counter index for flow counters. 1693 * Access: RW 1694 * 1695 * Note: Reserved for SwitchX-2. 1696 */ 1697 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1698 1699 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1700 enum mlxsw_reg_svfa_mt mt, bool valid, 1701 u16 fid, u16 vid) 1702 { 1703 MLXSW_REG_ZERO(svfa, payload); 1704 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1705 mlxsw_reg_svfa_swid_set(payload, 0); 1706 mlxsw_reg_svfa_local_port_set(payload, local_port); 1707 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1708 mlxsw_reg_svfa_v_set(payload, valid); 1709 mlxsw_reg_svfa_fid_set(payload, fid); 1710 mlxsw_reg_svfa_vid_set(payload, vid); 1711 } 1712 1713 /* SPVTR - Switch Port VLAN Stacking Register 1714 * ------------------------------------------ 1715 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1716 * to enable VLAN stacking. 1717 */ 1718 #define MLXSW_REG_SPVTR_ID 0x201D 1719 #define MLXSW_REG_SPVTR_LEN 0x10 1720 1721 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1722 1723 /* reg_spvtr_tport 1724 * Port is tunnel port. 1725 * Access: Index 1726 * 1727 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1728 */ 1729 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1730 1731 /* reg_spvtr_local_port 1732 * When tport = 0: local port number (Not supported from/to CPU). 1733 * When tport = 1: tunnel port. 1734 * Access: Index 1735 */ 1736 MLXSW_ITEM32(reg, spvtr, local_port, 0x00, 16, 8); 1737 1738 /* reg_spvtr_ippe 1739 * Ingress Port Prio Mode Update Enable. 1740 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1741 * Reserved on Get operations. 1742 * Access: OP 1743 */ 1744 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1745 1746 /* reg_spvtr_ipve 1747 * Ingress Port VID Mode Update Enable. 1748 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1749 * field. 1750 * Reserved on Get operations. 1751 * Access: OP 1752 */ 1753 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1754 1755 /* reg_spvtr_epve 1756 * Egress Port VID Mode Update Enable. 1757 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1758 * field. 1759 * Access: OP 1760 */ 1761 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1762 1763 /* reg_spvtr_ipprio_mode 1764 * Ingress Port Priority Mode. 1765 * This controls the PCP and DEI of the new outer VLAN 1766 * Note: for SwitchX/-2 the DEI is not affected. 1767 * 0: use port default PCP and DEI (configured by QPDPC). 1768 * 1: use C-VLAN PCP and DEI. 1769 * Has no effect when ipvid_mode = 0. 1770 * Reserved when tport = 1. 1771 * Access: RW 1772 */ 1773 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1774 1775 enum mlxsw_reg_spvtr_ipvid_mode { 1776 /* IEEE Compliant PVID (default) */ 1777 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1778 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1779 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1780 /* Always push VLAN (also for prio tagged packets) */ 1781 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1782 }; 1783 1784 /* reg_spvtr_ipvid_mode 1785 * Ingress Port VLAN-ID Mode. 1786 * For Spectrum family, this affects the values of SPVM.i 1787 * Access: RW 1788 */ 1789 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1790 1791 enum mlxsw_reg_spvtr_epvid_mode { 1792 /* IEEE Compliant VLAN membership */ 1793 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1794 /* Pop VLAN (for VLAN stacking) */ 1795 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1796 }; 1797 1798 /* reg_spvtr_epvid_mode 1799 * Egress Port VLAN-ID Mode. 1800 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1801 * Access: WO 1802 */ 1803 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1804 1805 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1806 u8 local_port, 1807 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1808 { 1809 MLXSW_REG_ZERO(spvtr, payload); 1810 mlxsw_reg_spvtr_tport_set(payload, tport); 1811 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1812 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1813 mlxsw_reg_spvtr_ipve_set(payload, true); 1814 } 1815 1816 /* SVPE - Switch Virtual-Port Enabling Register 1817 * -------------------------------------------- 1818 * Enables port virtualization. 1819 */ 1820 #define MLXSW_REG_SVPE_ID 0x201E 1821 #define MLXSW_REG_SVPE_LEN 0x4 1822 1823 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1824 1825 /* reg_svpe_local_port 1826 * Local port number 1827 * Access: Index 1828 * 1829 * Note: CPU port is not supported (uses VLAN mode only). 1830 */ 1831 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1832 1833 /* reg_svpe_vp_en 1834 * Virtual port enable. 1835 * 0 - Disable, VLAN mode (VID to FID). 1836 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1837 * Access: RW 1838 */ 1839 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1840 1841 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1842 bool enable) 1843 { 1844 MLXSW_REG_ZERO(svpe, payload); 1845 mlxsw_reg_svpe_local_port_set(payload, local_port); 1846 mlxsw_reg_svpe_vp_en_set(payload, enable); 1847 } 1848 1849 /* SFMR - Switch FID Management Register 1850 * ------------------------------------- 1851 * Creates and configures FIDs. 1852 */ 1853 #define MLXSW_REG_SFMR_ID 0x201F 1854 #define MLXSW_REG_SFMR_LEN 0x18 1855 1856 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1857 1858 enum mlxsw_reg_sfmr_op { 1859 MLXSW_REG_SFMR_OP_CREATE_FID, 1860 MLXSW_REG_SFMR_OP_DESTROY_FID, 1861 }; 1862 1863 /* reg_sfmr_op 1864 * Operation. 1865 * 0 - Create or edit FID. 1866 * 1 - Destroy FID. 1867 * Access: WO 1868 */ 1869 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1870 1871 /* reg_sfmr_fid 1872 * Filtering ID. 1873 * Access: Index 1874 */ 1875 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1876 1877 /* reg_sfmr_fid_offset 1878 * FID offset. 1879 * Used to point into the flooding table selected by SFGC register if 1880 * the table is of type FID-Offset. Otherwise, this field is reserved. 1881 * Access: RW 1882 */ 1883 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1884 1885 /* reg_sfmr_vtfp 1886 * Valid Tunnel Flood Pointer. 1887 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1888 * Access: RW 1889 * 1890 * Note: Reserved for 802.1Q FIDs. 1891 */ 1892 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1893 1894 /* reg_sfmr_nve_tunnel_flood_ptr 1895 * Underlay Flooding and BC Pointer. 1896 * Used as a pointer to the first entry of the group based link lists of 1897 * flooding or BC entries (for NVE tunnels). 1898 * Access: RW 1899 */ 1900 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1901 1902 /* reg_sfmr_vv 1903 * VNI Valid. 1904 * If not set, then vni is reserved. 1905 * Access: RW 1906 * 1907 * Note: Reserved for 802.1Q FIDs. 1908 */ 1909 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1910 1911 /* reg_sfmr_vni 1912 * Virtual Network Identifier. 1913 * Access: RW 1914 * 1915 * Note: A given VNI can only be assigned to one FID. 1916 */ 1917 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1918 1919 static inline void mlxsw_reg_sfmr_pack(char *payload, 1920 enum mlxsw_reg_sfmr_op op, u16 fid, 1921 u16 fid_offset) 1922 { 1923 MLXSW_REG_ZERO(sfmr, payload); 1924 mlxsw_reg_sfmr_op_set(payload, op); 1925 mlxsw_reg_sfmr_fid_set(payload, fid); 1926 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1927 mlxsw_reg_sfmr_vtfp_set(payload, false); 1928 mlxsw_reg_sfmr_vv_set(payload, false); 1929 } 1930 1931 /* SPVMLR - Switch Port VLAN MAC Learning Register 1932 * ----------------------------------------------- 1933 * Controls the switch MAC learning policy per {Port, VID}. 1934 */ 1935 #define MLXSW_REG_SPVMLR_ID 0x2020 1936 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1937 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1938 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1939 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1940 MLXSW_REG_SPVMLR_REC_LEN * \ 1941 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1942 1943 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1944 1945 /* reg_spvmlr_local_port 1946 * Local ingress port. 1947 * Access: Index 1948 * 1949 * Note: CPU port is not supported. 1950 */ 1951 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1952 1953 /* reg_spvmlr_num_rec 1954 * Number of records to update. 1955 * Access: OP 1956 */ 1957 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1958 1959 /* reg_spvmlr_rec_learn_enable 1960 * 0 - Disable learning for {Port, VID}. 1961 * 1 - Enable learning for {Port, VID}. 1962 * Access: RW 1963 */ 1964 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1965 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1966 1967 /* reg_spvmlr_rec_vid 1968 * VLAN ID to be added/removed from port or for querying. 1969 * Access: Index 1970 */ 1971 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1972 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1973 1974 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1975 u16 vid_begin, u16 vid_end, 1976 bool learn_enable) 1977 { 1978 int num_rec = vid_end - vid_begin + 1; 1979 int i; 1980 1981 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1982 1983 MLXSW_REG_ZERO(spvmlr, payload); 1984 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1985 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1986 1987 for (i = 0; i < num_rec; i++) { 1988 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1989 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1990 } 1991 } 1992 1993 /* SPVC - Switch Port VLAN Classification Register 1994 * ----------------------------------------------- 1995 * Configures the port to identify packets as untagged / single tagged / 1996 * double packets based on the packet EtherTypes. 1997 * Ethertype IDs are configured by SVER. 1998 */ 1999 #define MLXSW_REG_SPVC_ID 0x2026 2000 #define MLXSW_REG_SPVC_LEN 0x0C 2001 2002 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2003 2004 /* reg_spvc_local_port 2005 * Local port. 2006 * Access: Index 2007 * 2008 * Note: applies both to Rx port and Tx port, so if a packet traverses 2009 * through Rx port i and a Tx port j then port i and port j must have the 2010 * same configuration. 2011 */ 2012 MLXSW_ITEM32(reg, spvc, local_port, 0x00, 16, 8); 2013 2014 /* reg_spvc_inner_et2 2015 * Vlan Tag1 EtherType2 enable. 2016 * Packet is initially classified as double VLAN Tag if in addition to 2017 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2018 * equal to ether_type2. 2019 * 0: disable (default) 2020 * 1: enable 2021 * Access: RW 2022 */ 2023 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2024 2025 /* reg_spvc_et2 2026 * Vlan Tag0 EtherType2 enable. 2027 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2028 * equal to ether_type2. 2029 * 0: disable (default) 2030 * 1: enable 2031 * Access: RW 2032 */ 2033 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2034 2035 /* reg_spvc_inner_et1 2036 * Vlan Tag1 EtherType1 enable. 2037 * Packet is initially classified as double VLAN Tag if in addition to 2038 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2039 * equal to ether_type1. 2040 * 0: disable 2041 * 1: enable (default) 2042 * Access: RW 2043 */ 2044 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2045 2046 /* reg_spvc_et1 2047 * Vlan Tag0 EtherType1 enable. 2048 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2049 * equal to ether_type1. 2050 * 0: disable 2051 * 1: enable (default) 2052 * Access: RW 2053 */ 2054 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2055 2056 /* reg_inner_et0 2057 * Vlan Tag1 EtherType0 enable. 2058 * Packet is initially classified as double VLAN Tag if in addition to 2059 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2060 * equal to ether_type0. 2061 * 0: disable 2062 * 1: enable (default) 2063 * Access: RW 2064 */ 2065 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2066 2067 /* reg_et0 2068 * Vlan Tag0 EtherType0 enable. 2069 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2070 * equal to ether_type0. 2071 * 0: disable 2072 * 1: enable (default) 2073 * Access: RW 2074 */ 2075 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2076 2077 static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1, 2078 bool et0) 2079 { 2080 MLXSW_REG_ZERO(spvc, payload); 2081 mlxsw_reg_spvc_local_port_set(payload, local_port); 2082 /* Enable inner_et1 and inner_et0 to enable identification of double 2083 * tagged packets. 2084 */ 2085 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2086 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2087 mlxsw_reg_spvc_et1_set(payload, et1); 2088 mlxsw_reg_spvc_et0_set(payload, et0); 2089 } 2090 2091 /* SPEVET - Switch Port Egress VLAN EtherType 2092 * ------------------------------------------ 2093 * The switch port egress VLAN EtherType configures which EtherType to push at 2094 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2095 * is set. 2096 */ 2097 #define MLXSW_REG_SPEVET_ID 0x202A 2098 #define MLXSW_REG_SPEVET_LEN 0x08 2099 2100 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2101 2102 /* reg_spevet_local_port 2103 * Egress Local port number. 2104 * Not supported to CPU port. 2105 * Access: Index 2106 */ 2107 MLXSW_ITEM32(reg, spevet, local_port, 0x00, 16, 8); 2108 2109 /* reg_spevet_et_vlan 2110 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2111 * 0: ether_type0 - (default) 2112 * 1: ether_type1 2113 * 2: ether_type2 2114 * Access: RW 2115 */ 2116 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2117 2118 static inline void mlxsw_reg_spevet_pack(char *payload, u8 local_port, 2119 u8 et_vlan) 2120 { 2121 MLXSW_REG_ZERO(spevet, payload); 2122 mlxsw_reg_spevet_local_port_set(payload, local_port); 2123 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2124 } 2125 2126 /* CWTP - Congetion WRED ECN TClass Profile 2127 * ---------------------------------------- 2128 * Configures the profiles for queues of egress port and traffic class 2129 */ 2130 #define MLXSW_REG_CWTP_ID 0x2802 2131 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2132 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2133 #define MLXSW_REG_CWTP_LEN 0x40 2134 2135 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2136 2137 /* reg_cwtp_local_port 2138 * Local port number 2139 * Not supported for CPU port 2140 * Access: Index 2141 */ 2142 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 2143 2144 /* reg_cwtp_traffic_class 2145 * Traffic Class to configure 2146 * Access: Index 2147 */ 2148 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2149 2150 /* reg_cwtp_profile_min 2151 * Minimum Average Queue Size of the profile in cells. 2152 * Access: RW 2153 */ 2154 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2155 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2156 2157 /* reg_cwtp_profile_percent 2158 * Percentage of WRED and ECN marking for maximum Average Queue size 2159 * Range is 0 to 100, units of integer percentage 2160 * Access: RW 2161 */ 2162 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2163 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2164 2165 /* reg_cwtp_profile_max 2166 * Maximum Average Queue size of the profile in cells 2167 * Access: RW 2168 */ 2169 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2170 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2171 2172 #define MLXSW_REG_CWTP_MIN_VALUE 64 2173 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2174 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2175 2176 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 2177 u8 traffic_class) 2178 { 2179 int i; 2180 2181 MLXSW_REG_ZERO(cwtp, payload); 2182 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2183 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2184 2185 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2186 mlxsw_reg_cwtp_profile_min_set(payload, i, 2187 MLXSW_REG_CWTP_MIN_VALUE); 2188 mlxsw_reg_cwtp_profile_max_set(payload, i, 2189 MLXSW_REG_CWTP_MIN_VALUE); 2190 } 2191 } 2192 2193 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2194 2195 static inline void 2196 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2197 u32 probability) 2198 { 2199 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2200 2201 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2202 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2203 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2204 } 2205 2206 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2207 * --------------------------------------------------- 2208 * The CWTPM register maps each egress port and traffic class to profile num. 2209 */ 2210 #define MLXSW_REG_CWTPM_ID 0x2803 2211 #define MLXSW_REG_CWTPM_LEN 0x44 2212 2213 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2214 2215 /* reg_cwtpm_local_port 2216 * Local port number 2217 * Not supported for CPU port 2218 * Access: Index 2219 */ 2220 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 2221 2222 /* reg_cwtpm_traffic_class 2223 * Traffic Class to configure 2224 * Access: Index 2225 */ 2226 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2227 2228 /* reg_cwtpm_ew 2229 * Control enablement of WRED for traffic class: 2230 * 0 - Disable 2231 * 1 - Enable 2232 * Access: RW 2233 */ 2234 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2235 2236 /* reg_cwtpm_ee 2237 * Control enablement of ECN for traffic class: 2238 * 0 - Disable 2239 * 1 - Enable 2240 * Access: RW 2241 */ 2242 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2243 2244 /* reg_cwtpm_tcp_g 2245 * TCP Green Profile. 2246 * Index of the profile within {port, traffic class} to use. 2247 * 0 for disabling both WRED and ECN for this type of traffic. 2248 * Access: RW 2249 */ 2250 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2251 2252 /* reg_cwtpm_tcp_y 2253 * TCP Yellow Profile. 2254 * Index of the profile within {port, traffic class} to use. 2255 * 0 for disabling both WRED and ECN for this type of traffic. 2256 * Access: RW 2257 */ 2258 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2259 2260 /* reg_cwtpm_tcp_r 2261 * TCP Red Profile. 2262 * Index of the profile within {port, traffic class} to use. 2263 * 0 for disabling both WRED and ECN for this type of traffic. 2264 * Access: RW 2265 */ 2266 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2267 2268 /* reg_cwtpm_ntcp_g 2269 * Non-TCP Green Profile. 2270 * Index of the profile within {port, traffic class} to use. 2271 * 0 for disabling both WRED and ECN for this type of traffic. 2272 * Access: RW 2273 */ 2274 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2275 2276 /* reg_cwtpm_ntcp_y 2277 * Non-TCP Yellow Profile. 2278 * Index of the profile within {port, traffic class} to use. 2279 * 0 for disabling both WRED and ECN for this type of traffic. 2280 * Access: RW 2281 */ 2282 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2283 2284 /* reg_cwtpm_ntcp_r 2285 * Non-TCP Red Profile. 2286 * Index of the profile within {port, traffic class} to use. 2287 * 0 for disabling both WRED and ECN for this type of traffic. 2288 * Access: RW 2289 */ 2290 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2291 2292 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2293 2294 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2295 u8 traffic_class, u8 profile, 2296 bool wred, bool ecn) 2297 { 2298 MLXSW_REG_ZERO(cwtpm, payload); 2299 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2300 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2301 mlxsw_reg_cwtpm_ew_set(payload, wred); 2302 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2303 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2304 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2305 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2306 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2307 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2308 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2309 } 2310 2311 /* PGCR - Policy-Engine General Configuration Register 2312 * --------------------------------------------------- 2313 * This register configures general Policy-Engine settings. 2314 */ 2315 #define MLXSW_REG_PGCR_ID 0x3001 2316 #define MLXSW_REG_PGCR_LEN 0x20 2317 2318 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2319 2320 /* reg_pgcr_default_action_pointer_base 2321 * Default action pointer base. Each region has a default action pointer 2322 * which is equal to default_action_pointer_base + region_id. 2323 * Access: RW 2324 */ 2325 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2326 2327 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2328 { 2329 MLXSW_REG_ZERO(pgcr, payload); 2330 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2331 } 2332 2333 /* PPBT - Policy-Engine Port Binding Table 2334 * --------------------------------------- 2335 * This register is used for configuration of the Port Binding Table. 2336 */ 2337 #define MLXSW_REG_PPBT_ID 0x3002 2338 #define MLXSW_REG_PPBT_LEN 0x14 2339 2340 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2341 2342 enum mlxsw_reg_pxbt_e { 2343 MLXSW_REG_PXBT_E_IACL, 2344 MLXSW_REG_PXBT_E_EACL, 2345 }; 2346 2347 /* reg_ppbt_e 2348 * Access: Index 2349 */ 2350 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2351 2352 enum mlxsw_reg_pxbt_op { 2353 MLXSW_REG_PXBT_OP_BIND, 2354 MLXSW_REG_PXBT_OP_UNBIND, 2355 }; 2356 2357 /* reg_ppbt_op 2358 * Access: RW 2359 */ 2360 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2361 2362 /* reg_ppbt_local_port 2363 * Local port. Not including CPU port. 2364 * Access: Index 2365 */ 2366 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2367 2368 /* reg_ppbt_g 2369 * group - When set, the binding is of an ACL group. When cleared, 2370 * the binding is of an ACL. 2371 * Must be set to 1 for Spectrum. 2372 * Access: RW 2373 */ 2374 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2375 2376 /* reg_ppbt_acl_info 2377 * ACL/ACL group identifier. If the g bit is set, this field should hold 2378 * the acl_group_id, else it should hold the acl_id. 2379 * Access: RW 2380 */ 2381 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2382 2383 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2384 enum mlxsw_reg_pxbt_op op, 2385 u8 local_port, u16 acl_info) 2386 { 2387 MLXSW_REG_ZERO(ppbt, payload); 2388 mlxsw_reg_ppbt_e_set(payload, e); 2389 mlxsw_reg_ppbt_op_set(payload, op); 2390 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2391 mlxsw_reg_ppbt_g_set(payload, true); 2392 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2393 } 2394 2395 /* PACL - Policy-Engine ACL Register 2396 * --------------------------------- 2397 * This register is used for configuration of the ACL. 2398 */ 2399 #define MLXSW_REG_PACL_ID 0x3004 2400 #define MLXSW_REG_PACL_LEN 0x70 2401 2402 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2403 2404 /* reg_pacl_v 2405 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2406 * while the ACL is bounded to either a port, VLAN or ACL rule. 2407 * Access: RW 2408 */ 2409 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2410 2411 /* reg_pacl_acl_id 2412 * An identifier representing the ACL (managed by software) 2413 * Range 0 .. cap_max_acl_regions - 1 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2417 2418 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2419 2420 /* reg_pacl_tcam_region_info 2421 * Opaque object that represents a TCAM region. 2422 * Obtained through PTAR register. 2423 * Access: RW 2424 */ 2425 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2426 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2427 2428 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2429 bool valid, const char *tcam_region_info) 2430 { 2431 MLXSW_REG_ZERO(pacl, payload); 2432 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2433 mlxsw_reg_pacl_v_set(payload, valid); 2434 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2435 } 2436 2437 /* PAGT - Policy-Engine ACL Group Table 2438 * ------------------------------------ 2439 * This register is used for configuration of the ACL Group Table. 2440 */ 2441 #define MLXSW_REG_PAGT_ID 0x3005 2442 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2443 #define MLXSW_REG_PAGT_ACL_LEN 4 2444 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2445 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2446 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2447 2448 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2449 2450 /* reg_pagt_size 2451 * Number of ACLs in the group. 2452 * Size 0 invalidates a group. 2453 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2454 * Total number of ACLs in all groups must be lower or equal 2455 * to cap_max_acl_tot_groups 2456 * Note: a group which is binded must not be invalidated 2457 * Access: Index 2458 */ 2459 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2460 2461 /* reg_pagt_acl_group_id 2462 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2463 * the ACL Group identifier (managed by software). 2464 * Access: Index 2465 */ 2466 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2467 2468 /* reg_pagt_multi 2469 * Multi-ACL 2470 * 0 - This ACL is the last ACL in the multi-ACL 2471 * 1 - This ACL is part of a multi-ACL 2472 * Access: RW 2473 */ 2474 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2475 2476 /* reg_pagt_acl_id 2477 * ACL identifier 2478 * Access: RW 2479 */ 2480 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2481 2482 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2483 { 2484 MLXSW_REG_ZERO(pagt, payload); 2485 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2486 } 2487 2488 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2489 u16 acl_id, bool multi) 2490 { 2491 u8 size = mlxsw_reg_pagt_size_get(payload); 2492 2493 if (index >= size) 2494 mlxsw_reg_pagt_size_set(payload, index + 1); 2495 mlxsw_reg_pagt_multi_set(payload, index, multi); 2496 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2497 } 2498 2499 /* PTAR - Policy-Engine TCAM Allocation Register 2500 * --------------------------------------------- 2501 * This register is used for allocation of regions in the TCAM. 2502 * Note: Query method is not supported on this register. 2503 */ 2504 #define MLXSW_REG_PTAR_ID 0x3006 2505 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2506 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2507 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2508 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2509 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2510 2511 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2512 2513 enum mlxsw_reg_ptar_op { 2514 /* allocate a TCAM region */ 2515 MLXSW_REG_PTAR_OP_ALLOC, 2516 /* resize a TCAM region */ 2517 MLXSW_REG_PTAR_OP_RESIZE, 2518 /* deallocate TCAM region */ 2519 MLXSW_REG_PTAR_OP_FREE, 2520 /* test allocation */ 2521 MLXSW_REG_PTAR_OP_TEST, 2522 }; 2523 2524 /* reg_ptar_op 2525 * Access: OP 2526 */ 2527 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2528 2529 /* reg_ptar_action_set_type 2530 * Type of action set to be used on this region. 2531 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2532 * Access: WO 2533 */ 2534 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2535 2536 enum mlxsw_reg_ptar_key_type { 2537 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2538 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2539 }; 2540 2541 /* reg_ptar_key_type 2542 * TCAM key type for the region. 2543 * Access: WO 2544 */ 2545 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2546 2547 /* reg_ptar_region_size 2548 * TCAM region size. When allocating/resizing this is the requested size, 2549 * the response is the actual size. Note that actual size may be 2550 * larger than requested. 2551 * Allowed range 1 .. cap_max_rules-1 2552 * Reserved during op deallocate. 2553 * Access: WO 2554 */ 2555 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2556 2557 /* reg_ptar_region_id 2558 * Region identifier 2559 * Range 0 .. cap_max_regions-1 2560 * Access: Index 2561 */ 2562 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2563 2564 /* reg_ptar_tcam_region_info 2565 * Opaque object that represents the TCAM region. 2566 * Returned when allocating a region. 2567 * Provided by software for ACL generation and region deallocation and resize. 2568 * Access: RW 2569 */ 2570 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2571 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2572 2573 /* reg_ptar_flexible_key_id 2574 * Identifier of the Flexible Key. 2575 * Only valid if key_type == "FLEX_KEY" 2576 * The key size will be rounded up to one of the following values: 2577 * 9B, 18B, 36B, 54B. 2578 * This field is reserved for in resize operation. 2579 * Access: WO 2580 */ 2581 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2582 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2583 2584 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2585 enum mlxsw_reg_ptar_key_type key_type, 2586 u16 region_size, u16 region_id, 2587 const char *tcam_region_info) 2588 { 2589 MLXSW_REG_ZERO(ptar, payload); 2590 mlxsw_reg_ptar_op_set(payload, op); 2591 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2592 mlxsw_reg_ptar_key_type_set(payload, key_type); 2593 mlxsw_reg_ptar_region_size_set(payload, region_size); 2594 mlxsw_reg_ptar_region_id_set(payload, region_id); 2595 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2596 } 2597 2598 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2599 u16 key_id) 2600 { 2601 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2602 } 2603 2604 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2605 { 2606 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2607 } 2608 2609 /* PPBS - Policy-Engine Policy Based Switching Register 2610 * ---------------------------------------------------- 2611 * This register retrieves and sets Policy Based Switching Table entries. 2612 */ 2613 #define MLXSW_REG_PPBS_ID 0x300C 2614 #define MLXSW_REG_PPBS_LEN 0x14 2615 2616 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2617 2618 /* reg_ppbs_pbs_ptr 2619 * Index into the PBS table. 2620 * For Spectrum, the index points to the KVD Linear. 2621 * Access: Index 2622 */ 2623 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2624 2625 /* reg_ppbs_system_port 2626 * Unique port identifier for the final destination of the packet. 2627 * Access: RW 2628 */ 2629 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2630 2631 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2632 u16 system_port) 2633 { 2634 MLXSW_REG_ZERO(ppbs, payload); 2635 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2636 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2637 } 2638 2639 /* PRCR - Policy-Engine Rules Copy Register 2640 * ---------------------------------------- 2641 * This register is used for accessing rules within a TCAM region. 2642 */ 2643 #define MLXSW_REG_PRCR_ID 0x300D 2644 #define MLXSW_REG_PRCR_LEN 0x40 2645 2646 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2647 2648 enum mlxsw_reg_prcr_op { 2649 /* Move rules. Moves the rules from "tcam_region_info" starting 2650 * at offset "offset" to "dest_tcam_region_info" 2651 * at offset "dest_offset." 2652 */ 2653 MLXSW_REG_PRCR_OP_MOVE, 2654 /* Copy rules. Copies the rules from "tcam_region_info" starting 2655 * at offset "offset" to "dest_tcam_region_info" 2656 * at offset "dest_offset." 2657 */ 2658 MLXSW_REG_PRCR_OP_COPY, 2659 }; 2660 2661 /* reg_prcr_op 2662 * Access: OP 2663 */ 2664 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2665 2666 /* reg_prcr_offset 2667 * Offset within the source region to copy/move from. 2668 * Access: Index 2669 */ 2670 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2671 2672 /* reg_prcr_size 2673 * The number of rules to copy/move. 2674 * Access: WO 2675 */ 2676 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2677 2678 /* reg_prcr_tcam_region_info 2679 * Opaque object that represents the source TCAM region. 2680 * Access: Index 2681 */ 2682 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2683 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2684 2685 /* reg_prcr_dest_offset 2686 * Offset within the source region to copy/move to. 2687 * Access: Index 2688 */ 2689 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2690 2691 /* reg_prcr_dest_tcam_region_info 2692 * Opaque object that represents the destination TCAM region. 2693 * Access: Index 2694 */ 2695 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2696 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2697 2698 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2699 const char *src_tcam_region_info, 2700 u16 src_offset, 2701 const char *dest_tcam_region_info, 2702 u16 dest_offset, u16 size) 2703 { 2704 MLXSW_REG_ZERO(prcr, payload); 2705 mlxsw_reg_prcr_op_set(payload, op); 2706 mlxsw_reg_prcr_offset_set(payload, src_offset); 2707 mlxsw_reg_prcr_size_set(payload, size); 2708 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2709 src_tcam_region_info); 2710 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2711 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2712 dest_tcam_region_info); 2713 } 2714 2715 /* PEFA - Policy-Engine Extended Flexible Action Register 2716 * ------------------------------------------------------ 2717 * This register is used for accessing an extended flexible action entry 2718 * in the central KVD Linear Database. 2719 */ 2720 #define MLXSW_REG_PEFA_ID 0x300F 2721 #define MLXSW_REG_PEFA_LEN 0xB0 2722 2723 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2724 2725 /* reg_pefa_index 2726 * Index in the KVD Linear Centralized Database. 2727 * Access: Index 2728 */ 2729 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2730 2731 /* reg_pefa_a 2732 * Index in the KVD Linear Centralized Database. 2733 * Activity 2734 * For a new entry: set if ca=0, clear if ca=1 2735 * Set if a packet lookup has hit on the specific entry 2736 * Access: RO 2737 */ 2738 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2739 2740 /* reg_pefa_ca 2741 * Clear activity 2742 * When write: activity is according to this field 2743 * When read: after reading the activity is cleared according to ca 2744 * Access: OP 2745 */ 2746 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2747 2748 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2749 2750 /* reg_pefa_flex_action_set 2751 * Action-set to perform when rule is matched. 2752 * Must be zero padded if action set is shorter. 2753 * Access: RW 2754 */ 2755 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2756 2757 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2758 const char *flex_action_set) 2759 { 2760 MLXSW_REG_ZERO(pefa, payload); 2761 mlxsw_reg_pefa_index_set(payload, index); 2762 mlxsw_reg_pefa_ca_set(payload, ca); 2763 if (flex_action_set) 2764 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2765 flex_action_set); 2766 } 2767 2768 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2769 { 2770 *p_a = mlxsw_reg_pefa_a_get(payload); 2771 } 2772 2773 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2774 * -------------------------------------------------------------- 2775 * This register is used for binding Multicast router to an ACL group 2776 * that serves the MC router. 2777 * This register is not supported by SwitchX/-2 and Spectrum. 2778 */ 2779 #define MLXSW_REG_PEMRBT_ID 0x3014 2780 #define MLXSW_REG_PEMRBT_LEN 0x14 2781 2782 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2783 2784 enum mlxsw_reg_pemrbt_protocol { 2785 MLXSW_REG_PEMRBT_PROTO_IPV4, 2786 MLXSW_REG_PEMRBT_PROTO_IPV6, 2787 }; 2788 2789 /* reg_pemrbt_protocol 2790 * Access: Index 2791 */ 2792 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2793 2794 /* reg_pemrbt_group_id 2795 * ACL group identifier. 2796 * Range 0..cap_max_acl_groups-1 2797 * Access: RW 2798 */ 2799 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2800 2801 static inline void 2802 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2803 u16 group_id) 2804 { 2805 MLXSW_REG_ZERO(pemrbt, payload); 2806 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2807 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2808 } 2809 2810 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2811 * ----------------------------------------------------- 2812 * This register is used for accessing rules within a TCAM region. 2813 * It is a new version of PTCE in order to support wider key, 2814 * mask and action within a TCAM region. This register is not supported 2815 * by SwitchX and SwitchX-2. 2816 */ 2817 #define MLXSW_REG_PTCE2_ID 0x3017 2818 #define MLXSW_REG_PTCE2_LEN 0x1D8 2819 2820 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2821 2822 /* reg_ptce2_v 2823 * Valid. 2824 * Access: RW 2825 */ 2826 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2827 2828 /* reg_ptce2_a 2829 * Activity. Set if a packet lookup has hit on the specific entry. 2830 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2831 * Access: RO 2832 */ 2833 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2834 2835 enum mlxsw_reg_ptce2_op { 2836 /* Read operation. */ 2837 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2838 /* clear on read operation. Used to read entry 2839 * and clear Activity bit. 2840 */ 2841 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2842 /* Write operation. Used to write a new entry to the table. 2843 * All R/W fields are relevant for new entry. Activity bit is set 2844 * for new entries - Note write with v = 0 will delete the entry. 2845 */ 2846 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2847 /* Update action. Only action set will be updated. */ 2848 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2849 /* Clear activity. A bit is cleared for the entry. */ 2850 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2851 }; 2852 2853 /* reg_ptce2_op 2854 * Access: OP 2855 */ 2856 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2857 2858 /* reg_ptce2_offset 2859 * Access: Index 2860 */ 2861 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2862 2863 /* reg_ptce2_priority 2864 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2865 * Note: priority does not have to be unique per rule. 2866 * Within a region, higher priority should have lower offset (no limitation 2867 * between regions in a multi-region). 2868 * Access: RW 2869 */ 2870 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2871 2872 /* reg_ptce2_tcam_region_info 2873 * Opaque object that represents the TCAM region. 2874 * Access: Index 2875 */ 2876 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2877 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2878 2879 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2880 2881 /* reg_ptce2_flex_key_blocks 2882 * ACL Key. 2883 * Access: RW 2884 */ 2885 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2886 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2887 2888 /* reg_ptce2_mask 2889 * mask- in the same size as key. A bit that is set directs the TCAM 2890 * to compare the corresponding bit in key. A bit that is clear directs 2891 * the TCAM to ignore the corresponding bit in key. 2892 * Access: RW 2893 */ 2894 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2895 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2896 2897 /* reg_ptce2_flex_action_set 2898 * ACL action set. 2899 * Access: RW 2900 */ 2901 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2902 MLXSW_REG_FLEX_ACTION_SET_LEN); 2903 2904 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2905 enum mlxsw_reg_ptce2_op op, 2906 const char *tcam_region_info, 2907 u16 offset, u32 priority) 2908 { 2909 MLXSW_REG_ZERO(ptce2, payload); 2910 mlxsw_reg_ptce2_v_set(payload, valid); 2911 mlxsw_reg_ptce2_op_set(payload, op); 2912 mlxsw_reg_ptce2_offset_set(payload, offset); 2913 mlxsw_reg_ptce2_priority_set(payload, priority); 2914 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2915 } 2916 2917 /* PERPT - Policy-Engine ERP Table Register 2918 * ---------------------------------------- 2919 * This register adds and removes eRPs from the eRP table. 2920 */ 2921 #define MLXSW_REG_PERPT_ID 0x3021 2922 #define MLXSW_REG_PERPT_LEN 0x80 2923 2924 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2925 2926 /* reg_perpt_erpt_bank 2927 * eRP table bank. 2928 * Range 0 .. cap_max_erp_table_banks - 1 2929 * Access: Index 2930 */ 2931 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2932 2933 /* reg_perpt_erpt_index 2934 * Index to eRP table within the eRP bank. 2935 * Range is 0 .. cap_max_erp_table_bank_size - 1 2936 * Access: Index 2937 */ 2938 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2939 2940 enum mlxsw_reg_perpt_key_size { 2941 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2942 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2943 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2944 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2945 }; 2946 2947 /* reg_perpt_key_size 2948 * Access: OP 2949 */ 2950 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2951 2952 /* reg_perpt_bf_bypass 2953 * 0 - The eRP is used only if bloom filter state is set for the given 2954 * rule. 2955 * 1 - The eRP is used regardless of bloom filter state. 2956 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2957 * Access: RW 2958 */ 2959 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2960 2961 /* reg_perpt_erp_id 2962 * eRP ID for use by the rules. 2963 * Access: RW 2964 */ 2965 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2966 2967 /* reg_perpt_erpt_base_bank 2968 * Base eRP table bank, points to head of erp_vector 2969 * Range is 0 .. cap_max_erp_table_banks - 1 2970 * Access: OP 2971 */ 2972 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2973 2974 /* reg_perpt_erpt_base_index 2975 * Base index to eRP table within the eRP bank 2976 * Range is 0 .. cap_max_erp_table_bank_size - 1 2977 * Access: OP 2978 */ 2979 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2980 2981 /* reg_perpt_erp_index_in_vector 2982 * eRP index in the vector. 2983 * Access: OP 2984 */ 2985 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2986 2987 /* reg_perpt_erp_vector 2988 * eRP vector. 2989 * Access: OP 2990 */ 2991 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2992 2993 /* reg_perpt_mask 2994 * Mask 2995 * 0 - A-TCAM will ignore the bit in key 2996 * 1 - A-TCAM will compare the bit in key 2997 * Access: RW 2998 */ 2999 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3000 3001 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3002 unsigned long *erp_vector, 3003 unsigned long size) 3004 { 3005 unsigned long bit; 3006 3007 for_each_set_bit(bit, erp_vector, size) 3008 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3009 } 3010 3011 static inline void 3012 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3013 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3014 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3015 char *mask) 3016 { 3017 MLXSW_REG_ZERO(perpt, payload); 3018 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3019 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3020 mlxsw_reg_perpt_key_size_set(payload, key_size); 3021 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3022 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3023 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3024 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3025 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3026 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3027 } 3028 3029 /* PERAR - Policy-Engine Region Association Register 3030 * ------------------------------------------------- 3031 * This register associates a hw region for region_id's. Changing on the fly 3032 * is supported by the device. 3033 */ 3034 #define MLXSW_REG_PERAR_ID 0x3026 3035 #define MLXSW_REG_PERAR_LEN 0x08 3036 3037 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3038 3039 /* reg_perar_region_id 3040 * Region identifier 3041 * Range 0 .. cap_max_regions-1 3042 * Access: Index 3043 */ 3044 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3045 3046 static inline unsigned int 3047 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3048 { 3049 return DIV_ROUND_UP(block_num, 4); 3050 } 3051 3052 /* reg_perar_hw_region 3053 * HW Region 3054 * Range 0 .. cap_max_regions-1 3055 * Default: hw_region = region_id 3056 * For a 8 key block region, 2 consecutive regions are used 3057 * For a 12 key block region, 3 consecutive regions are used 3058 * Access: RW 3059 */ 3060 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3061 3062 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3063 u16 hw_region) 3064 { 3065 MLXSW_REG_ZERO(perar, payload); 3066 mlxsw_reg_perar_region_id_set(payload, region_id); 3067 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3068 } 3069 3070 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3071 * ----------------------------------------------------- 3072 * This register is a new version of PTCE-V2 in order to support the 3073 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3074 */ 3075 #define MLXSW_REG_PTCE3_ID 0x3027 3076 #define MLXSW_REG_PTCE3_LEN 0xF0 3077 3078 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3079 3080 /* reg_ptce3_v 3081 * Valid. 3082 * Access: RW 3083 */ 3084 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3085 3086 enum mlxsw_reg_ptce3_op { 3087 /* Write operation. Used to write a new entry to the table. 3088 * All R/W fields are relevant for new entry. Activity bit is set 3089 * for new entries. Write with v = 0 will delete the entry. Must 3090 * not be used if an entry exists. 3091 */ 3092 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3093 /* Update operation */ 3094 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3095 /* Read operation */ 3096 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3097 }; 3098 3099 /* reg_ptce3_op 3100 * Access: OP 3101 */ 3102 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3103 3104 /* reg_ptce3_priority 3105 * Priority of the rule. Higher values win. 3106 * For Spectrum-2 range is 1..cap_kvd_size - 1 3107 * Note: Priority does not have to be unique per rule. 3108 * Access: RW 3109 */ 3110 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3111 3112 /* reg_ptce3_tcam_region_info 3113 * Opaque object that represents the TCAM region. 3114 * Access: Index 3115 */ 3116 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3117 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3118 3119 /* reg_ptce3_flex2_key_blocks 3120 * ACL key. The key must be masked according to eRP (if exists) or 3121 * according to master mask. 3122 * Access: Index 3123 */ 3124 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3125 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3126 3127 /* reg_ptce3_erp_id 3128 * eRP ID. 3129 * Access: Index 3130 */ 3131 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3132 3133 /* reg_ptce3_delta_start 3134 * Start point of delta_value and delta_mask, in bits. Must not exceed 3135 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3136 * Access: Index 3137 */ 3138 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3139 3140 /* reg_ptce3_delta_mask 3141 * Delta mask. 3142 * 0 - Ignore relevant bit in delta_value 3143 * 1 - Compare relevant bit in delta_value 3144 * Delta mask must not be set for reserved fields in the key blocks. 3145 * Note: No delta when no eRPs. Thus, for regions with 3146 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3147 * Access: Index 3148 */ 3149 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3150 3151 /* reg_ptce3_delta_value 3152 * Delta value. 3153 * Bits which are masked by delta_mask must be 0. 3154 * Access: Index 3155 */ 3156 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3157 3158 /* reg_ptce3_prune_vector 3159 * Pruning vector relative to the PERPT.erp_id. 3160 * Used for reducing lookups. 3161 * 0 - NEED: Do a lookup using the eRP. 3162 * 1 - PRUNE: Do not perform a lookup using the eRP. 3163 * Maybe be modified by PEAPBL and PEAPBM. 3164 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3165 * all 1's or all 0's. 3166 * Access: RW 3167 */ 3168 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3169 3170 /* reg_ptce3_prune_ctcam 3171 * Pruning on C-TCAM. Used for reducing lookups. 3172 * 0 - NEED: Do a lookup in the C-TCAM. 3173 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3174 * Access: RW 3175 */ 3176 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3177 3178 /* reg_ptce3_large_exists 3179 * Large entry key ID exists. 3180 * Within the region: 3181 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3182 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3183 * For rule delete: The MSB of the key will be removed. 3184 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3185 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3186 * For rule delete: The MSB of the key will not be removed. 3187 * Access: WO 3188 */ 3189 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3190 3191 /* reg_ptce3_large_entry_key_id 3192 * Large entry key ID. 3193 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3194 * blocks. Must be different for different keys which have the same common 3195 * 6 key blocks (MSB, blocks 6..11) key within a region. 3196 * Range is 0..cap_max_pe_large_key_id - 1 3197 * Access: RW 3198 */ 3199 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3200 3201 /* reg_ptce3_action_pointer 3202 * Pointer to action. 3203 * Range is 0..cap_max_kvd_action_sets - 1 3204 * Access: RW 3205 */ 3206 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3207 3208 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3209 enum mlxsw_reg_ptce3_op op, 3210 u32 priority, 3211 const char *tcam_region_info, 3212 const char *key, u8 erp_id, 3213 u16 delta_start, u8 delta_mask, 3214 u8 delta_value, bool large_exists, 3215 u32 lkey_id, u32 action_pointer) 3216 { 3217 MLXSW_REG_ZERO(ptce3, payload); 3218 mlxsw_reg_ptce3_v_set(payload, valid); 3219 mlxsw_reg_ptce3_op_set(payload, op); 3220 mlxsw_reg_ptce3_priority_set(payload, priority); 3221 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3222 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3223 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3224 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3225 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3226 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3227 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3228 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3229 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3230 } 3231 3232 /* PERCR - Policy-Engine Region Configuration Register 3233 * --------------------------------------------------- 3234 * This register configures the region parameters. The region_id must be 3235 * allocated. 3236 */ 3237 #define MLXSW_REG_PERCR_ID 0x302A 3238 #define MLXSW_REG_PERCR_LEN 0x80 3239 3240 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3241 3242 /* reg_percr_region_id 3243 * Region identifier. 3244 * Range 0..cap_max_regions-1 3245 * Access: Index 3246 */ 3247 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3248 3249 /* reg_percr_atcam_ignore_prune 3250 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3251 * Access: RW 3252 */ 3253 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3254 3255 /* reg_percr_ctcam_ignore_prune 3256 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3257 * Access: RW 3258 */ 3259 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3260 3261 /* reg_percr_bf_bypass 3262 * Bloom filter bypass. 3263 * 0 - Bloom filter is used (default) 3264 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3265 * region_id or eRP. See PERPT.bf_bypass 3266 * Access: RW 3267 */ 3268 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3269 3270 /* reg_percr_master_mask 3271 * Master mask. Logical OR mask of all masks of all rules of a region 3272 * (both A-TCAM and C-TCAM). When there are no eRPs 3273 * (erpt_pointer_valid = 0), then this provides the mask. 3274 * Access: RW 3275 */ 3276 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3277 3278 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3279 { 3280 MLXSW_REG_ZERO(percr, payload); 3281 mlxsw_reg_percr_region_id_set(payload, region_id); 3282 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3283 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3284 mlxsw_reg_percr_bf_bypass_set(payload, false); 3285 } 3286 3287 /* PERERP - Policy-Engine Region eRP Register 3288 * ------------------------------------------ 3289 * This register configures the region eRP. The region_id must be 3290 * allocated. 3291 */ 3292 #define MLXSW_REG_PERERP_ID 0x302B 3293 #define MLXSW_REG_PERERP_LEN 0x1C 3294 3295 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3296 3297 /* reg_pererp_region_id 3298 * Region identifier. 3299 * Range 0..cap_max_regions-1 3300 * Access: Index 3301 */ 3302 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3303 3304 /* reg_pererp_ctcam_le 3305 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3306 * Access: RW 3307 */ 3308 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3309 3310 /* reg_pererp_erpt_pointer_valid 3311 * erpt_pointer is valid. 3312 * Access: RW 3313 */ 3314 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3315 3316 /* reg_pererp_erpt_bank_pointer 3317 * Pointer to eRP table bank. May be modified at any time. 3318 * Range 0..cap_max_erp_table_banks-1 3319 * Reserved when erpt_pointer_valid = 0 3320 */ 3321 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3322 3323 /* reg_pererp_erpt_pointer 3324 * Pointer to eRP table within the eRP bank. Can be changed for an 3325 * existing region. 3326 * Range 0..cap_max_erp_table_size-1 3327 * Reserved when erpt_pointer_valid = 0 3328 * Access: RW 3329 */ 3330 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3331 3332 /* reg_pererp_erpt_vector 3333 * Vector of allowed eRP indexes starting from erpt_pointer within the 3334 * erpt_bank_pointer. Next entries will be in next bank. 3335 * Note that eRP index is used and not eRP ID. 3336 * Reserved when erpt_pointer_valid = 0 3337 * Access: RW 3338 */ 3339 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3340 3341 /* reg_pererp_master_rp_id 3342 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3343 * for the lookup. Can be changed for an existing region. 3344 * Reserved when erpt_pointer_valid = 1 3345 * Access: RW 3346 */ 3347 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3348 3349 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3350 unsigned long *erp_vector, 3351 unsigned long size) 3352 { 3353 unsigned long bit; 3354 3355 for_each_set_bit(bit, erp_vector, size) 3356 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3357 } 3358 3359 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3360 bool ctcam_le, bool erpt_pointer_valid, 3361 u8 erpt_bank_pointer, u8 erpt_pointer, 3362 u8 master_rp_id) 3363 { 3364 MLXSW_REG_ZERO(pererp, payload); 3365 mlxsw_reg_pererp_region_id_set(payload, region_id); 3366 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3367 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3368 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3369 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3370 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3371 } 3372 3373 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3374 * ---------------------------------------------------------------- 3375 * This register configures the Bloom filter entries. 3376 */ 3377 #define MLXSW_REG_PEABFE_ID 0x3022 3378 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3379 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3380 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3381 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3382 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3383 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3384 3385 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3386 3387 /* reg_peabfe_size 3388 * Number of BF entries to be updated. 3389 * Range 1..256 3390 * Access: Op 3391 */ 3392 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3393 3394 /* reg_peabfe_bf_entry_state 3395 * Bloom filter state 3396 * 0 - Clear 3397 * 1 - Set 3398 * Access: RW 3399 */ 3400 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3401 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3402 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3403 3404 /* reg_peabfe_bf_entry_bank 3405 * Bloom filter bank ID 3406 * Range 0..cap_max_erp_table_banks-1 3407 * Access: Index 3408 */ 3409 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3410 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3411 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3412 3413 /* reg_peabfe_bf_entry_index 3414 * Bloom filter entry index 3415 * Range 0..2^cap_max_bf_log-1 3416 * Access: Index 3417 */ 3418 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3419 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3420 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3421 3422 static inline void mlxsw_reg_peabfe_pack(char *payload) 3423 { 3424 MLXSW_REG_ZERO(peabfe, payload); 3425 } 3426 3427 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3428 u8 state, u8 bank, u32 bf_index) 3429 { 3430 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3431 3432 if (rec_index >= num_rec) 3433 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3434 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3435 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3436 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3437 } 3438 3439 /* IEDR - Infrastructure Entry Delete Register 3440 * ---------------------------------------------------- 3441 * This register is used for deleting entries from the entry tables. 3442 * It is legitimate to attempt to delete a nonexisting entry (the device will 3443 * respond as a good flow). 3444 */ 3445 #define MLXSW_REG_IEDR_ID 0x3804 3446 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3447 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3448 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3449 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3450 MLXSW_REG_IEDR_REC_LEN * \ 3451 MLXSW_REG_IEDR_REC_MAX_COUNT) 3452 3453 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3454 3455 /* reg_iedr_num_rec 3456 * Number of records. 3457 * Access: OP 3458 */ 3459 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3460 3461 /* reg_iedr_rec_type 3462 * Resource type. 3463 * Access: OP 3464 */ 3465 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3466 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3467 3468 /* reg_iedr_rec_size 3469 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3470 * Access: OP 3471 */ 3472 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3473 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3474 3475 /* reg_iedr_rec_index_start 3476 * Resource index start. 3477 * Access: OP 3478 */ 3479 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3480 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3481 3482 static inline void mlxsw_reg_iedr_pack(char *payload) 3483 { 3484 MLXSW_REG_ZERO(iedr, payload); 3485 } 3486 3487 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3488 u8 rec_type, u16 rec_size, 3489 u32 rec_index_start) 3490 { 3491 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3492 3493 if (rec_index >= num_rec) 3494 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3495 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3496 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3497 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3498 } 3499 3500 /* QPTS - QoS Priority Trust State Register 3501 * ---------------------------------------- 3502 * This register controls the port policy to calculate the switch priority and 3503 * packet color based on incoming packet fields. 3504 */ 3505 #define MLXSW_REG_QPTS_ID 0x4002 3506 #define MLXSW_REG_QPTS_LEN 0x8 3507 3508 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3509 3510 /* reg_qpts_local_port 3511 * Local port number. 3512 * Access: Index 3513 * 3514 * Note: CPU port is supported. 3515 */ 3516 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3517 3518 enum mlxsw_reg_qpts_trust_state { 3519 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3520 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3521 }; 3522 3523 /* reg_qpts_trust_state 3524 * Trust state for a given port. 3525 * Access: RW 3526 */ 3527 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3528 3529 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3530 enum mlxsw_reg_qpts_trust_state ts) 3531 { 3532 MLXSW_REG_ZERO(qpts, payload); 3533 3534 mlxsw_reg_qpts_local_port_set(payload, local_port); 3535 mlxsw_reg_qpts_trust_state_set(payload, ts); 3536 } 3537 3538 /* QPCR - QoS Policer Configuration Register 3539 * ----------------------------------------- 3540 * The QPCR register is used to create policers - that limit 3541 * the rate of bytes or packets via some trap group. 3542 */ 3543 #define MLXSW_REG_QPCR_ID 0x4004 3544 #define MLXSW_REG_QPCR_LEN 0x28 3545 3546 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3547 3548 enum mlxsw_reg_qpcr_g { 3549 MLXSW_REG_QPCR_G_GLOBAL = 2, 3550 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3551 }; 3552 3553 /* reg_qpcr_g 3554 * The policer type. 3555 * Access: Index 3556 */ 3557 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3558 3559 /* reg_qpcr_pid 3560 * Policer ID. 3561 * Access: Index 3562 */ 3563 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3564 3565 /* reg_qpcr_clear_counter 3566 * Clear counters. 3567 * Access: OP 3568 */ 3569 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3570 3571 /* reg_qpcr_color_aware 3572 * Is the policer aware of colors. 3573 * Must be 0 (unaware) for cpu port. 3574 * Access: RW for unbounded policer. RO for bounded policer. 3575 */ 3576 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3577 3578 /* reg_qpcr_bytes 3579 * Is policer limit is for bytes per sec or packets per sec. 3580 * 0 - packets 3581 * 1 - bytes 3582 * Access: RW for unbounded policer. RO for bounded policer. 3583 */ 3584 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3585 3586 enum mlxsw_reg_qpcr_ir_units { 3587 MLXSW_REG_QPCR_IR_UNITS_M, 3588 MLXSW_REG_QPCR_IR_UNITS_K, 3589 }; 3590 3591 /* reg_qpcr_ir_units 3592 * Policer's units for cir and eir fields (for bytes limits only) 3593 * 1 - 10^3 3594 * 0 - 10^6 3595 * Access: OP 3596 */ 3597 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3598 3599 enum mlxsw_reg_qpcr_rate_type { 3600 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3601 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3602 }; 3603 3604 /* reg_qpcr_rate_type 3605 * Policer can have one limit (single rate) or 2 limits with specific operation 3606 * for packets that exceed the lower rate but not the upper one. 3607 * (For cpu port must be single rate) 3608 * Access: RW for unbounded policer. RO for bounded policer. 3609 */ 3610 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3611 3612 /* reg_qpc_cbs 3613 * Policer's committed burst size. 3614 * The policer is working with time slices of 50 nano sec. By default every 3615 * slice is granted the proportionate share of the committed rate. If we want to 3616 * allow a slice to exceed that share (while still keeping the rate per sec) we 3617 * can allow burst. The burst size is between the default proportionate share 3618 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3619 * committed rate will result in exceeding the rate). The burst size must be a 3620 * log of 2 and will be determined by 2^cbs. 3621 * Access: RW 3622 */ 3623 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3624 3625 /* reg_qpcr_cir 3626 * Policer's committed rate. 3627 * The rate used for sungle rate, the lower rate for double rate. 3628 * For bytes limits, the rate will be this value * the unit from ir_units. 3629 * (Resolution error is up to 1%). 3630 * Access: RW 3631 */ 3632 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3633 3634 /* reg_qpcr_eir 3635 * Policer's exceed rate. 3636 * The higher rate for double rate, reserved for single rate. 3637 * Lower rate for double rate policer. 3638 * For bytes limits, the rate will be this value * the unit from ir_units. 3639 * (Resolution error is up to 1%). 3640 * Access: RW 3641 */ 3642 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3643 3644 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3645 3646 /* reg_qpcr_exceed_action. 3647 * What to do with packets between the 2 limits for double rate. 3648 * Access: RW for unbounded policer. RO for bounded policer. 3649 */ 3650 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3651 3652 enum mlxsw_reg_qpcr_action { 3653 /* Discard */ 3654 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3655 /* Forward and set color to red. 3656 * If the packet is intended to cpu port, it will be dropped. 3657 */ 3658 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3659 }; 3660 3661 /* reg_qpcr_violate_action 3662 * What to do with packets that cross the cir limit (for single rate) or the eir 3663 * limit (for double rate). 3664 * Access: RW for unbounded policer. RO for bounded policer. 3665 */ 3666 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3667 3668 /* reg_qpcr_violate_count 3669 * Counts the number of times violate_action happened on this PID. 3670 * Access: RW 3671 */ 3672 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3673 3674 /* Packets */ 3675 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3676 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3677 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3678 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3679 3680 /* Bandwidth */ 3681 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3682 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3683 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3684 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3685 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3686 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3687 3688 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3689 enum mlxsw_reg_qpcr_ir_units ir_units, 3690 bool bytes, u32 cir, u16 cbs) 3691 { 3692 MLXSW_REG_ZERO(qpcr, payload); 3693 mlxsw_reg_qpcr_pid_set(payload, pid); 3694 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3695 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3696 mlxsw_reg_qpcr_violate_action_set(payload, 3697 MLXSW_REG_QPCR_ACTION_DISCARD); 3698 mlxsw_reg_qpcr_cir_set(payload, cir); 3699 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3700 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3701 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3702 } 3703 3704 /* QTCT - QoS Switch Traffic Class Table 3705 * ------------------------------------- 3706 * Configures the mapping between the packet switch priority and the 3707 * traffic class on the transmit port. 3708 */ 3709 #define MLXSW_REG_QTCT_ID 0x400A 3710 #define MLXSW_REG_QTCT_LEN 0x08 3711 3712 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3713 3714 /* reg_qtct_local_port 3715 * Local port number. 3716 * Access: Index 3717 * 3718 * Note: CPU port is not supported. 3719 */ 3720 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3721 3722 /* reg_qtct_sub_port 3723 * Virtual port within the physical port. 3724 * Should be set to 0 when virtual ports are not enabled on the port. 3725 * Access: Index 3726 */ 3727 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3728 3729 /* reg_qtct_switch_prio 3730 * Switch priority. 3731 * Access: Index 3732 */ 3733 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3734 3735 /* reg_qtct_tclass 3736 * Traffic class. 3737 * Default values: 3738 * switch_prio 0 : tclass 1 3739 * switch_prio 1 : tclass 0 3740 * switch_prio i : tclass i, for i > 1 3741 * Access: RW 3742 */ 3743 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3744 3745 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3746 u8 switch_prio, u8 tclass) 3747 { 3748 MLXSW_REG_ZERO(qtct, payload); 3749 mlxsw_reg_qtct_local_port_set(payload, local_port); 3750 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3751 mlxsw_reg_qtct_tclass_set(payload, tclass); 3752 } 3753 3754 /* QEEC - QoS ETS Element Configuration Register 3755 * --------------------------------------------- 3756 * Configures the ETS elements. 3757 */ 3758 #define MLXSW_REG_QEEC_ID 0x400D 3759 #define MLXSW_REG_QEEC_LEN 0x20 3760 3761 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3762 3763 /* reg_qeec_local_port 3764 * Local port number. 3765 * Access: Index 3766 * 3767 * Note: CPU port is supported. 3768 */ 3769 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3770 3771 enum mlxsw_reg_qeec_hr { 3772 MLXSW_REG_QEEC_HR_PORT, 3773 MLXSW_REG_QEEC_HR_GROUP, 3774 MLXSW_REG_QEEC_HR_SUBGROUP, 3775 MLXSW_REG_QEEC_HR_TC, 3776 }; 3777 3778 /* reg_qeec_element_hierarchy 3779 * 0 - Port 3780 * 1 - Group 3781 * 2 - Subgroup 3782 * 3 - Traffic Class 3783 * Access: Index 3784 */ 3785 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3786 3787 /* reg_qeec_element_index 3788 * The index of the element in the hierarchy. 3789 * Access: Index 3790 */ 3791 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3792 3793 /* reg_qeec_next_element_index 3794 * The index of the next (lower) element in the hierarchy. 3795 * Access: RW 3796 * 3797 * Note: Reserved for element_hierarchy 0. 3798 */ 3799 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3800 3801 /* reg_qeec_mise 3802 * Min shaper configuration enable. Enables configuration of the min 3803 * shaper on this ETS element 3804 * 0 - Disable 3805 * 1 - Enable 3806 * Access: RW 3807 */ 3808 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3809 3810 /* reg_qeec_ptps 3811 * PTP shaper 3812 * 0: regular shaper mode 3813 * 1: PTP oriented shaper 3814 * Allowed only for hierarchy 0 3815 * Not supported for CPU port 3816 * Note that ptps mode may affect the shaper rates of all hierarchies 3817 * Supported only on Spectrum-1 3818 * Access: RW 3819 */ 3820 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3821 3822 enum { 3823 MLXSW_REG_QEEC_BYTES_MODE, 3824 MLXSW_REG_QEEC_PACKETS_MODE, 3825 }; 3826 3827 /* reg_qeec_pb 3828 * Packets or bytes mode. 3829 * 0 - Bytes mode 3830 * 1 - Packets mode 3831 * Access: RW 3832 * 3833 * Note: Used for max shaper configuration. For Spectrum, packets mode 3834 * is supported only for traffic classes of CPU port. 3835 */ 3836 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3837 3838 /* The smallest permitted min shaper rate. */ 3839 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3840 3841 /* reg_qeec_min_shaper_rate 3842 * Min shaper information rate. 3843 * For CPU port, can only be configured for port hierarchy. 3844 * When in bytes mode, value is specified in units of 1000bps. 3845 * Access: RW 3846 */ 3847 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3848 3849 /* reg_qeec_mase 3850 * Max shaper configuration enable. Enables configuration of the max 3851 * shaper on this ETS element. 3852 * 0 - Disable 3853 * 1 - Enable 3854 * Access: RW 3855 */ 3856 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3857 3858 /* The largest max shaper value possible to disable the shaper. */ 3859 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3860 3861 /* reg_qeec_max_shaper_rate 3862 * Max shaper information rate. 3863 * For CPU port, can only be configured for port hierarchy. 3864 * When in bytes mode, value is specified in units of 1000bps. 3865 * Access: RW 3866 */ 3867 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3868 3869 /* reg_qeec_de 3870 * DWRR configuration enable. Enables configuration of the dwrr and 3871 * dwrr_weight. 3872 * 0 - Disable 3873 * 1 - Enable 3874 * Access: RW 3875 */ 3876 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3877 3878 /* reg_qeec_dwrr 3879 * Transmission selection algorithm to use on the link going down from 3880 * the ETS element. 3881 * 0 - Strict priority 3882 * 1 - DWRR 3883 * Access: RW 3884 */ 3885 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3886 3887 /* reg_qeec_dwrr_weight 3888 * DWRR weight on the link going down from the ETS element. The 3889 * percentage of bandwidth guaranteed to an ETS element within 3890 * its hierarchy. The sum of all weights across all ETS elements 3891 * within one hierarchy should be equal to 100. Reserved when 3892 * transmission selection algorithm is strict priority. 3893 * Access: RW 3894 */ 3895 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3896 3897 /* reg_qeec_max_shaper_bs 3898 * Max shaper burst size 3899 * Burst size is 2^max_shaper_bs * 512 bits 3900 * For Spectrum-1: Range is: 5..25 3901 * For Spectrum-2: Range is: 11..25 3902 * Reserved when ptps = 1 3903 * Access: RW 3904 */ 3905 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3906 3907 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3908 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3909 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3910 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 3911 3912 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3913 enum mlxsw_reg_qeec_hr hr, u8 index, 3914 u8 next_index) 3915 { 3916 MLXSW_REG_ZERO(qeec, payload); 3917 mlxsw_reg_qeec_local_port_set(payload, local_port); 3918 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3919 mlxsw_reg_qeec_element_index_set(payload, index); 3920 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3921 } 3922 3923 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3924 bool ptps) 3925 { 3926 MLXSW_REG_ZERO(qeec, payload); 3927 mlxsw_reg_qeec_local_port_set(payload, local_port); 3928 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3929 mlxsw_reg_qeec_ptps_set(payload, ptps); 3930 } 3931 3932 /* QRWE - QoS ReWrite Enable 3933 * ------------------------- 3934 * This register configures the rewrite enable per receive port. 3935 */ 3936 #define MLXSW_REG_QRWE_ID 0x400F 3937 #define MLXSW_REG_QRWE_LEN 0x08 3938 3939 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3940 3941 /* reg_qrwe_local_port 3942 * Local port number. 3943 * Access: Index 3944 * 3945 * Note: CPU port is supported. No support for router port. 3946 */ 3947 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3948 3949 /* reg_qrwe_dscp 3950 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3951 * Access: RW 3952 */ 3953 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3954 3955 /* reg_qrwe_pcp 3956 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3957 * Access: RW 3958 */ 3959 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3960 3961 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3962 bool rewrite_pcp, bool rewrite_dscp) 3963 { 3964 MLXSW_REG_ZERO(qrwe, payload); 3965 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3966 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3967 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3968 } 3969 3970 /* QPDSM - QoS Priority to DSCP Mapping 3971 * ------------------------------------ 3972 * QoS Priority to DSCP Mapping Register 3973 */ 3974 #define MLXSW_REG_QPDSM_ID 0x4011 3975 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3976 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3977 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3978 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3979 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3980 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3981 3982 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3983 3984 /* reg_qpdsm_local_port 3985 * Local Port. Supported for data packets from CPU port. 3986 * Access: Index 3987 */ 3988 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3989 3990 /* reg_qpdsm_prio_entry_color0_e 3991 * Enable update of the entry for color 0 and a given port. 3992 * Access: WO 3993 */ 3994 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3995 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3996 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3997 3998 /* reg_qpdsm_prio_entry_color0_dscp 3999 * DSCP field in the outer label of the packet for color 0 and a given port. 4000 * Reserved when e=0. 4001 * Access: RW 4002 */ 4003 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4004 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4005 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4006 4007 /* reg_qpdsm_prio_entry_color1_e 4008 * Enable update of the entry for color 1 and a given port. 4009 * Access: WO 4010 */ 4011 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4012 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4013 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4014 4015 /* reg_qpdsm_prio_entry_color1_dscp 4016 * DSCP field in the outer label of the packet for color 1 and a given port. 4017 * Reserved when e=0. 4018 * Access: RW 4019 */ 4020 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4021 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4022 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4023 4024 /* reg_qpdsm_prio_entry_color2_e 4025 * Enable update of the entry for color 2 and a given port. 4026 * Access: WO 4027 */ 4028 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4029 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4030 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4031 4032 /* reg_qpdsm_prio_entry_color2_dscp 4033 * DSCP field in the outer label of the packet for color 2 and a given port. 4034 * Reserved when e=0. 4035 * Access: RW 4036 */ 4037 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4038 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4039 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4040 4041 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 4042 { 4043 MLXSW_REG_ZERO(qpdsm, payload); 4044 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4045 } 4046 4047 static inline void 4048 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4049 { 4050 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4051 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4052 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4053 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4054 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4055 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4056 } 4057 4058 /* QPDP - QoS Port DSCP to Priority Mapping Register 4059 * ------------------------------------------------- 4060 * This register controls the port default Switch Priority and Color. The 4061 * default Switch Priority and Color are used for frames where the trust state 4062 * uses default values. All member ports of a LAG should be configured with the 4063 * same default values. 4064 */ 4065 #define MLXSW_REG_QPDP_ID 0x4007 4066 #define MLXSW_REG_QPDP_LEN 0x8 4067 4068 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4069 4070 /* reg_qpdp_local_port 4071 * Local Port. Supported for data packets from CPU port. 4072 * Access: Index 4073 */ 4074 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 4075 4076 /* reg_qpdp_switch_prio 4077 * Default port Switch Priority (default 0) 4078 * Access: RW 4079 */ 4080 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4081 4082 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 4083 u8 switch_prio) 4084 { 4085 MLXSW_REG_ZERO(qpdp, payload); 4086 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4087 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4088 } 4089 4090 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4091 * -------------------------------------------------- 4092 * This register controls the mapping from DSCP field to 4093 * Switch Priority for IP packets. 4094 */ 4095 #define MLXSW_REG_QPDPM_ID 0x4013 4096 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4097 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4098 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4099 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4100 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4101 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4102 4103 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4104 4105 /* reg_qpdpm_local_port 4106 * Local Port. Supported for data packets from CPU port. 4107 * Access: Index 4108 */ 4109 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 4110 4111 /* reg_qpdpm_dscp_e 4112 * Enable update of the specific entry. When cleared, the switch_prio and color 4113 * fields are ignored and the previous switch_prio and color values are 4114 * preserved. 4115 * Access: WO 4116 */ 4117 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4118 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4119 4120 /* reg_qpdpm_dscp_prio 4121 * The new Switch Priority value for the relevant DSCP value. 4122 * Access: RW 4123 */ 4124 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4125 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4126 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4127 4128 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 4129 { 4130 MLXSW_REG_ZERO(qpdpm, payload); 4131 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4132 } 4133 4134 static inline void 4135 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4136 { 4137 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4138 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4139 } 4140 4141 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4142 * ------------------------------------------------------------------ 4143 * This register configures if the Switch Priority to Traffic Class mapping is 4144 * based on Multicast packet indication. If so, then multicast packets will get 4145 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4146 * QTCT. 4147 * By default, Switch Priority to Traffic Class mapping is not based on 4148 * Multicast packet indication. 4149 */ 4150 #define MLXSW_REG_QTCTM_ID 0x401A 4151 #define MLXSW_REG_QTCTM_LEN 0x08 4152 4153 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4154 4155 /* reg_qtctm_local_port 4156 * Local port number. 4157 * No support for CPU port. 4158 * Access: Index 4159 */ 4160 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 4161 4162 /* reg_qtctm_mc 4163 * Multicast Mode 4164 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4165 * indication (default is 0, not based on Multicast packet indication). 4166 */ 4167 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4168 4169 static inline void 4170 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 4171 { 4172 MLXSW_REG_ZERO(qtctm, payload); 4173 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4174 mlxsw_reg_qtctm_mc_set(payload, mc); 4175 } 4176 4177 /* QPSC - QoS PTP Shaper Configuration Register 4178 * -------------------------------------------- 4179 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4180 * Supported only on Spectrum-1. 4181 */ 4182 #define MLXSW_REG_QPSC_ID 0x401B 4183 #define MLXSW_REG_QPSC_LEN 0x28 4184 4185 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4186 4187 enum mlxsw_reg_qpsc_port_speed { 4188 MLXSW_REG_QPSC_PORT_SPEED_100M, 4189 MLXSW_REG_QPSC_PORT_SPEED_1G, 4190 MLXSW_REG_QPSC_PORT_SPEED_10G, 4191 MLXSW_REG_QPSC_PORT_SPEED_25G, 4192 }; 4193 4194 /* reg_qpsc_port_speed 4195 * Port speed. 4196 * Access: Index 4197 */ 4198 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4199 4200 /* reg_qpsc_shaper_time_exp 4201 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4202 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4203 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4204 * Access: RW 4205 */ 4206 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4207 4208 /* reg_qpsc_shaper_time_mantissa 4209 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4210 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4211 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4212 * Access: RW 4213 */ 4214 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4215 4216 /* reg_qpsc_shaper_inc 4217 * Number of tokens added to shaper on each update. 4218 * Units of 8B. 4219 * Access: RW 4220 */ 4221 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4222 4223 /* reg_qpsc_shaper_bs 4224 * Max shaper Burst size. 4225 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4226 * Range is: 5..25 (from 2KB..2GB) 4227 * Access: RW 4228 */ 4229 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4230 4231 /* reg_qpsc_ptsc_we 4232 * Write enable to port_to_shaper_credits. 4233 * Access: WO 4234 */ 4235 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4236 4237 /* reg_qpsc_port_to_shaper_credits 4238 * For split ports: range 1..57 4239 * For non-split ports: range 1..112 4240 * Written only when ptsc_we is set. 4241 * Access: RW 4242 */ 4243 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4244 4245 /* reg_qpsc_ing_timestamp_inc 4246 * Ingress timestamp increment. 4247 * 2's complement. 4248 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4249 * value for all ports. 4250 * Same units as used by MTPPTR. 4251 * Access: RW 4252 */ 4253 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4254 4255 /* reg_qpsc_egr_timestamp_inc 4256 * Egress timestamp increment. 4257 * 2's complement. 4258 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4259 * value for all ports. 4260 * Same units as used by MTPPTR. 4261 * Access: RW 4262 */ 4263 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4264 4265 static inline void 4266 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4267 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4268 u8 shaper_bs, u8 port_to_shaper_credits, 4269 int ing_timestamp_inc, int egr_timestamp_inc) 4270 { 4271 MLXSW_REG_ZERO(qpsc, payload); 4272 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4273 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4274 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4275 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4276 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4277 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4278 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4279 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4280 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4281 } 4282 4283 /* PMLP - Ports Module to Local Port Register 4284 * ------------------------------------------ 4285 * Configures the assignment of modules to local ports. 4286 */ 4287 #define MLXSW_REG_PMLP_ID 0x5002 4288 #define MLXSW_REG_PMLP_LEN 0x40 4289 4290 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4291 4292 /* reg_pmlp_rxtx 4293 * 0 - Tx value is used for both Tx and Rx. 4294 * 1 - Rx value is taken from a separte field. 4295 * Access: RW 4296 */ 4297 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4298 4299 /* reg_pmlp_local_port 4300 * Local port number. 4301 * Access: Index 4302 */ 4303 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4304 4305 /* reg_pmlp_width 4306 * 0 - Unmap local port. 4307 * 1 - Lane 0 is used. 4308 * 2 - Lanes 0 and 1 are used. 4309 * 4 - Lanes 0, 1, 2 and 3 are used. 4310 * 8 - Lanes 0-7 are used. 4311 * Access: RW 4312 */ 4313 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4314 4315 /* reg_pmlp_module 4316 * Module number. 4317 * Access: RW 4318 */ 4319 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4320 4321 /* reg_pmlp_tx_lane 4322 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4323 * Access: RW 4324 */ 4325 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4326 4327 /* reg_pmlp_rx_lane 4328 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4329 * equal to Tx lane. 4330 * Access: RW 4331 */ 4332 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4333 4334 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4335 { 4336 MLXSW_REG_ZERO(pmlp, payload); 4337 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4338 } 4339 4340 /* PMTU - Port MTU Register 4341 * ------------------------ 4342 * Configures and reports the port MTU. 4343 */ 4344 #define MLXSW_REG_PMTU_ID 0x5003 4345 #define MLXSW_REG_PMTU_LEN 0x10 4346 4347 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4348 4349 /* reg_pmtu_local_port 4350 * Local port number. 4351 * Access: Index 4352 */ 4353 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4354 4355 /* reg_pmtu_max_mtu 4356 * Maximum MTU. 4357 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4358 * reported, otherwise the minimum between the max_mtu of the different 4359 * types is reported. 4360 * Access: RO 4361 */ 4362 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4363 4364 /* reg_pmtu_admin_mtu 4365 * MTU value to set port to. Must be smaller or equal to max_mtu. 4366 * Note: If port type is Infiniband, then port must be disabled, when its 4367 * MTU is set. 4368 * Access: RW 4369 */ 4370 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4371 4372 /* reg_pmtu_oper_mtu 4373 * The actual MTU configured on the port. Packets exceeding this size 4374 * will be dropped. 4375 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4376 * oper_mtu might be smaller than admin_mtu. 4377 * Access: RO 4378 */ 4379 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4380 4381 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4382 u16 new_mtu) 4383 { 4384 MLXSW_REG_ZERO(pmtu, payload); 4385 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4386 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4387 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4388 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4389 } 4390 4391 /* PTYS - Port Type and Speed Register 4392 * ----------------------------------- 4393 * Configures and reports the port speed type. 4394 * 4395 * Note: When set while the link is up, the changes will not take effect 4396 * until the port transitions from down to up state. 4397 */ 4398 #define MLXSW_REG_PTYS_ID 0x5004 4399 #define MLXSW_REG_PTYS_LEN 0x40 4400 4401 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4402 4403 /* an_disable_admin 4404 * Auto negotiation disable administrative configuration 4405 * 0 - Device doesn't support AN disable. 4406 * 1 - Device supports AN disable. 4407 * Access: RW 4408 */ 4409 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4410 4411 /* reg_ptys_local_port 4412 * Local port number. 4413 * Access: Index 4414 */ 4415 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4416 4417 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4418 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4419 4420 /* reg_ptys_proto_mask 4421 * Protocol mask. Indicates which protocol is used. 4422 * 0 - Infiniband. 4423 * 1 - Fibre Channel. 4424 * 2 - Ethernet. 4425 * Access: Index 4426 */ 4427 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4428 4429 enum { 4430 MLXSW_REG_PTYS_AN_STATUS_NA, 4431 MLXSW_REG_PTYS_AN_STATUS_OK, 4432 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4433 }; 4434 4435 /* reg_ptys_an_status 4436 * Autonegotiation status. 4437 * Access: RO 4438 */ 4439 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4440 4441 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4442 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4443 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4444 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4445 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4446 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4447 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4448 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4449 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4450 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4451 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4452 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4453 4454 /* reg_ptys_ext_eth_proto_cap 4455 * Extended Ethernet port supported speeds and protocols. 4456 * Access: RO 4457 */ 4458 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4459 4460 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4461 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4462 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4463 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4464 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4465 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4466 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4467 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4468 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4469 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4470 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4471 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4472 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4473 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4474 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4475 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4476 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4477 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4478 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4479 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4480 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4481 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4482 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4483 4484 /* reg_ptys_eth_proto_cap 4485 * Ethernet port supported speeds and protocols. 4486 * Access: RO 4487 */ 4488 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4489 4490 /* reg_ptys_ib_link_width_cap 4491 * IB port supported widths. 4492 * Access: RO 4493 */ 4494 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4495 4496 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4497 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4498 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4499 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4500 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4501 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4502 4503 /* reg_ptys_ib_proto_cap 4504 * IB port supported speeds and protocols. 4505 * Access: RO 4506 */ 4507 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4508 4509 /* reg_ptys_ext_eth_proto_admin 4510 * Extended speed and protocol to set port to. 4511 * Access: RW 4512 */ 4513 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4514 4515 /* reg_ptys_eth_proto_admin 4516 * Speed and protocol to set port to. 4517 * Access: RW 4518 */ 4519 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4520 4521 /* reg_ptys_ib_link_width_admin 4522 * IB width to set port to. 4523 * Access: RW 4524 */ 4525 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4526 4527 /* reg_ptys_ib_proto_admin 4528 * IB speeds and protocols to set port to. 4529 * Access: RW 4530 */ 4531 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4532 4533 /* reg_ptys_ext_eth_proto_oper 4534 * The extended current speed and protocol configured for the port. 4535 * Access: RO 4536 */ 4537 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4538 4539 /* reg_ptys_eth_proto_oper 4540 * The current speed and protocol configured for the port. 4541 * Access: RO 4542 */ 4543 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4544 4545 /* reg_ptys_ib_link_width_oper 4546 * The current IB width to set port to. 4547 * Access: RO 4548 */ 4549 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4550 4551 /* reg_ptys_ib_proto_oper 4552 * The current IB speed and protocol. 4553 * Access: RO 4554 */ 4555 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4556 4557 enum mlxsw_reg_ptys_connector_type { 4558 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4559 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4560 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4561 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4562 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4563 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4564 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4565 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4566 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4567 }; 4568 4569 /* reg_ptys_connector_type 4570 * Connector type indication. 4571 * Access: RO 4572 */ 4573 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4574 4575 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4576 u32 proto_admin, bool autoneg) 4577 { 4578 MLXSW_REG_ZERO(ptys, payload); 4579 mlxsw_reg_ptys_local_port_set(payload, local_port); 4580 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4581 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4582 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4583 } 4584 4585 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4586 u32 proto_admin, bool autoneg) 4587 { 4588 MLXSW_REG_ZERO(ptys, payload); 4589 mlxsw_reg_ptys_local_port_set(payload, local_port); 4590 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4591 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4592 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4593 } 4594 4595 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4596 u32 *p_eth_proto_cap, 4597 u32 *p_eth_proto_admin, 4598 u32 *p_eth_proto_oper) 4599 { 4600 if (p_eth_proto_cap) 4601 *p_eth_proto_cap = 4602 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4603 if (p_eth_proto_admin) 4604 *p_eth_proto_admin = 4605 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4606 if (p_eth_proto_oper) 4607 *p_eth_proto_oper = 4608 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4609 } 4610 4611 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4612 u32 *p_eth_proto_cap, 4613 u32 *p_eth_proto_admin, 4614 u32 *p_eth_proto_oper) 4615 { 4616 if (p_eth_proto_cap) 4617 *p_eth_proto_cap = 4618 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4619 if (p_eth_proto_admin) 4620 *p_eth_proto_admin = 4621 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4622 if (p_eth_proto_oper) 4623 *p_eth_proto_oper = 4624 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4625 } 4626 4627 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4628 u16 proto_admin, u16 link_width) 4629 { 4630 MLXSW_REG_ZERO(ptys, payload); 4631 mlxsw_reg_ptys_local_port_set(payload, local_port); 4632 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4633 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4634 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4635 } 4636 4637 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4638 u16 *p_ib_link_width_cap, 4639 u16 *p_ib_proto_oper, 4640 u16 *p_ib_link_width_oper) 4641 { 4642 if (p_ib_proto_cap) 4643 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4644 if (p_ib_link_width_cap) 4645 *p_ib_link_width_cap = 4646 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4647 if (p_ib_proto_oper) 4648 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4649 if (p_ib_link_width_oper) 4650 *p_ib_link_width_oper = 4651 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4652 } 4653 4654 /* PPAD - Port Physical Address Register 4655 * ------------------------------------- 4656 * The PPAD register configures the per port physical MAC address. 4657 */ 4658 #define MLXSW_REG_PPAD_ID 0x5005 4659 #define MLXSW_REG_PPAD_LEN 0x10 4660 4661 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4662 4663 /* reg_ppad_single_base_mac 4664 * 0: base_mac, local port should be 0 and mac[7:0] is 4665 * reserved. HW will set incremental 4666 * 1: single_mac - mac of the local_port 4667 * Access: RW 4668 */ 4669 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4670 4671 /* reg_ppad_local_port 4672 * port number, if single_base_mac = 0 then local_port is reserved 4673 * Access: RW 4674 */ 4675 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4676 4677 /* reg_ppad_mac 4678 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4679 * If single_base_mac = 1 - the per port MAC address 4680 * Access: RW 4681 */ 4682 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4683 4684 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4685 u8 local_port) 4686 { 4687 MLXSW_REG_ZERO(ppad, payload); 4688 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4689 mlxsw_reg_ppad_local_port_set(payload, local_port); 4690 } 4691 4692 /* PAOS - Ports Administrative and Operational Status Register 4693 * ----------------------------------------------------------- 4694 * Configures and retrieves per port administrative and operational status. 4695 */ 4696 #define MLXSW_REG_PAOS_ID 0x5006 4697 #define MLXSW_REG_PAOS_LEN 0x10 4698 4699 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4700 4701 /* reg_paos_swid 4702 * Switch partition ID with which to associate the port. 4703 * Note: while external ports uses unique local port numbers (and thus swid is 4704 * redundant), router ports use the same local port number where swid is the 4705 * only indication for the relevant port. 4706 * Access: Index 4707 */ 4708 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4709 4710 /* reg_paos_local_port 4711 * Local port number. 4712 * Access: Index 4713 */ 4714 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4715 4716 /* reg_paos_admin_status 4717 * Port administrative state (the desired state of the port): 4718 * 1 - Up. 4719 * 2 - Down. 4720 * 3 - Up once. This means that in case of link failure, the port won't go 4721 * into polling mode, but will wait to be re-enabled by software. 4722 * 4 - Disabled by system. Can only be set by hardware. 4723 * Access: RW 4724 */ 4725 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4726 4727 /* reg_paos_oper_status 4728 * Port operational state (the current state): 4729 * 1 - Up. 4730 * 2 - Down. 4731 * 3 - Down by port failure. This means that the device will not let the 4732 * port up again until explicitly specified by software. 4733 * Access: RO 4734 */ 4735 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4736 4737 /* reg_paos_ase 4738 * Admin state update enabled. 4739 * Access: WO 4740 */ 4741 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4742 4743 /* reg_paos_ee 4744 * Event update enable. If this bit is set, event generation will be 4745 * updated based on the e field. 4746 * Access: WO 4747 */ 4748 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4749 4750 /* reg_paos_e 4751 * Event generation on operational state change: 4752 * 0 - Do not generate event. 4753 * 1 - Generate Event. 4754 * 2 - Generate Single Event. 4755 * Access: RW 4756 */ 4757 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4758 4759 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4760 enum mlxsw_port_admin_status status) 4761 { 4762 MLXSW_REG_ZERO(paos, payload); 4763 mlxsw_reg_paos_swid_set(payload, 0); 4764 mlxsw_reg_paos_local_port_set(payload, local_port); 4765 mlxsw_reg_paos_admin_status_set(payload, status); 4766 mlxsw_reg_paos_oper_status_set(payload, 0); 4767 mlxsw_reg_paos_ase_set(payload, 1); 4768 mlxsw_reg_paos_ee_set(payload, 1); 4769 mlxsw_reg_paos_e_set(payload, 1); 4770 } 4771 4772 /* PFCC - Ports Flow Control Configuration Register 4773 * ------------------------------------------------ 4774 * Configures and retrieves the per port flow control configuration. 4775 */ 4776 #define MLXSW_REG_PFCC_ID 0x5007 4777 #define MLXSW_REG_PFCC_LEN 0x20 4778 4779 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4780 4781 /* reg_pfcc_local_port 4782 * Local port number. 4783 * Access: Index 4784 */ 4785 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4786 4787 /* reg_pfcc_pnat 4788 * Port number access type. Determines the way local_port is interpreted: 4789 * 0 - Local port number. 4790 * 1 - IB / label port number. 4791 * Access: Index 4792 */ 4793 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4794 4795 /* reg_pfcc_shl_cap 4796 * Send to higher layers capabilities: 4797 * 0 - No capability of sending Pause and PFC frames to higher layers. 4798 * 1 - Device has capability of sending Pause and PFC frames to higher 4799 * layers. 4800 * Access: RO 4801 */ 4802 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4803 4804 /* reg_pfcc_shl_opr 4805 * Send to higher layers operation: 4806 * 0 - Pause and PFC frames are handled by the port (default). 4807 * 1 - Pause and PFC frames are handled by the port and also sent to 4808 * higher layers. Only valid if shl_cap = 1. 4809 * Access: RW 4810 */ 4811 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4812 4813 /* reg_pfcc_ppan 4814 * Pause policy auto negotiation. 4815 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4816 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4817 * based on the auto-negotiation resolution. 4818 * Access: RW 4819 * 4820 * Note: The auto-negotiation advertisement is set according to pptx and 4821 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4822 */ 4823 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4824 4825 /* reg_pfcc_prio_mask_tx 4826 * Bit per priority indicating if Tx flow control policy should be 4827 * updated based on bit pfctx. 4828 * Access: WO 4829 */ 4830 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4831 4832 /* reg_pfcc_prio_mask_rx 4833 * Bit per priority indicating if Rx flow control policy should be 4834 * updated based on bit pfcrx. 4835 * Access: WO 4836 */ 4837 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4838 4839 /* reg_pfcc_pptx 4840 * Admin Pause policy on Tx. 4841 * 0 - Never generate Pause frames (default). 4842 * 1 - Generate Pause frames according to Rx buffer threshold. 4843 * Access: RW 4844 */ 4845 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4846 4847 /* reg_pfcc_aptx 4848 * Active (operational) Pause policy on Tx. 4849 * 0 - Never generate Pause frames. 4850 * 1 - Generate Pause frames according to Rx buffer threshold. 4851 * Access: RO 4852 */ 4853 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4854 4855 /* reg_pfcc_pfctx 4856 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4857 * 0 - Never generate priority Pause frames on the specified priority 4858 * (default). 4859 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4860 * the specified priority. 4861 * Access: RW 4862 * 4863 * Note: pfctx and pptx must be mutually exclusive. 4864 */ 4865 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4866 4867 /* reg_pfcc_pprx 4868 * Admin Pause policy on Rx. 4869 * 0 - Ignore received Pause frames (default). 4870 * 1 - Respect received Pause frames. 4871 * Access: RW 4872 */ 4873 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4874 4875 /* reg_pfcc_aprx 4876 * Active (operational) Pause policy on Rx. 4877 * 0 - Ignore received Pause frames. 4878 * 1 - Respect received Pause frames. 4879 * Access: RO 4880 */ 4881 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4882 4883 /* reg_pfcc_pfcrx 4884 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4885 * 0 - Ignore incoming priority Pause frames on the specified priority 4886 * (default). 4887 * 1 - Respect incoming priority Pause frames on the specified priority. 4888 * Access: RW 4889 */ 4890 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4891 4892 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4893 4894 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4895 { 4896 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4897 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4898 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4899 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4900 } 4901 4902 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4903 { 4904 MLXSW_REG_ZERO(pfcc, payload); 4905 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4906 } 4907 4908 /* PPCNT - Ports Performance Counters Register 4909 * ------------------------------------------- 4910 * The PPCNT register retrieves per port performance counters. 4911 */ 4912 #define MLXSW_REG_PPCNT_ID 0x5008 4913 #define MLXSW_REG_PPCNT_LEN 0x100 4914 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4915 4916 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4917 4918 /* reg_ppcnt_swid 4919 * For HCA: must be always 0. 4920 * Switch partition ID to associate port with. 4921 * Switch partitions are numbered from 0 to 7 inclusively. 4922 * Switch partition 254 indicates stacking ports. 4923 * Switch partition 255 indicates all switch partitions. 4924 * Only valid on Set() operation with local_port=255. 4925 * Access: Index 4926 */ 4927 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4928 4929 /* reg_ppcnt_local_port 4930 * Local port number. 4931 * 255 indicates all ports on the device, and is only allowed 4932 * for Set() operation. 4933 * Access: Index 4934 */ 4935 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4936 4937 /* reg_ppcnt_pnat 4938 * Port number access type: 4939 * 0 - Local port number 4940 * 1 - IB port number 4941 * Access: Index 4942 */ 4943 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4944 4945 enum mlxsw_reg_ppcnt_grp { 4946 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4947 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4948 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4949 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4950 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4951 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4952 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4953 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4954 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4955 }; 4956 4957 /* reg_ppcnt_grp 4958 * Performance counter group. 4959 * Group 63 indicates all groups. Only valid on Set() operation with 4960 * clr bit set. 4961 * 0x0: IEEE 802.3 Counters 4962 * 0x1: RFC 2863 Counters 4963 * 0x2: RFC 2819 Counters 4964 * 0x3: RFC 3635 Counters 4965 * 0x5: Ethernet Extended Counters 4966 * 0x6: Ethernet Discard Counters 4967 * 0x8: Link Level Retransmission Counters 4968 * 0x10: Per Priority Counters 4969 * 0x11: Per Traffic Class Counters 4970 * 0x12: Physical Layer Counters 4971 * 0x13: Per Traffic Class Congestion Counters 4972 * Access: Index 4973 */ 4974 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4975 4976 /* reg_ppcnt_clr 4977 * Clear counters. Setting the clr bit will reset the counter value 4978 * for all counters in the counter group. This bit can be set 4979 * for both Set() and Get() operation. 4980 * Access: OP 4981 */ 4982 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4983 4984 /* reg_ppcnt_prio_tc 4985 * Priority for counter set that support per priority, valid values: 0-7. 4986 * Traffic class for counter set that support per traffic class, 4987 * valid values: 0- cap_max_tclass-1 . 4988 * For HCA: cap_max_tclass is always 8. 4989 * Otherwise must be 0. 4990 * Access: Index 4991 */ 4992 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4993 4994 /* Ethernet IEEE 802.3 Counter Group */ 4995 4996 /* reg_ppcnt_a_frames_transmitted_ok 4997 * Access: RO 4998 */ 4999 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5000 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5001 5002 /* reg_ppcnt_a_frames_received_ok 5003 * Access: RO 5004 */ 5005 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5006 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5007 5008 /* reg_ppcnt_a_frame_check_sequence_errors 5009 * Access: RO 5010 */ 5011 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5012 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5013 5014 /* reg_ppcnt_a_alignment_errors 5015 * Access: RO 5016 */ 5017 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5018 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5019 5020 /* reg_ppcnt_a_octets_transmitted_ok 5021 * Access: RO 5022 */ 5023 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5024 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5025 5026 /* reg_ppcnt_a_octets_received_ok 5027 * Access: RO 5028 */ 5029 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5030 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5031 5032 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5033 * Access: RO 5034 */ 5035 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5036 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5037 5038 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5039 * Access: RO 5040 */ 5041 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5042 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5043 5044 /* reg_ppcnt_a_multicast_frames_received_ok 5045 * Access: RO 5046 */ 5047 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5048 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5049 5050 /* reg_ppcnt_a_broadcast_frames_received_ok 5051 * Access: RO 5052 */ 5053 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5054 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5055 5056 /* reg_ppcnt_a_in_range_length_errors 5057 * Access: RO 5058 */ 5059 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5060 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5061 5062 /* reg_ppcnt_a_out_of_range_length_field 5063 * Access: RO 5064 */ 5065 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5066 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5067 5068 /* reg_ppcnt_a_frame_too_long_errors 5069 * Access: RO 5070 */ 5071 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5072 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5073 5074 /* reg_ppcnt_a_symbol_error_during_carrier 5075 * Access: RO 5076 */ 5077 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5078 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5079 5080 /* reg_ppcnt_a_mac_control_frames_transmitted 5081 * Access: RO 5082 */ 5083 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5084 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5085 5086 /* reg_ppcnt_a_mac_control_frames_received 5087 * Access: RO 5088 */ 5089 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5090 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5091 5092 /* reg_ppcnt_a_unsupported_opcodes_received 5093 * Access: RO 5094 */ 5095 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5096 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5097 5098 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5099 * Access: RO 5100 */ 5101 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5102 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5103 5104 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5105 * Access: RO 5106 */ 5107 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5108 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5109 5110 /* Ethernet RFC 2863 Counter Group */ 5111 5112 /* reg_ppcnt_if_in_discards 5113 * Access: RO 5114 */ 5115 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5116 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5117 5118 /* reg_ppcnt_if_out_discards 5119 * Access: RO 5120 */ 5121 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5122 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5123 5124 /* reg_ppcnt_if_out_errors 5125 * Access: RO 5126 */ 5127 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5128 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5129 5130 /* Ethernet RFC 2819 Counter Group */ 5131 5132 /* reg_ppcnt_ether_stats_undersize_pkts 5133 * Access: RO 5134 */ 5135 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5136 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5137 5138 /* reg_ppcnt_ether_stats_oversize_pkts 5139 * Access: RO 5140 */ 5141 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5142 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5143 5144 /* reg_ppcnt_ether_stats_fragments 5145 * Access: RO 5146 */ 5147 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5148 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5149 5150 /* reg_ppcnt_ether_stats_pkts64octets 5151 * Access: RO 5152 */ 5153 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5154 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5155 5156 /* reg_ppcnt_ether_stats_pkts65to127octets 5157 * Access: RO 5158 */ 5159 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5160 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5161 5162 /* reg_ppcnt_ether_stats_pkts128to255octets 5163 * Access: RO 5164 */ 5165 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5166 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5167 5168 /* reg_ppcnt_ether_stats_pkts256to511octets 5169 * Access: RO 5170 */ 5171 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5172 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5173 5174 /* reg_ppcnt_ether_stats_pkts512to1023octets 5175 * Access: RO 5176 */ 5177 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5178 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5179 5180 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5181 * Access: RO 5182 */ 5183 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5184 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5185 5186 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5187 * Access: RO 5188 */ 5189 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5190 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5191 5192 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5193 * Access: RO 5194 */ 5195 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5196 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5197 5198 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5199 * Access: RO 5200 */ 5201 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5202 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5203 5204 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5205 * Access: RO 5206 */ 5207 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5208 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5209 5210 /* Ethernet RFC 3635 Counter Group */ 5211 5212 /* reg_ppcnt_dot3stats_fcs_errors 5213 * Access: RO 5214 */ 5215 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5216 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5217 5218 /* reg_ppcnt_dot3stats_symbol_errors 5219 * Access: RO 5220 */ 5221 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5222 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5223 5224 /* reg_ppcnt_dot3control_in_unknown_opcodes 5225 * Access: RO 5226 */ 5227 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5228 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5229 5230 /* reg_ppcnt_dot3in_pause_frames 5231 * Access: RO 5232 */ 5233 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5234 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5235 5236 /* Ethernet Extended Counter Group Counters */ 5237 5238 /* reg_ppcnt_ecn_marked 5239 * Access: RO 5240 */ 5241 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5242 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5243 5244 /* Ethernet Discard Counter Group Counters */ 5245 5246 /* reg_ppcnt_ingress_general 5247 * Access: RO 5248 */ 5249 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5250 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5251 5252 /* reg_ppcnt_ingress_policy_engine 5253 * Access: RO 5254 */ 5255 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5256 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5257 5258 /* reg_ppcnt_ingress_vlan_membership 5259 * Access: RO 5260 */ 5261 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5262 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5263 5264 /* reg_ppcnt_ingress_tag_frame_type 5265 * Access: RO 5266 */ 5267 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5268 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5269 5270 /* reg_ppcnt_egress_vlan_membership 5271 * Access: RO 5272 */ 5273 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5274 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5275 5276 /* reg_ppcnt_loopback_filter 5277 * Access: RO 5278 */ 5279 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5280 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5281 5282 /* reg_ppcnt_egress_general 5283 * Access: RO 5284 */ 5285 MLXSW_ITEM64(reg, ppcnt, egress_general, 5286 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5287 5288 /* reg_ppcnt_egress_hoq 5289 * Access: RO 5290 */ 5291 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5292 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5293 5294 /* reg_ppcnt_egress_policy_engine 5295 * Access: RO 5296 */ 5297 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5298 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5299 5300 /* reg_ppcnt_ingress_tx_link_down 5301 * Access: RO 5302 */ 5303 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5304 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5305 5306 /* reg_ppcnt_egress_stp_filter 5307 * Access: RO 5308 */ 5309 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5311 5312 /* reg_ppcnt_egress_sll 5313 * Access: RO 5314 */ 5315 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5317 5318 /* Ethernet Per Priority Group Counters */ 5319 5320 /* reg_ppcnt_rx_octets 5321 * Access: RO 5322 */ 5323 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5324 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5325 5326 /* reg_ppcnt_rx_frames 5327 * Access: RO 5328 */ 5329 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5330 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5331 5332 /* reg_ppcnt_tx_octets 5333 * Access: RO 5334 */ 5335 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5336 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5337 5338 /* reg_ppcnt_tx_frames 5339 * Access: RO 5340 */ 5341 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5342 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5343 5344 /* reg_ppcnt_rx_pause 5345 * Access: RO 5346 */ 5347 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5348 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5349 5350 /* reg_ppcnt_rx_pause_duration 5351 * Access: RO 5352 */ 5353 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5354 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5355 5356 /* reg_ppcnt_tx_pause 5357 * Access: RO 5358 */ 5359 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5360 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5361 5362 /* reg_ppcnt_tx_pause_duration 5363 * Access: RO 5364 */ 5365 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5366 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5367 5368 /* reg_ppcnt_rx_pause_transition 5369 * Access: RO 5370 */ 5371 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5372 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5373 5374 /* Ethernet Per Traffic Group Counters */ 5375 5376 /* reg_ppcnt_tc_transmit_queue 5377 * Contains the transmit queue depth in cells of traffic class 5378 * selected by prio_tc and the port selected by local_port. 5379 * The field cannot be cleared. 5380 * Access: RO 5381 */ 5382 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5383 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5384 5385 /* reg_ppcnt_tc_no_buffer_discard_uc 5386 * The number of unicast packets dropped due to lack of shared 5387 * buffer resources. 5388 * Access: RO 5389 */ 5390 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5391 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5392 5393 /* Ethernet Per Traffic Class Congestion Group Counters */ 5394 5395 /* reg_ppcnt_wred_discard 5396 * Access: RO 5397 */ 5398 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5399 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5400 5401 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5402 enum mlxsw_reg_ppcnt_grp grp, 5403 u8 prio_tc) 5404 { 5405 MLXSW_REG_ZERO(ppcnt, payload); 5406 mlxsw_reg_ppcnt_swid_set(payload, 0); 5407 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5408 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5409 mlxsw_reg_ppcnt_grp_set(payload, grp); 5410 mlxsw_reg_ppcnt_clr_set(payload, 0); 5411 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5412 } 5413 5414 /* PLIB - Port Local to InfiniBand Port 5415 * ------------------------------------ 5416 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5417 */ 5418 #define MLXSW_REG_PLIB_ID 0x500A 5419 #define MLXSW_REG_PLIB_LEN 0x10 5420 5421 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5422 5423 /* reg_plib_local_port 5424 * Local port number. 5425 * Access: Index 5426 */ 5427 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5428 5429 /* reg_plib_ib_port 5430 * InfiniBand port remapping for local_port. 5431 * Access: RW 5432 */ 5433 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5434 5435 /* PPTB - Port Prio To Buffer Register 5436 * ----------------------------------- 5437 * Configures the switch priority to buffer table. 5438 */ 5439 #define MLXSW_REG_PPTB_ID 0x500B 5440 #define MLXSW_REG_PPTB_LEN 0x10 5441 5442 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5443 5444 enum { 5445 MLXSW_REG_PPTB_MM_UM, 5446 MLXSW_REG_PPTB_MM_UNICAST, 5447 MLXSW_REG_PPTB_MM_MULTICAST, 5448 }; 5449 5450 /* reg_pptb_mm 5451 * Mapping mode. 5452 * 0 - Map both unicast and multicast packets to the same buffer. 5453 * 1 - Map only unicast packets. 5454 * 2 - Map only multicast packets. 5455 * Access: Index 5456 * 5457 * Note: SwitchX-2 only supports the first option. 5458 */ 5459 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5460 5461 /* reg_pptb_local_port 5462 * Local port number. 5463 * Access: Index 5464 */ 5465 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5466 5467 /* reg_pptb_um 5468 * Enables the update of the untagged_buf field. 5469 * Access: RW 5470 */ 5471 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5472 5473 /* reg_pptb_pm 5474 * Enables the update of the prio_to_buff field. 5475 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5476 * Access: RW 5477 */ 5478 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5479 5480 /* reg_pptb_prio_to_buff 5481 * Mapping of switch priority <i> to one of the allocated receive port 5482 * buffers. 5483 * Access: RW 5484 */ 5485 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5486 5487 /* reg_pptb_pm_msb 5488 * Enables the update of the prio_to_buff field. 5489 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5490 * Access: RW 5491 */ 5492 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5493 5494 /* reg_pptb_untagged_buff 5495 * Mapping of untagged frames to one of the allocated receive port buffers. 5496 * Access: RW 5497 * 5498 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5499 * Spectrum, as it maps untagged packets based on the default switch priority. 5500 */ 5501 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5502 5503 /* reg_pptb_prio_to_buff_msb 5504 * Mapping of switch priority <i+8> to one of the allocated receive port 5505 * buffers. 5506 * Access: RW 5507 */ 5508 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5509 5510 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5511 5512 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5513 { 5514 MLXSW_REG_ZERO(pptb, payload); 5515 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5516 mlxsw_reg_pptb_local_port_set(payload, local_port); 5517 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5518 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5519 } 5520 5521 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5522 u8 buff) 5523 { 5524 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5525 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5526 } 5527 5528 /* PBMC - Port Buffer Management Control Register 5529 * ---------------------------------------------- 5530 * The PBMC register configures and retrieves the port packet buffer 5531 * allocation for different Prios, and the Pause threshold management. 5532 */ 5533 #define MLXSW_REG_PBMC_ID 0x500C 5534 #define MLXSW_REG_PBMC_LEN 0x6C 5535 5536 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5537 5538 /* reg_pbmc_local_port 5539 * Local port number. 5540 * Access: Index 5541 */ 5542 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5543 5544 /* reg_pbmc_xoff_timer_value 5545 * When device generates a pause frame, it uses this value as the pause 5546 * timer (time for the peer port to pause in quota-512 bit time). 5547 * Access: RW 5548 */ 5549 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5550 5551 /* reg_pbmc_xoff_refresh 5552 * The time before a new pause frame should be sent to refresh the pause RW 5553 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5554 * time). 5555 * Access: RW 5556 */ 5557 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5558 5559 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5560 5561 /* reg_pbmc_buf_lossy 5562 * The field indicates if the buffer is lossy. 5563 * 0 - Lossless 5564 * 1 - Lossy 5565 * Access: RW 5566 */ 5567 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5568 5569 /* reg_pbmc_buf_epsb 5570 * Eligible for Port Shared buffer. 5571 * If epsb is set, packets assigned to buffer are allowed to insert the port 5572 * shared buffer. 5573 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5574 * Access: RW 5575 */ 5576 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5577 5578 /* reg_pbmc_buf_size 5579 * The part of the packet buffer array is allocated for the specific buffer. 5580 * Units are represented in cells. 5581 * Access: RW 5582 */ 5583 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5584 5585 /* reg_pbmc_buf_xoff_threshold 5586 * Once the amount of data in the buffer goes above this value, device 5587 * starts sending PFC frames for all priorities associated with the 5588 * buffer. Units are represented in cells. Reserved in case of lossy 5589 * buffer. 5590 * Access: RW 5591 * 5592 * Note: In Spectrum, reserved for buffer[9]. 5593 */ 5594 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5595 0x08, 0x04, false); 5596 5597 /* reg_pbmc_buf_xon_threshold 5598 * When the amount of data in the buffer goes below this value, device 5599 * stops sending PFC frames for the priorities associated with the 5600 * buffer. Units are represented in cells. Reserved in case of lossy 5601 * buffer. 5602 * Access: RW 5603 * 5604 * Note: In Spectrum, reserved for buffer[9]. 5605 */ 5606 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5607 0x08, 0x04, false); 5608 5609 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5610 u16 xoff_timer_value, u16 xoff_refresh) 5611 { 5612 MLXSW_REG_ZERO(pbmc, payload); 5613 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5614 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5615 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5616 } 5617 5618 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5619 int buf_index, 5620 u16 size) 5621 { 5622 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5623 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5624 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5625 } 5626 5627 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5628 int buf_index, u16 size, 5629 u16 threshold) 5630 { 5631 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5632 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5633 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5634 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5635 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5636 } 5637 5638 /* PSPA - Port Switch Partition Allocation 5639 * --------------------------------------- 5640 * Controls the association of a port with a switch partition and enables 5641 * configuring ports as stacking ports. 5642 */ 5643 #define MLXSW_REG_PSPA_ID 0x500D 5644 #define MLXSW_REG_PSPA_LEN 0x8 5645 5646 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5647 5648 /* reg_pspa_swid 5649 * Switch partition ID. 5650 * Access: RW 5651 */ 5652 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5653 5654 /* reg_pspa_local_port 5655 * Local port number. 5656 * Access: Index 5657 */ 5658 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5659 5660 /* reg_pspa_sub_port 5661 * Virtual port within the local port. Set to 0 when virtual ports are 5662 * disabled on the local port. 5663 * Access: Index 5664 */ 5665 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5666 5667 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5668 { 5669 MLXSW_REG_ZERO(pspa, payload); 5670 mlxsw_reg_pspa_swid_set(payload, swid); 5671 mlxsw_reg_pspa_local_port_set(payload, local_port); 5672 mlxsw_reg_pspa_sub_port_set(payload, 0); 5673 } 5674 5675 /* PMAOS - Ports Module Administrative and Operational Status 5676 * ---------------------------------------------------------- 5677 * This register configures and retrieves the per module status. 5678 */ 5679 #define MLXSW_REG_PMAOS_ID 0x5012 5680 #define MLXSW_REG_PMAOS_LEN 0x10 5681 5682 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5683 5684 /* reg_pmaos_slot_index 5685 * Slot index. 5686 * Access: Index 5687 */ 5688 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5689 5690 /* reg_pmaos_module 5691 * Module number. 5692 * Access: Index 5693 */ 5694 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5695 5696 /* reg_pmaos_ase 5697 * Admin state update enable. 5698 * If this bit is set, admin state will be updated based on admin_state field. 5699 * Only relevant on Set() operations. 5700 * Access: WO 5701 */ 5702 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5703 5704 /* reg_pmaos_ee 5705 * Event update enable. 5706 * If this bit is set, event generation will be updated based on the e field. 5707 * Only relevant on Set operations. 5708 * Access: WO 5709 */ 5710 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5711 5712 enum mlxsw_reg_pmaos_e { 5713 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5714 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5715 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5716 }; 5717 5718 /* reg_pmaos_e 5719 * Event Generation on operational state change. 5720 * Access: RW 5721 */ 5722 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5723 5724 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module, 5725 enum mlxsw_reg_pmaos_e e) 5726 { 5727 MLXSW_REG_ZERO(pmaos, payload); 5728 mlxsw_reg_pmaos_module_set(payload, module); 5729 mlxsw_reg_pmaos_e_set(payload, e); 5730 mlxsw_reg_pmaos_ee_set(payload, true); 5731 } 5732 5733 /* PPLR - Port Physical Loopback Register 5734 * -------------------------------------- 5735 * This register allows configuration of the port's loopback mode. 5736 */ 5737 #define MLXSW_REG_PPLR_ID 0x5018 5738 #define MLXSW_REG_PPLR_LEN 0x8 5739 5740 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5741 5742 /* reg_pplr_local_port 5743 * Local port number. 5744 * Access: Index 5745 */ 5746 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5747 5748 /* Phy local loopback. When set the port's egress traffic is looped back 5749 * to the receiver and the port transmitter is disabled. 5750 */ 5751 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5752 5753 /* reg_pplr_lb_en 5754 * Loopback enable. 5755 * Access: RW 5756 */ 5757 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5758 5759 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5760 bool phy_local) 5761 { 5762 MLXSW_REG_ZERO(pplr, payload); 5763 mlxsw_reg_pplr_local_port_set(payload, local_port); 5764 mlxsw_reg_pplr_lb_en_set(payload, 5765 phy_local ? 5766 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5767 } 5768 5769 /* PMPE - Port Module Plug/Unplug Event Register 5770 * --------------------------------------------- 5771 * This register reports any operational status change of a module. 5772 * A change in the module’s state will generate an event only if the change 5773 * happens after arming the event mechanism. Any changes to the module state 5774 * while the event mechanism is not armed will not be reported. Software can 5775 * query the PMPE register for module status. 5776 */ 5777 #define MLXSW_REG_PMPE_ID 0x5024 5778 #define MLXSW_REG_PMPE_LEN 0x10 5779 5780 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 5781 5782 /* reg_pmpe_slot_index 5783 * Slot index. 5784 * Access: Index 5785 */ 5786 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 5787 5788 /* reg_pmpe_module 5789 * Module number. 5790 * Access: Index 5791 */ 5792 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 5793 5794 enum mlxsw_reg_pmpe_module_status { 5795 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 5796 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 5797 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 5798 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 5799 }; 5800 5801 /* reg_pmpe_module_status 5802 * Module status. 5803 * Access: RO 5804 */ 5805 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 5806 5807 /* reg_pmpe_error_type 5808 * Module error details. 5809 * Access: RO 5810 */ 5811 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 5812 5813 /* PDDR - Port Diagnostics Database Register 5814 * ----------------------------------------- 5815 * The PDDR enables to read the Phy debug database 5816 */ 5817 #define MLXSW_REG_PDDR_ID 0x5031 5818 #define MLXSW_REG_PDDR_LEN 0x100 5819 5820 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 5821 5822 /* reg_pddr_local_port 5823 * Local port number. 5824 * Access: Index 5825 */ 5826 MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8); 5827 5828 enum mlxsw_reg_pddr_page_select { 5829 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 5830 }; 5831 5832 /* reg_pddr_page_select 5833 * Page select index. 5834 * Access: Index 5835 */ 5836 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 5837 5838 enum mlxsw_reg_pddr_trblsh_group_opcode { 5839 /* Monitor opcodes */ 5840 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 5841 }; 5842 5843 /* reg_pddr_group_opcode 5844 * Group selector. 5845 * Access: Index 5846 */ 5847 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 5848 5849 /* reg_pddr_status_opcode 5850 * Group selector. 5851 * Access: RO 5852 */ 5853 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 5854 5855 static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port, 5856 u8 page_select) 5857 { 5858 MLXSW_REG_ZERO(pddr, payload); 5859 mlxsw_reg_pddr_local_port_set(payload, local_port); 5860 mlxsw_reg_pddr_page_select_set(payload, page_select); 5861 } 5862 5863 /* PMTM - Port Module Type Mapping Register 5864 * ---------------------------------------- 5865 * The PMTM allows query or configuration of module types. 5866 */ 5867 #define MLXSW_REG_PMTM_ID 0x5067 5868 #define MLXSW_REG_PMTM_LEN 0x10 5869 5870 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5871 5872 /* reg_pmtm_module 5873 * Module number. 5874 * Access: Index 5875 */ 5876 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5877 5878 enum mlxsw_reg_pmtm_module_type { 5879 /* Backplane with 4 lanes */ 5880 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5881 /* QSFP */ 5882 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5883 /* SFP */ 5884 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5885 /* Backplane with single lane */ 5886 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5887 /* Backplane with two lane */ 5888 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5889 /* Chip2Chip4x */ 5890 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5891 /* Chip2Chip2x */ 5892 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5893 /* Chip2Chip1x */ 5894 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5895 /* QSFP-DD */ 5896 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5897 /* OSFP */ 5898 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5899 /* SFP-DD */ 5900 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5901 /* DSFP */ 5902 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5903 /* Chip2Chip8x */ 5904 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5905 }; 5906 5907 /* reg_pmtm_module_type 5908 * Module type. 5909 * Access: RW 5910 */ 5911 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5912 5913 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5914 { 5915 MLXSW_REG_ZERO(pmtm, payload); 5916 mlxsw_reg_pmtm_module_set(payload, module); 5917 } 5918 5919 static inline void 5920 mlxsw_reg_pmtm_unpack(char *payload, 5921 enum mlxsw_reg_pmtm_module_type *module_type) 5922 { 5923 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5924 } 5925 5926 /* HTGT - Host Trap Group Table 5927 * ---------------------------- 5928 * Configures the properties for forwarding to CPU. 5929 */ 5930 #define MLXSW_REG_HTGT_ID 0x7002 5931 #define MLXSW_REG_HTGT_LEN 0x20 5932 5933 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5934 5935 /* reg_htgt_swid 5936 * Switch partition ID. 5937 * Access: Index 5938 */ 5939 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5940 5941 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5942 5943 /* reg_htgt_type 5944 * CPU path type. 5945 * Access: RW 5946 */ 5947 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5948 5949 enum mlxsw_reg_htgt_trap_group { 5950 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5951 MLXSW_REG_HTGT_TRAP_GROUP_MFDE, 5952 MLXSW_REG_HTGT_TRAP_GROUP_MTWE, 5953 MLXSW_REG_HTGT_TRAP_GROUP_PMPE, 5954 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5955 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5956 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5957 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5958 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5959 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5960 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5961 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5962 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5963 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5964 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 5965 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5966 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5967 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5968 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5969 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5970 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5971 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5972 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5973 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5974 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5975 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5976 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5977 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5978 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5979 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5980 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5981 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5982 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5983 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 5984 5985 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5986 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5987 }; 5988 5989 /* reg_htgt_trap_group 5990 * Trap group number. User defined number specifying which trap groups 5991 * should be forwarded to the CPU. The mapping between trap IDs and trap 5992 * groups is configured using HPKT register. 5993 * Access: Index 5994 */ 5995 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5996 5997 enum { 5998 MLXSW_REG_HTGT_POLICER_DISABLE, 5999 MLXSW_REG_HTGT_POLICER_ENABLE, 6000 }; 6001 6002 /* reg_htgt_pide 6003 * Enable policer ID specified using 'pid' field. 6004 * Access: RW 6005 */ 6006 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6007 6008 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6009 6010 /* reg_htgt_pid 6011 * Policer ID for the trap group. 6012 * Access: RW 6013 */ 6014 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6015 6016 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6017 6018 /* reg_htgt_mirror_action 6019 * Mirror action to use. 6020 * 0 - Trap to CPU. 6021 * 1 - Trap to CPU and mirror to a mirroring agent. 6022 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6023 * Access: RW 6024 * 6025 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6026 */ 6027 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6028 6029 /* reg_htgt_mirroring_agent 6030 * Mirroring agent. 6031 * Access: RW 6032 */ 6033 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6034 6035 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6036 6037 /* reg_htgt_priority 6038 * Trap group priority. 6039 * In case a packet matches multiple classification rules, the packet will 6040 * only be trapped once, based on the trap ID associated with the group (via 6041 * register HPKT) with the highest priority. 6042 * Supported values are 0-7, with 7 represnting the highest priority. 6043 * Access: RW 6044 * 6045 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6046 * by the 'trap_group' field. 6047 */ 6048 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6049 6050 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6051 6052 /* reg_htgt_local_path_cpu_tclass 6053 * CPU ingress traffic class for the trap group. 6054 * Access: RW 6055 */ 6056 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6057 6058 enum mlxsw_reg_htgt_local_path_rdq { 6059 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6060 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6061 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6062 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6063 }; 6064 /* reg_htgt_local_path_rdq 6065 * Receive descriptor queue (RDQ) to use for the trap group. 6066 * Access: RW 6067 */ 6068 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6069 6070 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6071 u8 priority, u8 tc) 6072 { 6073 MLXSW_REG_ZERO(htgt, payload); 6074 6075 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6076 mlxsw_reg_htgt_pide_set(payload, 6077 MLXSW_REG_HTGT_POLICER_DISABLE); 6078 } else { 6079 mlxsw_reg_htgt_pide_set(payload, 6080 MLXSW_REG_HTGT_POLICER_ENABLE); 6081 mlxsw_reg_htgt_pid_set(payload, policer_id); 6082 } 6083 6084 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6085 mlxsw_reg_htgt_trap_group_set(payload, group); 6086 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6087 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6088 mlxsw_reg_htgt_priority_set(payload, priority); 6089 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6090 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6091 } 6092 6093 /* HPKT - Host Packet Trap 6094 * ----------------------- 6095 * Configures trap IDs inside trap groups. 6096 */ 6097 #define MLXSW_REG_HPKT_ID 0x7003 6098 #define MLXSW_REG_HPKT_LEN 0x10 6099 6100 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6101 6102 enum { 6103 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6104 MLXSW_REG_HPKT_ACK_REQUIRED, 6105 }; 6106 6107 /* reg_hpkt_ack 6108 * Require acknowledgements from the host for events. 6109 * If set, then the device will wait for the event it sent to be acknowledged 6110 * by the host. This option is only relevant for event trap IDs. 6111 * Access: RW 6112 * 6113 * Note: Currently not supported by firmware. 6114 */ 6115 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6116 6117 enum mlxsw_reg_hpkt_action { 6118 MLXSW_REG_HPKT_ACTION_FORWARD, 6119 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6120 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6121 MLXSW_REG_HPKT_ACTION_DISCARD, 6122 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6123 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6124 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6125 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6126 }; 6127 6128 /* reg_hpkt_action 6129 * Action to perform on packet when trapped. 6130 * 0 - No action. Forward to CPU based on switching rules. 6131 * 1 - Trap to CPU (CPU receives sole copy). 6132 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6133 * 3 - Discard. 6134 * 4 - Soft discard (allow other traps to act on the packet). 6135 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6136 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6137 * 15 - Restore the firmware's default action. 6138 * Access: RW 6139 * 6140 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6141 * addressed to the CPU. 6142 */ 6143 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6144 6145 /* reg_hpkt_trap_group 6146 * Trap group to associate the trap with. 6147 * Access: RW 6148 */ 6149 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6150 6151 /* reg_hpkt_trap_id 6152 * Trap ID. 6153 * Access: Index 6154 * 6155 * Note: A trap ID can only be associated with a single trap group. The device 6156 * will associate the trap ID with the last trap group configured. 6157 */ 6158 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6159 6160 enum { 6161 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6162 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6163 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6164 }; 6165 6166 /* reg_hpkt_ctrl 6167 * Configure dedicated buffer resources for control packets. 6168 * Ignored by SwitchX-2. 6169 * 0 - Keep factory defaults. 6170 * 1 - Do not use control buffer for this trap ID. 6171 * 2 - Use control buffer for this trap ID. 6172 * Access: RW 6173 */ 6174 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6175 6176 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6177 enum mlxsw_reg_htgt_trap_group trap_group, 6178 bool is_ctrl) 6179 { 6180 MLXSW_REG_ZERO(hpkt, payload); 6181 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6182 mlxsw_reg_hpkt_action_set(payload, action); 6183 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6184 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6185 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6186 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6187 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6188 } 6189 6190 /* RGCR - Router General Configuration Register 6191 * -------------------------------------------- 6192 * The register is used for setting up the router configuration. 6193 */ 6194 #define MLXSW_REG_RGCR_ID 0x8001 6195 #define MLXSW_REG_RGCR_LEN 0x28 6196 6197 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6198 6199 /* reg_rgcr_ipv4_en 6200 * IPv4 router enable. 6201 * Access: RW 6202 */ 6203 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6204 6205 /* reg_rgcr_ipv6_en 6206 * IPv6 router enable. 6207 * Access: RW 6208 */ 6209 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6210 6211 /* reg_rgcr_max_router_interfaces 6212 * Defines the maximum number of active router interfaces for all virtual 6213 * routers. 6214 * Access: RW 6215 */ 6216 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6217 6218 /* reg_rgcr_usp 6219 * Update switch priority and packet color. 6220 * 0 - Preserve the value of Switch Priority and packet color. 6221 * 1 - Recalculate the value of Switch Priority and packet color. 6222 * Access: RW 6223 * 6224 * Note: Not supported by SwitchX and SwitchX-2. 6225 */ 6226 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6227 6228 /* reg_rgcr_pcp_rw 6229 * Indicates how to handle the pcp_rewrite_en value: 6230 * 0 - Preserve the value of pcp_rewrite_en. 6231 * 2 - Disable PCP rewrite. 6232 * 3 - Enable PCP rewrite. 6233 * Access: RW 6234 * 6235 * Note: Not supported by SwitchX and SwitchX-2. 6236 */ 6237 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6238 6239 /* reg_rgcr_activity_dis 6240 * Activity disable: 6241 * 0 - Activity will be set when an entry is hit (default). 6242 * 1 - Activity will not be set when an entry is hit. 6243 * 6244 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6245 * (RALUE). 6246 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6247 * Entry (RAUHT). 6248 * Bits 2:7 are reserved. 6249 * Access: RW 6250 * 6251 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6252 */ 6253 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6254 6255 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6256 bool ipv6_en) 6257 { 6258 MLXSW_REG_ZERO(rgcr, payload); 6259 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6260 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6261 } 6262 6263 /* RITR - Router Interface Table Register 6264 * -------------------------------------- 6265 * The register is used to configure the router interface table. 6266 */ 6267 #define MLXSW_REG_RITR_ID 0x8002 6268 #define MLXSW_REG_RITR_LEN 0x40 6269 6270 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6271 6272 /* reg_ritr_enable 6273 * Enables routing on the router interface. 6274 * Access: RW 6275 */ 6276 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6277 6278 /* reg_ritr_ipv4 6279 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6280 * interface. 6281 * Access: RW 6282 */ 6283 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6284 6285 /* reg_ritr_ipv6 6286 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6287 * interface. 6288 * Access: RW 6289 */ 6290 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6291 6292 /* reg_ritr_ipv4_mc 6293 * IPv4 multicast routing enable. 6294 * Access: RW 6295 */ 6296 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6297 6298 /* reg_ritr_ipv6_mc 6299 * IPv6 multicast routing enable. 6300 * Access: RW 6301 */ 6302 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6303 6304 enum mlxsw_reg_ritr_if_type { 6305 /* VLAN interface. */ 6306 MLXSW_REG_RITR_VLAN_IF, 6307 /* FID interface. */ 6308 MLXSW_REG_RITR_FID_IF, 6309 /* Sub-port interface. */ 6310 MLXSW_REG_RITR_SP_IF, 6311 /* Loopback Interface. */ 6312 MLXSW_REG_RITR_LOOPBACK_IF, 6313 }; 6314 6315 /* reg_ritr_type 6316 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6317 * Access: RW 6318 */ 6319 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6320 6321 enum { 6322 MLXSW_REG_RITR_RIF_CREATE, 6323 MLXSW_REG_RITR_RIF_DEL, 6324 }; 6325 6326 /* reg_ritr_op 6327 * Opcode: 6328 * 0 - Create or edit RIF. 6329 * 1 - Delete RIF. 6330 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6331 * is not supported. An interface must be deleted and re-created in order 6332 * to update properties. 6333 * Access: WO 6334 */ 6335 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6336 6337 /* reg_ritr_rif 6338 * Router interface index. A pointer to the Router Interface Table. 6339 * Access: Index 6340 */ 6341 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6342 6343 /* reg_ritr_ipv4_fe 6344 * IPv4 Forwarding Enable. 6345 * Enables routing of IPv4 traffic on the router interface. When disabled, 6346 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6347 * Not supported in SwitchX-2. 6348 * Access: RW 6349 */ 6350 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6351 6352 /* reg_ritr_ipv6_fe 6353 * IPv6 Forwarding Enable. 6354 * Enables routing of IPv6 traffic on the router interface. When disabled, 6355 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6356 * Not supported in SwitchX-2. 6357 * Access: RW 6358 */ 6359 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6360 6361 /* reg_ritr_ipv4_mc_fe 6362 * IPv4 Multicast Forwarding Enable. 6363 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6364 * will be enabled. 6365 * Access: RW 6366 */ 6367 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6368 6369 /* reg_ritr_ipv6_mc_fe 6370 * IPv6 Multicast Forwarding Enable. 6371 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6372 * will be enabled. 6373 * Access: RW 6374 */ 6375 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6376 6377 /* reg_ritr_lb_en 6378 * Loop-back filter enable for unicast packets. 6379 * If the flag is set then loop-back filter for unicast packets is 6380 * implemented on the RIF. Multicast packets are always subject to 6381 * loop-back filtering. 6382 * Access: RW 6383 */ 6384 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6385 6386 /* reg_ritr_virtual_router 6387 * Virtual router ID associated with the router interface. 6388 * Access: RW 6389 */ 6390 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6391 6392 /* reg_ritr_mtu 6393 * Router interface MTU. 6394 * Access: RW 6395 */ 6396 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6397 6398 /* reg_ritr_if_swid 6399 * Switch partition ID. 6400 * Access: RW 6401 */ 6402 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6403 6404 /* reg_ritr_if_mac 6405 * Router interface MAC address. 6406 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6407 * Access: RW 6408 */ 6409 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6410 6411 /* reg_ritr_if_vrrp_id_ipv6 6412 * VRRP ID for IPv6 6413 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6414 * Access: RW 6415 */ 6416 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6417 6418 /* reg_ritr_if_vrrp_id_ipv4 6419 * VRRP ID for IPv4 6420 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6421 * Access: RW 6422 */ 6423 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6424 6425 /* VLAN Interface */ 6426 6427 /* reg_ritr_vlan_if_vid 6428 * VLAN ID. 6429 * Access: RW 6430 */ 6431 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6432 6433 /* FID Interface */ 6434 6435 /* reg_ritr_fid_if_fid 6436 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6437 * the vFID range are supported. 6438 * Access: RW 6439 */ 6440 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6441 6442 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6443 enum mlxsw_reg_ritr_if_type rif_type, 6444 u16 fid) 6445 { 6446 if (rif_type == MLXSW_REG_RITR_FID_IF) 6447 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6448 else 6449 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6450 } 6451 6452 /* Sub-port Interface */ 6453 6454 /* reg_ritr_sp_if_lag 6455 * LAG indication. When this bit is set the system_port field holds the 6456 * LAG identifier. 6457 * Access: RW 6458 */ 6459 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6460 6461 /* reg_ritr_sp_system_port 6462 * Port unique indentifier. When lag bit is set, this field holds the 6463 * lag_id in bits 0:9. 6464 * Access: RW 6465 */ 6466 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6467 6468 /* reg_ritr_sp_if_vid 6469 * VLAN ID. 6470 * Access: RW 6471 */ 6472 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6473 6474 /* Loopback Interface */ 6475 6476 enum mlxsw_reg_ritr_loopback_protocol { 6477 /* IPinIP IPv4 underlay Unicast */ 6478 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6479 /* IPinIP IPv6 underlay Unicast */ 6480 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6481 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6482 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6483 }; 6484 6485 /* reg_ritr_loopback_protocol 6486 * Access: RW 6487 */ 6488 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6489 6490 enum mlxsw_reg_ritr_loopback_ipip_type { 6491 /* Tunnel is IPinIP. */ 6492 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6493 /* Tunnel is GRE, no key. */ 6494 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6495 /* Tunnel is GRE, with a key. */ 6496 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6497 }; 6498 6499 /* reg_ritr_loopback_ipip_type 6500 * Encapsulation type. 6501 * Access: RW 6502 */ 6503 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6504 6505 enum mlxsw_reg_ritr_loopback_ipip_options { 6506 /* The key is defined by gre_key. */ 6507 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6508 }; 6509 6510 /* reg_ritr_loopback_ipip_options 6511 * Access: RW 6512 */ 6513 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6514 6515 /* reg_ritr_loopback_ipip_uvr 6516 * Underlay Virtual Router ID. 6517 * Range is 0..cap_max_virtual_routers-1. 6518 * Reserved for Spectrum-2. 6519 * Access: RW 6520 */ 6521 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6522 6523 /* reg_ritr_loopback_ipip_underlay_rif 6524 * Underlay ingress router interface. 6525 * Reserved for Spectrum. 6526 * Access: RW 6527 */ 6528 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6529 6530 /* reg_ritr_loopback_ipip_usip* 6531 * Encapsulation Underlay source IP. 6532 * Access: RW 6533 */ 6534 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6535 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6536 6537 /* reg_ritr_loopback_ipip_gre_key 6538 * GRE Key. 6539 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6540 * Access: RW 6541 */ 6542 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6543 6544 /* Shared between ingress/egress */ 6545 enum mlxsw_reg_ritr_counter_set_type { 6546 /* No Count. */ 6547 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6548 /* Basic. Used for router interfaces, counting the following: 6549 * - Error and Discard counters. 6550 * - Unicast, Multicast and Broadcast counters. Sharing the 6551 * same set of counters for the different type of traffic 6552 * (IPv4, IPv6 and mpls). 6553 */ 6554 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6555 }; 6556 6557 /* reg_ritr_ingress_counter_index 6558 * Counter Index for flow counter. 6559 * Access: RW 6560 */ 6561 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6562 6563 /* reg_ritr_ingress_counter_set_type 6564 * Igress Counter Set Type for router interface counter. 6565 * Access: RW 6566 */ 6567 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6568 6569 /* reg_ritr_egress_counter_index 6570 * Counter Index for flow counter. 6571 * Access: RW 6572 */ 6573 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6574 6575 /* reg_ritr_egress_counter_set_type 6576 * Egress Counter Set Type for router interface counter. 6577 * Access: RW 6578 */ 6579 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6580 6581 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6582 bool enable, bool egress) 6583 { 6584 enum mlxsw_reg_ritr_counter_set_type set_type; 6585 6586 if (enable) 6587 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6588 else 6589 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6590 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6591 6592 if (egress) 6593 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6594 else 6595 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6596 } 6597 6598 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6599 { 6600 MLXSW_REG_ZERO(ritr, payload); 6601 mlxsw_reg_ritr_rif_set(payload, rif); 6602 } 6603 6604 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6605 u16 system_port, u16 vid) 6606 { 6607 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6608 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6609 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6610 } 6611 6612 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6613 enum mlxsw_reg_ritr_if_type type, 6614 u16 rif, u16 vr_id, u16 mtu) 6615 { 6616 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6617 6618 MLXSW_REG_ZERO(ritr, payload); 6619 mlxsw_reg_ritr_enable_set(payload, enable); 6620 mlxsw_reg_ritr_ipv4_set(payload, 1); 6621 mlxsw_reg_ritr_ipv6_set(payload, 1); 6622 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6623 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6624 mlxsw_reg_ritr_type_set(payload, type); 6625 mlxsw_reg_ritr_op_set(payload, op); 6626 mlxsw_reg_ritr_rif_set(payload, rif); 6627 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6628 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6629 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6630 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6631 mlxsw_reg_ritr_lb_en_set(payload, 1); 6632 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6633 mlxsw_reg_ritr_mtu_set(payload, mtu); 6634 } 6635 6636 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6637 { 6638 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6639 } 6640 6641 static inline void 6642 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6643 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6644 enum mlxsw_reg_ritr_loopback_ipip_options options, 6645 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6646 { 6647 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6648 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6649 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6650 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6651 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6652 } 6653 6654 static inline void 6655 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6656 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6657 enum mlxsw_reg_ritr_loopback_ipip_options options, 6658 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6659 { 6660 mlxsw_reg_ritr_loopback_protocol_set(payload, 6661 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6662 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6663 uvr_id, underlay_rif, gre_key); 6664 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6665 } 6666 6667 /* RTAR - Router TCAM Allocation Register 6668 * -------------------------------------- 6669 * This register is used for allocation of regions in the TCAM table. 6670 */ 6671 #define MLXSW_REG_RTAR_ID 0x8004 6672 #define MLXSW_REG_RTAR_LEN 0x20 6673 6674 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6675 6676 enum mlxsw_reg_rtar_op { 6677 MLXSW_REG_RTAR_OP_ALLOCATE, 6678 MLXSW_REG_RTAR_OP_RESIZE, 6679 MLXSW_REG_RTAR_OP_DEALLOCATE, 6680 }; 6681 6682 /* reg_rtar_op 6683 * Access: WO 6684 */ 6685 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6686 6687 enum mlxsw_reg_rtar_key_type { 6688 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6689 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6690 }; 6691 6692 /* reg_rtar_key_type 6693 * TCAM key type for the region. 6694 * Access: WO 6695 */ 6696 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6697 6698 /* reg_rtar_region_size 6699 * TCAM region size. When allocating/resizing this is the requested 6700 * size, the response is the actual size. 6701 * Note: Actual size may be larger than requested. 6702 * Reserved for op = Deallocate 6703 * Access: WO 6704 */ 6705 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6706 6707 static inline void mlxsw_reg_rtar_pack(char *payload, 6708 enum mlxsw_reg_rtar_op op, 6709 enum mlxsw_reg_rtar_key_type key_type, 6710 u16 region_size) 6711 { 6712 MLXSW_REG_ZERO(rtar, payload); 6713 mlxsw_reg_rtar_op_set(payload, op); 6714 mlxsw_reg_rtar_key_type_set(payload, key_type); 6715 mlxsw_reg_rtar_region_size_set(payload, region_size); 6716 } 6717 6718 /* RATR - Router Adjacency Table Register 6719 * -------------------------------------- 6720 * The RATR register is used to configure the Router Adjacency (next-hop) 6721 * Table. 6722 */ 6723 #define MLXSW_REG_RATR_ID 0x8008 6724 #define MLXSW_REG_RATR_LEN 0x2C 6725 6726 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6727 6728 enum mlxsw_reg_ratr_op { 6729 /* Read */ 6730 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6731 /* Read and clear activity */ 6732 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6733 /* Write Adjacency entry */ 6734 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6735 /* Write Adjacency entry only if the activity is cleared. 6736 * The write may not succeed if the activity is set. There is not 6737 * direct feedback if the write has succeeded or not, however 6738 * the get will reveal the actual entry (SW can compare the get 6739 * response to the set command). 6740 */ 6741 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6742 }; 6743 6744 /* reg_ratr_op 6745 * Note that Write operation may also be used for updating 6746 * counter_set_type and counter_index. In this case all other 6747 * fields must not be updated. 6748 * Access: OP 6749 */ 6750 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6751 6752 /* reg_ratr_v 6753 * Valid bit. Indicates if the adjacency entry is valid. 6754 * Note: the device may need some time before reusing an invalidated 6755 * entry. During this time the entry can not be reused. It is 6756 * recommended to use another entry before reusing an invalidated 6757 * entry (e.g. software can put it at the end of the list for 6758 * reusing). Trying to access an invalidated entry not yet cleared 6759 * by the device results with failure indicating "Try Again" status. 6760 * When valid is '0' then egress_router_interface,trap_action, 6761 * adjacency_parameters and counters are reserved 6762 * Access: RW 6763 */ 6764 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6765 6766 /* reg_ratr_a 6767 * Activity. Set for new entries. Set if a packet lookup has hit on 6768 * the specific entry. To clear the a bit, use "clear activity". 6769 * Access: RO 6770 */ 6771 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6772 6773 enum mlxsw_reg_ratr_type { 6774 /* Ethernet */ 6775 MLXSW_REG_RATR_TYPE_ETHERNET, 6776 /* IPoIB Unicast without GRH. 6777 * Reserved for Spectrum. 6778 */ 6779 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6780 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6781 * adjacency). 6782 * Reserved for Spectrum. 6783 */ 6784 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6785 /* IPoIB Multicast. 6786 * Reserved for Spectrum. 6787 */ 6788 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6789 /* MPLS. 6790 * Reserved for SwitchX/-2. 6791 */ 6792 MLXSW_REG_RATR_TYPE_MPLS, 6793 /* IPinIP Encap. 6794 * Reserved for SwitchX/-2. 6795 */ 6796 MLXSW_REG_RATR_TYPE_IPIP, 6797 }; 6798 6799 /* reg_ratr_type 6800 * Adjacency entry type. 6801 * Access: RW 6802 */ 6803 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6804 6805 /* reg_ratr_adjacency_index_low 6806 * Bits 15:0 of index into the adjacency table. 6807 * For SwitchX and SwitchX-2, the adjacency table is linear and 6808 * used for adjacency entries only. 6809 * For Spectrum, the index is to the KVD linear. 6810 * Access: Index 6811 */ 6812 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6813 6814 /* reg_ratr_egress_router_interface 6815 * Range is 0 .. cap_max_router_interfaces - 1 6816 * Access: RW 6817 */ 6818 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6819 6820 enum mlxsw_reg_ratr_trap_action { 6821 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6822 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6823 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6824 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6825 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6826 }; 6827 6828 /* reg_ratr_trap_action 6829 * see mlxsw_reg_ratr_trap_action 6830 * Access: RW 6831 */ 6832 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6833 6834 /* reg_ratr_adjacency_index_high 6835 * Bits 23:16 of the adjacency_index. 6836 * Access: Index 6837 */ 6838 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6839 6840 enum mlxsw_reg_ratr_trap_id { 6841 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6842 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6843 }; 6844 6845 /* reg_ratr_trap_id 6846 * Trap ID to be reported to CPU. 6847 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6848 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6849 * Access: RW 6850 */ 6851 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6852 6853 /* reg_ratr_eth_destination_mac 6854 * MAC address of the destination next-hop. 6855 * Access: RW 6856 */ 6857 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6858 6859 enum mlxsw_reg_ratr_ipip_type { 6860 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6861 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6862 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6863 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6864 }; 6865 6866 /* reg_ratr_ipip_type 6867 * Underlay destination ip type. 6868 * Note: the type field must match the protocol of the router interface. 6869 * Access: RW 6870 */ 6871 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6872 6873 /* reg_ratr_ipip_ipv4_udip 6874 * Underlay ipv4 dip. 6875 * Reserved when ipip_type is IPv6. 6876 * Access: RW 6877 */ 6878 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6879 6880 /* reg_ratr_ipip_ipv6_ptr 6881 * Pointer to IPv6 underlay destination ip address. 6882 * For Spectrum: Pointer to KVD linear space. 6883 * Access: RW 6884 */ 6885 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6886 6887 enum mlxsw_reg_flow_counter_set_type { 6888 /* No count */ 6889 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6890 /* Count packets and bytes */ 6891 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6892 /* Count only packets */ 6893 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6894 }; 6895 6896 /* reg_ratr_counter_set_type 6897 * Counter set type for flow counters 6898 * Access: RW 6899 */ 6900 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6901 6902 /* reg_ratr_counter_index 6903 * Counter index for flow counters 6904 * Access: RW 6905 */ 6906 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6907 6908 static inline void 6909 mlxsw_reg_ratr_pack(char *payload, 6910 enum mlxsw_reg_ratr_op op, bool valid, 6911 enum mlxsw_reg_ratr_type type, 6912 u32 adjacency_index, u16 egress_rif) 6913 { 6914 MLXSW_REG_ZERO(ratr, payload); 6915 mlxsw_reg_ratr_op_set(payload, op); 6916 mlxsw_reg_ratr_v_set(payload, valid); 6917 mlxsw_reg_ratr_type_set(payload, type); 6918 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6919 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6920 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6921 } 6922 6923 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6924 const char *dest_mac) 6925 { 6926 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6927 } 6928 6929 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6930 { 6931 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6932 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6933 } 6934 6935 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6936 bool counter_enable) 6937 { 6938 enum mlxsw_reg_flow_counter_set_type set_type; 6939 6940 if (counter_enable) 6941 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6942 else 6943 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6944 6945 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6946 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6947 } 6948 6949 /* RDPM - Router DSCP to Priority Mapping 6950 * -------------------------------------- 6951 * Controls the mapping from DSCP field to switch priority on routed packets 6952 */ 6953 #define MLXSW_REG_RDPM_ID 0x8009 6954 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6955 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6956 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6957 #define MLXSW_REG_RDPM_LEN 0x40 6958 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6959 MLXSW_REG_RDPM_LEN - \ 6960 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6961 6962 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6963 6964 /* reg_dscp_entry_e 6965 * Enable update of the specific entry 6966 * Access: Index 6967 */ 6968 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6969 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6970 6971 /* reg_dscp_entry_prio 6972 * Switch Priority 6973 * Access: RW 6974 */ 6975 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6976 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6977 6978 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6979 u8 prio) 6980 { 6981 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6982 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6983 } 6984 6985 /* RICNT - Router Interface Counter Register 6986 * ----------------------------------------- 6987 * The RICNT register retrieves per port performance counters 6988 */ 6989 #define MLXSW_REG_RICNT_ID 0x800B 6990 #define MLXSW_REG_RICNT_LEN 0x100 6991 6992 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6993 6994 /* reg_ricnt_counter_index 6995 * Counter index 6996 * Access: RW 6997 */ 6998 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6999 7000 enum mlxsw_reg_ricnt_counter_set_type { 7001 /* No Count. */ 7002 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7003 /* Basic. Used for router interfaces, counting the following: 7004 * - Error and Discard counters. 7005 * - Unicast, Multicast and Broadcast counters. Sharing the 7006 * same set of counters for the different type of traffic 7007 * (IPv4, IPv6 and mpls). 7008 */ 7009 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7010 }; 7011 7012 /* reg_ricnt_counter_set_type 7013 * Counter Set Type for router interface counter 7014 * Access: RW 7015 */ 7016 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7017 7018 enum mlxsw_reg_ricnt_opcode { 7019 /* Nop. Supported only for read access*/ 7020 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7021 /* Clear. Setting the clr bit will reset the counter value for 7022 * all counters of the specified Router Interface. 7023 */ 7024 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7025 }; 7026 7027 /* reg_ricnt_opcode 7028 * Opcode 7029 * Access: RW 7030 */ 7031 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7032 7033 /* reg_ricnt_good_unicast_packets 7034 * good unicast packets. 7035 * Access: RW 7036 */ 7037 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7038 7039 /* reg_ricnt_good_multicast_packets 7040 * good multicast packets. 7041 * Access: RW 7042 */ 7043 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7044 7045 /* reg_ricnt_good_broadcast_packets 7046 * good broadcast packets 7047 * Access: RW 7048 */ 7049 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7050 7051 /* reg_ricnt_good_unicast_bytes 7052 * A count of L3 data and padding octets not including L2 headers 7053 * for good unicast frames. 7054 * Access: RW 7055 */ 7056 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7057 7058 /* reg_ricnt_good_multicast_bytes 7059 * A count of L3 data and padding octets not including L2 headers 7060 * for good multicast frames. 7061 * Access: RW 7062 */ 7063 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7064 7065 /* reg_ritr_good_broadcast_bytes 7066 * A count of L3 data and padding octets not including L2 headers 7067 * for good broadcast frames. 7068 * Access: RW 7069 */ 7070 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7071 7072 /* reg_ricnt_error_packets 7073 * A count of errored frames that do not pass the router checks. 7074 * Access: RW 7075 */ 7076 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7077 7078 /* reg_ricnt_discrad_packets 7079 * A count of non-errored frames that do not pass the router checks. 7080 * Access: RW 7081 */ 7082 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7083 7084 /* reg_ricnt_error_bytes 7085 * A count of L3 data and padding octets not including L2 headers 7086 * for errored frames. 7087 * Access: RW 7088 */ 7089 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7090 7091 /* reg_ricnt_discard_bytes 7092 * A count of L3 data and padding octets not including L2 headers 7093 * for non-errored frames that do not pass the router checks. 7094 * Access: RW 7095 */ 7096 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7097 7098 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7099 enum mlxsw_reg_ricnt_opcode op) 7100 { 7101 MLXSW_REG_ZERO(ricnt, payload); 7102 mlxsw_reg_ricnt_op_set(payload, op); 7103 mlxsw_reg_ricnt_counter_index_set(payload, index); 7104 mlxsw_reg_ricnt_counter_set_type_set(payload, 7105 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7106 } 7107 7108 /* RRCR - Router Rules Copy Register Layout 7109 * ---------------------------------------- 7110 * This register is used for moving and copying route entry rules. 7111 */ 7112 #define MLXSW_REG_RRCR_ID 0x800F 7113 #define MLXSW_REG_RRCR_LEN 0x24 7114 7115 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7116 7117 enum mlxsw_reg_rrcr_op { 7118 /* Move rules */ 7119 MLXSW_REG_RRCR_OP_MOVE, 7120 /* Copy rules */ 7121 MLXSW_REG_RRCR_OP_COPY, 7122 }; 7123 7124 /* reg_rrcr_op 7125 * Access: WO 7126 */ 7127 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7128 7129 /* reg_rrcr_offset 7130 * Offset within the region from which to copy/move. 7131 * Access: Index 7132 */ 7133 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7134 7135 /* reg_rrcr_size 7136 * The number of rules to copy/move. 7137 * Access: WO 7138 */ 7139 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7140 7141 /* reg_rrcr_table_id 7142 * Identifier of the table on which to perform the operation. Encoding is the 7143 * same as in RTAR.key_type 7144 * Access: Index 7145 */ 7146 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7147 7148 /* reg_rrcr_dest_offset 7149 * Offset within the region to which to copy/move 7150 * Access: Index 7151 */ 7152 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7153 7154 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7155 u16 offset, u16 size, 7156 enum mlxsw_reg_rtar_key_type table_id, 7157 u16 dest_offset) 7158 { 7159 MLXSW_REG_ZERO(rrcr, payload); 7160 mlxsw_reg_rrcr_op_set(payload, op); 7161 mlxsw_reg_rrcr_offset_set(payload, offset); 7162 mlxsw_reg_rrcr_size_set(payload, size); 7163 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7164 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7165 } 7166 7167 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7168 * ------------------------------------------------------- 7169 * RALTA is used to allocate the LPM trees of the SHSPM method. 7170 */ 7171 #define MLXSW_REG_RALTA_ID 0x8010 7172 #define MLXSW_REG_RALTA_LEN 0x04 7173 7174 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7175 7176 /* reg_ralta_op 7177 * opcode (valid for Write, must be 0 on Read) 7178 * 0 - allocate a tree 7179 * 1 - deallocate a tree 7180 * Access: OP 7181 */ 7182 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7183 7184 enum mlxsw_reg_ralxx_protocol { 7185 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7186 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7187 }; 7188 7189 /* reg_ralta_protocol 7190 * Protocol. 7191 * Deallocation opcode: Reserved. 7192 * Access: RW 7193 */ 7194 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7195 7196 /* reg_ralta_tree_id 7197 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7198 * the tree identifier (managed by software). 7199 * Note that tree_id 0 is allocated for a default-route tree. 7200 * Access: Index 7201 */ 7202 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7203 7204 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7205 enum mlxsw_reg_ralxx_protocol protocol, 7206 u8 tree_id) 7207 { 7208 MLXSW_REG_ZERO(ralta, payload); 7209 mlxsw_reg_ralta_op_set(payload, !alloc); 7210 mlxsw_reg_ralta_protocol_set(payload, protocol); 7211 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7212 } 7213 7214 /* RALST - Router Algorithmic LPM Structure Tree Register 7215 * ------------------------------------------------------ 7216 * RALST is used to set and query the structure of an LPM tree. 7217 * The structure of the tree must be sorted as a sorted binary tree, while 7218 * each node is a bin that is tagged as the length of the prefixes the lookup 7219 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7220 * of X bits to match with the destination address. The bin 0 indicates 7221 * the default action, when there is no match of any prefix. 7222 */ 7223 #define MLXSW_REG_RALST_ID 0x8011 7224 #define MLXSW_REG_RALST_LEN 0x104 7225 7226 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7227 7228 /* reg_ralst_root_bin 7229 * The bin number of the root bin. 7230 * 0<root_bin=<(length of IP address) 7231 * For a default-route tree configure 0xff 7232 * Access: RW 7233 */ 7234 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7235 7236 /* reg_ralst_tree_id 7237 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7238 * Access: Index 7239 */ 7240 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7241 7242 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7243 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7244 #define MLXSW_REG_RALST_BIN_COUNT 128 7245 7246 /* reg_ralst_left_child_bin 7247 * Holding the children of the bin according to the stored tree's structure. 7248 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7249 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7250 * Access: RW 7251 */ 7252 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7253 7254 /* reg_ralst_right_child_bin 7255 * Holding the children of the bin according to the stored tree's structure. 7256 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7257 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7258 * Access: RW 7259 */ 7260 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7261 false); 7262 7263 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7264 { 7265 MLXSW_REG_ZERO(ralst, payload); 7266 7267 /* Initialize all bins to have no left or right child */ 7268 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7269 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7270 7271 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7272 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7273 } 7274 7275 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7276 u8 left_child_bin, 7277 u8 right_child_bin) 7278 { 7279 int bin_index = bin_number - 1; 7280 7281 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7282 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7283 right_child_bin); 7284 } 7285 7286 /* RALTB - Router Algorithmic LPM Tree Binding Register 7287 * ---------------------------------------------------- 7288 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7289 */ 7290 #define MLXSW_REG_RALTB_ID 0x8012 7291 #define MLXSW_REG_RALTB_LEN 0x04 7292 7293 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7294 7295 /* reg_raltb_virtual_router 7296 * Virtual Router ID 7297 * Range is 0..cap_max_virtual_routers-1 7298 * Access: Index 7299 */ 7300 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7301 7302 /* reg_raltb_protocol 7303 * Protocol. 7304 * Access: Index 7305 */ 7306 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7307 7308 /* reg_raltb_tree_id 7309 * Tree to be used for the {virtual_router, protocol} 7310 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7311 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7312 * Access: RW 7313 */ 7314 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7315 7316 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7317 enum mlxsw_reg_ralxx_protocol protocol, 7318 u8 tree_id) 7319 { 7320 MLXSW_REG_ZERO(raltb, payload); 7321 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7322 mlxsw_reg_raltb_protocol_set(payload, protocol); 7323 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7324 } 7325 7326 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7327 * ----------------------------------------------------- 7328 * RALUE is used to configure and query LPM entries that serve 7329 * the Unicast protocols. 7330 */ 7331 #define MLXSW_REG_RALUE_ID 0x8013 7332 #define MLXSW_REG_RALUE_LEN 0x38 7333 7334 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7335 7336 /* reg_ralue_protocol 7337 * Protocol. 7338 * Access: Index 7339 */ 7340 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7341 7342 enum mlxsw_reg_ralue_op { 7343 /* Read operation. If entry doesn't exist, the operation fails. */ 7344 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7345 /* Clear on read operation. Used to read entry and 7346 * clear Activity bit. 7347 */ 7348 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7349 /* Write operation. Used to write a new entry to the table. All RW 7350 * fields are written for new entry. Activity bit is set 7351 * for new entries. 7352 */ 7353 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7354 /* Update operation. Used to update an existing route entry and 7355 * only update the RW fields that are detailed in the field 7356 * op_u_mask. If entry doesn't exist, the operation fails. 7357 */ 7358 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7359 /* Clear activity. The Activity bit (the field a) is cleared 7360 * for the entry. 7361 */ 7362 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7363 /* Delete operation. Used to delete an existing entry. If entry 7364 * doesn't exist, the operation fails. 7365 */ 7366 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7367 }; 7368 7369 /* reg_ralue_op 7370 * Operation. 7371 * Access: OP 7372 */ 7373 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7374 7375 /* reg_ralue_a 7376 * Activity. Set for new entries. Set if a packet lookup has hit on the 7377 * specific entry, only if the entry is a route. To clear the a bit, use 7378 * "clear activity" op. 7379 * Enabled by activity_dis in RGCR 7380 * Access: RO 7381 */ 7382 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7383 7384 /* reg_ralue_virtual_router 7385 * Virtual Router ID 7386 * Range is 0..cap_max_virtual_routers-1 7387 * Access: Index 7388 */ 7389 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7390 7391 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7392 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7393 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7394 7395 /* reg_ralue_op_u_mask 7396 * opcode update mask. 7397 * On read operation, this field is reserved. 7398 * This field is valid for update opcode, otherwise - reserved. 7399 * This field is a bitmask of the fields that should be updated. 7400 * Access: WO 7401 */ 7402 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7403 7404 /* reg_ralue_prefix_len 7405 * Number of bits in the prefix of the LPM route. 7406 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7407 * two entries in the physical HW table. 7408 * Access: Index 7409 */ 7410 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7411 7412 /* reg_ralue_dip* 7413 * The prefix of the route or of the marker that the object of the LPM 7414 * is compared with. The most significant bits of the dip are the prefix. 7415 * The least significant bits must be '0' if the prefix_len is smaller 7416 * than 128 for IPv6 or smaller than 32 for IPv4. 7417 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7418 * Access: Index 7419 */ 7420 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7421 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7422 7423 enum mlxsw_reg_ralue_entry_type { 7424 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7425 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7426 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7427 }; 7428 7429 /* reg_ralue_entry_type 7430 * Entry type. 7431 * Note - for Marker entries, the action_type and action fields are reserved. 7432 * Access: RW 7433 */ 7434 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7435 7436 /* reg_ralue_bmp_len 7437 * The best match prefix length in the case that there is no match for 7438 * longer prefixes. 7439 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7440 * Note for any update operation with entry_type modification this 7441 * field must be set. 7442 * Access: RW 7443 */ 7444 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7445 7446 enum mlxsw_reg_ralue_action_type { 7447 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7448 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7449 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7450 }; 7451 7452 /* reg_ralue_action_type 7453 * Action Type 7454 * Indicates how the IP address is connected. 7455 * It can be connected to a local subnet through local_erif or can be 7456 * on a remote subnet connected through a next-hop router, 7457 * or transmitted to the CPU. 7458 * Reserved when entry_type = MARKER_ENTRY 7459 * Access: RW 7460 */ 7461 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7462 7463 enum mlxsw_reg_ralue_trap_action { 7464 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7465 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7466 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7467 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7468 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7469 }; 7470 7471 /* reg_ralue_trap_action 7472 * Trap action. 7473 * For IP2ME action, only NOP and MIRROR are possible. 7474 * Access: RW 7475 */ 7476 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7477 7478 /* reg_ralue_trap_id 7479 * Trap ID to be reported to CPU. 7480 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7481 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7482 * Access: RW 7483 */ 7484 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7485 7486 /* reg_ralue_adjacency_index 7487 * Points to the first entry of the group-based ECMP. 7488 * Only relevant in case of REMOTE action. 7489 * Access: RW 7490 */ 7491 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7492 7493 /* reg_ralue_ecmp_size 7494 * Amount of sequential entries starting 7495 * from the adjacency_index (the number of ECMPs). 7496 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7497 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7498 * Only relevant in case of REMOTE action. 7499 * Access: RW 7500 */ 7501 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7502 7503 /* reg_ralue_local_erif 7504 * Egress Router Interface. 7505 * Only relevant in case of LOCAL action. 7506 * Access: RW 7507 */ 7508 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7509 7510 /* reg_ralue_ip2me_v 7511 * Valid bit for the tunnel_ptr field. 7512 * If valid = 0 then trap to CPU as IP2ME trap ID. 7513 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7514 * decapsulation then tunnel decapsulation is done. 7515 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7516 * decapsulation then trap as IP2ME trap ID. 7517 * Only relevant in case of IP2ME action. 7518 * Access: RW 7519 */ 7520 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7521 7522 /* reg_ralue_ip2me_tunnel_ptr 7523 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7524 * For Spectrum, pointer to KVD Linear. 7525 * Only relevant in case of IP2ME action. 7526 * Access: RW 7527 */ 7528 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7529 7530 static inline void mlxsw_reg_ralue_pack(char *payload, 7531 enum mlxsw_reg_ralxx_protocol protocol, 7532 enum mlxsw_reg_ralue_op op, 7533 u16 virtual_router, u8 prefix_len) 7534 { 7535 MLXSW_REG_ZERO(ralue, payload); 7536 mlxsw_reg_ralue_protocol_set(payload, protocol); 7537 mlxsw_reg_ralue_op_set(payload, op); 7538 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7539 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7540 mlxsw_reg_ralue_entry_type_set(payload, 7541 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7542 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7543 } 7544 7545 static inline void mlxsw_reg_ralue_pack4(char *payload, 7546 enum mlxsw_reg_ralxx_protocol protocol, 7547 enum mlxsw_reg_ralue_op op, 7548 u16 virtual_router, u8 prefix_len, 7549 u32 *dip) 7550 { 7551 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7552 if (dip) 7553 mlxsw_reg_ralue_dip4_set(payload, *dip); 7554 } 7555 7556 static inline void mlxsw_reg_ralue_pack6(char *payload, 7557 enum mlxsw_reg_ralxx_protocol protocol, 7558 enum mlxsw_reg_ralue_op op, 7559 u16 virtual_router, u8 prefix_len, 7560 const void *dip) 7561 { 7562 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7563 if (dip) 7564 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7565 } 7566 7567 static inline void 7568 mlxsw_reg_ralue_act_remote_pack(char *payload, 7569 enum mlxsw_reg_ralue_trap_action trap_action, 7570 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7571 { 7572 mlxsw_reg_ralue_action_type_set(payload, 7573 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7574 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7575 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7576 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7577 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7578 } 7579 7580 static inline void 7581 mlxsw_reg_ralue_act_local_pack(char *payload, 7582 enum mlxsw_reg_ralue_trap_action trap_action, 7583 u16 trap_id, u16 local_erif) 7584 { 7585 mlxsw_reg_ralue_action_type_set(payload, 7586 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7587 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7588 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7589 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7590 } 7591 7592 static inline void 7593 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7594 { 7595 mlxsw_reg_ralue_action_type_set(payload, 7596 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7597 } 7598 7599 static inline void 7600 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7601 { 7602 mlxsw_reg_ralue_action_type_set(payload, 7603 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7604 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7605 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7606 } 7607 7608 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7609 * ---------------------------------------------------------- 7610 * The RAUHT register is used to configure and query the Unicast Host table in 7611 * devices that implement the Algorithmic LPM. 7612 */ 7613 #define MLXSW_REG_RAUHT_ID 0x8014 7614 #define MLXSW_REG_RAUHT_LEN 0x74 7615 7616 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7617 7618 enum mlxsw_reg_rauht_type { 7619 MLXSW_REG_RAUHT_TYPE_IPV4, 7620 MLXSW_REG_RAUHT_TYPE_IPV6, 7621 }; 7622 7623 /* reg_rauht_type 7624 * Access: Index 7625 */ 7626 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7627 7628 enum mlxsw_reg_rauht_op { 7629 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7630 /* Read operation */ 7631 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7632 /* Clear on read operation. Used to read entry and clear 7633 * activity bit. 7634 */ 7635 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7636 /* Add. Used to write a new entry to the table. All R/W fields are 7637 * relevant for new entry. Activity bit is set for new entries. 7638 */ 7639 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7640 /* Update action. Used to update an existing route entry and 7641 * only update the following fields: 7642 * trap_action, trap_id, mac, counter_set_type, counter_index 7643 */ 7644 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7645 /* Clear activity. A bit is cleared for the entry. */ 7646 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7647 /* Delete entry */ 7648 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7649 /* Delete all host entries on a RIF. In this command, dip 7650 * field is reserved. 7651 */ 7652 }; 7653 7654 /* reg_rauht_op 7655 * Access: OP 7656 */ 7657 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7658 7659 /* reg_rauht_a 7660 * Activity. Set for new entries. Set if a packet lookup has hit on 7661 * the specific entry. 7662 * To clear the a bit, use "clear activity" op. 7663 * Enabled by activity_dis in RGCR 7664 * Access: RO 7665 */ 7666 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7667 7668 /* reg_rauht_rif 7669 * Router Interface 7670 * Access: Index 7671 */ 7672 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7673 7674 /* reg_rauht_dip* 7675 * Destination address. 7676 * Access: Index 7677 */ 7678 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7679 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7680 7681 enum mlxsw_reg_rauht_trap_action { 7682 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7683 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7684 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7685 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7686 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7687 }; 7688 7689 /* reg_rauht_trap_action 7690 * Access: RW 7691 */ 7692 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7693 7694 enum mlxsw_reg_rauht_trap_id { 7695 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7696 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7697 }; 7698 7699 /* reg_rauht_trap_id 7700 * Trap ID to be reported to CPU. 7701 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7702 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7703 * trap_id is reserved. 7704 * Access: RW 7705 */ 7706 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7707 7708 /* reg_rauht_counter_set_type 7709 * Counter set type for flow counters 7710 * Access: RW 7711 */ 7712 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7713 7714 /* reg_rauht_counter_index 7715 * Counter index for flow counters 7716 * Access: RW 7717 */ 7718 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7719 7720 /* reg_rauht_mac 7721 * MAC address. 7722 * Access: RW 7723 */ 7724 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7725 7726 static inline void mlxsw_reg_rauht_pack(char *payload, 7727 enum mlxsw_reg_rauht_op op, u16 rif, 7728 const char *mac) 7729 { 7730 MLXSW_REG_ZERO(rauht, payload); 7731 mlxsw_reg_rauht_op_set(payload, op); 7732 mlxsw_reg_rauht_rif_set(payload, rif); 7733 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7734 } 7735 7736 static inline void mlxsw_reg_rauht_pack4(char *payload, 7737 enum mlxsw_reg_rauht_op op, u16 rif, 7738 const char *mac, u32 dip) 7739 { 7740 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7741 mlxsw_reg_rauht_dip4_set(payload, dip); 7742 } 7743 7744 static inline void mlxsw_reg_rauht_pack6(char *payload, 7745 enum mlxsw_reg_rauht_op op, u16 rif, 7746 const char *mac, const char *dip) 7747 { 7748 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7749 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7750 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7751 } 7752 7753 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7754 u64 counter_index) 7755 { 7756 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7757 mlxsw_reg_rauht_counter_set_type_set(payload, 7758 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7759 } 7760 7761 /* RALEU - Router Algorithmic LPM ECMP Update Register 7762 * --------------------------------------------------- 7763 * The register enables updating the ECMP section in the action for multiple 7764 * LPM Unicast entries in a single operation. The update is executed to 7765 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7766 */ 7767 #define MLXSW_REG_RALEU_ID 0x8015 7768 #define MLXSW_REG_RALEU_LEN 0x28 7769 7770 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7771 7772 /* reg_raleu_protocol 7773 * Protocol. 7774 * Access: Index 7775 */ 7776 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7777 7778 /* reg_raleu_virtual_router 7779 * Virtual Router ID 7780 * Range is 0..cap_max_virtual_routers-1 7781 * Access: Index 7782 */ 7783 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7784 7785 /* reg_raleu_adjacency_index 7786 * Adjacency Index used for matching on the existing entries. 7787 * Access: Index 7788 */ 7789 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7790 7791 /* reg_raleu_ecmp_size 7792 * ECMP Size used for matching on the existing entries. 7793 * Access: Index 7794 */ 7795 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7796 7797 /* reg_raleu_new_adjacency_index 7798 * New Adjacency Index. 7799 * Access: WO 7800 */ 7801 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7802 7803 /* reg_raleu_new_ecmp_size 7804 * New ECMP Size. 7805 * Access: WO 7806 */ 7807 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7808 7809 static inline void mlxsw_reg_raleu_pack(char *payload, 7810 enum mlxsw_reg_ralxx_protocol protocol, 7811 u16 virtual_router, 7812 u32 adjacency_index, u16 ecmp_size, 7813 u32 new_adjacency_index, 7814 u16 new_ecmp_size) 7815 { 7816 MLXSW_REG_ZERO(raleu, payload); 7817 mlxsw_reg_raleu_protocol_set(payload, protocol); 7818 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7819 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7820 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7821 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7822 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7823 } 7824 7825 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7826 * ---------------------------------------------------------------- 7827 * The RAUHTD register allows dumping entries from the Router Unicast Host 7828 * Table. For a given session an entry is dumped no more than one time. The 7829 * first RAUHTD access after reset is a new session. A session ends when the 7830 * num_rec response is smaller than num_rec request or for IPv4 when the 7831 * num_entries is smaller than 4. The clear activity affect the current session 7832 * or the last session if a new session has not started. 7833 */ 7834 #define MLXSW_REG_RAUHTD_ID 0x8018 7835 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7836 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7837 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7838 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7839 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7840 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7841 7842 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7843 7844 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7845 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7846 7847 /* reg_rauhtd_filter_fields 7848 * if a bit is '0' then the relevant field is ignored and dump is done 7849 * regardless of the field value 7850 * Bit0 - filter by activity: entry_a 7851 * Bit3 - filter by entry rip: entry_rif 7852 * Access: Index 7853 */ 7854 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7855 7856 enum mlxsw_reg_rauhtd_op { 7857 MLXSW_REG_RAUHTD_OP_DUMP, 7858 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7859 }; 7860 7861 /* reg_rauhtd_op 7862 * Access: OP 7863 */ 7864 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7865 7866 /* reg_rauhtd_num_rec 7867 * At request: number of records requested 7868 * At response: number of records dumped 7869 * For IPv4, each record has 4 entries at request and up to 4 entries 7870 * at response 7871 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7872 * Access: Index 7873 */ 7874 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7875 7876 /* reg_rauhtd_entry_a 7877 * Dump only if activity has value of entry_a 7878 * Reserved if filter_fields bit0 is '0' 7879 * Access: Index 7880 */ 7881 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7882 7883 enum mlxsw_reg_rauhtd_type { 7884 MLXSW_REG_RAUHTD_TYPE_IPV4, 7885 MLXSW_REG_RAUHTD_TYPE_IPV6, 7886 }; 7887 7888 /* reg_rauhtd_type 7889 * Dump only if record type is: 7890 * 0 - IPv4 7891 * 1 - IPv6 7892 * Access: Index 7893 */ 7894 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7895 7896 /* reg_rauhtd_entry_rif 7897 * Dump only if RIF has value of entry_rif 7898 * Reserved if filter_fields bit3 is '0' 7899 * Access: Index 7900 */ 7901 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7902 7903 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7904 enum mlxsw_reg_rauhtd_type type) 7905 { 7906 MLXSW_REG_ZERO(rauhtd, payload); 7907 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7908 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7909 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7910 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7911 mlxsw_reg_rauhtd_type_set(payload, type); 7912 } 7913 7914 /* reg_rauhtd_ipv4_rec_num_entries 7915 * Number of valid entries in this record: 7916 * 0 - 1 valid entry 7917 * 1 - 2 valid entries 7918 * 2 - 3 valid entries 7919 * 3 - 4 valid entries 7920 * Access: RO 7921 */ 7922 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7923 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7924 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7925 7926 /* reg_rauhtd_rec_type 7927 * Record type. 7928 * 0 - IPv4 7929 * 1 - IPv6 7930 * Access: RO 7931 */ 7932 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7933 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7934 7935 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7936 7937 /* reg_rauhtd_ipv4_ent_a 7938 * Activity. Set for new entries. Set if a packet lookup has hit on the 7939 * specific entry. 7940 * Access: RO 7941 */ 7942 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7943 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7944 7945 /* reg_rauhtd_ipv4_ent_rif 7946 * Router interface. 7947 * Access: RO 7948 */ 7949 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7950 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7951 7952 /* reg_rauhtd_ipv4_ent_dip 7953 * Destination IPv4 address. 7954 * Access: RO 7955 */ 7956 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7957 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7958 7959 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7960 7961 /* reg_rauhtd_ipv6_ent_a 7962 * Activity. Set for new entries. Set if a packet lookup has hit on the 7963 * specific entry. 7964 * Access: RO 7965 */ 7966 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7967 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7968 7969 /* reg_rauhtd_ipv6_ent_rif 7970 * Router interface. 7971 * Access: RO 7972 */ 7973 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7974 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7975 7976 /* reg_rauhtd_ipv6_ent_dip 7977 * Destination IPv6 address. 7978 * Access: RO 7979 */ 7980 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7981 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7982 7983 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7984 int ent_index, u16 *p_rif, 7985 u32 *p_dip) 7986 { 7987 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7988 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7989 } 7990 7991 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7992 int rec_index, u16 *p_rif, 7993 char *p_dip) 7994 { 7995 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7996 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7997 } 7998 7999 /* RTDP - Routing Tunnel Decap Properties Register 8000 * ----------------------------------------------- 8001 * The RTDP register is used for configuring the tunnel decap properties of NVE 8002 * and IPinIP. 8003 */ 8004 #define MLXSW_REG_RTDP_ID 0x8020 8005 #define MLXSW_REG_RTDP_LEN 0x44 8006 8007 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8008 8009 enum mlxsw_reg_rtdp_type { 8010 MLXSW_REG_RTDP_TYPE_NVE, 8011 MLXSW_REG_RTDP_TYPE_IPIP, 8012 }; 8013 8014 /* reg_rtdp_type 8015 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8016 * Access: RW 8017 */ 8018 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8019 8020 /* reg_rtdp_tunnel_index 8021 * Index to the Decap entry. 8022 * For Spectrum, Index to KVD Linear. 8023 * Access: Index 8024 */ 8025 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8026 8027 /* reg_rtdp_egress_router_interface 8028 * Underlay egress router interface. 8029 * Valid range is from 0 to cap_max_router_interfaces - 1 8030 * Access: RW 8031 */ 8032 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8033 8034 /* IPinIP */ 8035 8036 /* reg_rtdp_ipip_irif 8037 * Ingress Router Interface for the overlay router 8038 * Access: RW 8039 */ 8040 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8041 8042 enum mlxsw_reg_rtdp_ipip_sip_check { 8043 /* No sip checks. */ 8044 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8045 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8046 * equal ipv4_usip. 8047 */ 8048 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8049 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8050 * equal ipv6_usip. 8051 */ 8052 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8053 }; 8054 8055 /* reg_rtdp_ipip_sip_check 8056 * SIP check to perform. If decapsulation failed due to these configurations 8057 * then trap_id is IPIP_DECAP_ERROR. 8058 * Access: RW 8059 */ 8060 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8061 8062 /* If set, allow decapsulation of IPinIP (without GRE). */ 8063 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8064 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8065 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8066 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8067 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8068 8069 /* reg_rtdp_ipip_type_check 8070 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8071 * these configurations then trap_id is IPIP_DECAP_ERROR. 8072 * Access: RW 8073 */ 8074 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8075 8076 /* reg_rtdp_ipip_gre_key_check 8077 * Whether GRE key should be checked. When check is enabled: 8078 * - A packet received as IPinIP (without GRE) will always pass. 8079 * - A packet received as IPinGREinIP without a key will not pass the check. 8080 * - A packet received as IPinGREinIP with a key will pass the check only if the 8081 * key in the packet is equal to expected_gre_key. 8082 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8083 * Access: RW 8084 */ 8085 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8086 8087 /* reg_rtdp_ipip_ipv4_usip 8088 * Underlay IPv4 address for ipv4 source address check. 8089 * Reserved when sip_check is not '1'. 8090 * Access: RW 8091 */ 8092 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8093 8094 /* reg_rtdp_ipip_ipv6_usip_ptr 8095 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8096 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8097 * is to the KVD linear. 8098 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8099 * Access: RW 8100 */ 8101 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8102 8103 /* reg_rtdp_ipip_expected_gre_key 8104 * GRE key for checking. 8105 * Reserved when gre_key_check is '0'. 8106 * Access: RW 8107 */ 8108 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8109 8110 static inline void mlxsw_reg_rtdp_pack(char *payload, 8111 enum mlxsw_reg_rtdp_type type, 8112 u32 tunnel_index) 8113 { 8114 MLXSW_REG_ZERO(rtdp, payload); 8115 mlxsw_reg_rtdp_type_set(payload, type); 8116 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8117 } 8118 8119 static inline void 8120 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8121 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8122 unsigned int type_check, bool gre_key_check, 8123 u32 ipv4_usip, u32 expected_gre_key) 8124 { 8125 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8126 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8127 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8128 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8129 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8130 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8131 } 8132 8133 /* RATRAD - Router Adjacency Table Activity Dump Register 8134 * ------------------------------------------------------ 8135 * The RATRAD register is used to dump and optionally clear activity bits of 8136 * router adjacency table entries. 8137 */ 8138 #define MLXSW_REG_RATRAD_ID 0x8022 8139 #define MLXSW_REG_RATRAD_LEN 0x210 8140 8141 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8142 8143 enum { 8144 /* Read activity */ 8145 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8146 /* Read and clear activity */ 8147 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8148 }; 8149 8150 /* reg_ratrad_op 8151 * Access: Operation 8152 */ 8153 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8154 8155 /* reg_ratrad_ecmp_size 8156 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8157 * ranges: 8158 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8159 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8160 * Access: Index 8161 */ 8162 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8163 8164 /* reg_ratrad_adjacency_index 8165 * Index into the adjacency table. 8166 * Access: Index 8167 */ 8168 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8169 8170 /* reg_ratrad_activity_vector 8171 * Activity bit per adjacency index. 8172 * Bits higher than ecmp_size are reserved. 8173 * Access: RO 8174 */ 8175 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8176 8177 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8178 u16 ecmp_size) 8179 { 8180 MLXSW_REG_ZERO(ratrad, payload); 8181 mlxsw_reg_ratrad_op_set(payload, 8182 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8183 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8184 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8185 } 8186 8187 /* RIGR-V2 - Router Interface Group Register Version 2 8188 * --------------------------------------------------- 8189 * The RIGR_V2 register is used to add, remove and query egress interface list 8190 * of a multicast forwarding entry. 8191 */ 8192 #define MLXSW_REG_RIGR2_ID 0x8023 8193 #define MLXSW_REG_RIGR2_LEN 0xB0 8194 8195 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8196 8197 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8198 8199 /* reg_rigr2_rigr_index 8200 * KVD Linear index. 8201 * Access: Index 8202 */ 8203 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8204 8205 /* reg_rigr2_vnext 8206 * Next RIGR Index is valid. 8207 * Access: RW 8208 */ 8209 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8210 8211 /* reg_rigr2_next_rigr_index 8212 * Next RIGR Index. The index is to the KVD linear. 8213 * Reserved when vnxet = '0'. 8214 * Access: RW 8215 */ 8216 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8217 8218 /* reg_rigr2_vrmid 8219 * RMID Index is valid. 8220 * Access: RW 8221 */ 8222 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8223 8224 /* reg_rigr2_rmid_index 8225 * RMID Index. 8226 * Range 0 .. max_mid - 1 8227 * Reserved when vrmid = '0'. 8228 * The index is to the Port Group Table (PGT) 8229 * Access: RW 8230 */ 8231 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8232 8233 /* reg_rigr2_erif_entry_v 8234 * Egress Router Interface is valid. 8235 * Note that low-entries must be set if high-entries are set. For 8236 * example: if erif_entry[2].v is set then erif_entry[1].v and 8237 * erif_entry[0].v must be set. 8238 * Index can be from 0 to cap_mc_erif_list_entries-1 8239 * Access: RW 8240 */ 8241 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8242 8243 /* reg_rigr2_erif_entry_erif 8244 * Egress Router Interface. 8245 * Valid range is from 0 to cap_max_router_interfaces - 1 8246 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8247 * Access: RW 8248 */ 8249 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8250 8251 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8252 bool vnext, u32 next_rigr_index) 8253 { 8254 MLXSW_REG_ZERO(rigr2, payload); 8255 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8256 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8257 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8258 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8259 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8260 } 8261 8262 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8263 bool v, u16 erif) 8264 { 8265 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8266 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8267 } 8268 8269 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8270 * ------------------------------------------------------ 8271 */ 8272 #define MLXSW_REG_RECR2_ID 0x8025 8273 #define MLXSW_REG_RECR2_LEN 0x38 8274 8275 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8276 8277 /* reg_recr2_pp 8278 * Per-port configuration 8279 * Access: Index 8280 */ 8281 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8282 8283 /* reg_recr2_sh 8284 * Symmetric hash 8285 * Access: RW 8286 */ 8287 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8288 8289 /* reg_recr2_seed 8290 * Seed 8291 * Access: RW 8292 */ 8293 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8294 8295 enum { 8296 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8297 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8298 /* Enable IPv4 fields if packet is TCP or UDP */ 8299 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8300 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8301 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8302 /* Enable IPv6 fields if packet is TCP or UDP */ 8303 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8304 /* Enable TCP/UDP header fields if packet is IPv4 */ 8305 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8306 /* Enable TCP/UDP header fields if packet is IPv6 */ 8307 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8308 8309 __MLXSW_REG_RECR2_HEADER_CNT, 8310 }; 8311 8312 /* reg_recr2_outer_header_enables 8313 * Bit mask where each bit enables a specific layer to be included in 8314 * the hash calculation. 8315 * Access: RW 8316 */ 8317 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8318 8319 enum { 8320 /* IPv4 Source IP */ 8321 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8322 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8323 /* IPv4 Destination IP */ 8324 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8325 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8326 /* IP Protocol */ 8327 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8328 /* IPv6 Source IP */ 8329 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8330 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8331 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8332 /* IPv6 Destination IP */ 8333 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8334 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8335 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8336 /* IPv6 Next Header */ 8337 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8338 /* IPv6 Flow Label */ 8339 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8340 /* TCP/UDP Source Port */ 8341 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8342 /* TCP/UDP Destination Port */ 8343 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8344 8345 __MLXSW_REG_RECR2_FIELD_CNT, 8346 }; 8347 8348 /* reg_recr2_outer_header_fields_enable 8349 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8350 * Access: RW 8351 */ 8352 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8353 8354 /* reg_recr2_inner_header_enables 8355 * Bit mask where each bit enables a specific inner layer to be included in the 8356 * hash calculation. Same values as reg_recr2_outer_header_enables. 8357 * Access: RW 8358 */ 8359 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8360 8361 enum { 8362 /* Inner IPv4 Source IP */ 8363 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8364 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8365 /* Inner IPv4 Destination IP */ 8366 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8367 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8368 /* Inner IP Protocol */ 8369 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8370 /* Inner IPv6 Source IP */ 8371 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8372 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8373 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8374 /* Inner IPv6 Destination IP */ 8375 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8376 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8377 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8378 /* Inner IPv6 Next Header */ 8379 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8380 /* Inner IPv6 Flow Label */ 8381 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8382 /* Inner TCP/UDP Source Port */ 8383 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8384 /* Inner TCP/UDP Destination Port */ 8385 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8386 8387 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8388 }; 8389 8390 /* reg_recr2_inner_header_fields_enable 8391 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8392 * Access: RW 8393 */ 8394 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8395 8396 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8397 { 8398 MLXSW_REG_ZERO(recr2, payload); 8399 mlxsw_reg_recr2_pp_set(payload, false); 8400 mlxsw_reg_recr2_sh_set(payload, true); 8401 mlxsw_reg_recr2_seed_set(payload, seed); 8402 } 8403 8404 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8405 * -------------------------------------------------------------- 8406 * The RMFT_V2 register is used to configure and query the multicast table. 8407 */ 8408 #define MLXSW_REG_RMFT2_ID 0x8027 8409 #define MLXSW_REG_RMFT2_LEN 0x174 8410 8411 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8412 8413 /* reg_rmft2_v 8414 * Valid 8415 * Access: RW 8416 */ 8417 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8418 8419 enum mlxsw_reg_rmft2_type { 8420 MLXSW_REG_RMFT2_TYPE_IPV4, 8421 MLXSW_REG_RMFT2_TYPE_IPV6 8422 }; 8423 8424 /* reg_rmft2_type 8425 * Access: Index 8426 */ 8427 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8428 8429 enum mlxsw_sp_reg_rmft2_op { 8430 /* For Write: 8431 * Write operation. Used to write a new entry to the table. All RW 8432 * fields are relevant for new entry. Activity bit is set for new 8433 * entries - Note write with v (Valid) 0 will delete the entry. 8434 * For Query: 8435 * Read operation 8436 */ 8437 MLXSW_REG_RMFT2_OP_READ_WRITE, 8438 }; 8439 8440 /* reg_rmft2_op 8441 * Operation. 8442 * Access: OP 8443 */ 8444 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8445 8446 /* reg_rmft2_a 8447 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8448 * entry. 8449 * Access: RO 8450 */ 8451 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8452 8453 /* reg_rmft2_offset 8454 * Offset within the multicast forwarding table to write to. 8455 * Access: Index 8456 */ 8457 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8458 8459 /* reg_rmft2_virtual_router 8460 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8461 * Access: RW 8462 */ 8463 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8464 8465 enum mlxsw_reg_rmft2_irif_mask { 8466 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8467 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8468 }; 8469 8470 /* reg_rmft2_irif_mask 8471 * Ingress RIF mask. 8472 * Access: RW 8473 */ 8474 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8475 8476 /* reg_rmft2_irif 8477 * Ingress RIF index. 8478 * Access: RW 8479 */ 8480 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8481 8482 /* reg_rmft2_dip{4,6} 8483 * Destination IPv4/6 address 8484 * Access: RW 8485 */ 8486 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8487 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8488 8489 /* reg_rmft2_dip{4,6}_mask 8490 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8491 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8492 * Access: RW 8493 */ 8494 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8495 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8496 8497 /* reg_rmft2_sip{4,6} 8498 * Source IPv4/6 address 8499 * Access: RW 8500 */ 8501 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8502 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8503 8504 /* reg_rmft2_sip{4,6}_mask 8505 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8506 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8507 * Access: RW 8508 */ 8509 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8510 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8511 8512 /* reg_rmft2_flexible_action_set 8513 * ACL action set. The only supported action types in this field and in any 8514 * action-set pointed from here are as follows: 8515 * 00h: ACTION_NULL 8516 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8517 * 03h: ACTION_TRAP 8518 * 06h: ACTION_QOS 8519 * 08h: ACTION_POLICING_MONITORING 8520 * 10h: ACTION_ROUTER_MC 8521 * Access: RW 8522 */ 8523 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8524 MLXSW_REG_FLEX_ACTION_SET_LEN); 8525 8526 static inline void 8527 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8528 u16 virtual_router, 8529 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8530 const char *flex_action_set) 8531 { 8532 MLXSW_REG_ZERO(rmft2, payload); 8533 mlxsw_reg_rmft2_v_set(payload, v); 8534 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8535 mlxsw_reg_rmft2_offset_set(payload, offset); 8536 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8537 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8538 mlxsw_reg_rmft2_irif_set(payload, irif); 8539 if (flex_action_set) 8540 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8541 flex_action_set); 8542 } 8543 8544 static inline void 8545 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8546 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8547 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8548 const char *flexible_action_set) 8549 { 8550 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8551 irif_mask, irif, flexible_action_set); 8552 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8553 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8554 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8555 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8556 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8557 } 8558 8559 static inline void 8560 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8561 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8562 struct in6_addr dip6, struct in6_addr dip6_mask, 8563 struct in6_addr sip6, struct in6_addr sip6_mask, 8564 const char *flexible_action_set) 8565 { 8566 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8567 irif_mask, irif, flexible_action_set); 8568 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8569 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8570 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8571 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8572 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8573 } 8574 8575 /* RXLTE - Router XLT Enable Register 8576 * ---------------------------------- 8577 * The RXLTE enables XLT (eXtended Lookup Table) LPM lookups if a capable 8578 * XM is present on the system. 8579 */ 8580 8581 #define MLXSW_REG_RXLTE_ID 0x8050 8582 #define MLXSW_REG_RXLTE_LEN 0x0C 8583 8584 MLXSW_REG_DEFINE(rxlte, MLXSW_REG_RXLTE_ID, MLXSW_REG_RXLTE_LEN); 8585 8586 /* reg_rxlte_virtual_router 8587 * Virtual router ID associated with the router interface. 8588 * Range is 0..cap_max_virtual_routers-1 8589 * Access: Index 8590 */ 8591 MLXSW_ITEM32(reg, rxlte, virtual_router, 0x00, 0, 16); 8592 8593 enum mlxsw_reg_rxlte_protocol { 8594 MLXSW_REG_RXLTE_PROTOCOL_IPV4, 8595 MLXSW_REG_RXLTE_PROTOCOL_IPV6, 8596 }; 8597 8598 /* reg_rxlte_protocol 8599 * Access: Index 8600 */ 8601 MLXSW_ITEM32(reg, rxlte, protocol, 0x04, 0, 4); 8602 8603 /* reg_rxlte_lpm_xlt_en 8604 * Access: RW 8605 */ 8606 MLXSW_ITEM32(reg, rxlte, lpm_xlt_en, 0x08, 0, 1); 8607 8608 static inline void mlxsw_reg_rxlte_pack(char *payload, u16 virtual_router, 8609 enum mlxsw_reg_rxlte_protocol protocol, 8610 bool lpm_xlt_en) 8611 { 8612 MLXSW_REG_ZERO(rxlte, payload); 8613 mlxsw_reg_rxlte_virtual_router_set(payload, virtual_router); 8614 mlxsw_reg_rxlte_protocol_set(payload, protocol); 8615 mlxsw_reg_rxlte_lpm_xlt_en_set(payload, lpm_xlt_en); 8616 } 8617 8618 /* RXLTM - Router XLT M select Register 8619 * ------------------------------------ 8620 * The RXLTM configures and selects the M for the XM lookups. 8621 */ 8622 8623 #define MLXSW_REG_RXLTM_ID 0x8051 8624 #define MLXSW_REG_RXLTM_LEN 0x14 8625 8626 MLXSW_REG_DEFINE(rxltm, MLXSW_REG_RXLTM_ID, MLXSW_REG_RXLTM_LEN); 8627 8628 /* reg_rxltm_m0_val_v6 8629 * Global M0 value For IPv6. 8630 * Range 0..128 8631 * Access: RW 8632 */ 8633 MLXSW_ITEM32(reg, rxltm, m0_val_v6, 0x10, 16, 8); 8634 8635 /* reg_rxltm_m0_val_v4 8636 * Global M0 value For IPv4. 8637 * Range 0..32 8638 * Access: RW 8639 */ 8640 MLXSW_ITEM32(reg, rxltm, m0_val_v4, 0x10, 0, 6); 8641 8642 static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v6) 8643 { 8644 MLXSW_REG_ZERO(rxltm, payload); 8645 mlxsw_reg_rxltm_m0_val_v6_set(payload, m0_val_v6); 8646 mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4); 8647 } 8648 8649 /* RLCMLD - Router LPM Cache ML Delete Register 8650 * -------------------------------------------- 8651 * The RLCMLD register is used to bulk delete the XLT-LPM cache ML entries. 8652 * This can be used by SW when L is increased or decreased, thus need to 8653 * remove entries with old ML values. 8654 */ 8655 8656 #define MLXSW_REG_RLCMLD_ID 0x8055 8657 #define MLXSW_REG_RLCMLD_LEN 0x30 8658 8659 MLXSW_REG_DEFINE(rlcmld, MLXSW_REG_RLCMLD_ID, MLXSW_REG_RLCMLD_LEN); 8660 8661 enum mlxsw_reg_rlcmld_select { 8662 MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES, 8663 MLXSW_REG_RLCMLD_SELECT_M_ENTRIES, 8664 MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES, 8665 }; 8666 8667 /* reg_rlcmld_select 8668 * Which entries to delete. 8669 * Access: Index 8670 */ 8671 MLXSW_ITEM32(reg, rlcmld, select, 0x00, 16, 2); 8672 8673 enum mlxsw_reg_rlcmld_filter_fields { 8674 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL = 0x04, 8675 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER = 0x08, 8676 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP = 0x10, 8677 }; 8678 8679 /* reg_rlcmld_filter_fields 8680 * If a bit is '0' then the relevant field is ignored. 8681 * Access: Index 8682 */ 8683 MLXSW_ITEM32(reg, rlcmld, filter_fields, 0x00, 0, 8); 8684 8685 enum mlxsw_reg_rlcmld_protocol { 8686 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, 8687 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, 8688 }; 8689 8690 /* reg_rlcmld_protocol 8691 * Access: Index 8692 */ 8693 MLXSW_ITEM32(reg, rlcmld, protocol, 0x08, 0, 4); 8694 8695 /* reg_rlcmld_virtual_router 8696 * Virtual router ID. 8697 * Range is 0..cap_max_virtual_routers-1 8698 * Access: Index 8699 */ 8700 MLXSW_ITEM32(reg, rlcmld, virtual_router, 0x0C, 0, 16); 8701 8702 /* reg_rlcmld_dip 8703 * The prefix of the route or of the marker that the object of the LPM 8704 * is compared with. The most significant bits of the dip are the prefix. 8705 * Access: Index 8706 */ 8707 MLXSW_ITEM32(reg, rlcmld, dip4, 0x1C, 0, 32); 8708 MLXSW_ITEM_BUF(reg, rlcmld, dip6, 0x10, 16); 8709 8710 /* reg_rlcmld_dip_mask 8711 * per bit: 8712 * 0: no match 8713 * 1: match 8714 * Access: Index 8715 */ 8716 MLXSW_ITEM32(reg, rlcmld, dip_mask4, 0x2C, 0, 32); 8717 MLXSW_ITEM_BUF(reg, rlcmld, dip_mask6, 0x20, 16); 8718 8719 static inline void __mlxsw_reg_rlcmld_pack(char *payload, 8720 enum mlxsw_reg_rlcmld_select select, 8721 enum mlxsw_reg_rlcmld_protocol protocol, 8722 u16 virtual_router) 8723 { 8724 u8 filter_fields = MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL | 8725 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER | 8726 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP; 8727 8728 MLXSW_REG_ZERO(rlcmld, payload); 8729 mlxsw_reg_rlcmld_select_set(payload, select); 8730 mlxsw_reg_rlcmld_filter_fields_set(payload, filter_fields); 8731 mlxsw_reg_rlcmld_protocol_set(payload, protocol); 8732 mlxsw_reg_rlcmld_virtual_router_set(payload, virtual_router); 8733 } 8734 8735 static inline void mlxsw_reg_rlcmld_pack4(char *payload, 8736 enum mlxsw_reg_rlcmld_select select, 8737 u16 virtual_router, 8738 u32 dip, u32 dip_mask) 8739 { 8740 __mlxsw_reg_rlcmld_pack(payload, select, 8741 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, 8742 virtual_router); 8743 mlxsw_reg_rlcmld_dip4_set(payload, dip); 8744 mlxsw_reg_rlcmld_dip_mask4_set(payload, dip_mask); 8745 } 8746 8747 static inline void mlxsw_reg_rlcmld_pack6(char *payload, 8748 enum mlxsw_reg_rlcmld_select select, 8749 u16 virtual_router, 8750 const void *dip, const void *dip_mask) 8751 { 8752 __mlxsw_reg_rlcmld_pack(payload, select, 8753 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, 8754 virtual_router); 8755 mlxsw_reg_rlcmld_dip6_memcpy_to(payload, dip); 8756 mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask); 8757 } 8758 8759 /* RLPMCE - Router LPM Cache Enable Register 8760 * ----------------------------------------- 8761 * Allows disabling the LPM cache. Can be changed on the fly. 8762 */ 8763 8764 #define MLXSW_REG_RLPMCE_ID 0x8056 8765 #define MLXSW_REG_RLPMCE_LEN 0x4 8766 8767 MLXSW_REG_DEFINE(rlpmce, MLXSW_REG_RLPMCE_ID, MLXSW_REG_RLPMCE_LEN); 8768 8769 /* reg_rlpmce_flush 8770 * Flush: 8771 * 0: do not flush the cache (default) 8772 * 1: flush (clear) the cache 8773 * Access: WO 8774 */ 8775 MLXSW_ITEM32(reg, rlpmce, flush, 0x00, 4, 1); 8776 8777 /* reg_rlpmce_disable 8778 * LPM cache: 8779 * 0: enabled (default) 8780 * 1: disabled 8781 * Access: RW 8782 */ 8783 MLXSW_ITEM32(reg, rlpmce, disable, 0x00, 0, 1); 8784 8785 static inline void mlxsw_reg_rlpmce_pack(char *payload, bool flush, 8786 bool disable) 8787 { 8788 MLXSW_REG_ZERO(rlpmce, payload); 8789 mlxsw_reg_rlpmce_flush_set(payload, flush); 8790 mlxsw_reg_rlpmce_disable_set(payload, disable); 8791 } 8792 8793 /* Note that XLTQ, XMDR, XRMT and XRALXX register positions violate the rule 8794 * of ordering register definitions by the ID. However, XRALXX pack helpers are 8795 * using RALXX pack helpers, RALXX registers have higher IDs. 8796 * Also XMDR is using RALUE enums. XLRQ and XRMT are just put alongside with the 8797 * related registers. 8798 */ 8799 8800 /* XLTQ - XM Lookup Table Query Register 8801 * ------------------------------------- 8802 */ 8803 #define MLXSW_REG_XLTQ_ID 0x7802 8804 #define MLXSW_REG_XLTQ_LEN 0x2C 8805 8806 MLXSW_REG_DEFINE(xltq, MLXSW_REG_XLTQ_ID, MLXSW_REG_XLTQ_LEN); 8807 8808 enum mlxsw_reg_xltq_xm_device_id { 8809 MLXSW_REG_XLTQ_XM_DEVICE_ID_UNKNOWN, 8810 MLXSW_REG_XLTQ_XM_DEVICE_ID_XLT = 0xCF71, 8811 }; 8812 8813 /* reg_xltq_xm_device_id 8814 * XM device ID. 8815 * Access: RO 8816 */ 8817 MLXSW_ITEM32(reg, xltq, xm_device_id, 0x04, 0, 16); 8818 8819 /* reg_xltq_xlt_cap_ipv4_lpm 8820 * Access: RO 8821 */ 8822 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv4_lpm, 0x10, 0, 1); 8823 8824 /* reg_xltq_xlt_cap_ipv6_lpm 8825 * Access: RO 8826 */ 8827 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv6_lpm, 0x10, 1, 1); 8828 8829 /* reg_xltq_cap_xlt_entries 8830 * Number of XLT entries 8831 * Note: SW must not fill more than 80% in order to avoid overflow 8832 * Access: RO 8833 */ 8834 MLXSW_ITEM32(reg, xltq, cap_xlt_entries, 0x20, 0, 32); 8835 8836 /* reg_xltq_cap_xlt_mtable 8837 * XLT M-Table max size 8838 * Access: RO 8839 */ 8840 MLXSW_ITEM32(reg, xltq, cap_xlt_mtable, 0x24, 0, 32); 8841 8842 static inline void mlxsw_reg_xltq_pack(char *payload) 8843 { 8844 MLXSW_REG_ZERO(xltq, payload); 8845 } 8846 8847 static inline void mlxsw_reg_xltq_unpack(char *payload, u16 *xm_device_id, bool *xlt_cap_ipv4_lpm, 8848 bool *xlt_cap_ipv6_lpm, u32 *cap_xlt_entries, 8849 u32 *cap_xlt_mtable) 8850 { 8851 *xm_device_id = mlxsw_reg_xltq_xm_device_id_get(payload); 8852 *xlt_cap_ipv4_lpm = mlxsw_reg_xltq_xlt_cap_ipv4_lpm_get(payload); 8853 *xlt_cap_ipv6_lpm = mlxsw_reg_xltq_xlt_cap_ipv6_lpm_get(payload); 8854 *cap_xlt_entries = mlxsw_reg_xltq_cap_xlt_entries_get(payload); 8855 *cap_xlt_mtable = mlxsw_reg_xltq_cap_xlt_mtable_get(payload); 8856 } 8857 8858 /* XMDR - XM Direct Register 8859 * ------------------------- 8860 * The XMDR allows direct access to the XM device via the switch. 8861 * Working in synchronous mode. FW waits for response from the XLT 8862 * for each command. FW acks the XMDR accordingly. 8863 */ 8864 #define MLXSW_REG_XMDR_ID 0x7803 8865 #define MLXSW_REG_XMDR_BASE_LEN 0x20 8866 #define MLXSW_REG_XMDR_TRANS_LEN 0x80 8867 #define MLXSW_REG_XMDR_LEN (MLXSW_REG_XMDR_BASE_LEN + \ 8868 MLXSW_REG_XMDR_TRANS_LEN) 8869 8870 MLXSW_REG_DEFINE(xmdr, MLXSW_REG_XMDR_ID, MLXSW_REG_XMDR_LEN); 8871 8872 /* reg_xmdr_bulk_entry 8873 * Bulk_entry 8874 * 0: Last entry - immediate flush of XRT-cache 8875 * 1: Bulk entry - do not flush the XRT-cache 8876 * Access: OP 8877 */ 8878 MLXSW_ITEM32(reg, xmdr, bulk_entry, 0x04, 8, 1); 8879 8880 /* reg_xmdr_num_rec 8881 * Number of records for Direct access to XM 8882 * Supported: 0..4 commands (except NOP which is a filler) 8883 * 0 commands is reserved when bulk_entry = 1. 8884 * 0 commands is allowed when bulk_entry = 0 for immediate XRT-cache flush. 8885 * Access: OP 8886 */ 8887 MLXSW_ITEM32(reg, xmdr, num_rec, 0x04, 0, 4); 8888 8889 /* reg_xmdr_reply_vect 8890 * Reply Vector 8891 * Bit i for command index i+1 8892 * values per bit: 8893 * 0: failed 8894 * 1: succeeded 8895 * e.g. if commands 1, 2, 4 succeeded and command 3 failed then binary 8896 * value will be 0b1011 8897 * Access: RO 8898 */ 8899 MLXSW_ITEM_BIT_ARRAY(reg, xmdr, reply_vect, 0x08, 4, 1); 8900 8901 static inline void mlxsw_reg_xmdr_pack(char *payload, bool bulk_entry) 8902 { 8903 MLXSW_REG_ZERO(xmdr, payload); 8904 mlxsw_reg_xmdr_bulk_entry_set(payload, bulk_entry); 8905 } 8906 8907 enum mlxsw_reg_xmdr_c_cmd_id { 8908 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4 = 0x30, 8909 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6 = 0x31, 8910 }; 8911 8912 #define MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN 32 8913 #define MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN 48 8914 8915 /* reg_xmdr_c_cmd_id 8916 */ 8917 MLXSW_ITEM32(reg, xmdr_c, cmd_id, 0x00, 24, 8); 8918 8919 /* reg_xmdr_c_seq_number 8920 */ 8921 MLXSW_ITEM32(reg, xmdr_c, seq_number, 0x00, 12, 12); 8922 8923 enum mlxsw_reg_xmdr_c_ltr_op { 8924 /* Activity is set */ 8925 MLXSW_REG_XMDR_C_LTR_OP_WRITE = 0, 8926 /* There is no update mask. All fields are updated. */ 8927 MLXSW_REG_XMDR_C_LTR_OP_UPDATE = 1, 8928 MLXSW_REG_XMDR_C_LTR_OP_DELETE = 2, 8929 }; 8930 8931 /* reg_xmdr_c_ltr_op 8932 * Operation. 8933 */ 8934 MLXSW_ITEM32(reg, xmdr_c, ltr_op, 0x04, 24, 8); 8935 8936 /* reg_xmdr_c_ltr_trap_action 8937 * Trap action. 8938 * Values are defined in enum mlxsw_reg_ralue_trap_action. 8939 */ 8940 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_action, 0x04, 20, 4); 8941 8942 enum mlxsw_reg_xmdr_c_ltr_trap_id_num { 8943 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS0, 8944 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS1, 8945 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS2, 8946 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS3, 8947 }; 8948 8949 /* reg_xmdr_c_ltr_trap_id_num 8950 * Trap-ID number. 8951 */ 8952 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_id_num, 0x04, 16, 4); 8953 8954 /* reg_xmdr_c_ltr_virtual_router 8955 * Virtual Router ID. 8956 * Range is 0..cap_max_virtual_routers-1 8957 */ 8958 MLXSW_ITEM32(reg, xmdr_c, ltr_virtual_router, 0x04, 0, 16); 8959 8960 /* reg_xmdr_c_ltr_prefix_len 8961 * Number of bits in the prefix of the LPM route. 8962 */ 8963 MLXSW_ITEM32(reg, xmdr_c, ltr_prefix_len, 0x08, 24, 8); 8964 8965 /* reg_xmdr_c_ltr_bmp_len 8966 * The best match prefix length in the case that there is no match for 8967 * longer prefixes. 8968 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 8969 */ 8970 MLXSW_ITEM32(reg, xmdr_c, ltr_bmp_len, 0x08, 16, 8); 8971 8972 /* reg_xmdr_c_ltr_entry_type 8973 * Entry type. 8974 * Values are defined in enum mlxsw_reg_ralue_entry_type. 8975 */ 8976 MLXSW_ITEM32(reg, xmdr_c, ltr_entry_type, 0x08, 4, 4); 8977 8978 enum mlxsw_reg_xmdr_c_ltr_action_type { 8979 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL, 8980 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE, 8981 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME, 8982 }; 8983 8984 /* reg_xmdr_c_ltr_action_type 8985 * Action Type. 8986 */ 8987 MLXSW_ITEM32(reg, xmdr_c, ltr_action_type, 0x08, 0, 4); 8988 8989 /* reg_xmdr_c_ltr_erif 8990 * Egress Router Interface. 8991 * Only relevant in case of LOCAL action. 8992 */ 8993 MLXSW_ITEM32(reg, xmdr_c, ltr_erif, 0x10, 0, 16); 8994 8995 /* reg_xmdr_c_ltr_adjacency_index 8996 * Points to the first entry of the group-based ECMP. 8997 * Only relevant in case of REMOTE action. 8998 */ 8999 MLXSW_ITEM32(reg, xmdr_c, ltr_adjacency_index, 0x10, 0, 24); 9000 9001 #define MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC 0xFFFFFF 9002 9003 /* reg_xmdr_c_ltr_pointer_to_tunnel 9004 * Only relevant in case of IP2ME action. 9005 */ 9006 MLXSW_ITEM32(reg, xmdr_c, ltr_pointer_to_tunnel, 0x10, 0, 24); 9007 9008 /* reg_xmdr_c_ltr_ecmp_size 9009 * Amount of sequential entries starting 9010 * from the adjacency_index (the number of ECMPs). 9011 * The valid range is 1-64, 512, 1024, 2048 and 4096. 9012 * Only relevant in case of REMOTE action. 9013 */ 9014 MLXSW_ITEM32(reg, xmdr_c, ltr_ecmp_size, 0x14, 0, 32); 9015 9016 /* reg_xmdr_c_ltr_dip* 9017 * The prefix of the route or of the marker that the object of the LPM 9018 * is compared with. The most significant bits of the dip are the prefix. 9019 * The least significant bits must be '0' if the prefix_len is smaller 9020 * than 128 for IPv6 or smaller than 32 for IPv4. 9021 */ 9022 MLXSW_ITEM32(reg, xmdr_c, ltr_dip4, 0x1C, 0, 32); 9023 MLXSW_ITEM_BUF(reg, xmdr_c, ltr_dip6, 0x1C, 16); 9024 9025 static inline void 9026 mlxsw_reg_xmdr_c_ltr_pack(char *xmdr_payload, unsigned int trans_offset, 9027 enum mlxsw_reg_xmdr_c_cmd_id cmd_id, u16 seq_number, 9028 enum mlxsw_reg_xmdr_c_ltr_op op, u16 virtual_router, 9029 u8 prefix_len) 9030 { 9031 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9032 u8 num_rec = mlxsw_reg_xmdr_num_rec_get(xmdr_payload); 9033 9034 mlxsw_reg_xmdr_num_rec_set(xmdr_payload, num_rec + 1); 9035 9036 mlxsw_reg_xmdr_c_cmd_id_set(payload, cmd_id); 9037 mlxsw_reg_xmdr_c_seq_number_set(payload, seq_number); 9038 mlxsw_reg_xmdr_c_ltr_op_set(payload, op); 9039 mlxsw_reg_xmdr_c_ltr_virtual_router_set(payload, virtual_router); 9040 mlxsw_reg_xmdr_c_ltr_prefix_len_set(payload, prefix_len); 9041 mlxsw_reg_xmdr_c_ltr_entry_type_set(payload, 9042 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 9043 mlxsw_reg_xmdr_c_ltr_bmp_len_set(payload, prefix_len); 9044 } 9045 9046 static inline unsigned int 9047 mlxsw_reg_xmdr_c_ltr_pack4(char *xmdr_payload, unsigned int trans_offset, 9048 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op, 9049 u16 virtual_router, u8 prefix_len, u32 *dip) 9050 { 9051 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9052 9053 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset, 9054 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4, 9055 seq_number, op, virtual_router, prefix_len); 9056 if (dip) 9057 mlxsw_reg_xmdr_c_ltr_dip4_set(payload, *dip); 9058 return MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN; 9059 } 9060 9061 static inline unsigned int 9062 mlxsw_reg_xmdr_c_ltr_pack6(char *xmdr_payload, unsigned int trans_offset, 9063 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op, 9064 u16 virtual_router, u8 prefix_len, const void *dip) 9065 { 9066 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9067 9068 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset, 9069 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6, 9070 seq_number, op, virtual_router, prefix_len); 9071 if (dip) 9072 mlxsw_reg_xmdr_c_ltr_dip6_memcpy_to(payload, dip); 9073 return MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN; 9074 } 9075 9076 static inline void 9077 mlxsw_reg_xmdr_c_ltr_act_remote_pack(char *xmdr_payload, unsigned int trans_offset, 9078 enum mlxsw_reg_ralue_trap_action trap_action, 9079 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, 9080 u32 adjacency_index, u16 ecmp_size) 9081 { 9082 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9083 9084 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE); 9085 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action); 9086 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num); 9087 mlxsw_reg_xmdr_c_ltr_adjacency_index_set(payload, adjacency_index); 9088 mlxsw_reg_xmdr_c_ltr_ecmp_size_set(payload, ecmp_size); 9089 } 9090 9091 static inline void 9092 mlxsw_reg_xmdr_c_ltr_act_local_pack(char *xmdr_payload, unsigned int trans_offset, 9093 enum mlxsw_reg_ralue_trap_action trap_action, 9094 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, u16 erif) 9095 { 9096 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9097 9098 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL); 9099 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action); 9100 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num); 9101 mlxsw_reg_xmdr_c_ltr_erif_set(payload, erif); 9102 } 9103 9104 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char *xmdr_payload, 9105 unsigned int trans_offset) 9106 { 9107 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9108 9109 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME); 9110 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, 9111 MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC); 9112 } 9113 9114 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload, 9115 unsigned int trans_offset, 9116 u32 pointer_to_tunnel) 9117 { 9118 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9119 9120 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME); 9121 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel); 9122 } 9123 9124 /* XRMT - XM Router M Table Register 9125 * --------------------------------- 9126 * The XRMT configures the M-Table for the XLT-LPM. 9127 */ 9128 #define MLXSW_REG_XRMT_ID 0x7810 9129 #define MLXSW_REG_XRMT_LEN 0x14 9130 9131 MLXSW_REG_DEFINE(xrmt, MLXSW_REG_XRMT_ID, MLXSW_REG_XRMT_LEN); 9132 9133 /* reg_xrmt_index 9134 * Index in M-Table. 9135 * Range 0..cap_xlt_mtable-1 9136 * Access: Index 9137 */ 9138 MLXSW_ITEM32(reg, xrmt, index, 0x04, 0, 20); 9139 9140 /* reg_xrmt_l0_val 9141 * Access: RW 9142 */ 9143 MLXSW_ITEM32(reg, xrmt, l0_val, 0x10, 24, 8); 9144 9145 static inline void mlxsw_reg_xrmt_pack(char *payload, u32 index, u8 l0_val) 9146 { 9147 MLXSW_REG_ZERO(xrmt, payload); 9148 mlxsw_reg_xrmt_index_set(payload, index); 9149 mlxsw_reg_xrmt_l0_val_set(payload, l0_val); 9150 } 9151 9152 /* XRALTA - XM Router Algorithmic LPM Tree Allocation Register 9153 * ----------------------------------------------------------- 9154 * The XRALTA is used to allocate the XLT LPM trees. 9155 * 9156 * This register embeds original RALTA register. 9157 */ 9158 #define MLXSW_REG_XRALTA_ID 0x7811 9159 #define MLXSW_REG_XRALTA_LEN 0x08 9160 #define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04 9161 9162 MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN); 9163 9164 static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc, 9165 enum mlxsw_reg_ralxx_protocol protocol, 9166 u8 tree_id) 9167 { 9168 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET; 9169 9170 MLXSW_REG_ZERO(xralta, payload); 9171 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id); 9172 } 9173 9174 /* XRALST - XM Router Algorithmic LPM Structure Tree Register 9175 * ---------------------------------------------------------- 9176 * The XRALST is used to set and query the structure of an XLT LPM tree. 9177 * 9178 * This register embeds original RALST register. 9179 */ 9180 #define MLXSW_REG_XRALST_ID 0x7812 9181 #define MLXSW_REG_XRALST_LEN 0x108 9182 #define MLXSW_REG_XRALST_RALST_OFFSET 0x04 9183 9184 MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN); 9185 9186 static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id) 9187 { 9188 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 9189 9190 MLXSW_REG_ZERO(xralst, payload); 9191 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id); 9192 } 9193 9194 static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number, 9195 u8 left_child_bin, 9196 u8 right_child_bin) 9197 { 9198 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 9199 9200 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin, 9201 right_child_bin); 9202 } 9203 9204 /* XRALTB - XM Router Algorithmic LPM Tree Binding Register 9205 * -------------------------------------------------------- 9206 * The XRALTB register is used to bind virtual router and protocol 9207 * to an allocated LPM tree. 9208 * 9209 * This register embeds original RALTB register. 9210 */ 9211 #define MLXSW_REG_XRALTB_ID 0x7813 9212 #define MLXSW_REG_XRALTB_LEN 0x08 9213 #define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04 9214 9215 MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN); 9216 9217 static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router, 9218 enum mlxsw_reg_ralxx_protocol protocol, 9219 u8 tree_id) 9220 { 9221 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET; 9222 9223 MLXSW_REG_ZERO(xraltb, payload); 9224 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id); 9225 } 9226 9227 /* MFCR - Management Fan Control Register 9228 * -------------------------------------- 9229 * This register controls the settings of the Fan Speed PWM mechanism. 9230 */ 9231 #define MLXSW_REG_MFCR_ID 0x9001 9232 #define MLXSW_REG_MFCR_LEN 0x08 9233 9234 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9235 9236 enum mlxsw_reg_mfcr_pwm_frequency { 9237 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9238 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9239 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9240 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9241 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9242 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9243 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9244 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9245 }; 9246 9247 /* reg_mfcr_pwm_frequency 9248 * Controls the frequency of the PWM signal. 9249 * Access: RW 9250 */ 9251 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9252 9253 #define MLXSW_MFCR_TACHOS_MAX 10 9254 9255 /* reg_mfcr_tacho_active 9256 * Indicates which of the tachometer is active (bit per tachometer). 9257 * Access: RO 9258 */ 9259 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9260 9261 #define MLXSW_MFCR_PWMS_MAX 5 9262 9263 /* reg_mfcr_pwm_active 9264 * Indicates which of the PWM control is active (bit per PWM). 9265 * Access: RO 9266 */ 9267 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9268 9269 static inline void 9270 mlxsw_reg_mfcr_pack(char *payload, 9271 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9272 { 9273 MLXSW_REG_ZERO(mfcr, payload); 9274 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9275 } 9276 9277 static inline void 9278 mlxsw_reg_mfcr_unpack(char *payload, 9279 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9280 u16 *p_tacho_active, u8 *p_pwm_active) 9281 { 9282 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9283 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9284 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9285 } 9286 9287 /* MFSC - Management Fan Speed Control Register 9288 * -------------------------------------------- 9289 * This register controls the settings of the Fan Speed PWM mechanism. 9290 */ 9291 #define MLXSW_REG_MFSC_ID 0x9002 9292 #define MLXSW_REG_MFSC_LEN 0x08 9293 9294 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9295 9296 /* reg_mfsc_pwm 9297 * Fan pwm to control / monitor. 9298 * Access: Index 9299 */ 9300 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9301 9302 /* reg_mfsc_pwm_duty_cycle 9303 * Controls the duty cycle of the PWM. Value range from 0..255 to 9304 * represent duty cycle of 0%...100%. 9305 * Access: RW 9306 */ 9307 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9308 9309 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9310 u8 pwm_duty_cycle) 9311 { 9312 MLXSW_REG_ZERO(mfsc, payload); 9313 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9314 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9315 } 9316 9317 /* MFSM - Management Fan Speed Measurement 9318 * --------------------------------------- 9319 * This register controls the settings of the Tacho measurements and 9320 * enables reading the Tachometer measurements. 9321 */ 9322 #define MLXSW_REG_MFSM_ID 0x9003 9323 #define MLXSW_REG_MFSM_LEN 0x08 9324 9325 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9326 9327 /* reg_mfsm_tacho 9328 * Fan tachometer index. 9329 * Access: Index 9330 */ 9331 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9332 9333 /* reg_mfsm_rpm 9334 * Fan speed (round per minute). 9335 * Access: RO 9336 */ 9337 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9338 9339 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9340 { 9341 MLXSW_REG_ZERO(mfsm, payload); 9342 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9343 } 9344 9345 /* MFSL - Management Fan Speed Limit Register 9346 * ------------------------------------------ 9347 * The Fan Speed Limit register is used to configure the fan speed 9348 * event / interrupt notification mechanism. Fan speed threshold are 9349 * defined for both under-speed and over-speed. 9350 */ 9351 #define MLXSW_REG_MFSL_ID 0x9004 9352 #define MLXSW_REG_MFSL_LEN 0x0C 9353 9354 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9355 9356 /* reg_mfsl_tacho 9357 * Fan tachometer index. 9358 * Access: Index 9359 */ 9360 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9361 9362 /* reg_mfsl_tach_min 9363 * Tachometer minimum value (minimum RPM). 9364 * Access: RW 9365 */ 9366 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9367 9368 /* reg_mfsl_tach_max 9369 * Tachometer maximum value (maximum RPM). 9370 * Access: RW 9371 */ 9372 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9373 9374 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9375 u16 tach_min, u16 tach_max) 9376 { 9377 MLXSW_REG_ZERO(mfsl, payload); 9378 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9379 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9380 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9381 } 9382 9383 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9384 u16 *p_tach_min, u16 *p_tach_max) 9385 { 9386 if (p_tach_min) 9387 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9388 9389 if (p_tach_max) 9390 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9391 } 9392 9393 /* FORE - Fan Out of Range Event Register 9394 * -------------------------------------- 9395 * This register reports the status of the controlled fans compared to the 9396 * range defined by the MFSL register. 9397 */ 9398 #define MLXSW_REG_FORE_ID 0x9007 9399 #define MLXSW_REG_FORE_LEN 0x0C 9400 9401 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9402 9403 /* fan_under_limit 9404 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9405 * to a single tachometer and indicates the specific tachometer reading is 9406 * below the threshold. 9407 * Access: RO 9408 */ 9409 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9410 9411 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9412 bool *fault) 9413 { 9414 u16 limit; 9415 9416 if (fault) { 9417 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9418 *fault = limit & BIT(tacho); 9419 } 9420 } 9421 9422 /* MTCAP - Management Temperature Capabilities 9423 * ------------------------------------------- 9424 * This register exposes the capabilities of the device and 9425 * system temperature sensing. 9426 */ 9427 #define MLXSW_REG_MTCAP_ID 0x9009 9428 #define MLXSW_REG_MTCAP_LEN 0x08 9429 9430 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9431 9432 /* reg_mtcap_sensor_count 9433 * Number of sensors supported by the device. 9434 * This includes the QSFP module sensors (if exists in the QSFP module). 9435 * Access: RO 9436 */ 9437 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9438 9439 /* MTMP - Management Temperature 9440 * ----------------------------- 9441 * This register controls the settings of the temperature measurements 9442 * and enables reading the temperature measurements. Note that temperature 9443 * is in 0.125 degrees Celsius. 9444 */ 9445 #define MLXSW_REG_MTMP_ID 0x900A 9446 #define MLXSW_REG_MTMP_LEN 0x20 9447 9448 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9449 9450 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9451 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9452 /* reg_mtmp_sensor_index 9453 * Sensors index to access. 9454 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9455 * (module 0 is mapped to sensor_index 64). 9456 * Access: Index 9457 */ 9458 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9459 9460 /* Convert to milli degrees Celsius */ 9461 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9462 ((v_) >= 0) ? ((v_) * 125) : \ 9463 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9464 * 125)); }) 9465 9466 /* reg_mtmp_max_operational_temperature 9467 * The highest temperature in the nominal operational range. Reading is in 9468 * 0.125 Celsius degrees units. 9469 * In case of module this is SFF critical temperature threshold. 9470 * Access: RO 9471 */ 9472 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9473 9474 /* reg_mtmp_temperature 9475 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9476 * degrees units. 9477 * Access: RO 9478 */ 9479 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9480 9481 /* reg_mtmp_mte 9482 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9483 * Access: RW 9484 */ 9485 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9486 9487 /* reg_mtmp_mtr 9488 * Max Temperature Reset - clears the value of the max temperature register. 9489 * Access: WO 9490 */ 9491 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9492 9493 /* reg_mtmp_max_temperature 9494 * The highest measured temperature from the sensor. 9495 * When the bit mte is cleared, the field max_temperature is reserved. 9496 * Access: RO 9497 */ 9498 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9499 9500 /* reg_mtmp_tee 9501 * Temperature Event Enable. 9502 * 0 - Do not generate event 9503 * 1 - Generate event 9504 * 2 - Generate single event 9505 * Access: RW 9506 */ 9507 9508 enum mlxsw_reg_mtmp_tee { 9509 MLXSW_REG_MTMP_TEE_NO_EVENT, 9510 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9511 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9512 }; 9513 9514 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9515 9516 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9517 9518 /* reg_mtmp_temperature_threshold_hi 9519 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9520 * Access: RW 9521 */ 9522 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9523 9524 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9525 /* reg_mtmp_temperature_threshold_lo 9526 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9527 * Access: RW 9528 */ 9529 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9530 9531 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9532 9533 /* reg_mtmp_sensor_name 9534 * Sensor Name 9535 * Access: RO 9536 */ 9537 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9538 9539 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 9540 bool max_temp_enable, 9541 bool max_temp_reset) 9542 { 9543 MLXSW_REG_ZERO(mtmp, payload); 9544 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9545 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9546 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9547 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9548 MLXSW_REG_MTMP_THRESH_HI); 9549 } 9550 9551 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9552 int *p_max_temp, int *p_temp_hi, 9553 int *p_max_oper_temp, 9554 char *sensor_name) 9555 { 9556 s16 temp; 9557 9558 if (p_temp) { 9559 temp = mlxsw_reg_mtmp_temperature_get(payload); 9560 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9561 } 9562 if (p_max_temp) { 9563 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9564 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9565 } 9566 if (p_temp_hi) { 9567 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9568 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9569 } 9570 if (p_max_oper_temp) { 9571 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9572 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9573 } 9574 if (sensor_name) 9575 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9576 } 9577 9578 /* MTWE - Management Temperature Warning Event 9579 * ------------------------------------------- 9580 * This register is used for over temperature warning. 9581 */ 9582 #define MLXSW_REG_MTWE_ID 0x900B 9583 #define MLXSW_REG_MTWE_LEN 0x10 9584 9585 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9586 9587 /* reg_mtwe_sensor_warning 9588 * Bit vector indicating which of the sensor reading is above threshold. 9589 * Address 00h bit31 is sensor_warning[127]. 9590 * Address 0Ch bit0 is sensor_warning[0]. 9591 * Access: RO 9592 */ 9593 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9594 9595 /* MTBR - Management Temperature Bulk Register 9596 * ------------------------------------------- 9597 * This register is used for bulk temperature reading. 9598 */ 9599 #define MLXSW_REG_MTBR_ID 0x900F 9600 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9601 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9602 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9603 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9604 MLXSW_REG_MTBR_REC_LEN * \ 9605 MLXSW_REG_MTBR_REC_MAX_COUNT) 9606 9607 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9608 9609 /* reg_mtbr_base_sensor_index 9610 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9611 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9612 * Access: Index 9613 */ 9614 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9615 9616 /* reg_mtbr_num_rec 9617 * Request: Number of records to read 9618 * Response: Number of records read 9619 * See above description for more details. 9620 * Range 1..255 9621 * Access: RW 9622 */ 9623 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9624 9625 /* reg_mtbr_rec_max_temp 9626 * The highest measured temperature from the sensor. 9627 * When the bit mte is cleared, the field max_temperature is reserved. 9628 * Access: RO 9629 */ 9630 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9631 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9632 9633 /* reg_mtbr_rec_temp 9634 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9635 * degrees units. 9636 * Access: RO 9637 */ 9638 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9639 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9640 9641 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 9642 u8 num_rec) 9643 { 9644 MLXSW_REG_ZERO(mtbr, payload); 9645 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9646 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9647 } 9648 9649 /* Error codes from temperatute reading */ 9650 enum mlxsw_reg_mtbr_temp_status { 9651 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9652 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9653 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9654 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9655 }; 9656 9657 /* Base index for reading modules temperature */ 9658 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9659 9660 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9661 u16 *p_temp, u16 *p_max_temp) 9662 { 9663 if (p_temp) 9664 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9665 if (p_max_temp) 9666 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9667 } 9668 9669 /* MCIA - Management Cable Info Access 9670 * ----------------------------------- 9671 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9672 */ 9673 9674 #define MLXSW_REG_MCIA_ID 0x9014 9675 #define MLXSW_REG_MCIA_LEN 0x40 9676 9677 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9678 9679 /* reg_mcia_l 9680 * Lock bit. Setting this bit will lock the access to the specific 9681 * cable. Used for updating a full page in a cable EPROM. Any access 9682 * other then subsequence writes will fail while the port is locked. 9683 * Access: RW 9684 */ 9685 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9686 9687 /* reg_mcia_module 9688 * Module number. 9689 * Access: Index 9690 */ 9691 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9692 9693 enum { 9694 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9695 /* No response from module's EEPROM. */ 9696 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9697 /* Module type not supported by the device. */ 9698 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9699 /* No module present indication. */ 9700 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9701 /* Error occurred while trying to access module's EEPROM using I2C. */ 9702 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9703 /* Module is disabled. */ 9704 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9705 }; 9706 9707 /* reg_mcia_status 9708 * Module status. 9709 * Access: RO 9710 */ 9711 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9712 9713 /* reg_mcia_i2c_device_address 9714 * I2C device address. 9715 * Access: RW 9716 */ 9717 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9718 9719 /* reg_mcia_page_number 9720 * Page number. 9721 * Access: RW 9722 */ 9723 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9724 9725 /* reg_mcia_device_address 9726 * Device address. 9727 * Access: RW 9728 */ 9729 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9730 9731 /* reg_mcia_bank_number 9732 * Bank number. 9733 * Access: Index 9734 */ 9735 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9736 9737 /* reg_mcia_size 9738 * Number of bytes to read/write (up to 48 bytes). 9739 * Access: RW 9740 */ 9741 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9742 9743 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9744 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9745 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9746 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9747 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9748 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9749 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9750 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9751 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9752 #define MLXSW_REG_MCIA_PAGE0_LO 0 9753 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9754 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9755 9756 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9757 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9758 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9759 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9760 }; 9761 9762 enum mlxsw_reg_mcia_eeprom_module_info_id { 9763 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9764 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9765 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9766 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9767 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9768 }; 9769 9770 enum mlxsw_reg_mcia_eeprom_module_info { 9771 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9772 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9773 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9774 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9775 }; 9776 9777 /* reg_mcia_eeprom 9778 * Bytes to read/write. 9779 * Access: RW 9780 */ 9781 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9782 9783 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9784 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9785 * on offset 384 through 511, page 3 - on offset 512 through 639. 9786 */ 9787 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9788 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9789 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9790 9791 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 9792 u8 page_number, u16 device_addr, 9793 u8 size, u8 i2c_device_addr) 9794 { 9795 MLXSW_REG_ZERO(mcia, payload); 9796 mlxsw_reg_mcia_module_set(payload, module); 9797 mlxsw_reg_mcia_l_set(payload, lock); 9798 mlxsw_reg_mcia_page_number_set(payload, page_number); 9799 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9800 mlxsw_reg_mcia_size_set(payload, size); 9801 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9802 } 9803 9804 /* MPAT - Monitoring Port Analyzer Table 9805 * ------------------------------------- 9806 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9807 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9808 */ 9809 #define MLXSW_REG_MPAT_ID 0x901A 9810 #define MLXSW_REG_MPAT_LEN 0x78 9811 9812 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9813 9814 /* reg_mpat_pa_id 9815 * Port Analyzer ID. 9816 * Access: Index 9817 */ 9818 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9819 9820 /* reg_mpat_session_id 9821 * Mirror Session ID. 9822 * Used for MIRROR_SESSION<i> trap. 9823 * Access: RW 9824 */ 9825 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9826 9827 /* reg_mpat_system_port 9828 * A unique port identifier for the final destination of the packet. 9829 * Access: RW 9830 */ 9831 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9832 9833 /* reg_mpat_e 9834 * Enable. Indicating the Port Analyzer is enabled. 9835 * Access: RW 9836 */ 9837 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9838 9839 /* reg_mpat_qos 9840 * Quality Of Service Mode. 9841 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9842 * PCP, DEI, DSCP or VL) are configured. 9843 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9844 * same as in the original packet that has triggered the mirroring. For 9845 * SPAN also the pcp,dei are maintained. 9846 * Access: RW 9847 */ 9848 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9849 9850 /* reg_mpat_be 9851 * Best effort mode. Indicates mirroring traffic should not cause packet 9852 * drop or back pressure, but will discard the mirrored packets. Mirrored 9853 * packets will be forwarded on a best effort manner. 9854 * 0: Do not discard mirrored packets 9855 * 1: Discard mirrored packets if causing congestion 9856 * Access: RW 9857 */ 9858 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9859 9860 enum mlxsw_reg_mpat_span_type { 9861 /* Local SPAN Ethernet. 9862 * The original packet is not encapsulated. 9863 */ 9864 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9865 9866 /* Remote SPAN Ethernet VLAN. 9867 * The packet is forwarded to the monitoring port on the monitoring 9868 * VLAN. 9869 */ 9870 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9871 9872 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9873 * The packet is encapsulated with GRE header. 9874 */ 9875 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9876 }; 9877 9878 /* reg_mpat_span_type 9879 * SPAN type. 9880 * Access: RW 9881 */ 9882 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9883 9884 /* reg_mpat_pide 9885 * Policer enable. 9886 * Access: RW 9887 */ 9888 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9889 9890 /* reg_mpat_pid 9891 * Policer ID. 9892 * Access: RW 9893 */ 9894 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9895 9896 /* Remote SPAN - Ethernet VLAN 9897 * - - - - - - - - - - - - - - 9898 */ 9899 9900 /* reg_mpat_eth_rspan_vid 9901 * Encapsulation header VLAN ID. 9902 * Access: RW 9903 */ 9904 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9905 9906 /* Encapsulated Remote SPAN - Ethernet L2 9907 * - - - - - - - - - - - - - - - - - - - 9908 */ 9909 9910 enum mlxsw_reg_mpat_eth_rspan_version { 9911 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9912 }; 9913 9914 /* reg_mpat_eth_rspan_version 9915 * RSPAN mirror header version. 9916 * Access: RW 9917 */ 9918 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9919 9920 /* reg_mpat_eth_rspan_mac 9921 * Destination MAC address. 9922 * Access: RW 9923 */ 9924 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9925 9926 /* reg_mpat_eth_rspan_tp 9927 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9928 * Access: RW 9929 */ 9930 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9931 9932 /* Encapsulated Remote SPAN - Ethernet L3 9933 * - - - - - - - - - - - - - - - - - - - 9934 */ 9935 9936 enum mlxsw_reg_mpat_eth_rspan_protocol { 9937 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9938 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9939 }; 9940 9941 /* reg_mpat_eth_rspan_protocol 9942 * SPAN encapsulation protocol. 9943 * Access: RW 9944 */ 9945 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9946 9947 /* reg_mpat_eth_rspan_ttl 9948 * Encapsulation header Time-to-Live/HopLimit. 9949 * Access: RW 9950 */ 9951 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9952 9953 /* reg_mpat_eth_rspan_smac 9954 * Source MAC address 9955 * Access: RW 9956 */ 9957 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9958 9959 /* reg_mpat_eth_rspan_dip* 9960 * Destination IP address. The IP version is configured by protocol. 9961 * Access: RW 9962 */ 9963 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9964 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9965 9966 /* reg_mpat_eth_rspan_sip* 9967 * Source IP address. The IP version is configured by protocol. 9968 * Access: RW 9969 */ 9970 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9971 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9972 9973 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9974 u16 system_port, bool e, 9975 enum mlxsw_reg_mpat_span_type span_type) 9976 { 9977 MLXSW_REG_ZERO(mpat, payload); 9978 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9979 mlxsw_reg_mpat_system_port_set(payload, system_port); 9980 mlxsw_reg_mpat_e_set(payload, e); 9981 mlxsw_reg_mpat_qos_set(payload, 1); 9982 mlxsw_reg_mpat_be_set(payload, 1); 9983 mlxsw_reg_mpat_span_type_set(payload, span_type); 9984 } 9985 9986 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9987 { 9988 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9989 } 9990 9991 static inline void 9992 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9993 enum mlxsw_reg_mpat_eth_rspan_version version, 9994 const char *mac, 9995 bool tp) 9996 { 9997 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9998 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9999 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 10000 } 10001 10002 static inline void 10003 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 10004 const char *smac, 10005 u32 sip, u32 dip) 10006 { 10007 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10008 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10009 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10010 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 10011 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 10012 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 10013 } 10014 10015 static inline void 10016 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 10017 const char *smac, 10018 struct in6_addr sip, struct in6_addr dip) 10019 { 10020 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10021 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10022 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10023 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 10024 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 10025 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 10026 } 10027 10028 /* MPAR - Monitoring Port Analyzer Register 10029 * ---------------------------------------- 10030 * MPAR register is used to query and configure the port analyzer port mirroring 10031 * properties. 10032 */ 10033 #define MLXSW_REG_MPAR_ID 0x901B 10034 #define MLXSW_REG_MPAR_LEN 0x0C 10035 10036 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 10037 10038 /* reg_mpar_local_port 10039 * The local port to mirror the packets from. 10040 * Access: Index 10041 */ 10042 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 10043 10044 enum mlxsw_reg_mpar_i_e { 10045 MLXSW_REG_MPAR_TYPE_EGRESS, 10046 MLXSW_REG_MPAR_TYPE_INGRESS, 10047 }; 10048 10049 /* reg_mpar_i_e 10050 * Ingress/Egress 10051 * Access: Index 10052 */ 10053 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10054 10055 /* reg_mpar_enable 10056 * Enable mirroring 10057 * By default, port mirroring is disabled for all ports. 10058 * Access: RW 10059 */ 10060 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10061 10062 /* reg_mpar_pa_id 10063 * Port Analyzer ID. 10064 * Access: RW 10065 */ 10066 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10067 10068 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10069 10070 /* reg_mpar_probability_rate 10071 * Sampling rate. 10072 * Valid values are: 1 to 3.5*10^9 10073 * Value of 1 means "sample all". Default is 1. 10074 * Reserved when Spectrum-1. 10075 * Access: RW 10076 */ 10077 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10078 10079 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 10080 enum mlxsw_reg_mpar_i_e i_e, 10081 bool enable, u8 pa_id, 10082 u32 probability_rate) 10083 { 10084 MLXSW_REG_ZERO(mpar, payload); 10085 mlxsw_reg_mpar_local_port_set(payload, local_port); 10086 mlxsw_reg_mpar_enable_set(payload, enable); 10087 mlxsw_reg_mpar_i_e_set(payload, i_e); 10088 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10089 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10090 } 10091 10092 /* MGIR - Management General Information Register 10093 * ---------------------------------------------- 10094 * MGIR register allows software to query the hardware and firmware general 10095 * information. 10096 */ 10097 #define MLXSW_REG_MGIR_ID 0x9020 10098 #define MLXSW_REG_MGIR_LEN 0x9C 10099 10100 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10101 10102 /* reg_mgir_hw_info_device_hw_revision 10103 * Access: RO 10104 */ 10105 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10106 10107 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10108 10109 /* reg_mgir_fw_info_psid 10110 * PSID (ASCII string). 10111 * Access: RO 10112 */ 10113 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10114 10115 /* reg_mgir_fw_info_extended_major 10116 * Access: RO 10117 */ 10118 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10119 10120 /* reg_mgir_fw_info_extended_minor 10121 * Access: RO 10122 */ 10123 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10124 10125 /* reg_mgir_fw_info_extended_sub_minor 10126 * Access: RO 10127 */ 10128 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10129 10130 static inline void mlxsw_reg_mgir_pack(char *payload) 10131 { 10132 MLXSW_REG_ZERO(mgir, payload); 10133 } 10134 10135 static inline void 10136 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10137 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10138 { 10139 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10140 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10141 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10142 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10143 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10144 } 10145 10146 /* MRSR - Management Reset and Shutdown Register 10147 * --------------------------------------------- 10148 * MRSR register is used to reset or shutdown the switch or 10149 * the entire system (when applicable). 10150 */ 10151 #define MLXSW_REG_MRSR_ID 0x9023 10152 #define MLXSW_REG_MRSR_LEN 0x08 10153 10154 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10155 10156 /* reg_mrsr_command 10157 * Reset/shutdown command 10158 * 0 - do nothing 10159 * 1 - software reset 10160 * Access: WO 10161 */ 10162 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10163 10164 static inline void mlxsw_reg_mrsr_pack(char *payload) 10165 { 10166 MLXSW_REG_ZERO(mrsr, payload); 10167 mlxsw_reg_mrsr_command_set(payload, 1); 10168 } 10169 10170 /* MLCR - Management LED Control Register 10171 * -------------------------------------- 10172 * Controls the system LEDs. 10173 */ 10174 #define MLXSW_REG_MLCR_ID 0x902B 10175 #define MLXSW_REG_MLCR_LEN 0x0C 10176 10177 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10178 10179 /* reg_mlcr_local_port 10180 * Local port number. 10181 * Access: RW 10182 */ 10183 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 10184 10185 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10186 10187 /* reg_mlcr_beacon_duration 10188 * Duration of the beacon to be active, in seconds. 10189 * 0x0 - Will turn off the beacon. 10190 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10191 * Access: RW 10192 */ 10193 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10194 10195 /* reg_mlcr_beacon_remain 10196 * Remaining duration of the beacon, in seconds. 10197 * 0xFFFF indicates an infinite amount of time. 10198 * Access: RO 10199 */ 10200 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10201 10202 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 10203 bool active) 10204 { 10205 MLXSW_REG_ZERO(mlcr, payload); 10206 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10207 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10208 MLXSW_REG_MLCR_DURATION_MAX : 0); 10209 } 10210 10211 /* MTPPS - Management Pulse Per Second Register 10212 * -------------------------------------------- 10213 * This register provides the device PPS capabilities, configure the PPS in and 10214 * out modules and holds the PPS in time stamp. 10215 */ 10216 #define MLXSW_REG_MTPPS_ID 0x9053 10217 #define MLXSW_REG_MTPPS_LEN 0x3C 10218 10219 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10220 10221 /* reg_mtpps_enable 10222 * Enables the PPS functionality the specific pin. 10223 * A boolean variable. 10224 * Access: RW 10225 */ 10226 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10227 10228 enum mlxsw_reg_mtpps_pin_mode { 10229 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10230 }; 10231 10232 /* reg_mtpps_pin_mode 10233 * Pin mode to be used. The mode must comply with the supported modes of the 10234 * requested pin. 10235 * Access: RW 10236 */ 10237 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10238 10239 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10240 10241 /* reg_mtpps_pin 10242 * Pin to be configured or queried out of the supported pins. 10243 * Access: Index 10244 */ 10245 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10246 10247 /* reg_mtpps_time_stamp 10248 * When pin_mode = pps_in, the latched device time when it was triggered from 10249 * the external GPIO pin. 10250 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10251 * time to generate next output signal. 10252 * Time is in units of device clock. 10253 * Access: RW 10254 */ 10255 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10256 10257 static inline void 10258 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10259 { 10260 MLXSW_REG_ZERO(mtpps, payload); 10261 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10262 mlxsw_reg_mtpps_pin_mode_set(payload, 10263 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10264 mlxsw_reg_mtpps_enable_set(payload, true); 10265 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10266 } 10267 10268 /* MTUTC - Management UTC Register 10269 * ------------------------------- 10270 * Configures the HW UTC counter. 10271 */ 10272 #define MLXSW_REG_MTUTC_ID 0x9055 10273 #define MLXSW_REG_MTUTC_LEN 0x1C 10274 10275 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10276 10277 enum mlxsw_reg_mtutc_operation { 10278 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10279 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10280 }; 10281 10282 /* reg_mtutc_operation 10283 * Operation. 10284 * Access: OP 10285 */ 10286 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10287 10288 /* reg_mtutc_freq_adjustment 10289 * Frequency adjustment: Every PPS the HW frequency will be 10290 * adjusted by this value. Units of HW clock, where HW counts 10291 * 10^9 HW clocks for 1 HW second. 10292 * Access: RW 10293 */ 10294 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10295 10296 /* reg_mtutc_utc_sec 10297 * UTC seconds. 10298 * Access: WO 10299 */ 10300 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10301 10302 static inline void 10303 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10304 u32 freq_adj, u32 utc_sec) 10305 { 10306 MLXSW_REG_ZERO(mtutc, payload); 10307 mlxsw_reg_mtutc_operation_set(payload, oper); 10308 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10309 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10310 } 10311 10312 /* MCQI - Management Component Query Information 10313 * --------------------------------------------- 10314 * This register allows querying information about firmware components. 10315 */ 10316 #define MLXSW_REG_MCQI_ID 0x9061 10317 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10318 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10319 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10320 10321 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10322 10323 /* reg_mcqi_component_index 10324 * Index of the accessed component. 10325 * Access: Index 10326 */ 10327 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10328 10329 enum mlxfw_reg_mcqi_info_type { 10330 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10331 }; 10332 10333 /* reg_mcqi_info_type 10334 * Component properties set. 10335 * Access: RW 10336 */ 10337 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10338 10339 /* reg_mcqi_offset 10340 * The requested/returned data offset from the section start, given in bytes. 10341 * Must be DWORD aligned. 10342 * Access: RW 10343 */ 10344 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10345 10346 /* reg_mcqi_data_size 10347 * The requested/returned data size, given in bytes. If data_size is not DWORD 10348 * aligned, the last bytes are zero padded. 10349 * Access: RW 10350 */ 10351 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10352 10353 /* reg_mcqi_cap_max_component_size 10354 * Maximum size for this component, given in bytes. 10355 * Access: RO 10356 */ 10357 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10358 10359 /* reg_mcqi_cap_log_mcda_word_size 10360 * Log 2 of the access word size in bytes. Read and write access must be aligned 10361 * to the word size. Write access must be done for an integer number of words. 10362 * Access: RO 10363 */ 10364 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10365 10366 /* reg_mcqi_cap_mcda_max_write_size 10367 * Maximal write size for MCDA register 10368 * Access: RO 10369 */ 10370 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10371 10372 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10373 { 10374 MLXSW_REG_ZERO(mcqi, payload); 10375 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10376 mlxsw_reg_mcqi_info_type_set(payload, 10377 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10378 mlxsw_reg_mcqi_offset_set(payload, 0); 10379 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10380 } 10381 10382 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10383 u32 *p_cap_max_component_size, 10384 u8 *p_cap_log_mcda_word_size, 10385 u16 *p_cap_mcda_max_write_size) 10386 { 10387 *p_cap_max_component_size = 10388 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10389 *p_cap_log_mcda_word_size = 10390 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10391 *p_cap_mcda_max_write_size = 10392 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10393 } 10394 10395 /* MCC - Management Component Control 10396 * ---------------------------------- 10397 * Controls the firmware component and updates the FSM. 10398 */ 10399 #define MLXSW_REG_MCC_ID 0x9062 10400 #define MLXSW_REG_MCC_LEN 0x1C 10401 10402 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10403 10404 enum mlxsw_reg_mcc_instruction { 10405 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10406 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10407 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10408 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10409 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10410 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10411 }; 10412 10413 /* reg_mcc_instruction 10414 * Command to be executed by the FSM. 10415 * Applicable for write operation only. 10416 * Access: RW 10417 */ 10418 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10419 10420 /* reg_mcc_component_index 10421 * Index of the accessed component. Applicable only for commands that 10422 * refer to components. Otherwise, this field is reserved. 10423 * Access: Index 10424 */ 10425 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10426 10427 /* reg_mcc_update_handle 10428 * Token representing the current flow executed by the FSM. 10429 * Access: WO 10430 */ 10431 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10432 10433 /* reg_mcc_error_code 10434 * Indicates the successful completion of the instruction, or the reason it 10435 * failed 10436 * Access: RO 10437 */ 10438 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10439 10440 /* reg_mcc_control_state 10441 * Current FSM state 10442 * Access: RO 10443 */ 10444 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10445 10446 /* reg_mcc_component_size 10447 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10448 * the size may shorten the update time. Value 0x0 means that size is 10449 * unspecified. 10450 * Access: WO 10451 */ 10452 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10453 10454 static inline void mlxsw_reg_mcc_pack(char *payload, 10455 enum mlxsw_reg_mcc_instruction instr, 10456 u16 component_index, u32 update_handle, 10457 u32 component_size) 10458 { 10459 MLXSW_REG_ZERO(mcc, payload); 10460 mlxsw_reg_mcc_instruction_set(payload, instr); 10461 mlxsw_reg_mcc_component_index_set(payload, component_index); 10462 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10463 mlxsw_reg_mcc_component_size_set(payload, component_size); 10464 } 10465 10466 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10467 u8 *p_error_code, u8 *p_control_state) 10468 { 10469 if (p_update_handle) 10470 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10471 if (p_error_code) 10472 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10473 if (p_control_state) 10474 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10475 } 10476 10477 /* MCDA - Management Component Data Access 10478 * --------------------------------------- 10479 * This register allows reading and writing a firmware component. 10480 */ 10481 #define MLXSW_REG_MCDA_ID 0x9063 10482 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10483 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10484 #define MLXSW_REG_MCDA_LEN \ 10485 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10486 10487 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10488 10489 /* reg_mcda_update_handle 10490 * Token representing the current flow executed by the FSM. 10491 * Access: RW 10492 */ 10493 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10494 10495 /* reg_mcda_offset 10496 * Offset of accessed address relative to component start. Accesses must be in 10497 * accordance to log_mcda_word_size in MCQI reg. 10498 * Access: RW 10499 */ 10500 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10501 10502 /* reg_mcda_size 10503 * Size of the data accessed, given in bytes. 10504 * Access: RW 10505 */ 10506 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10507 10508 /* reg_mcda_data 10509 * Data block accessed. 10510 * Access: RW 10511 */ 10512 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10513 10514 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10515 u32 offset, u16 size, u8 *data) 10516 { 10517 int i; 10518 10519 MLXSW_REG_ZERO(mcda, payload); 10520 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10521 mlxsw_reg_mcda_offset_set(payload, offset); 10522 mlxsw_reg_mcda_size_set(payload, size); 10523 10524 for (i = 0; i < size / 4; i++) 10525 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10526 } 10527 10528 /* MPSC - Monitoring Packet Sampling Configuration Register 10529 * -------------------------------------------------------- 10530 * MPSC Register is used to configure the Packet Sampling mechanism. 10531 */ 10532 #define MLXSW_REG_MPSC_ID 0x9080 10533 #define MLXSW_REG_MPSC_LEN 0x1C 10534 10535 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10536 10537 /* reg_mpsc_local_port 10538 * Local port number 10539 * Not supported for CPU port 10540 * Access: Index 10541 */ 10542 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 10543 10544 /* reg_mpsc_e 10545 * Enable sampling on port local_port 10546 * Access: RW 10547 */ 10548 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10549 10550 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10551 10552 /* reg_mpsc_rate 10553 * Sampling rate = 1 out of rate packets (with randomization around 10554 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10555 * Access: RW 10556 */ 10557 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10558 10559 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 10560 u32 rate) 10561 { 10562 MLXSW_REG_ZERO(mpsc, payload); 10563 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10564 mlxsw_reg_mpsc_e_set(payload, e); 10565 mlxsw_reg_mpsc_rate_set(payload, rate); 10566 } 10567 10568 /* MGPC - Monitoring General Purpose Counter Set Register 10569 * The MGPC register retrieves and sets the General Purpose Counter Set. 10570 */ 10571 #define MLXSW_REG_MGPC_ID 0x9081 10572 #define MLXSW_REG_MGPC_LEN 0x18 10573 10574 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10575 10576 /* reg_mgpc_counter_set_type 10577 * Counter set type. 10578 * Access: OP 10579 */ 10580 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10581 10582 /* reg_mgpc_counter_index 10583 * Counter index. 10584 * Access: Index 10585 */ 10586 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10587 10588 enum mlxsw_reg_mgpc_opcode { 10589 /* Nop */ 10590 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10591 /* Clear counters */ 10592 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10593 }; 10594 10595 /* reg_mgpc_opcode 10596 * Opcode. 10597 * Access: OP 10598 */ 10599 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10600 10601 /* reg_mgpc_byte_counter 10602 * Byte counter value. 10603 * Access: RW 10604 */ 10605 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10606 10607 /* reg_mgpc_packet_counter 10608 * Packet counter value. 10609 * Access: RW 10610 */ 10611 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10612 10613 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10614 enum mlxsw_reg_mgpc_opcode opcode, 10615 enum mlxsw_reg_flow_counter_set_type set_type) 10616 { 10617 MLXSW_REG_ZERO(mgpc, payload); 10618 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10619 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10620 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10621 } 10622 10623 /* MPRS - Monitoring Parsing State Register 10624 * ---------------------------------------- 10625 * The MPRS register is used for setting up the parsing for hash, 10626 * policy-engine and routing. 10627 */ 10628 #define MLXSW_REG_MPRS_ID 0x9083 10629 #define MLXSW_REG_MPRS_LEN 0x14 10630 10631 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10632 10633 /* reg_mprs_parsing_depth 10634 * Minimum parsing depth. 10635 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10636 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10637 * Access: RW 10638 */ 10639 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10640 10641 /* reg_mprs_parsing_en 10642 * Parsing enable. 10643 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10644 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10645 * Access: RW 10646 */ 10647 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10648 10649 /* reg_mprs_vxlan_udp_dport 10650 * VxLAN UDP destination port. 10651 * Used for identifying VxLAN packets and for dport field in 10652 * encapsulation. Default is 4789. 10653 * Access: RW 10654 */ 10655 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10656 10657 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10658 u16 vxlan_udp_dport) 10659 { 10660 MLXSW_REG_ZERO(mprs, payload); 10661 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10662 mlxsw_reg_mprs_parsing_en_set(payload, true); 10663 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10664 } 10665 10666 /* MOGCR - Monitoring Global Configuration Register 10667 * ------------------------------------------------ 10668 */ 10669 #define MLXSW_REG_MOGCR_ID 0x9086 10670 #define MLXSW_REG_MOGCR_LEN 0x20 10671 10672 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10673 10674 /* reg_mogcr_ptp_iftc 10675 * PTP Ingress FIFO Trap Clear 10676 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10677 * to this value. Default 0. 10678 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10679 * Access: RW 10680 */ 10681 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10682 10683 /* reg_mogcr_ptp_eftc 10684 * PTP Egress FIFO Trap Clear 10685 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10686 * to this value. Default 0. 10687 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10688 * Access: RW 10689 */ 10690 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10691 10692 /* reg_mogcr_mirroring_pid_base 10693 * Base policer id for mirroring policers. 10694 * Must have an even value (e.g. 1000, not 1001). 10695 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10696 * Access: RW 10697 */ 10698 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10699 10700 /* MPAGR - Monitoring Port Analyzer Global Register 10701 * ------------------------------------------------ 10702 * This register is used for global port analyzer configurations. 10703 * Note: This register is not supported by current FW versions for Spectrum-1. 10704 */ 10705 #define MLXSW_REG_MPAGR_ID 0x9089 10706 #define MLXSW_REG_MPAGR_LEN 0x0C 10707 10708 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10709 10710 enum mlxsw_reg_mpagr_trigger { 10711 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10712 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10713 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10714 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10715 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10716 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10717 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10718 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10719 }; 10720 10721 /* reg_mpagr_trigger 10722 * Mirror trigger. 10723 * Access: Index 10724 */ 10725 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10726 10727 /* reg_mpagr_pa_id 10728 * Port analyzer ID. 10729 * Access: RW 10730 */ 10731 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10732 10733 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10734 10735 /* reg_mpagr_probability_rate 10736 * Sampling rate. 10737 * Valid values are: 1 to 3.5*10^9 10738 * Value of 1 means "sample all". Default is 1. 10739 * Access: RW 10740 */ 10741 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10742 10743 static inline void mlxsw_reg_mpagr_pack(char *payload, 10744 enum mlxsw_reg_mpagr_trigger trigger, 10745 u8 pa_id, u32 probability_rate) 10746 { 10747 MLXSW_REG_ZERO(mpagr, payload); 10748 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10749 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10750 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10751 } 10752 10753 /* MOMTE - Monitoring Mirror Trigger Enable Register 10754 * ------------------------------------------------- 10755 * This register is used to configure the mirror enable for different mirror 10756 * reasons. 10757 */ 10758 #define MLXSW_REG_MOMTE_ID 0x908D 10759 #define MLXSW_REG_MOMTE_LEN 0x10 10760 10761 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10762 10763 /* reg_momte_local_port 10764 * Local port number. 10765 * Access: Index 10766 */ 10767 MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8); 10768 10769 enum mlxsw_reg_momte_type { 10770 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10771 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10772 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10773 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10774 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10775 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10776 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10777 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10778 }; 10779 10780 /* reg_momte_type 10781 * Type of mirroring. 10782 * Access: Index 10783 */ 10784 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10785 10786 /* reg_momte_tclass_en 10787 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10788 * 0: disable (default) 10789 * 1: enable 10790 * Access: RW 10791 */ 10792 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10793 10794 static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port, 10795 enum mlxsw_reg_momte_type type) 10796 { 10797 MLXSW_REG_ZERO(momte, payload); 10798 mlxsw_reg_momte_local_port_set(payload, local_port); 10799 mlxsw_reg_momte_type_set(payload, type); 10800 } 10801 10802 /* MTPPPC - Time Precision Packet Port Configuration 10803 * ------------------------------------------------- 10804 * This register serves for configuration of which PTP messages should be 10805 * timestamped. This is a global configuration, despite the register name. 10806 * 10807 * Reserved when Spectrum-2. 10808 */ 10809 #define MLXSW_REG_MTPPPC_ID 0x9090 10810 #define MLXSW_REG_MTPPPC_LEN 0x28 10811 10812 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10813 10814 /* reg_mtpppc_ing_timestamp_message_type 10815 * Bitwise vector of PTP message types to timestamp at ingress. 10816 * MessageType field as defined by IEEE 1588 10817 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10818 * Default all 0 10819 * Access: RW 10820 */ 10821 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10822 10823 /* reg_mtpppc_egr_timestamp_message_type 10824 * Bitwise vector of PTP message types to timestamp at egress. 10825 * MessageType field as defined by IEEE 1588 10826 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10827 * Default all 0 10828 * Access: RW 10829 */ 10830 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10831 10832 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10833 { 10834 MLXSW_REG_ZERO(mtpppc, payload); 10835 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10836 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10837 } 10838 10839 /* MTPPTR - Time Precision Packet Timestamping Reading 10840 * --------------------------------------------------- 10841 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10842 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10843 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10844 * trapped. The sequence number is used to synchronize the timestamp FIFO 10845 * entries and the trapped packets. 10846 * Reserved when Spectrum-2. 10847 */ 10848 10849 #define MLXSW_REG_MTPPTR_ID 0x9091 10850 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10851 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10852 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10853 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10854 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10855 10856 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10857 10858 /* reg_mtpptr_local_port 10859 * Not supported for CPU port. 10860 * Access: Index 10861 */ 10862 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 10863 10864 enum mlxsw_reg_mtpptr_dir { 10865 MLXSW_REG_MTPPTR_DIR_INGRESS, 10866 MLXSW_REG_MTPPTR_DIR_EGRESS, 10867 }; 10868 10869 /* reg_mtpptr_dir 10870 * Direction. 10871 * Access: Index 10872 */ 10873 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10874 10875 /* reg_mtpptr_clr 10876 * Clear the records. 10877 * Access: OP 10878 */ 10879 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10880 10881 /* reg_mtpptr_num_rec 10882 * Number of valid records in the response 10883 * Range 0.. cap_ptp_timestamp_fifo 10884 * Access: RO 10885 */ 10886 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10887 10888 /* reg_mtpptr_rec_message_type 10889 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10890 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10891 * Access: RO 10892 */ 10893 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10894 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10895 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10896 10897 /* reg_mtpptr_rec_domain_number 10898 * DomainNumber field as defined by IEEE 1588 10899 * Access: RO 10900 */ 10901 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10902 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10903 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10904 10905 /* reg_mtpptr_rec_sequence_id 10906 * SequenceId field as defined by IEEE 1588 10907 * Access: RO 10908 */ 10909 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10910 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10911 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10912 10913 /* reg_mtpptr_rec_timestamp_high 10914 * Timestamp of when the PTP packet has passed through the port Units of PLL 10915 * clock time. 10916 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10917 * Access: RO 10918 */ 10919 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10920 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10921 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10922 10923 /* reg_mtpptr_rec_timestamp_low 10924 * See rec_timestamp_high. 10925 * Access: RO 10926 */ 10927 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10928 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10929 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10930 10931 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10932 unsigned int rec, 10933 u8 *p_message_type, 10934 u8 *p_domain_number, 10935 u16 *p_sequence_id, 10936 u64 *p_timestamp) 10937 { 10938 u32 timestamp_high, timestamp_low; 10939 10940 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10941 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10942 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10943 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10944 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10945 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10946 } 10947 10948 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10949 * --------------------------------------------------------- 10950 * This register is used for configuring under which trap to deliver PTP 10951 * packets depending on type of the packet. 10952 */ 10953 #define MLXSW_REG_MTPTPT_ID 0x9092 10954 #define MLXSW_REG_MTPTPT_LEN 0x08 10955 10956 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10957 10958 enum mlxsw_reg_mtptpt_trap_id { 10959 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10960 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10961 }; 10962 10963 /* reg_mtptpt_trap_id 10964 * Trap id. 10965 * Access: Index 10966 */ 10967 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10968 10969 /* reg_mtptpt_message_type 10970 * Bitwise vector of PTP message types to trap. This is a necessary but 10971 * non-sufficient condition since need to enable also per port. See MTPPPC. 10972 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10973 * Bit0: Sync, Bit1: Delay_Req) 10974 */ 10975 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10976 10977 static inline void mlxsw_reg_mtptptp_pack(char *payload, 10978 enum mlxsw_reg_mtptpt_trap_id trap_id, 10979 u16 message_type) 10980 { 10981 MLXSW_REG_ZERO(mtptpt, payload); 10982 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10983 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10984 } 10985 10986 /* MFGD - Monitoring FW General Debug Register 10987 * ------------------------------------------- 10988 */ 10989 #define MLXSW_REG_MFGD_ID 0x90F0 10990 #define MLXSW_REG_MFGD_LEN 0x0C 10991 10992 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 10993 10994 /* reg_mfgd_fw_fatal_event_mode 10995 * 0 - don't check FW fatal (default) 10996 * 1 - check FW fatal - enable MFDE trap 10997 * Access: RW 10998 */ 10999 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11000 11001 /* reg_mfgd_trigger_test 11002 * Access: WO 11003 */ 11004 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11005 11006 /* MGPIR - Management General Peripheral Information Register 11007 * ---------------------------------------------------------- 11008 * MGPIR register allows software to query the hardware and 11009 * firmware general information of peripheral entities. 11010 */ 11011 #define MLXSW_REG_MGPIR_ID 0x9100 11012 #define MLXSW_REG_MGPIR_LEN 0xA0 11013 11014 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11015 11016 enum mlxsw_reg_mgpir_device_type { 11017 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11018 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11019 }; 11020 11021 /* device_type 11022 * Access: RO 11023 */ 11024 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11025 11026 /* devices_per_flash 11027 * Number of devices of device_type per flash (can be shared by few devices). 11028 * Access: RO 11029 */ 11030 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11031 11032 /* num_of_devices 11033 * Number of devices of device_type. 11034 * Access: RO 11035 */ 11036 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11037 11038 /* num_of_modules 11039 * Number of modules. 11040 * Access: RO 11041 */ 11042 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11043 11044 static inline void mlxsw_reg_mgpir_pack(char *payload) 11045 { 11046 MLXSW_REG_ZERO(mgpir, payload); 11047 } 11048 11049 static inline void 11050 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11051 enum mlxsw_reg_mgpir_device_type *device_type, 11052 u8 *devices_per_flash, u8 *num_of_modules) 11053 { 11054 if (num_of_devices) 11055 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11056 if (device_type) 11057 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11058 if (devices_per_flash) 11059 *devices_per_flash = 11060 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11061 if (num_of_modules) 11062 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11063 } 11064 11065 /* MFDE - Monitoring FW Debug Register 11066 * ----------------------------------- 11067 */ 11068 #define MLXSW_REG_MFDE_ID 0x9200 11069 #define MLXSW_REG_MFDE_LEN 0x18 11070 11071 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11072 11073 /* reg_mfde_irisc_id 11074 * Which irisc triggered the event 11075 * Access: RO 11076 */ 11077 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11078 11079 enum mlxsw_reg_mfde_event_id { 11080 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11081 /* KVD insertion machine stopped */ 11082 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11083 }; 11084 11085 /* reg_mfde_event_id 11086 * Access: RO 11087 */ 11088 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11089 11090 enum mlxsw_reg_mfde_method { 11091 MLXSW_REG_MFDE_METHOD_QUERY, 11092 MLXSW_REG_MFDE_METHOD_WRITE, 11093 }; 11094 11095 /* reg_mfde_method 11096 * Access: RO 11097 */ 11098 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11099 11100 /* reg_mfde_long_process 11101 * Indicates if the command is in long_process mode. 11102 * Access: RO 11103 */ 11104 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11105 11106 enum mlxsw_reg_mfde_command_type { 11107 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11108 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11109 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11110 }; 11111 11112 /* reg_mfde_command_type 11113 * Access: RO 11114 */ 11115 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11116 11117 /* reg_mfde_reg_attr_id 11118 * EMAD - register id, MAD - attibute id 11119 * Access: RO 11120 */ 11121 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11122 11123 /* reg_mfde_log_address 11124 * crspace address accessed, which resulted in timeout. 11125 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 11126 * Access: RO 11127 */ 11128 MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32); 11129 11130 /* reg_mfde_log_id 11131 * Which irisc triggered the timeout. 11132 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 11133 * Access: RO 11134 */ 11135 MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4); 11136 11137 /* reg_mfde_log_ip 11138 * IP (instruction pointer) that triggered the timeout. 11139 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 11140 * Access: RO 11141 */ 11142 MLXSW_ITEM64(reg, mfde, log_ip, 0x18, 0, 64); 11143 11144 /* reg_mfde_pipes_mask 11145 * Bit per kvh pipe. 11146 * Access: RO 11147 */ 11148 MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16); 11149 11150 /* TNGCR - Tunneling NVE General Configuration Register 11151 * ---------------------------------------------------- 11152 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11153 */ 11154 #define MLXSW_REG_TNGCR_ID 0xA001 11155 #define MLXSW_REG_TNGCR_LEN 0x44 11156 11157 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11158 11159 enum mlxsw_reg_tngcr_type { 11160 MLXSW_REG_TNGCR_TYPE_VXLAN, 11161 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11162 MLXSW_REG_TNGCR_TYPE_GENEVE, 11163 MLXSW_REG_TNGCR_TYPE_NVGRE, 11164 }; 11165 11166 /* reg_tngcr_type 11167 * Tunnel type for encapsulation and decapsulation. The types are mutually 11168 * exclusive. 11169 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11170 * Access: RW 11171 */ 11172 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11173 11174 /* reg_tngcr_nve_valid 11175 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11176 * Access: RW 11177 */ 11178 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11179 11180 /* reg_tngcr_nve_ttl_uc 11181 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11182 * Access: RW 11183 */ 11184 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11185 11186 /* reg_tngcr_nve_ttl_mc 11187 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11188 * Access: RW 11189 */ 11190 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11191 11192 enum { 11193 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11194 MLXSW_REG_TNGCR_FL_NO_COPY, 11195 /* Copy flow label from inner packet if packet is IPv6 and 11196 * encapsulation is by IPv6. Otherwise, calculate flow label using 11197 * nve_flh. 11198 */ 11199 MLXSW_REG_TNGCR_FL_COPY, 11200 }; 11201 11202 /* reg_tngcr_nve_flc 11203 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11204 * Access: RW 11205 */ 11206 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11207 11208 enum { 11209 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11210 * uses {nve_fl_prefix, nve_fl_suffix}. 11211 */ 11212 MLXSW_REG_TNGCR_FL_NO_HASH, 11213 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11214 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11215 */ 11216 MLXSW_REG_TNGCR_FL_HASH, 11217 }; 11218 11219 /* reg_tngcr_nve_flh 11220 * NVE flow label hash. 11221 * Access: RW 11222 */ 11223 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11224 11225 /* reg_tngcr_nve_fl_prefix 11226 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11227 * Access: RW 11228 */ 11229 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11230 11231 /* reg_tngcr_nve_fl_suffix 11232 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11233 * Reserved when nve_flh=1 and for Spectrum. 11234 * Access: RW 11235 */ 11236 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11237 11238 enum { 11239 /* Source UDP port is fixed (default '0') */ 11240 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11241 /* Source UDP port is calculated based on hash */ 11242 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11243 }; 11244 11245 /* reg_tngcr_nve_udp_sport_type 11246 * NVE UDP source port type. 11247 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11248 * When the source UDP port is calculated based on hash, then the 8 LSBs 11249 * are calculated from hash the 8 MSBs are configured by 11250 * nve_udp_sport_prefix. 11251 * Access: RW 11252 */ 11253 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11254 11255 /* reg_tngcr_nve_udp_sport_prefix 11256 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11257 * Reserved when NVE type is NVGRE. 11258 * Access: RW 11259 */ 11260 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11261 11262 /* reg_tngcr_nve_group_size_mc 11263 * The amount of sequential linked lists of MC entries. The first linked 11264 * list is configured by SFD.underlay_mc_ptr. 11265 * Valid values: 1, 2, 4, 8, 16, 32, 64 11266 * The linked list are configured by TNUMT. 11267 * The hash is set by LAG hash. 11268 * Access: RW 11269 */ 11270 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11271 11272 /* reg_tngcr_nve_group_size_flood 11273 * The amount of sequential linked lists of flooding entries. The first 11274 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11275 * Valid values: 1, 2, 4, 8, 16, 32, 64 11276 * The linked list are configured by TNUMT. 11277 * The hash is set by LAG hash. 11278 * Access: RW 11279 */ 11280 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11281 11282 /* reg_tngcr_learn_enable 11283 * During decapsulation, whether to learn from NVE port. 11284 * Reserved when Spectrum-2. See TNPC. 11285 * Access: RW 11286 */ 11287 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11288 11289 /* reg_tngcr_underlay_virtual_router 11290 * Underlay virtual router. 11291 * Reserved when Spectrum-2. 11292 * Access: RW 11293 */ 11294 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11295 11296 /* reg_tngcr_underlay_rif 11297 * Underlay ingress router interface. RIF type should be loopback generic. 11298 * Reserved when Spectrum. 11299 * Access: RW 11300 */ 11301 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11302 11303 /* reg_tngcr_usipv4 11304 * Underlay source IPv4 address of the NVE. 11305 * Access: RW 11306 */ 11307 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11308 11309 /* reg_tngcr_usipv6 11310 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11311 * modified under traffic of NVE tunneling encapsulation. 11312 * Access: RW 11313 */ 11314 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11315 11316 static inline void mlxsw_reg_tngcr_pack(char *payload, 11317 enum mlxsw_reg_tngcr_type type, 11318 bool valid, u8 ttl) 11319 { 11320 MLXSW_REG_ZERO(tngcr, payload); 11321 mlxsw_reg_tngcr_type_set(payload, type); 11322 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11323 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11324 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11325 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11326 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11327 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11328 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11329 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11330 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11331 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11332 } 11333 11334 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11335 * ------------------------------------------------------- 11336 * The TNUMT register is for building the underlay MC table. It is used 11337 * for MC, flooding and BC traffic into the NVE tunnel. 11338 */ 11339 #define MLXSW_REG_TNUMT_ID 0xA003 11340 #define MLXSW_REG_TNUMT_LEN 0x20 11341 11342 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11343 11344 enum mlxsw_reg_tnumt_record_type { 11345 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11346 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11347 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11348 }; 11349 11350 /* reg_tnumt_record_type 11351 * Record type. 11352 * Access: RW 11353 */ 11354 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11355 11356 /* reg_tnumt_tunnel_port 11357 * Tunnel port. 11358 * Access: RW 11359 */ 11360 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11361 11362 /* reg_tnumt_underlay_mc_ptr 11363 * Index to the underlay multicast table. 11364 * For Spectrum the index is to the KVD linear. 11365 * Access: Index 11366 */ 11367 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11368 11369 /* reg_tnumt_vnext 11370 * The next_underlay_mc_ptr is valid. 11371 * Access: RW 11372 */ 11373 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11374 11375 /* reg_tnumt_next_underlay_mc_ptr 11376 * The next index to the underlay multicast table. 11377 * Access: RW 11378 */ 11379 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11380 11381 /* reg_tnumt_record_size 11382 * Number of IP addresses in the record. 11383 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11384 * Access: RW 11385 */ 11386 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11387 11388 /* reg_tnumt_udip 11389 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11390 * Access: RW 11391 */ 11392 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11393 11394 /* reg_tnumt_udip_ptr 11395 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11396 * i >= size. The IPv6 addresses are configured by RIPS. 11397 * Access: RW 11398 */ 11399 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11400 11401 static inline void mlxsw_reg_tnumt_pack(char *payload, 11402 enum mlxsw_reg_tnumt_record_type type, 11403 enum mlxsw_reg_tunnel_port tport, 11404 u32 underlay_mc_ptr, bool vnext, 11405 u32 next_underlay_mc_ptr, 11406 u8 record_size) 11407 { 11408 MLXSW_REG_ZERO(tnumt, payload); 11409 mlxsw_reg_tnumt_record_type_set(payload, type); 11410 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 11411 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 11412 mlxsw_reg_tnumt_vnext_set(payload, vnext); 11413 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 11414 mlxsw_reg_tnumt_record_size_set(payload, record_size); 11415 } 11416 11417 /* TNQCR - Tunneling NVE QoS Configuration Register 11418 * ------------------------------------------------ 11419 * The TNQCR register configures how QoS is set in encapsulation into the 11420 * underlay network. 11421 */ 11422 #define MLXSW_REG_TNQCR_ID 0xA010 11423 #define MLXSW_REG_TNQCR_LEN 0x0C 11424 11425 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 11426 11427 /* reg_tnqcr_enc_set_dscp 11428 * For encapsulation: How to set DSCP field: 11429 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 11430 * (outer) IP header. If there is no IP header, use TNQDR.dscp 11431 * 1 - Set the DSCP field as TNQDR.dscp 11432 * Access: RW 11433 */ 11434 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 11435 11436 static inline void mlxsw_reg_tnqcr_pack(char *payload) 11437 { 11438 MLXSW_REG_ZERO(tnqcr, payload); 11439 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 11440 } 11441 11442 /* TNQDR - Tunneling NVE QoS Default Register 11443 * ------------------------------------------ 11444 * The TNQDR register configures the default QoS settings for NVE 11445 * encapsulation. 11446 */ 11447 #define MLXSW_REG_TNQDR_ID 0xA011 11448 #define MLXSW_REG_TNQDR_LEN 0x08 11449 11450 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 11451 11452 /* reg_tnqdr_local_port 11453 * Local port number (receive port). CPU port is supported. 11454 * Access: Index 11455 */ 11456 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 11457 11458 /* reg_tnqdr_dscp 11459 * For encapsulation, the default DSCP. 11460 * Access: RW 11461 */ 11462 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 11463 11464 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 11465 { 11466 MLXSW_REG_ZERO(tnqdr, payload); 11467 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 11468 mlxsw_reg_tnqdr_dscp_set(payload, 0); 11469 } 11470 11471 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 11472 * -------------------------------------------------------- 11473 * The TNEEM register maps ECN of the IP header at the ingress to the 11474 * encapsulation to the ECN of the underlay network. 11475 */ 11476 #define MLXSW_REG_TNEEM_ID 0xA012 11477 #define MLXSW_REG_TNEEM_LEN 0x0C 11478 11479 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 11480 11481 /* reg_tneem_overlay_ecn 11482 * ECN of the IP header in the overlay network. 11483 * Access: Index 11484 */ 11485 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 11486 11487 /* reg_tneem_underlay_ecn 11488 * ECN of the IP header in the underlay network. 11489 * Access: RW 11490 */ 11491 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 11492 11493 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 11494 u8 underlay_ecn) 11495 { 11496 MLXSW_REG_ZERO(tneem, payload); 11497 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 11498 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 11499 } 11500 11501 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 11502 * -------------------------------------------------------- 11503 * The TNDEM register configures the actions that are done in the 11504 * decapsulation. 11505 */ 11506 #define MLXSW_REG_TNDEM_ID 0xA013 11507 #define MLXSW_REG_TNDEM_LEN 0x0C 11508 11509 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 11510 11511 /* reg_tndem_underlay_ecn 11512 * ECN field of the IP header in the underlay network. 11513 * Access: Index 11514 */ 11515 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 11516 11517 /* reg_tndem_overlay_ecn 11518 * ECN field of the IP header in the overlay network. 11519 * Access: Index 11520 */ 11521 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 11522 11523 /* reg_tndem_eip_ecn 11524 * Egress IP ECN. ECN field of the IP header of the packet which goes out 11525 * from the decapsulation. 11526 * Access: RW 11527 */ 11528 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 11529 11530 /* reg_tndem_trap_en 11531 * Trap enable: 11532 * 0 - No trap due to decap ECN 11533 * 1 - Trap enable with trap_id 11534 * Access: RW 11535 */ 11536 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 11537 11538 /* reg_tndem_trap_id 11539 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 11540 * Reserved when trap_en is '0'. 11541 * Access: RW 11542 */ 11543 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 11544 11545 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 11546 u8 overlay_ecn, u8 ecn, bool trap_en, 11547 u16 trap_id) 11548 { 11549 MLXSW_REG_ZERO(tndem, payload); 11550 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 11551 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 11552 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 11553 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 11554 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 11555 } 11556 11557 /* TNPC - Tunnel Port Configuration Register 11558 * ----------------------------------------- 11559 * The TNPC register is used for tunnel port configuration. 11560 * Reserved when Spectrum. 11561 */ 11562 #define MLXSW_REG_TNPC_ID 0xA020 11563 #define MLXSW_REG_TNPC_LEN 0x18 11564 11565 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 11566 11567 /* reg_tnpc_tunnel_port 11568 * Tunnel port. 11569 * Access: Index 11570 */ 11571 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 11572 11573 /* reg_tnpc_learn_enable_v6 11574 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 11575 * Access: RW 11576 */ 11577 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 11578 11579 /* reg_tnpc_learn_enable_v4 11580 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 11581 * Access: RW 11582 */ 11583 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 11584 11585 static inline void mlxsw_reg_tnpc_pack(char *payload, 11586 enum mlxsw_reg_tunnel_port tport, 11587 bool learn_enable) 11588 { 11589 MLXSW_REG_ZERO(tnpc, payload); 11590 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 11591 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 11592 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 11593 } 11594 11595 /* TIGCR - Tunneling IPinIP General Configuration Register 11596 * ------------------------------------------------------- 11597 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 11598 */ 11599 #define MLXSW_REG_TIGCR_ID 0xA801 11600 #define MLXSW_REG_TIGCR_LEN 0x10 11601 11602 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 11603 11604 /* reg_tigcr_ipip_ttlc 11605 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 11606 * header. 11607 * Access: RW 11608 */ 11609 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 11610 11611 /* reg_tigcr_ipip_ttl_uc 11612 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 11613 * reg_tigcr_ipip_ttlc is unset. 11614 * Access: RW 11615 */ 11616 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 11617 11618 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 11619 { 11620 MLXSW_REG_ZERO(tigcr, payload); 11621 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 11622 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 11623 } 11624 11625 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 11626 * ----------------------------------------------------------- 11627 * The TIEEM register maps ECN of the IP header at the ingress to the 11628 * encapsulation to the ECN of the underlay network. 11629 */ 11630 #define MLXSW_REG_TIEEM_ID 0xA812 11631 #define MLXSW_REG_TIEEM_LEN 0x0C 11632 11633 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 11634 11635 /* reg_tieem_overlay_ecn 11636 * ECN of the IP header in the overlay network. 11637 * Access: Index 11638 */ 11639 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 11640 11641 /* reg_tineem_underlay_ecn 11642 * ECN of the IP header in the underlay network. 11643 * Access: RW 11644 */ 11645 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 11646 11647 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 11648 u8 underlay_ecn) 11649 { 11650 MLXSW_REG_ZERO(tieem, payload); 11651 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 11652 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 11653 } 11654 11655 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 11656 * ----------------------------------------------------------- 11657 * The TIDEM register configures the actions that are done in the 11658 * decapsulation. 11659 */ 11660 #define MLXSW_REG_TIDEM_ID 0xA813 11661 #define MLXSW_REG_TIDEM_LEN 0x0C 11662 11663 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 11664 11665 /* reg_tidem_underlay_ecn 11666 * ECN field of the IP header in the underlay network. 11667 * Access: Index 11668 */ 11669 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 11670 11671 /* reg_tidem_overlay_ecn 11672 * ECN field of the IP header in the overlay network. 11673 * Access: Index 11674 */ 11675 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 11676 11677 /* reg_tidem_eip_ecn 11678 * Egress IP ECN. ECN field of the IP header of the packet which goes out 11679 * from the decapsulation. 11680 * Access: RW 11681 */ 11682 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 11683 11684 /* reg_tidem_trap_en 11685 * Trap enable: 11686 * 0 - No trap due to decap ECN 11687 * 1 - Trap enable with trap_id 11688 * Access: RW 11689 */ 11690 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 11691 11692 /* reg_tidem_trap_id 11693 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 11694 * Reserved when trap_en is '0'. 11695 * Access: RW 11696 */ 11697 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 11698 11699 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 11700 u8 overlay_ecn, u8 eip_ecn, 11701 bool trap_en, u16 trap_id) 11702 { 11703 MLXSW_REG_ZERO(tidem, payload); 11704 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 11705 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 11706 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 11707 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 11708 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 11709 } 11710 11711 /* SBPR - Shared Buffer Pools Register 11712 * ----------------------------------- 11713 * The SBPR configures and retrieves the shared buffer pools and configuration. 11714 */ 11715 #define MLXSW_REG_SBPR_ID 0xB001 11716 #define MLXSW_REG_SBPR_LEN 0x14 11717 11718 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 11719 11720 /* shared direstion enum for SBPR, SBCM, SBPM */ 11721 enum mlxsw_reg_sbxx_dir { 11722 MLXSW_REG_SBXX_DIR_INGRESS, 11723 MLXSW_REG_SBXX_DIR_EGRESS, 11724 }; 11725 11726 /* reg_sbpr_dir 11727 * Direction. 11728 * Access: Index 11729 */ 11730 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 11731 11732 /* reg_sbpr_pool 11733 * Pool index. 11734 * Access: Index 11735 */ 11736 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 11737 11738 /* reg_sbpr_infi_size 11739 * Size is infinite. 11740 * Access: RW 11741 */ 11742 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 11743 11744 /* reg_sbpr_size 11745 * Pool size in buffer cells. 11746 * Reserved when infi_size = 1. 11747 * Access: RW 11748 */ 11749 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 11750 11751 enum mlxsw_reg_sbpr_mode { 11752 MLXSW_REG_SBPR_MODE_STATIC, 11753 MLXSW_REG_SBPR_MODE_DYNAMIC, 11754 }; 11755 11756 /* reg_sbpr_mode 11757 * Pool quota calculation mode. 11758 * Access: RW 11759 */ 11760 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 11761 11762 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 11763 enum mlxsw_reg_sbxx_dir dir, 11764 enum mlxsw_reg_sbpr_mode mode, u32 size, 11765 bool infi_size) 11766 { 11767 MLXSW_REG_ZERO(sbpr, payload); 11768 mlxsw_reg_sbpr_pool_set(payload, pool); 11769 mlxsw_reg_sbpr_dir_set(payload, dir); 11770 mlxsw_reg_sbpr_mode_set(payload, mode); 11771 mlxsw_reg_sbpr_size_set(payload, size); 11772 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 11773 } 11774 11775 /* SBCM - Shared Buffer Class Management Register 11776 * ---------------------------------------------- 11777 * The SBCM register configures and retrieves the shared buffer allocation 11778 * and configuration according to Port-PG, including the binding to pool 11779 * and definition of the associated quota. 11780 */ 11781 #define MLXSW_REG_SBCM_ID 0xB002 11782 #define MLXSW_REG_SBCM_LEN 0x28 11783 11784 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 11785 11786 /* reg_sbcm_local_port 11787 * Local port number. 11788 * For Ingress: excludes CPU port and Router port 11789 * For Egress: excludes IP Router 11790 * Access: Index 11791 */ 11792 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 11793 11794 /* reg_sbcm_pg_buff 11795 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 11796 * For PG buffer: range is 0..cap_max_pg_buffers - 1 11797 * For traffic class: range is 0..cap_max_tclass - 1 11798 * Note that when traffic class is in MC aware mode then the traffic 11799 * classes which are MC aware cannot be configured. 11800 * Access: Index 11801 */ 11802 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 11803 11804 /* reg_sbcm_dir 11805 * Direction. 11806 * Access: Index 11807 */ 11808 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 11809 11810 /* reg_sbcm_min_buff 11811 * Minimum buffer size for the limiter, in cells. 11812 * Access: RW 11813 */ 11814 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 11815 11816 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 11817 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 11818 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 11819 11820 /* reg_sbcm_infi_max 11821 * Max buffer is infinite. 11822 * Access: RW 11823 */ 11824 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 11825 11826 /* reg_sbcm_max_buff 11827 * When the pool associated to the port-pg/tclass is configured to 11828 * static, Maximum buffer size for the limiter configured in cells. 11829 * When the pool associated to the port-pg/tclass is configured to 11830 * dynamic, the max_buff holds the "alpha" parameter, supporting 11831 * the following values: 11832 * 0: 0 11833 * i: (1/128)*2^(i-1), for i=1..14 11834 * 0xFF: Infinity 11835 * Reserved when infi_max = 1. 11836 * Access: RW 11837 */ 11838 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 11839 11840 /* reg_sbcm_pool 11841 * Association of the port-priority to a pool. 11842 * Access: RW 11843 */ 11844 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 11845 11846 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 11847 enum mlxsw_reg_sbxx_dir dir, 11848 u32 min_buff, u32 max_buff, 11849 bool infi_max, u8 pool) 11850 { 11851 MLXSW_REG_ZERO(sbcm, payload); 11852 mlxsw_reg_sbcm_local_port_set(payload, local_port); 11853 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 11854 mlxsw_reg_sbcm_dir_set(payload, dir); 11855 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 11856 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 11857 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 11858 mlxsw_reg_sbcm_pool_set(payload, pool); 11859 } 11860 11861 /* SBPM - Shared Buffer Port Management Register 11862 * --------------------------------------------- 11863 * The SBPM register configures and retrieves the shared buffer allocation 11864 * and configuration according to Port-Pool, including the definition 11865 * of the associated quota. 11866 */ 11867 #define MLXSW_REG_SBPM_ID 0xB003 11868 #define MLXSW_REG_SBPM_LEN 0x28 11869 11870 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 11871 11872 /* reg_sbpm_local_port 11873 * Local port number. 11874 * For Ingress: excludes CPU port and Router port 11875 * For Egress: excludes IP Router 11876 * Access: Index 11877 */ 11878 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 11879 11880 /* reg_sbpm_pool 11881 * The pool associated to quota counting on the local_port. 11882 * Access: Index 11883 */ 11884 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 11885 11886 /* reg_sbpm_dir 11887 * Direction. 11888 * Access: Index 11889 */ 11890 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 11891 11892 /* reg_sbpm_buff_occupancy 11893 * Current buffer occupancy in cells. 11894 * Access: RO 11895 */ 11896 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 11897 11898 /* reg_sbpm_clr 11899 * Clear Max Buffer Occupancy 11900 * When this bit is set, max_buff_occupancy field is cleared (and a 11901 * new max value is tracked from the time the clear was performed). 11902 * Access: OP 11903 */ 11904 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 11905 11906 /* reg_sbpm_max_buff_occupancy 11907 * Maximum value of buffer occupancy in cells monitored. Cleared by 11908 * writing to the clr field. 11909 * Access: RO 11910 */ 11911 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 11912 11913 /* reg_sbpm_min_buff 11914 * Minimum buffer size for the limiter, in cells. 11915 * Access: RW 11916 */ 11917 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 11918 11919 /* reg_sbpm_max_buff 11920 * When the pool associated to the port-pg/tclass is configured to 11921 * static, Maximum buffer size for the limiter configured in cells. 11922 * When the pool associated to the port-pg/tclass is configured to 11923 * dynamic, the max_buff holds the "alpha" parameter, supporting 11924 * the following values: 11925 * 0: 0 11926 * i: (1/128)*2^(i-1), for i=1..14 11927 * 0xFF: Infinity 11928 * Access: RW 11929 */ 11930 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 11931 11932 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 11933 enum mlxsw_reg_sbxx_dir dir, bool clr, 11934 u32 min_buff, u32 max_buff) 11935 { 11936 MLXSW_REG_ZERO(sbpm, payload); 11937 mlxsw_reg_sbpm_local_port_set(payload, local_port); 11938 mlxsw_reg_sbpm_pool_set(payload, pool); 11939 mlxsw_reg_sbpm_dir_set(payload, dir); 11940 mlxsw_reg_sbpm_clr_set(payload, clr); 11941 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 11942 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 11943 } 11944 11945 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 11946 u32 *p_max_buff_occupancy) 11947 { 11948 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 11949 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 11950 } 11951 11952 /* SBMM - Shared Buffer Multicast Management Register 11953 * -------------------------------------------------- 11954 * The SBMM register configures and retrieves the shared buffer allocation 11955 * and configuration for MC packets according to Switch-Priority, including 11956 * the binding to pool and definition of the associated quota. 11957 */ 11958 #define MLXSW_REG_SBMM_ID 0xB004 11959 #define MLXSW_REG_SBMM_LEN 0x28 11960 11961 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 11962 11963 /* reg_sbmm_prio 11964 * Switch Priority. 11965 * Access: Index 11966 */ 11967 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 11968 11969 /* reg_sbmm_min_buff 11970 * Minimum buffer size for the limiter, in cells. 11971 * Access: RW 11972 */ 11973 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 11974 11975 /* reg_sbmm_max_buff 11976 * When the pool associated to the port-pg/tclass is configured to 11977 * static, Maximum buffer size for the limiter configured in cells. 11978 * When the pool associated to the port-pg/tclass is configured to 11979 * dynamic, the max_buff holds the "alpha" parameter, supporting 11980 * the following values: 11981 * 0: 0 11982 * i: (1/128)*2^(i-1), for i=1..14 11983 * 0xFF: Infinity 11984 * Access: RW 11985 */ 11986 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 11987 11988 /* reg_sbmm_pool 11989 * Association of the port-priority to a pool. 11990 * Access: RW 11991 */ 11992 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 11993 11994 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 11995 u32 max_buff, u8 pool) 11996 { 11997 MLXSW_REG_ZERO(sbmm, payload); 11998 mlxsw_reg_sbmm_prio_set(payload, prio); 11999 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12000 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12001 mlxsw_reg_sbmm_pool_set(payload, pool); 12002 } 12003 12004 /* SBSR - Shared Buffer Status Register 12005 * ------------------------------------ 12006 * The SBSR register retrieves the shared buffer occupancy according to 12007 * Port-Pool. Note that this register enables reading a large amount of data. 12008 * It is the user's responsibility to limit the amount of data to ensure the 12009 * response can match the maximum transfer unit. In case the response exceeds 12010 * the maximum transport unit, it will be truncated with no special notice. 12011 */ 12012 #define MLXSW_REG_SBSR_ID 0xB005 12013 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12014 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12015 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12016 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12017 MLXSW_REG_SBSR_REC_LEN * \ 12018 MLXSW_REG_SBSR_REC_MAX_COUNT) 12019 12020 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12021 12022 /* reg_sbsr_clr 12023 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12024 * field is cleared (and a new max value is tracked from the time the clear 12025 * was performed). 12026 * Access: OP 12027 */ 12028 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12029 12030 /* reg_sbsr_ingress_port_mask 12031 * Bit vector for all ingress network ports. 12032 * Indicates which of the ports (for which the relevant bit is set) 12033 * are affected by the set operation. Configuration of any other port 12034 * does not change. 12035 * Access: Index 12036 */ 12037 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12038 12039 /* reg_sbsr_pg_buff_mask 12040 * Bit vector for all switch priority groups. 12041 * Indicates which of the priorities (for which the relevant bit is set) 12042 * are affected by the set operation. Configuration of any other priority 12043 * does not change. 12044 * Range is 0..cap_max_pg_buffers - 1 12045 * Access: Index 12046 */ 12047 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12048 12049 /* reg_sbsr_egress_port_mask 12050 * Bit vector for all egress network ports. 12051 * Indicates which of the ports (for which the relevant bit is set) 12052 * are affected by the set operation. Configuration of any other port 12053 * does not change. 12054 * Access: Index 12055 */ 12056 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12057 12058 /* reg_sbsr_tclass_mask 12059 * Bit vector for all traffic classes. 12060 * Indicates which of the traffic classes (for which the relevant bit is 12061 * set) are affected by the set operation. Configuration of any other 12062 * traffic class does not change. 12063 * Range is 0..cap_max_tclass - 1 12064 * Access: Index 12065 */ 12066 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12067 12068 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12069 { 12070 MLXSW_REG_ZERO(sbsr, payload); 12071 mlxsw_reg_sbsr_clr_set(payload, clr); 12072 } 12073 12074 /* reg_sbsr_rec_buff_occupancy 12075 * Current buffer occupancy in cells. 12076 * Access: RO 12077 */ 12078 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12079 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12080 12081 /* reg_sbsr_rec_max_buff_occupancy 12082 * Maximum value of buffer occupancy in cells monitored. Cleared by 12083 * writing to the clr field. 12084 * Access: RO 12085 */ 12086 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12087 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12088 12089 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12090 u32 *p_buff_occupancy, 12091 u32 *p_max_buff_occupancy) 12092 { 12093 *p_buff_occupancy = 12094 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12095 *p_max_buff_occupancy = 12096 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12097 } 12098 12099 /* SBIB - Shared Buffer Internal Buffer Register 12100 * --------------------------------------------- 12101 * The SBIB register configures per port buffers for internal use. The internal 12102 * buffers consume memory on the port buffers (note that the port buffers are 12103 * used also by PBMC). 12104 * 12105 * For Spectrum this is used for egress mirroring. 12106 */ 12107 #define MLXSW_REG_SBIB_ID 0xB006 12108 #define MLXSW_REG_SBIB_LEN 0x10 12109 12110 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12111 12112 /* reg_sbib_local_port 12113 * Local port number 12114 * Not supported for CPU port and router port 12115 * Access: Index 12116 */ 12117 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 12118 12119 /* reg_sbib_buff_size 12120 * Units represented in cells 12121 * Allowed range is 0 to (cap_max_headroom_size - 1) 12122 * Default is 0 12123 * Access: RW 12124 */ 12125 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12126 12127 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 12128 u32 buff_size) 12129 { 12130 MLXSW_REG_ZERO(sbib, payload); 12131 mlxsw_reg_sbib_local_port_set(payload, local_port); 12132 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12133 } 12134 12135 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12136 MLXSW_REG(sgcr), 12137 MLXSW_REG(spad), 12138 MLXSW_REG(smid), 12139 MLXSW_REG(sspr), 12140 MLXSW_REG(sfdat), 12141 MLXSW_REG(sfd), 12142 MLXSW_REG(sfn), 12143 MLXSW_REG(spms), 12144 MLXSW_REG(spvid), 12145 MLXSW_REG(spvm), 12146 MLXSW_REG(spaft), 12147 MLXSW_REG(sfgc), 12148 MLXSW_REG(sftr), 12149 MLXSW_REG(sfdf), 12150 MLXSW_REG(sldr), 12151 MLXSW_REG(slcr), 12152 MLXSW_REG(slcor), 12153 MLXSW_REG(spmlr), 12154 MLXSW_REG(svfa), 12155 MLXSW_REG(spvtr), 12156 MLXSW_REG(svpe), 12157 MLXSW_REG(sfmr), 12158 MLXSW_REG(spvmlr), 12159 MLXSW_REG(spvc), 12160 MLXSW_REG(spevet), 12161 MLXSW_REG(cwtp), 12162 MLXSW_REG(cwtpm), 12163 MLXSW_REG(pgcr), 12164 MLXSW_REG(ppbt), 12165 MLXSW_REG(pacl), 12166 MLXSW_REG(pagt), 12167 MLXSW_REG(ptar), 12168 MLXSW_REG(ppbs), 12169 MLXSW_REG(prcr), 12170 MLXSW_REG(pefa), 12171 MLXSW_REG(pemrbt), 12172 MLXSW_REG(ptce2), 12173 MLXSW_REG(perpt), 12174 MLXSW_REG(peabfe), 12175 MLXSW_REG(perar), 12176 MLXSW_REG(ptce3), 12177 MLXSW_REG(percr), 12178 MLXSW_REG(pererp), 12179 MLXSW_REG(iedr), 12180 MLXSW_REG(qpts), 12181 MLXSW_REG(qpcr), 12182 MLXSW_REG(qtct), 12183 MLXSW_REG(qeec), 12184 MLXSW_REG(qrwe), 12185 MLXSW_REG(qpdsm), 12186 MLXSW_REG(qpdp), 12187 MLXSW_REG(qpdpm), 12188 MLXSW_REG(qtctm), 12189 MLXSW_REG(qpsc), 12190 MLXSW_REG(pmlp), 12191 MLXSW_REG(pmtu), 12192 MLXSW_REG(ptys), 12193 MLXSW_REG(ppad), 12194 MLXSW_REG(paos), 12195 MLXSW_REG(pfcc), 12196 MLXSW_REG(ppcnt), 12197 MLXSW_REG(plib), 12198 MLXSW_REG(pptb), 12199 MLXSW_REG(pbmc), 12200 MLXSW_REG(pspa), 12201 MLXSW_REG(pmaos), 12202 MLXSW_REG(pplr), 12203 MLXSW_REG(pmpe), 12204 MLXSW_REG(pddr), 12205 MLXSW_REG(pmtm), 12206 MLXSW_REG(htgt), 12207 MLXSW_REG(hpkt), 12208 MLXSW_REG(rgcr), 12209 MLXSW_REG(ritr), 12210 MLXSW_REG(rtar), 12211 MLXSW_REG(ratr), 12212 MLXSW_REG(rtdp), 12213 MLXSW_REG(ratrad), 12214 MLXSW_REG(rdpm), 12215 MLXSW_REG(ricnt), 12216 MLXSW_REG(rrcr), 12217 MLXSW_REG(ralta), 12218 MLXSW_REG(ralst), 12219 MLXSW_REG(raltb), 12220 MLXSW_REG(ralue), 12221 MLXSW_REG(rauht), 12222 MLXSW_REG(raleu), 12223 MLXSW_REG(rauhtd), 12224 MLXSW_REG(rigr2), 12225 MLXSW_REG(recr2), 12226 MLXSW_REG(rmft2), 12227 MLXSW_REG(rxlte), 12228 MLXSW_REG(rxltm), 12229 MLXSW_REG(rlcmld), 12230 MLXSW_REG(rlpmce), 12231 MLXSW_REG(xltq), 12232 MLXSW_REG(xmdr), 12233 MLXSW_REG(xrmt), 12234 MLXSW_REG(xralta), 12235 MLXSW_REG(xralst), 12236 MLXSW_REG(xraltb), 12237 MLXSW_REG(mfcr), 12238 MLXSW_REG(mfsc), 12239 MLXSW_REG(mfsm), 12240 MLXSW_REG(mfsl), 12241 MLXSW_REG(fore), 12242 MLXSW_REG(mtcap), 12243 MLXSW_REG(mtmp), 12244 MLXSW_REG(mtwe), 12245 MLXSW_REG(mtbr), 12246 MLXSW_REG(mcia), 12247 MLXSW_REG(mpat), 12248 MLXSW_REG(mpar), 12249 MLXSW_REG(mgir), 12250 MLXSW_REG(mrsr), 12251 MLXSW_REG(mlcr), 12252 MLXSW_REG(mtpps), 12253 MLXSW_REG(mtutc), 12254 MLXSW_REG(mpsc), 12255 MLXSW_REG(mcqi), 12256 MLXSW_REG(mcc), 12257 MLXSW_REG(mcda), 12258 MLXSW_REG(mgpc), 12259 MLXSW_REG(mprs), 12260 MLXSW_REG(mogcr), 12261 MLXSW_REG(mpagr), 12262 MLXSW_REG(momte), 12263 MLXSW_REG(mtpppc), 12264 MLXSW_REG(mtpptr), 12265 MLXSW_REG(mtptpt), 12266 MLXSW_REG(mfgd), 12267 MLXSW_REG(mgpir), 12268 MLXSW_REG(mfde), 12269 MLXSW_REG(tngcr), 12270 MLXSW_REG(tnumt), 12271 MLXSW_REG(tnqcr), 12272 MLXSW_REG(tnqdr), 12273 MLXSW_REG(tneem), 12274 MLXSW_REG(tndem), 12275 MLXSW_REG(tnpc), 12276 MLXSW_REG(tigcr), 12277 MLXSW_REG(tieem), 12278 MLXSW_REG(tidem), 12279 MLXSW_REG(sbpr), 12280 MLXSW_REG(sbcm), 12281 MLXSW_REG(sbpm), 12282 MLXSW_REG(sbmm), 12283 MLXSW_REG(sbsr), 12284 MLXSW_REG(sbib), 12285 }; 12286 12287 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12288 { 12289 const struct mlxsw_reg_info *reg_info; 12290 int i; 12291 12292 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12293 reg_info = mlxsw_reg_infos[i]; 12294 if (reg_info->id == reg_id) 12295 return reg_info->name; 12296 } 12297 return "*UNKNOWN*"; 12298 } 12299 12300 /* PUDE - Port Up / Down Event 12301 * --------------------------- 12302 * Reports the operational state change of a port. 12303 */ 12304 #define MLXSW_REG_PUDE_LEN 0x10 12305 12306 /* reg_pude_swid 12307 * Switch partition ID with which to associate the port. 12308 * Access: Index 12309 */ 12310 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12311 12312 /* reg_pude_local_port 12313 * Local port number. 12314 * Access: Index 12315 */ 12316 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 12317 12318 /* reg_pude_admin_status 12319 * Port administrative state (the desired state). 12320 * 1 - Up. 12321 * 2 - Down. 12322 * 3 - Up once. This means that in case of link failure, the port won't go 12323 * into polling mode, but will wait to be re-enabled by software. 12324 * 4 - Disabled by system. Can only be set by hardware. 12325 * Access: RO 12326 */ 12327 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12328 12329 /* reg_pude_oper_status 12330 * Port operatioanl state. 12331 * 1 - Up. 12332 * 2 - Down. 12333 * 3 - Down by port failure. This means that the device will not let the 12334 * port up again until explicitly specified by software. 12335 * Access: RO 12336 */ 12337 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12338 12339 #endif 12340