1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 }; 299 300 /* reg_sfd_rec_type 301 * FDB record type. 302 * Access: RW 303 */ 304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 305 MLXSW_REG_SFD_REC_LEN, 0x00, false); 306 307 enum mlxsw_reg_sfd_rec_policy { 308 /* Replacement disabled, aging disabled. */ 309 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 310 /* (mlag remote): Replacement enabled, aging disabled, 311 * learning notification enabled on this port. 312 */ 313 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 314 /* (ingress device): Replacement enabled, aging enabled. */ 315 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 316 }; 317 318 /* reg_sfd_rec_policy 319 * Policy. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 323 MLXSW_REG_SFD_REC_LEN, 0x00, false); 324 325 /* reg_sfd_rec_a 326 * Activity. Set for new static entries. Set for static entries if a frame SMAC 327 * lookup hits on the entry. 328 * To clear the a bit, use "query and clear activity" op. 329 * Access: RO 330 */ 331 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 332 MLXSW_REG_SFD_REC_LEN, 0x00, false); 333 334 /* reg_sfd_rec_mac 335 * MAC address. 336 * Access: Index 337 */ 338 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 339 MLXSW_REG_SFD_REC_LEN, 0x02); 340 341 enum mlxsw_reg_sfd_rec_action { 342 /* forward */ 343 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 344 /* forward and trap, trap_id is FDB_TRAP */ 345 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 346 /* trap and do not forward, trap_id is FDB_TRAP */ 347 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 348 /* forward to IP router */ 349 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 350 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 351 }; 352 353 /* reg_sfd_rec_action 354 * Action to apply on the packet. 355 * Note: Dynamic entries can only be configured with NOP action. 356 * Access: RW 357 */ 358 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 359 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 360 361 /* reg_sfd_uc_sub_port 362 * VEPA channel on local port. 363 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 364 * VEPA is not enabled. 365 * Access: RW 366 */ 367 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 368 MLXSW_REG_SFD_REC_LEN, 0x08, false); 369 370 /* reg_sfd_uc_fid_vid 371 * Filtering ID or VLAN ID 372 * For SwitchX and SwitchX-2: 373 * - Dynamic entries (policy 2,3) use FID 374 * - Static entries (policy 0) use VID 375 * - When independent learning is configured, VID=FID 376 * For Spectrum: use FID for both Dynamic and Static entries. 377 * VID should not be used. 378 * Access: Index 379 */ 380 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 381 MLXSW_REG_SFD_REC_LEN, 0x08, false); 382 383 /* reg_sfd_uc_system_port 384 * Unique port identifier for the final destination of the packet. 385 * Access: RW 386 */ 387 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 388 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 389 390 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 391 enum mlxsw_reg_sfd_rec_type rec_type, 392 const char *mac, 393 enum mlxsw_reg_sfd_rec_action action) 394 { 395 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 396 397 if (rec_index >= num_rec) 398 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 399 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 400 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 401 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 402 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 403 } 404 405 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 406 enum mlxsw_reg_sfd_rec_policy policy, 407 const char *mac, u16 fid_vid, 408 enum mlxsw_reg_sfd_rec_action action, 409 u8 local_port) 410 { 411 mlxsw_reg_sfd_rec_pack(payload, rec_index, 412 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 413 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 414 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 415 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 416 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 417 } 418 419 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 420 char *mac, u16 *p_fid_vid, 421 u8 *p_local_port) 422 { 423 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 424 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 425 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 426 } 427 428 /* reg_sfd_uc_lag_sub_port 429 * LAG sub port. 430 * Must be 0 if multichannel VEPA is not enabled. 431 * Access: RW 432 */ 433 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 434 MLXSW_REG_SFD_REC_LEN, 0x08, false); 435 436 /* reg_sfd_uc_lag_fid_vid 437 * Filtering ID or VLAN ID 438 * For SwitchX and SwitchX-2: 439 * - Dynamic entries (policy 2,3) use FID 440 * - Static entries (policy 0) use VID 441 * - When independent learning is configured, VID=FID 442 * For Spectrum: use FID for both Dynamic and Static entries. 443 * VID should not be used. 444 * Access: Index 445 */ 446 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 447 MLXSW_REG_SFD_REC_LEN, 0x08, false); 448 449 /* reg_sfd_uc_lag_lag_vid 450 * Indicates VID in case of vFIDs. Reserved for FIDs. 451 * Access: RW 452 */ 453 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 454 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 455 456 /* reg_sfd_uc_lag_lag_id 457 * LAG Identifier - pointer into the LAG descriptor table. 458 * Access: RW 459 */ 460 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 461 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 462 463 static inline void 464 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 465 enum mlxsw_reg_sfd_rec_policy policy, 466 const char *mac, u16 fid_vid, 467 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 468 u16 lag_id) 469 { 470 mlxsw_reg_sfd_rec_pack(payload, rec_index, 471 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 472 mac, action); 473 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 474 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 475 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 476 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 477 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 478 } 479 480 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 481 char *mac, u16 *p_vid, 482 u16 *p_lag_id) 483 { 484 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 485 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 486 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 487 } 488 489 /* reg_sfd_mc_pgi 490 * 491 * Multicast port group index - index into the port group table. 492 * Value 0x1FFF indicates the pgi should point to the MID entry. 493 * For Spectrum this value must be set to 0x1FFF 494 * Access: RW 495 */ 496 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 497 MLXSW_REG_SFD_REC_LEN, 0x08, false); 498 499 /* reg_sfd_mc_fid_vid 500 * 501 * Filtering ID or VLAN ID 502 * Access: Index 503 */ 504 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 505 MLXSW_REG_SFD_REC_LEN, 0x08, false); 506 507 /* reg_sfd_mc_mid 508 * 509 * Multicast identifier - global identifier that represents the multicast 510 * group across all devices. 511 * Access: RW 512 */ 513 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 514 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 515 516 static inline void 517 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 518 const char *mac, u16 fid_vid, 519 enum mlxsw_reg_sfd_rec_action action, u16 mid) 520 { 521 mlxsw_reg_sfd_rec_pack(payload, rec_index, 522 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 523 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 524 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 525 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 526 } 527 528 /* SFN - Switch FDB Notification Register 529 * ------------------------------------------- 530 * The switch provides notifications on newly learned FDB entries and 531 * aged out entries. The notifications can be polled by software. 532 */ 533 #define MLXSW_REG_SFN_ID 0x200B 534 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 535 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 536 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 537 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 538 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 539 540 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 541 542 /* reg_sfn_swid 543 * Switch partition ID. 544 * Access: Index 545 */ 546 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 547 548 /* reg_sfn_end 549 * Forces the current session to end. 550 * Access: OP 551 */ 552 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 553 554 /* reg_sfn_num_rec 555 * Request: Number of learned notifications and aged-out notification 556 * records requested. 557 * Response: Number of notification records returned (must be smaller 558 * than or equal to the value requested) 559 * Ranges 0..64 560 * Access: OP 561 */ 562 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 563 564 static inline void mlxsw_reg_sfn_pack(char *payload) 565 { 566 MLXSW_REG_ZERO(sfn, payload); 567 mlxsw_reg_sfn_swid_set(payload, 0); 568 mlxsw_reg_sfn_end_set(payload, 1); 569 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 570 } 571 572 /* reg_sfn_rec_swid 573 * Switch partition ID. 574 * Access: RO 575 */ 576 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 577 MLXSW_REG_SFN_REC_LEN, 0x00, false); 578 579 enum mlxsw_reg_sfn_rec_type { 580 /* MAC addresses learned on a regular port. */ 581 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 582 /* MAC addresses learned on a LAG port. */ 583 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 584 /* Aged-out MAC address on a regular port. */ 585 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 586 /* Aged-out MAC address on a LAG port. */ 587 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 588 }; 589 590 /* reg_sfn_rec_type 591 * Notification record type. 592 * Access: RO 593 */ 594 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 595 MLXSW_REG_SFN_REC_LEN, 0x00, false); 596 597 /* reg_sfn_rec_mac 598 * MAC address. 599 * Access: RO 600 */ 601 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 602 MLXSW_REG_SFN_REC_LEN, 0x02); 603 604 /* reg_sfn_mac_sub_port 605 * VEPA channel on the local port. 606 * 0 if multichannel VEPA is not enabled. 607 * Access: RO 608 */ 609 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 610 MLXSW_REG_SFN_REC_LEN, 0x08, false); 611 612 /* reg_sfn_mac_fid 613 * Filtering identifier. 614 * Access: RO 615 */ 616 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 617 MLXSW_REG_SFN_REC_LEN, 0x08, false); 618 619 /* reg_sfn_mac_system_port 620 * Unique port identifier for the final destination of the packet. 621 * Access: RO 622 */ 623 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 624 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 625 626 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 627 char *mac, u16 *p_vid, 628 u8 *p_local_port) 629 { 630 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 631 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 632 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 633 } 634 635 /* reg_sfn_mac_lag_lag_id 636 * LAG ID (pointer into the LAG descriptor table). 637 * Access: RO 638 */ 639 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 640 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 641 642 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 643 char *mac, u16 *p_vid, 644 u16 *p_lag_id) 645 { 646 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 647 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 648 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 649 } 650 651 /* SPMS - Switch Port MSTP/RSTP State Register 652 * ------------------------------------------- 653 * Configures the spanning tree state of a physical port. 654 */ 655 #define MLXSW_REG_SPMS_ID 0x200D 656 #define MLXSW_REG_SPMS_LEN 0x404 657 658 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 659 660 /* reg_spms_local_port 661 * Local port number. 662 * Access: Index 663 */ 664 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 665 666 enum mlxsw_reg_spms_state { 667 MLXSW_REG_SPMS_STATE_NO_CHANGE, 668 MLXSW_REG_SPMS_STATE_DISCARDING, 669 MLXSW_REG_SPMS_STATE_LEARNING, 670 MLXSW_REG_SPMS_STATE_FORWARDING, 671 }; 672 673 /* reg_spms_state 674 * Spanning tree state of each VLAN ID (VID) of the local port. 675 * 0 - Do not change spanning tree state (used only when writing). 676 * 1 - Discarding. No learning or forwarding to/from this port (default). 677 * 2 - Learning. Port is learning, but not forwarding. 678 * 3 - Forwarding. Port is learning and forwarding. 679 * Access: RW 680 */ 681 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 682 683 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 684 { 685 MLXSW_REG_ZERO(spms, payload); 686 mlxsw_reg_spms_local_port_set(payload, local_port); 687 } 688 689 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 690 enum mlxsw_reg_spms_state state) 691 { 692 mlxsw_reg_spms_state_set(payload, vid, state); 693 } 694 695 /* SPVID - Switch Port VID 696 * ----------------------- 697 * The switch port VID configures the default VID for a port. 698 */ 699 #define MLXSW_REG_SPVID_ID 0x200E 700 #define MLXSW_REG_SPVID_LEN 0x08 701 702 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 703 704 /* reg_spvid_local_port 705 * Local port number. 706 * Access: Index 707 */ 708 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 709 710 /* reg_spvid_sub_port 711 * Virtual port within the physical port. 712 * Should be set to 0 when virtual ports are not enabled on the port. 713 * Access: Index 714 */ 715 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 716 717 /* reg_spvid_pvid 718 * Port default VID 719 * Access: RW 720 */ 721 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 722 723 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 724 { 725 MLXSW_REG_ZERO(spvid, payload); 726 mlxsw_reg_spvid_local_port_set(payload, local_port); 727 mlxsw_reg_spvid_pvid_set(payload, pvid); 728 } 729 730 /* SPVM - Switch Port VLAN Membership 731 * ---------------------------------- 732 * The Switch Port VLAN Membership register configures the VLAN membership 733 * of a port in a VLAN denoted by VID. VLAN membership is managed per 734 * virtual port. The register can be used to add and remove VID(s) from a port. 735 */ 736 #define MLXSW_REG_SPVM_ID 0x200F 737 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 738 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 739 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 740 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 741 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 742 743 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 744 745 /* reg_spvm_pt 746 * Priority tagged. If this bit is set, packets forwarded to the port with 747 * untagged VLAN membership (u bit is set) will be tagged with priority tag 748 * (VID=0) 749 * Access: RW 750 */ 751 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 752 753 /* reg_spvm_pte 754 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 755 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 756 * Access: WO 757 */ 758 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 759 760 /* reg_spvm_local_port 761 * Local port number. 762 * Access: Index 763 */ 764 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 765 766 /* reg_spvm_sub_port 767 * Virtual port within the physical port. 768 * Should be set to 0 when virtual ports are not enabled on the port. 769 * Access: Index 770 */ 771 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 772 773 /* reg_spvm_num_rec 774 * Number of records to update. Each record contains: i, e, u, vid. 775 * Access: OP 776 */ 777 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 778 779 /* reg_spvm_rec_i 780 * Ingress membership in VLAN ID. 781 * Access: Index 782 */ 783 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 784 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 785 MLXSW_REG_SPVM_REC_LEN, 0, false); 786 787 /* reg_spvm_rec_e 788 * Egress membership in VLAN ID. 789 * Access: Index 790 */ 791 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 792 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 793 MLXSW_REG_SPVM_REC_LEN, 0, false); 794 795 /* reg_spvm_rec_u 796 * Untagged - port is an untagged member - egress transmission uses untagged 797 * frames on VID<n> 798 * Access: Index 799 */ 800 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 801 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 802 MLXSW_REG_SPVM_REC_LEN, 0, false); 803 804 /* reg_spvm_rec_vid 805 * Egress membership in VLAN ID. 806 * Access: Index 807 */ 808 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 809 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 810 MLXSW_REG_SPVM_REC_LEN, 0, false); 811 812 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 813 u16 vid_begin, u16 vid_end, 814 bool is_member, bool untagged) 815 { 816 int size = vid_end - vid_begin + 1; 817 int i; 818 819 MLXSW_REG_ZERO(spvm, payload); 820 mlxsw_reg_spvm_local_port_set(payload, local_port); 821 mlxsw_reg_spvm_num_rec_set(payload, size); 822 823 for (i = 0; i < size; i++) { 824 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 825 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 826 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 827 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 828 } 829 } 830 831 /* SPAFT - Switch Port Acceptable Frame Types 832 * ------------------------------------------ 833 * The Switch Port Acceptable Frame Types register configures the frame 834 * admittance of the port. 835 */ 836 #define MLXSW_REG_SPAFT_ID 0x2010 837 #define MLXSW_REG_SPAFT_LEN 0x08 838 839 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 840 841 /* reg_spaft_local_port 842 * Local port number. 843 * Access: Index 844 * 845 * Note: CPU port is not supported (all tag types are allowed). 846 */ 847 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 848 849 /* reg_spaft_sub_port 850 * Virtual port within the physical port. 851 * Should be set to 0 when virtual ports are not enabled on the port. 852 * Access: RW 853 */ 854 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 855 856 /* reg_spaft_allow_untagged 857 * When set, untagged frames on the ingress are allowed (default). 858 * Access: RW 859 */ 860 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 861 862 /* reg_spaft_allow_prio_tagged 863 * When set, priority tagged frames on the ingress are allowed (default). 864 * Access: RW 865 */ 866 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 867 868 /* reg_spaft_allow_tagged 869 * When set, tagged frames on the ingress are allowed (default). 870 * Access: RW 871 */ 872 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 873 874 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 875 bool allow_untagged) 876 { 877 MLXSW_REG_ZERO(spaft, payload); 878 mlxsw_reg_spaft_local_port_set(payload, local_port); 879 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 880 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 881 mlxsw_reg_spaft_allow_tagged_set(payload, true); 882 } 883 884 /* SFGC - Switch Flooding Group Configuration 885 * ------------------------------------------ 886 * The following register controls the association of flooding tables and MIDs 887 * to packet types used for flooding. 888 */ 889 #define MLXSW_REG_SFGC_ID 0x2011 890 #define MLXSW_REG_SFGC_LEN 0x10 891 892 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 893 894 enum mlxsw_reg_sfgc_type { 895 MLXSW_REG_SFGC_TYPE_BROADCAST, 896 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 897 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 898 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 899 MLXSW_REG_SFGC_TYPE_RESERVED, 900 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 901 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 902 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 903 MLXSW_REG_SFGC_TYPE_MAX, 904 }; 905 906 /* reg_sfgc_type 907 * The traffic type to reach the flooding table. 908 * Access: Index 909 */ 910 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 911 912 enum mlxsw_reg_sfgc_bridge_type { 913 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 914 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 915 }; 916 917 /* reg_sfgc_bridge_type 918 * Access: Index 919 * 920 * Note: SwitchX-2 only supports 802.1Q mode. 921 */ 922 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 923 924 enum mlxsw_flood_table_type { 925 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 926 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 927 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 928 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 929 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 930 }; 931 932 /* reg_sfgc_table_type 933 * See mlxsw_flood_table_type 934 * Access: RW 935 * 936 * Note: FID offset and FID types are not supported in SwitchX-2. 937 */ 938 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 939 940 /* reg_sfgc_flood_table 941 * Flooding table index to associate with the specific type on the specific 942 * switch partition. 943 * Access: RW 944 */ 945 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 946 947 /* reg_sfgc_mid 948 * The multicast ID for the swid. Not supported for Spectrum 949 * Access: RW 950 */ 951 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 952 953 /* reg_sfgc_counter_set_type 954 * Counter Set Type for flow counters. 955 * Access: RW 956 */ 957 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 958 959 /* reg_sfgc_counter_index 960 * Counter Index for flow counters. 961 * Access: RW 962 */ 963 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 964 965 static inline void 966 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 967 enum mlxsw_reg_sfgc_bridge_type bridge_type, 968 enum mlxsw_flood_table_type table_type, 969 unsigned int flood_table) 970 { 971 MLXSW_REG_ZERO(sfgc, payload); 972 mlxsw_reg_sfgc_type_set(payload, type); 973 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 974 mlxsw_reg_sfgc_table_type_set(payload, table_type); 975 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 976 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 977 } 978 979 /* SFTR - Switch Flooding Table Register 980 * ------------------------------------- 981 * The switch flooding table is used for flooding packet replication. The table 982 * defines a bit mask of ports for packet replication. 983 */ 984 #define MLXSW_REG_SFTR_ID 0x2012 985 #define MLXSW_REG_SFTR_LEN 0x420 986 987 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 988 989 /* reg_sftr_swid 990 * Switch partition ID with which to associate the port. 991 * Access: Index 992 */ 993 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 994 995 /* reg_sftr_flood_table 996 * Flooding table index to associate with the specific type on the specific 997 * switch partition. 998 * Access: Index 999 */ 1000 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1001 1002 /* reg_sftr_index 1003 * Index. Used as an index into the Flooding Table in case the table is 1004 * configured to use VID / FID or FID Offset. 1005 * Access: Index 1006 */ 1007 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1008 1009 /* reg_sftr_table_type 1010 * See mlxsw_flood_table_type 1011 * Access: RW 1012 */ 1013 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1014 1015 /* reg_sftr_range 1016 * Range of entries to update 1017 * Access: Index 1018 */ 1019 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1020 1021 /* reg_sftr_port 1022 * Local port membership (1 bit per port). 1023 * Access: RW 1024 */ 1025 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1026 1027 /* reg_sftr_cpu_port_mask 1028 * CPU port mask (1 bit per port). 1029 * Access: W 1030 */ 1031 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1032 1033 static inline void mlxsw_reg_sftr_pack(char *payload, 1034 unsigned int flood_table, 1035 unsigned int index, 1036 enum mlxsw_flood_table_type table_type, 1037 unsigned int range, u8 port, bool set) 1038 { 1039 MLXSW_REG_ZERO(sftr, payload); 1040 mlxsw_reg_sftr_swid_set(payload, 0); 1041 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1042 mlxsw_reg_sftr_index_set(payload, index); 1043 mlxsw_reg_sftr_table_type_set(payload, table_type); 1044 mlxsw_reg_sftr_range_set(payload, range); 1045 mlxsw_reg_sftr_port_set(payload, port, set); 1046 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1047 } 1048 1049 /* SFDF - Switch Filtering DB Flush 1050 * -------------------------------- 1051 * The switch filtering DB flush register is used to flush the FDB. 1052 * Note that FDB notifications are flushed as well. 1053 */ 1054 #define MLXSW_REG_SFDF_ID 0x2013 1055 #define MLXSW_REG_SFDF_LEN 0x14 1056 1057 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1058 1059 /* reg_sfdf_swid 1060 * Switch partition ID. 1061 * Access: Index 1062 */ 1063 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1064 1065 enum mlxsw_reg_sfdf_flush_type { 1066 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1067 MLXSW_REG_SFDF_FLUSH_PER_FID, 1068 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1069 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1070 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1071 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1072 }; 1073 1074 /* reg_sfdf_flush_type 1075 * Flush type. 1076 * 0 - All SWID dynamic entries are flushed. 1077 * 1 - All FID dynamic entries are flushed. 1078 * 2 - All dynamic entries pointing to port are flushed. 1079 * 3 - All FID dynamic entries pointing to port are flushed. 1080 * 4 - All dynamic entries pointing to LAG are flushed. 1081 * 5 - All FID dynamic entries pointing to LAG are flushed. 1082 * Access: RW 1083 */ 1084 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1085 1086 /* reg_sfdf_flush_static 1087 * Static. 1088 * 0 - Flush only dynamic entries. 1089 * 1 - Flush both dynamic and static entries. 1090 * Access: RW 1091 */ 1092 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1093 1094 static inline void mlxsw_reg_sfdf_pack(char *payload, 1095 enum mlxsw_reg_sfdf_flush_type type) 1096 { 1097 MLXSW_REG_ZERO(sfdf, payload); 1098 mlxsw_reg_sfdf_flush_type_set(payload, type); 1099 mlxsw_reg_sfdf_flush_static_set(payload, true); 1100 } 1101 1102 /* reg_sfdf_fid 1103 * FID to flush. 1104 * Access: RW 1105 */ 1106 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1107 1108 /* reg_sfdf_system_port 1109 * Port to flush. 1110 * Access: RW 1111 */ 1112 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1113 1114 /* reg_sfdf_port_fid_system_port 1115 * Port to flush, pointed to by FID. 1116 * Access: RW 1117 */ 1118 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1119 1120 /* reg_sfdf_lag_id 1121 * LAG ID to flush. 1122 * Access: RW 1123 */ 1124 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1125 1126 /* reg_sfdf_lag_fid_lag_id 1127 * LAG ID to flush, pointed to by FID. 1128 * Access: RW 1129 */ 1130 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1131 1132 /* SLDR - Switch LAG Descriptor Register 1133 * ----------------------------------------- 1134 * The switch LAG descriptor register is populated by LAG descriptors. 1135 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1136 * max_lag-1. 1137 */ 1138 #define MLXSW_REG_SLDR_ID 0x2014 1139 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1140 1141 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1142 1143 enum mlxsw_reg_sldr_op { 1144 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1145 MLXSW_REG_SLDR_OP_LAG_CREATE, 1146 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1147 /* Ports that appear in the list have the Distributor enabled */ 1148 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1149 /* Removes ports from the disributor list */ 1150 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1151 }; 1152 1153 /* reg_sldr_op 1154 * Operation. 1155 * Access: RW 1156 */ 1157 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1158 1159 /* reg_sldr_lag_id 1160 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1161 * Access: Index 1162 */ 1163 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1164 1165 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1166 { 1167 MLXSW_REG_ZERO(sldr, payload); 1168 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1169 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1170 } 1171 1172 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1173 { 1174 MLXSW_REG_ZERO(sldr, payload); 1175 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1176 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1177 } 1178 1179 /* reg_sldr_num_ports 1180 * The number of member ports of the LAG. 1181 * Reserved for Create / Destroy operations 1182 * For Add / Remove operations - indicates the number of ports in the list. 1183 * Access: RW 1184 */ 1185 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1186 1187 /* reg_sldr_system_port 1188 * System port. 1189 * Access: RW 1190 */ 1191 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1192 1193 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1194 u8 local_port) 1195 { 1196 MLXSW_REG_ZERO(sldr, payload); 1197 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1198 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1199 mlxsw_reg_sldr_num_ports_set(payload, 1); 1200 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1201 } 1202 1203 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1204 u8 local_port) 1205 { 1206 MLXSW_REG_ZERO(sldr, payload); 1207 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1208 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1209 mlxsw_reg_sldr_num_ports_set(payload, 1); 1210 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1211 } 1212 1213 /* SLCR - Switch LAG Configuration 2 Register 1214 * ------------------------------------------- 1215 * The Switch LAG Configuration register is used for configuring the 1216 * LAG properties of the switch. 1217 */ 1218 #define MLXSW_REG_SLCR_ID 0x2015 1219 #define MLXSW_REG_SLCR_LEN 0x10 1220 1221 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1222 1223 enum mlxsw_reg_slcr_pp { 1224 /* Global Configuration (for all ports) */ 1225 MLXSW_REG_SLCR_PP_GLOBAL, 1226 /* Per port configuration, based on local_port field */ 1227 MLXSW_REG_SLCR_PP_PER_PORT, 1228 }; 1229 1230 /* reg_slcr_pp 1231 * Per Port Configuration 1232 * Note: Reading at Global mode results in reading port 1 configuration. 1233 * Access: Index 1234 */ 1235 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1236 1237 /* reg_slcr_local_port 1238 * Local port number 1239 * Supported from CPU port 1240 * Not supported from router port 1241 * Reserved when pp = Global Configuration 1242 * Access: Index 1243 */ 1244 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1245 1246 enum mlxsw_reg_slcr_type { 1247 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1248 MLXSW_REG_SLCR_TYPE_XOR, 1249 MLXSW_REG_SLCR_TYPE_RANDOM, 1250 }; 1251 1252 /* reg_slcr_type 1253 * Hash type 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1257 1258 /* Ingress port */ 1259 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1260 /* SMAC - for IPv4 and IPv6 packets */ 1261 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1262 /* SMAC - for non-IP packets */ 1263 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1264 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1265 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1266 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1267 /* DMAC - for IPv4 and IPv6 packets */ 1268 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1269 /* DMAC - for non-IP packets */ 1270 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1271 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1272 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1273 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1274 /* Ethertype - for IPv4 and IPv6 packets */ 1275 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1276 /* Ethertype - for non-IP packets */ 1277 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1278 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1279 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1280 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1281 /* VLAN ID - for IPv4 and IPv6 packets */ 1282 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1283 /* VLAN ID - for non-IP packets */ 1284 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1285 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1286 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1287 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1288 /* Source IP address (can be IPv4 or IPv6) */ 1289 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1290 /* Destination IP address (can be IPv4 or IPv6) */ 1291 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1292 /* TCP/UDP source port */ 1293 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1294 /* TCP/UDP destination port*/ 1295 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1296 /* IPv4 Protocol/IPv6 Next Header */ 1297 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1298 /* IPv6 Flow label */ 1299 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1300 /* SID - FCoE source ID */ 1301 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1302 /* DID - FCoE destination ID */ 1303 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1304 /* OXID - FCoE originator exchange ID */ 1305 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1306 /* Destination QP number - for RoCE packets */ 1307 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1308 1309 /* reg_slcr_lag_hash 1310 * LAG hashing configuration. This is a bitmask, in which each set 1311 * bit includes the corresponding item in the LAG hash calculation. 1312 * The default lag_hash contains SMAC, DMAC, VLANID and 1313 * Ethertype (for all packet types). 1314 * Access: RW 1315 */ 1316 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1317 1318 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1319 { 1320 MLXSW_REG_ZERO(slcr, payload); 1321 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1322 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1323 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1324 } 1325 1326 /* SLCOR - Switch LAG Collector Register 1327 * ------------------------------------- 1328 * The Switch LAG Collector register controls the Local Port membership 1329 * in a LAG and enablement of the collector. 1330 */ 1331 #define MLXSW_REG_SLCOR_ID 0x2016 1332 #define MLXSW_REG_SLCOR_LEN 0x10 1333 1334 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1335 1336 enum mlxsw_reg_slcor_col { 1337 /* Port is added with collector disabled */ 1338 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1339 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1340 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1341 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1342 }; 1343 1344 /* reg_slcor_col 1345 * Collector configuration 1346 * Access: RW 1347 */ 1348 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1349 1350 /* reg_slcor_local_port 1351 * Local port number 1352 * Not supported for CPU port 1353 * Access: Index 1354 */ 1355 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1356 1357 /* reg_slcor_lag_id 1358 * LAG Identifier. Index into the LAG descriptor table. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1362 1363 /* reg_slcor_port_index 1364 * Port index in the LAG list. Only valid on Add Port to LAG col. 1365 * Valid range is from 0 to cap_max_lag_members-1 1366 * Access: RW 1367 */ 1368 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1369 1370 static inline void mlxsw_reg_slcor_pack(char *payload, 1371 u8 local_port, u16 lag_id, 1372 enum mlxsw_reg_slcor_col col) 1373 { 1374 MLXSW_REG_ZERO(slcor, payload); 1375 mlxsw_reg_slcor_col_set(payload, col); 1376 mlxsw_reg_slcor_local_port_set(payload, local_port); 1377 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1378 } 1379 1380 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1381 u8 local_port, u16 lag_id, 1382 u8 port_index) 1383 { 1384 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1385 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1386 mlxsw_reg_slcor_port_index_set(payload, port_index); 1387 } 1388 1389 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1390 u8 local_port, u16 lag_id) 1391 { 1392 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1393 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1394 } 1395 1396 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1397 u8 local_port, u16 lag_id) 1398 { 1399 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1400 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1401 } 1402 1403 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1404 u8 local_port, u16 lag_id) 1405 { 1406 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1407 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1408 } 1409 1410 /* SPMLR - Switch Port MAC Learning Register 1411 * ----------------------------------------- 1412 * Controls the Switch MAC learning policy per port. 1413 */ 1414 #define MLXSW_REG_SPMLR_ID 0x2018 1415 #define MLXSW_REG_SPMLR_LEN 0x8 1416 1417 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1418 1419 /* reg_spmlr_local_port 1420 * Local port number. 1421 * Access: Index 1422 */ 1423 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1424 1425 /* reg_spmlr_sub_port 1426 * Virtual port within the physical port. 1427 * Should be set to 0 when virtual ports are not enabled on the port. 1428 * Access: Index 1429 */ 1430 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1431 1432 enum mlxsw_reg_spmlr_learn_mode { 1433 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1434 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1435 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1436 }; 1437 1438 /* reg_spmlr_learn_mode 1439 * Learning mode on the port. 1440 * 0 - Learning disabled. 1441 * 2 - Learning enabled. 1442 * 3 - Security mode. 1443 * 1444 * In security mode the switch does not learn MACs on the port, but uses the 1445 * SMAC to see if it exists on another ingress port. If so, the packet is 1446 * classified as a bad packet and is discarded unless the software registers 1447 * to receive port security error packets usign HPKT. 1448 */ 1449 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1450 1451 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1452 enum mlxsw_reg_spmlr_learn_mode mode) 1453 { 1454 MLXSW_REG_ZERO(spmlr, payload); 1455 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1456 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1457 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1458 } 1459 1460 /* SVFA - Switch VID to FID Allocation Register 1461 * -------------------------------------------- 1462 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1463 * virtualized ports. 1464 */ 1465 #define MLXSW_REG_SVFA_ID 0x201C 1466 #define MLXSW_REG_SVFA_LEN 0x10 1467 1468 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1469 1470 /* reg_svfa_swid 1471 * Switch partition ID. 1472 * Access: Index 1473 */ 1474 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1475 1476 /* reg_svfa_local_port 1477 * Local port number. 1478 * Access: Index 1479 * 1480 * Note: Reserved for 802.1Q FIDs. 1481 */ 1482 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1483 1484 enum mlxsw_reg_svfa_mt { 1485 MLXSW_REG_SVFA_MT_VID_TO_FID, 1486 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1487 }; 1488 1489 /* reg_svfa_mapping_table 1490 * Mapping table: 1491 * 0 - VID to FID 1492 * 1 - {Port, VID} to FID 1493 * Access: Index 1494 * 1495 * Note: Reserved for SwitchX-2. 1496 */ 1497 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1498 1499 /* reg_svfa_v 1500 * Valid. 1501 * Valid if set. 1502 * Access: RW 1503 * 1504 * Note: Reserved for SwitchX-2. 1505 */ 1506 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1507 1508 /* reg_svfa_fid 1509 * Filtering ID. 1510 * Access: RW 1511 */ 1512 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1513 1514 /* reg_svfa_vid 1515 * VLAN ID. 1516 * Access: Index 1517 */ 1518 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1519 1520 /* reg_svfa_counter_set_type 1521 * Counter set type for flow counters. 1522 * Access: RW 1523 * 1524 * Note: Reserved for SwitchX-2. 1525 */ 1526 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1527 1528 /* reg_svfa_counter_index 1529 * Counter index for flow counters. 1530 * Access: RW 1531 * 1532 * Note: Reserved for SwitchX-2. 1533 */ 1534 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1535 1536 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1537 enum mlxsw_reg_svfa_mt mt, bool valid, 1538 u16 fid, u16 vid) 1539 { 1540 MLXSW_REG_ZERO(svfa, payload); 1541 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1542 mlxsw_reg_svfa_swid_set(payload, 0); 1543 mlxsw_reg_svfa_local_port_set(payload, local_port); 1544 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1545 mlxsw_reg_svfa_v_set(payload, valid); 1546 mlxsw_reg_svfa_fid_set(payload, fid); 1547 mlxsw_reg_svfa_vid_set(payload, vid); 1548 } 1549 1550 /* SVPE - Switch Virtual-Port Enabling Register 1551 * -------------------------------------------- 1552 * Enables port virtualization. 1553 */ 1554 #define MLXSW_REG_SVPE_ID 0x201E 1555 #define MLXSW_REG_SVPE_LEN 0x4 1556 1557 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1558 1559 /* reg_svpe_local_port 1560 * Local port number 1561 * Access: Index 1562 * 1563 * Note: CPU port is not supported (uses VLAN mode only). 1564 */ 1565 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1566 1567 /* reg_svpe_vp_en 1568 * Virtual port enable. 1569 * 0 - Disable, VLAN mode (VID to FID). 1570 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1571 * Access: RW 1572 */ 1573 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1574 1575 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1576 bool enable) 1577 { 1578 MLXSW_REG_ZERO(svpe, payload); 1579 mlxsw_reg_svpe_local_port_set(payload, local_port); 1580 mlxsw_reg_svpe_vp_en_set(payload, enable); 1581 } 1582 1583 /* SFMR - Switch FID Management Register 1584 * ------------------------------------- 1585 * Creates and configures FIDs. 1586 */ 1587 #define MLXSW_REG_SFMR_ID 0x201F 1588 #define MLXSW_REG_SFMR_LEN 0x18 1589 1590 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1591 1592 enum mlxsw_reg_sfmr_op { 1593 MLXSW_REG_SFMR_OP_CREATE_FID, 1594 MLXSW_REG_SFMR_OP_DESTROY_FID, 1595 }; 1596 1597 /* reg_sfmr_op 1598 * Operation. 1599 * 0 - Create or edit FID. 1600 * 1 - Destroy FID. 1601 * Access: WO 1602 */ 1603 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1604 1605 /* reg_sfmr_fid 1606 * Filtering ID. 1607 * Access: Index 1608 */ 1609 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1610 1611 /* reg_sfmr_fid_offset 1612 * FID offset. 1613 * Used to point into the flooding table selected by SFGC register if 1614 * the table is of type FID-Offset. Otherwise, this field is reserved. 1615 * Access: RW 1616 */ 1617 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1618 1619 /* reg_sfmr_vtfp 1620 * Valid Tunnel Flood Pointer. 1621 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1622 * Access: RW 1623 * 1624 * Note: Reserved for 802.1Q FIDs. 1625 */ 1626 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1627 1628 /* reg_sfmr_nve_tunnel_flood_ptr 1629 * Underlay Flooding and BC Pointer. 1630 * Used as a pointer to the first entry of the group based link lists of 1631 * flooding or BC entries (for NVE tunnels). 1632 * Access: RW 1633 */ 1634 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1635 1636 /* reg_sfmr_vv 1637 * VNI Valid. 1638 * If not set, then vni is reserved. 1639 * Access: RW 1640 * 1641 * Note: Reserved for 802.1Q FIDs. 1642 */ 1643 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1644 1645 /* reg_sfmr_vni 1646 * Virtual Network Identifier. 1647 * Access: RW 1648 * 1649 * Note: A given VNI can only be assigned to one FID. 1650 */ 1651 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1652 1653 static inline void mlxsw_reg_sfmr_pack(char *payload, 1654 enum mlxsw_reg_sfmr_op op, u16 fid, 1655 u16 fid_offset) 1656 { 1657 MLXSW_REG_ZERO(sfmr, payload); 1658 mlxsw_reg_sfmr_op_set(payload, op); 1659 mlxsw_reg_sfmr_fid_set(payload, fid); 1660 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1661 mlxsw_reg_sfmr_vtfp_set(payload, false); 1662 mlxsw_reg_sfmr_vv_set(payload, false); 1663 } 1664 1665 /* SPVMLR - Switch Port VLAN MAC Learning Register 1666 * ----------------------------------------------- 1667 * Controls the switch MAC learning policy per {Port, VID}. 1668 */ 1669 #define MLXSW_REG_SPVMLR_ID 0x2020 1670 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1671 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1672 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1673 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1674 MLXSW_REG_SPVMLR_REC_LEN * \ 1675 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1676 1677 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1678 1679 /* reg_spvmlr_local_port 1680 * Local ingress port. 1681 * Access: Index 1682 * 1683 * Note: CPU port is not supported. 1684 */ 1685 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1686 1687 /* reg_spvmlr_num_rec 1688 * Number of records to update. 1689 * Access: OP 1690 */ 1691 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1692 1693 /* reg_spvmlr_rec_learn_enable 1694 * 0 - Disable learning for {Port, VID}. 1695 * 1 - Enable learning for {Port, VID}. 1696 * Access: RW 1697 */ 1698 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1699 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1700 1701 /* reg_spvmlr_rec_vid 1702 * VLAN ID to be added/removed from port or for querying. 1703 * Access: Index 1704 */ 1705 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1706 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1707 1708 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1709 u16 vid_begin, u16 vid_end, 1710 bool learn_enable) 1711 { 1712 int num_rec = vid_end - vid_begin + 1; 1713 int i; 1714 1715 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1716 1717 MLXSW_REG_ZERO(spvmlr, payload); 1718 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1719 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1720 1721 for (i = 0; i < num_rec; i++) { 1722 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1723 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1724 } 1725 } 1726 1727 /* CWTP - Congetion WRED ECN TClass Profile 1728 * ---------------------------------------- 1729 * Configures the profiles for queues of egress port and traffic class 1730 */ 1731 #define MLXSW_REG_CWTP_ID 0x2802 1732 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1733 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1734 #define MLXSW_REG_CWTP_LEN 0x40 1735 1736 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1737 1738 /* reg_cwtp_local_port 1739 * Local port number 1740 * Not supported for CPU port 1741 * Access: Index 1742 */ 1743 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1744 1745 /* reg_cwtp_traffic_class 1746 * Traffic Class to configure 1747 * Access: Index 1748 */ 1749 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1750 1751 /* reg_cwtp_profile_min 1752 * Minimum Average Queue Size of the profile in cells. 1753 * Access: RW 1754 */ 1755 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1756 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1757 1758 /* reg_cwtp_profile_percent 1759 * Percentage of WRED and ECN marking for maximum Average Queue size 1760 * Range is 0 to 100, units of integer percentage 1761 * Access: RW 1762 */ 1763 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1764 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1765 1766 /* reg_cwtp_profile_max 1767 * Maximum Average Queue size of the profile in cells 1768 * Access: RW 1769 */ 1770 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1771 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1772 1773 #define MLXSW_REG_CWTP_MIN_VALUE 64 1774 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1775 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1776 1777 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1778 u8 traffic_class) 1779 { 1780 int i; 1781 1782 MLXSW_REG_ZERO(cwtp, payload); 1783 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1784 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1785 1786 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1787 mlxsw_reg_cwtp_profile_min_set(payload, i, 1788 MLXSW_REG_CWTP_MIN_VALUE); 1789 mlxsw_reg_cwtp_profile_max_set(payload, i, 1790 MLXSW_REG_CWTP_MIN_VALUE); 1791 } 1792 } 1793 1794 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1795 1796 static inline void 1797 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1798 u32 probability) 1799 { 1800 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1801 1802 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1803 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1804 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1805 } 1806 1807 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1808 * --------------------------------------------------- 1809 * The CWTPM register maps each egress port and traffic class to profile num. 1810 */ 1811 #define MLXSW_REG_CWTPM_ID 0x2803 1812 #define MLXSW_REG_CWTPM_LEN 0x44 1813 1814 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1815 1816 /* reg_cwtpm_local_port 1817 * Local port number 1818 * Not supported for CPU port 1819 * Access: Index 1820 */ 1821 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1822 1823 /* reg_cwtpm_traffic_class 1824 * Traffic Class to configure 1825 * Access: Index 1826 */ 1827 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1828 1829 /* reg_cwtpm_ew 1830 * Control enablement of WRED for traffic class: 1831 * 0 - Disable 1832 * 1 - Enable 1833 * Access: RW 1834 */ 1835 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1836 1837 /* reg_cwtpm_ee 1838 * Control enablement of ECN for traffic class: 1839 * 0 - Disable 1840 * 1 - Enable 1841 * Access: RW 1842 */ 1843 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1844 1845 /* reg_cwtpm_tcp_g 1846 * TCP Green Profile. 1847 * Index of the profile within {port, traffic class} to use. 1848 * 0 for disabling both WRED and ECN for this type of traffic. 1849 * Access: RW 1850 */ 1851 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1852 1853 /* reg_cwtpm_tcp_y 1854 * TCP Yellow Profile. 1855 * Index of the profile within {port, traffic class} to use. 1856 * 0 for disabling both WRED and ECN for this type of traffic. 1857 * Access: RW 1858 */ 1859 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1860 1861 /* reg_cwtpm_tcp_r 1862 * TCP Red Profile. 1863 * Index of the profile within {port, traffic class} to use. 1864 * 0 for disabling both WRED and ECN for this type of traffic. 1865 * Access: RW 1866 */ 1867 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 1868 1869 /* reg_cwtpm_ntcp_g 1870 * Non-TCP Green Profile. 1871 * Index of the profile within {port, traffic class} to use. 1872 * 0 for disabling both WRED and ECN for this type of traffic. 1873 * Access: RW 1874 */ 1875 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 1876 1877 /* reg_cwtpm_ntcp_y 1878 * Non-TCP Yellow Profile. 1879 * Index of the profile within {port, traffic class} to use. 1880 * 0 for disabling both WRED and ECN for this type of traffic. 1881 * Access: RW 1882 */ 1883 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 1884 1885 /* reg_cwtpm_ntcp_r 1886 * Non-TCP Red Profile. 1887 * Index of the profile within {port, traffic class} to use. 1888 * 0 for disabling both WRED and ECN for this type of traffic. 1889 * Access: RW 1890 */ 1891 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 1892 1893 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 1894 1895 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 1896 u8 traffic_class, u8 profile, 1897 bool wred, bool ecn) 1898 { 1899 MLXSW_REG_ZERO(cwtpm, payload); 1900 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 1901 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 1902 mlxsw_reg_cwtpm_ew_set(payload, wred); 1903 mlxsw_reg_cwtpm_ee_set(payload, ecn); 1904 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 1905 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 1906 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 1907 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 1908 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 1909 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 1910 } 1911 1912 /* PGCR - Policy-Engine General Configuration Register 1913 * --------------------------------------------------- 1914 * This register configures general Policy-Engine settings. 1915 */ 1916 #define MLXSW_REG_PGCR_ID 0x3001 1917 #define MLXSW_REG_PGCR_LEN 0x20 1918 1919 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 1920 1921 /* reg_pgcr_default_action_pointer_base 1922 * Default action pointer base. Each region has a default action pointer 1923 * which is equal to default_action_pointer_base + region_id. 1924 * Access: RW 1925 */ 1926 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 1927 1928 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 1929 { 1930 MLXSW_REG_ZERO(pgcr, payload); 1931 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 1932 } 1933 1934 /* PPBT - Policy-Engine Port Binding Table 1935 * --------------------------------------- 1936 * This register is used for configuration of the Port Binding Table. 1937 */ 1938 #define MLXSW_REG_PPBT_ID 0x3002 1939 #define MLXSW_REG_PPBT_LEN 0x14 1940 1941 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 1942 1943 enum mlxsw_reg_pxbt_e { 1944 MLXSW_REG_PXBT_E_IACL, 1945 MLXSW_REG_PXBT_E_EACL, 1946 }; 1947 1948 /* reg_ppbt_e 1949 * Access: Index 1950 */ 1951 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 1952 1953 enum mlxsw_reg_pxbt_op { 1954 MLXSW_REG_PXBT_OP_BIND, 1955 MLXSW_REG_PXBT_OP_UNBIND, 1956 }; 1957 1958 /* reg_ppbt_op 1959 * Access: RW 1960 */ 1961 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 1962 1963 /* reg_ppbt_local_port 1964 * Local port. Not including CPU port. 1965 * Access: Index 1966 */ 1967 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 1968 1969 /* reg_ppbt_g 1970 * group - When set, the binding is of an ACL group. When cleared, 1971 * the binding is of an ACL. 1972 * Must be set to 1 for Spectrum. 1973 * Access: RW 1974 */ 1975 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 1976 1977 /* reg_ppbt_acl_info 1978 * ACL/ACL group identifier. If the g bit is set, this field should hold 1979 * the acl_group_id, else it should hold the acl_id. 1980 * Access: RW 1981 */ 1982 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 1983 1984 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 1985 enum mlxsw_reg_pxbt_op op, 1986 u8 local_port, u16 acl_info) 1987 { 1988 MLXSW_REG_ZERO(ppbt, payload); 1989 mlxsw_reg_ppbt_e_set(payload, e); 1990 mlxsw_reg_ppbt_op_set(payload, op); 1991 mlxsw_reg_ppbt_local_port_set(payload, local_port); 1992 mlxsw_reg_ppbt_g_set(payload, true); 1993 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 1994 } 1995 1996 /* PACL - Policy-Engine ACL Register 1997 * --------------------------------- 1998 * This register is used for configuration of the ACL. 1999 */ 2000 #define MLXSW_REG_PACL_ID 0x3004 2001 #define MLXSW_REG_PACL_LEN 0x70 2002 2003 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2004 2005 /* reg_pacl_v 2006 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2007 * while the ACL is bounded to either a port, VLAN or ACL rule. 2008 * Access: RW 2009 */ 2010 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2011 2012 /* reg_pacl_acl_id 2013 * An identifier representing the ACL (managed by software) 2014 * Range 0 .. cap_max_acl_regions - 1 2015 * Access: Index 2016 */ 2017 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2018 2019 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2020 2021 /* reg_pacl_tcam_region_info 2022 * Opaque object that represents a TCAM region. 2023 * Obtained through PTAR register. 2024 * Access: RW 2025 */ 2026 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2027 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2028 2029 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2030 bool valid, const char *tcam_region_info) 2031 { 2032 MLXSW_REG_ZERO(pacl, payload); 2033 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2034 mlxsw_reg_pacl_v_set(payload, valid); 2035 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2036 } 2037 2038 /* PAGT - Policy-Engine ACL Group Table 2039 * ------------------------------------ 2040 * This register is used for configuration of the ACL Group Table. 2041 */ 2042 #define MLXSW_REG_PAGT_ID 0x3005 2043 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2044 #define MLXSW_REG_PAGT_ACL_LEN 4 2045 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2046 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2047 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2048 2049 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2050 2051 /* reg_pagt_size 2052 * Number of ACLs in the group. 2053 * Size 0 invalidates a group. 2054 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2055 * Total number of ACLs in all groups must be lower or equal 2056 * to cap_max_acl_tot_groups 2057 * Note: a group which is binded must not be invalidated 2058 * Access: Index 2059 */ 2060 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2061 2062 /* reg_pagt_acl_group_id 2063 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2064 * the ACL Group identifier (managed by software). 2065 * Access: Index 2066 */ 2067 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2068 2069 /* reg_pagt_acl_id 2070 * ACL identifier 2071 * Access: RW 2072 */ 2073 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2074 2075 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2076 { 2077 MLXSW_REG_ZERO(pagt, payload); 2078 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2079 } 2080 2081 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2082 u16 acl_id) 2083 { 2084 u8 size = mlxsw_reg_pagt_size_get(payload); 2085 2086 if (index >= size) 2087 mlxsw_reg_pagt_size_set(payload, index + 1); 2088 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2089 } 2090 2091 /* PTAR - Policy-Engine TCAM Allocation Register 2092 * --------------------------------------------- 2093 * This register is used for allocation of regions in the TCAM. 2094 * Note: Query method is not supported on this register. 2095 */ 2096 #define MLXSW_REG_PTAR_ID 0x3006 2097 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2098 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2099 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2100 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2101 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2102 2103 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2104 2105 enum mlxsw_reg_ptar_op { 2106 /* allocate a TCAM region */ 2107 MLXSW_REG_PTAR_OP_ALLOC, 2108 /* resize a TCAM region */ 2109 MLXSW_REG_PTAR_OP_RESIZE, 2110 /* deallocate TCAM region */ 2111 MLXSW_REG_PTAR_OP_FREE, 2112 /* test allocation */ 2113 MLXSW_REG_PTAR_OP_TEST, 2114 }; 2115 2116 /* reg_ptar_op 2117 * Access: OP 2118 */ 2119 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2120 2121 /* reg_ptar_action_set_type 2122 * Type of action set to be used on this region. 2123 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2124 * Access: WO 2125 */ 2126 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2127 2128 enum mlxsw_reg_ptar_key_type { 2129 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2130 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2131 }; 2132 2133 /* reg_ptar_key_type 2134 * TCAM key type for the region. 2135 * Access: WO 2136 */ 2137 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2138 2139 /* reg_ptar_region_size 2140 * TCAM region size. When allocating/resizing this is the requested size, 2141 * the response is the actual size. Note that actual size may be 2142 * larger than requested. 2143 * Allowed range 1 .. cap_max_rules-1 2144 * Reserved during op deallocate. 2145 * Access: WO 2146 */ 2147 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2148 2149 /* reg_ptar_region_id 2150 * Region identifier 2151 * Range 0 .. cap_max_regions-1 2152 * Access: Index 2153 */ 2154 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2155 2156 /* reg_ptar_tcam_region_info 2157 * Opaque object that represents the TCAM region. 2158 * Returned when allocating a region. 2159 * Provided by software for ACL generation and region deallocation and resize. 2160 * Access: RW 2161 */ 2162 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2163 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2164 2165 /* reg_ptar_flexible_key_id 2166 * Identifier of the Flexible Key. 2167 * Only valid if key_type == "FLEX_KEY" 2168 * The key size will be rounded up to one of the following values: 2169 * 9B, 18B, 36B, 54B. 2170 * This field is reserved for in resize operation. 2171 * Access: WO 2172 */ 2173 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2174 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2175 2176 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2177 enum mlxsw_reg_ptar_key_type key_type, 2178 u16 region_size, u16 region_id, 2179 const char *tcam_region_info) 2180 { 2181 MLXSW_REG_ZERO(ptar, payload); 2182 mlxsw_reg_ptar_op_set(payload, op); 2183 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2184 mlxsw_reg_ptar_key_type_set(payload, key_type); 2185 mlxsw_reg_ptar_region_size_set(payload, region_size); 2186 mlxsw_reg_ptar_region_id_set(payload, region_id); 2187 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2188 } 2189 2190 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2191 u16 key_id) 2192 { 2193 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2194 } 2195 2196 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2197 { 2198 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2199 } 2200 2201 /* PPBS - Policy-Engine Policy Based Switching Register 2202 * ---------------------------------------------------- 2203 * This register retrieves and sets Policy Based Switching Table entries. 2204 */ 2205 #define MLXSW_REG_PPBS_ID 0x300C 2206 #define MLXSW_REG_PPBS_LEN 0x14 2207 2208 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2209 2210 /* reg_ppbs_pbs_ptr 2211 * Index into the PBS table. 2212 * For Spectrum, the index points to the KVD Linear. 2213 * Access: Index 2214 */ 2215 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2216 2217 /* reg_ppbs_system_port 2218 * Unique port identifier for the final destination of the packet. 2219 * Access: RW 2220 */ 2221 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2222 2223 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2224 u16 system_port) 2225 { 2226 MLXSW_REG_ZERO(ppbs, payload); 2227 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2228 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2229 } 2230 2231 /* PRCR - Policy-Engine Rules Copy Register 2232 * ---------------------------------------- 2233 * This register is used for accessing rules within a TCAM region. 2234 */ 2235 #define MLXSW_REG_PRCR_ID 0x300D 2236 #define MLXSW_REG_PRCR_LEN 0x40 2237 2238 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2239 2240 enum mlxsw_reg_prcr_op { 2241 /* Move rules. Moves the rules from "tcam_region_info" starting 2242 * at offset "offset" to "dest_tcam_region_info" 2243 * at offset "dest_offset." 2244 */ 2245 MLXSW_REG_PRCR_OP_MOVE, 2246 /* Copy rules. Copies the rules from "tcam_region_info" starting 2247 * at offset "offset" to "dest_tcam_region_info" 2248 * at offset "dest_offset." 2249 */ 2250 MLXSW_REG_PRCR_OP_COPY, 2251 }; 2252 2253 /* reg_prcr_op 2254 * Access: OP 2255 */ 2256 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2257 2258 /* reg_prcr_offset 2259 * Offset within the source region to copy/move from. 2260 * Access: Index 2261 */ 2262 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2263 2264 /* reg_prcr_size 2265 * The number of rules to copy/move. 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2269 2270 /* reg_prcr_tcam_region_info 2271 * Opaque object that represents the source TCAM region. 2272 * Access: Index 2273 */ 2274 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2275 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2276 2277 /* reg_prcr_dest_offset 2278 * Offset within the source region to copy/move to. 2279 * Access: Index 2280 */ 2281 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2282 2283 /* reg_prcr_dest_tcam_region_info 2284 * Opaque object that represents the destination TCAM region. 2285 * Access: Index 2286 */ 2287 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2288 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2289 2290 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2291 const char *src_tcam_region_info, 2292 u16 src_offset, 2293 const char *dest_tcam_region_info, 2294 u16 dest_offset, u16 size) 2295 { 2296 MLXSW_REG_ZERO(prcr, payload); 2297 mlxsw_reg_prcr_op_set(payload, op); 2298 mlxsw_reg_prcr_offset_set(payload, src_offset); 2299 mlxsw_reg_prcr_size_set(payload, size); 2300 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2301 src_tcam_region_info); 2302 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2303 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2304 dest_tcam_region_info); 2305 } 2306 2307 /* PEFA - Policy-Engine Extended Flexible Action Register 2308 * ------------------------------------------------------ 2309 * This register is used for accessing an extended flexible action entry 2310 * in the central KVD Linear Database. 2311 */ 2312 #define MLXSW_REG_PEFA_ID 0x300F 2313 #define MLXSW_REG_PEFA_LEN 0xB0 2314 2315 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2316 2317 /* reg_pefa_index 2318 * Index in the KVD Linear Centralized Database. 2319 * Access: Index 2320 */ 2321 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2322 2323 /* reg_pefa_a 2324 * Index in the KVD Linear Centralized Database. 2325 * Activity 2326 * For a new entry: set if ca=0, clear if ca=1 2327 * Set if a packet lookup has hit on the specific entry 2328 * Access: RO 2329 */ 2330 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2331 2332 /* reg_pefa_ca 2333 * Clear activity 2334 * When write: activity is according to this field 2335 * When read: after reading the activity is cleared according to ca 2336 * Access: OP 2337 */ 2338 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2339 2340 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2341 2342 /* reg_pefa_flex_action_set 2343 * Action-set to perform when rule is matched. 2344 * Must be zero padded if action set is shorter. 2345 * Access: RW 2346 */ 2347 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2348 2349 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2350 const char *flex_action_set) 2351 { 2352 MLXSW_REG_ZERO(pefa, payload); 2353 mlxsw_reg_pefa_index_set(payload, index); 2354 mlxsw_reg_pefa_ca_set(payload, ca); 2355 if (flex_action_set) 2356 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2357 flex_action_set); 2358 } 2359 2360 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2361 { 2362 *p_a = mlxsw_reg_pefa_a_get(payload); 2363 } 2364 2365 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2366 * ----------------------------------------------------- 2367 * This register is used for accessing rules within a TCAM region. 2368 * It is a new version of PTCE in order to support wider key, 2369 * mask and action within a TCAM region. This register is not supported 2370 * by SwitchX and SwitchX-2. 2371 */ 2372 #define MLXSW_REG_PTCE2_ID 0x3017 2373 #define MLXSW_REG_PTCE2_LEN 0x1D8 2374 2375 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2376 2377 /* reg_ptce2_v 2378 * Valid. 2379 * Access: RW 2380 */ 2381 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2382 2383 /* reg_ptce2_a 2384 * Activity. Set if a packet lookup has hit on the specific entry. 2385 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2386 * Access: RO 2387 */ 2388 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2389 2390 enum mlxsw_reg_ptce2_op { 2391 /* Read operation. */ 2392 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2393 /* clear on read operation. Used to read entry 2394 * and clear Activity bit. 2395 */ 2396 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2397 /* Write operation. Used to write a new entry to the table. 2398 * All R/W fields are relevant for new entry. Activity bit is set 2399 * for new entries - Note write with v = 0 will delete the entry. 2400 */ 2401 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2402 /* Update action. Only action set will be updated. */ 2403 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2404 /* Clear activity. A bit is cleared for the entry. */ 2405 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2406 }; 2407 2408 /* reg_ptce2_op 2409 * Access: OP 2410 */ 2411 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2412 2413 /* reg_ptce2_offset 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2417 2418 /* reg_ptce2_priority 2419 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2420 * Note: priority does not have to be unique per rule. 2421 * Within a region, higher priority should have lower offset (no limitation 2422 * between regions in a multi-region). 2423 * Access: RW 2424 */ 2425 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2426 2427 /* reg_ptce2_tcam_region_info 2428 * Opaque object that represents the TCAM region. 2429 * Access: Index 2430 */ 2431 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2432 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2433 2434 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2435 2436 /* reg_ptce2_flex_key_blocks 2437 * ACL Key. 2438 * Access: RW 2439 */ 2440 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2441 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2442 2443 /* reg_ptce2_mask 2444 * mask- in the same size as key. A bit that is set directs the TCAM 2445 * to compare the corresponding bit in key. A bit that is clear directs 2446 * the TCAM to ignore the corresponding bit in key. 2447 * Access: RW 2448 */ 2449 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2450 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2451 2452 /* reg_ptce2_flex_action_set 2453 * ACL action set. 2454 * Access: RW 2455 */ 2456 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2457 MLXSW_REG_FLEX_ACTION_SET_LEN); 2458 2459 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2460 enum mlxsw_reg_ptce2_op op, 2461 const char *tcam_region_info, 2462 u16 offset, u32 priority) 2463 { 2464 MLXSW_REG_ZERO(ptce2, payload); 2465 mlxsw_reg_ptce2_v_set(payload, valid); 2466 mlxsw_reg_ptce2_op_set(payload, op); 2467 mlxsw_reg_ptce2_offset_set(payload, offset); 2468 mlxsw_reg_ptce2_priority_set(payload, priority); 2469 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2470 } 2471 2472 /* PERPT - Policy-Engine ERP Table Register 2473 * ---------------------------------------- 2474 * This register adds and removes eRPs from the eRP table. 2475 */ 2476 #define MLXSW_REG_PERPT_ID 0x3021 2477 #define MLXSW_REG_PERPT_LEN 0x80 2478 2479 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2480 2481 /* reg_perpt_erpt_bank 2482 * eRP table bank. 2483 * Range 0 .. cap_max_erp_table_banks - 1 2484 * Access: Index 2485 */ 2486 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2487 2488 /* reg_perpt_erpt_index 2489 * Index to eRP table within the eRP bank. 2490 * Range is 0 .. cap_max_erp_table_bank_size - 1 2491 * Access: Index 2492 */ 2493 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2494 2495 enum mlxsw_reg_perpt_key_size { 2496 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2497 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2498 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2499 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2500 }; 2501 2502 /* reg_perpt_key_size 2503 * Access: OP 2504 */ 2505 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2506 2507 /* reg_perpt_bf_bypass 2508 * 0 - The eRP is used only if bloom filter state is set for the given 2509 * rule. 2510 * 1 - The eRP is used regardless of bloom filter state. 2511 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2512 * Access: RW 2513 */ 2514 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2515 2516 /* reg_perpt_erp_id 2517 * eRP ID for use by the rules. 2518 * Access: RW 2519 */ 2520 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2521 2522 /* reg_perpt_erpt_base_bank 2523 * Base eRP table bank, points to head of erp_vector 2524 * Range is 0 .. cap_max_erp_table_banks - 1 2525 * Access: OP 2526 */ 2527 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2528 2529 /* reg_perpt_erpt_base_index 2530 * Base index to eRP table within the eRP bank 2531 * Range is 0 .. cap_max_erp_table_bank_size - 1 2532 * Access: OP 2533 */ 2534 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2535 2536 /* reg_perpt_erp_index_in_vector 2537 * eRP index in the vector. 2538 * Access: OP 2539 */ 2540 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2541 2542 /* reg_perpt_erp_vector 2543 * eRP vector. 2544 * Access: OP 2545 */ 2546 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2547 2548 /* reg_perpt_mask 2549 * Mask 2550 * 0 - A-TCAM will ignore the bit in key 2551 * 1 - A-TCAM will compare the bit in key 2552 * Access: RW 2553 */ 2554 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2555 2556 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2557 unsigned long *erp_vector, 2558 unsigned long size) 2559 { 2560 unsigned long bit; 2561 2562 for_each_set_bit(bit, erp_vector, size) 2563 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2564 } 2565 2566 static inline void 2567 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2568 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2569 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2570 char *mask) 2571 { 2572 MLXSW_REG_ZERO(perpt, payload); 2573 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2574 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2575 mlxsw_reg_perpt_key_size_set(payload, key_size); 2576 mlxsw_reg_perpt_bf_bypass_set(payload, true); 2577 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2578 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2579 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2580 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2581 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2582 } 2583 2584 /* PERAR - Policy-Engine Region Association Register 2585 * ------------------------------------------------- 2586 * This register associates a hw region for region_id's. Changing on the fly 2587 * is supported by the device. 2588 */ 2589 #define MLXSW_REG_PERAR_ID 0x3026 2590 #define MLXSW_REG_PERAR_LEN 0x08 2591 2592 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2593 2594 /* reg_perar_region_id 2595 * Region identifier 2596 * Range 0 .. cap_max_regions-1 2597 * Access: Index 2598 */ 2599 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2600 2601 static inline unsigned int 2602 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2603 { 2604 return DIV_ROUND_UP(block_num, 4); 2605 } 2606 2607 /* reg_perar_hw_region 2608 * HW Region 2609 * Range 0 .. cap_max_regions-1 2610 * Default: hw_region = region_id 2611 * For a 8 key block region, 2 consecutive regions are used 2612 * For a 12 key block region, 3 consecutive regions are used 2613 * Access: RW 2614 */ 2615 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2616 2617 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2618 u16 hw_region) 2619 { 2620 MLXSW_REG_ZERO(perar, payload); 2621 mlxsw_reg_perar_region_id_set(payload, region_id); 2622 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2623 } 2624 2625 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2626 * ----------------------------------------------------- 2627 * This register is a new version of PTCE-V2 in order to support the 2628 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2629 */ 2630 #define MLXSW_REG_PTCE3_ID 0x3027 2631 #define MLXSW_REG_PTCE3_LEN 0xF0 2632 2633 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2634 2635 /* reg_ptce3_v 2636 * Valid. 2637 * Access: RW 2638 */ 2639 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2640 2641 enum mlxsw_reg_ptce3_op { 2642 /* Write operation. Used to write a new entry to the table. 2643 * All R/W fields are relevant for new entry. Activity bit is set 2644 * for new entries. Write with v = 0 will delete the entry. Must 2645 * not be used if an entry exists. 2646 */ 2647 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2648 /* Update operation */ 2649 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2650 /* Read operation */ 2651 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2652 }; 2653 2654 /* reg_ptce3_op 2655 * Access: OP 2656 */ 2657 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2658 2659 /* reg_ptce3_priority 2660 * Priority of the rule. Higher values win. 2661 * For Spectrum-2 range is 1..cap_kvd_size - 1 2662 * Note: Priority does not have to be unique per rule. 2663 * Access: RW 2664 */ 2665 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2666 2667 /* reg_ptce3_tcam_region_info 2668 * Opaque object that represents the TCAM region. 2669 * Access: Index 2670 */ 2671 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2672 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2673 2674 /* reg_ptce3_flex2_key_blocks 2675 * ACL key. The key must be masked according to eRP (if exists) or 2676 * according to master mask. 2677 * Access: Index 2678 */ 2679 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2680 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2681 2682 /* reg_ptce3_erp_id 2683 * eRP ID. 2684 * Access: Index 2685 */ 2686 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2687 2688 /* reg_ptce3_delta_start 2689 * Start point of delta_value and delta_mask, in bits. Must not exceed 2690 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2691 * Access: Index 2692 */ 2693 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2694 2695 /* reg_ptce3_delta_mask 2696 * Delta mask. 2697 * 0 - Ignore relevant bit in delta_value 2698 * 1 - Compare relevant bit in delta_value 2699 * Delta mask must not be set for reserved fields in the key blocks. 2700 * Note: No delta when no eRPs. Thus, for regions with 2701 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2702 * Access: Index 2703 */ 2704 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2705 2706 /* reg_ptce3_delta_value 2707 * Delta value. 2708 * Bits which are masked by delta_mask must be 0. 2709 * Access: Index 2710 */ 2711 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2712 2713 /* reg_ptce3_prune_vector 2714 * Pruning vector relative to the PERPT.erp_id. 2715 * Used for reducing lookups. 2716 * 0 - NEED: Do a lookup using the eRP. 2717 * 1 - PRUNE: Do not perform a lookup using the eRP. 2718 * Maybe be modified by PEAPBL and PEAPBM. 2719 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2720 * all 1's or all 0's. 2721 * Access: RW 2722 */ 2723 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2724 2725 /* reg_ptce3_prune_ctcam 2726 * Pruning on C-TCAM. Used for reducing lookups. 2727 * 0 - NEED: Do a lookup in the C-TCAM. 2728 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2729 * Access: RW 2730 */ 2731 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2732 2733 /* reg_ptce3_large_exists 2734 * Large entry key ID exists. 2735 * Within the region: 2736 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2737 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2738 * For rule delete: The MSB of the key will be removed. 2739 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2740 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2741 * For rule delete: The MSB of the key will not be removed. 2742 * Access: WO 2743 */ 2744 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2745 2746 /* reg_ptce3_large_entry_key_id 2747 * Large entry key ID. 2748 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2749 * blocks. Must be different for different keys which have the same common 2750 * 6 key blocks (MSB, blocks 6..11) key within a region. 2751 * Range is 0..cap_max_pe_large_key_id - 1 2752 * Access: RW 2753 */ 2754 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2755 2756 /* reg_ptce3_action_pointer 2757 * Pointer to action. 2758 * Range is 0..cap_max_kvd_action_sets - 1 2759 * Access: RW 2760 */ 2761 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2762 2763 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2764 enum mlxsw_reg_ptce3_op op, 2765 u32 priority, 2766 const char *tcam_region_info, 2767 const char *key, u8 erp_id, 2768 bool large_exists, u32 lkey_id, 2769 u32 action_pointer) 2770 { 2771 MLXSW_REG_ZERO(ptce3, payload); 2772 mlxsw_reg_ptce3_v_set(payload, valid); 2773 mlxsw_reg_ptce3_op_set(payload, op); 2774 mlxsw_reg_ptce3_priority_set(payload, priority); 2775 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2776 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2777 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2778 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2779 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2780 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2781 } 2782 2783 /* PERCR - Policy-Engine Region Configuration Register 2784 * --------------------------------------------------- 2785 * This register configures the region parameters. The region_id must be 2786 * allocated. 2787 */ 2788 #define MLXSW_REG_PERCR_ID 0x302A 2789 #define MLXSW_REG_PERCR_LEN 0x80 2790 2791 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2792 2793 /* reg_percr_region_id 2794 * Region identifier. 2795 * Range 0..cap_max_regions-1 2796 * Access: Index 2797 */ 2798 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2799 2800 /* reg_percr_atcam_ignore_prune 2801 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2802 * Access: RW 2803 */ 2804 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2805 2806 /* reg_percr_ctcam_ignore_prune 2807 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2808 * Access: RW 2809 */ 2810 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2811 2812 /* reg_percr_bf_bypass 2813 * Bloom filter bypass. 2814 * 0 - Bloom filter is used (default) 2815 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2816 * region_id or eRP. See PERPT.bf_bypass 2817 * Access: RW 2818 */ 2819 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 2820 2821 /* reg_percr_master_mask 2822 * Master mask. Logical OR mask of all masks of all rules of a region 2823 * (both A-TCAM and C-TCAM). When there are no eRPs 2824 * (erpt_pointer_valid = 0), then this provides the mask. 2825 * Access: RW 2826 */ 2827 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 2828 2829 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 2830 { 2831 MLXSW_REG_ZERO(percr, payload); 2832 mlxsw_reg_percr_region_id_set(payload, region_id); 2833 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 2834 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 2835 mlxsw_reg_percr_bf_bypass_set(payload, true); 2836 } 2837 2838 /* PERERP - Policy-Engine Region eRP Register 2839 * ------------------------------------------ 2840 * This register configures the region eRP. The region_id must be 2841 * allocated. 2842 */ 2843 #define MLXSW_REG_PERERP_ID 0x302B 2844 #define MLXSW_REG_PERERP_LEN 0x1C 2845 2846 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 2847 2848 /* reg_pererp_region_id 2849 * Region identifier. 2850 * Range 0..cap_max_regions-1 2851 * Access: Index 2852 */ 2853 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 2854 2855 /* reg_pererp_ctcam_le 2856 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 2857 * Access: RW 2858 */ 2859 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 2860 2861 /* reg_pererp_erpt_pointer_valid 2862 * erpt_pointer is valid. 2863 * Access: RW 2864 */ 2865 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 2866 2867 /* reg_pererp_erpt_bank_pointer 2868 * Pointer to eRP table bank. May be modified at any time. 2869 * Range 0..cap_max_erp_table_banks-1 2870 * Reserved when erpt_pointer_valid = 0 2871 */ 2872 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 2873 2874 /* reg_pererp_erpt_pointer 2875 * Pointer to eRP table within the eRP bank. Can be changed for an 2876 * existing region. 2877 * Range 0..cap_max_erp_table_size-1 2878 * Reserved when erpt_pointer_valid = 0 2879 * Access: RW 2880 */ 2881 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 2882 2883 /* reg_pererp_erpt_vector 2884 * Vector of allowed eRP indexes starting from erpt_pointer within the 2885 * erpt_bank_pointer. Next entries will be in next bank. 2886 * Note that eRP index is used and not eRP ID. 2887 * Reserved when erpt_pointer_valid = 0 2888 * Access: RW 2889 */ 2890 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 2891 2892 /* reg_pererp_master_rp_id 2893 * Master RP ID. When there are no eRPs, then this provides the eRP ID 2894 * for the lookup. Can be changed for an existing region. 2895 * Reserved when erpt_pointer_valid = 1 2896 * Access: RW 2897 */ 2898 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 2899 2900 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 2901 unsigned long *erp_vector, 2902 unsigned long size) 2903 { 2904 unsigned long bit; 2905 2906 for_each_set_bit(bit, erp_vector, size) 2907 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 2908 } 2909 2910 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 2911 bool ctcam_le, bool erpt_pointer_valid, 2912 u8 erpt_bank_pointer, u8 erpt_pointer, 2913 u8 master_rp_id) 2914 { 2915 MLXSW_REG_ZERO(pererp, payload); 2916 mlxsw_reg_pererp_region_id_set(payload, region_id); 2917 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 2918 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 2919 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 2920 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 2921 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 2922 } 2923 2924 /* IEDR - Infrastructure Entry Delete Register 2925 * ---------------------------------------------------- 2926 * This register is used for deleting entries from the entry tables. 2927 * It is legitimate to attempt to delete a nonexisting entry (the device will 2928 * respond as a good flow). 2929 */ 2930 #define MLXSW_REG_IEDR_ID 0x3804 2931 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 2932 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 2933 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 2934 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 2935 MLXSW_REG_IEDR_REC_LEN * \ 2936 MLXSW_REG_IEDR_REC_MAX_COUNT) 2937 2938 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 2939 2940 /* reg_iedr_num_rec 2941 * Number of records. 2942 * Access: OP 2943 */ 2944 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 2945 2946 /* reg_iedr_rec_type 2947 * Resource type. 2948 * Access: OP 2949 */ 2950 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 2951 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 2952 2953 /* reg_iedr_rec_size 2954 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 2955 * Access: OP 2956 */ 2957 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 2958 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 2959 2960 /* reg_iedr_rec_index_start 2961 * Resource index start. 2962 * Access: OP 2963 */ 2964 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 2965 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 2966 2967 static inline void mlxsw_reg_iedr_pack(char *payload) 2968 { 2969 MLXSW_REG_ZERO(iedr, payload); 2970 } 2971 2972 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 2973 u8 rec_type, u16 rec_size, 2974 u32 rec_index_start) 2975 { 2976 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 2977 2978 if (rec_index >= num_rec) 2979 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 2980 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 2981 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 2982 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 2983 } 2984 2985 /* QPTS - QoS Priority Trust State Register 2986 * ---------------------------------------- 2987 * This register controls the port policy to calculate the switch priority and 2988 * packet color based on incoming packet fields. 2989 */ 2990 #define MLXSW_REG_QPTS_ID 0x4002 2991 #define MLXSW_REG_QPTS_LEN 0x8 2992 2993 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 2994 2995 /* reg_qpts_local_port 2996 * Local port number. 2997 * Access: Index 2998 * 2999 * Note: CPU port is supported. 3000 */ 3001 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3002 3003 enum mlxsw_reg_qpts_trust_state { 3004 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3005 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3006 }; 3007 3008 /* reg_qpts_trust_state 3009 * Trust state for a given port. 3010 * Access: RW 3011 */ 3012 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3013 3014 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3015 enum mlxsw_reg_qpts_trust_state ts) 3016 { 3017 MLXSW_REG_ZERO(qpts, payload); 3018 3019 mlxsw_reg_qpts_local_port_set(payload, local_port); 3020 mlxsw_reg_qpts_trust_state_set(payload, ts); 3021 } 3022 3023 /* QPCR - QoS Policer Configuration Register 3024 * ----------------------------------------- 3025 * The QPCR register is used to create policers - that limit 3026 * the rate of bytes or packets via some trap group. 3027 */ 3028 #define MLXSW_REG_QPCR_ID 0x4004 3029 #define MLXSW_REG_QPCR_LEN 0x28 3030 3031 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3032 3033 enum mlxsw_reg_qpcr_g { 3034 MLXSW_REG_QPCR_G_GLOBAL = 2, 3035 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3036 }; 3037 3038 /* reg_qpcr_g 3039 * The policer type. 3040 * Access: Index 3041 */ 3042 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3043 3044 /* reg_qpcr_pid 3045 * Policer ID. 3046 * Access: Index 3047 */ 3048 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3049 3050 /* reg_qpcr_color_aware 3051 * Is the policer aware of colors. 3052 * Must be 0 (unaware) for cpu port. 3053 * Access: RW for unbounded policer. RO for bounded policer. 3054 */ 3055 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3056 3057 /* reg_qpcr_bytes 3058 * Is policer limit is for bytes per sec or packets per sec. 3059 * 0 - packets 3060 * 1 - bytes 3061 * Access: RW for unbounded policer. RO for bounded policer. 3062 */ 3063 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3064 3065 enum mlxsw_reg_qpcr_ir_units { 3066 MLXSW_REG_QPCR_IR_UNITS_M, 3067 MLXSW_REG_QPCR_IR_UNITS_K, 3068 }; 3069 3070 /* reg_qpcr_ir_units 3071 * Policer's units for cir and eir fields (for bytes limits only) 3072 * 1 - 10^3 3073 * 0 - 10^6 3074 * Access: OP 3075 */ 3076 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3077 3078 enum mlxsw_reg_qpcr_rate_type { 3079 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3080 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3081 }; 3082 3083 /* reg_qpcr_rate_type 3084 * Policer can have one limit (single rate) or 2 limits with specific operation 3085 * for packets that exceed the lower rate but not the upper one. 3086 * (For cpu port must be single rate) 3087 * Access: RW for unbounded policer. RO for bounded policer. 3088 */ 3089 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3090 3091 /* reg_qpc_cbs 3092 * Policer's committed burst size. 3093 * The policer is working with time slices of 50 nano sec. By default every 3094 * slice is granted the proportionate share of the committed rate. If we want to 3095 * allow a slice to exceed that share (while still keeping the rate per sec) we 3096 * can allow burst. The burst size is between the default proportionate share 3097 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3098 * committed rate will result in exceeding the rate). The burst size must be a 3099 * log of 2 and will be determined by 2^cbs. 3100 * Access: RW 3101 */ 3102 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3103 3104 /* reg_qpcr_cir 3105 * Policer's committed rate. 3106 * The rate used for sungle rate, the lower rate for double rate. 3107 * For bytes limits, the rate will be this value * the unit from ir_units. 3108 * (Resolution error is up to 1%). 3109 * Access: RW 3110 */ 3111 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3112 3113 /* reg_qpcr_eir 3114 * Policer's exceed rate. 3115 * The higher rate for double rate, reserved for single rate. 3116 * Lower rate for double rate policer. 3117 * For bytes limits, the rate will be this value * the unit from ir_units. 3118 * (Resolution error is up to 1%). 3119 * Access: RW 3120 */ 3121 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3122 3123 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3124 3125 /* reg_qpcr_exceed_action. 3126 * What to do with packets between the 2 limits for double rate. 3127 * Access: RW for unbounded policer. RO for bounded policer. 3128 */ 3129 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3130 3131 enum mlxsw_reg_qpcr_action { 3132 /* Discard */ 3133 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3134 /* Forward and set color to red. 3135 * If the packet is intended to cpu port, it will be dropped. 3136 */ 3137 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3138 }; 3139 3140 /* reg_qpcr_violate_action 3141 * What to do with packets that cross the cir limit (for single rate) or the eir 3142 * limit (for double rate). 3143 * Access: RW for unbounded policer. RO for bounded policer. 3144 */ 3145 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3146 3147 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3148 enum mlxsw_reg_qpcr_ir_units ir_units, 3149 bool bytes, u32 cir, u16 cbs) 3150 { 3151 MLXSW_REG_ZERO(qpcr, payload); 3152 mlxsw_reg_qpcr_pid_set(payload, pid); 3153 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3154 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3155 mlxsw_reg_qpcr_violate_action_set(payload, 3156 MLXSW_REG_QPCR_ACTION_DISCARD); 3157 mlxsw_reg_qpcr_cir_set(payload, cir); 3158 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3159 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3160 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3161 } 3162 3163 /* QTCT - QoS Switch Traffic Class Table 3164 * ------------------------------------- 3165 * Configures the mapping between the packet switch priority and the 3166 * traffic class on the transmit port. 3167 */ 3168 #define MLXSW_REG_QTCT_ID 0x400A 3169 #define MLXSW_REG_QTCT_LEN 0x08 3170 3171 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3172 3173 /* reg_qtct_local_port 3174 * Local port number. 3175 * Access: Index 3176 * 3177 * Note: CPU port is not supported. 3178 */ 3179 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3180 3181 /* reg_qtct_sub_port 3182 * Virtual port within the physical port. 3183 * Should be set to 0 when virtual ports are not enabled on the port. 3184 * Access: Index 3185 */ 3186 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3187 3188 /* reg_qtct_switch_prio 3189 * Switch priority. 3190 * Access: Index 3191 */ 3192 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3193 3194 /* reg_qtct_tclass 3195 * Traffic class. 3196 * Default values: 3197 * switch_prio 0 : tclass 1 3198 * switch_prio 1 : tclass 0 3199 * switch_prio i : tclass i, for i > 1 3200 * Access: RW 3201 */ 3202 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3203 3204 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3205 u8 switch_prio, u8 tclass) 3206 { 3207 MLXSW_REG_ZERO(qtct, payload); 3208 mlxsw_reg_qtct_local_port_set(payload, local_port); 3209 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3210 mlxsw_reg_qtct_tclass_set(payload, tclass); 3211 } 3212 3213 /* QEEC - QoS ETS Element Configuration Register 3214 * --------------------------------------------- 3215 * Configures the ETS elements. 3216 */ 3217 #define MLXSW_REG_QEEC_ID 0x400D 3218 #define MLXSW_REG_QEEC_LEN 0x1C 3219 3220 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3221 3222 /* reg_qeec_local_port 3223 * Local port number. 3224 * Access: Index 3225 * 3226 * Note: CPU port is supported. 3227 */ 3228 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3229 3230 enum mlxsw_reg_qeec_hr { 3231 MLXSW_REG_QEEC_HIERARCY_PORT, 3232 MLXSW_REG_QEEC_HIERARCY_GROUP, 3233 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3234 MLXSW_REG_QEEC_HIERARCY_TC, 3235 }; 3236 3237 /* reg_qeec_element_hierarchy 3238 * 0 - Port 3239 * 1 - Group 3240 * 2 - Subgroup 3241 * 3 - Traffic Class 3242 * Access: Index 3243 */ 3244 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3245 3246 /* reg_qeec_element_index 3247 * The index of the element in the hierarchy. 3248 * Access: Index 3249 */ 3250 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3251 3252 /* reg_qeec_next_element_index 3253 * The index of the next (lower) element in the hierarchy. 3254 * Access: RW 3255 * 3256 * Note: Reserved for element_hierarchy 0. 3257 */ 3258 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3259 3260 enum { 3261 MLXSW_REG_QEEC_BYTES_MODE, 3262 MLXSW_REG_QEEC_PACKETS_MODE, 3263 }; 3264 3265 /* reg_qeec_pb 3266 * Packets or bytes mode. 3267 * 0 - Bytes mode 3268 * 1 - Packets mode 3269 * Access: RW 3270 * 3271 * Note: Used for max shaper configuration. For Spectrum, packets mode 3272 * is supported only for traffic classes of CPU port. 3273 */ 3274 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3275 3276 /* reg_qeec_mase 3277 * Max shaper configuration enable. Enables configuration of the max 3278 * shaper on this ETS element. 3279 * 0 - Disable 3280 * 1 - Enable 3281 * Access: RW 3282 */ 3283 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3284 3285 /* A large max rate will disable the max shaper. */ 3286 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3287 3288 /* reg_qeec_max_shaper_rate 3289 * Max shaper information rate. 3290 * For CPU port, can only be configured for port hierarchy. 3291 * When in bytes mode, value is specified in units of 1000bps. 3292 * Access: RW 3293 */ 3294 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3295 3296 /* reg_qeec_de 3297 * DWRR configuration enable. Enables configuration of the dwrr and 3298 * dwrr_weight. 3299 * 0 - Disable 3300 * 1 - Enable 3301 * Access: RW 3302 */ 3303 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3304 3305 /* reg_qeec_dwrr 3306 * Transmission selection algorithm to use on the link going down from 3307 * the ETS element. 3308 * 0 - Strict priority 3309 * 1 - DWRR 3310 * Access: RW 3311 */ 3312 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3313 3314 /* reg_qeec_dwrr_weight 3315 * DWRR weight on the link going down from the ETS element. The 3316 * percentage of bandwidth guaranteed to an ETS element within 3317 * its hierarchy. The sum of all weights across all ETS elements 3318 * within one hierarchy should be equal to 100. Reserved when 3319 * transmission selection algorithm is strict priority. 3320 * Access: RW 3321 */ 3322 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3323 3324 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3325 enum mlxsw_reg_qeec_hr hr, u8 index, 3326 u8 next_index) 3327 { 3328 MLXSW_REG_ZERO(qeec, payload); 3329 mlxsw_reg_qeec_local_port_set(payload, local_port); 3330 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3331 mlxsw_reg_qeec_element_index_set(payload, index); 3332 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3333 } 3334 3335 /* QRWE - QoS ReWrite Enable 3336 * ------------------------- 3337 * This register configures the rewrite enable per receive port. 3338 */ 3339 #define MLXSW_REG_QRWE_ID 0x400F 3340 #define MLXSW_REG_QRWE_LEN 0x08 3341 3342 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3343 3344 /* reg_qrwe_local_port 3345 * Local port number. 3346 * Access: Index 3347 * 3348 * Note: CPU port is supported. No support for router port. 3349 */ 3350 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3351 3352 /* reg_qrwe_dscp 3353 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3354 * Access: RW 3355 */ 3356 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3357 3358 /* reg_qrwe_pcp 3359 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3360 * Access: RW 3361 */ 3362 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3363 3364 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3365 bool rewrite_pcp, bool rewrite_dscp) 3366 { 3367 MLXSW_REG_ZERO(qrwe, payload); 3368 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3369 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3370 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3371 } 3372 3373 /* QPDSM - QoS Priority to DSCP Mapping 3374 * ------------------------------------ 3375 * QoS Priority to DSCP Mapping Register 3376 */ 3377 #define MLXSW_REG_QPDSM_ID 0x4011 3378 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3379 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3380 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3381 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3382 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3383 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3384 3385 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3386 3387 /* reg_qpdsm_local_port 3388 * Local Port. Supported for data packets from CPU port. 3389 * Access: Index 3390 */ 3391 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3392 3393 /* reg_qpdsm_prio_entry_color0_e 3394 * Enable update of the entry for color 0 and a given port. 3395 * Access: WO 3396 */ 3397 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3398 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3399 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3400 3401 /* reg_qpdsm_prio_entry_color0_dscp 3402 * DSCP field in the outer label of the packet for color 0 and a given port. 3403 * Reserved when e=0. 3404 * Access: RW 3405 */ 3406 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3407 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3408 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3409 3410 /* reg_qpdsm_prio_entry_color1_e 3411 * Enable update of the entry for color 1 and a given port. 3412 * Access: WO 3413 */ 3414 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3415 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3416 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3417 3418 /* reg_qpdsm_prio_entry_color1_dscp 3419 * DSCP field in the outer label of the packet for color 1 and a given port. 3420 * Reserved when e=0. 3421 * Access: RW 3422 */ 3423 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3424 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3425 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3426 3427 /* reg_qpdsm_prio_entry_color2_e 3428 * Enable update of the entry for color 2 and a given port. 3429 * Access: WO 3430 */ 3431 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3432 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3433 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3434 3435 /* reg_qpdsm_prio_entry_color2_dscp 3436 * DSCP field in the outer label of the packet for color 2 and a given port. 3437 * Reserved when e=0. 3438 * Access: RW 3439 */ 3440 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3441 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3442 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3443 3444 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3445 { 3446 MLXSW_REG_ZERO(qpdsm, payload); 3447 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3448 } 3449 3450 static inline void 3451 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3452 { 3453 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3454 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3455 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3456 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3457 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3458 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3459 } 3460 3461 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3462 * -------------------------------------------------- 3463 * This register controls the mapping from DSCP field to 3464 * Switch Priority for IP packets. 3465 */ 3466 #define MLXSW_REG_QPDPM_ID 0x4013 3467 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3468 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3469 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3470 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3471 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3472 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3473 3474 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3475 3476 /* reg_qpdpm_local_port 3477 * Local Port. Supported for data packets from CPU port. 3478 * Access: Index 3479 */ 3480 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3481 3482 /* reg_qpdpm_dscp_e 3483 * Enable update of the specific entry. When cleared, the switch_prio and color 3484 * fields are ignored and the previous switch_prio and color values are 3485 * preserved. 3486 * Access: WO 3487 */ 3488 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3489 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3490 3491 /* reg_qpdpm_dscp_prio 3492 * The new Switch Priority value for the relevant DSCP value. 3493 * Access: RW 3494 */ 3495 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3496 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3497 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3498 3499 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3500 { 3501 MLXSW_REG_ZERO(qpdpm, payload); 3502 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3503 } 3504 3505 static inline void 3506 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3507 { 3508 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3509 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3510 } 3511 3512 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3513 * ------------------------------------------------------------------ 3514 * This register configures if the Switch Priority to Traffic Class mapping is 3515 * based on Multicast packet indication. If so, then multicast packets will get 3516 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3517 * QTCT. 3518 * By default, Switch Priority to Traffic Class mapping is not based on 3519 * Multicast packet indication. 3520 */ 3521 #define MLXSW_REG_QTCTM_ID 0x401A 3522 #define MLXSW_REG_QTCTM_LEN 0x08 3523 3524 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3525 3526 /* reg_qtctm_local_port 3527 * Local port number. 3528 * No support for CPU port. 3529 * Access: Index 3530 */ 3531 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3532 3533 /* reg_qtctm_mc 3534 * Multicast Mode 3535 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3536 * indication (default is 0, not based on Multicast packet indication). 3537 */ 3538 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3539 3540 static inline void 3541 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3542 { 3543 MLXSW_REG_ZERO(qtctm, payload); 3544 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3545 mlxsw_reg_qtctm_mc_set(payload, mc); 3546 } 3547 3548 /* PMLP - Ports Module to Local Port Register 3549 * ------------------------------------------ 3550 * Configures the assignment of modules to local ports. 3551 */ 3552 #define MLXSW_REG_PMLP_ID 0x5002 3553 #define MLXSW_REG_PMLP_LEN 0x40 3554 3555 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3556 3557 /* reg_pmlp_rxtx 3558 * 0 - Tx value is used for both Tx and Rx. 3559 * 1 - Rx value is taken from a separte field. 3560 * Access: RW 3561 */ 3562 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3563 3564 /* reg_pmlp_local_port 3565 * Local port number. 3566 * Access: Index 3567 */ 3568 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3569 3570 /* reg_pmlp_width 3571 * 0 - Unmap local port. 3572 * 1 - Lane 0 is used. 3573 * 2 - Lanes 0 and 1 are used. 3574 * 4 - Lanes 0, 1, 2 and 3 are used. 3575 * Access: RW 3576 */ 3577 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3578 3579 /* reg_pmlp_module 3580 * Module number. 3581 * Access: RW 3582 */ 3583 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3584 3585 /* reg_pmlp_tx_lane 3586 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3587 * Access: RW 3588 */ 3589 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3590 3591 /* reg_pmlp_rx_lane 3592 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3593 * equal to Tx lane. 3594 * Access: RW 3595 */ 3596 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3597 3598 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3599 { 3600 MLXSW_REG_ZERO(pmlp, payload); 3601 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3602 } 3603 3604 /* PMTU - Port MTU Register 3605 * ------------------------ 3606 * Configures and reports the port MTU. 3607 */ 3608 #define MLXSW_REG_PMTU_ID 0x5003 3609 #define MLXSW_REG_PMTU_LEN 0x10 3610 3611 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3612 3613 /* reg_pmtu_local_port 3614 * Local port number. 3615 * Access: Index 3616 */ 3617 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3618 3619 /* reg_pmtu_max_mtu 3620 * Maximum MTU. 3621 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3622 * reported, otherwise the minimum between the max_mtu of the different 3623 * types is reported. 3624 * Access: RO 3625 */ 3626 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3627 3628 /* reg_pmtu_admin_mtu 3629 * MTU value to set port to. Must be smaller or equal to max_mtu. 3630 * Note: If port type is Infiniband, then port must be disabled, when its 3631 * MTU is set. 3632 * Access: RW 3633 */ 3634 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3635 3636 /* reg_pmtu_oper_mtu 3637 * The actual MTU configured on the port. Packets exceeding this size 3638 * will be dropped. 3639 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3640 * oper_mtu might be smaller than admin_mtu. 3641 * Access: RO 3642 */ 3643 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3644 3645 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3646 u16 new_mtu) 3647 { 3648 MLXSW_REG_ZERO(pmtu, payload); 3649 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3650 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3651 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3652 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3653 } 3654 3655 /* PTYS - Port Type and Speed Register 3656 * ----------------------------------- 3657 * Configures and reports the port speed type. 3658 * 3659 * Note: When set while the link is up, the changes will not take effect 3660 * until the port transitions from down to up state. 3661 */ 3662 #define MLXSW_REG_PTYS_ID 0x5004 3663 #define MLXSW_REG_PTYS_LEN 0x40 3664 3665 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3666 3667 /* an_disable_admin 3668 * Auto negotiation disable administrative configuration 3669 * 0 - Device doesn't support AN disable. 3670 * 1 - Device supports AN disable. 3671 * Access: RW 3672 */ 3673 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3674 3675 /* reg_ptys_local_port 3676 * Local port number. 3677 * Access: Index 3678 */ 3679 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3680 3681 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3682 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3683 3684 /* reg_ptys_proto_mask 3685 * Protocol mask. Indicates which protocol is used. 3686 * 0 - Infiniband. 3687 * 1 - Fibre Channel. 3688 * 2 - Ethernet. 3689 * Access: Index 3690 */ 3691 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3692 3693 enum { 3694 MLXSW_REG_PTYS_AN_STATUS_NA, 3695 MLXSW_REG_PTYS_AN_STATUS_OK, 3696 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3697 }; 3698 3699 /* reg_ptys_an_status 3700 * Autonegotiation status. 3701 * Access: RO 3702 */ 3703 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3704 3705 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3706 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3707 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3708 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3709 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3710 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3711 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 3712 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 3713 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 3714 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 3715 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 3716 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 3717 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 3718 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 3719 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 3720 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 3721 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 3722 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 3723 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 3724 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 3725 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 3726 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 3727 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 3728 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 3729 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 3730 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 3731 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 3732 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 3733 3734 /* reg_ptys_eth_proto_cap 3735 * Ethernet port supported speeds and protocols. 3736 * Access: RO 3737 */ 3738 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 3739 3740 /* reg_ptys_ib_link_width_cap 3741 * IB port supported widths. 3742 * Access: RO 3743 */ 3744 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 3745 3746 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 3747 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 3748 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 3749 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 3750 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 3751 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 3752 3753 /* reg_ptys_ib_proto_cap 3754 * IB port supported speeds and protocols. 3755 * Access: RO 3756 */ 3757 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 3758 3759 /* reg_ptys_eth_proto_admin 3760 * Speed and protocol to set port to. 3761 * Access: RW 3762 */ 3763 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 3764 3765 /* reg_ptys_ib_link_width_admin 3766 * IB width to set port to. 3767 * Access: RW 3768 */ 3769 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 3770 3771 /* reg_ptys_ib_proto_admin 3772 * IB speeds and protocols to set port to. 3773 * Access: RW 3774 */ 3775 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 3776 3777 /* reg_ptys_eth_proto_oper 3778 * The current speed and protocol configured for the port. 3779 * Access: RO 3780 */ 3781 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 3782 3783 /* reg_ptys_ib_link_width_oper 3784 * The current IB width to set port to. 3785 * Access: RO 3786 */ 3787 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 3788 3789 /* reg_ptys_ib_proto_oper 3790 * The current IB speed and protocol. 3791 * Access: RO 3792 */ 3793 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 3794 3795 /* reg_ptys_eth_proto_lp_advertise 3796 * The protocols that were advertised by the link partner during 3797 * autonegotiation. 3798 * Access: RO 3799 */ 3800 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3801 3802 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3803 u32 proto_admin, bool autoneg) 3804 { 3805 MLXSW_REG_ZERO(ptys, payload); 3806 mlxsw_reg_ptys_local_port_set(payload, local_port); 3807 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 3808 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 3809 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 3810 } 3811 3812 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 3813 u32 *p_eth_proto_cap, 3814 u32 *p_eth_proto_adm, 3815 u32 *p_eth_proto_oper) 3816 { 3817 if (p_eth_proto_cap) 3818 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 3819 if (p_eth_proto_adm) 3820 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 3821 if (p_eth_proto_oper) 3822 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 3823 } 3824 3825 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 3826 u16 proto_admin, u16 link_width) 3827 { 3828 MLXSW_REG_ZERO(ptys, payload); 3829 mlxsw_reg_ptys_local_port_set(payload, local_port); 3830 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 3831 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 3832 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 3833 } 3834 3835 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 3836 u16 *p_ib_link_width_cap, 3837 u16 *p_ib_proto_oper, 3838 u16 *p_ib_link_width_oper) 3839 { 3840 if (p_ib_proto_cap) 3841 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 3842 if (p_ib_link_width_cap) 3843 *p_ib_link_width_cap = 3844 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 3845 if (p_ib_proto_oper) 3846 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 3847 if (p_ib_link_width_oper) 3848 *p_ib_link_width_oper = 3849 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 3850 } 3851 3852 /* PPAD - Port Physical Address Register 3853 * ------------------------------------- 3854 * The PPAD register configures the per port physical MAC address. 3855 */ 3856 #define MLXSW_REG_PPAD_ID 0x5005 3857 #define MLXSW_REG_PPAD_LEN 0x10 3858 3859 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 3860 3861 /* reg_ppad_single_base_mac 3862 * 0: base_mac, local port should be 0 and mac[7:0] is 3863 * reserved. HW will set incremental 3864 * 1: single_mac - mac of the local_port 3865 * Access: RW 3866 */ 3867 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 3868 3869 /* reg_ppad_local_port 3870 * port number, if single_base_mac = 0 then local_port is reserved 3871 * Access: RW 3872 */ 3873 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 3874 3875 /* reg_ppad_mac 3876 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 3877 * If single_base_mac = 1 - the per port MAC address 3878 * Access: RW 3879 */ 3880 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 3881 3882 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 3883 u8 local_port) 3884 { 3885 MLXSW_REG_ZERO(ppad, payload); 3886 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 3887 mlxsw_reg_ppad_local_port_set(payload, local_port); 3888 } 3889 3890 /* PAOS - Ports Administrative and Operational Status Register 3891 * ----------------------------------------------------------- 3892 * Configures and retrieves per port administrative and operational status. 3893 */ 3894 #define MLXSW_REG_PAOS_ID 0x5006 3895 #define MLXSW_REG_PAOS_LEN 0x10 3896 3897 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 3898 3899 /* reg_paos_swid 3900 * Switch partition ID with which to associate the port. 3901 * Note: while external ports uses unique local port numbers (and thus swid is 3902 * redundant), router ports use the same local port number where swid is the 3903 * only indication for the relevant port. 3904 * Access: Index 3905 */ 3906 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 3907 3908 /* reg_paos_local_port 3909 * Local port number. 3910 * Access: Index 3911 */ 3912 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 3913 3914 /* reg_paos_admin_status 3915 * Port administrative state (the desired state of the port): 3916 * 1 - Up. 3917 * 2 - Down. 3918 * 3 - Up once. This means that in case of link failure, the port won't go 3919 * into polling mode, but will wait to be re-enabled by software. 3920 * 4 - Disabled by system. Can only be set by hardware. 3921 * Access: RW 3922 */ 3923 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 3924 3925 /* reg_paos_oper_status 3926 * Port operational state (the current state): 3927 * 1 - Up. 3928 * 2 - Down. 3929 * 3 - Down by port failure. This means that the device will not let the 3930 * port up again until explicitly specified by software. 3931 * Access: RO 3932 */ 3933 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 3934 3935 /* reg_paos_ase 3936 * Admin state update enabled. 3937 * Access: WO 3938 */ 3939 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 3940 3941 /* reg_paos_ee 3942 * Event update enable. If this bit is set, event generation will be 3943 * updated based on the e field. 3944 * Access: WO 3945 */ 3946 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 3947 3948 /* reg_paos_e 3949 * Event generation on operational state change: 3950 * 0 - Do not generate event. 3951 * 1 - Generate Event. 3952 * 2 - Generate Single Event. 3953 * Access: RW 3954 */ 3955 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 3956 3957 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 3958 enum mlxsw_port_admin_status status) 3959 { 3960 MLXSW_REG_ZERO(paos, payload); 3961 mlxsw_reg_paos_swid_set(payload, 0); 3962 mlxsw_reg_paos_local_port_set(payload, local_port); 3963 mlxsw_reg_paos_admin_status_set(payload, status); 3964 mlxsw_reg_paos_oper_status_set(payload, 0); 3965 mlxsw_reg_paos_ase_set(payload, 1); 3966 mlxsw_reg_paos_ee_set(payload, 1); 3967 mlxsw_reg_paos_e_set(payload, 1); 3968 } 3969 3970 /* PFCC - Ports Flow Control Configuration Register 3971 * ------------------------------------------------ 3972 * Configures and retrieves the per port flow control configuration. 3973 */ 3974 #define MLXSW_REG_PFCC_ID 0x5007 3975 #define MLXSW_REG_PFCC_LEN 0x20 3976 3977 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 3978 3979 /* reg_pfcc_local_port 3980 * Local port number. 3981 * Access: Index 3982 */ 3983 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 3984 3985 /* reg_pfcc_pnat 3986 * Port number access type. Determines the way local_port is interpreted: 3987 * 0 - Local port number. 3988 * 1 - IB / label port number. 3989 * Access: Index 3990 */ 3991 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 3992 3993 /* reg_pfcc_shl_cap 3994 * Send to higher layers capabilities: 3995 * 0 - No capability of sending Pause and PFC frames to higher layers. 3996 * 1 - Device has capability of sending Pause and PFC frames to higher 3997 * layers. 3998 * Access: RO 3999 */ 4000 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4001 4002 /* reg_pfcc_shl_opr 4003 * Send to higher layers operation: 4004 * 0 - Pause and PFC frames are handled by the port (default). 4005 * 1 - Pause and PFC frames are handled by the port and also sent to 4006 * higher layers. Only valid if shl_cap = 1. 4007 * Access: RW 4008 */ 4009 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4010 4011 /* reg_pfcc_ppan 4012 * Pause policy auto negotiation. 4013 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4014 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4015 * based on the auto-negotiation resolution. 4016 * Access: RW 4017 * 4018 * Note: The auto-negotiation advertisement is set according to pptx and 4019 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4020 */ 4021 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4022 4023 /* reg_pfcc_prio_mask_tx 4024 * Bit per priority indicating if Tx flow control policy should be 4025 * updated based on bit pfctx. 4026 * Access: WO 4027 */ 4028 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4029 4030 /* reg_pfcc_prio_mask_rx 4031 * Bit per priority indicating if Rx flow control policy should be 4032 * updated based on bit pfcrx. 4033 * Access: WO 4034 */ 4035 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4036 4037 /* reg_pfcc_pptx 4038 * Admin Pause policy on Tx. 4039 * 0 - Never generate Pause frames (default). 4040 * 1 - Generate Pause frames according to Rx buffer threshold. 4041 * Access: RW 4042 */ 4043 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4044 4045 /* reg_pfcc_aptx 4046 * Active (operational) Pause policy on Tx. 4047 * 0 - Never generate Pause frames. 4048 * 1 - Generate Pause frames according to Rx buffer threshold. 4049 * Access: RO 4050 */ 4051 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4052 4053 /* reg_pfcc_pfctx 4054 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4055 * 0 - Never generate priority Pause frames on the specified priority 4056 * (default). 4057 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4058 * the specified priority. 4059 * Access: RW 4060 * 4061 * Note: pfctx and pptx must be mutually exclusive. 4062 */ 4063 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4064 4065 /* reg_pfcc_pprx 4066 * Admin Pause policy on Rx. 4067 * 0 - Ignore received Pause frames (default). 4068 * 1 - Respect received Pause frames. 4069 * Access: RW 4070 */ 4071 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4072 4073 /* reg_pfcc_aprx 4074 * Active (operational) Pause policy on Rx. 4075 * 0 - Ignore received Pause frames. 4076 * 1 - Respect received Pause frames. 4077 * Access: RO 4078 */ 4079 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4080 4081 /* reg_pfcc_pfcrx 4082 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4083 * 0 - Ignore incoming priority Pause frames on the specified priority 4084 * (default). 4085 * 1 - Respect incoming priority Pause frames on the specified priority. 4086 * Access: RW 4087 */ 4088 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4089 4090 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4091 4092 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4093 { 4094 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4095 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4096 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4097 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4098 } 4099 4100 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4101 { 4102 MLXSW_REG_ZERO(pfcc, payload); 4103 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4104 } 4105 4106 /* PPCNT - Ports Performance Counters Register 4107 * ------------------------------------------- 4108 * The PPCNT register retrieves per port performance counters. 4109 */ 4110 #define MLXSW_REG_PPCNT_ID 0x5008 4111 #define MLXSW_REG_PPCNT_LEN 0x100 4112 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4113 4114 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4115 4116 /* reg_ppcnt_swid 4117 * For HCA: must be always 0. 4118 * Switch partition ID to associate port with. 4119 * Switch partitions are numbered from 0 to 7 inclusively. 4120 * Switch partition 254 indicates stacking ports. 4121 * Switch partition 255 indicates all switch partitions. 4122 * Only valid on Set() operation with local_port=255. 4123 * Access: Index 4124 */ 4125 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4126 4127 /* reg_ppcnt_local_port 4128 * Local port number. 4129 * 255 indicates all ports on the device, and is only allowed 4130 * for Set() operation. 4131 * Access: Index 4132 */ 4133 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4134 4135 /* reg_ppcnt_pnat 4136 * Port number access type: 4137 * 0 - Local port number 4138 * 1 - IB port number 4139 * Access: Index 4140 */ 4141 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4142 4143 enum mlxsw_reg_ppcnt_grp { 4144 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4145 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4146 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4147 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4148 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4149 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4150 }; 4151 4152 /* reg_ppcnt_grp 4153 * Performance counter group. 4154 * Group 63 indicates all groups. Only valid on Set() operation with 4155 * clr bit set. 4156 * 0x0: IEEE 802.3 Counters 4157 * 0x1: RFC 2863 Counters 4158 * 0x2: RFC 2819 Counters 4159 * 0x3: RFC 3635 Counters 4160 * 0x5: Ethernet Extended Counters 4161 * 0x8: Link Level Retransmission Counters 4162 * 0x10: Per Priority Counters 4163 * 0x11: Per Traffic Class Counters 4164 * 0x12: Physical Layer Counters 4165 * 0x13: Per Traffic Class Congestion Counters 4166 * Access: Index 4167 */ 4168 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4169 4170 /* reg_ppcnt_clr 4171 * Clear counters. Setting the clr bit will reset the counter value 4172 * for all counters in the counter group. This bit can be set 4173 * for both Set() and Get() operation. 4174 * Access: OP 4175 */ 4176 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4177 4178 /* reg_ppcnt_prio_tc 4179 * Priority for counter set that support per priority, valid values: 0-7. 4180 * Traffic class for counter set that support per traffic class, 4181 * valid values: 0- cap_max_tclass-1 . 4182 * For HCA: cap_max_tclass is always 8. 4183 * Otherwise must be 0. 4184 * Access: Index 4185 */ 4186 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4187 4188 /* Ethernet IEEE 802.3 Counter Group */ 4189 4190 /* reg_ppcnt_a_frames_transmitted_ok 4191 * Access: RO 4192 */ 4193 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4194 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4195 4196 /* reg_ppcnt_a_frames_received_ok 4197 * Access: RO 4198 */ 4199 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4200 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4201 4202 /* reg_ppcnt_a_frame_check_sequence_errors 4203 * Access: RO 4204 */ 4205 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4206 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4207 4208 /* reg_ppcnt_a_alignment_errors 4209 * Access: RO 4210 */ 4211 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4212 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4213 4214 /* reg_ppcnt_a_octets_transmitted_ok 4215 * Access: RO 4216 */ 4217 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4218 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4219 4220 /* reg_ppcnt_a_octets_received_ok 4221 * Access: RO 4222 */ 4223 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4224 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4225 4226 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4227 * Access: RO 4228 */ 4229 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4230 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4231 4232 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4233 * Access: RO 4234 */ 4235 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4236 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4237 4238 /* reg_ppcnt_a_multicast_frames_received_ok 4239 * Access: RO 4240 */ 4241 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4242 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4243 4244 /* reg_ppcnt_a_broadcast_frames_received_ok 4245 * Access: RO 4246 */ 4247 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4248 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4249 4250 /* reg_ppcnt_a_in_range_length_errors 4251 * Access: RO 4252 */ 4253 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4254 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4255 4256 /* reg_ppcnt_a_out_of_range_length_field 4257 * Access: RO 4258 */ 4259 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4260 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4261 4262 /* reg_ppcnt_a_frame_too_long_errors 4263 * Access: RO 4264 */ 4265 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4266 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4267 4268 /* reg_ppcnt_a_symbol_error_during_carrier 4269 * Access: RO 4270 */ 4271 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4272 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4273 4274 /* reg_ppcnt_a_mac_control_frames_transmitted 4275 * Access: RO 4276 */ 4277 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4278 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4279 4280 /* reg_ppcnt_a_mac_control_frames_received 4281 * Access: RO 4282 */ 4283 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4284 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4285 4286 /* reg_ppcnt_a_unsupported_opcodes_received 4287 * Access: RO 4288 */ 4289 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4290 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4291 4292 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4293 * Access: RO 4294 */ 4295 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4296 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4297 4298 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4299 * Access: RO 4300 */ 4301 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4302 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4303 4304 /* Ethernet RFC 2819 Counter Group */ 4305 4306 /* reg_ppcnt_ether_stats_pkts64octets 4307 * Access: RO 4308 */ 4309 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4311 4312 /* reg_ppcnt_ether_stats_pkts65to127octets 4313 * Access: RO 4314 */ 4315 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4317 4318 /* reg_ppcnt_ether_stats_pkts128to255octets 4319 * Access: RO 4320 */ 4321 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4322 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4323 4324 /* reg_ppcnt_ether_stats_pkts256to511octets 4325 * Access: RO 4326 */ 4327 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4328 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4329 4330 /* reg_ppcnt_ether_stats_pkts512to1023octets 4331 * Access: RO 4332 */ 4333 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4334 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4335 4336 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4337 * Access: RO 4338 */ 4339 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4340 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4341 4342 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4343 * Access: RO 4344 */ 4345 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4346 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4347 4348 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4349 * Access: RO 4350 */ 4351 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4352 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4353 4354 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4355 * Access: RO 4356 */ 4357 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4358 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4359 4360 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4361 * Access: RO 4362 */ 4363 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4364 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4365 4366 /* Ethernet Extended Counter Group Counters */ 4367 4368 /* reg_ppcnt_ecn_marked 4369 * Access: RO 4370 */ 4371 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4372 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4373 4374 /* Ethernet Per Priority Group Counters */ 4375 4376 /* reg_ppcnt_rx_octets 4377 * Access: RO 4378 */ 4379 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4380 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4381 4382 /* reg_ppcnt_rx_frames 4383 * Access: RO 4384 */ 4385 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4386 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4387 4388 /* reg_ppcnt_tx_octets 4389 * Access: RO 4390 */ 4391 MLXSW_ITEM64(reg, ppcnt, tx_octets, 4392 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4393 4394 /* reg_ppcnt_tx_frames 4395 * Access: RO 4396 */ 4397 MLXSW_ITEM64(reg, ppcnt, tx_frames, 4398 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4399 4400 /* reg_ppcnt_rx_pause 4401 * Access: RO 4402 */ 4403 MLXSW_ITEM64(reg, ppcnt, rx_pause, 4404 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4405 4406 /* reg_ppcnt_rx_pause_duration 4407 * Access: RO 4408 */ 4409 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 4410 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4411 4412 /* reg_ppcnt_tx_pause 4413 * Access: RO 4414 */ 4415 MLXSW_ITEM64(reg, ppcnt, tx_pause, 4416 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4417 4418 /* reg_ppcnt_tx_pause_duration 4419 * Access: RO 4420 */ 4421 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 4422 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4423 4424 /* reg_ppcnt_rx_pause_transition 4425 * Access: RO 4426 */ 4427 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 4428 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4429 4430 /* Ethernet Per Traffic Group Counters */ 4431 4432 /* reg_ppcnt_tc_transmit_queue 4433 * Contains the transmit queue depth in cells of traffic class 4434 * selected by prio_tc and the port selected by local_port. 4435 * The field cannot be cleared. 4436 * Access: RO 4437 */ 4438 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 4439 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4440 4441 /* reg_ppcnt_tc_no_buffer_discard_uc 4442 * The number of unicast packets dropped due to lack of shared 4443 * buffer resources. 4444 * Access: RO 4445 */ 4446 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 4447 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4448 4449 /* Ethernet Per Traffic Class Congestion Group Counters */ 4450 4451 /* reg_ppcnt_wred_discard 4452 * Access: RO 4453 */ 4454 MLXSW_ITEM64(reg, ppcnt, wred_discard, 4455 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4456 4457 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 4458 enum mlxsw_reg_ppcnt_grp grp, 4459 u8 prio_tc) 4460 { 4461 MLXSW_REG_ZERO(ppcnt, payload); 4462 mlxsw_reg_ppcnt_swid_set(payload, 0); 4463 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 4464 mlxsw_reg_ppcnt_pnat_set(payload, 0); 4465 mlxsw_reg_ppcnt_grp_set(payload, grp); 4466 mlxsw_reg_ppcnt_clr_set(payload, 0); 4467 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 4468 } 4469 4470 /* PLIB - Port Local to InfiniBand Port 4471 * ------------------------------------ 4472 * The PLIB register performs mapping from Local Port into InfiniBand Port. 4473 */ 4474 #define MLXSW_REG_PLIB_ID 0x500A 4475 #define MLXSW_REG_PLIB_LEN 0x10 4476 4477 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 4478 4479 /* reg_plib_local_port 4480 * Local port number. 4481 * Access: Index 4482 */ 4483 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 4484 4485 /* reg_plib_ib_port 4486 * InfiniBand port remapping for local_port. 4487 * Access: RW 4488 */ 4489 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 4490 4491 /* PPTB - Port Prio To Buffer Register 4492 * ----------------------------------- 4493 * Configures the switch priority to buffer table. 4494 */ 4495 #define MLXSW_REG_PPTB_ID 0x500B 4496 #define MLXSW_REG_PPTB_LEN 0x10 4497 4498 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 4499 4500 enum { 4501 MLXSW_REG_PPTB_MM_UM, 4502 MLXSW_REG_PPTB_MM_UNICAST, 4503 MLXSW_REG_PPTB_MM_MULTICAST, 4504 }; 4505 4506 /* reg_pptb_mm 4507 * Mapping mode. 4508 * 0 - Map both unicast and multicast packets to the same buffer. 4509 * 1 - Map only unicast packets. 4510 * 2 - Map only multicast packets. 4511 * Access: Index 4512 * 4513 * Note: SwitchX-2 only supports the first option. 4514 */ 4515 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4516 4517 /* reg_pptb_local_port 4518 * Local port number. 4519 * Access: Index 4520 */ 4521 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 4522 4523 /* reg_pptb_um 4524 * Enables the update of the untagged_buf field. 4525 * Access: RW 4526 */ 4527 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 4528 4529 /* reg_pptb_pm 4530 * Enables the update of the prio_to_buff field. 4531 * Bit <i> is a flag for updating the mapping for switch priority <i>. 4532 * Access: RW 4533 */ 4534 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 4535 4536 /* reg_pptb_prio_to_buff 4537 * Mapping of switch priority <i> to one of the allocated receive port 4538 * buffers. 4539 * Access: RW 4540 */ 4541 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 4542 4543 /* reg_pptb_pm_msb 4544 * Enables the update of the prio_to_buff field. 4545 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 4546 * Access: RW 4547 */ 4548 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 4549 4550 /* reg_pptb_untagged_buff 4551 * Mapping of untagged frames to one of the allocated receive port buffers. 4552 * Access: RW 4553 * 4554 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 4555 * Spectrum, as it maps untagged packets based on the default switch priority. 4556 */ 4557 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 4558 4559 /* reg_pptb_prio_to_buff_msb 4560 * Mapping of switch priority <i+8> to one of the allocated receive port 4561 * buffers. 4562 * Access: RW 4563 */ 4564 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 4565 4566 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 4567 4568 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 4569 { 4570 MLXSW_REG_ZERO(pptb, payload); 4571 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 4572 mlxsw_reg_pptb_local_port_set(payload, local_port); 4573 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4574 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4575 } 4576 4577 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 4578 u8 buff) 4579 { 4580 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 4581 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 4582 } 4583 4584 /* PBMC - Port Buffer Management Control Register 4585 * ---------------------------------------------- 4586 * The PBMC register configures and retrieves the port packet buffer 4587 * allocation for different Prios, and the Pause threshold management. 4588 */ 4589 #define MLXSW_REG_PBMC_ID 0x500C 4590 #define MLXSW_REG_PBMC_LEN 0x6C 4591 4592 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 4593 4594 /* reg_pbmc_local_port 4595 * Local port number. 4596 * Access: Index 4597 */ 4598 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 4599 4600 /* reg_pbmc_xoff_timer_value 4601 * When device generates a pause frame, it uses this value as the pause 4602 * timer (time for the peer port to pause in quota-512 bit time). 4603 * Access: RW 4604 */ 4605 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 4606 4607 /* reg_pbmc_xoff_refresh 4608 * The time before a new pause frame should be sent to refresh the pause RW 4609 * state. Using the same units as xoff_timer_value above (in quota-512 bit 4610 * time). 4611 * Access: RW 4612 */ 4613 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 4614 4615 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 4616 4617 /* reg_pbmc_buf_lossy 4618 * The field indicates if the buffer is lossy. 4619 * 0 - Lossless 4620 * 1 - Lossy 4621 * Access: RW 4622 */ 4623 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 4624 4625 /* reg_pbmc_buf_epsb 4626 * Eligible for Port Shared buffer. 4627 * If epsb is set, packets assigned to buffer are allowed to insert the port 4628 * shared buffer. 4629 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 4630 * Access: RW 4631 */ 4632 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 4633 4634 /* reg_pbmc_buf_size 4635 * The part of the packet buffer array is allocated for the specific buffer. 4636 * Units are represented in cells. 4637 * Access: RW 4638 */ 4639 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 4640 4641 /* reg_pbmc_buf_xoff_threshold 4642 * Once the amount of data in the buffer goes above this value, device 4643 * starts sending PFC frames for all priorities associated with the 4644 * buffer. Units are represented in cells. Reserved in case of lossy 4645 * buffer. 4646 * Access: RW 4647 * 4648 * Note: In Spectrum, reserved for buffer[9]. 4649 */ 4650 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 4651 0x08, 0x04, false); 4652 4653 /* reg_pbmc_buf_xon_threshold 4654 * When the amount of data in the buffer goes below this value, device 4655 * stops sending PFC frames for the priorities associated with the 4656 * buffer. Units are represented in cells. Reserved in case of lossy 4657 * buffer. 4658 * Access: RW 4659 * 4660 * Note: In Spectrum, reserved for buffer[9]. 4661 */ 4662 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 4663 0x08, 0x04, false); 4664 4665 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 4666 u16 xoff_timer_value, u16 xoff_refresh) 4667 { 4668 MLXSW_REG_ZERO(pbmc, payload); 4669 mlxsw_reg_pbmc_local_port_set(payload, local_port); 4670 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 4671 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 4672 } 4673 4674 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 4675 int buf_index, 4676 u16 size) 4677 { 4678 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 4679 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4680 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4681 } 4682 4683 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 4684 int buf_index, u16 size, 4685 u16 threshold) 4686 { 4687 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 4688 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4689 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4690 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 4691 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 4692 } 4693 4694 /* PSPA - Port Switch Partition Allocation 4695 * --------------------------------------- 4696 * Controls the association of a port with a switch partition and enables 4697 * configuring ports as stacking ports. 4698 */ 4699 #define MLXSW_REG_PSPA_ID 0x500D 4700 #define MLXSW_REG_PSPA_LEN 0x8 4701 4702 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 4703 4704 /* reg_pspa_swid 4705 * Switch partition ID. 4706 * Access: RW 4707 */ 4708 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 4709 4710 /* reg_pspa_local_port 4711 * Local port number. 4712 * Access: Index 4713 */ 4714 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 4715 4716 /* reg_pspa_sub_port 4717 * Virtual port within the local port. Set to 0 when virtual ports are 4718 * disabled on the local port. 4719 * Access: Index 4720 */ 4721 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 4722 4723 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 4724 { 4725 MLXSW_REG_ZERO(pspa, payload); 4726 mlxsw_reg_pspa_swid_set(payload, swid); 4727 mlxsw_reg_pspa_local_port_set(payload, local_port); 4728 mlxsw_reg_pspa_sub_port_set(payload, 0); 4729 } 4730 4731 /* HTGT - Host Trap Group Table 4732 * ---------------------------- 4733 * Configures the properties for forwarding to CPU. 4734 */ 4735 #define MLXSW_REG_HTGT_ID 0x7002 4736 #define MLXSW_REG_HTGT_LEN 0x20 4737 4738 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 4739 4740 /* reg_htgt_swid 4741 * Switch partition ID. 4742 * Access: Index 4743 */ 4744 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 4745 4746 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 4747 4748 /* reg_htgt_type 4749 * CPU path type. 4750 * Access: RW 4751 */ 4752 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 4753 4754 enum mlxsw_reg_htgt_trap_group { 4755 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 4756 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 4757 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 4758 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 4759 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 4760 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 4761 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 4762 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 4763 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 4764 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 4765 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 4766 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 4767 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 4768 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 4769 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 4770 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 4771 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 4772 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 4773 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 4774 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 4775 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 4776 }; 4777 4778 /* reg_htgt_trap_group 4779 * Trap group number. User defined number specifying which trap groups 4780 * should be forwarded to the CPU. The mapping between trap IDs and trap 4781 * groups is configured using HPKT register. 4782 * Access: Index 4783 */ 4784 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 4785 4786 enum { 4787 MLXSW_REG_HTGT_POLICER_DISABLE, 4788 MLXSW_REG_HTGT_POLICER_ENABLE, 4789 }; 4790 4791 /* reg_htgt_pide 4792 * Enable policer ID specified using 'pid' field. 4793 * Access: RW 4794 */ 4795 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 4796 4797 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 4798 4799 /* reg_htgt_pid 4800 * Policer ID for the trap group. 4801 * Access: RW 4802 */ 4803 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 4804 4805 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 4806 4807 /* reg_htgt_mirror_action 4808 * Mirror action to use. 4809 * 0 - Trap to CPU. 4810 * 1 - Trap to CPU and mirror to a mirroring agent. 4811 * 2 - Mirror to a mirroring agent and do not trap to CPU. 4812 * Access: RW 4813 * 4814 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 4815 */ 4816 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 4817 4818 /* reg_htgt_mirroring_agent 4819 * Mirroring agent. 4820 * Access: RW 4821 */ 4822 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 4823 4824 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 4825 4826 /* reg_htgt_priority 4827 * Trap group priority. 4828 * In case a packet matches multiple classification rules, the packet will 4829 * only be trapped once, based on the trap ID associated with the group (via 4830 * register HPKT) with the highest priority. 4831 * Supported values are 0-7, with 7 represnting the highest priority. 4832 * Access: RW 4833 * 4834 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 4835 * by the 'trap_group' field. 4836 */ 4837 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 4838 4839 #define MLXSW_REG_HTGT_DEFAULT_TC 7 4840 4841 /* reg_htgt_local_path_cpu_tclass 4842 * CPU ingress traffic class for the trap group. 4843 * Access: RW 4844 */ 4845 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 4846 4847 enum mlxsw_reg_htgt_local_path_rdq { 4848 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 4849 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 4850 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 4851 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 4852 }; 4853 /* reg_htgt_local_path_rdq 4854 * Receive descriptor queue (RDQ) to use for the trap group. 4855 * Access: RW 4856 */ 4857 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 4858 4859 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 4860 u8 priority, u8 tc) 4861 { 4862 MLXSW_REG_ZERO(htgt, payload); 4863 4864 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 4865 mlxsw_reg_htgt_pide_set(payload, 4866 MLXSW_REG_HTGT_POLICER_DISABLE); 4867 } else { 4868 mlxsw_reg_htgt_pide_set(payload, 4869 MLXSW_REG_HTGT_POLICER_ENABLE); 4870 mlxsw_reg_htgt_pid_set(payload, policer_id); 4871 } 4872 4873 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 4874 mlxsw_reg_htgt_trap_group_set(payload, group); 4875 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 4876 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 4877 mlxsw_reg_htgt_priority_set(payload, priority); 4878 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 4879 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 4880 } 4881 4882 /* HPKT - Host Packet Trap 4883 * ----------------------- 4884 * Configures trap IDs inside trap groups. 4885 */ 4886 #define MLXSW_REG_HPKT_ID 0x7003 4887 #define MLXSW_REG_HPKT_LEN 0x10 4888 4889 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 4890 4891 enum { 4892 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 4893 MLXSW_REG_HPKT_ACK_REQUIRED, 4894 }; 4895 4896 /* reg_hpkt_ack 4897 * Require acknowledgements from the host for events. 4898 * If set, then the device will wait for the event it sent to be acknowledged 4899 * by the host. This option is only relevant for event trap IDs. 4900 * Access: RW 4901 * 4902 * Note: Currently not supported by firmware. 4903 */ 4904 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 4905 4906 enum mlxsw_reg_hpkt_action { 4907 MLXSW_REG_HPKT_ACTION_FORWARD, 4908 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 4909 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 4910 MLXSW_REG_HPKT_ACTION_DISCARD, 4911 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 4912 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 4913 }; 4914 4915 /* reg_hpkt_action 4916 * Action to perform on packet when trapped. 4917 * 0 - No action. Forward to CPU based on switching rules. 4918 * 1 - Trap to CPU (CPU receives sole copy). 4919 * 2 - Mirror to CPU (CPU receives a replica of the packet). 4920 * 3 - Discard. 4921 * 4 - Soft discard (allow other traps to act on the packet). 4922 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 4923 * Access: RW 4924 * 4925 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 4926 * addressed to the CPU. 4927 */ 4928 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 4929 4930 /* reg_hpkt_trap_group 4931 * Trap group to associate the trap with. 4932 * Access: RW 4933 */ 4934 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 4935 4936 /* reg_hpkt_trap_id 4937 * Trap ID. 4938 * Access: Index 4939 * 4940 * Note: A trap ID can only be associated with a single trap group. The device 4941 * will associate the trap ID with the last trap group configured. 4942 */ 4943 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 4944 4945 enum { 4946 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 4947 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 4948 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 4949 }; 4950 4951 /* reg_hpkt_ctrl 4952 * Configure dedicated buffer resources for control packets. 4953 * Ignored by SwitchX-2. 4954 * 0 - Keep factory defaults. 4955 * 1 - Do not use control buffer for this trap ID. 4956 * 2 - Use control buffer for this trap ID. 4957 * Access: RW 4958 */ 4959 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 4960 4961 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 4962 enum mlxsw_reg_htgt_trap_group trap_group, 4963 bool is_ctrl) 4964 { 4965 MLXSW_REG_ZERO(hpkt, payload); 4966 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 4967 mlxsw_reg_hpkt_action_set(payload, action); 4968 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 4969 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 4970 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 4971 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 4972 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 4973 } 4974 4975 /* RGCR - Router General Configuration Register 4976 * -------------------------------------------- 4977 * The register is used for setting up the router configuration. 4978 */ 4979 #define MLXSW_REG_RGCR_ID 0x8001 4980 #define MLXSW_REG_RGCR_LEN 0x28 4981 4982 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 4983 4984 /* reg_rgcr_ipv4_en 4985 * IPv4 router enable. 4986 * Access: RW 4987 */ 4988 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 4989 4990 /* reg_rgcr_ipv6_en 4991 * IPv6 router enable. 4992 * Access: RW 4993 */ 4994 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 4995 4996 /* reg_rgcr_max_router_interfaces 4997 * Defines the maximum number of active router interfaces for all virtual 4998 * routers. 4999 * Access: RW 5000 */ 5001 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5002 5003 /* reg_rgcr_usp 5004 * Update switch priority and packet color. 5005 * 0 - Preserve the value of Switch Priority and packet color. 5006 * 1 - Recalculate the value of Switch Priority and packet color. 5007 * Access: RW 5008 * 5009 * Note: Not supported by SwitchX and SwitchX-2. 5010 */ 5011 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5012 5013 /* reg_rgcr_pcp_rw 5014 * Indicates how to handle the pcp_rewrite_en value: 5015 * 0 - Preserve the value of pcp_rewrite_en. 5016 * 2 - Disable PCP rewrite. 5017 * 3 - Enable PCP rewrite. 5018 * Access: RW 5019 * 5020 * Note: Not supported by SwitchX and SwitchX-2. 5021 */ 5022 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5023 5024 /* reg_rgcr_activity_dis 5025 * Activity disable: 5026 * 0 - Activity will be set when an entry is hit (default). 5027 * 1 - Activity will not be set when an entry is hit. 5028 * 5029 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5030 * (RALUE). 5031 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5032 * Entry (RAUHT). 5033 * Bits 2:7 are reserved. 5034 * Access: RW 5035 * 5036 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5037 */ 5038 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5039 5040 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5041 bool ipv6_en) 5042 { 5043 MLXSW_REG_ZERO(rgcr, payload); 5044 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5045 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5046 } 5047 5048 /* RITR - Router Interface Table Register 5049 * -------------------------------------- 5050 * The register is used to configure the router interface table. 5051 */ 5052 #define MLXSW_REG_RITR_ID 0x8002 5053 #define MLXSW_REG_RITR_LEN 0x40 5054 5055 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5056 5057 /* reg_ritr_enable 5058 * Enables routing on the router interface. 5059 * Access: RW 5060 */ 5061 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5062 5063 /* reg_ritr_ipv4 5064 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5065 * interface. 5066 * Access: RW 5067 */ 5068 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5069 5070 /* reg_ritr_ipv6 5071 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5072 * interface. 5073 * Access: RW 5074 */ 5075 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5076 5077 /* reg_ritr_ipv4_mc 5078 * IPv4 multicast routing enable. 5079 * Access: RW 5080 */ 5081 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5082 5083 /* reg_ritr_ipv6_mc 5084 * IPv6 multicast routing enable. 5085 * Access: RW 5086 */ 5087 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5088 5089 enum mlxsw_reg_ritr_if_type { 5090 /* VLAN interface. */ 5091 MLXSW_REG_RITR_VLAN_IF, 5092 /* FID interface. */ 5093 MLXSW_REG_RITR_FID_IF, 5094 /* Sub-port interface. */ 5095 MLXSW_REG_RITR_SP_IF, 5096 /* Loopback Interface. */ 5097 MLXSW_REG_RITR_LOOPBACK_IF, 5098 }; 5099 5100 /* reg_ritr_type 5101 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5102 * Access: RW 5103 */ 5104 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5105 5106 enum { 5107 MLXSW_REG_RITR_RIF_CREATE, 5108 MLXSW_REG_RITR_RIF_DEL, 5109 }; 5110 5111 /* reg_ritr_op 5112 * Opcode: 5113 * 0 - Create or edit RIF. 5114 * 1 - Delete RIF. 5115 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5116 * is not supported. An interface must be deleted and re-created in order 5117 * to update properties. 5118 * Access: WO 5119 */ 5120 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5121 5122 /* reg_ritr_rif 5123 * Router interface index. A pointer to the Router Interface Table. 5124 * Access: Index 5125 */ 5126 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5127 5128 /* reg_ritr_ipv4_fe 5129 * IPv4 Forwarding Enable. 5130 * Enables routing of IPv4 traffic on the router interface. When disabled, 5131 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5132 * Not supported in SwitchX-2. 5133 * Access: RW 5134 */ 5135 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5136 5137 /* reg_ritr_ipv6_fe 5138 * IPv6 Forwarding Enable. 5139 * Enables routing of IPv6 traffic on the router interface. When disabled, 5140 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5141 * Not supported in SwitchX-2. 5142 * Access: RW 5143 */ 5144 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5145 5146 /* reg_ritr_ipv4_mc_fe 5147 * IPv4 Multicast Forwarding Enable. 5148 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5149 * will be enabled. 5150 * Access: RW 5151 */ 5152 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5153 5154 /* reg_ritr_ipv6_mc_fe 5155 * IPv6 Multicast Forwarding Enable. 5156 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5157 * will be enabled. 5158 * Access: RW 5159 */ 5160 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5161 5162 /* reg_ritr_lb_en 5163 * Loop-back filter enable for unicast packets. 5164 * If the flag is set then loop-back filter for unicast packets is 5165 * implemented on the RIF. Multicast packets are always subject to 5166 * loop-back filtering. 5167 * Access: RW 5168 */ 5169 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5170 5171 /* reg_ritr_virtual_router 5172 * Virtual router ID associated with the router interface. 5173 * Access: RW 5174 */ 5175 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5176 5177 /* reg_ritr_mtu 5178 * Router interface MTU. 5179 * Access: RW 5180 */ 5181 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5182 5183 /* reg_ritr_if_swid 5184 * Switch partition ID. 5185 * Access: RW 5186 */ 5187 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5188 5189 /* reg_ritr_if_mac 5190 * Router interface MAC address. 5191 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5192 * Access: RW 5193 */ 5194 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5195 5196 /* reg_ritr_if_vrrp_id_ipv6 5197 * VRRP ID for IPv6 5198 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5199 * Access: RW 5200 */ 5201 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5202 5203 /* reg_ritr_if_vrrp_id_ipv4 5204 * VRRP ID for IPv4 5205 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5206 * Access: RW 5207 */ 5208 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5209 5210 /* VLAN Interface */ 5211 5212 /* reg_ritr_vlan_if_vid 5213 * VLAN ID. 5214 * Access: RW 5215 */ 5216 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5217 5218 /* FID Interface */ 5219 5220 /* reg_ritr_fid_if_fid 5221 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5222 * the vFID range are supported. 5223 * Access: RW 5224 */ 5225 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5226 5227 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5228 enum mlxsw_reg_ritr_if_type rif_type, 5229 u16 fid) 5230 { 5231 if (rif_type == MLXSW_REG_RITR_FID_IF) 5232 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5233 else 5234 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5235 } 5236 5237 /* Sub-port Interface */ 5238 5239 /* reg_ritr_sp_if_lag 5240 * LAG indication. When this bit is set the system_port field holds the 5241 * LAG identifier. 5242 * Access: RW 5243 */ 5244 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5245 5246 /* reg_ritr_sp_system_port 5247 * Port unique indentifier. When lag bit is set, this field holds the 5248 * lag_id in bits 0:9. 5249 * Access: RW 5250 */ 5251 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5252 5253 /* reg_ritr_sp_if_vid 5254 * VLAN ID. 5255 * Access: RW 5256 */ 5257 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5258 5259 /* Loopback Interface */ 5260 5261 enum mlxsw_reg_ritr_loopback_protocol { 5262 /* IPinIP IPv4 underlay Unicast */ 5263 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5264 /* IPinIP IPv6 underlay Unicast */ 5265 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5266 }; 5267 5268 /* reg_ritr_loopback_protocol 5269 * Access: RW 5270 */ 5271 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5272 5273 enum mlxsw_reg_ritr_loopback_ipip_type { 5274 /* Tunnel is IPinIP. */ 5275 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5276 /* Tunnel is GRE, no key. */ 5277 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5278 /* Tunnel is GRE, with a key. */ 5279 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5280 }; 5281 5282 /* reg_ritr_loopback_ipip_type 5283 * Encapsulation type. 5284 * Access: RW 5285 */ 5286 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 5287 5288 enum mlxsw_reg_ritr_loopback_ipip_options { 5289 /* The key is defined by gre_key. */ 5290 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 5291 }; 5292 5293 /* reg_ritr_loopback_ipip_options 5294 * Access: RW 5295 */ 5296 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 5297 5298 /* reg_ritr_loopback_ipip_uvr 5299 * Underlay Virtual Router ID. 5300 * Range is 0..cap_max_virtual_routers-1. 5301 * Reserved for Spectrum-2. 5302 * Access: RW 5303 */ 5304 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 5305 5306 /* reg_ritr_loopback_ipip_usip* 5307 * Encapsulation Underlay source IP. 5308 * Access: RW 5309 */ 5310 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 5311 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 5312 5313 /* reg_ritr_loopback_ipip_gre_key 5314 * GRE Key. 5315 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 5316 * Access: RW 5317 */ 5318 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 5319 5320 /* Shared between ingress/egress */ 5321 enum mlxsw_reg_ritr_counter_set_type { 5322 /* No Count. */ 5323 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 5324 /* Basic. Used for router interfaces, counting the following: 5325 * - Error and Discard counters. 5326 * - Unicast, Multicast and Broadcast counters. Sharing the 5327 * same set of counters for the different type of traffic 5328 * (IPv4, IPv6 and mpls). 5329 */ 5330 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 5331 }; 5332 5333 /* reg_ritr_ingress_counter_index 5334 * Counter Index for flow counter. 5335 * Access: RW 5336 */ 5337 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 5338 5339 /* reg_ritr_ingress_counter_set_type 5340 * Igress Counter Set Type for router interface counter. 5341 * Access: RW 5342 */ 5343 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 5344 5345 /* reg_ritr_egress_counter_index 5346 * Counter Index for flow counter. 5347 * Access: RW 5348 */ 5349 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 5350 5351 /* reg_ritr_egress_counter_set_type 5352 * Egress Counter Set Type for router interface counter. 5353 * Access: RW 5354 */ 5355 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 5356 5357 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 5358 bool enable, bool egress) 5359 { 5360 enum mlxsw_reg_ritr_counter_set_type set_type; 5361 5362 if (enable) 5363 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 5364 else 5365 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 5366 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 5367 5368 if (egress) 5369 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 5370 else 5371 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 5372 } 5373 5374 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 5375 { 5376 MLXSW_REG_ZERO(ritr, payload); 5377 mlxsw_reg_ritr_rif_set(payload, rif); 5378 } 5379 5380 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 5381 u16 system_port, u16 vid) 5382 { 5383 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 5384 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 5385 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 5386 } 5387 5388 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 5389 enum mlxsw_reg_ritr_if_type type, 5390 u16 rif, u16 vr_id, u16 mtu) 5391 { 5392 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 5393 5394 MLXSW_REG_ZERO(ritr, payload); 5395 mlxsw_reg_ritr_enable_set(payload, enable); 5396 mlxsw_reg_ritr_ipv4_set(payload, 1); 5397 mlxsw_reg_ritr_ipv6_set(payload, 1); 5398 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 5399 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 5400 mlxsw_reg_ritr_type_set(payload, type); 5401 mlxsw_reg_ritr_op_set(payload, op); 5402 mlxsw_reg_ritr_rif_set(payload, rif); 5403 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 5404 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 5405 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 5406 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 5407 mlxsw_reg_ritr_lb_en_set(payload, 1); 5408 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 5409 mlxsw_reg_ritr_mtu_set(payload, mtu); 5410 } 5411 5412 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 5413 { 5414 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 5415 } 5416 5417 static inline void 5418 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 5419 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5420 enum mlxsw_reg_ritr_loopback_ipip_options options, 5421 u16 uvr_id, u32 gre_key) 5422 { 5423 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 5424 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 5425 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 5426 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 5427 } 5428 5429 static inline void 5430 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 5431 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5432 enum mlxsw_reg_ritr_loopback_ipip_options options, 5433 u16 uvr_id, u32 usip, u32 gre_key) 5434 { 5435 mlxsw_reg_ritr_loopback_protocol_set(payload, 5436 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 5437 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 5438 uvr_id, gre_key); 5439 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 5440 } 5441 5442 /* RTAR - Router TCAM Allocation Register 5443 * -------------------------------------- 5444 * This register is used for allocation of regions in the TCAM table. 5445 */ 5446 #define MLXSW_REG_RTAR_ID 0x8004 5447 #define MLXSW_REG_RTAR_LEN 0x20 5448 5449 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 5450 5451 enum mlxsw_reg_rtar_op { 5452 MLXSW_REG_RTAR_OP_ALLOCATE, 5453 MLXSW_REG_RTAR_OP_RESIZE, 5454 MLXSW_REG_RTAR_OP_DEALLOCATE, 5455 }; 5456 5457 /* reg_rtar_op 5458 * Access: WO 5459 */ 5460 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 5461 5462 enum mlxsw_reg_rtar_key_type { 5463 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 5464 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 5465 }; 5466 5467 /* reg_rtar_key_type 5468 * TCAM key type for the region. 5469 * Access: WO 5470 */ 5471 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 5472 5473 /* reg_rtar_region_size 5474 * TCAM region size. When allocating/resizing this is the requested 5475 * size, the response is the actual size. 5476 * Note: Actual size may be larger than requested. 5477 * Reserved for op = Deallocate 5478 * Access: WO 5479 */ 5480 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 5481 5482 static inline void mlxsw_reg_rtar_pack(char *payload, 5483 enum mlxsw_reg_rtar_op op, 5484 enum mlxsw_reg_rtar_key_type key_type, 5485 u16 region_size) 5486 { 5487 MLXSW_REG_ZERO(rtar, payload); 5488 mlxsw_reg_rtar_op_set(payload, op); 5489 mlxsw_reg_rtar_key_type_set(payload, key_type); 5490 mlxsw_reg_rtar_region_size_set(payload, region_size); 5491 } 5492 5493 /* RATR - Router Adjacency Table Register 5494 * -------------------------------------- 5495 * The RATR register is used to configure the Router Adjacency (next-hop) 5496 * Table. 5497 */ 5498 #define MLXSW_REG_RATR_ID 0x8008 5499 #define MLXSW_REG_RATR_LEN 0x2C 5500 5501 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5502 5503 enum mlxsw_reg_ratr_op { 5504 /* Read */ 5505 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5506 /* Read and clear activity */ 5507 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 5508 /* Write Adjacency entry */ 5509 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 5510 /* Write Adjacency entry only if the activity is cleared. 5511 * The write may not succeed if the activity is set. There is not 5512 * direct feedback if the write has succeeded or not, however 5513 * the get will reveal the actual entry (SW can compare the get 5514 * response to the set command). 5515 */ 5516 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 5517 }; 5518 5519 /* reg_ratr_op 5520 * Note that Write operation may also be used for updating 5521 * counter_set_type and counter_index. In this case all other 5522 * fields must not be updated. 5523 * Access: OP 5524 */ 5525 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 5526 5527 /* reg_ratr_v 5528 * Valid bit. Indicates if the adjacency entry is valid. 5529 * Note: the device may need some time before reusing an invalidated 5530 * entry. During this time the entry can not be reused. It is 5531 * recommended to use another entry before reusing an invalidated 5532 * entry (e.g. software can put it at the end of the list for 5533 * reusing). Trying to access an invalidated entry not yet cleared 5534 * by the device results with failure indicating "Try Again" status. 5535 * When valid is '0' then egress_router_interface,trap_action, 5536 * adjacency_parameters and counters are reserved 5537 * Access: RW 5538 */ 5539 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 5540 5541 /* reg_ratr_a 5542 * Activity. Set for new entries. Set if a packet lookup has hit on 5543 * the specific entry. To clear the a bit, use "clear activity". 5544 * Access: RO 5545 */ 5546 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 5547 5548 enum mlxsw_reg_ratr_type { 5549 /* Ethernet */ 5550 MLXSW_REG_RATR_TYPE_ETHERNET, 5551 /* IPoIB Unicast without GRH. 5552 * Reserved for Spectrum. 5553 */ 5554 MLXSW_REG_RATR_TYPE_IPOIB_UC, 5555 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 5556 * adjacency). 5557 * Reserved for Spectrum. 5558 */ 5559 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 5560 /* IPoIB Multicast. 5561 * Reserved for Spectrum. 5562 */ 5563 MLXSW_REG_RATR_TYPE_IPOIB_MC, 5564 /* MPLS. 5565 * Reserved for SwitchX/-2. 5566 */ 5567 MLXSW_REG_RATR_TYPE_MPLS, 5568 /* IPinIP Encap. 5569 * Reserved for SwitchX/-2. 5570 */ 5571 MLXSW_REG_RATR_TYPE_IPIP, 5572 }; 5573 5574 /* reg_ratr_type 5575 * Adjacency entry type. 5576 * Access: RW 5577 */ 5578 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 5579 5580 /* reg_ratr_adjacency_index_low 5581 * Bits 15:0 of index into the adjacency table. 5582 * For SwitchX and SwitchX-2, the adjacency table is linear and 5583 * used for adjacency entries only. 5584 * For Spectrum, the index is to the KVD linear. 5585 * Access: Index 5586 */ 5587 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 5588 5589 /* reg_ratr_egress_router_interface 5590 * Range is 0 .. cap_max_router_interfaces - 1 5591 * Access: RW 5592 */ 5593 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 5594 5595 enum mlxsw_reg_ratr_trap_action { 5596 MLXSW_REG_RATR_TRAP_ACTION_NOP, 5597 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 5598 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 5599 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 5600 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 5601 }; 5602 5603 /* reg_ratr_trap_action 5604 * see mlxsw_reg_ratr_trap_action 5605 * Access: RW 5606 */ 5607 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 5608 5609 /* reg_ratr_adjacency_index_high 5610 * Bits 23:16 of the adjacency_index. 5611 * Access: Index 5612 */ 5613 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 5614 5615 enum mlxsw_reg_ratr_trap_id { 5616 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 5617 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 5618 }; 5619 5620 /* reg_ratr_trap_id 5621 * Trap ID to be reported to CPU. 5622 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5623 * For trap_action of NOP, MIRROR and DISCARD_ERROR 5624 * Access: RW 5625 */ 5626 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 5627 5628 /* reg_ratr_eth_destination_mac 5629 * MAC address of the destination next-hop. 5630 * Access: RW 5631 */ 5632 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 5633 5634 enum mlxsw_reg_ratr_ipip_type { 5635 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 5636 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 5637 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 5638 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 5639 }; 5640 5641 /* reg_ratr_ipip_type 5642 * Underlay destination ip type. 5643 * Note: the type field must match the protocol of the router interface. 5644 * Access: RW 5645 */ 5646 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 5647 5648 /* reg_ratr_ipip_ipv4_udip 5649 * Underlay ipv4 dip. 5650 * Reserved when ipip_type is IPv6. 5651 * Access: RW 5652 */ 5653 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 5654 5655 /* reg_ratr_ipip_ipv6_ptr 5656 * Pointer to IPv6 underlay destination ip address. 5657 * For Spectrum: Pointer to KVD linear space. 5658 * Access: RW 5659 */ 5660 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 5661 5662 enum mlxsw_reg_flow_counter_set_type { 5663 /* No count */ 5664 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 5665 /* Count packets and bytes */ 5666 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 5667 /* Count only packets */ 5668 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 5669 }; 5670 5671 /* reg_ratr_counter_set_type 5672 * Counter set type for flow counters 5673 * Access: RW 5674 */ 5675 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 5676 5677 /* reg_ratr_counter_index 5678 * Counter index for flow counters 5679 * Access: RW 5680 */ 5681 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 5682 5683 static inline void 5684 mlxsw_reg_ratr_pack(char *payload, 5685 enum mlxsw_reg_ratr_op op, bool valid, 5686 enum mlxsw_reg_ratr_type type, 5687 u32 adjacency_index, u16 egress_rif) 5688 { 5689 MLXSW_REG_ZERO(ratr, payload); 5690 mlxsw_reg_ratr_op_set(payload, op); 5691 mlxsw_reg_ratr_v_set(payload, valid); 5692 mlxsw_reg_ratr_type_set(payload, type); 5693 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 5694 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 5695 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 5696 } 5697 5698 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 5699 const char *dest_mac) 5700 { 5701 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 5702 } 5703 5704 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 5705 { 5706 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 5707 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 5708 } 5709 5710 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 5711 bool counter_enable) 5712 { 5713 enum mlxsw_reg_flow_counter_set_type set_type; 5714 5715 if (counter_enable) 5716 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 5717 else 5718 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 5719 5720 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 5721 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 5722 } 5723 5724 /* RDPM - Router DSCP to Priority Mapping 5725 * -------------------------------------- 5726 * Controls the mapping from DSCP field to switch priority on routed packets 5727 */ 5728 #define MLXSW_REG_RDPM_ID 0x8009 5729 #define MLXSW_REG_RDPM_BASE_LEN 0x00 5730 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 5731 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 5732 #define MLXSW_REG_RDPM_LEN 0x40 5733 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 5734 MLXSW_REG_RDPM_LEN - \ 5735 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 5736 5737 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 5738 5739 /* reg_dscp_entry_e 5740 * Enable update of the specific entry 5741 * Access: Index 5742 */ 5743 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 5744 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 5745 5746 /* reg_dscp_entry_prio 5747 * Switch Priority 5748 * Access: RW 5749 */ 5750 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 5751 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 5752 5753 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 5754 u8 prio) 5755 { 5756 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 5757 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 5758 } 5759 5760 /* RICNT - Router Interface Counter Register 5761 * ----------------------------------------- 5762 * The RICNT register retrieves per port performance counters 5763 */ 5764 #define MLXSW_REG_RICNT_ID 0x800B 5765 #define MLXSW_REG_RICNT_LEN 0x100 5766 5767 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 5768 5769 /* reg_ricnt_counter_index 5770 * Counter index 5771 * Access: RW 5772 */ 5773 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 5774 5775 enum mlxsw_reg_ricnt_counter_set_type { 5776 /* No Count. */ 5777 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 5778 /* Basic. Used for router interfaces, counting the following: 5779 * - Error and Discard counters. 5780 * - Unicast, Multicast and Broadcast counters. Sharing the 5781 * same set of counters for the different type of traffic 5782 * (IPv4, IPv6 and mpls). 5783 */ 5784 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 5785 }; 5786 5787 /* reg_ricnt_counter_set_type 5788 * Counter Set Type for router interface counter 5789 * Access: RW 5790 */ 5791 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 5792 5793 enum mlxsw_reg_ricnt_opcode { 5794 /* Nop. Supported only for read access*/ 5795 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 5796 /* Clear. Setting the clr bit will reset the counter value for 5797 * all counters of the specified Router Interface. 5798 */ 5799 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 5800 }; 5801 5802 /* reg_ricnt_opcode 5803 * Opcode 5804 * Access: RW 5805 */ 5806 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 5807 5808 /* reg_ricnt_good_unicast_packets 5809 * good unicast packets. 5810 * Access: RW 5811 */ 5812 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 5813 5814 /* reg_ricnt_good_multicast_packets 5815 * good multicast packets. 5816 * Access: RW 5817 */ 5818 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 5819 5820 /* reg_ricnt_good_broadcast_packets 5821 * good broadcast packets 5822 * Access: RW 5823 */ 5824 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 5825 5826 /* reg_ricnt_good_unicast_bytes 5827 * A count of L3 data and padding octets not including L2 headers 5828 * for good unicast frames. 5829 * Access: RW 5830 */ 5831 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 5832 5833 /* reg_ricnt_good_multicast_bytes 5834 * A count of L3 data and padding octets not including L2 headers 5835 * for good multicast frames. 5836 * Access: RW 5837 */ 5838 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 5839 5840 /* reg_ritr_good_broadcast_bytes 5841 * A count of L3 data and padding octets not including L2 headers 5842 * for good broadcast frames. 5843 * Access: RW 5844 */ 5845 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 5846 5847 /* reg_ricnt_error_packets 5848 * A count of errored frames that do not pass the router checks. 5849 * Access: RW 5850 */ 5851 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 5852 5853 /* reg_ricnt_discrad_packets 5854 * A count of non-errored frames that do not pass the router checks. 5855 * Access: RW 5856 */ 5857 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 5858 5859 /* reg_ricnt_error_bytes 5860 * A count of L3 data and padding octets not including L2 headers 5861 * for errored frames. 5862 * Access: RW 5863 */ 5864 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 5865 5866 /* reg_ricnt_discard_bytes 5867 * A count of L3 data and padding octets not including L2 headers 5868 * for non-errored frames that do not pass the router checks. 5869 * Access: RW 5870 */ 5871 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 5872 5873 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 5874 enum mlxsw_reg_ricnt_opcode op) 5875 { 5876 MLXSW_REG_ZERO(ricnt, payload); 5877 mlxsw_reg_ricnt_op_set(payload, op); 5878 mlxsw_reg_ricnt_counter_index_set(payload, index); 5879 mlxsw_reg_ricnt_counter_set_type_set(payload, 5880 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 5881 } 5882 5883 /* RRCR - Router Rules Copy Register Layout 5884 * ---------------------------------------- 5885 * This register is used for moving and copying route entry rules. 5886 */ 5887 #define MLXSW_REG_RRCR_ID 0x800F 5888 #define MLXSW_REG_RRCR_LEN 0x24 5889 5890 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 5891 5892 enum mlxsw_reg_rrcr_op { 5893 /* Move rules */ 5894 MLXSW_REG_RRCR_OP_MOVE, 5895 /* Copy rules */ 5896 MLXSW_REG_RRCR_OP_COPY, 5897 }; 5898 5899 /* reg_rrcr_op 5900 * Access: WO 5901 */ 5902 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 5903 5904 /* reg_rrcr_offset 5905 * Offset within the region from which to copy/move. 5906 * Access: Index 5907 */ 5908 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 5909 5910 /* reg_rrcr_size 5911 * The number of rules to copy/move. 5912 * Access: WO 5913 */ 5914 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 5915 5916 /* reg_rrcr_table_id 5917 * Identifier of the table on which to perform the operation. Encoding is the 5918 * same as in RTAR.key_type 5919 * Access: Index 5920 */ 5921 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 5922 5923 /* reg_rrcr_dest_offset 5924 * Offset within the region to which to copy/move 5925 * Access: Index 5926 */ 5927 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 5928 5929 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 5930 u16 offset, u16 size, 5931 enum mlxsw_reg_rtar_key_type table_id, 5932 u16 dest_offset) 5933 { 5934 MLXSW_REG_ZERO(rrcr, payload); 5935 mlxsw_reg_rrcr_op_set(payload, op); 5936 mlxsw_reg_rrcr_offset_set(payload, offset); 5937 mlxsw_reg_rrcr_size_set(payload, size); 5938 mlxsw_reg_rrcr_table_id_set(payload, table_id); 5939 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 5940 } 5941 5942 /* RALTA - Router Algorithmic LPM Tree Allocation Register 5943 * ------------------------------------------------------- 5944 * RALTA is used to allocate the LPM trees of the SHSPM method. 5945 */ 5946 #define MLXSW_REG_RALTA_ID 0x8010 5947 #define MLXSW_REG_RALTA_LEN 0x04 5948 5949 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 5950 5951 /* reg_ralta_op 5952 * opcode (valid for Write, must be 0 on Read) 5953 * 0 - allocate a tree 5954 * 1 - deallocate a tree 5955 * Access: OP 5956 */ 5957 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 5958 5959 enum mlxsw_reg_ralxx_protocol { 5960 MLXSW_REG_RALXX_PROTOCOL_IPV4, 5961 MLXSW_REG_RALXX_PROTOCOL_IPV6, 5962 }; 5963 5964 /* reg_ralta_protocol 5965 * Protocol. 5966 * Deallocation opcode: Reserved. 5967 * Access: RW 5968 */ 5969 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 5970 5971 /* reg_ralta_tree_id 5972 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 5973 * the tree identifier (managed by software). 5974 * Note that tree_id 0 is allocated for a default-route tree. 5975 * Access: Index 5976 */ 5977 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 5978 5979 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 5980 enum mlxsw_reg_ralxx_protocol protocol, 5981 u8 tree_id) 5982 { 5983 MLXSW_REG_ZERO(ralta, payload); 5984 mlxsw_reg_ralta_op_set(payload, !alloc); 5985 mlxsw_reg_ralta_protocol_set(payload, protocol); 5986 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 5987 } 5988 5989 /* RALST - Router Algorithmic LPM Structure Tree Register 5990 * ------------------------------------------------------ 5991 * RALST is used to set and query the structure of an LPM tree. 5992 * The structure of the tree must be sorted as a sorted binary tree, while 5993 * each node is a bin that is tagged as the length of the prefixes the lookup 5994 * will refer to. Therefore, bin X refers to a set of entries with prefixes 5995 * of X bits to match with the destination address. The bin 0 indicates 5996 * the default action, when there is no match of any prefix. 5997 */ 5998 #define MLXSW_REG_RALST_ID 0x8011 5999 #define MLXSW_REG_RALST_LEN 0x104 6000 6001 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6002 6003 /* reg_ralst_root_bin 6004 * The bin number of the root bin. 6005 * 0<root_bin=<(length of IP address) 6006 * For a default-route tree configure 0xff 6007 * Access: RW 6008 */ 6009 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6010 6011 /* reg_ralst_tree_id 6012 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6013 * Access: Index 6014 */ 6015 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6016 6017 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6018 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6019 #define MLXSW_REG_RALST_BIN_COUNT 128 6020 6021 /* reg_ralst_left_child_bin 6022 * Holding the children of the bin according to the stored tree's structure. 6023 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6024 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6025 * Access: RW 6026 */ 6027 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6028 6029 /* reg_ralst_right_child_bin 6030 * Holding the children of the bin according to the stored tree's structure. 6031 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6032 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6033 * Access: RW 6034 */ 6035 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6036 false); 6037 6038 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6039 { 6040 MLXSW_REG_ZERO(ralst, payload); 6041 6042 /* Initialize all bins to have no left or right child */ 6043 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6044 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6045 6046 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6047 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6048 } 6049 6050 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6051 u8 left_child_bin, 6052 u8 right_child_bin) 6053 { 6054 int bin_index = bin_number - 1; 6055 6056 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6057 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6058 right_child_bin); 6059 } 6060 6061 /* RALTB - Router Algorithmic LPM Tree Binding Register 6062 * ---------------------------------------------------- 6063 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6064 */ 6065 #define MLXSW_REG_RALTB_ID 0x8012 6066 #define MLXSW_REG_RALTB_LEN 0x04 6067 6068 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6069 6070 /* reg_raltb_virtual_router 6071 * Virtual Router ID 6072 * Range is 0..cap_max_virtual_routers-1 6073 * Access: Index 6074 */ 6075 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6076 6077 /* reg_raltb_protocol 6078 * Protocol. 6079 * Access: Index 6080 */ 6081 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6082 6083 /* reg_raltb_tree_id 6084 * Tree to be used for the {virtual_router, protocol} 6085 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6086 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6087 * Access: RW 6088 */ 6089 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6090 6091 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6092 enum mlxsw_reg_ralxx_protocol protocol, 6093 u8 tree_id) 6094 { 6095 MLXSW_REG_ZERO(raltb, payload); 6096 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6097 mlxsw_reg_raltb_protocol_set(payload, protocol); 6098 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6099 } 6100 6101 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6102 * ----------------------------------------------------- 6103 * RALUE is used to configure and query LPM entries that serve 6104 * the Unicast protocols. 6105 */ 6106 #define MLXSW_REG_RALUE_ID 0x8013 6107 #define MLXSW_REG_RALUE_LEN 0x38 6108 6109 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6110 6111 /* reg_ralue_protocol 6112 * Protocol. 6113 * Access: Index 6114 */ 6115 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6116 6117 enum mlxsw_reg_ralue_op { 6118 /* Read operation. If entry doesn't exist, the operation fails. */ 6119 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6120 /* Clear on read operation. Used to read entry and 6121 * clear Activity bit. 6122 */ 6123 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6124 /* Write operation. Used to write a new entry to the table. All RW 6125 * fields are written for new entry. Activity bit is set 6126 * for new entries. 6127 */ 6128 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6129 /* Update operation. Used to update an existing route entry and 6130 * only update the RW fields that are detailed in the field 6131 * op_u_mask. If entry doesn't exist, the operation fails. 6132 */ 6133 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6134 /* Clear activity. The Activity bit (the field a) is cleared 6135 * for the entry. 6136 */ 6137 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6138 /* Delete operation. Used to delete an existing entry. If entry 6139 * doesn't exist, the operation fails. 6140 */ 6141 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6142 }; 6143 6144 /* reg_ralue_op 6145 * Operation. 6146 * Access: OP 6147 */ 6148 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6149 6150 /* reg_ralue_a 6151 * Activity. Set for new entries. Set if a packet lookup has hit on the 6152 * specific entry, only if the entry is a route. To clear the a bit, use 6153 * "clear activity" op. 6154 * Enabled by activity_dis in RGCR 6155 * Access: RO 6156 */ 6157 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6158 6159 /* reg_ralue_virtual_router 6160 * Virtual Router ID 6161 * Range is 0..cap_max_virtual_routers-1 6162 * Access: Index 6163 */ 6164 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6165 6166 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6167 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6168 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6169 6170 /* reg_ralue_op_u_mask 6171 * opcode update mask. 6172 * On read operation, this field is reserved. 6173 * This field is valid for update opcode, otherwise - reserved. 6174 * This field is a bitmask of the fields that should be updated. 6175 * Access: WO 6176 */ 6177 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6178 6179 /* reg_ralue_prefix_len 6180 * Number of bits in the prefix of the LPM route. 6181 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6182 * two entries in the physical HW table. 6183 * Access: Index 6184 */ 6185 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6186 6187 /* reg_ralue_dip* 6188 * The prefix of the route or of the marker that the object of the LPM 6189 * is compared with. The most significant bits of the dip are the prefix. 6190 * The least significant bits must be '0' if the prefix_len is smaller 6191 * than 128 for IPv6 or smaller than 32 for IPv4. 6192 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6193 * Access: Index 6194 */ 6195 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6196 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6197 6198 enum mlxsw_reg_ralue_entry_type { 6199 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6200 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6201 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6202 }; 6203 6204 /* reg_ralue_entry_type 6205 * Entry type. 6206 * Note - for Marker entries, the action_type and action fields are reserved. 6207 * Access: RW 6208 */ 6209 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6210 6211 /* reg_ralue_bmp_len 6212 * The best match prefix length in the case that there is no match for 6213 * longer prefixes. 6214 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6215 * Note for any update operation with entry_type modification this 6216 * field must be set. 6217 * Access: RW 6218 */ 6219 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6220 6221 enum mlxsw_reg_ralue_action_type { 6222 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6223 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6224 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6225 }; 6226 6227 /* reg_ralue_action_type 6228 * Action Type 6229 * Indicates how the IP address is connected. 6230 * It can be connected to a local subnet through local_erif or can be 6231 * on a remote subnet connected through a next-hop router, 6232 * or transmitted to the CPU. 6233 * Reserved when entry_type = MARKER_ENTRY 6234 * Access: RW 6235 */ 6236 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6237 6238 enum mlxsw_reg_ralue_trap_action { 6239 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6240 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6241 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6242 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6243 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6244 }; 6245 6246 /* reg_ralue_trap_action 6247 * Trap action. 6248 * For IP2ME action, only NOP and MIRROR are possible. 6249 * Access: RW 6250 */ 6251 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6252 6253 /* reg_ralue_trap_id 6254 * Trap ID to be reported to CPU. 6255 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6256 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6257 * Access: RW 6258 */ 6259 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6260 6261 /* reg_ralue_adjacency_index 6262 * Points to the first entry of the group-based ECMP. 6263 * Only relevant in case of REMOTE action. 6264 * Access: RW 6265 */ 6266 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6267 6268 /* reg_ralue_ecmp_size 6269 * Amount of sequential entries starting 6270 * from the adjacency_index (the number of ECMPs). 6271 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6272 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6273 * Only relevant in case of REMOTE action. 6274 * Access: RW 6275 */ 6276 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6277 6278 /* reg_ralue_local_erif 6279 * Egress Router Interface. 6280 * Only relevant in case of LOCAL action. 6281 * Access: RW 6282 */ 6283 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 6284 6285 /* reg_ralue_ip2me_v 6286 * Valid bit for the tunnel_ptr field. 6287 * If valid = 0 then trap to CPU as IP2ME trap ID. 6288 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 6289 * decapsulation then tunnel decapsulation is done. 6290 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 6291 * decapsulation then trap as IP2ME trap ID. 6292 * Only relevant in case of IP2ME action. 6293 * Access: RW 6294 */ 6295 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 6296 6297 /* reg_ralue_ip2me_tunnel_ptr 6298 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 6299 * For Spectrum, pointer to KVD Linear. 6300 * Only relevant in case of IP2ME action. 6301 * Access: RW 6302 */ 6303 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 6304 6305 static inline void mlxsw_reg_ralue_pack(char *payload, 6306 enum mlxsw_reg_ralxx_protocol protocol, 6307 enum mlxsw_reg_ralue_op op, 6308 u16 virtual_router, u8 prefix_len) 6309 { 6310 MLXSW_REG_ZERO(ralue, payload); 6311 mlxsw_reg_ralue_protocol_set(payload, protocol); 6312 mlxsw_reg_ralue_op_set(payload, op); 6313 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 6314 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 6315 mlxsw_reg_ralue_entry_type_set(payload, 6316 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 6317 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 6318 } 6319 6320 static inline void mlxsw_reg_ralue_pack4(char *payload, 6321 enum mlxsw_reg_ralxx_protocol protocol, 6322 enum mlxsw_reg_ralue_op op, 6323 u16 virtual_router, u8 prefix_len, 6324 u32 dip) 6325 { 6326 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6327 mlxsw_reg_ralue_dip4_set(payload, dip); 6328 } 6329 6330 static inline void mlxsw_reg_ralue_pack6(char *payload, 6331 enum mlxsw_reg_ralxx_protocol protocol, 6332 enum mlxsw_reg_ralue_op op, 6333 u16 virtual_router, u8 prefix_len, 6334 const void *dip) 6335 { 6336 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6337 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 6338 } 6339 6340 static inline void 6341 mlxsw_reg_ralue_act_remote_pack(char *payload, 6342 enum mlxsw_reg_ralue_trap_action trap_action, 6343 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 6344 { 6345 mlxsw_reg_ralue_action_type_set(payload, 6346 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 6347 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6348 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6349 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 6350 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 6351 } 6352 6353 static inline void 6354 mlxsw_reg_ralue_act_local_pack(char *payload, 6355 enum mlxsw_reg_ralue_trap_action trap_action, 6356 u16 trap_id, u16 local_erif) 6357 { 6358 mlxsw_reg_ralue_action_type_set(payload, 6359 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 6360 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6361 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6362 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 6363 } 6364 6365 static inline void 6366 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 6367 { 6368 mlxsw_reg_ralue_action_type_set(payload, 6369 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6370 } 6371 6372 static inline void 6373 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 6374 { 6375 mlxsw_reg_ralue_action_type_set(payload, 6376 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6377 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 6378 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 6379 } 6380 6381 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 6382 * ---------------------------------------------------------- 6383 * The RAUHT register is used to configure and query the Unicast Host table in 6384 * devices that implement the Algorithmic LPM. 6385 */ 6386 #define MLXSW_REG_RAUHT_ID 0x8014 6387 #define MLXSW_REG_RAUHT_LEN 0x74 6388 6389 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 6390 6391 enum mlxsw_reg_rauht_type { 6392 MLXSW_REG_RAUHT_TYPE_IPV4, 6393 MLXSW_REG_RAUHT_TYPE_IPV6, 6394 }; 6395 6396 /* reg_rauht_type 6397 * Access: Index 6398 */ 6399 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 6400 6401 enum mlxsw_reg_rauht_op { 6402 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 6403 /* Read operation */ 6404 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 6405 /* Clear on read operation. Used to read entry and clear 6406 * activity bit. 6407 */ 6408 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 6409 /* Add. Used to write a new entry to the table. All R/W fields are 6410 * relevant for new entry. Activity bit is set for new entries. 6411 */ 6412 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 6413 /* Update action. Used to update an existing route entry and 6414 * only update the following fields: 6415 * trap_action, trap_id, mac, counter_set_type, counter_index 6416 */ 6417 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 6418 /* Clear activity. A bit is cleared for the entry. */ 6419 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 6420 /* Delete entry */ 6421 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 6422 /* Delete all host entries on a RIF. In this command, dip 6423 * field is reserved. 6424 */ 6425 }; 6426 6427 /* reg_rauht_op 6428 * Access: OP 6429 */ 6430 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 6431 6432 /* reg_rauht_a 6433 * Activity. Set for new entries. Set if a packet lookup has hit on 6434 * the specific entry. 6435 * To clear the a bit, use "clear activity" op. 6436 * Enabled by activity_dis in RGCR 6437 * Access: RO 6438 */ 6439 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 6440 6441 /* reg_rauht_rif 6442 * Router Interface 6443 * Access: Index 6444 */ 6445 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 6446 6447 /* reg_rauht_dip* 6448 * Destination address. 6449 * Access: Index 6450 */ 6451 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 6452 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 6453 6454 enum mlxsw_reg_rauht_trap_action { 6455 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 6456 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 6457 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 6458 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 6459 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 6460 }; 6461 6462 /* reg_rauht_trap_action 6463 * Access: RW 6464 */ 6465 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 6466 6467 enum mlxsw_reg_rauht_trap_id { 6468 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 6469 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 6470 }; 6471 6472 /* reg_rauht_trap_id 6473 * Trap ID to be reported to CPU. 6474 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6475 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 6476 * trap_id is reserved. 6477 * Access: RW 6478 */ 6479 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 6480 6481 /* reg_rauht_counter_set_type 6482 * Counter set type for flow counters 6483 * Access: RW 6484 */ 6485 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 6486 6487 /* reg_rauht_counter_index 6488 * Counter index for flow counters 6489 * Access: RW 6490 */ 6491 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 6492 6493 /* reg_rauht_mac 6494 * MAC address. 6495 * Access: RW 6496 */ 6497 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 6498 6499 static inline void mlxsw_reg_rauht_pack(char *payload, 6500 enum mlxsw_reg_rauht_op op, u16 rif, 6501 const char *mac) 6502 { 6503 MLXSW_REG_ZERO(rauht, payload); 6504 mlxsw_reg_rauht_op_set(payload, op); 6505 mlxsw_reg_rauht_rif_set(payload, rif); 6506 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 6507 } 6508 6509 static inline void mlxsw_reg_rauht_pack4(char *payload, 6510 enum mlxsw_reg_rauht_op op, u16 rif, 6511 const char *mac, u32 dip) 6512 { 6513 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6514 mlxsw_reg_rauht_dip4_set(payload, dip); 6515 } 6516 6517 static inline void mlxsw_reg_rauht_pack6(char *payload, 6518 enum mlxsw_reg_rauht_op op, u16 rif, 6519 const char *mac, const char *dip) 6520 { 6521 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6522 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 6523 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 6524 } 6525 6526 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 6527 u64 counter_index) 6528 { 6529 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 6530 mlxsw_reg_rauht_counter_set_type_set(payload, 6531 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 6532 } 6533 6534 /* RALEU - Router Algorithmic LPM ECMP Update Register 6535 * --------------------------------------------------- 6536 * The register enables updating the ECMP section in the action for multiple 6537 * LPM Unicast entries in a single operation. The update is executed to 6538 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 6539 */ 6540 #define MLXSW_REG_RALEU_ID 0x8015 6541 #define MLXSW_REG_RALEU_LEN 0x28 6542 6543 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 6544 6545 /* reg_raleu_protocol 6546 * Protocol. 6547 * Access: Index 6548 */ 6549 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 6550 6551 /* reg_raleu_virtual_router 6552 * Virtual Router ID 6553 * Range is 0..cap_max_virtual_routers-1 6554 * Access: Index 6555 */ 6556 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 6557 6558 /* reg_raleu_adjacency_index 6559 * Adjacency Index used for matching on the existing entries. 6560 * Access: Index 6561 */ 6562 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 6563 6564 /* reg_raleu_ecmp_size 6565 * ECMP Size used for matching on the existing entries. 6566 * Access: Index 6567 */ 6568 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 6569 6570 /* reg_raleu_new_adjacency_index 6571 * New Adjacency Index. 6572 * Access: WO 6573 */ 6574 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 6575 6576 /* reg_raleu_new_ecmp_size 6577 * New ECMP Size. 6578 * Access: WO 6579 */ 6580 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 6581 6582 static inline void mlxsw_reg_raleu_pack(char *payload, 6583 enum mlxsw_reg_ralxx_protocol protocol, 6584 u16 virtual_router, 6585 u32 adjacency_index, u16 ecmp_size, 6586 u32 new_adjacency_index, 6587 u16 new_ecmp_size) 6588 { 6589 MLXSW_REG_ZERO(raleu, payload); 6590 mlxsw_reg_raleu_protocol_set(payload, protocol); 6591 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 6592 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 6593 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 6594 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 6595 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 6596 } 6597 6598 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 6599 * ---------------------------------------------------------------- 6600 * The RAUHTD register allows dumping entries from the Router Unicast Host 6601 * Table. For a given session an entry is dumped no more than one time. The 6602 * first RAUHTD access after reset is a new session. A session ends when the 6603 * num_rec response is smaller than num_rec request or for IPv4 when the 6604 * num_entries is smaller than 4. The clear activity affect the current session 6605 * or the last session if a new session has not started. 6606 */ 6607 #define MLXSW_REG_RAUHTD_ID 0x8018 6608 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 6609 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 6610 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 6611 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 6612 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 6613 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 6614 6615 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 6616 6617 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 6618 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 6619 6620 /* reg_rauhtd_filter_fields 6621 * if a bit is '0' then the relevant field is ignored and dump is done 6622 * regardless of the field value 6623 * Bit0 - filter by activity: entry_a 6624 * Bit3 - filter by entry rip: entry_rif 6625 * Access: Index 6626 */ 6627 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 6628 6629 enum mlxsw_reg_rauhtd_op { 6630 MLXSW_REG_RAUHTD_OP_DUMP, 6631 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 6632 }; 6633 6634 /* reg_rauhtd_op 6635 * Access: OP 6636 */ 6637 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 6638 6639 /* reg_rauhtd_num_rec 6640 * At request: number of records requested 6641 * At response: number of records dumped 6642 * For IPv4, each record has 4 entries at request and up to 4 entries 6643 * at response 6644 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 6645 * Access: Index 6646 */ 6647 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 6648 6649 /* reg_rauhtd_entry_a 6650 * Dump only if activity has value of entry_a 6651 * Reserved if filter_fields bit0 is '0' 6652 * Access: Index 6653 */ 6654 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 6655 6656 enum mlxsw_reg_rauhtd_type { 6657 MLXSW_REG_RAUHTD_TYPE_IPV4, 6658 MLXSW_REG_RAUHTD_TYPE_IPV6, 6659 }; 6660 6661 /* reg_rauhtd_type 6662 * Dump only if record type is: 6663 * 0 - IPv4 6664 * 1 - IPv6 6665 * Access: Index 6666 */ 6667 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 6668 6669 /* reg_rauhtd_entry_rif 6670 * Dump only if RIF has value of entry_rif 6671 * Reserved if filter_fields bit3 is '0' 6672 * Access: Index 6673 */ 6674 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 6675 6676 static inline void mlxsw_reg_rauhtd_pack(char *payload, 6677 enum mlxsw_reg_rauhtd_type type) 6678 { 6679 MLXSW_REG_ZERO(rauhtd, payload); 6680 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 6681 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 6682 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 6683 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 6684 mlxsw_reg_rauhtd_type_set(payload, type); 6685 } 6686 6687 /* reg_rauhtd_ipv4_rec_num_entries 6688 * Number of valid entries in this record: 6689 * 0 - 1 valid entry 6690 * 1 - 2 valid entries 6691 * 2 - 3 valid entries 6692 * 3 - 4 valid entries 6693 * Access: RO 6694 */ 6695 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 6696 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 6697 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 6698 6699 /* reg_rauhtd_rec_type 6700 * Record type. 6701 * 0 - IPv4 6702 * 1 - IPv6 6703 * Access: RO 6704 */ 6705 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 6706 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 6707 6708 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 6709 6710 /* reg_rauhtd_ipv4_ent_a 6711 * Activity. Set for new entries. Set if a packet lookup has hit on the 6712 * specific entry. 6713 * Access: RO 6714 */ 6715 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 6716 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 6717 6718 /* reg_rauhtd_ipv4_ent_rif 6719 * Router interface. 6720 * Access: RO 6721 */ 6722 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6723 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 6724 6725 /* reg_rauhtd_ipv4_ent_dip 6726 * Destination IPv4 address. 6727 * Access: RO 6728 */ 6729 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6730 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 6731 6732 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 6733 6734 /* reg_rauhtd_ipv6_ent_a 6735 * Activity. Set for new entries. Set if a packet lookup has hit on the 6736 * specific entry. 6737 * Access: RO 6738 */ 6739 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 6740 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 6741 6742 /* reg_rauhtd_ipv6_ent_rif 6743 * Router interface. 6744 * Access: RO 6745 */ 6746 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6747 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 6748 6749 /* reg_rauhtd_ipv6_ent_dip 6750 * Destination IPv6 address. 6751 * Access: RO 6752 */ 6753 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 6754 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 6755 6756 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 6757 int ent_index, u16 *p_rif, 6758 u32 *p_dip) 6759 { 6760 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 6761 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 6762 } 6763 6764 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 6765 int rec_index, u16 *p_rif, 6766 char *p_dip) 6767 { 6768 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 6769 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 6770 } 6771 6772 /* RTDP - Routing Tunnel Decap Properties Register 6773 * ----------------------------------------------- 6774 * The RTDP register is used for configuring the tunnel decap properties of NVE 6775 * and IPinIP. 6776 */ 6777 #define MLXSW_REG_RTDP_ID 0x8020 6778 #define MLXSW_REG_RTDP_LEN 0x44 6779 6780 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 6781 6782 enum mlxsw_reg_rtdp_type { 6783 MLXSW_REG_RTDP_TYPE_NVE, 6784 MLXSW_REG_RTDP_TYPE_IPIP, 6785 }; 6786 6787 /* reg_rtdp_type 6788 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 6789 * Access: RW 6790 */ 6791 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 6792 6793 /* reg_rtdp_tunnel_index 6794 * Index to the Decap entry. 6795 * For Spectrum, Index to KVD Linear. 6796 * Access: Index 6797 */ 6798 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 6799 6800 /* IPinIP */ 6801 6802 /* reg_rtdp_ipip_irif 6803 * Ingress Router Interface for the overlay router 6804 * Access: RW 6805 */ 6806 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 6807 6808 enum mlxsw_reg_rtdp_ipip_sip_check { 6809 /* No sip checks. */ 6810 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 6811 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 6812 * equal ipv4_usip. 6813 */ 6814 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 6815 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 6816 * equal ipv6_usip. 6817 */ 6818 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 6819 }; 6820 6821 /* reg_rtdp_ipip_sip_check 6822 * SIP check to perform. If decapsulation failed due to these configurations 6823 * then trap_id is IPIP_DECAP_ERROR. 6824 * Access: RW 6825 */ 6826 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 6827 6828 /* If set, allow decapsulation of IPinIP (without GRE). */ 6829 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 6830 /* If set, allow decapsulation of IPinGREinIP without a key. */ 6831 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 6832 /* If set, allow decapsulation of IPinGREinIP with a key. */ 6833 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 6834 6835 /* reg_rtdp_ipip_type_check 6836 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 6837 * these configurations then trap_id is IPIP_DECAP_ERROR. 6838 * Access: RW 6839 */ 6840 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 6841 6842 /* reg_rtdp_ipip_gre_key_check 6843 * Whether GRE key should be checked. When check is enabled: 6844 * - A packet received as IPinIP (without GRE) will always pass. 6845 * - A packet received as IPinGREinIP without a key will not pass the check. 6846 * - A packet received as IPinGREinIP with a key will pass the check only if the 6847 * key in the packet is equal to expected_gre_key. 6848 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 6849 * Access: RW 6850 */ 6851 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 6852 6853 /* reg_rtdp_ipip_ipv4_usip 6854 * Underlay IPv4 address for ipv4 source address check. 6855 * Reserved when sip_check is not '1'. 6856 * Access: RW 6857 */ 6858 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 6859 6860 /* reg_rtdp_ipip_ipv6_usip_ptr 6861 * This field is valid when sip_check is "sipv6 check explicitly". This is a 6862 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 6863 * is to the KVD linear. 6864 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 6865 * Access: RW 6866 */ 6867 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 6868 6869 /* reg_rtdp_ipip_expected_gre_key 6870 * GRE key for checking. 6871 * Reserved when gre_key_check is '0'. 6872 * Access: RW 6873 */ 6874 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 6875 6876 static inline void mlxsw_reg_rtdp_pack(char *payload, 6877 enum mlxsw_reg_rtdp_type type, 6878 u32 tunnel_index) 6879 { 6880 MLXSW_REG_ZERO(rtdp, payload); 6881 mlxsw_reg_rtdp_type_set(payload, type); 6882 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 6883 } 6884 6885 static inline void 6886 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 6887 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 6888 unsigned int type_check, bool gre_key_check, 6889 u32 ipv4_usip, u32 expected_gre_key) 6890 { 6891 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 6892 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 6893 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 6894 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 6895 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 6896 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 6897 } 6898 6899 /* RIGR-V2 - Router Interface Group Register Version 2 6900 * --------------------------------------------------- 6901 * The RIGR_V2 register is used to add, remove and query egress interface list 6902 * of a multicast forwarding entry. 6903 */ 6904 #define MLXSW_REG_RIGR2_ID 0x8023 6905 #define MLXSW_REG_RIGR2_LEN 0xB0 6906 6907 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 6908 6909 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 6910 6911 /* reg_rigr2_rigr_index 6912 * KVD Linear index. 6913 * Access: Index 6914 */ 6915 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 6916 6917 /* reg_rigr2_vnext 6918 * Next RIGR Index is valid. 6919 * Access: RW 6920 */ 6921 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 6922 6923 /* reg_rigr2_next_rigr_index 6924 * Next RIGR Index. The index is to the KVD linear. 6925 * Reserved when vnxet = '0'. 6926 * Access: RW 6927 */ 6928 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 6929 6930 /* reg_rigr2_vrmid 6931 * RMID Index is valid. 6932 * Access: RW 6933 */ 6934 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 6935 6936 /* reg_rigr2_rmid_index 6937 * RMID Index. 6938 * Range 0 .. max_mid - 1 6939 * Reserved when vrmid = '0'. 6940 * The index is to the Port Group Table (PGT) 6941 * Access: RW 6942 */ 6943 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 6944 6945 /* reg_rigr2_erif_entry_v 6946 * Egress Router Interface is valid. 6947 * Note that low-entries must be set if high-entries are set. For 6948 * example: if erif_entry[2].v is set then erif_entry[1].v and 6949 * erif_entry[0].v must be set. 6950 * Index can be from 0 to cap_mc_erif_list_entries-1 6951 * Access: RW 6952 */ 6953 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 6954 6955 /* reg_rigr2_erif_entry_erif 6956 * Egress Router Interface. 6957 * Valid range is from 0 to cap_max_router_interfaces - 1 6958 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 6959 * Access: RW 6960 */ 6961 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 6962 6963 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 6964 bool vnext, u32 next_rigr_index) 6965 { 6966 MLXSW_REG_ZERO(rigr2, payload); 6967 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 6968 mlxsw_reg_rigr2_vnext_set(payload, vnext); 6969 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 6970 mlxsw_reg_rigr2_vrmid_set(payload, 0); 6971 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 6972 } 6973 6974 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 6975 bool v, u16 erif) 6976 { 6977 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 6978 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 6979 } 6980 6981 /* RECR-V2 - Router ECMP Configuration Version 2 Register 6982 * ------------------------------------------------------ 6983 */ 6984 #define MLXSW_REG_RECR2_ID 0x8025 6985 #define MLXSW_REG_RECR2_LEN 0x38 6986 6987 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 6988 6989 /* reg_recr2_pp 6990 * Per-port configuration 6991 * Access: Index 6992 */ 6993 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 6994 6995 /* reg_recr2_sh 6996 * Symmetric hash 6997 * Access: RW 6998 */ 6999 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7000 7001 /* reg_recr2_seed 7002 * Seed 7003 * Access: RW 7004 */ 7005 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7006 7007 enum { 7008 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7009 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7010 /* Enable IPv4 fields if packet is TCP or UDP */ 7011 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7012 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7013 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7014 /* Enable IPv6 fields if packet is TCP or UDP */ 7015 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7016 /* Enable TCP/UDP header fields if packet is IPv4 */ 7017 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7018 /* Enable TCP/UDP header fields if packet is IPv6 */ 7019 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7020 }; 7021 7022 /* reg_recr2_outer_header_enables 7023 * Bit mask where each bit enables a specific layer to be included in 7024 * the hash calculation. 7025 * Access: RW 7026 */ 7027 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7028 7029 enum { 7030 /* IPv4 Source IP */ 7031 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7032 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7033 /* IPv4 Destination IP */ 7034 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7035 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7036 /* IP Protocol */ 7037 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7038 /* IPv6 Source IP */ 7039 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7040 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7041 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7042 /* IPv6 Destination IP */ 7043 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7044 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7045 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7046 /* IPv6 Next Header */ 7047 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7048 /* IPv6 Flow Label */ 7049 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7050 /* TCP/UDP Source Port */ 7051 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7052 /* TCP/UDP Destination Port */ 7053 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7054 }; 7055 7056 /* reg_recr2_outer_header_fields_enable 7057 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7058 * Access: RW 7059 */ 7060 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7061 7062 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7063 { 7064 int i; 7065 7066 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7067 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7068 true); 7069 } 7070 7071 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7072 { 7073 int i; 7074 7075 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7076 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7077 true); 7078 } 7079 7080 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7081 { 7082 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7083 7084 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7085 7086 i = MLXSW_REG_RECR2_IPV6_SIP8; 7087 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7088 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7089 true); 7090 } 7091 7092 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7093 { 7094 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7095 7096 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7097 7098 i = MLXSW_REG_RECR2_IPV6_DIP8; 7099 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7100 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7101 true); 7102 } 7103 7104 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7105 { 7106 MLXSW_REG_ZERO(recr2, payload); 7107 mlxsw_reg_recr2_pp_set(payload, false); 7108 mlxsw_reg_recr2_sh_set(payload, true); 7109 mlxsw_reg_recr2_seed_set(payload, seed); 7110 } 7111 7112 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7113 * -------------------------------------------------------------- 7114 * The RMFT_V2 register is used to configure and query the multicast table. 7115 */ 7116 #define MLXSW_REG_RMFT2_ID 0x8027 7117 #define MLXSW_REG_RMFT2_LEN 0x174 7118 7119 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7120 7121 /* reg_rmft2_v 7122 * Valid 7123 * Access: RW 7124 */ 7125 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7126 7127 enum mlxsw_reg_rmft2_type { 7128 MLXSW_REG_RMFT2_TYPE_IPV4, 7129 MLXSW_REG_RMFT2_TYPE_IPV6 7130 }; 7131 7132 /* reg_rmft2_type 7133 * Access: Index 7134 */ 7135 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7136 7137 enum mlxsw_sp_reg_rmft2_op { 7138 /* For Write: 7139 * Write operation. Used to write a new entry to the table. All RW 7140 * fields are relevant for new entry. Activity bit is set for new 7141 * entries - Note write with v (Valid) 0 will delete the entry. 7142 * For Query: 7143 * Read operation 7144 */ 7145 MLXSW_REG_RMFT2_OP_READ_WRITE, 7146 }; 7147 7148 /* reg_rmft2_op 7149 * Operation. 7150 * Access: OP 7151 */ 7152 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7153 7154 /* reg_rmft2_a 7155 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7156 * entry. 7157 * Access: RO 7158 */ 7159 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7160 7161 /* reg_rmft2_offset 7162 * Offset within the multicast forwarding table to write to. 7163 * Access: Index 7164 */ 7165 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7166 7167 /* reg_rmft2_virtual_router 7168 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7169 * Access: RW 7170 */ 7171 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7172 7173 enum mlxsw_reg_rmft2_irif_mask { 7174 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7175 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7176 }; 7177 7178 /* reg_rmft2_irif_mask 7179 * Ingress RIF mask. 7180 * Access: RW 7181 */ 7182 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7183 7184 /* reg_rmft2_irif 7185 * Ingress RIF index. 7186 * Access: RW 7187 */ 7188 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7189 7190 /* reg_rmft2_dip{4,6} 7191 * Destination IPv4/6 address 7192 * Access: RW 7193 */ 7194 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7195 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7196 7197 /* reg_rmft2_dip{4,6}_mask 7198 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7199 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7200 * Access: RW 7201 */ 7202 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7203 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7204 7205 /* reg_rmft2_sip{4,6} 7206 * Source IPv4/6 address 7207 * Access: RW 7208 */ 7209 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7210 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7211 7212 /* reg_rmft2_sip{4,6}_mask 7213 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7214 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7215 * Access: RW 7216 */ 7217 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7218 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7219 7220 /* reg_rmft2_flexible_action_set 7221 * ACL action set. The only supported action types in this field and in any 7222 * action-set pointed from here are as follows: 7223 * 00h: ACTION_NULL 7224 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7225 * 03h: ACTION_TRAP 7226 * 06h: ACTION_QOS 7227 * 08h: ACTION_POLICING_MONITORING 7228 * 10h: ACTION_ROUTER_MC 7229 * Access: RW 7230 */ 7231 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7232 MLXSW_REG_FLEX_ACTION_SET_LEN); 7233 7234 static inline void 7235 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7236 u16 virtual_router, 7237 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7238 const char *flex_action_set) 7239 { 7240 MLXSW_REG_ZERO(rmft2, payload); 7241 mlxsw_reg_rmft2_v_set(payload, v); 7242 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7243 mlxsw_reg_rmft2_offset_set(payload, offset); 7244 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7245 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7246 mlxsw_reg_rmft2_irif_set(payload, irif); 7247 if (flex_action_set) 7248 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7249 flex_action_set); 7250 } 7251 7252 static inline void 7253 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7254 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7255 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7256 const char *flexible_action_set) 7257 { 7258 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7259 irif_mask, irif, flexible_action_set); 7260 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7261 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7262 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7263 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7264 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7265 } 7266 7267 static inline void 7268 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7269 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7270 struct in6_addr dip6, struct in6_addr dip6_mask, 7271 struct in6_addr sip6, struct in6_addr sip6_mask, 7272 const char *flexible_action_set) 7273 { 7274 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7275 irif_mask, irif, flexible_action_set); 7276 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 7277 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 7278 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 7279 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 7280 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 7281 } 7282 7283 /* MFCR - Management Fan Control Register 7284 * -------------------------------------- 7285 * This register controls the settings of the Fan Speed PWM mechanism. 7286 */ 7287 #define MLXSW_REG_MFCR_ID 0x9001 7288 #define MLXSW_REG_MFCR_LEN 0x08 7289 7290 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 7291 7292 enum mlxsw_reg_mfcr_pwm_frequency { 7293 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 7294 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 7295 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 7296 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 7297 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 7298 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 7299 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 7300 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 7301 }; 7302 7303 /* reg_mfcr_pwm_frequency 7304 * Controls the frequency of the PWM signal. 7305 * Access: RW 7306 */ 7307 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 7308 7309 #define MLXSW_MFCR_TACHOS_MAX 10 7310 7311 /* reg_mfcr_tacho_active 7312 * Indicates which of the tachometer is active (bit per tachometer). 7313 * Access: RO 7314 */ 7315 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 7316 7317 #define MLXSW_MFCR_PWMS_MAX 5 7318 7319 /* reg_mfcr_pwm_active 7320 * Indicates which of the PWM control is active (bit per PWM). 7321 * Access: RO 7322 */ 7323 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 7324 7325 static inline void 7326 mlxsw_reg_mfcr_pack(char *payload, 7327 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 7328 { 7329 MLXSW_REG_ZERO(mfcr, payload); 7330 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 7331 } 7332 7333 static inline void 7334 mlxsw_reg_mfcr_unpack(char *payload, 7335 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 7336 u16 *p_tacho_active, u8 *p_pwm_active) 7337 { 7338 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 7339 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 7340 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 7341 } 7342 7343 /* MFSC - Management Fan Speed Control Register 7344 * -------------------------------------------- 7345 * This register controls the settings of the Fan Speed PWM mechanism. 7346 */ 7347 #define MLXSW_REG_MFSC_ID 0x9002 7348 #define MLXSW_REG_MFSC_LEN 0x08 7349 7350 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 7351 7352 /* reg_mfsc_pwm 7353 * Fan pwm to control / monitor. 7354 * Access: Index 7355 */ 7356 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 7357 7358 /* reg_mfsc_pwm_duty_cycle 7359 * Controls the duty cycle of the PWM. Value range from 0..255 to 7360 * represent duty cycle of 0%...100%. 7361 * Access: RW 7362 */ 7363 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 7364 7365 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 7366 u8 pwm_duty_cycle) 7367 { 7368 MLXSW_REG_ZERO(mfsc, payload); 7369 mlxsw_reg_mfsc_pwm_set(payload, pwm); 7370 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 7371 } 7372 7373 /* MFSM - Management Fan Speed Measurement 7374 * --------------------------------------- 7375 * This register controls the settings of the Tacho measurements and 7376 * enables reading the Tachometer measurements. 7377 */ 7378 #define MLXSW_REG_MFSM_ID 0x9003 7379 #define MLXSW_REG_MFSM_LEN 0x08 7380 7381 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 7382 7383 /* reg_mfsm_tacho 7384 * Fan tachometer index. 7385 * Access: Index 7386 */ 7387 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 7388 7389 /* reg_mfsm_rpm 7390 * Fan speed (round per minute). 7391 * Access: RO 7392 */ 7393 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 7394 7395 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 7396 { 7397 MLXSW_REG_ZERO(mfsm, payload); 7398 mlxsw_reg_mfsm_tacho_set(payload, tacho); 7399 } 7400 7401 /* MFSL - Management Fan Speed Limit Register 7402 * ------------------------------------------ 7403 * The Fan Speed Limit register is used to configure the fan speed 7404 * event / interrupt notification mechanism. Fan speed threshold are 7405 * defined for both under-speed and over-speed. 7406 */ 7407 #define MLXSW_REG_MFSL_ID 0x9004 7408 #define MLXSW_REG_MFSL_LEN 0x0C 7409 7410 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 7411 7412 /* reg_mfsl_tacho 7413 * Fan tachometer index. 7414 * Access: Index 7415 */ 7416 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 7417 7418 /* reg_mfsl_tach_min 7419 * Tachometer minimum value (minimum RPM). 7420 * Access: RW 7421 */ 7422 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 7423 7424 /* reg_mfsl_tach_max 7425 * Tachometer maximum value (maximum RPM). 7426 * Access: RW 7427 */ 7428 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 7429 7430 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 7431 u16 tach_min, u16 tach_max) 7432 { 7433 MLXSW_REG_ZERO(mfsl, payload); 7434 mlxsw_reg_mfsl_tacho_set(payload, tacho); 7435 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 7436 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 7437 } 7438 7439 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 7440 u16 *p_tach_min, u16 *p_tach_max) 7441 { 7442 if (p_tach_min) 7443 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 7444 7445 if (p_tach_max) 7446 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 7447 } 7448 7449 /* MTCAP - Management Temperature Capabilities 7450 * ------------------------------------------- 7451 * This register exposes the capabilities of the device and 7452 * system temperature sensing. 7453 */ 7454 #define MLXSW_REG_MTCAP_ID 0x9009 7455 #define MLXSW_REG_MTCAP_LEN 0x08 7456 7457 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 7458 7459 /* reg_mtcap_sensor_count 7460 * Number of sensors supported by the device. 7461 * This includes the QSFP module sensors (if exists in the QSFP module). 7462 * Access: RO 7463 */ 7464 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 7465 7466 /* MTMP - Management Temperature 7467 * ----------------------------- 7468 * This register controls the settings of the temperature measurements 7469 * and enables reading the temperature measurements. Note that temperature 7470 * is in 0.125 degrees Celsius. 7471 */ 7472 #define MLXSW_REG_MTMP_ID 0x900A 7473 #define MLXSW_REG_MTMP_LEN 0x20 7474 7475 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 7476 7477 /* reg_mtmp_sensor_index 7478 * Sensors index to access. 7479 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 7480 * (module 0 is mapped to sensor_index 64). 7481 * Access: Index 7482 */ 7483 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 7484 7485 /* Convert to milli degrees Celsius */ 7486 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 7487 7488 /* reg_mtmp_temperature 7489 * Temperature reading from the sensor. Reading is in 0.125 Celsius 7490 * degrees units. 7491 * Access: RO 7492 */ 7493 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 7494 7495 /* reg_mtmp_mte 7496 * Max Temperature Enable - enables measuring the max temperature on a sensor. 7497 * Access: RW 7498 */ 7499 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 7500 7501 /* reg_mtmp_mtr 7502 * Max Temperature Reset - clears the value of the max temperature register. 7503 * Access: WO 7504 */ 7505 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 7506 7507 /* reg_mtmp_max_temperature 7508 * The highest measured temperature from the sensor. 7509 * When the bit mte is cleared, the field max_temperature is reserved. 7510 * Access: RO 7511 */ 7512 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 7513 7514 /* reg_mtmp_tee 7515 * Temperature Event Enable. 7516 * 0 - Do not generate event 7517 * 1 - Generate event 7518 * 2 - Generate single event 7519 * Access: RW 7520 */ 7521 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 7522 7523 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 7524 7525 /* reg_mtmp_temperature_threshold_hi 7526 * High threshold for Temperature Warning Event. In 0.125 Celsius. 7527 * Access: RW 7528 */ 7529 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 7530 7531 /* reg_mtmp_temperature_threshold_lo 7532 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 7533 * Access: RW 7534 */ 7535 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 7536 7537 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 7538 7539 /* reg_mtmp_sensor_name 7540 * Sensor Name 7541 * Access: RO 7542 */ 7543 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 7544 7545 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 7546 bool max_temp_enable, 7547 bool max_temp_reset) 7548 { 7549 MLXSW_REG_ZERO(mtmp, payload); 7550 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 7551 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 7552 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 7553 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 7554 MLXSW_REG_MTMP_THRESH_HI); 7555 } 7556 7557 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 7558 unsigned int *p_max_temp, 7559 char *sensor_name) 7560 { 7561 u16 temp; 7562 7563 if (p_temp) { 7564 temp = mlxsw_reg_mtmp_temperature_get(payload); 7565 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7566 } 7567 if (p_max_temp) { 7568 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 7569 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7570 } 7571 if (sensor_name) 7572 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 7573 } 7574 7575 /* MCIA - Management Cable Info Access 7576 * ----------------------------------- 7577 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 7578 */ 7579 7580 #define MLXSW_REG_MCIA_ID 0x9014 7581 #define MLXSW_REG_MCIA_LEN 0x40 7582 7583 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 7584 7585 /* reg_mcia_l 7586 * Lock bit. Setting this bit will lock the access to the specific 7587 * cable. Used for updating a full page in a cable EPROM. Any access 7588 * other then subsequence writes will fail while the port is locked. 7589 * Access: RW 7590 */ 7591 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 7592 7593 /* reg_mcia_module 7594 * Module number. 7595 * Access: Index 7596 */ 7597 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 7598 7599 /* reg_mcia_status 7600 * Module status. 7601 * Access: RO 7602 */ 7603 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 7604 7605 /* reg_mcia_i2c_device_address 7606 * I2C device address. 7607 * Access: RW 7608 */ 7609 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 7610 7611 /* reg_mcia_page_number 7612 * Page number. 7613 * Access: RW 7614 */ 7615 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 7616 7617 /* reg_mcia_device_address 7618 * Device address. 7619 * Access: RW 7620 */ 7621 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 7622 7623 /* reg_mcia_size 7624 * Number of bytes to read/write (up to 48 bytes). 7625 * Access: RW 7626 */ 7627 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 7628 7629 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 7630 7631 /* reg_mcia_eeprom 7632 * Bytes to read/write. 7633 * Access: RW 7634 */ 7635 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 7636 7637 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 7638 u8 page_number, u16 device_addr, 7639 u8 size, u8 i2c_device_addr) 7640 { 7641 MLXSW_REG_ZERO(mcia, payload); 7642 mlxsw_reg_mcia_module_set(payload, module); 7643 mlxsw_reg_mcia_l_set(payload, lock); 7644 mlxsw_reg_mcia_page_number_set(payload, page_number); 7645 mlxsw_reg_mcia_device_address_set(payload, device_addr); 7646 mlxsw_reg_mcia_size_set(payload, size); 7647 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 7648 } 7649 7650 /* MPAT - Monitoring Port Analyzer Table 7651 * ------------------------------------- 7652 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 7653 * For an enabled analyzer, all fields except e (enable) cannot be modified. 7654 */ 7655 #define MLXSW_REG_MPAT_ID 0x901A 7656 #define MLXSW_REG_MPAT_LEN 0x78 7657 7658 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 7659 7660 /* reg_mpat_pa_id 7661 * Port Analyzer ID. 7662 * Access: Index 7663 */ 7664 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 7665 7666 /* reg_mpat_system_port 7667 * A unique port identifier for the final destination of the packet. 7668 * Access: RW 7669 */ 7670 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 7671 7672 /* reg_mpat_e 7673 * Enable. Indicating the Port Analyzer is enabled. 7674 * Access: RW 7675 */ 7676 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 7677 7678 /* reg_mpat_qos 7679 * Quality Of Service Mode. 7680 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 7681 * PCP, DEI, DSCP or VL) are configured. 7682 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 7683 * same as in the original packet that has triggered the mirroring. For 7684 * SPAN also the pcp,dei are maintained. 7685 * Access: RW 7686 */ 7687 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 7688 7689 /* reg_mpat_be 7690 * Best effort mode. Indicates mirroring traffic should not cause packet 7691 * drop or back pressure, but will discard the mirrored packets. Mirrored 7692 * packets will be forwarded on a best effort manner. 7693 * 0: Do not discard mirrored packets 7694 * 1: Discard mirrored packets if causing congestion 7695 * Access: RW 7696 */ 7697 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 7698 7699 enum mlxsw_reg_mpat_span_type { 7700 /* Local SPAN Ethernet. 7701 * The original packet is not encapsulated. 7702 */ 7703 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 7704 7705 /* Remote SPAN Ethernet VLAN. 7706 * The packet is forwarded to the monitoring port on the monitoring 7707 * VLAN. 7708 */ 7709 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 7710 7711 /* Encapsulated Remote SPAN Ethernet L3 GRE. 7712 * The packet is encapsulated with GRE header. 7713 */ 7714 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 7715 }; 7716 7717 /* reg_mpat_span_type 7718 * SPAN type. 7719 * Access: RW 7720 */ 7721 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 7722 7723 /* Remote SPAN - Ethernet VLAN 7724 * - - - - - - - - - - - - - - 7725 */ 7726 7727 /* reg_mpat_eth_rspan_vid 7728 * Encapsulation header VLAN ID. 7729 * Access: RW 7730 */ 7731 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 7732 7733 /* Encapsulated Remote SPAN - Ethernet L2 7734 * - - - - - - - - - - - - - - - - - - - 7735 */ 7736 7737 enum mlxsw_reg_mpat_eth_rspan_version { 7738 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 7739 }; 7740 7741 /* reg_mpat_eth_rspan_version 7742 * RSPAN mirror header version. 7743 * Access: RW 7744 */ 7745 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 7746 7747 /* reg_mpat_eth_rspan_mac 7748 * Destination MAC address. 7749 * Access: RW 7750 */ 7751 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 7752 7753 /* reg_mpat_eth_rspan_tp 7754 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 7755 * Access: RW 7756 */ 7757 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 7758 7759 /* Encapsulated Remote SPAN - Ethernet L3 7760 * - - - - - - - - - - - - - - - - - - - 7761 */ 7762 7763 enum mlxsw_reg_mpat_eth_rspan_protocol { 7764 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 7765 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 7766 }; 7767 7768 /* reg_mpat_eth_rspan_protocol 7769 * SPAN encapsulation protocol. 7770 * Access: RW 7771 */ 7772 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 7773 7774 /* reg_mpat_eth_rspan_ttl 7775 * Encapsulation header Time-to-Live/HopLimit. 7776 * Access: RW 7777 */ 7778 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 7779 7780 /* reg_mpat_eth_rspan_smac 7781 * Source MAC address 7782 * Access: RW 7783 */ 7784 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 7785 7786 /* reg_mpat_eth_rspan_dip* 7787 * Destination IP address. The IP version is configured by protocol. 7788 * Access: RW 7789 */ 7790 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 7791 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 7792 7793 /* reg_mpat_eth_rspan_sip* 7794 * Source IP address. The IP version is configured by protocol. 7795 * Access: RW 7796 */ 7797 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 7798 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 7799 7800 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 7801 u16 system_port, bool e, 7802 enum mlxsw_reg_mpat_span_type span_type) 7803 { 7804 MLXSW_REG_ZERO(mpat, payload); 7805 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 7806 mlxsw_reg_mpat_system_port_set(payload, system_port); 7807 mlxsw_reg_mpat_e_set(payload, e); 7808 mlxsw_reg_mpat_qos_set(payload, 1); 7809 mlxsw_reg_mpat_be_set(payload, 1); 7810 mlxsw_reg_mpat_span_type_set(payload, span_type); 7811 } 7812 7813 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 7814 { 7815 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 7816 } 7817 7818 static inline void 7819 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 7820 enum mlxsw_reg_mpat_eth_rspan_version version, 7821 const char *mac, 7822 bool tp) 7823 { 7824 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 7825 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 7826 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 7827 } 7828 7829 static inline void 7830 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 7831 const char *smac, 7832 u32 sip, u32 dip) 7833 { 7834 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 7835 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 7836 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 7837 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 7838 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 7839 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 7840 } 7841 7842 static inline void 7843 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 7844 const char *smac, 7845 struct in6_addr sip, struct in6_addr dip) 7846 { 7847 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 7848 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 7849 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 7850 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 7851 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 7852 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 7853 } 7854 7855 /* MPAR - Monitoring Port Analyzer Register 7856 * ---------------------------------------- 7857 * MPAR register is used to query and configure the port analyzer port mirroring 7858 * properties. 7859 */ 7860 #define MLXSW_REG_MPAR_ID 0x901B 7861 #define MLXSW_REG_MPAR_LEN 0x08 7862 7863 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 7864 7865 /* reg_mpar_local_port 7866 * The local port to mirror the packets from. 7867 * Access: Index 7868 */ 7869 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 7870 7871 enum mlxsw_reg_mpar_i_e { 7872 MLXSW_REG_MPAR_TYPE_EGRESS, 7873 MLXSW_REG_MPAR_TYPE_INGRESS, 7874 }; 7875 7876 /* reg_mpar_i_e 7877 * Ingress/Egress 7878 * Access: Index 7879 */ 7880 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 7881 7882 /* reg_mpar_enable 7883 * Enable mirroring 7884 * By default, port mirroring is disabled for all ports. 7885 * Access: RW 7886 */ 7887 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 7888 7889 /* reg_mpar_pa_id 7890 * Port Analyzer ID. 7891 * Access: RW 7892 */ 7893 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 7894 7895 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 7896 enum mlxsw_reg_mpar_i_e i_e, 7897 bool enable, u8 pa_id) 7898 { 7899 MLXSW_REG_ZERO(mpar, payload); 7900 mlxsw_reg_mpar_local_port_set(payload, local_port); 7901 mlxsw_reg_mpar_enable_set(payload, enable); 7902 mlxsw_reg_mpar_i_e_set(payload, i_e); 7903 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 7904 } 7905 7906 /* MRSR - Management Reset and Shutdown Register 7907 * --------------------------------------------- 7908 * MRSR register is used to reset or shutdown the switch or 7909 * the entire system (when applicable). 7910 */ 7911 #define MLXSW_REG_MRSR_ID 0x9023 7912 #define MLXSW_REG_MRSR_LEN 0x08 7913 7914 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 7915 7916 /* reg_mrsr_command 7917 * Reset/shutdown command 7918 * 0 - do nothing 7919 * 1 - software reset 7920 * Access: WO 7921 */ 7922 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 7923 7924 static inline void mlxsw_reg_mrsr_pack(char *payload) 7925 { 7926 MLXSW_REG_ZERO(mrsr, payload); 7927 mlxsw_reg_mrsr_command_set(payload, 1); 7928 } 7929 7930 /* MLCR - Management LED Control Register 7931 * -------------------------------------- 7932 * Controls the system LEDs. 7933 */ 7934 #define MLXSW_REG_MLCR_ID 0x902B 7935 #define MLXSW_REG_MLCR_LEN 0x0C 7936 7937 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 7938 7939 /* reg_mlcr_local_port 7940 * Local port number. 7941 * Access: RW 7942 */ 7943 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 7944 7945 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 7946 7947 /* reg_mlcr_beacon_duration 7948 * Duration of the beacon to be active, in seconds. 7949 * 0x0 - Will turn off the beacon. 7950 * 0xFFFF - Will turn on the beacon until explicitly turned off. 7951 * Access: RW 7952 */ 7953 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 7954 7955 /* reg_mlcr_beacon_remain 7956 * Remaining duration of the beacon, in seconds. 7957 * 0xFFFF indicates an infinite amount of time. 7958 * Access: RO 7959 */ 7960 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 7961 7962 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 7963 bool active) 7964 { 7965 MLXSW_REG_ZERO(mlcr, payload); 7966 mlxsw_reg_mlcr_local_port_set(payload, local_port); 7967 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 7968 MLXSW_REG_MLCR_DURATION_MAX : 0); 7969 } 7970 7971 /* MCQI - Management Component Query Information 7972 * --------------------------------------------- 7973 * This register allows querying information about firmware components. 7974 */ 7975 #define MLXSW_REG_MCQI_ID 0x9061 7976 #define MLXSW_REG_MCQI_BASE_LEN 0x18 7977 #define MLXSW_REG_MCQI_CAP_LEN 0x14 7978 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 7979 7980 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 7981 7982 /* reg_mcqi_component_index 7983 * Index of the accessed component. 7984 * Access: Index 7985 */ 7986 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 7987 7988 enum mlxfw_reg_mcqi_info_type { 7989 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 7990 }; 7991 7992 /* reg_mcqi_info_type 7993 * Component properties set. 7994 * Access: RW 7995 */ 7996 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 7997 7998 /* reg_mcqi_offset 7999 * The requested/returned data offset from the section start, given in bytes. 8000 * Must be DWORD aligned. 8001 * Access: RW 8002 */ 8003 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 8004 8005 /* reg_mcqi_data_size 8006 * The requested/returned data size, given in bytes. If data_size is not DWORD 8007 * aligned, the last bytes are zero padded. 8008 * Access: RW 8009 */ 8010 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 8011 8012 /* reg_mcqi_cap_max_component_size 8013 * Maximum size for this component, given in bytes. 8014 * Access: RO 8015 */ 8016 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 8017 8018 /* reg_mcqi_cap_log_mcda_word_size 8019 * Log 2 of the access word size in bytes. Read and write access must be aligned 8020 * to the word size. Write access must be done for an integer number of words. 8021 * Access: RO 8022 */ 8023 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 8024 8025 /* reg_mcqi_cap_mcda_max_write_size 8026 * Maximal write size for MCDA register 8027 * Access: RO 8028 */ 8029 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 8030 8031 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 8032 { 8033 MLXSW_REG_ZERO(mcqi, payload); 8034 mlxsw_reg_mcqi_component_index_set(payload, component_index); 8035 mlxsw_reg_mcqi_info_type_set(payload, 8036 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 8037 mlxsw_reg_mcqi_offset_set(payload, 0); 8038 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 8039 } 8040 8041 static inline void mlxsw_reg_mcqi_unpack(char *payload, 8042 u32 *p_cap_max_component_size, 8043 u8 *p_cap_log_mcda_word_size, 8044 u16 *p_cap_mcda_max_write_size) 8045 { 8046 *p_cap_max_component_size = 8047 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 8048 *p_cap_log_mcda_word_size = 8049 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 8050 *p_cap_mcda_max_write_size = 8051 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 8052 } 8053 8054 /* MCC - Management Component Control 8055 * ---------------------------------- 8056 * Controls the firmware component and updates the FSM. 8057 */ 8058 #define MLXSW_REG_MCC_ID 0x9062 8059 #define MLXSW_REG_MCC_LEN 0x1C 8060 8061 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 8062 8063 enum mlxsw_reg_mcc_instruction { 8064 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 8065 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 8066 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 8067 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 8068 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 8069 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 8070 }; 8071 8072 /* reg_mcc_instruction 8073 * Command to be executed by the FSM. 8074 * Applicable for write operation only. 8075 * Access: RW 8076 */ 8077 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 8078 8079 /* reg_mcc_component_index 8080 * Index of the accessed component. Applicable only for commands that 8081 * refer to components. Otherwise, this field is reserved. 8082 * Access: Index 8083 */ 8084 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 8085 8086 /* reg_mcc_update_handle 8087 * Token representing the current flow executed by the FSM. 8088 * Access: WO 8089 */ 8090 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 8091 8092 /* reg_mcc_error_code 8093 * Indicates the successful completion of the instruction, or the reason it 8094 * failed 8095 * Access: RO 8096 */ 8097 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 8098 8099 /* reg_mcc_control_state 8100 * Current FSM state 8101 * Access: RO 8102 */ 8103 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 8104 8105 /* reg_mcc_component_size 8106 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 8107 * the size may shorten the update time. Value 0x0 means that size is 8108 * unspecified. 8109 * Access: WO 8110 */ 8111 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 8112 8113 static inline void mlxsw_reg_mcc_pack(char *payload, 8114 enum mlxsw_reg_mcc_instruction instr, 8115 u16 component_index, u32 update_handle, 8116 u32 component_size) 8117 { 8118 MLXSW_REG_ZERO(mcc, payload); 8119 mlxsw_reg_mcc_instruction_set(payload, instr); 8120 mlxsw_reg_mcc_component_index_set(payload, component_index); 8121 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 8122 mlxsw_reg_mcc_component_size_set(payload, component_size); 8123 } 8124 8125 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 8126 u8 *p_error_code, u8 *p_control_state) 8127 { 8128 if (p_update_handle) 8129 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 8130 if (p_error_code) 8131 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 8132 if (p_control_state) 8133 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 8134 } 8135 8136 /* MCDA - Management Component Data Access 8137 * --------------------------------------- 8138 * This register allows reading and writing a firmware component. 8139 */ 8140 #define MLXSW_REG_MCDA_ID 0x9063 8141 #define MLXSW_REG_MCDA_BASE_LEN 0x10 8142 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 8143 #define MLXSW_REG_MCDA_LEN \ 8144 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 8145 8146 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 8147 8148 /* reg_mcda_update_handle 8149 * Token representing the current flow executed by the FSM. 8150 * Access: RW 8151 */ 8152 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 8153 8154 /* reg_mcda_offset 8155 * Offset of accessed address relative to component start. Accesses must be in 8156 * accordance to log_mcda_word_size in MCQI reg. 8157 * Access: RW 8158 */ 8159 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 8160 8161 /* reg_mcda_size 8162 * Size of the data accessed, given in bytes. 8163 * Access: RW 8164 */ 8165 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 8166 8167 /* reg_mcda_data 8168 * Data block accessed. 8169 * Access: RW 8170 */ 8171 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 8172 8173 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 8174 u32 offset, u16 size, u8 *data) 8175 { 8176 int i; 8177 8178 MLXSW_REG_ZERO(mcda, payload); 8179 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 8180 mlxsw_reg_mcda_offset_set(payload, offset); 8181 mlxsw_reg_mcda_size_set(payload, size); 8182 8183 for (i = 0; i < size / 4; i++) 8184 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 8185 } 8186 8187 /* MPSC - Monitoring Packet Sampling Configuration Register 8188 * -------------------------------------------------------- 8189 * MPSC Register is used to configure the Packet Sampling mechanism. 8190 */ 8191 #define MLXSW_REG_MPSC_ID 0x9080 8192 #define MLXSW_REG_MPSC_LEN 0x1C 8193 8194 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 8195 8196 /* reg_mpsc_local_port 8197 * Local port number 8198 * Not supported for CPU port 8199 * Access: Index 8200 */ 8201 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 8202 8203 /* reg_mpsc_e 8204 * Enable sampling on port local_port 8205 * Access: RW 8206 */ 8207 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 8208 8209 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 8210 8211 /* reg_mpsc_rate 8212 * Sampling rate = 1 out of rate packets (with randomization around 8213 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 8214 * Access: RW 8215 */ 8216 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 8217 8218 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 8219 u32 rate) 8220 { 8221 MLXSW_REG_ZERO(mpsc, payload); 8222 mlxsw_reg_mpsc_local_port_set(payload, local_port); 8223 mlxsw_reg_mpsc_e_set(payload, e); 8224 mlxsw_reg_mpsc_rate_set(payload, rate); 8225 } 8226 8227 /* MGPC - Monitoring General Purpose Counter Set Register 8228 * The MGPC register retrieves and sets the General Purpose Counter Set. 8229 */ 8230 #define MLXSW_REG_MGPC_ID 0x9081 8231 #define MLXSW_REG_MGPC_LEN 0x18 8232 8233 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 8234 8235 /* reg_mgpc_counter_set_type 8236 * Counter set type. 8237 * Access: OP 8238 */ 8239 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 8240 8241 /* reg_mgpc_counter_index 8242 * Counter index. 8243 * Access: Index 8244 */ 8245 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 8246 8247 enum mlxsw_reg_mgpc_opcode { 8248 /* Nop */ 8249 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 8250 /* Clear counters */ 8251 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 8252 }; 8253 8254 /* reg_mgpc_opcode 8255 * Opcode. 8256 * Access: OP 8257 */ 8258 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 8259 8260 /* reg_mgpc_byte_counter 8261 * Byte counter value. 8262 * Access: RW 8263 */ 8264 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 8265 8266 /* reg_mgpc_packet_counter 8267 * Packet counter value. 8268 * Access: RW 8269 */ 8270 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 8271 8272 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 8273 enum mlxsw_reg_mgpc_opcode opcode, 8274 enum mlxsw_reg_flow_counter_set_type set_type) 8275 { 8276 MLXSW_REG_ZERO(mgpc, payload); 8277 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 8278 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 8279 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8280 } 8281 8282 /* TIGCR - Tunneling IPinIP General Configuration Register 8283 * ------------------------------------------------------- 8284 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 8285 */ 8286 #define MLXSW_REG_TIGCR_ID 0xA801 8287 #define MLXSW_REG_TIGCR_LEN 0x10 8288 8289 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 8290 8291 /* reg_tigcr_ipip_ttlc 8292 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 8293 * header. 8294 * Access: RW 8295 */ 8296 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 8297 8298 /* reg_tigcr_ipip_ttl_uc 8299 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 8300 * reg_tigcr_ipip_ttlc is unset. 8301 * Access: RW 8302 */ 8303 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 8304 8305 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 8306 { 8307 MLXSW_REG_ZERO(tigcr, payload); 8308 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 8309 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 8310 } 8311 8312 /* SBPR - Shared Buffer Pools Register 8313 * ----------------------------------- 8314 * The SBPR configures and retrieves the shared buffer pools and configuration. 8315 */ 8316 #define MLXSW_REG_SBPR_ID 0xB001 8317 #define MLXSW_REG_SBPR_LEN 0x14 8318 8319 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 8320 8321 /* shared direstion enum for SBPR, SBCM, SBPM */ 8322 enum mlxsw_reg_sbxx_dir { 8323 MLXSW_REG_SBXX_DIR_INGRESS, 8324 MLXSW_REG_SBXX_DIR_EGRESS, 8325 }; 8326 8327 /* reg_sbpr_dir 8328 * Direction. 8329 * Access: Index 8330 */ 8331 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 8332 8333 /* reg_sbpr_pool 8334 * Pool index. 8335 * Access: Index 8336 */ 8337 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 8338 8339 /* reg_sbpr_size 8340 * Pool size in buffer cells. 8341 * Access: RW 8342 */ 8343 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 8344 8345 enum mlxsw_reg_sbpr_mode { 8346 MLXSW_REG_SBPR_MODE_STATIC, 8347 MLXSW_REG_SBPR_MODE_DYNAMIC, 8348 }; 8349 8350 /* reg_sbpr_mode 8351 * Pool quota calculation mode. 8352 * Access: RW 8353 */ 8354 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 8355 8356 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 8357 enum mlxsw_reg_sbxx_dir dir, 8358 enum mlxsw_reg_sbpr_mode mode, u32 size) 8359 { 8360 MLXSW_REG_ZERO(sbpr, payload); 8361 mlxsw_reg_sbpr_pool_set(payload, pool); 8362 mlxsw_reg_sbpr_dir_set(payload, dir); 8363 mlxsw_reg_sbpr_mode_set(payload, mode); 8364 mlxsw_reg_sbpr_size_set(payload, size); 8365 } 8366 8367 /* SBCM - Shared Buffer Class Management Register 8368 * ---------------------------------------------- 8369 * The SBCM register configures and retrieves the shared buffer allocation 8370 * and configuration according to Port-PG, including the binding to pool 8371 * and definition of the associated quota. 8372 */ 8373 #define MLXSW_REG_SBCM_ID 0xB002 8374 #define MLXSW_REG_SBCM_LEN 0x28 8375 8376 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 8377 8378 /* reg_sbcm_local_port 8379 * Local port number. 8380 * For Ingress: excludes CPU port and Router port 8381 * For Egress: excludes IP Router 8382 * Access: Index 8383 */ 8384 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 8385 8386 /* reg_sbcm_pg_buff 8387 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 8388 * For PG buffer: range is 0..cap_max_pg_buffers - 1 8389 * For traffic class: range is 0..cap_max_tclass - 1 8390 * Note that when traffic class is in MC aware mode then the traffic 8391 * classes which are MC aware cannot be configured. 8392 * Access: Index 8393 */ 8394 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 8395 8396 /* reg_sbcm_dir 8397 * Direction. 8398 * Access: Index 8399 */ 8400 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 8401 8402 /* reg_sbcm_min_buff 8403 * Minimum buffer size for the limiter, in cells. 8404 * Access: RW 8405 */ 8406 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 8407 8408 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 8409 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 8410 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 8411 8412 /* reg_sbcm_max_buff 8413 * When the pool associated to the port-pg/tclass is configured to 8414 * static, Maximum buffer size for the limiter configured in cells. 8415 * When the pool associated to the port-pg/tclass is configured to 8416 * dynamic, the max_buff holds the "alpha" parameter, supporting 8417 * the following values: 8418 * 0: 0 8419 * i: (1/128)*2^(i-1), for i=1..14 8420 * 0xFF: Infinity 8421 * Access: RW 8422 */ 8423 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 8424 8425 /* reg_sbcm_pool 8426 * Association of the port-priority to a pool. 8427 * Access: RW 8428 */ 8429 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 8430 8431 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 8432 enum mlxsw_reg_sbxx_dir dir, 8433 u32 min_buff, u32 max_buff, u8 pool) 8434 { 8435 MLXSW_REG_ZERO(sbcm, payload); 8436 mlxsw_reg_sbcm_local_port_set(payload, local_port); 8437 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 8438 mlxsw_reg_sbcm_dir_set(payload, dir); 8439 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 8440 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 8441 mlxsw_reg_sbcm_pool_set(payload, pool); 8442 } 8443 8444 /* SBPM - Shared Buffer Port Management Register 8445 * --------------------------------------------- 8446 * The SBPM register configures and retrieves the shared buffer allocation 8447 * and configuration according to Port-Pool, including the definition 8448 * of the associated quota. 8449 */ 8450 #define MLXSW_REG_SBPM_ID 0xB003 8451 #define MLXSW_REG_SBPM_LEN 0x28 8452 8453 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 8454 8455 /* reg_sbpm_local_port 8456 * Local port number. 8457 * For Ingress: excludes CPU port and Router port 8458 * For Egress: excludes IP Router 8459 * Access: Index 8460 */ 8461 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 8462 8463 /* reg_sbpm_pool 8464 * The pool associated to quota counting on the local_port. 8465 * Access: Index 8466 */ 8467 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 8468 8469 /* reg_sbpm_dir 8470 * Direction. 8471 * Access: Index 8472 */ 8473 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 8474 8475 /* reg_sbpm_buff_occupancy 8476 * Current buffer occupancy in cells. 8477 * Access: RO 8478 */ 8479 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 8480 8481 /* reg_sbpm_clr 8482 * Clear Max Buffer Occupancy 8483 * When this bit is set, max_buff_occupancy field is cleared (and a 8484 * new max value is tracked from the time the clear was performed). 8485 * Access: OP 8486 */ 8487 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 8488 8489 /* reg_sbpm_max_buff_occupancy 8490 * Maximum value of buffer occupancy in cells monitored. Cleared by 8491 * writing to the clr field. 8492 * Access: RO 8493 */ 8494 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 8495 8496 /* reg_sbpm_min_buff 8497 * Minimum buffer size for the limiter, in cells. 8498 * Access: RW 8499 */ 8500 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 8501 8502 /* reg_sbpm_max_buff 8503 * When the pool associated to the port-pg/tclass is configured to 8504 * static, Maximum buffer size for the limiter configured in cells. 8505 * When the pool associated to the port-pg/tclass is configured to 8506 * dynamic, the max_buff holds the "alpha" parameter, supporting 8507 * the following values: 8508 * 0: 0 8509 * i: (1/128)*2^(i-1), for i=1..14 8510 * 0xFF: Infinity 8511 * Access: RW 8512 */ 8513 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 8514 8515 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 8516 enum mlxsw_reg_sbxx_dir dir, bool clr, 8517 u32 min_buff, u32 max_buff) 8518 { 8519 MLXSW_REG_ZERO(sbpm, payload); 8520 mlxsw_reg_sbpm_local_port_set(payload, local_port); 8521 mlxsw_reg_sbpm_pool_set(payload, pool); 8522 mlxsw_reg_sbpm_dir_set(payload, dir); 8523 mlxsw_reg_sbpm_clr_set(payload, clr); 8524 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 8525 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 8526 } 8527 8528 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 8529 u32 *p_max_buff_occupancy) 8530 { 8531 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 8532 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 8533 } 8534 8535 /* SBMM - Shared Buffer Multicast Management Register 8536 * -------------------------------------------------- 8537 * The SBMM register configures and retrieves the shared buffer allocation 8538 * and configuration for MC packets according to Switch-Priority, including 8539 * the binding to pool and definition of the associated quota. 8540 */ 8541 #define MLXSW_REG_SBMM_ID 0xB004 8542 #define MLXSW_REG_SBMM_LEN 0x28 8543 8544 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 8545 8546 /* reg_sbmm_prio 8547 * Switch Priority. 8548 * Access: Index 8549 */ 8550 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 8551 8552 /* reg_sbmm_min_buff 8553 * Minimum buffer size for the limiter, in cells. 8554 * Access: RW 8555 */ 8556 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 8557 8558 /* reg_sbmm_max_buff 8559 * When the pool associated to the port-pg/tclass is configured to 8560 * static, Maximum buffer size for the limiter configured in cells. 8561 * When the pool associated to the port-pg/tclass is configured to 8562 * dynamic, the max_buff holds the "alpha" parameter, supporting 8563 * the following values: 8564 * 0: 0 8565 * i: (1/128)*2^(i-1), for i=1..14 8566 * 0xFF: Infinity 8567 * Access: RW 8568 */ 8569 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 8570 8571 /* reg_sbmm_pool 8572 * Association of the port-priority to a pool. 8573 * Access: RW 8574 */ 8575 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 8576 8577 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 8578 u32 max_buff, u8 pool) 8579 { 8580 MLXSW_REG_ZERO(sbmm, payload); 8581 mlxsw_reg_sbmm_prio_set(payload, prio); 8582 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 8583 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 8584 mlxsw_reg_sbmm_pool_set(payload, pool); 8585 } 8586 8587 /* SBSR - Shared Buffer Status Register 8588 * ------------------------------------ 8589 * The SBSR register retrieves the shared buffer occupancy according to 8590 * Port-Pool. Note that this register enables reading a large amount of data. 8591 * It is the user's responsibility to limit the amount of data to ensure the 8592 * response can match the maximum transfer unit. In case the response exceeds 8593 * the maximum transport unit, it will be truncated with no special notice. 8594 */ 8595 #define MLXSW_REG_SBSR_ID 0xB005 8596 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 8597 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 8598 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 8599 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 8600 MLXSW_REG_SBSR_REC_LEN * \ 8601 MLXSW_REG_SBSR_REC_MAX_COUNT) 8602 8603 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 8604 8605 /* reg_sbsr_clr 8606 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 8607 * field is cleared (and a new max value is tracked from the time the clear 8608 * was performed). 8609 * Access: OP 8610 */ 8611 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 8612 8613 /* reg_sbsr_ingress_port_mask 8614 * Bit vector for all ingress network ports. 8615 * Indicates which of the ports (for which the relevant bit is set) 8616 * are affected by the set operation. Configuration of any other port 8617 * does not change. 8618 * Access: Index 8619 */ 8620 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 8621 8622 /* reg_sbsr_pg_buff_mask 8623 * Bit vector for all switch priority groups. 8624 * Indicates which of the priorities (for which the relevant bit is set) 8625 * are affected by the set operation. Configuration of any other priority 8626 * does not change. 8627 * Range is 0..cap_max_pg_buffers - 1 8628 * Access: Index 8629 */ 8630 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 8631 8632 /* reg_sbsr_egress_port_mask 8633 * Bit vector for all egress network ports. 8634 * Indicates which of the ports (for which the relevant bit is set) 8635 * are affected by the set operation. Configuration of any other port 8636 * does not change. 8637 * Access: Index 8638 */ 8639 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 8640 8641 /* reg_sbsr_tclass_mask 8642 * Bit vector for all traffic classes. 8643 * Indicates which of the traffic classes (for which the relevant bit is 8644 * set) are affected by the set operation. Configuration of any other 8645 * traffic class does not change. 8646 * Range is 0..cap_max_tclass - 1 8647 * Access: Index 8648 */ 8649 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 8650 8651 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 8652 { 8653 MLXSW_REG_ZERO(sbsr, payload); 8654 mlxsw_reg_sbsr_clr_set(payload, clr); 8655 } 8656 8657 /* reg_sbsr_rec_buff_occupancy 8658 * Current buffer occupancy in cells. 8659 * Access: RO 8660 */ 8661 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 8662 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 8663 8664 /* reg_sbsr_rec_max_buff_occupancy 8665 * Maximum value of buffer occupancy in cells monitored. Cleared by 8666 * writing to the clr field. 8667 * Access: RO 8668 */ 8669 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 8670 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 8671 8672 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 8673 u32 *p_buff_occupancy, 8674 u32 *p_max_buff_occupancy) 8675 { 8676 *p_buff_occupancy = 8677 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 8678 *p_max_buff_occupancy = 8679 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 8680 } 8681 8682 /* SBIB - Shared Buffer Internal Buffer Register 8683 * --------------------------------------------- 8684 * The SBIB register configures per port buffers for internal use. The internal 8685 * buffers consume memory on the port buffers (note that the port buffers are 8686 * used also by PBMC). 8687 * 8688 * For Spectrum this is used for egress mirroring. 8689 */ 8690 #define MLXSW_REG_SBIB_ID 0xB006 8691 #define MLXSW_REG_SBIB_LEN 0x10 8692 8693 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 8694 8695 /* reg_sbib_local_port 8696 * Local port number 8697 * Not supported for CPU port and router port 8698 * Access: Index 8699 */ 8700 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 8701 8702 /* reg_sbib_buff_size 8703 * Units represented in cells 8704 * Allowed range is 0 to (cap_max_headroom_size - 1) 8705 * Default is 0 8706 * Access: RW 8707 */ 8708 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 8709 8710 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 8711 u32 buff_size) 8712 { 8713 MLXSW_REG_ZERO(sbib, payload); 8714 mlxsw_reg_sbib_local_port_set(payload, local_port); 8715 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 8716 } 8717 8718 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 8719 MLXSW_REG(sgcr), 8720 MLXSW_REG(spad), 8721 MLXSW_REG(smid), 8722 MLXSW_REG(sspr), 8723 MLXSW_REG(sfdat), 8724 MLXSW_REG(sfd), 8725 MLXSW_REG(sfn), 8726 MLXSW_REG(spms), 8727 MLXSW_REG(spvid), 8728 MLXSW_REG(spvm), 8729 MLXSW_REG(spaft), 8730 MLXSW_REG(sfgc), 8731 MLXSW_REG(sftr), 8732 MLXSW_REG(sfdf), 8733 MLXSW_REG(sldr), 8734 MLXSW_REG(slcr), 8735 MLXSW_REG(slcor), 8736 MLXSW_REG(spmlr), 8737 MLXSW_REG(svfa), 8738 MLXSW_REG(svpe), 8739 MLXSW_REG(sfmr), 8740 MLXSW_REG(spvmlr), 8741 MLXSW_REG(cwtp), 8742 MLXSW_REG(cwtpm), 8743 MLXSW_REG(pgcr), 8744 MLXSW_REG(ppbt), 8745 MLXSW_REG(pacl), 8746 MLXSW_REG(pagt), 8747 MLXSW_REG(ptar), 8748 MLXSW_REG(ppbs), 8749 MLXSW_REG(prcr), 8750 MLXSW_REG(pefa), 8751 MLXSW_REG(ptce2), 8752 MLXSW_REG(perpt), 8753 MLXSW_REG(perar), 8754 MLXSW_REG(ptce3), 8755 MLXSW_REG(percr), 8756 MLXSW_REG(pererp), 8757 MLXSW_REG(iedr), 8758 MLXSW_REG(qpts), 8759 MLXSW_REG(qpcr), 8760 MLXSW_REG(qtct), 8761 MLXSW_REG(qeec), 8762 MLXSW_REG(qrwe), 8763 MLXSW_REG(qpdsm), 8764 MLXSW_REG(qpdpm), 8765 MLXSW_REG(qtctm), 8766 MLXSW_REG(pmlp), 8767 MLXSW_REG(pmtu), 8768 MLXSW_REG(ptys), 8769 MLXSW_REG(ppad), 8770 MLXSW_REG(paos), 8771 MLXSW_REG(pfcc), 8772 MLXSW_REG(ppcnt), 8773 MLXSW_REG(plib), 8774 MLXSW_REG(pptb), 8775 MLXSW_REG(pbmc), 8776 MLXSW_REG(pspa), 8777 MLXSW_REG(htgt), 8778 MLXSW_REG(hpkt), 8779 MLXSW_REG(rgcr), 8780 MLXSW_REG(ritr), 8781 MLXSW_REG(rtar), 8782 MLXSW_REG(ratr), 8783 MLXSW_REG(rtdp), 8784 MLXSW_REG(rdpm), 8785 MLXSW_REG(ricnt), 8786 MLXSW_REG(rrcr), 8787 MLXSW_REG(ralta), 8788 MLXSW_REG(ralst), 8789 MLXSW_REG(raltb), 8790 MLXSW_REG(ralue), 8791 MLXSW_REG(rauht), 8792 MLXSW_REG(raleu), 8793 MLXSW_REG(rauhtd), 8794 MLXSW_REG(rigr2), 8795 MLXSW_REG(recr2), 8796 MLXSW_REG(rmft2), 8797 MLXSW_REG(mfcr), 8798 MLXSW_REG(mfsc), 8799 MLXSW_REG(mfsm), 8800 MLXSW_REG(mfsl), 8801 MLXSW_REG(mtcap), 8802 MLXSW_REG(mtmp), 8803 MLXSW_REG(mcia), 8804 MLXSW_REG(mpat), 8805 MLXSW_REG(mpar), 8806 MLXSW_REG(mrsr), 8807 MLXSW_REG(mlcr), 8808 MLXSW_REG(mpsc), 8809 MLXSW_REG(mcqi), 8810 MLXSW_REG(mcc), 8811 MLXSW_REG(mcda), 8812 MLXSW_REG(mgpc), 8813 MLXSW_REG(tigcr), 8814 MLXSW_REG(sbpr), 8815 MLXSW_REG(sbcm), 8816 MLXSW_REG(sbpm), 8817 MLXSW_REG(sbmm), 8818 MLXSW_REG(sbsr), 8819 MLXSW_REG(sbib), 8820 }; 8821 8822 static inline const char *mlxsw_reg_id_str(u16 reg_id) 8823 { 8824 const struct mlxsw_reg_info *reg_info; 8825 int i; 8826 8827 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 8828 reg_info = mlxsw_reg_infos[i]; 8829 if (reg_info->id == reg_id) 8830 return reg_info->name; 8831 } 8832 return "*UNKNOWN*"; 8833 } 8834 8835 /* PUDE - Port Up / Down Event 8836 * --------------------------- 8837 * Reports the operational state change of a port. 8838 */ 8839 #define MLXSW_REG_PUDE_LEN 0x10 8840 8841 /* reg_pude_swid 8842 * Switch partition ID with which to associate the port. 8843 * Access: Index 8844 */ 8845 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 8846 8847 /* reg_pude_local_port 8848 * Local port number. 8849 * Access: Index 8850 */ 8851 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 8852 8853 /* reg_pude_admin_status 8854 * Port administrative state (the desired state). 8855 * 1 - Up. 8856 * 2 - Down. 8857 * 3 - Up once. This means that in case of link failure, the port won't go 8858 * into polling mode, but will wait to be re-enabled by software. 8859 * 4 - Disabled by system. Can only be set by hardware. 8860 * Access: RO 8861 */ 8862 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 8863 8864 /* reg_pude_oper_status 8865 * Port operatioanl state. 8866 * 1 - Up. 8867 * 2 - Down. 8868 * 3 - Down by port failure. This means that the device will not let the 8869 * port up again until explicitly specified by software. 8870 * Access: RO 8871 */ 8872 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 8873 8874 #endif 8875