1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 0); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210 /* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217 { 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220 } 2221 2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224 { 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231 } 2232 2233 /* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238 #define MLXSW_REG_PTAR_ID 0x3006 2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247 enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256 }; 2257 2258 /* reg_ptar_op 2259 * Access: OP 2260 */ 2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263 /* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270 enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273 }; 2274 2275 /* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281 /* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291 /* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298 /* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307 /* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322 { 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330 } 2331 2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334 { 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336 } 2337 2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339 { 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341 } 2342 2343 /* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347 #define MLXSW_REG_PPBS_ID 0x300C 2348 #define MLXSW_REG_PPBS_LEN 0x14 2349 2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352 /* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359 /* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367 { 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371 } 2372 2373 /* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377 #define MLXSW_REG_PRCR_ID 0x300D 2378 #define MLXSW_REG_PRCR_LEN 0x40 2379 2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382 enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393 }; 2394 2395 /* reg_prcr_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400 /* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406 /* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412 /* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419 /* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425 /* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437 { 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447 } 2448 2449 /* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454 #define MLXSW_REG_PEFA_ID 0x300F 2455 #define MLXSW_REG_PEFA_LEN 0xB0 2456 2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459 /* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465 /* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474 /* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484 /* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493 { 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500 } 2501 2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503 { 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505 } 2506 2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513 #define MLXSW_REG_PEMRBT_ID 0x3014 2514 #define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518 enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521 }; 2522 2523 /* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528 /* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535 static inline void 2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538 { 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542 } 2543 2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551 #define MLXSW_REG_PTCE2_ID 0x3017 2552 #define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556 /* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562 /* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569 enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585 }; 2586 2587 /* reg_ptce2_op 2588 * Access: OP 2589 */ 2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592 /* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597 /* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606 /* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615 /* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631 /* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642 { 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649 } 2650 2651 /* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655 #define MLXSW_REG_PERPT_ID 0x3021 2656 #define MLXSW_REG_PERPT_LEN 0x80 2657 2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660 /* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667 /* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674 enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679 }; 2680 2681 /* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686 /* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695 /* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701 /* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708 /* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715 /* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721 /* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727 /* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738 { 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743 } 2744 2745 static inline void 2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750 { 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761 } 2762 2763 /* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768 #define MLXSW_REG_PERAR_ID 0x3026 2769 #define MLXSW_REG_PERAR_LEN 0x08 2770 2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773 /* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780 static inline unsigned int 2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782 { 2783 return DIV_ROUND_UP(block_num, 4); 2784 } 2785 2786 /* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798 { 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802 } 2803 2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809 #define MLXSW_REG_PTCE3_ID 0x3027 2810 #define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814 /* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820 enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831 }; 2832 2833 /* reg_ptce3_op 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838 /* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846 /* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853 /* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861 /* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867 /* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874 /* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885 /* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892 /* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904 /* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912 /* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925 /* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935 /* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950 { 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964 } 2965 2966 /* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971 #define MLXSW_REG_PERCR_ID 0x302A 2972 #define MLXSW_REG_PERCR_LEN 0x80 2973 2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976 /* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983 /* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989 /* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995 /* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004 /* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013 { 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019 } 3020 3021 /* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026 #define MLXSW_REG_PERERP_ID 0x302B 3027 #define MLXSW_REG_PERERP_LEN 0x1C 3028 3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031 /* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038 /* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044 /* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050 /* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057 /* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066 /* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075 /* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086 { 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091 } 3092 3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097 { 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105 } 3106 3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111 #define MLXSW_REG_PEABFE_ID 0x3022 3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121 /* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128 /* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 /* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156 static inline void mlxsw_reg_peabfe_pack(char *payload) 3157 { 3158 MLXSW_REG_ZERO(peabfe, payload); 3159 } 3160 3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163 { 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171 } 3172 3173 /* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179 #define MLXSW_REG_IEDR_ID 0x3804 3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189 /* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195 /* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202 /* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209 /* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216 static inline void mlxsw_reg_iedr_pack(char *payload) 3217 { 3218 MLXSW_REG_ZERO(iedr, payload); 3219 } 3220 3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224 { 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232 } 3233 3234 /* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239 #define MLXSW_REG_QPTS_ID 0x4002 3240 #define MLXSW_REG_QPTS_LEN 0x8 3241 3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244 /* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252 enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255 }; 3256 3257 /* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265 { 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270 } 3271 3272 /* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277 #define MLXSW_REG_QPCR_ID 0x4004 3278 #define MLXSW_REG_QPCR_LEN 0x28 3279 3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282 enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285 }; 3286 3287 /* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293 /* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299 /* reg_qpcr_clear_counter 3300 * Clear counters. 3301 * Access: OP 3302 */ 3303 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3304 3305 /* reg_qpcr_color_aware 3306 * Is the policer aware of colors. 3307 * Must be 0 (unaware) for cpu port. 3308 * Access: RW for unbounded policer. RO for bounded policer. 3309 */ 3310 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3311 3312 /* reg_qpcr_bytes 3313 * Is policer limit is for bytes per sec or packets per sec. 3314 * 0 - packets 3315 * 1 - bytes 3316 * Access: RW for unbounded policer. RO for bounded policer. 3317 */ 3318 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3319 3320 enum mlxsw_reg_qpcr_ir_units { 3321 MLXSW_REG_QPCR_IR_UNITS_M, 3322 MLXSW_REG_QPCR_IR_UNITS_K, 3323 }; 3324 3325 /* reg_qpcr_ir_units 3326 * Policer's units for cir and eir fields (for bytes limits only) 3327 * 1 - 10^3 3328 * 0 - 10^6 3329 * Access: OP 3330 */ 3331 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3332 3333 enum mlxsw_reg_qpcr_rate_type { 3334 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3335 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3336 }; 3337 3338 /* reg_qpcr_rate_type 3339 * Policer can have one limit (single rate) or 2 limits with specific operation 3340 * for packets that exceed the lower rate but not the upper one. 3341 * (For cpu port must be single rate) 3342 * Access: RW for unbounded policer. RO for bounded policer. 3343 */ 3344 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3345 3346 /* reg_qpc_cbs 3347 * Policer's committed burst size. 3348 * The policer is working with time slices of 50 nano sec. By default every 3349 * slice is granted the proportionate share of the committed rate. If we want to 3350 * allow a slice to exceed that share (while still keeping the rate per sec) we 3351 * can allow burst. The burst size is between the default proportionate share 3352 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3353 * committed rate will result in exceeding the rate). The burst size must be a 3354 * log of 2 and will be determined by 2^cbs. 3355 * Access: RW 3356 */ 3357 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3358 3359 /* reg_qpcr_cir 3360 * Policer's committed rate. 3361 * The rate used for sungle rate, the lower rate for double rate. 3362 * For bytes limits, the rate will be this value * the unit from ir_units. 3363 * (Resolution error is up to 1%). 3364 * Access: RW 3365 */ 3366 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3367 3368 /* reg_qpcr_eir 3369 * Policer's exceed rate. 3370 * The higher rate for double rate, reserved for single rate. 3371 * Lower rate for double rate policer. 3372 * For bytes limits, the rate will be this value * the unit from ir_units. 3373 * (Resolution error is up to 1%). 3374 * Access: RW 3375 */ 3376 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3377 3378 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3379 3380 /* reg_qpcr_exceed_action. 3381 * What to do with packets between the 2 limits for double rate. 3382 * Access: RW for unbounded policer. RO for bounded policer. 3383 */ 3384 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3385 3386 enum mlxsw_reg_qpcr_action { 3387 /* Discard */ 3388 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3389 /* Forward and set color to red. 3390 * If the packet is intended to cpu port, it will be dropped. 3391 */ 3392 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3393 }; 3394 3395 /* reg_qpcr_violate_action 3396 * What to do with packets that cross the cir limit (for single rate) or the eir 3397 * limit (for double rate). 3398 * Access: RW for unbounded policer. RO for bounded policer. 3399 */ 3400 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3401 3402 /* reg_qpcr_violate_count 3403 * Counts the number of times violate_action happened on this PID. 3404 * Access: RW 3405 */ 3406 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3407 3408 /* Packets */ 3409 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3410 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3411 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3412 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3413 3414 /* Bandwidth */ 3415 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3416 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3417 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3418 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3419 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3420 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3421 3422 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3423 enum mlxsw_reg_qpcr_ir_units ir_units, 3424 bool bytes, u32 cir, u16 cbs) 3425 { 3426 MLXSW_REG_ZERO(qpcr, payload); 3427 mlxsw_reg_qpcr_pid_set(payload, pid); 3428 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3429 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3430 mlxsw_reg_qpcr_violate_action_set(payload, 3431 MLXSW_REG_QPCR_ACTION_DISCARD); 3432 mlxsw_reg_qpcr_cir_set(payload, cir); 3433 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3434 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3435 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3436 } 3437 3438 /* QTCT - QoS Switch Traffic Class Table 3439 * ------------------------------------- 3440 * Configures the mapping between the packet switch priority and the 3441 * traffic class on the transmit port. 3442 */ 3443 #define MLXSW_REG_QTCT_ID 0x400A 3444 #define MLXSW_REG_QTCT_LEN 0x08 3445 3446 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3447 3448 /* reg_qtct_local_port 3449 * Local port number. 3450 * Access: Index 3451 * 3452 * Note: CPU port is not supported. 3453 */ 3454 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3455 3456 /* reg_qtct_sub_port 3457 * Virtual port within the physical port. 3458 * Should be set to 0 when virtual ports are not enabled on the port. 3459 * Access: Index 3460 */ 3461 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3462 3463 /* reg_qtct_switch_prio 3464 * Switch priority. 3465 * Access: Index 3466 */ 3467 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3468 3469 /* reg_qtct_tclass 3470 * Traffic class. 3471 * Default values: 3472 * switch_prio 0 : tclass 1 3473 * switch_prio 1 : tclass 0 3474 * switch_prio i : tclass i, for i > 1 3475 * Access: RW 3476 */ 3477 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3478 3479 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3480 u8 switch_prio, u8 tclass) 3481 { 3482 MLXSW_REG_ZERO(qtct, payload); 3483 mlxsw_reg_qtct_local_port_set(payload, local_port); 3484 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3485 mlxsw_reg_qtct_tclass_set(payload, tclass); 3486 } 3487 3488 /* QEEC - QoS ETS Element Configuration Register 3489 * --------------------------------------------- 3490 * Configures the ETS elements. 3491 */ 3492 #define MLXSW_REG_QEEC_ID 0x400D 3493 #define MLXSW_REG_QEEC_LEN 0x20 3494 3495 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3496 3497 /* reg_qeec_local_port 3498 * Local port number. 3499 * Access: Index 3500 * 3501 * Note: CPU port is supported. 3502 */ 3503 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3504 3505 enum mlxsw_reg_qeec_hr { 3506 MLXSW_REG_QEEC_HR_PORT, 3507 MLXSW_REG_QEEC_HR_GROUP, 3508 MLXSW_REG_QEEC_HR_SUBGROUP, 3509 MLXSW_REG_QEEC_HR_TC, 3510 }; 3511 3512 /* reg_qeec_element_hierarchy 3513 * 0 - Port 3514 * 1 - Group 3515 * 2 - Subgroup 3516 * 3 - Traffic Class 3517 * Access: Index 3518 */ 3519 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3520 3521 /* reg_qeec_element_index 3522 * The index of the element in the hierarchy. 3523 * Access: Index 3524 */ 3525 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3526 3527 /* reg_qeec_next_element_index 3528 * The index of the next (lower) element in the hierarchy. 3529 * Access: RW 3530 * 3531 * Note: Reserved for element_hierarchy 0. 3532 */ 3533 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3534 3535 /* reg_qeec_mise 3536 * Min shaper configuration enable. Enables configuration of the min 3537 * shaper on this ETS element 3538 * 0 - Disable 3539 * 1 - Enable 3540 * Access: RW 3541 */ 3542 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3543 3544 /* reg_qeec_ptps 3545 * PTP shaper 3546 * 0: regular shaper mode 3547 * 1: PTP oriented shaper 3548 * Allowed only for hierarchy 0 3549 * Not supported for CPU port 3550 * Note that ptps mode may affect the shaper rates of all hierarchies 3551 * Supported only on Spectrum-1 3552 * Access: RW 3553 */ 3554 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3555 3556 enum { 3557 MLXSW_REG_QEEC_BYTES_MODE, 3558 MLXSW_REG_QEEC_PACKETS_MODE, 3559 }; 3560 3561 /* reg_qeec_pb 3562 * Packets or bytes mode. 3563 * 0 - Bytes mode 3564 * 1 - Packets mode 3565 * Access: RW 3566 * 3567 * Note: Used for max shaper configuration. For Spectrum, packets mode 3568 * is supported only for traffic classes of CPU port. 3569 */ 3570 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3571 3572 /* The smallest permitted min shaper rate. */ 3573 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3574 3575 /* reg_qeec_min_shaper_rate 3576 * Min shaper information rate. 3577 * For CPU port, can only be configured for port hierarchy. 3578 * When in bytes mode, value is specified in units of 1000bps. 3579 * Access: RW 3580 */ 3581 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3582 3583 /* reg_qeec_mase 3584 * Max shaper configuration enable. Enables configuration of the max 3585 * shaper on this ETS element. 3586 * 0 - Disable 3587 * 1 - Enable 3588 * Access: RW 3589 */ 3590 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3591 3592 /* The largest max shaper value possible to disable the shaper. */ 3593 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3594 3595 /* reg_qeec_max_shaper_rate 3596 * Max shaper information rate. 3597 * For CPU port, can only be configured for port hierarchy. 3598 * When in bytes mode, value is specified in units of 1000bps. 3599 * Access: RW 3600 */ 3601 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3602 3603 /* reg_qeec_de 3604 * DWRR configuration enable. Enables configuration of the dwrr and 3605 * dwrr_weight. 3606 * 0 - Disable 3607 * 1 - Enable 3608 * Access: RW 3609 */ 3610 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3611 3612 /* reg_qeec_dwrr 3613 * Transmission selection algorithm to use on the link going down from 3614 * the ETS element. 3615 * 0 - Strict priority 3616 * 1 - DWRR 3617 * Access: RW 3618 */ 3619 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3620 3621 /* reg_qeec_dwrr_weight 3622 * DWRR weight on the link going down from the ETS element. The 3623 * percentage of bandwidth guaranteed to an ETS element within 3624 * its hierarchy. The sum of all weights across all ETS elements 3625 * within one hierarchy should be equal to 100. Reserved when 3626 * transmission selection algorithm is strict priority. 3627 * Access: RW 3628 */ 3629 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3630 3631 /* reg_qeec_max_shaper_bs 3632 * Max shaper burst size 3633 * Burst size is 2^max_shaper_bs * 512 bits 3634 * For Spectrum-1: Range is: 5..25 3635 * For Spectrum-2: Range is: 11..25 3636 * Reserved when ptps = 1 3637 * Access: RW 3638 */ 3639 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3640 3641 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3642 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3643 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3644 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 5 3645 3646 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3647 enum mlxsw_reg_qeec_hr hr, u8 index, 3648 u8 next_index) 3649 { 3650 MLXSW_REG_ZERO(qeec, payload); 3651 mlxsw_reg_qeec_local_port_set(payload, local_port); 3652 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3653 mlxsw_reg_qeec_element_index_set(payload, index); 3654 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3655 } 3656 3657 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3658 bool ptps) 3659 { 3660 MLXSW_REG_ZERO(qeec, payload); 3661 mlxsw_reg_qeec_local_port_set(payload, local_port); 3662 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3663 mlxsw_reg_qeec_ptps_set(payload, ptps); 3664 } 3665 3666 /* QRWE - QoS ReWrite Enable 3667 * ------------------------- 3668 * This register configures the rewrite enable per receive port. 3669 */ 3670 #define MLXSW_REG_QRWE_ID 0x400F 3671 #define MLXSW_REG_QRWE_LEN 0x08 3672 3673 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3674 3675 /* reg_qrwe_local_port 3676 * Local port number. 3677 * Access: Index 3678 * 3679 * Note: CPU port is supported. No support for router port. 3680 */ 3681 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3682 3683 /* reg_qrwe_dscp 3684 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3685 * Access: RW 3686 */ 3687 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3688 3689 /* reg_qrwe_pcp 3690 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3691 * Access: RW 3692 */ 3693 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3694 3695 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3696 bool rewrite_pcp, bool rewrite_dscp) 3697 { 3698 MLXSW_REG_ZERO(qrwe, payload); 3699 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3700 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3701 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3702 } 3703 3704 /* QPDSM - QoS Priority to DSCP Mapping 3705 * ------------------------------------ 3706 * QoS Priority to DSCP Mapping Register 3707 */ 3708 #define MLXSW_REG_QPDSM_ID 0x4011 3709 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3710 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3711 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3712 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3713 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3714 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3715 3716 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3717 3718 /* reg_qpdsm_local_port 3719 * Local Port. Supported for data packets from CPU port. 3720 * Access: Index 3721 */ 3722 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3723 3724 /* reg_qpdsm_prio_entry_color0_e 3725 * Enable update of the entry for color 0 and a given port. 3726 * Access: WO 3727 */ 3728 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3729 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3730 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3731 3732 /* reg_qpdsm_prio_entry_color0_dscp 3733 * DSCP field in the outer label of the packet for color 0 and a given port. 3734 * Reserved when e=0. 3735 * Access: RW 3736 */ 3737 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3738 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3739 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3740 3741 /* reg_qpdsm_prio_entry_color1_e 3742 * Enable update of the entry for color 1 and a given port. 3743 * Access: WO 3744 */ 3745 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3746 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3747 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3748 3749 /* reg_qpdsm_prio_entry_color1_dscp 3750 * DSCP field in the outer label of the packet for color 1 and a given port. 3751 * Reserved when e=0. 3752 * Access: RW 3753 */ 3754 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3755 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3756 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3757 3758 /* reg_qpdsm_prio_entry_color2_e 3759 * Enable update of the entry for color 2 and a given port. 3760 * Access: WO 3761 */ 3762 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3763 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3764 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3765 3766 /* reg_qpdsm_prio_entry_color2_dscp 3767 * DSCP field in the outer label of the packet for color 2 and a given port. 3768 * Reserved when e=0. 3769 * Access: RW 3770 */ 3771 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3772 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3773 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3774 3775 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3776 { 3777 MLXSW_REG_ZERO(qpdsm, payload); 3778 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3779 } 3780 3781 static inline void 3782 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3783 { 3784 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3785 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3786 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3787 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3788 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3789 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3790 } 3791 3792 /* QPDP - QoS Port DSCP to Priority Mapping Register 3793 * ------------------------------------------------- 3794 * This register controls the port default Switch Priority and Color. The 3795 * default Switch Priority and Color are used for frames where the trust state 3796 * uses default values. All member ports of a LAG should be configured with the 3797 * same default values. 3798 */ 3799 #define MLXSW_REG_QPDP_ID 0x4007 3800 #define MLXSW_REG_QPDP_LEN 0x8 3801 3802 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 3803 3804 /* reg_qpdp_local_port 3805 * Local Port. Supported for data packets from CPU port. 3806 * Access: Index 3807 */ 3808 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 3809 3810 /* reg_qpdp_switch_prio 3811 * Default port Switch Priority (default 0) 3812 * Access: RW 3813 */ 3814 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 3815 3816 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 3817 u8 switch_prio) 3818 { 3819 MLXSW_REG_ZERO(qpdp, payload); 3820 mlxsw_reg_qpdp_local_port_set(payload, local_port); 3821 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 3822 } 3823 3824 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3825 * -------------------------------------------------- 3826 * This register controls the mapping from DSCP field to 3827 * Switch Priority for IP packets. 3828 */ 3829 #define MLXSW_REG_QPDPM_ID 0x4013 3830 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3831 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3832 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3833 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3834 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3835 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3836 3837 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3838 3839 /* reg_qpdpm_local_port 3840 * Local Port. Supported for data packets from CPU port. 3841 * Access: Index 3842 */ 3843 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3844 3845 /* reg_qpdpm_dscp_e 3846 * Enable update of the specific entry. When cleared, the switch_prio and color 3847 * fields are ignored and the previous switch_prio and color values are 3848 * preserved. 3849 * Access: WO 3850 */ 3851 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3852 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3853 3854 /* reg_qpdpm_dscp_prio 3855 * The new Switch Priority value for the relevant DSCP value. 3856 * Access: RW 3857 */ 3858 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3859 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3860 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3861 3862 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3863 { 3864 MLXSW_REG_ZERO(qpdpm, payload); 3865 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3866 } 3867 3868 static inline void 3869 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3870 { 3871 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3872 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3873 } 3874 3875 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3876 * ------------------------------------------------------------------ 3877 * This register configures if the Switch Priority to Traffic Class mapping is 3878 * based on Multicast packet indication. If so, then multicast packets will get 3879 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3880 * QTCT. 3881 * By default, Switch Priority to Traffic Class mapping is not based on 3882 * Multicast packet indication. 3883 */ 3884 #define MLXSW_REG_QTCTM_ID 0x401A 3885 #define MLXSW_REG_QTCTM_LEN 0x08 3886 3887 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3888 3889 /* reg_qtctm_local_port 3890 * Local port number. 3891 * No support for CPU port. 3892 * Access: Index 3893 */ 3894 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3895 3896 /* reg_qtctm_mc 3897 * Multicast Mode 3898 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3899 * indication (default is 0, not based on Multicast packet indication). 3900 */ 3901 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3902 3903 static inline void 3904 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3905 { 3906 MLXSW_REG_ZERO(qtctm, payload); 3907 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3908 mlxsw_reg_qtctm_mc_set(payload, mc); 3909 } 3910 3911 /* QPSC - QoS PTP Shaper Configuration Register 3912 * -------------------------------------------- 3913 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 3914 * Supported only on Spectrum-1. 3915 */ 3916 #define MLXSW_REG_QPSC_ID 0x401B 3917 #define MLXSW_REG_QPSC_LEN 0x28 3918 3919 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 3920 3921 enum mlxsw_reg_qpsc_port_speed { 3922 MLXSW_REG_QPSC_PORT_SPEED_100M, 3923 MLXSW_REG_QPSC_PORT_SPEED_1G, 3924 MLXSW_REG_QPSC_PORT_SPEED_10G, 3925 MLXSW_REG_QPSC_PORT_SPEED_25G, 3926 }; 3927 3928 /* reg_qpsc_port_speed 3929 * Port speed. 3930 * Access: Index 3931 */ 3932 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 3933 3934 /* reg_qpsc_shaper_time_exp 3935 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3936 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3937 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3938 * Access: RW 3939 */ 3940 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 3941 3942 /* reg_qpsc_shaper_time_mantissa 3943 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3944 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3945 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3946 * Access: RW 3947 */ 3948 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 3949 3950 /* reg_qpsc_shaper_inc 3951 * Number of tokens added to shaper on each update. 3952 * Units of 8B. 3953 * Access: RW 3954 */ 3955 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 3956 3957 /* reg_qpsc_shaper_bs 3958 * Max shaper Burst size. 3959 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 3960 * Range is: 5..25 (from 2KB..2GB) 3961 * Access: RW 3962 */ 3963 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 3964 3965 /* reg_qpsc_ptsc_we 3966 * Write enable to port_to_shaper_credits. 3967 * Access: WO 3968 */ 3969 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 3970 3971 /* reg_qpsc_port_to_shaper_credits 3972 * For split ports: range 1..57 3973 * For non-split ports: range 1..112 3974 * Written only when ptsc_we is set. 3975 * Access: RW 3976 */ 3977 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 3978 3979 /* reg_qpsc_ing_timestamp_inc 3980 * Ingress timestamp increment. 3981 * 2's complement. 3982 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 3983 * value for all ports. 3984 * Same units as used by MTPPTR. 3985 * Access: RW 3986 */ 3987 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 3988 3989 /* reg_qpsc_egr_timestamp_inc 3990 * Egress timestamp increment. 3991 * 2's complement. 3992 * The timestamp of MTPPTR at egress will be incremented by this value. Global 3993 * value for all ports. 3994 * Same units as used by MTPPTR. 3995 * Access: RW 3996 */ 3997 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 3998 3999 static inline void 4000 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4001 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4002 u8 shaper_bs, u8 port_to_shaper_credits, 4003 int ing_timestamp_inc, int egr_timestamp_inc) 4004 { 4005 MLXSW_REG_ZERO(qpsc, payload); 4006 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4007 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4008 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4009 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4010 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4011 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4012 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4013 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4014 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4015 } 4016 4017 /* PMLP - Ports Module to Local Port Register 4018 * ------------------------------------------ 4019 * Configures the assignment of modules to local ports. 4020 */ 4021 #define MLXSW_REG_PMLP_ID 0x5002 4022 #define MLXSW_REG_PMLP_LEN 0x40 4023 4024 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4025 4026 /* reg_pmlp_rxtx 4027 * 0 - Tx value is used for both Tx and Rx. 4028 * 1 - Rx value is taken from a separte field. 4029 * Access: RW 4030 */ 4031 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4032 4033 /* reg_pmlp_local_port 4034 * Local port number. 4035 * Access: Index 4036 */ 4037 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4038 4039 /* reg_pmlp_width 4040 * 0 - Unmap local port. 4041 * 1 - Lane 0 is used. 4042 * 2 - Lanes 0 and 1 are used. 4043 * 4 - Lanes 0, 1, 2 and 3 are used. 4044 * 8 - Lanes 0-7 are used. 4045 * Access: RW 4046 */ 4047 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4048 4049 /* reg_pmlp_module 4050 * Module number. 4051 * Access: RW 4052 */ 4053 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4054 4055 /* reg_pmlp_tx_lane 4056 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4057 * Access: RW 4058 */ 4059 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4060 4061 /* reg_pmlp_rx_lane 4062 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4063 * equal to Tx lane. 4064 * Access: RW 4065 */ 4066 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4067 4068 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4069 { 4070 MLXSW_REG_ZERO(pmlp, payload); 4071 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4072 } 4073 4074 /* PMTU - Port MTU Register 4075 * ------------------------ 4076 * Configures and reports the port MTU. 4077 */ 4078 #define MLXSW_REG_PMTU_ID 0x5003 4079 #define MLXSW_REG_PMTU_LEN 0x10 4080 4081 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4082 4083 /* reg_pmtu_local_port 4084 * Local port number. 4085 * Access: Index 4086 */ 4087 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4088 4089 /* reg_pmtu_max_mtu 4090 * Maximum MTU. 4091 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4092 * reported, otherwise the minimum between the max_mtu of the different 4093 * types is reported. 4094 * Access: RO 4095 */ 4096 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4097 4098 /* reg_pmtu_admin_mtu 4099 * MTU value to set port to. Must be smaller or equal to max_mtu. 4100 * Note: If port type is Infiniband, then port must be disabled, when its 4101 * MTU is set. 4102 * Access: RW 4103 */ 4104 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4105 4106 /* reg_pmtu_oper_mtu 4107 * The actual MTU configured on the port. Packets exceeding this size 4108 * will be dropped. 4109 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4110 * oper_mtu might be smaller than admin_mtu. 4111 * Access: RO 4112 */ 4113 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4114 4115 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4116 u16 new_mtu) 4117 { 4118 MLXSW_REG_ZERO(pmtu, payload); 4119 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4120 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4121 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4122 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4123 } 4124 4125 /* PTYS - Port Type and Speed Register 4126 * ----------------------------------- 4127 * Configures and reports the port speed type. 4128 * 4129 * Note: When set while the link is up, the changes will not take effect 4130 * until the port transitions from down to up state. 4131 */ 4132 #define MLXSW_REG_PTYS_ID 0x5004 4133 #define MLXSW_REG_PTYS_LEN 0x40 4134 4135 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4136 4137 /* an_disable_admin 4138 * Auto negotiation disable administrative configuration 4139 * 0 - Device doesn't support AN disable. 4140 * 1 - Device supports AN disable. 4141 * Access: RW 4142 */ 4143 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4144 4145 /* reg_ptys_local_port 4146 * Local port number. 4147 * Access: Index 4148 */ 4149 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4150 4151 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4152 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4153 4154 /* reg_ptys_proto_mask 4155 * Protocol mask. Indicates which protocol is used. 4156 * 0 - Infiniband. 4157 * 1 - Fibre Channel. 4158 * 2 - Ethernet. 4159 * Access: Index 4160 */ 4161 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4162 4163 enum { 4164 MLXSW_REG_PTYS_AN_STATUS_NA, 4165 MLXSW_REG_PTYS_AN_STATUS_OK, 4166 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4167 }; 4168 4169 /* reg_ptys_an_status 4170 * Autonegotiation status. 4171 * Access: RO 4172 */ 4173 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4174 4175 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4176 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4177 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) 4178 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4179 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4180 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4181 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4182 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4183 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4184 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4185 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4186 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4187 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4188 4189 /* reg_ptys_ext_eth_proto_cap 4190 * Extended Ethernet port supported speeds and protocols. 4191 * Access: RO 4192 */ 4193 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4194 4195 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4196 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4197 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4198 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4199 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4200 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 4201 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4202 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4203 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4204 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4205 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4206 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4207 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4208 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4209 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4210 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4211 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4212 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4213 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4214 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 4215 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 4216 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 4217 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4218 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4219 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4220 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4221 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4222 4223 /* reg_ptys_eth_proto_cap 4224 * Ethernet port supported speeds and protocols. 4225 * Access: RO 4226 */ 4227 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4228 4229 /* reg_ptys_ib_link_width_cap 4230 * IB port supported widths. 4231 * Access: RO 4232 */ 4233 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4234 4235 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4236 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4237 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4238 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4239 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4240 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4241 4242 /* reg_ptys_ib_proto_cap 4243 * IB port supported speeds and protocols. 4244 * Access: RO 4245 */ 4246 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4247 4248 /* reg_ptys_ext_eth_proto_admin 4249 * Extended speed and protocol to set port to. 4250 * Access: RW 4251 */ 4252 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4253 4254 /* reg_ptys_eth_proto_admin 4255 * Speed and protocol to set port to. 4256 * Access: RW 4257 */ 4258 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4259 4260 /* reg_ptys_ib_link_width_admin 4261 * IB width to set port to. 4262 * Access: RW 4263 */ 4264 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4265 4266 /* reg_ptys_ib_proto_admin 4267 * IB speeds and protocols to set port to. 4268 * Access: RW 4269 */ 4270 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4271 4272 /* reg_ptys_ext_eth_proto_oper 4273 * The extended current speed and protocol configured for the port. 4274 * Access: RO 4275 */ 4276 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4277 4278 /* reg_ptys_eth_proto_oper 4279 * The current speed and protocol configured for the port. 4280 * Access: RO 4281 */ 4282 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4283 4284 /* reg_ptys_ib_link_width_oper 4285 * The current IB width to set port to. 4286 * Access: RO 4287 */ 4288 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4289 4290 /* reg_ptys_ib_proto_oper 4291 * The current IB speed and protocol. 4292 * Access: RO 4293 */ 4294 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4295 4296 enum mlxsw_reg_ptys_connector_type { 4297 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4298 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4299 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4300 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4301 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4302 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4303 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4304 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4305 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4306 }; 4307 4308 /* reg_ptys_connector_type 4309 * Connector type indication. 4310 * Access: RO 4311 */ 4312 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4313 4314 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4315 u32 proto_admin, bool autoneg) 4316 { 4317 MLXSW_REG_ZERO(ptys, payload); 4318 mlxsw_reg_ptys_local_port_set(payload, local_port); 4319 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4320 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4321 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4322 } 4323 4324 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4325 u32 proto_admin, bool autoneg) 4326 { 4327 MLXSW_REG_ZERO(ptys, payload); 4328 mlxsw_reg_ptys_local_port_set(payload, local_port); 4329 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4330 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4331 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4332 } 4333 4334 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4335 u32 *p_eth_proto_cap, 4336 u32 *p_eth_proto_admin, 4337 u32 *p_eth_proto_oper) 4338 { 4339 if (p_eth_proto_cap) 4340 *p_eth_proto_cap = 4341 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4342 if (p_eth_proto_admin) 4343 *p_eth_proto_admin = 4344 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4345 if (p_eth_proto_oper) 4346 *p_eth_proto_oper = 4347 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4348 } 4349 4350 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4351 u32 *p_eth_proto_cap, 4352 u32 *p_eth_proto_admin, 4353 u32 *p_eth_proto_oper) 4354 { 4355 if (p_eth_proto_cap) 4356 *p_eth_proto_cap = 4357 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4358 if (p_eth_proto_admin) 4359 *p_eth_proto_admin = 4360 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4361 if (p_eth_proto_oper) 4362 *p_eth_proto_oper = 4363 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4364 } 4365 4366 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4367 u16 proto_admin, u16 link_width) 4368 { 4369 MLXSW_REG_ZERO(ptys, payload); 4370 mlxsw_reg_ptys_local_port_set(payload, local_port); 4371 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4372 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4373 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4374 } 4375 4376 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4377 u16 *p_ib_link_width_cap, 4378 u16 *p_ib_proto_oper, 4379 u16 *p_ib_link_width_oper) 4380 { 4381 if (p_ib_proto_cap) 4382 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4383 if (p_ib_link_width_cap) 4384 *p_ib_link_width_cap = 4385 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4386 if (p_ib_proto_oper) 4387 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4388 if (p_ib_link_width_oper) 4389 *p_ib_link_width_oper = 4390 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4391 } 4392 4393 /* PPAD - Port Physical Address Register 4394 * ------------------------------------- 4395 * The PPAD register configures the per port physical MAC address. 4396 */ 4397 #define MLXSW_REG_PPAD_ID 0x5005 4398 #define MLXSW_REG_PPAD_LEN 0x10 4399 4400 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4401 4402 /* reg_ppad_single_base_mac 4403 * 0: base_mac, local port should be 0 and mac[7:0] is 4404 * reserved. HW will set incremental 4405 * 1: single_mac - mac of the local_port 4406 * Access: RW 4407 */ 4408 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4409 4410 /* reg_ppad_local_port 4411 * port number, if single_base_mac = 0 then local_port is reserved 4412 * Access: RW 4413 */ 4414 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4415 4416 /* reg_ppad_mac 4417 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4418 * If single_base_mac = 1 - the per port MAC address 4419 * Access: RW 4420 */ 4421 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4422 4423 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4424 u8 local_port) 4425 { 4426 MLXSW_REG_ZERO(ppad, payload); 4427 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4428 mlxsw_reg_ppad_local_port_set(payload, local_port); 4429 } 4430 4431 /* PAOS - Ports Administrative and Operational Status Register 4432 * ----------------------------------------------------------- 4433 * Configures and retrieves per port administrative and operational status. 4434 */ 4435 #define MLXSW_REG_PAOS_ID 0x5006 4436 #define MLXSW_REG_PAOS_LEN 0x10 4437 4438 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4439 4440 /* reg_paos_swid 4441 * Switch partition ID with which to associate the port. 4442 * Note: while external ports uses unique local port numbers (and thus swid is 4443 * redundant), router ports use the same local port number where swid is the 4444 * only indication for the relevant port. 4445 * Access: Index 4446 */ 4447 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4448 4449 /* reg_paos_local_port 4450 * Local port number. 4451 * Access: Index 4452 */ 4453 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4454 4455 /* reg_paos_admin_status 4456 * Port administrative state (the desired state of the port): 4457 * 1 - Up. 4458 * 2 - Down. 4459 * 3 - Up once. This means that in case of link failure, the port won't go 4460 * into polling mode, but will wait to be re-enabled by software. 4461 * 4 - Disabled by system. Can only be set by hardware. 4462 * Access: RW 4463 */ 4464 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4465 4466 /* reg_paos_oper_status 4467 * Port operational state (the current state): 4468 * 1 - Up. 4469 * 2 - Down. 4470 * 3 - Down by port failure. This means that the device will not let the 4471 * port up again until explicitly specified by software. 4472 * Access: RO 4473 */ 4474 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4475 4476 /* reg_paos_ase 4477 * Admin state update enabled. 4478 * Access: WO 4479 */ 4480 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4481 4482 /* reg_paos_ee 4483 * Event update enable. If this bit is set, event generation will be 4484 * updated based on the e field. 4485 * Access: WO 4486 */ 4487 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4488 4489 /* reg_paos_e 4490 * Event generation on operational state change: 4491 * 0 - Do not generate event. 4492 * 1 - Generate Event. 4493 * 2 - Generate Single Event. 4494 * Access: RW 4495 */ 4496 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4497 4498 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4499 enum mlxsw_port_admin_status status) 4500 { 4501 MLXSW_REG_ZERO(paos, payload); 4502 mlxsw_reg_paos_swid_set(payload, 0); 4503 mlxsw_reg_paos_local_port_set(payload, local_port); 4504 mlxsw_reg_paos_admin_status_set(payload, status); 4505 mlxsw_reg_paos_oper_status_set(payload, 0); 4506 mlxsw_reg_paos_ase_set(payload, 1); 4507 mlxsw_reg_paos_ee_set(payload, 1); 4508 mlxsw_reg_paos_e_set(payload, 1); 4509 } 4510 4511 /* PFCC - Ports Flow Control Configuration Register 4512 * ------------------------------------------------ 4513 * Configures and retrieves the per port flow control configuration. 4514 */ 4515 #define MLXSW_REG_PFCC_ID 0x5007 4516 #define MLXSW_REG_PFCC_LEN 0x20 4517 4518 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4519 4520 /* reg_pfcc_local_port 4521 * Local port number. 4522 * Access: Index 4523 */ 4524 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4525 4526 /* reg_pfcc_pnat 4527 * Port number access type. Determines the way local_port is interpreted: 4528 * 0 - Local port number. 4529 * 1 - IB / label port number. 4530 * Access: Index 4531 */ 4532 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4533 4534 /* reg_pfcc_shl_cap 4535 * Send to higher layers capabilities: 4536 * 0 - No capability of sending Pause and PFC frames to higher layers. 4537 * 1 - Device has capability of sending Pause and PFC frames to higher 4538 * layers. 4539 * Access: RO 4540 */ 4541 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4542 4543 /* reg_pfcc_shl_opr 4544 * Send to higher layers operation: 4545 * 0 - Pause and PFC frames are handled by the port (default). 4546 * 1 - Pause and PFC frames are handled by the port and also sent to 4547 * higher layers. Only valid if shl_cap = 1. 4548 * Access: RW 4549 */ 4550 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4551 4552 /* reg_pfcc_ppan 4553 * Pause policy auto negotiation. 4554 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4555 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4556 * based on the auto-negotiation resolution. 4557 * Access: RW 4558 * 4559 * Note: The auto-negotiation advertisement is set according to pptx and 4560 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4561 */ 4562 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4563 4564 /* reg_pfcc_prio_mask_tx 4565 * Bit per priority indicating if Tx flow control policy should be 4566 * updated based on bit pfctx. 4567 * Access: WO 4568 */ 4569 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4570 4571 /* reg_pfcc_prio_mask_rx 4572 * Bit per priority indicating if Rx flow control policy should be 4573 * updated based on bit pfcrx. 4574 * Access: WO 4575 */ 4576 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4577 4578 /* reg_pfcc_pptx 4579 * Admin Pause policy on Tx. 4580 * 0 - Never generate Pause frames (default). 4581 * 1 - Generate Pause frames according to Rx buffer threshold. 4582 * Access: RW 4583 */ 4584 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4585 4586 /* reg_pfcc_aptx 4587 * Active (operational) Pause policy on Tx. 4588 * 0 - Never generate Pause frames. 4589 * 1 - Generate Pause frames according to Rx buffer threshold. 4590 * Access: RO 4591 */ 4592 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4593 4594 /* reg_pfcc_pfctx 4595 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4596 * 0 - Never generate priority Pause frames on the specified priority 4597 * (default). 4598 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4599 * the specified priority. 4600 * Access: RW 4601 * 4602 * Note: pfctx and pptx must be mutually exclusive. 4603 */ 4604 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4605 4606 /* reg_pfcc_pprx 4607 * Admin Pause policy on Rx. 4608 * 0 - Ignore received Pause frames (default). 4609 * 1 - Respect received Pause frames. 4610 * Access: RW 4611 */ 4612 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4613 4614 /* reg_pfcc_aprx 4615 * Active (operational) Pause policy on Rx. 4616 * 0 - Ignore received Pause frames. 4617 * 1 - Respect received Pause frames. 4618 * Access: RO 4619 */ 4620 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4621 4622 /* reg_pfcc_pfcrx 4623 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4624 * 0 - Ignore incoming priority Pause frames on the specified priority 4625 * (default). 4626 * 1 - Respect incoming priority Pause frames on the specified priority. 4627 * Access: RW 4628 */ 4629 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4630 4631 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4632 4633 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4634 { 4635 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4636 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4637 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4638 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4639 } 4640 4641 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4642 { 4643 MLXSW_REG_ZERO(pfcc, payload); 4644 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4645 } 4646 4647 /* PPCNT - Ports Performance Counters Register 4648 * ------------------------------------------- 4649 * The PPCNT register retrieves per port performance counters. 4650 */ 4651 #define MLXSW_REG_PPCNT_ID 0x5008 4652 #define MLXSW_REG_PPCNT_LEN 0x100 4653 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4654 4655 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4656 4657 /* reg_ppcnt_swid 4658 * For HCA: must be always 0. 4659 * Switch partition ID to associate port with. 4660 * Switch partitions are numbered from 0 to 7 inclusively. 4661 * Switch partition 254 indicates stacking ports. 4662 * Switch partition 255 indicates all switch partitions. 4663 * Only valid on Set() operation with local_port=255. 4664 * Access: Index 4665 */ 4666 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4667 4668 /* reg_ppcnt_local_port 4669 * Local port number. 4670 * 255 indicates all ports on the device, and is only allowed 4671 * for Set() operation. 4672 * Access: Index 4673 */ 4674 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4675 4676 /* reg_ppcnt_pnat 4677 * Port number access type: 4678 * 0 - Local port number 4679 * 1 - IB port number 4680 * Access: Index 4681 */ 4682 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4683 4684 enum mlxsw_reg_ppcnt_grp { 4685 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4686 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4687 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4688 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4689 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4690 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4691 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4692 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4693 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4694 }; 4695 4696 /* reg_ppcnt_grp 4697 * Performance counter group. 4698 * Group 63 indicates all groups. Only valid on Set() operation with 4699 * clr bit set. 4700 * 0x0: IEEE 802.3 Counters 4701 * 0x1: RFC 2863 Counters 4702 * 0x2: RFC 2819 Counters 4703 * 0x3: RFC 3635 Counters 4704 * 0x5: Ethernet Extended Counters 4705 * 0x6: Ethernet Discard Counters 4706 * 0x8: Link Level Retransmission Counters 4707 * 0x10: Per Priority Counters 4708 * 0x11: Per Traffic Class Counters 4709 * 0x12: Physical Layer Counters 4710 * 0x13: Per Traffic Class Congestion Counters 4711 * Access: Index 4712 */ 4713 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4714 4715 /* reg_ppcnt_clr 4716 * Clear counters. Setting the clr bit will reset the counter value 4717 * for all counters in the counter group. This bit can be set 4718 * for both Set() and Get() operation. 4719 * Access: OP 4720 */ 4721 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4722 4723 /* reg_ppcnt_prio_tc 4724 * Priority for counter set that support per priority, valid values: 0-7. 4725 * Traffic class for counter set that support per traffic class, 4726 * valid values: 0- cap_max_tclass-1 . 4727 * For HCA: cap_max_tclass is always 8. 4728 * Otherwise must be 0. 4729 * Access: Index 4730 */ 4731 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4732 4733 /* Ethernet IEEE 802.3 Counter Group */ 4734 4735 /* reg_ppcnt_a_frames_transmitted_ok 4736 * Access: RO 4737 */ 4738 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4739 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4740 4741 /* reg_ppcnt_a_frames_received_ok 4742 * Access: RO 4743 */ 4744 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4745 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4746 4747 /* reg_ppcnt_a_frame_check_sequence_errors 4748 * Access: RO 4749 */ 4750 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4751 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4752 4753 /* reg_ppcnt_a_alignment_errors 4754 * Access: RO 4755 */ 4756 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4757 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4758 4759 /* reg_ppcnt_a_octets_transmitted_ok 4760 * Access: RO 4761 */ 4762 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4763 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4764 4765 /* reg_ppcnt_a_octets_received_ok 4766 * Access: RO 4767 */ 4768 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4769 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4770 4771 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4772 * Access: RO 4773 */ 4774 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4775 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4776 4777 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4778 * Access: RO 4779 */ 4780 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4781 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4782 4783 /* reg_ppcnt_a_multicast_frames_received_ok 4784 * Access: RO 4785 */ 4786 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4787 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4788 4789 /* reg_ppcnt_a_broadcast_frames_received_ok 4790 * Access: RO 4791 */ 4792 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4793 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4794 4795 /* reg_ppcnt_a_in_range_length_errors 4796 * Access: RO 4797 */ 4798 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4799 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4800 4801 /* reg_ppcnt_a_out_of_range_length_field 4802 * Access: RO 4803 */ 4804 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4805 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4806 4807 /* reg_ppcnt_a_frame_too_long_errors 4808 * Access: RO 4809 */ 4810 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4811 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4812 4813 /* reg_ppcnt_a_symbol_error_during_carrier 4814 * Access: RO 4815 */ 4816 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4817 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4818 4819 /* reg_ppcnt_a_mac_control_frames_transmitted 4820 * Access: RO 4821 */ 4822 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4823 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4824 4825 /* reg_ppcnt_a_mac_control_frames_received 4826 * Access: RO 4827 */ 4828 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4829 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4830 4831 /* reg_ppcnt_a_unsupported_opcodes_received 4832 * Access: RO 4833 */ 4834 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4835 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4836 4837 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4838 * Access: RO 4839 */ 4840 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4841 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4842 4843 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4844 * Access: RO 4845 */ 4846 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4847 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4848 4849 /* Ethernet RFC 2863 Counter Group */ 4850 4851 /* reg_ppcnt_if_in_discards 4852 * Access: RO 4853 */ 4854 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4855 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4856 4857 /* reg_ppcnt_if_out_discards 4858 * Access: RO 4859 */ 4860 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4861 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4862 4863 /* reg_ppcnt_if_out_errors 4864 * Access: RO 4865 */ 4866 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4867 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4868 4869 /* Ethernet RFC 2819 Counter Group */ 4870 4871 /* reg_ppcnt_ether_stats_undersize_pkts 4872 * Access: RO 4873 */ 4874 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4875 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4876 4877 /* reg_ppcnt_ether_stats_oversize_pkts 4878 * Access: RO 4879 */ 4880 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4881 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4882 4883 /* reg_ppcnt_ether_stats_fragments 4884 * Access: RO 4885 */ 4886 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4887 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4888 4889 /* reg_ppcnt_ether_stats_pkts64octets 4890 * Access: RO 4891 */ 4892 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4893 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4894 4895 /* reg_ppcnt_ether_stats_pkts65to127octets 4896 * Access: RO 4897 */ 4898 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4899 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4900 4901 /* reg_ppcnt_ether_stats_pkts128to255octets 4902 * Access: RO 4903 */ 4904 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4905 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4906 4907 /* reg_ppcnt_ether_stats_pkts256to511octets 4908 * Access: RO 4909 */ 4910 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4911 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4912 4913 /* reg_ppcnt_ether_stats_pkts512to1023octets 4914 * Access: RO 4915 */ 4916 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4917 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4918 4919 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4920 * Access: RO 4921 */ 4922 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4923 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4924 4925 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4926 * Access: RO 4927 */ 4928 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4929 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4930 4931 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4932 * Access: RO 4933 */ 4934 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4935 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4936 4937 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4938 * Access: RO 4939 */ 4940 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4941 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4942 4943 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4944 * Access: RO 4945 */ 4946 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4947 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4948 4949 /* Ethernet RFC 3635 Counter Group */ 4950 4951 /* reg_ppcnt_dot3stats_fcs_errors 4952 * Access: RO 4953 */ 4954 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4955 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4956 4957 /* reg_ppcnt_dot3stats_symbol_errors 4958 * Access: RO 4959 */ 4960 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4961 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4962 4963 /* reg_ppcnt_dot3control_in_unknown_opcodes 4964 * Access: RO 4965 */ 4966 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4967 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4968 4969 /* reg_ppcnt_dot3in_pause_frames 4970 * Access: RO 4971 */ 4972 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4973 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4974 4975 /* Ethernet Extended Counter Group Counters */ 4976 4977 /* reg_ppcnt_ecn_marked 4978 * Access: RO 4979 */ 4980 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4981 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4982 4983 /* Ethernet Discard Counter Group Counters */ 4984 4985 /* reg_ppcnt_ingress_general 4986 * Access: RO 4987 */ 4988 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4989 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4990 4991 /* reg_ppcnt_ingress_policy_engine 4992 * Access: RO 4993 */ 4994 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4995 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4996 4997 /* reg_ppcnt_ingress_vlan_membership 4998 * Access: RO 4999 */ 5000 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5001 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5002 5003 /* reg_ppcnt_ingress_tag_frame_type 5004 * Access: RO 5005 */ 5006 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5007 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5008 5009 /* reg_ppcnt_egress_vlan_membership 5010 * Access: RO 5011 */ 5012 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5013 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5014 5015 /* reg_ppcnt_loopback_filter 5016 * Access: RO 5017 */ 5018 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5019 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5020 5021 /* reg_ppcnt_egress_general 5022 * Access: RO 5023 */ 5024 MLXSW_ITEM64(reg, ppcnt, egress_general, 5025 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5026 5027 /* reg_ppcnt_egress_hoq 5028 * Access: RO 5029 */ 5030 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5031 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5032 5033 /* reg_ppcnt_egress_policy_engine 5034 * Access: RO 5035 */ 5036 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5037 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5038 5039 /* reg_ppcnt_ingress_tx_link_down 5040 * Access: RO 5041 */ 5042 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5043 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5044 5045 /* reg_ppcnt_egress_stp_filter 5046 * Access: RO 5047 */ 5048 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5049 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5050 5051 /* reg_ppcnt_egress_sll 5052 * Access: RO 5053 */ 5054 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5055 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5056 5057 /* Ethernet Per Priority Group Counters */ 5058 5059 /* reg_ppcnt_rx_octets 5060 * Access: RO 5061 */ 5062 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5063 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5064 5065 /* reg_ppcnt_rx_frames 5066 * Access: RO 5067 */ 5068 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5069 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5070 5071 /* reg_ppcnt_tx_octets 5072 * Access: RO 5073 */ 5074 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5075 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5076 5077 /* reg_ppcnt_tx_frames 5078 * Access: RO 5079 */ 5080 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5081 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5082 5083 /* reg_ppcnt_rx_pause 5084 * Access: RO 5085 */ 5086 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5087 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5088 5089 /* reg_ppcnt_rx_pause_duration 5090 * Access: RO 5091 */ 5092 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5093 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5094 5095 /* reg_ppcnt_tx_pause 5096 * Access: RO 5097 */ 5098 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5099 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5100 5101 /* reg_ppcnt_tx_pause_duration 5102 * Access: RO 5103 */ 5104 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5105 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5106 5107 /* reg_ppcnt_rx_pause_transition 5108 * Access: RO 5109 */ 5110 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5111 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5112 5113 /* Ethernet Per Traffic Group Counters */ 5114 5115 /* reg_ppcnt_tc_transmit_queue 5116 * Contains the transmit queue depth in cells of traffic class 5117 * selected by prio_tc and the port selected by local_port. 5118 * The field cannot be cleared. 5119 * Access: RO 5120 */ 5121 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5122 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5123 5124 /* reg_ppcnt_tc_no_buffer_discard_uc 5125 * The number of unicast packets dropped due to lack of shared 5126 * buffer resources. 5127 * Access: RO 5128 */ 5129 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5130 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5131 5132 /* Ethernet Per Traffic Class Congestion Group Counters */ 5133 5134 /* reg_ppcnt_wred_discard 5135 * Access: RO 5136 */ 5137 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5138 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5139 5140 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5141 enum mlxsw_reg_ppcnt_grp grp, 5142 u8 prio_tc) 5143 { 5144 MLXSW_REG_ZERO(ppcnt, payload); 5145 mlxsw_reg_ppcnt_swid_set(payload, 0); 5146 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5147 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5148 mlxsw_reg_ppcnt_grp_set(payload, grp); 5149 mlxsw_reg_ppcnt_clr_set(payload, 0); 5150 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5151 } 5152 5153 /* PLIB - Port Local to InfiniBand Port 5154 * ------------------------------------ 5155 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5156 */ 5157 #define MLXSW_REG_PLIB_ID 0x500A 5158 #define MLXSW_REG_PLIB_LEN 0x10 5159 5160 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5161 5162 /* reg_plib_local_port 5163 * Local port number. 5164 * Access: Index 5165 */ 5166 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5167 5168 /* reg_plib_ib_port 5169 * InfiniBand port remapping for local_port. 5170 * Access: RW 5171 */ 5172 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5173 5174 /* PPTB - Port Prio To Buffer Register 5175 * ----------------------------------- 5176 * Configures the switch priority to buffer table. 5177 */ 5178 #define MLXSW_REG_PPTB_ID 0x500B 5179 #define MLXSW_REG_PPTB_LEN 0x10 5180 5181 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5182 5183 enum { 5184 MLXSW_REG_PPTB_MM_UM, 5185 MLXSW_REG_PPTB_MM_UNICAST, 5186 MLXSW_REG_PPTB_MM_MULTICAST, 5187 }; 5188 5189 /* reg_pptb_mm 5190 * Mapping mode. 5191 * 0 - Map both unicast and multicast packets to the same buffer. 5192 * 1 - Map only unicast packets. 5193 * 2 - Map only multicast packets. 5194 * Access: Index 5195 * 5196 * Note: SwitchX-2 only supports the first option. 5197 */ 5198 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5199 5200 /* reg_pptb_local_port 5201 * Local port number. 5202 * Access: Index 5203 */ 5204 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5205 5206 /* reg_pptb_um 5207 * Enables the update of the untagged_buf field. 5208 * Access: RW 5209 */ 5210 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5211 5212 /* reg_pptb_pm 5213 * Enables the update of the prio_to_buff field. 5214 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5215 * Access: RW 5216 */ 5217 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5218 5219 /* reg_pptb_prio_to_buff 5220 * Mapping of switch priority <i> to one of the allocated receive port 5221 * buffers. 5222 * Access: RW 5223 */ 5224 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5225 5226 /* reg_pptb_pm_msb 5227 * Enables the update of the prio_to_buff field. 5228 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5229 * Access: RW 5230 */ 5231 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5232 5233 /* reg_pptb_untagged_buff 5234 * Mapping of untagged frames to one of the allocated receive port buffers. 5235 * Access: RW 5236 * 5237 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5238 * Spectrum, as it maps untagged packets based on the default switch priority. 5239 */ 5240 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5241 5242 /* reg_pptb_prio_to_buff_msb 5243 * Mapping of switch priority <i+8> to one of the allocated receive port 5244 * buffers. 5245 * Access: RW 5246 */ 5247 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5248 5249 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5250 5251 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5252 { 5253 MLXSW_REG_ZERO(pptb, payload); 5254 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5255 mlxsw_reg_pptb_local_port_set(payload, local_port); 5256 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5257 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5258 } 5259 5260 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5261 u8 buff) 5262 { 5263 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5264 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5265 } 5266 5267 /* PBMC - Port Buffer Management Control Register 5268 * ---------------------------------------------- 5269 * The PBMC register configures and retrieves the port packet buffer 5270 * allocation for different Prios, and the Pause threshold management. 5271 */ 5272 #define MLXSW_REG_PBMC_ID 0x500C 5273 #define MLXSW_REG_PBMC_LEN 0x6C 5274 5275 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5276 5277 /* reg_pbmc_local_port 5278 * Local port number. 5279 * Access: Index 5280 */ 5281 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5282 5283 /* reg_pbmc_xoff_timer_value 5284 * When device generates a pause frame, it uses this value as the pause 5285 * timer (time for the peer port to pause in quota-512 bit time). 5286 * Access: RW 5287 */ 5288 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5289 5290 /* reg_pbmc_xoff_refresh 5291 * The time before a new pause frame should be sent to refresh the pause RW 5292 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5293 * time). 5294 * Access: RW 5295 */ 5296 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5297 5298 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5299 5300 /* reg_pbmc_buf_lossy 5301 * The field indicates if the buffer is lossy. 5302 * 0 - Lossless 5303 * 1 - Lossy 5304 * Access: RW 5305 */ 5306 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5307 5308 /* reg_pbmc_buf_epsb 5309 * Eligible for Port Shared buffer. 5310 * If epsb is set, packets assigned to buffer are allowed to insert the port 5311 * shared buffer. 5312 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5313 * Access: RW 5314 */ 5315 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5316 5317 /* reg_pbmc_buf_size 5318 * The part of the packet buffer array is allocated for the specific buffer. 5319 * Units are represented in cells. 5320 * Access: RW 5321 */ 5322 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5323 5324 /* reg_pbmc_buf_xoff_threshold 5325 * Once the amount of data in the buffer goes above this value, device 5326 * starts sending PFC frames for all priorities associated with the 5327 * buffer. Units are represented in cells. Reserved in case of lossy 5328 * buffer. 5329 * Access: RW 5330 * 5331 * Note: In Spectrum, reserved for buffer[9]. 5332 */ 5333 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5334 0x08, 0x04, false); 5335 5336 /* reg_pbmc_buf_xon_threshold 5337 * When the amount of data in the buffer goes below this value, device 5338 * stops sending PFC frames for the priorities associated with the 5339 * buffer. Units are represented in cells. Reserved in case of lossy 5340 * buffer. 5341 * Access: RW 5342 * 5343 * Note: In Spectrum, reserved for buffer[9]. 5344 */ 5345 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5346 0x08, 0x04, false); 5347 5348 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5349 u16 xoff_timer_value, u16 xoff_refresh) 5350 { 5351 MLXSW_REG_ZERO(pbmc, payload); 5352 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5353 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5354 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5355 } 5356 5357 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5358 int buf_index, 5359 u16 size) 5360 { 5361 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5362 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5363 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5364 } 5365 5366 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5367 int buf_index, u16 size, 5368 u16 threshold) 5369 { 5370 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5371 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5372 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5373 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5374 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5375 } 5376 5377 /* PSPA - Port Switch Partition Allocation 5378 * --------------------------------------- 5379 * Controls the association of a port with a switch partition and enables 5380 * configuring ports as stacking ports. 5381 */ 5382 #define MLXSW_REG_PSPA_ID 0x500D 5383 #define MLXSW_REG_PSPA_LEN 0x8 5384 5385 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5386 5387 /* reg_pspa_swid 5388 * Switch partition ID. 5389 * Access: RW 5390 */ 5391 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5392 5393 /* reg_pspa_local_port 5394 * Local port number. 5395 * Access: Index 5396 */ 5397 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5398 5399 /* reg_pspa_sub_port 5400 * Virtual port within the local port. Set to 0 when virtual ports are 5401 * disabled on the local port. 5402 * Access: Index 5403 */ 5404 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5405 5406 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5407 { 5408 MLXSW_REG_ZERO(pspa, payload); 5409 mlxsw_reg_pspa_swid_set(payload, swid); 5410 mlxsw_reg_pspa_local_port_set(payload, local_port); 5411 mlxsw_reg_pspa_sub_port_set(payload, 0); 5412 } 5413 5414 /* PPLR - Port Physical Loopback Register 5415 * -------------------------------------- 5416 * This register allows configuration of the port's loopback mode. 5417 */ 5418 #define MLXSW_REG_PPLR_ID 0x5018 5419 #define MLXSW_REG_PPLR_LEN 0x8 5420 5421 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5422 5423 /* reg_pplr_local_port 5424 * Local port number. 5425 * Access: Index 5426 */ 5427 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5428 5429 /* Phy local loopback. When set the port's egress traffic is looped back 5430 * to the receiver and the port transmitter is disabled. 5431 */ 5432 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5433 5434 /* reg_pplr_lb_en 5435 * Loopback enable. 5436 * Access: RW 5437 */ 5438 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5439 5440 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5441 bool phy_local) 5442 { 5443 MLXSW_REG_ZERO(pplr, payload); 5444 mlxsw_reg_pplr_local_port_set(payload, local_port); 5445 mlxsw_reg_pplr_lb_en_set(payload, 5446 phy_local ? 5447 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5448 } 5449 5450 /* PDDR - Port Diagnostics Database Register 5451 * ----------------------------------------- 5452 * The PDDR enables to read the Phy debug database 5453 */ 5454 #define MLXSW_REG_PDDR_ID 0x5031 5455 #define MLXSW_REG_PDDR_LEN 0x100 5456 5457 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 5458 5459 /* reg_pddr_local_port 5460 * Local port number. 5461 * Access: Index 5462 */ 5463 MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8); 5464 5465 enum mlxsw_reg_pddr_page_select { 5466 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 5467 }; 5468 5469 /* reg_pddr_page_select 5470 * Page select index. 5471 * Access: Index 5472 */ 5473 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 5474 5475 enum mlxsw_reg_pddr_trblsh_group_opcode { 5476 /* Monitor opcodes */ 5477 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 5478 }; 5479 5480 /* reg_pddr_group_opcode 5481 * Group selector. 5482 * Access: Index 5483 */ 5484 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 5485 5486 /* reg_pddr_status_opcode 5487 * Group selector. 5488 * Access: RO 5489 */ 5490 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 5491 5492 static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port, 5493 u8 page_select) 5494 { 5495 MLXSW_REG_ZERO(pddr, payload); 5496 mlxsw_reg_pddr_local_port_set(payload, local_port); 5497 mlxsw_reg_pddr_page_select_set(payload, page_select); 5498 } 5499 5500 /* PMTM - Port Module Type Mapping Register 5501 * ---------------------------------------- 5502 * The PMTM allows query or configuration of module types. 5503 */ 5504 #define MLXSW_REG_PMTM_ID 0x5067 5505 #define MLXSW_REG_PMTM_LEN 0x10 5506 5507 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5508 5509 /* reg_pmtm_module 5510 * Module number. 5511 * Access: Index 5512 */ 5513 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5514 5515 enum mlxsw_reg_pmtm_module_type { 5516 /* Backplane with 4 lanes */ 5517 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5518 /* QSFP */ 5519 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5520 /* SFP */ 5521 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5522 /* Backplane with single lane */ 5523 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5524 /* Backplane with two lane */ 5525 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5526 /* Chip2Chip4x */ 5527 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5528 /* Chip2Chip2x */ 5529 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5530 /* Chip2Chip1x */ 5531 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5532 /* QSFP-DD */ 5533 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5534 /* OSFP */ 5535 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5536 /* SFP-DD */ 5537 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5538 /* DSFP */ 5539 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5540 /* Chip2Chip8x */ 5541 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5542 }; 5543 5544 /* reg_pmtm_module_type 5545 * Module type. 5546 * Access: RW 5547 */ 5548 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5549 5550 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5551 { 5552 MLXSW_REG_ZERO(pmtm, payload); 5553 mlxsw_reg_pmtm_module_set(payload, module); 5554 } 5555 5556 static inline void 5557 mlxsw_reg_pmtm_unpack(char *payload, 5558 enum mlxsw_reg_pmtm_module_type *module_type) 5559 { 5560 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5561 } 5562 5563 /* HTGT - Host Trap Group Table 5564 * ---------------------------- 5565 * Configures the properties for forwarding to CPU. 5566 */ 5567 #define MLXSW_REG_HTGT_ID 0x7002 5568 #define MLXSW_REG_HTGT_LEN 0x20 5569 5570 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5571 5572 /* reg_htgt_swid 5573 * Switch partition ID. 5574 * Access: Index 5575 */ 5576 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5577 5578 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5579 5580 /* reg_htgt_type 5581 * CPU path type. 5582 * Access: RW 5583 */ 5584 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5585 5586 enum mlxsw_reg_htgt_trap_group { 5587 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5588 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5589 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5590 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5591 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5592 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5593 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5594 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5595 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5596 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5597 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5598 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 5599 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5600 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5601 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5602 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5603 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5604 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5605 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5606 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5607 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5608 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5609 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5610 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5611 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5612 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5613 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5614 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5615 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5616 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5617 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 5618 5619 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5620 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5621 }; 5622 5623 /* reg_htgt_trap_group 5624 * Trap group number. User defined number specifying which trap groups 5625 * should be forwarded to the CPU. The mapping between trap IDs and trap 5626 * groups is configured using HPKT register. 5627 * Access: Index 5628 */ 5629 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5630 5631 enum { 5632 MLXSW_REG_HTGT_POLICER_DISABLE, 5633 MLXSW_REG_HTGT_POLICER_ENABLE, 5634 }; 5635 5636 /* reg_htgt_pide 5637 * Enable policer ID specified using 'pid' field. 5638 * Access: RW 5639 */ 5640 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5641 5642 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5643 5644 /* reg_htgt_pid 5645 * Policer ID for the trap group. 5646 * Access: RW 5647 */ 5648 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5649 5650 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5651 5652 /* reg_htgt_mirror_action 5653 * Mirror action to use. 5654 * 0 - Trap to CPU. 5655 * 1 - Trap to CPU and mirror to a mirroring agent. 5656 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5657 * Access: RW 5658 * 5659 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5660 */ 5661 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5662 5663 /* reg_htgt_mirroring_agent 5664 * Mirroring agent. 5665 * Access: RW 5666 */ 5667 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5668 5669 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5670 5671 /* reg_htgt_priority 5672 * Trap group priority. 5673 * In case a packet matches multiple classification rules, the packet will 5674 * only be trapped once, based on the trap ID associated with the group (via 5675 * register HPKT) with the highest priority. 5676 * Supported values are 0-7, with 7 represnting the highest priority. 5677 * Access: RW 5678 * 5679 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5680 * by the 'trap_group' field. 5681 */ 5682 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5683 5684 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5685 5686 /* reg_htgt_local_path_cpu_tclass 5687 * CPU ingress traffic class for the trap group. 5688 * Access: RW 5689 */ 5690 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5691 5692 enum mlxsw_reg_htgt_local_path_rdq { 5693 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5694 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5695 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5696 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5697 }; 5698 /* reg_htgt_local_path_rdq 5699 * Receive descriptor queue (RDQ) to use for the trap group. 5700 * Access: RW 5701 */ 5702 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5703 5704 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5705 u8 priority, u8 tc) 5706 { 5707 MLXSW_REG_ZERO(htgt, payload); 5708 5709 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5710 mlxsw_reg_htgt_pide_set(payload, 5711 MLXSW_REG_HTGT_POLICER_DISABLE); 5712 } else { 5713 mlxsw_reg_htgt_pide_set(payload, 5714 MLXSW_REG_HTGT_POLICER_ENABLE); 5715 mlxsw_reg_htgt_pid_set(payload, policer_id); 5716 } 5717 5718 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5719 mlxsw_reg_htgt_trap_group_set(payload, group); 5720 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5721 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5722 mlxsw_reg_htgt_priority_set(payload, priority); 5723 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5724 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5725 } 5726 5727 /* HPKT - Host Packet Trap 5728 * ----------------------- 5729 * Configures trap IDs inside trap groups. 5730 */ 5731 #define MLXSW_REG_HPKT_ID 0x7003 5732 #define MLXSW_REG_HPKT_LEN 0x10 5733 5734 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5735 5736 enum { 5737 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5738 MLXSW_REG_HPKT_ACK_REQUIRED, 5739 }; 5740 5741 /* reg_hpkt_ack 5742 * Require acknowledgements from the host for events. 5743 * If set, then the device will wait for the event it sent to be acknowledged 5744 * by the host. This option is only relevant for event trap IDs. 5745 * Access: RW 5746 * 5747 * Note: Currently not supported by firmware. 5748 */ 5749 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5750 5751 enum mlxsw_reg_hpkt_action { 5752 MLXSW_REG_HPKT_ACTION_FORWARD, 5753 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5754 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5755 MLXSW_REG_HPKT_ACTION_DISCARD, 5756 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5757 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5758 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 5759 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 5760 }; 5761 5762 /* reg_hpkt_action 5763 * Action to perform on packet when trapped. 5764 * 0 - No action. Forward to CPU based on switching rules. 5765 * 1 - Trap to CPU (CPU receives sole copy). 5766 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5767 * 3 - Discard. 5768 * 4 - Soft discard (allow other traps to act on the packet). 5769 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5770 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 5771 * 15 - Restore the firmware's default action. 5772 * Access: RW 5773 * 5774 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5775 * addressed to the CPU. 5776 */ 5777 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5778 5779 /* reg_hpkt_trap_group 5780 * Trap group to associate the trap with. 5781 * Access: RW 5782 */ 5783 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5784 5785 /* reg_hpkt_trap_id 5786 * Trap ID. 5787 * Access: Index 5788 * 5789 * Note: A trap ID can only be associated with a single trap group. The device 5790 * will associate the trap ID with the last trap group configured. 5791 */ 5792 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 5793 5794 enum { 5795 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5796 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5797 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5798 }; 5799 5800 /* reg_hpkt_ctrl 5801 * Configure dedicated buffer resources for control packets. 5802 * Ignored by SwitchX-2. 5803 * 0 - Keep factory defaults. 5804 * 1 - Do not use control buffer for this trap ID. 5805 * 2 - Use control buffer for this trap ID. 5806 * Access: RW 5807 */ 5808 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5809 5810 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5811 enum mlxsw_reg_htgt_trap_group trap_group, 5812 bool is_ctrl) 5813 { 5814 MLXSW_REG_ZERO(hpkt, payload); 5815 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5816 mlxsw_reg_hpkt_action_set(payload, action); 5817 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5818 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5819 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5820 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5821 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5822 } 5823 5824 /* RGCR - Router General Configuration Register 5825 * -------------------------------------------- 5826 * The register is used for setting up the router configuration. 5827 */ 5828 #define MLXSW_REG_RGCR_ID 0x8001 5829 #define MLXSW_REG_RGCR_LEN 0x28 5830 5831 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5832 5833 /* reg_rgcr_ipv4_en 5834 * IPv4 router enable. 5835 * Access: RW 5836 */ 5837 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5838 5839 /* reg_rgcr_ipv6_en 5840 * IPv6 router enable. 5841 * Access: RW 5842 */ 5843 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5844 5845 /* reg_rgcr_max_router_interfaces 5846 * Defines the maximum number of active router interfaces for all virtual 5847 * routers. 5848 * Access: RW 5849 */ 5850 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5851 5852 /* reg_rgcr_usp 5853 * Update switch priority and packet color. 5854 * 0 - Preserve the value of Switch Priority and packet color. 5855 * 1 - Recalculate the value of Switch Priority and packet color. 5856 * Access: RW 5857 * 5858 * Note: Not supported by SwitchX and SwitchX-2. 5859 */ 5860 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5861 5862 /* reg_rgcr_pcp_rw 5863 * Indicates how to handle the pcp_rewrite_en value: 5864 * 0 - Preserve the value of pcp_rewrite_en. 5865 * 2 - Disable PCP rewrite. 5866 * 3 - Enable PCP rewrite. 5867 * Access: RW 5868 * 5869 * Note: Not supported by SwitchX and SwitchX-2. 5870 */ 5871 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5872 5873 /* reg_rgcr_activity_dis 5874 * Activity disable: 5875 * 0 - Activity will be set when an entry is hit (default). 5876 * 1 - Activity will not be set when an entry is hit. 5877 * 5878 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5879 * (RALUE). 5880 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5881 * Entry (RAUHT). 5882 * Bits 2:7 are reserved. 5883 * Access: RW 5884 * 5885 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5886 */ 5887 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5888 5889 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5890 bool ipv6_en) 5891 { 5892 MLXSW_REG_ZERO(rgcr, payload); 5893 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5894 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5895 } 5896 5897 /* RITR - Router Interface Table Register 5898 * -------------------------------------- 5899 * The register is used to configure the router interface table. 5900 */ 5901 #define MLXSW_REG_RITR_ID 0x8002 5902 #define MLXSW_REG_RITR_LEN 0x40 5903 5904 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5905 5906 /* reg_ritr_enable 5907 * Enables routing on the router interface. 5908 * Access: RW 5909 */ 5910 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5911 5912 /* reg_ritr_ipv4 5913 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5914 * interface. 5915 * Access: RW 5916 */ 5917 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5918 5919 /* reg_ritr_ipv6 5920 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5921 * interface. 5922 * Access: RW 5923 */ 5924 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5925 5926 /* reg_ritr_ipv4_mc 5927 * IPv4 multicast routing enable. 5928 * Access: RW 5929 */ 5930 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5931 5932 /* reg_ritr_ipv6_mc 5933 * IPv6 multicast routing enable. 5934 * Access: RW 5935 */ 5936 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5937 5938 enum mlxsw_reg_ritr_if_type { 5939 /* VLAN interface. */ 5940 MLXSW_REG_RITR_VLAN_IF, 5941 /* FID interface. */ 5942 MLXSW_REG_RITR_FID_IF, 5943 /* Sub-port interface. */ 5944 MLXSW_REG_RITR_SP_IF, 5945 /* Loopback Interface. */ 5946 MLXSW_REG_RITR_LOOPBACK_IF, 5947 }; 5948 5949 /* reg_ritr_type 5950 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5951 * Access: RW 5952 */ 5953 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5954 5955 enum { 5956 MLXSW_REG_RITR_RIF_CREATE, 5957 MLXSW_REG_RITR_RIF_DEL, 5958 }; 5959 5960 /* reg_ritr_op 5961 * Opcode: 5962 * 0 - Create or edit RIF. 5963 * 1 - Delete RIF. 5964 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5965 * is not supported. An interface must be deleted and re-created in order 5966 * to update properties. 5967 * Access: WO 5968 */ 5969 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5970 5971 /* reg_ritr_rif 5972 * Router interface index. A pointer to the Router Interface Table. 5973 * Access: Index 5974 */ 5975 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5976 5977 /* reg_ritr_ipv4_fe 5978 * IPv4 Forwarding Enable. 5979 * Enables routing of IPv4 traffic on the router interface. When disabled, 5980 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5981 * Not supported in SwitchX-2. 5982 * Access: RW 5983 */ 5984 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5985 5986 /* reg_ritr_ipv6_fe 5987 * IPv6 Forwarding Enable. 5988 * Enables routing of IPv6 traffic on the router interface. When disabled, 5989 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5990 * Not supported in SwitchX-2. 5991 * Access: RW 5992 */ 5993 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5994 5995 /* reg_ritr_ipv4_mc_fe 5996 * IPv4 Multicast Forwarding Enable. 5997 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5998 * will be enabled. 5999 * Access: RW 6000 */ 6001 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6002 6003 /* reg_ritr_ipv6_mc_fe 6004 * IPv6 Multicast Forwarding Enable. 6005 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6006 * will be enabled. 6007 * Access: RW 6008 */ 6009 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6010 6011 /* reg_ritr_lb_en 6012 * Loop-back filter enable for unicast packets. 6013 * If the flag is set then loop-back filter for unicast packets is 6014 * implemented on the RIF. Multicast packets are always subject to 6015 * loop-back filtering. 6016 * Access: RW 6017 */ 6018 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6019 6020 /* reg_ritr_virtual_router 6021 * Virtual router ID associated with the router interface. 6022 * Access: RW 6023 */ 6024 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6025 6026 /* reg_ritr_mtu 6027 * Router interface MTU. 6028 * Access: RW 6029 */ 6030 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6031 6032 /* reg_ritr_if_swid 6033 * Switch partition ID. 6034 * Access: RW 6035 */ 6036 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6037 6038 /* reg_ritr_if_mac 6039 * Router interface MAC address. 6040 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6041 * Access: RW 6042 */ 6043 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6044 6045 /* reg_ritr_if_vrrp_id_ipv6 6046 * VRRP ID for IPv6 6047 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6048 * Access: RW 6049 */ 6050 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6051 6052 /* reg_ritr_if_vrrp_id_ipv4 6053 * VRRP ID for IPv4 6054 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6055 * Access: RW 6056 */ 6057 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6058 6059 /* VLAN Interface */ 6060 6061 /* reg_ritr_vlan_if_vid 6062 * VLAN ID. 6063 * Access: RW 6064 */ 6065 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6066 6067 /* FID Interface */ 6068 6069 /* reg_ritr_fid_if_fid 6070 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6071 * the vFID range are supported. 6072 * Access: RW 6073 */ 6074 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6075 6076 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6077 enum mlxsw_reg_ritr_if_type rif_type, 6078 u16 fid) 6079 { 6080 if (rif_type == MLXSW_REG_RITR_FID_IF) 6081 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6082 else 6083 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6084 } 6085 6086 /* Sub-port Interface */ 6087 6088 /* reg_ritr_sp_if_lag 6089 * LAG indication. When this bit is set the system_port field holds the 6090 * LAG identifier. 6091 * Access: RW 6092 */ 6093 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6094 6095 /* reg_ritr_sp_system_port 6096 * Port unique indentifier. When lag bit is set, this field holds the 6097 * lag_id in bits 0:9. 6098 * Access: RW 6099 */ 6100 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6101 6102 /* reg_ritr_sp_if_vid 6103 * VLAN ID. 6104 * Access: RW 6105 */ 6106 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6107 6108 /* Loopback Interface */ 6109 6110 enum mlxsw_reg_ritr_loopback_protocol { 6111 /* IPinIP IPv4 underlay Unicast */ 6112 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6113 /* IPinIP IPv6 underlay Unicast */ 6114 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6115 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6116 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6117 }; 6118 6119 /* reg_ritr_loopback_protocol 6120 * Access: RW 6121 */ 6122 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6123 6124 enum mlxsw_reg_ritr_loopback_ipip_type { 6125 /* Tunnel is IPinIP. */ 6126 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6127 /* Tunnel is GRE, no key. */ 6128 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6129 /* Tunnel is GRE, with a key. */ 6130 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6131 }; 6132 6133 /* reg_ritr_loopback_ipip_type 6134 * Encapsulation type. 6135 * Access: RW 6136 */ 6137 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6138 6139 enum mlxsw_reg_ritr_loopback_ipip_options { 6140 /* The key is defined by gre_key. */ 6141 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6142 }; 6143 6144 /* reg_ritr_loopback_ipip_options 6145 * Access: RW 6146 */ 6147 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6148 6149 /* reg_ritr_loopback_ipip_uvr 6150 * Underlay Virtual Router ID. 6151 * Range is 0..cap_max_virtual_routers-1. 6152 * Reserved for Spectrum-2. 6153 * Access: RW 6154 */ 6155 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6156 6157 /* reg_ritr_loopback_ipip_underlay_rif 6158 * Underlay ingress router interface. 6159 * Reserved for Spectrum. 6160 * Access: RW 6161 */ 6162 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6163 6164 /* reg_ritr_loopback_ipip_usip* 6165 * Encapsulation Underlay source IP. 6166 * Access: RW 6167 */ 6168 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6169 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6170 6171 /* reg_ritr_loopback_ipip_gre_key 6172 * GRE Key. 6173 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6174 * Access: RW 6175 */ 6176 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6177 6178 /* Shared between ingress/egress */ 6179 enum mlxsw_reg_ritr_counter_set_type { 6180 /* No Count. */ 6181 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6182 /* Basic. Used for router interfaces, counting the following: 6183 * - Error and Discard counters. 6184 * - Unicast, Multicast and Broadcast counters. Sharing the 6185 * same set of counters for the different type of traffic 6186 * (IPv4, IPv6 and mpls). 6187 */ 6188 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6189 }; 6190 6191 /* reg_ritr_ingress_counter_index 6192 * Counter Index for flow counter. 6193 * Access: RW 6194 */ 6195 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6196 6197 /* reg_ritr_ingress_counter_set_type 6198 * Igress Counter Set Type for router interface counter. 6199 * Access: RW 6200 */ 6201 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6202 6203 /* reg_ritr_egress_counter_index 6204 * Counter Index for flow counter. 6205 * Access: RW 6206 */ 6207 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6208 6209 /* reg_ritr_egress_counter_set_type 6210 * Egress Counter Set Type for router interface counter. 6211 * Access: RW 6212 */ 6213 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6214 6215 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6216 bool enable, bool egress) 6217 { 6218 enum mlxsw_reg_ritr_counter_set_type set_type; 6219 6220 if (enable) 6221 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6222 else 6223 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6224 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6225 6226 if (egress) 6227 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6228 else 6229 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6230 } 6231 6232 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6233 { 6234 MLXSW_REG_ZERO(ritr, payload); 6235 mlxsw_reg_ritr_rif_set(payload, rif); 6236 } 6237 6238 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6239 u16 system_port, u16 vid) 6240 { 6241 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6242 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6243 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6244 } 6245 6246 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6247 enum mlxsw_reg_ritr_if_type type, 6248 u16 rif, u16 vr_id, u16 mtu) 6249 { 6250 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6251 6252 MLXSW_REG_ZERO(ritr, payload); 6253 mlxsw_reg_ritr_enable_set(payload, enable); 6254 mlxsw_reg_ritr_ipv4_set(payload, 1); 6255 mlxsw_reg_ritr_ipv6_set(payload, 1); 6256 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6257 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6258 mlxsw_reg_ritr_type_set(payload, type); 6259 mlxsw_reg_ritr_op_set(payload, op); 6260 mlxsw_reg_ritr_rif_set(payload, rif); 6261 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6262 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6263 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6264 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6265 mlxsw_reg_ritr_lb_en_set(payload, 1); 6266 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6267 mlxsw_reg_ritr_mtu_set(payload, mtu); 6268 } 6269 6270 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6271 { 6272 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6273 } 6274 6275 static inline void 6276 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6277 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6278 enum mlxsw_reg_ritr_loopback_ipip_options options, 6279 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6280 { 6281 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6282 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6283 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6284 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6285 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6286 } 6287 6288 static inline void 6289 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6290 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6291 enum mlxsw_reg_ritr_loopback_ipip_options options, 6292 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6293 { 6294 mlxsw_reg_ritr_loopback_protocol_set(payload, 6295 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6296 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6297 uvr_id, underlay_rif, gre_key); 6298 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6299 } 6300 6301 /* RTAR - Router TCAM Allocation Register 6302 * -------------------------------------- 6303 * This register is used for allocation of regions in the TCAM table. 6304 */ 6305 #define MLXSW_REG_RTAR_ID 0x8004 6306 #define MLXSW_REG_RTAR_LEN 0x20 6307 6308 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6309 6310 enum mlxsw_reg_rtar_op { 6311 MLXSW_REG_RTAR_OP_ALLOCATE, 6312 MLXSW_REG_RTAR_OP_RESIZE, 6313 MLXSW_REG_RTAR_OP_DEALLOCATE, 6314 }; 6315 6316 /* reg_rtar_op 6317 * Access: WO 6318 */ 6319 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6320 6321 enum mlxsw_reg_rtar_key_type { 6322 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6323 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6324 }; 6325 6326 /* reg_rtar_key_type 6327 * TCAM key type for the region. 6328 * Access: WO 6329 */ 6330 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6331 6332 /* reg_rtar_region_size 6333 * TCAM region size. When allocating/resizing this is the requested 6334 * size, the response is the actual size. 6335 * Note: Actual size may be larger than requested. 6336 * Reserved for op = Deallocate 6337 * Access: WO 6338 */ 6339 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6340 6341 static inline void mlxsw_reg_rtar_pack(char *payload, 6342 enum mlxsw_reg_rtar_op op, 6343 enum mlxsw_reg_rtar_key_type key_type, 6344 u16 region_size) 6345 { 6346 MLXSW_REG_ZERO(rtar, payload); 6347 mlxsw_reg_rtar_op_set(payload, op); 6348 mlxsw_reg_rtar_key_type_set(payload, key_type); 6349 mlxsw_reg_rtar_region_size_set(payload, region_size); 6350 } 6351 6352 /* RATR - Router Adjacency Table Register 6353 * -------------------------------------- 6354 * The RATR register is used to configure the Router Adjacency (next-hop) 6355 * Table. 6356 */ 6357 #define MLXSW_REG_RATR_ID 0x8008 6358 #define MLXSW_REG_RATR_LEN 0x2C 6359 6360 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6361 6362 enum mlxsw_reg_ratr_op { 6363 /* Read */ 6364 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6365 /* Read and clear activity */ 6366 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6367 /* Write Adjacency entry */ 6368 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6369 /* Write Adjacency entry only if the activity is cleared. 6370 * The write may not succeed if the activity is set. There is not 6371 * direct feedback if the write has succeeded or not, however 6372 * the get will reveal the actual entry (SW can compare the get 6373 * response to the set command). 6374 */ 6375 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6376 }; 6377 6378 /* reg_ratr_op 6379 * Note that Write operation may also be used for updating 6380 * counter_set_type and counter_index. In this case all other 6381 * fields must not be updated. 6382 * Access: OP 6383 */ 6384 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6385 6386 /* reg_ratr_v 6387 * Valid bit. Indicates if the adjacency entry is valid. 6388 * Note: the device may need some time before reusing an invalidated 6389 * entry. During this time the entry can not be reused. It is 6390 * recommended to use another entry before reusing an invalidated 6391 * entry (e.g. software can put it at the end of the list for 6392 * reusing). Trying to access an invalidated entry not yet cleared 6393 * by the device results with failure indicating "Try Again" status. 6394 * When valid is '0' then egress_router_interface,trap_action, 6395 * adjacency_parameters and counters are reserved 6396 * Access: RW 6397 */ 6398 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6399 6400 /* reg_ratr_a 6401 * Activity. Set for new entries. Set if a packet lookup has hit on 6402 * the specific entry. To clear the a bit, use "clear activity". 6403 * Access: RO 6404 */ 6405 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6406 6407 enum mlxsw_reg_ratr_type { 6408 /* Ethernet */ 6409 MLXSW_REG_RATR_TYPE_ETHERNET, 6410 /* IPoIB Unicast without GRH. 6411 * Reserved for Spectrum. 6412 */ 6413 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6414 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6415 * adjacency). 6416 * Reserved for Spectrum. 6417 */ 6418 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6419 /* IPoIB Multicast. 6420 * Reserved for Spectrum. 6421 */ 6422 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6423 /* MPLS. 6424 * Reserved for SwitchX/-2. 6425 */ 6426 MLXSW_REG_RATR_TYPE_MPLS, 6427 /* IPinIP Encap. 6428 * Reserved for SwitchX/-2. 6429 */ 6430 MLXSW_REG_RATR_TYPE_IPIP, 6431 }; 6432 6433 /* reg_ratr_type 6434 * Adjacency entry type. 6435 * Access: RW 6436 */ 6437 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6438 6439 /* reg_ratr_adjacency_index_low 6440 * Bits 15:0 of index into the adjacency table. 6441 * For SwitchX and SwitchX-2, the adjacency table is linear and 6442 * used for adjacency entries only. 6443 * For Spectrum, the index is to the KVD linear. 6444 * Access: Index 6445 */ 6446 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6447 6448 /* reg_ratr_egress_router_interface 6449 * Range is 0 .. cap_max_router_interfaces - 1 6450 * Access: RW 6451 */ 6452 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6453 6454 enum mlxsw_reg_ratr_trap_action { 6455 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6456 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6457 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6458 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6459 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6460 }; 6461 6462 /* reg_ratr_trap_action 6463 * see mlxsw_reg_ratr_trap_action 6464 * Access: RW 6465 */ 6466 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6467 6468 /* reg_ratr_adjacency_index_high 6469 * Bits 23:16 of the adjacency_index. 6470 * Access: Index 6471 */ 6472 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6473 6474 enum mlxsw_reg_ratr_trap_id { 6475 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6476 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6477 }; 6478 6479 /* reg_ratr_trap_id 6480 * Trap ID to be reported to CPU. 6481 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6482 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6483 * Access: RW 6484 */ 6485 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6486 6487 /* reg_ratr_eth_destination_mac 6488 * MAC address of the destination next-hop. 6489 * Access: RW 6490 */ 6491 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6492 6493 enum mlxsw_reg_ratr_ipip_type { 6494 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6495 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6496 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6497 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6498 }; 6499 6500 /* reg_ratr_ipip_type 6501 * Underlay destination ip type. 6502 * Note: the type field must match the protocol of the router interface. 6503 * Access: RW 6504 */ 6505 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6506 6507 /* reg_ratr_ipip_ipv4_udip 6508 * Underlay ipv4 dip. 6509 * Reserved when ipip_type is IPv6. 6510 * Access: RW 6511 */ 6512 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6513 6514 /* reg_ratr_ipip_ipv6_ptr 6515 * Pointer to IPv6 underlay destination ip address. 6516 * For Spectrum: Pointer to KVD linear space. 6517 * Access: RW 6518 */ 6519 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6520 6521 enum mlxsw_reg_flow_counter_set_type { 6522 /* No count */ 6523 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6524 /* Count packets and bytes */ 6525 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6526 /* Count only packets */ 6527 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6528 }; 6529 6530 /* reg_ratr_counter_set_type 6531 * Counter set type for flow counters 6532 * Access: RW 6533 */ 6534 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6535 6536 /* reg_ratr_counter_index 6537 * Counter index for flow counters 6538 * Access: RW 6539 */ 6540 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6541 6542 static inline void 6543 mlxsw_reg_ratr_pack(char *payload, 6544 enum mlxsw_reg_ratr_op op, bool valid, 6545 enum mlxsw_reg_ratr_type type, 6546 u32 adjacency_index, u16 egress_rif) 6547 { 6548 MLXSW_REG_ZERO(ratr, payload); 6549 mlxsw_reg_ratr_op_set(payload, op); 6550 mlxsw_reg_ratr_v_set(payload, valid); 6551 mlxsw_reg_ratr_type_set(payload, type); 6552 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6553 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6554 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6555 } 6556 6557 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6558 const char *dest_mac) 6559 { 6560 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6561 } 6562 6563 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6564 { 6565 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6566 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6567 } 6568 6569 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6570 bool counter_enable) 6571 { 6572 enum mlxsw_reg_flow_counter_set_type set_type; 6573 6574 if (counter_enable) 6575 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6576 else 6577 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6578 6579 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6580 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6581 } 6582 6583 /* RDPM - Router DSCP to Priority Mapping 6584 * -------------------------------------- 6585 * Controls the mapping from DSCP field to switch priority on routed packets 6586 */ 6587 #define MLXSW_REG_RDPM_ID 0x8009 6588 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6589 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6590 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6591 #define MLXSW_REG_RDPM_LEN 0x40 6592 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6593 MLXSW_REG_RDPM_LEN - \ 6594 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6595 6596 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6597 6598 /* reg_dscp_entry_e 6599 * Enable update of the specific entry 6600 * Access: Index 6601 */ 6602 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6603 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6604 6605 /* reg_dscp_entry_prio 6606 * Switch Priority 6607 * Access: RW 6608 */ 6609 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6610 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6611 6612 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6613 u8 prio) 6614 { 6615 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6616 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6617 } 6618 6619 /* RICNT - Router Interface Counter Register 6620 * ----------------------------------------- 6621 * The RICNT register retrieves per port performance counters 6622 */ 6623 #define MLXSW_REG_RICNT_ID 0x800B 6624 #define MLXSW_REG_RICNT_LEN 0x100 6625 6626 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6627 6628 /* reg_ricnt_counter_index 6629 * Counter index 6630 * Access: RW 6631 */ 6632 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6633 6634 enum mlxsw_reg_ricnt_counter_set_type { 6635 /* No Count. */ 6636 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6637 /* Basic. Used for router interfaces, counting the following: 6638 * - Error and Discard counters. 6639 * - Unicast, Multicast and Broadcast counters. Sharing the 6640 * same set of counters for the different type of traffic 6641 * (IPv4, IPv6 and mpls). 6642 */ 6643 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6644 }; 6645 6646 /* reg_ricnt_counter_set_type 6647 * Counter Set Type for router interface counter 6648 * Access: RW 6649 */ 6650 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6651 6652 enum mlxsw_reg_ricnt_opcode { 6653 /* Nop. Supported only for read access*/ 6654 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6655 /* Clear. Setting the clr bit will reset the counter value for 6656 * all counters of the specified Router Interface. 6657 */ 6658 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6659 }; 6660 6661 /* reg_ricnt_opcode 6662 * Opcode 6663 * Access: RW 6664 */ 6665 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6666 6667 /* reg_ricnt_good_unicast_packets 6668 * good unicast packets. 6669 * Access: RW 6670 */ 6671 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6672 6673 /* reg_ricnt_good_multicast_packets 6674 * good multicast packets. 6675 * Access: RW 6676 */ 6677 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6678 6679 /* reg_ricnt_good_broadcast_packets 6680 * good broadcast packets 6681 * Access: RW 6682 */ 6683 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6684 6685 /* reg_ricnt_good_unicast_bytes 6686 * A count of L3 data and padding octets not including L2 headers 6687 * for good unicast frames. 6688 * Access: RW 6689 */ 6690 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6691 6692 /* reg_ricnt_good_multicast_bytes 6693 * A count of L3 data and padding octets not including L2 headers 6694 * for good multicast frames. 6695 * Access: RW 6696 */ 6697 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6698 6699 /* reg_ritr_good_broadcast_bytes 6700 * A count of L3 data and padding octets not including L2 headers 6701 * for good broadcast frames. 6702 * Access: RW 6703 */ 6704 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6705 6706 /* reg_ricnt_error_packets 6707 * A count of errored frames that do not pass the router checks. 6708 * Access: RW 6709 */ 6710 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6711 6712 /* reg_ricnt_discrad_packets 6713 * A count of non-errored frames that do not pass the router checks. 6714 * Access: RW 6715 */ 6716 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6717 6718 /* reg_ricnt_error_bytes 6719 * A count of L3 data and padding octets not including L2 headers 6720 * for errored frames. 6721 * Access: RW 6722 */ 6723 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6724 6725 /* reg_ricnt_discard_bytes 6726 * A count of L3 data and padding octets not including L2 headers 6727 * for non-errored frames that do not pass the router checks. 6728 * Access: RW 6729 */ 6730 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6731 6732 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6733 enum mlxsw_reg_ricnt_opcode op) 6734 { 6735 MLXSW_REG_ZERO(ricnt, payload); 6736 mlxsw_reg_ricnt_op_set(payload, op); 6737 mlxsw_reg_ricnt_counter_index_set(payload, index); 6738 mlxsw_reg_ricnt_counter_set_type_set(payload, 6739 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6740 } 6741 6742 /* RRCR - Router Rules Copy Register Layout 6743 * ---------------------------------------- 6744 * This register is used for moving and copying route entry rules. 6745 */ 6746 #define MLXSW_REG_RRCR_ID 0x800F 6747 #define MLXSW_REG_RRCR_LEN 0x24 6748 6749 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6750 6751 enum mlxsw_reg_rrcr_op { 6752 /* Move rules */ 6753 MLXSW_REG_RRCR_OP_MOVE, 6754 /* Copy rules */ 6755 MLXSW_REG_RRCR_OP_COPY, 6756 }; 6757 6758 /* reg_rrcr_op 6759 * Access: WO 6760 */ 6761 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6762 6763 /* reg_rrcr_offset 6764 * Offset within the region from which to copy/move. 6765 * Access: Index 6766 */ 6767 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6768 6769 /* reg_rrcr_size 6770 * The number of rules to copy/move. 6771 * Access: WO 6772 */ 6773 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6774 6775 /* reg_rrcr_table_id 6776 * Identifier of the table on which to perform the operation. Encoding is the 6777 * same as in RTAR.key_type 6778 * Access: Index 6779 */ 6780 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6781 6782 /* reg_rrcr_dest_offset 6783 * Offset within the region to which to copy/move 6784 * Access: Index 6785 */ 6786 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6787 6788 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6789 u16 offset, u16 size, 6790 enum mlxsw_reg_rtar_key_type table_id, 6791 u16 dest_offset) 6792 { 6793 MLXSW_REG_ZERO(rrcr, payload); 6794 mlxsw_reg_rrcr_op_set(payload, op); 6795 mlxsw_reg_rrcr_offset_set(payload, offset); 6796 mlxsw_reg_rrcr_size_set(payload, size); 6797 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6798 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6799 } 6800 6801 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6802 * ------------------------------------------------------- 6803 * RALTA is used to allocate the LPM trees of the SHSPM method. 6804 */ 6805 #define MLXSW_REG_RALTA_ID 0x8010 6806 #define MLXSW_REG_RALTA_LEN 0x04 6807 6808 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6809 6810 /* reg_ralta_op 6811 * opcode (valid for Write, must be 0 on Read) 6812 * 0 - allocate a tree 6813 * 1 - deallocate a tree 6814 * Access: OP 6815 */ 6816 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6817 6818 enum mlxsw_reg_ralxx_protocol { 6819 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6820 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6821 }; 6822 6823 /* reg_ralta_protocol 6824 * Protocol. 6825 * Deallocation opcode: Reserved. 6826 * Access: RW 6827 */ 6828 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6829 6830 /* reg_ralta_tree_id 6831 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6832 * the tree identifier (managed by software). 6833 * Note that tree_id 0 is allocated for a default-route tree. 6834 * Access: Index 6835 */ 6836 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6837 6838 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6839 enum mlxsw_reg_ralxx_protocol protocol, 6840 u8 tree_id) 6841 { 6842 MLXSW_REG_ZERO(ralta, payload); 6843 mlxsw_reg_ralta_op_set(payload, !alloc); 6844 mlxsw_reg_ralta_protocol_set(payload, protocol); 6845 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6846 } 6847 6848 /* RALST - Router Algorithmic LPM Structure Tree Register 6849 * ------------------------------------------------------ 6850 * RALST is used to set and query the structure of an LPM tree. 6851 * The structure of the tree must be sorted as a sorted binary tree, while 6852 * each node is a bin that is tagged as the length of the prefixes the lookup 6853 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6854 * of X bits to match with the destination address. The bin 0 indicates 6855 * the default action, when there is no match of any prefix. 6856 */ 6857 #define MLXSW_REG_RALST_ID 0x8011 6858 #define MLXSW_REG_RALST_LEN 0x104 6859 6860 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6861 6862 /* reg_ralst_root_bin 6863 * The bin number of the root bin. 6864 * 0<root_bin=<(length of IP address) 6865 * For a default-route tree configure 0xff 6866 * Access: RW 6867 */ 6868 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6869 6870 /* reg_ralst_tree_id 6871 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6872 * Access: Index 6873 */ 6874 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6875 6876 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6877 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6878 #define MLXSW_REG_RALST_BIN_COUNT 128 6879 6880 /* reg_ralst_left_child_bin 6881 * Holding the children of the bin according to the stored tree's structure. 6882 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6883 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6884 * Access: RW 6885 */ 6886 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6887 6888 /* reg_ralst_right_child_bin 6889 * Holding the children of the bin according to the stored tree's structure. 6890 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6891 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6892 * Access: RW 6893 */ 6894 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6895 false); 6896 6897 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6898 { 6899 MLXSW_REG_ZERO(ralst, payload); 6900 6901 /* Initialize all bins to have no left or right child */ 6902 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6903 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6904 6905 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6906 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6907 } 6908 6909 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6910 u8 left_child_bin, 6911 u8 right_child_bin) 6912 { 6913 int bin_index = bin_number - 1; 6914 6915 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6916 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6917 right_child_bin); 6918 } 6919 6920 /* RALTB - Router Algorithmic LPM Tree Binding Register 6921 * ---------------------------------------------------- 6922 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6923 */ 6924 #define MLXSW_REG_RALTB_ID 0x8012 6925 #define MLXSW_REG_RALTB_LEN 0x04 6926 6927 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6928 6929 /* reg_raltb_virtual_router 6930 * Virtual Router ID 6931 * Range is 0..cap_max_virtual_routers-1 6932 * Access: Index 6933 */ 6934 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6935 6936 /* reg_raltb_protocol 6937 * Protocol. 6938 * Access: Index 6939 */ 6940 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6941 6942 /* reg_raltb_tree_id 6943 * Tree to be used for the {virtual_router, protocol} 6944 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6945 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6946 * Access: RW 6947 */ 6948 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6949 6950 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6951 enum mlxsw_reg_ralxx_protocol protocol, 6952 u8 tree_id) 6953 { 6954 MLXSW_REG_ZERO(raltb, payload); 6955 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6956 mlxsw_reg_raltb_protocol_set(payload, protocol); 6957 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6958 } 6959 6960 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6961 * ----------------------------------------------------- 6962 * RALUE is used to configure and query LPM entries that serve 6963 * the Unicast protocols. 6964 */ 6965 #define MLXSW_REG_RALUE_ID 0x8013 6966 #define MLXSW_REG_RALUE_LEN 0x38 6967 6968 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6969 6970 /* reg_ralue_protocol 6971 * Protocol. 6972 * Access: Index 6973 */ 6974 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6975 6976 enum mlxsw_reg_ralue_op { 6977 /* Read operation. If entry doesn't exist, the operation fails. */ 6978 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6979 /* Clear on read operation. Used to read entry and 6980 * clear Activity bit. 6981 */ 6982 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6983 /* Write operation. Used to write a new entry to the table. All RW 6984 * fields are written for new entry. Activity bit is set 6985 * for new entries. 6986 */ 6987 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6988 /* Update operation. Used to update an existing route entry and 6989 * only update the RW fields that are detailed in the field 6990 * op_u_mask. If entry doesn't exist, the operation fails. 6991 */ 6992 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6993 /* Clear activity. The Activity bit (the field a) is cleared 6994 * for the entry. 6995 */ 6996 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6997 /* Delete operation. Used to delete an existing entry. If entry 6998 * doesn't exist, the operation fails. 6999 */ 7000 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7001 }; 7002 7003 /* reg_ralue_op 7004 * Operation. 7005 * Access: OP 7006 */ 7007 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7008 7009 /* reg_ralue_a 7010 * Activity. Set for new entries. Set if a packet lookup has hit on the 7011 * specific entry, only if the entry is a route. To clear the a bit, use 7012 * "clear activity" op. 7013 * Enabled by activity_dis in RGCR 7014 * Access: RO 7015 */ 7016 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7017 7018 /* reg_ralue_virtual_router 7019 * Virtual Router ID 7020 * Range is 0..cap_max_virtual_routers-1 7021 * Access: Index 7022 */ 7023 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7024 7025 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7026 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7027 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7028 7029 /* reg_ralue_op_u_mask 7030 * opcode update mask. 7031 * On read operation, this field is reserved. 7032 * This field is valid for update opcode, otherwise - reserved. 7033 * This field is a bitmask of the fields that should be updated. 7034 * Access: WO 7035 */ 7036 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7037 7038 /* reg_ralue_prefix_len 7039 * Number of bits in the prefix of the LPM route. 7040 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7041 * two entries in the physical HW table. 7042 * Access: Index 7043 */ 7044 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7045 7046 /* reg_ralue_dip* 7047 * The prefix of the route or of the marker that the object of the LPM 7048 * is compared with. The most significant bits of the dip are the prefix. 7049 * The least significant bits must be '0' if the prefix_len is smaller 7050 * than 128 for IPv6 or smaller than 32 for IPv4. 7051 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7052 * Access: Index 7053 */ 7054 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7055 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7056 7057 enum mlxsw_reg_ralue_entry_type { 7058 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7059 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7060 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7061 }; 7062 7063 /* reg_ralue_entry_type 7064 * Entry type. 7065 * Note - for Marker entries, the action_type and action fields are reserved. 7066 * Access: RW 7067 */ 7068 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7069 7070 /* reg_ralue_bmp_len 7071 * The best match prefix length in the case that there is no match for 7072 * longer prefixes. 7073 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7074 * Note for any update operation with entry_type modification this 7075 * field must be set. 7076 * Access: RW 7077 */ 7078 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7079 7080 enum mlxsw_reg_ralue_action_type { 7081 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7082 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7083 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7084 }; 7085 7086 /* reg_ralue_action_type 7087 * Action Type 7088 * Indicates how the IP address is connected. 7089 * It can be connected to a local subnet through local_erif or can be 7090 * on a remote subnet connected through a next-hop router, 7091 * or transmitted to the CPU. 7092 * Reserved when entry_type = MARKER_ENTRY 7093 * Access: RW 7094 */ 7095 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7096 7097 enum mlxsw_reg_ralue_trap_action { 7098 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7099 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7100 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7101 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7102 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7103 }; 7104 7105 /* reg_ralue_trap_action 7106 * Trap action. 7107 * For IP2ME action, only NOP and MIRROR are possible. 7108 * Access: RW 7109 */ 7110 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7111 7112 /* reg_ralue_trap_id 7113 * Trap ID to be reported to CPU. 7114 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7115 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7116 * Access: RW 7117 */ 7118 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7119 7120 /* reg_ralue_adjacency_index 7121 * Points to the first entry of the group-based ECMP. 7122 * Only relevant in case of REMOTE action. 7123 * Access: RW 7124 */ 7125 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7126 7127 /* reg_ralue_ecmp_size 7128 * Amount of sequential entries starting 7129 * from the adjacency_index (the number of ECMPs). 7130 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7131 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7132 * Only relevant in case of REMOTE action. 7133 * Access: RW 7134 */ 7135 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7136 7137 /* reg_ralue_local_erif 7138 * Egress Router Interface. 7139 * Only relevant in case of LOCAL action. 7140 * Access: RW 7141 */ 7142 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7143 7144 /* reg_ralue_ip2me_v 7145 * Valid bit for the tunnel_ptr field. 7146 * If valid = 0 then trap to CPU as IP2ME trap ID. 7147 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7148 * decapsulation then tunnel decapsulation is done. 7149 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7150 * decapsulation then trap as IP2ME trap ID. 7151 * Only relevant in case of IP2ME action. 7152 * Access: RW 7153 */ 7154 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7155 7156 /* reg_ralue_ip2me_tunnel_ptr 7157 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7158 * For Spectrum, pointer to KVD Linear. 7159 * Only relevant in case of IP2ME action. 7160 * Access: RW 7161 */ 7162 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7163 7164 static inline void mlxsw_reg_ralue_pack(char *payload, 7165 enum mlxsw_reg_ralxx_protocol protocol, 7166 enum mlxsw_reg_ralue_op op, 7167 u16 virtual_router, u8 prefix_len) 7168 { 7169 MLXSW_REG_ZERO(ralue, payload); 7170 mlxsw_reg_ralue_protocol_set(payload, protocol); 7171 mlxsw_reg_ralue_op_set(payload, op); 7172 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7173 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7174 mlxsw_reg_ralue_entry_type_set(payload, 7175 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7176 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7177 } 7178 7179 static inline void mlxsw_reg_ralue_pack4(char *payload, 7180 enum mlxsw_reg_ralxx_protocol protocol, 7181 enum mlxsw_reg_ralue_op op, 7182 u16 virtual_router, u8 prefix_len, 7183 u32 dip) 7184 { 7185 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7186 mlxsw_reg_ralue_dip4_set(payload, dip); 7187 } 7188 7189 static inline void mlxsw_reg_ralue_pack6(char *payload, 7190 enum mlxsw_reg_ralxx_protocol protocol, 7191 enum mlxsw_reg_ralue_op op, 7192 u16 virtual_router, u8 prefix_len, 7193 const void *dip) 7194 { 7195 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7196 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7197 } 7198 7199 static inline void 7200 mlxsw_reg_ralue_act_remote_pack(char *payload, 7201 enum mlxsw_reg_ralue_trap_action trap_action, 7202 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7203 { 7204 mlxsw_reg_ralue_action_type_set(payload, 7205 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7206 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7207 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7208 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7209 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7210 } 7211 7212 static inline void 7213 mlxsw_reg_ralue_act_local_pack(char *payload, 7214 enum mlxsw_reg_ralue_trap_action trap_action, 7215 u16 trap_id, u16 local_erif) 7216 { 7217 mlxsw_reg_ralue_action_type_set(payload, 7218 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7219 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7220 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7221 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7222 } 7223 7224 static inline void 7225 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7226 { 7227 mlxsw_reg_ralue_action_type_set(payload, 7228 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7229 } 7230 7231 static inline void 7232 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7233 { 7234 mlxsw_reg_ralue_action_type_set(payload, 7235 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7236 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7237 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7238 } 7239 7240 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7241 * ---------------------------------------------------------- 7242 * The RAUHT register is used to configure and query the Unicast Host table in 7243 * devices that implement the Algorithmic LPM. 7244 */ 7245 #define MLXSW_REG_RAUHT_ID 0x8014 7246 #define MLXSW_REG_RAUHT_LEN 0x74 7247 7248 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7249 7250 enum mlxsw_reg_rauht_type { 7251 MLXSW_REG_RAUHT_TYPE_IPV4, 7252 MLXSW_REG_RAUHT_TYPE_IPV6, 7253 }; 7254 7255 /* reg_rauht_type 7256 * Access: Index 7257 */ 7258 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7259 7260 enum mlxsw_reg_rauht_op { 7261 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7262 /* Read operation */ 7263 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7264 /* Clear on read operation. Used to read entry and clear 7265 * activity bit. 7266 */ 7267 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7268 /* Add. Used to write a new entry to the table. All R/W fields are 7269 * relevant for new entry. Activity bit is set for new entries. 7270 */ 7271 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7272 /* Update action. Used to update an existing route entry and 7273 * only update the following fields: 7274 * trap_action, trap_id, mac, counter_set_type, counter_index 7275 */ 7276 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7277 /* Clear activity. A bit is cleared for the entry. */ 7278 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7279 /* Delete entry */ 7280 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7281 /* Delete all host entries on a RIF. In this command, dip 7282 * field is reserved. 7283 */ 7284 }; 7285 7286 /* reg_rauht_op 7287 * Access: OP 7288 */ 7289 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7290 7291 /* reg_rauht_a 7292 * Activity. Set for new entries. Set if a packet lookup has hit on 7293 * the specific entry. 7294 * To clear the a bit, use "clear activity" op. 7295 * Enabled by activity_dis in RGCR 7296 * Access: RO 7297 */ 7298 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7299 7300 /* reg_rauht_rif 7301 * Router Interface 7302 * Access: Index 7303 */ 7304 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7305 7306 /* reg_rauht_dip* 7307 * Destination address. 7308 * Access: Index 7309 */ 7310 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7311 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7312 7313 enum mlxsw_reg_rauht_trap_action { 7314 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7315 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7316 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7317 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7318 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7319 }; 7320 7321 /* reg_rauht_trap_action 7322 * Access: RW 7323 */ 7324 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7325 7326 enum mlxsw_reg_rauht_trap_id { 7327 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7328 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7329 }; 7330 7331 /* reg_rauht_trap_id 7332 * Trap ID to be reported to CPU. 7333 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7334 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7335 * trap_id is reserved. 7336 * Access: RW 7337 */ 7338 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7339 7340 /* reg_rauht_counter_set_type 7341 * Counter set type for flow counters 7342 * Access: RW 7343 */ 7344 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7345 7346 /* reg_rauht_counter_index 7347 * Counter index for flow counters 7348 * Access: RW 7349 */ 7350 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7351 7352 /* reg_rauht_mac 7353 * MAC address. 7354 * Access: RW 7355 */ 7356 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7357 7358 static inline void mlxsw_reg_rauht_pack(char *payload, 7359 enum mlxsw_reg_rauht_op op, u16 rif, 7360 const char *mac) 7361 { 7362 MLXSW_REG_ZERO(rauht, payload); 7363 mlxsw_reg_rauht_op_set(payload, op); 7364 mlxsw_reg_rauht_rif_set(payload, rif); 7365 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7366 } 7367 7368 static inline void mlxsw_reg_rauht_pack4(char *payload, 7369 enum mlxsw_reg_rauht_op op, u16 rif, 7370 const char *mac, u32 dip) 7371 { 7372 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7373 mlxsw_reg_rauht_dip4_set(payload, dip); 7374 } 7375 7376 static inline void mlxsw_reg_rauht_pack6(char *payload, 7377 enum mlxsw_reg_rauht_op op, u16 rif, 7378 const char *mac, const char *dip) 7379 { 7380 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7381 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7382 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7383 } 7384 7385 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7386 u64 counter_index) 7387 { 7388 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7389 mlxsw_reg_rauht_counter_set_type_set(payload, 7390 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7391 } 7392 7393 /* RALEU - Router Algorithmic LPM ECMP Update Register 7394 * --------------------------------------------------- 7395 * The register enables updating the ECMP section in the action for multiple 7396 * LPM Unicast entries in a single operation. The update is executed to 7397 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7398 */ 7399 #define MLXSW_REG_RALEU_ID 0x8015 7400 #define MLXSW_REG_RALEU_LEN 0x28 7401 7402 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7403 7404 /* reg_raleu_protocol 7405 * Protocol. 7406 * Access: Index 7407 */ 7408 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7409 7410 /* reg_raleu_virtual_router 7411 * Virtual Router ID 7412 * Range is 0..cap_max_virtual_routers-1 7413 * Access: Index 7414 */ 7415 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7416 7417 /* reg_raleu_adjacency_index 7418 * Adjacency Index used for matching on the existing entries. 7419 * Access: Index 7420 */ 7421 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7422 7423 /* reg_raleu_ecmp_size 7424 * ECMP Size used for matching on the existing entries. 7425 * Access: Index 7426 */ 7427 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7428 7429 /* reg_raleu_new_adjacency_index 7430 * New Adjacency Index. 7431 * Access: WO 7432 */ 7433 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7434 7435 /* reg_raleu_new_ecmp_size 7436 * New ECMP Size. 7437 * Access: WO 7438 */ 7439 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7440 7441 static inline void mlxsw_reg_raleu_pack(char *payload, 7442 enum mlxsw_reg_ralxx_protocol protocol, 7443 u16 virtual_router, 7444 u32 adjacency_index, u16 ecmp_size, 7445 u32 new_adjacency_index, 7446 u16 new_ecmp_size) 7447 { 7448 MLXSW_REG_ZERO(raleu, payload); 7449 mlxsw_reg_raleu_protocol_set(payload, protocol); 7450 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7451 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7452 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7453 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7454 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7455 } 7456 7457 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7458 * ---------------------------------------------------------------- 7459 * The RAUHTD register allows dumping entries from the Router Unicast Host 7460 * Table. For a given session an entry is dumped no more than one time. The 7461 * first RAUHTD access after reset is a new session. A session ends when the 7462 * num_rec response is smaller than num_rec request or for IPv4 when the 7463 * num_entries is smaller than 4. The clear activity affect the current session 7464 * or the last session if a new session has not started. 7465 */ 7466 #define MLXSW_REG_RAUHTD_ID 0x8018 7467 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7468 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7469 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7470 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7471 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7472 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7473 7474 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7475 7476 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7477 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7478 7479 /* reg_rauhtd_filter_fields 7480 * if a bit is '0' then the relevant field is ignored and dump is done 7481 * regardless of the field value 7482 * Bit0 - filter by activity: entry_a 7483 * Bit3 - filter by entry rip: entry_rif 7484 * Access: Index 7485 */ 7486 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7487 7488 enum mlxsw_reg_rauhtd_op { 7489 MLXSW_REG_RAUHTD_OP_DUMP, 7490 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7491 }; 7492 7493 /* reg_rauhtd_op 7494 * Access: OP 7495 */ 7496 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7497 7498 /* reg_rauhtd_num_rec 7499 * At request: number of records requested 7500 * At response: number of records dumped 7501 * For IPv4, each record has 4 entries at request and up to 4 entries 7502 * at response 7503 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7504 * Access: Index 7505 */ 7506 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7507 7508 /* reg_rauhtd_entry_a 7509 * Dump only if activity has value of entry_a 7510 * Reserved if filter_fields bit0 is '0' 7511 * Access: Index 7512 */ 7513 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7514 7515 enum mlxsw_reg_rauhtd_type { 7516 MLXSW_REG_RAUHTD_TYPE_IPV4, 7517 MLXSW_REG_RAUHTD_TYPE_IPV6, 7518 }; 7519 7520 /* reg_rauhtd_type 7521 * Dump only if record type is: 7522 * 0 - IPv4 7523 * 1 - IPv6 7524 * Access: Index 7525 */ 7526 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7527 7528 /* reg_rauhtd_entry_rif 7529 * Dump only if RIF has value of entry_rif 7530 * Reserved if filter_fields bit3 is '0' 7531 * Access: Index 7532 */ 7533 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7534 7535 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7536 enum mlxsw_reg_rauhtd_type type) 7537 { 7538 MLXSW_REG_ZERO(rauhtd, payload); 7539 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7540 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7541 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7542 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7543 mlxsw_reg_rauhtd_type_set(payload, type); 7544 } 7545 7546 /* reg_rauhtd_ipv4_rec_num_entries 7547 * Number of valid entries in this record: 7548 * 0 - 1 valid entry 7549 * 1 - 2 valid entries 7550 * 2 - 3 valid entries 7551 * 3 - 4 valid entries 7552 * Access: RO 7553 */ 7554 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7555 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7556 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7557 7558 /* reg_rauhtd_rec_type 7559 * Record type. 7560 * 0 - IPv4 7561 * 1 - IPv6 7562 * Access: RO 7563 */ 7564 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7565 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7566 7567 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7568 7569 /* reg_rauhtd_ipv4_ent_a 7570 * Activity. Set for new entries. Set if a packet lookup has hit on the 7571 * specific entry. 7572 * Access: RO 7573 */ 7574 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7575 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7576 7577 /* reg_rauhtd_ipv4_ent_rif 7578 * Router interface. 7579 * Access: RO 7580 */ 7581 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7582 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7583 7584 /* reg_rauhtd_ipv4_ent_dip 7585 * Destination IPv4 address. 7586 * Access: RO 7587 */ 7588 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7589 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7590 7591 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7592 7593 /* reg_rauhtd_ipv6_ent_a 7594 * Activity. Set for new entries. Set if a packet lookup has hit on the 7595 * specific entry. 7596 * Access: RO 7597 */ 7598 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7599 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7600 7601 /* reg_rauhtd_ipv6_ent_rif 7602 * Router interface. 7603 * Access: RO 7604 */ 7605 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7606 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7607 7608 /* reg_rauhtd_ipv6_ent_dip 7609 * Destination IPv6 address. 7610 * Access: RO 7611 */ 7612 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7613 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7614 7615 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7616 int ent_index, u16 *p_rif, 7617 u32 *p_dip) 7618 { 7619 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7620 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7621 } 7622 7623 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7624 int rec_index, u16 *p_rif, 7625 char *p_dip) 7626 { 7627 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7628 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7629 } 7630 7631 /* RTDP - Routing Tunnel Decap Properties Register 7632 * ----------------------------------------------- 7633 * The RTDP register is used for configuring the tunnel decap properties of NVE 7634 * and IPinIP. 7635 */ 7636 #define MLXSW_REG_RTDP_ID 0x8020 7637 #define MLXSW_REG_RTDP_LEN 0x44 7638 7639 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7640 7641 enum mlxsw_reg_rtdp_type { 7642 MLXSW_REG_RTDP_TYPE_NVE, 7643 MLXSW_REG_RTDP_TYPE_IPIP, 7644 }; 7645 7646 /* reg_rtdp_type 7647 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7648 * Access: RW 7649 */ 7650 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7651 7652 /* reg_rtdp_tunnel_index 7653 * Index to the Decap entry. 7654 * For Spectrum, Index to KVD Linear. 7655 * Access: Index 7656 */ 7657 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7658 7659 /* reg_rtdp_egress_router_interface 7660 * Underlay egress router interface. 7661 * Valid range is from 0 to cap_max_router_interfaces - 1 7662 * Access: RW 7663 */ 7664 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7665 7666 /* IPinIP */ 7667 7668 /* reg_rtdp_ipip_irif 7669 * Ingress Router Interface for the overlay router 7670 * Access: RW 7671 */ 7672 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7673 7674 enum mlxsw_reg_rtdp_ipip_sip_check { 7675 /* No sip checks. */ 7676 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7677 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7678 * equal ipv4_usip. 7679 */ 7680 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7681 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7682 * equal ipv6_usip. 7683 */ 7684 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7685 }; 7686 7687 /* reg_rtdp_ipip_sip_check 7688 * SIP check to perform. If decapsulation failed due to these configurations 7689 * then trap_id is IPIP_DECAP_ERROR. 7690 * Access: RW 7691 */ 7692 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7693 7694 /* If set, allow decapsulation of IPinIP (without GRE). */ 7695 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7696 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7697 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7698 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7699 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7700 7701 /* reg_rtdp_ipip_type_check 7702 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7703 * these configurations then trap_id is IPIP_DECAP_ERROR. 7704 * Access: RW 7705 */ 7706 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7707 7708 /* reg_rtdp_ipip_gre_key_check 7709 * Whether GRE key should be checked. When check is enabled: 7710 * - A packet received as IPinIP (without GRE) will always pass. 7711 * - A packet received as IPinGREinIP without a key will not pass the check. 7712 * - A packet received as IPinGREinIP with a key will pass the check only if the 7713 * key in the packet is equal to expected_gre_key. 7714 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7715 * Access: RW 7716 */ 7717 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7718 7719 /* reg_rtdp_ipip_ipv4_usip 7720 * Underlay IPv4 address for ipv4 source address check. 7721 * Reserved when sip_check is not '1'. 7722 * Access: RW 7723 */ 7724 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7725 7726 /* reg_rtdp_ipip_ipv6_usip_ptr 7727 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7728 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7729 * is to the KVD linear. 7730 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7731 * Access: RW 7732 */ 7733 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7734 7735 /* reg_rtdp_ipip_expected_gre_key 7736 * GRE key for checking. 7737 * Reserved when gre_key_check is '0'. 7738 * Access: RW 7739 */ 7740 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7741 7742 static inline void mlxsw_reg_rtdp_pack(char *payload, 7743 enum mlxsw_reg_rtdp_type type, 7744 u32 tunnel_index) 7745 { 7746 MLXSW_REG_ZERO(rtdp, payload); 7747 mlxsw_reg_rtdp_type_set(payload, type); 7748 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7749 } 7750 7751 static inline void 7752 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7753 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7754 unsigned int type_check, bool gre_key_check, 7755 u32 ipv4_usip, u32 expected_gre_key) 7756 { 7757 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7758 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7759 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7760 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7761 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7762 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7763 } 7764 7765 /* RIGR-V2 - Router Interface Group Register Version 2 7766 * --------------------------------------------------- 7767 * The RIGR_V2 register is used to add, remove and query egress interface list 7768 * of a multicast forwarding entry. 7769 */ 7770 #define MLXSW_REG_RIGR2_ID 0x8023 7771 #define MLXSW_REG_RIGR2_LEN 0xB0 7772 7773 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7774 7775 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7776 7777 /* reg_rigr2_rigr_index 7778 * KVD Linear index. 7779 * Access: Index 7780 */ 7781 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7782 7783 /* reg_rigr2_vnext 7784 * Next RIGR Index is valid. 7785 * Access: RW 7786 */ 7787 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7788 7789 /* reg_rigr2_next_rigr_index 7790 * Next RIGR Index. The index is to the KVD linear. 7791 * Reserved when vnxet = '0'. 7792 * Access: RW 7793 */ 7794 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7795 7796 /* reg_rigr2_vrmid 7797 * RMID Index is valid. 7798 * Access: RW 7799 */ 7800 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7801 7802 /* reg_rigr2_rmid_index 7803 * RMID Index. 7804 * Range 0 .. max_mid - 1 7805 * Reserved when vrmid = '0'. 7806 * The index is to the Port Group Table (PGT) 7807 * Access: RW 7808 */ 7809 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7810 7811 /* reg_rigr2_erif_entry_v 7812 * Egress Router Interface is valid. 7813 * Note that low-entries must be set if high-entries are set. For 7814 * example: if erif_entry[2].v is set then erif_entry[1].v and 7815 * erif_entry[0].v must be set. 7816 * Index can be from 0 to cap_mc_erif_list_entries-1 7817 * Access: RW 7818 */ 7819 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7820 7821 /* reg_rigr2_erif_entry_erif 7822 * Egress Router Interface. 7823 * Valid range is from 0 to cap_max_router_interfaces - 1 7824 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7825 * Access: RW 7826 */ 7827 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7828 7829 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7830 bool vnext, u32 next_rigr_index) 7831 { 7832 MLXSW_REG_ZERO(rigr2, payload); 7833 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7834 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7835 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7836 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7837 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7838 } 7839 7840 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7841 bool v, u16 erif) 7842 { 7843 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7844 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7845 } 7846 7847 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7848 * ------------------------------------------------------ 7849 */ 7850 #define MLXSW_REG_RECR2_ID 0x8025 7851 #define MLXSW_REG_RECR2_LEN 0x38 7852 7853 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7854 7855 /* reg_recr2_pp 7856 * Per-port configuration 7857 * Access: Index 7858 */ 7859 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7860 7861 /* reg_recr2_sh 7862 * Symmetric hash 7863 * Access: RW 7864 */ 7865 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7866 7867 /* reg_recr2_seed 7868 * Seed 7869 * Access: RW 7870 */ 7871 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7872 7873 enum { 7874 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7875 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7876 /* Enable IPv4 fields if packet is TCP or UDP */ 7877 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7878 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7879 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7880 /* Enable IPv6 fields if packet is TCP or UDP */ 7881 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7882 /* Enable TCP/UDP header fields if packet is IPv4 */ 7883 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7884 /* Enable TCP/UDP header fields if packet is IPv6 */ 7885 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7886 }; 7887 7888 /* reg_recr2_outer_header_enables 7889 * Bit mask where each bit enables a specific layer to be included in 7890 * the hash calculation. 7891 * Access: RW 7892 */ 7893 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7894 7895 enum { 7896 /* IPv4 Source IP */ 7897 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7898 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7899 /* IPv4 Destination IP */ 7900 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7901 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7902 /* IP Protocol */ 7903 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7904 /* IPv6 Source IP */ 7905 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7906 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7907 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7908 /* IPv6 Destination IP */ 7909 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7910 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7911 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7912 /* IPv6 Next Header */ 7913 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7914 /* IPv6 Flow Label */ 7915 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7916 /* TCP/UDP Source Port */ 7917 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7918 /* TCP/UDP Destination Port */ 7919 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7920 }; 7921 7922 /* reg_recr2_outer_header_fields_enable 7923 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7924 * Access: RW 7925 */ 7926 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7927 7928 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7929 { 7930 int i; 7931 7932 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7933 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7934 true); 7935 } 7936 7937 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7938 { 7939 int i; 7940 7941 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7942 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7943 true); 7944 } 7945 7946 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7947 { 7948 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7949 7950 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7951 7952 i = MLXSW_REG_RECR2_IPV6_SIP8; 7953 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7954 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7955 true); 7956 } 7957 7958 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7959 { 7960 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7961 7962 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7963 7964 i = MLXSW_REG_RECR2_IPV6_DIP8; 7965 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7966 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7967 true); 7968 } 7969 7970 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7971 { 7972 MLXSW_REG_ZERO(recr2, payload); 7973 mlxsw_reg_recr2_pp_set(payload, false); 7974 mlxsw_reg_recr2_sh_set(payload, true); 7975 mlxsw_reg_recr2_seed_set(payload, seed); 7976 } 7977 7978 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7979 * -------------------------------------------------------------- 7980 * The RMFT_V2 register is used to configure and query the multicast table. 7981 */ 7982 #define MLXSW_REG_RMFT2_ID 0x8027 7983 #define MLXSW_REG_RMFT2_LEN 0x174 7984 7985 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7986 7987 /* reg_rmft2_v 7988 * Valid 7989 * Access: RW 7990 */ 7991 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7992 7993 enum mlxsw_reg_rmft2_type { 7994 MLXSW_REG_RMFT2_TYPE_IPV4, 7995 MLXSW_REG_RMFT2_TYPE_IPV6 7996 }; 7997 7998 /* reg_rmft2_type 7999 * Access: Index 8000 */ 8001 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8002 8003 enum mlxsw_sp_reg_rmft2_op { 8004 /* For Write: 8005 * Write operation. Used to write a new entry to the table. All RW 8006 * fields are relevant for new entry. Activity bit is set for new 8007 * entries - Note write with v (Valid) 0 will delete the entry. 8008 * For Query: 8009 * Read operation 8010 */ 8011 MLXSW_REG_RMFT2_OP_READ_WRITE, 8012 }; 8013 8014 /* reg_rmft2_op 8015 * Operation. 8016 * Access: OP 8017 */ 8018 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8019 8020 /* reg_rmft2_a 8021 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8022 * entry. 8023 * Access: RO 8024 */ 8025 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8026 8027 /* reg_rmft2_offset 8028 * Offset within the multicast forwarding table to write to. 8029 * Access: Index 8030 */ 8031 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8032 8033 /* reg_rmft2_virtual_router 8034 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8035 * Access: RW 8036 */ 8037 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8038 8039 enum mlxsw_reg_rmft2_irif_mask { 8040 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8041 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8042 }; 8043 8044 /* reg_rmft2_irif_mask 8045 * Ingress RIF mask. 8046 * Access: RW 8047 */ 8048 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8049 8050 /* reg_rmft2_irif 8051 * Ingress RIF index. 8052 * Access: RW 8053 */ 8054 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8055 8056 /* reg_rmft2_dip{4,6} 8057 * Destination IPv4/6 address 8058 * Access: RW 8059 */ 8060 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8061 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8062 8063 /* reg_rmft2_dip{4,6}_mask 8064 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8065 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8066 * Access: RW 8067 */ 8068 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8069 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8070 8071 /* reg_rmft2_sip{4,6} 8072 * Source IPv4/6 address 8073 * Access: RW 8074 */ 8075 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8076 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8077 8078 /* reg_rmft2_sip{4,6}_mask 8079 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8080 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8081 * Access: RW 8082 */ 8083 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8084 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8085 8086 /* reg_rmft2_flexible_action_set 8087 * ACL action set. The only supported action types in this field and in any 8088 * action-set pointed from here are as follows: 8089 * 00h: ACTION_NULL 8090 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8091 * 03h: ACTION_TRAP 8092 * 06h: ACTION_QOS 8093 * 08h: ACTION_POLICING_MONITORING 8094 * 10h: ACTION_ROUTER_MC 8095 * Access: RW 8096 */ 8097 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8098 MLXSW_REG_FLEX_ACTION_SET_LEN); 8099 8100 static inline void 8101 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8102 u16 virtual_router, 8103 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8104 const char *flex_action_set) 8105 { 8106 MLXSW_REG_ZERO(rmft2, payload); 8107 mlxsw_reg_rmft2_v_set(payload, v); 8108 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8109 mlxsw_reg_rmft2_offset_set(payload, offset); 8110 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8111 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8112 mlxsw_reg_rmft2_irif_set(payload, irif); 8113 if (flex_action_set) 8114 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8115 flex_action_set); 8116 } 8117 8118 static inline void 8119 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8120 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8121 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8122 const char *flexible_action_set) 8123 { 8124 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8125 irif_mask, irif, flexible_action_set); 8126 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8127 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8128 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8129 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8130 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8131 } 8132 8133 static inline void 8134 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8135 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8136 struct in6_addr dip6, struct in6_addr dip6_mask, 8137 struct in6_addr sip6, struct in6_addr sip6_mask, 8138 const char *flexible_action_set) 8139 { 8140 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8141 irif_mask, irif, flexible_action_set); 8142 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8143 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8144 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8145 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8146 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8147 } 8148 8149 /* MFCR - Management Fan Control Register 8150 * -------------------------------------- 8151 * This register controls the settings of the Fan Speed PWM mechanism. 8152 */ 8153 #define MLXSW_REG_MFCR_ID 0x9001 8154 #define MLXSW_REG_MFCR_LEN 0x08 8155 8156 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8157 8158 enum mlxsw_reg_mfcr_pwm_frequency { 8159 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8160 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8161 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8162 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8163 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8164 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8165 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8166 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8167 }; 8168 8169 /* reg_mfcr_pwm_frequency 8170 * Controls the frequency of the PWM signal. 8171 * Access: RW 8172 */ 8173 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8174 8175 #define MLXSW_MFCR_TACHOS_MAX 10 8176 8177 /* reg_mfcr_tacho_active 8178 * Indicates which of the tachometer is active (bit per tachometer). 8179 * Access: RO 8180 */ 8181 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8182 8183 #define MLXSW_MFCR_PWMS_MAX 5 8184 8185 /* reg_mfcr_pwm_active 8186 * Indicates which of the PWM control is active (bit per PWM). 8187 * Access: RO 8188 */ 8189 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8190 8191 static inline void 8192 mlxsw_reg_mfcr_pack(char *payload, 8193 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8194 { 8195 MLXSW_REG_ZERO(mfcr, payload); 8196 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8197 } 8198 8199 static inline void 8200 mlxsw_reg_mfcr_unpack(char *payload, 8201 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8202 u16 *p_tacho_active, u8 *p_pwm_active) 8203 { 8204 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8205 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8206 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8207 } 8208 8209 /* MFSC - Management Fan Speed Control Register 8210 * -------------------------------------------- 8211 * This register controls the settings of the Fan Speed PWM mechanism. 8212 */ 8213 #define MLXSW_REG_MFSC_ID 0x9002 8214 #define MLXSW_REG_MFSC_LEN 0x08 8215 8216 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8217 8218 /* reg_mfsc_pwm 8219 * Fan pwm to control / monitor. 8220 * Access: Index 8221 */ 8222 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8223 8224 /* reg_mfsc_pwm_duty_cycle 8225 * Controls the duty cycle of the PWM. Value range from 0..255 to 8226 * represent duty cycle of 0%...100%. 8227 * Access: RW 8228 */ 8229 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8230 8231 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8232 u8 pwm_duty_cycle) 8233 { 8234 MLXSW_REG_ZERO(mfsc, payload); 8235 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8236 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8237 } 8238 8239 /* MFSM - Management Fan Speed Measurement 8240 * --------------------------------------- 8241 * This register controls the settings of the Tacho measurements and 8242 * enables reading the Tachometer measurements. 8243 */ 8244 #define MLXSW_REG_MFSM_ID 0x9003 8245 #define MLXSW_REG_MFSM_LEN 0x08 8246 8247 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8248 8249 /* reg_mfsm_tacho 8250 * Fan tachometer index. 8251 * Access: Index 8252 */ 8253 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8254 8255 /* reg_mfsm_rpm 8256 * Fan speed (round per minute). 8257 * Access: RO 8258 */ 8259 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8260 8261 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8262 { 8263 MLXSW_REG_ZERO(mfsm, payload); 8264 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8265 } 8266 8267 /* MFSL - Management Fan Speed Limit Register 8268 * ------------------------------------------ 8269 * The Fan Speed Limit register is used to configure the fan speed 8270 * event / interrupt notification mechanism. Fan speed threshold are 8271 * defined for both under-speed and over-speed. 8272 */ 8273 #define MLXSW_REG_MFSL_ID 0x9004 8274 #define MLXSW_REG_MFSL_LEN 0x0C 8275 8276 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8277 8278 /* reg_mfsl_tacho 8279 * Fan tachometer index. 8280 * Access: Index 8281 */ 8282 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8283 8284 /* reg_mfsl_tach_min 8285 * Tachometer minimum value (minimum RPM). 8286 * Access: RW 8287 */ 8288 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8289 8290 /* reg_mfsl_tach_max 8291 * Tachometer maximum value (maximum RPM). 8292 * Access: RW 8293 */ 8294 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8295 8296 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8297 u16 tach_min, u16 tach_max) 8298 { 8299 MLXSW_REG_ZERO(mfsl, payload); 8300 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8301 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8302 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8303 } 8304 8305 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8306 u16 *p_tach_min, u16 *p_tach_max) 8307 { 8308 if (p_tach_min) 8309 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8310 8311 if (p_tach_max) 8312 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8313 } 8314 8315 /* FORE - Fan Out of Range Event Register 8316 * -------------------------------------- 8317 * This register reports the status of the controlled fans compared to the 8318 * range defined by the MFSL register. 8319 */ 8320 #define MLXSW_REG_FORE_ID 0x9007 8321 #define MLXSW_REG_FORE_LEN 0x0C 8322 8323 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8324 8325 /* fan_under_limit 8326 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8327 * to a single tachometer and indicates the specific tachometer reading is 8328 * below the threshold. 8329 * Access: RO 8330 */ 8331 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8332 8333 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8334 bool *fault) 8335 { 8336 u16 limit; 8337 8338 if (fault) { 8339 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8340 *fault = limit & BIT(tacho); 8341 } 8342 } 8343 8344 /* MTCAP - Management Temperature Capabilities 8345 * ------------------------------------------- 8346 * This register exposes the capabilities of the device and 8347 * system temperature sensing. 8348 */ 8349 #define MLXSW_REG_MTCAP_ID 0x9009 8350 #define MLXSW_REG_MTCAP_LEN 0x08 8351 8352 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8353 8354 /* reg_mtcap_sensor_count 8355 * Number of sensors supported by the device. 8356 * This includes the QSFP module sensors (if exists in the QSFP module). 8357 * Access: RO 8358 */ 8359 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8360 8361 /* MTMP - Management Temperature 8362 * ----------------------------- 8363 * This register controls the settings of the temperature measurements 8364 * and enables reading the temperature measurements. Note that temperature 8365 * is in 0.125 degrees Celsius. 8366 */ 8367 #define MLXSW_REG_MTMP_ID 0x900A 8368 #define MLXSW_REG_MTMP_LEN 0x20 8369 8370 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8371 8372 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8373 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8374 /* reg_mtmp_sensor_index 8375 * Sensors index to access. 8376 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8377 * (module 0 is mapped to sensor_index 64). 8378 * Access: Index 8379 */ 8380 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8381 8382 /* Convert to milli degrees Celsius */ 8383 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8384 ((v_) >= 0) ? ((v_) * 125) : \ 8385 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8386 * 125)); }) 8387 8388 /* reg_mtmp_temperature 8389 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8390 * degrees units. 8391 * Access: RO 8392 */ 8393 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8394 8395 /* reg_mtmp_mte 8396 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8397 * Access: RW 8398 */ 8399 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8400 8401 /* reg_mtmp_mtr 8402 * Max Temperature Reset - clears the value of the max temperature register. 8403 * Access: WO 8404 */ 8405 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8406 8407 /* reg_mtmp_max_temperature 8408 * The highest measured temperature from the sensor. 8409 * When the bit mte is cleared, the field max_temperature is reserved. 8410 * Access: RO 8411 */ 8412 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8413 8414 /* reg_mtmp_tee 8415 * Temperature Event Enable. 8416 * 0 - Do not generate event 8417 * 1 - Generate event 8418 * 2 - Generate single event 8419 * Access: RW 8420 */ 8421 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8422 8423 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8424 8425 /* reg_mtmp_temperature_threshold_hi 8426 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8427 * Access: RW 8428 */ 8429 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8430 8431 /* reg_mtmp_temperature_threshold_lo 8432 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8433 * Access: RW 8434 */ 8435 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8436 8437 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8438 8439 /* reg_mtmp_sensor_name 8440 * Sensor Name 8441 * Access: RO 8442 */ 8443 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8444 8445 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8446 bool max_temp_enable, 8447 bool max_temp_reset) 8448 { 8449 MLXSW_REG_ZERO(mtmp, payload); 8450 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8451 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8452 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8453 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8454 MLXSW_REG_MTMP_THRESH_HI); 8455 } 8456 8457 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8458 int *p_max_temp, char *sensor_name) 8459 { 8460 s16 temp; 8461 8462 if (p_temp) { 8463 temp = mlxsw_reg_mtmp_temperature_get(payload); 8464 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8465 } 8466 if (p_max_temp) { 8467 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8468 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8469 } 8470 if (sensor_name) 8471 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8472 } 8473 8474 /* MTBR - Management Temperature Bulk Register 8475 * ------------------------------------------- 8476 * This register is used for bulk temperature reading. 8477 */ 8478 #define MLXSW_REG_MTBR_ID 0x900F 8479 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8480 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8481 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8482 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8483 MLXSW_REG_MTBR_REC_LEN * \ 8484 MLXSW_REG_MTBR_REC_MAX_COUNT) 8485 8486 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8487 8488 /* reg_mtbr_base_sensor_index 8489 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8490 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8491 * Access: Index 8492 */ 8493 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8494 8495 /* reg_mtbr_num_rec 8496 * Request: Number of records to read 8497 * Response: Number of records read 8498 * See above description for more details. 8499 * Range 1..255 8500 * Access: RW 8501 */ 8502 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8503 8504 /* reg_mtbr_rec_max_temp 8505 * The highest measured temperature from the sensor. 8506 * When the bit mte is cleared, the field max_temperature is reserved. 8507 * Access: RO 8508 */ 8509 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8510 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8511 8512 /* reg_mtbr_rec_temp 8513 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8514 * degrees units. 8515 * Access: RO 8516 */ 8517 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8518 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8519 8520 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8521 u8 num_rec) 8522 { 8523 MLXSW_REG_ZERO(mtbr, payload); 8524 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8525 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8526 } 8527 8528 /* Error codes from temperatute reading */ 8529 enum mlxsw_reg_mtbr_temp_status { 8530 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8531 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8532 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8533 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8534 }; 8535 8536 /* Base index for reading modules temperature */ 8537 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8538 8539 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8540 u16 *p_temp, u16 *p_max_temp) 8541 { 8542 if (p_temp) 8543 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8544 if (p_max_temp) 8545 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8546 } 8547 8548 /* MCIA - Management Cable Info Access 8549 * ----------------------------------- 8550 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8551 */ 8552 8553 #define MLXSW_REG_MCIA_ID 0x9014 8554 #define MLXSW_REG_MCIA_LEN 0x40 8555 8556 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8557 8558 /* reg_mcia_l 8559 * Lock bit. Setting this bit will lock the access to the specific 8560 * cable. Used for updating a full page in a cable EPROM. Any access 8561 * other then subsequence writes will fail while the port is locked. 8562 * Access: RW 8563 */ 8564 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8565 8566 /* reg_mcia_module 8567 * Module number. 8568 * Access: Index 8569 */ 8570 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8571 8572 /* reg_mcia_status 8573 * Module status. 8574 * Access: RO 8575 */ 8576 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8577 8578 /* reg_mcia_i2c_device_address 8579 * I2C device address. 8580 * Access: RW 8581 */ 8582 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8583 8584 /* reg_mcia_page_number 8585 * Page number. 8586 * Access: RW 8587 */ 8588 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8589 8590 /* reg_mcia_device_address 8591 * Device address. 8592 * Access: RW 8593 */ 8594 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8595 8596 /* reg_mcia_size 8597 * Number of bytes to read/write (up to 48 bytes). 8598 * Access: RW 8599 */ 8600 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8601 8602 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8603 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 8604 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8605 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8606 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8607 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8608 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8609 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8610 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 8611 #define MLXSW_REG_MCIA_PAGE0_LO 0 8612 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8613 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 8614 8615 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8616 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8617 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8618 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8619 }; 8620 8621 enum mlxsw_reg_mcia_eeprom_module_info_id { 8622 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8623 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8624 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8625 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8626 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8627 }; 8628 8629 enum mlxsw_reg_mcia_eeprom_module_info { 8630 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8631 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8632 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 8633 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8634 }; 8635 8636 /* reg_mcia_eeprom 8637 * Bytes to read/write. 8638 * Access: RW 8639 */ 8640 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8641 8642 /* This is used to access the optional upper pages (1-3) in the QSFP+ 8643 * memory map. Page 1 is available on offset 256 through 383, page 2 - 8644 * on offset 384 through 511, page 3 - on offset 512 through 639. 8645 */ 8646 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 8647 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 8648 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 8649 8650 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8651 u8 page_number, u16 device_addr, 8652 u8 size, u8 i2c_device_addr) 8653 { 8654 MLXSW_REG_ZERO(mcia, payload); 8655 mlxsw_reg_mcia_module_set(payload, module); 8656 mlxsw_reg_mcia_l_set(payload, lock); 8657 mlxsw_reg_mcia_page_number_set(payload, page_number); 8658 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8659 mlxsw_reg_mcia_size_set(payload, size); 8660 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8661 } 8662 8663 /* MPAT - Monitoring Port Analyzer Table 8664 * ------------------------------------- 8665 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8666 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8667 */ 8668 #define MLXSW_REG_MPAT_ID 0x901A 8669 #define MLXSW_REG_MPAT_LEN 0x78 8670 8671 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8672 8673 /* reg_mpat_pa_id 8674 * Port Analyzer ID. 8675 * Access: Index 8676 */ 8677 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8678 8679 /* reg_mpat_session_id 8680 * Mirror Session ID. 8681 * Used for MIRROR_SESSION<i> trap. 8682 * Access: RW 8683 */ 8684 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 8685 8686 /* reg_mpat_system_port 8687 * A unique port identifier for the final destination of the packet. 8688 * Access: RW 8689 */ 8690 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8691 8692 /* reg_mpat_e 8693 * Enable. Indicating the Port Analyzer is enabled. 8694 * Access: RW 8695 */ 8696 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8697 8698 /* reg_mpat_qos 8699 * Quality Of Service Mode. 8700 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8701 * PCP, DEI, DSCP or VL) are configured. 8702 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8703 * same as in the original packet that has triggered the mirroring. For 8704 * SPAN also the pcp,dei are maintained. 8705 * Access: RW 8706 */ 8707 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8708 8709 /* reg_mpat_be 8710 * Best effort mode. Indicates mirroring traffic should not cause packet 8711 * drop or back pressure, but will discard the mirrored packets. Mirrored 8712 * packets will be forwarded on a best effort manner. 8713 * 0: Do not discard mirrored packets 8714 * 1: Discard mirrored packets if causing congestion 8715 * Access: RW 8716 */ 8717 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8718 8719 enum mlxsw_reg_mpat_span_type { 8720 /* Local SPAN Ethernet. 8721 * The original packet is not encapsulated. 8722 */ 8723 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8724 8725 /* Remote SPAN Ethernet VLAN. 8726 * The packet is forwarded to the monitoring port on the monitoring 8727 * VLAN. 8728 */ 8729 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8730 8731 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8732 * The packet is encapsulated with GRE header. 8733 */ 8734 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8735 }; 8736 8737 /* reg_mpat_span_type 8738 * SPAN type. 8739 * Access: RW 8740 */ 8741 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8742 8743 /* reg_mpat_pide 8744 * Policer enable. 8745 * Access: RW 8746 */ 8747 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 8748 8749 /* reg_mpat_pid 8750 * Policer ID. 8751 * Access: RW 8752 */ 8753 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 8754 8755 /* Remote SPAN - Ethernet VLAN 8756 * - - - - - - - - - - - - - - 8757 */ 8758 8759 /* reg_mpat_eth_rspan_vid 8760 * Encapsulation header VLAN ID. 8761 * Access: RW 8762 */ 8763 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8764 8765 /* Encapsulated Remote SPAN - Ethernet L2 8766 * - - - - - - - - - - - - - - - - - - - 8767 */ 8768 8769 enum mlxsw_reg_mpat_eth_rspan_version { 8770 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8771 }; 8772 8773 /* reg_mpat_eth_rspan_version 8774 * RSPAN mirror header version. 8775 * Access: RW 8776 */ 8777 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8778 8779 /* reg_mpat_eth_rspan_mac 8780 * Destination MAC address. 8781 * Access: RW 8782 */ 8783 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8784 8785 /* reg_mpat_eth_rspan_tp 8786 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8787 * Access: RW 8788 */ 8789 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8790 8791 /* Encapsulated Remote SPAN - Ethernet L3 8792 * - - - - - - - - - - - - - - - - - - - 8793 */ 8794 8795 enum mlxsw_reg_mpat_eth_rspan_protocol { 8796 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8797 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8798 }; 8799 8800 /* reg_mpat_eth_rspan_protocol 8801 * SPAN encapsulation protocol. 8802 * Access: RW 8803 */ 8804 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8805 8806 /* reg_mpat_eth_rspan_ttl 8807 * Encapsulation header Time-to-Live/HopLimit. 8808 * Access: RW 8809 */ 8810 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8811 8812 /* reg_mpat_eth_rspan_smac 8813 * Source MAC address 8814 * Access: RW 8815 */ 8816 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8817 8818 /* reg_mpat_eth_rspan_dip* 8819 * Destination IP address. The IP version is configured by protocol. 8820 * Access: RW 8821 */ 8822 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8823 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8824 8825 /* reg_mpat_eth_rspan_sip* 8826 * Source IP address. The IP version is configured by protocol. 8827 * Access: RW 8828 */ 8829 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8830 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8831 8832 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8833 u16 system_port, bool e, 8834 enum mlxsw_reg_mpat_span_type span_type) 8835 { 8836 MLXSW_REG_ZERO(mpat, payload); 8837 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8838 mlxsw_reg_mpat_system_port_set(payload, system_port); 8839 mlxsw_reg_mpat_e_set(payload, e); 8840 mlxsw_reg_mpat_qos_set(payload, 1); 8841 mlxsw_reg_mpat_be_set(payload, 1); 8842 mlxsw_reg_mpat_span_type_set(payload, span_type); 8843 } 8844 8845 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8846 { 8847 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8848 } 8849 8850 static inline void 8851 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8852 enum mlxsw_reg_mpat_eth_rspan_version version, 8853 const char *mac, 8854 bool tp) 8855 { 8856 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8857 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8858 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8859 } 8860 8861 static inline void 8862 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8863 const char *smac, 8864 u32 sip, u32 dip) 8865 { 8866 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8867 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8868 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8869 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8870 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8871 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8872 } 8873 8874 static inline void 8875 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8876 const char *smac, 8877 struct in6_addr sip, struct in6_addr dip) 8878 { 8879 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8880 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8881 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8882 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8883 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8884 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8885 } 8886 8887 /* MPAR - Monitoring Port Analyzer Register 8888 * ---------------------------------------- 8889 * MPAR register is used to query and configure the port analyzer port mirroring 8890 * properties. 8891 */ 8892 #define MLXSW_REG_MPAR_ID 0x901B 8893 #define MLXSW_REG_MPAR_LEN 0x0C 8894 8895 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8896 8897 /* reg_mpar_local_port 8898 * The local port to mirror the packets from. 8899 * Access: Index 8900 */ 8901 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8902 8903 enum mlxsw_reg_mpar_i_e { 8904 MLXSW_REG_MPAR_TYPE_EGRESS, 8905 MLXSW_REG_MPAR_TYPE_INGRESS, 8906 }; 8907 8908 /* reg_mpar_i_e 8909 * Ingress/Egress 8910 * Access: Index 8911 */ 8912 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8913 8914 /* reg_mpar_enable 8915 * Enable mirroring 8916 * By default, port mirroring is disabled for all ports. 8917 * Access: RW 8918 */ 8919 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8920 8921 /* reg_mpar_pa_id 8922 * Port Analyzer ID. 8923 * Access: RW 8924 */ 8925 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8926 8927 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8928 enum mlxsw_reg_mpar_i_e i_e, 8929 bool enable, u8 pa_id) 8930 { 8931 MLXSW_REG_ZERO(mpar, payload); 8932 mlxsw_reg_mpar_local_port_set(payload, local_port); 8933 mlxsw_reg_mpar_enable_set(payload, enable); 8934 mlxsw_reg_mpar_i_e_set(payload, i_e); 8935 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8936 } 8937 8938 /* MGIR - Management General Information Register 8939 * ---------------------------------------------- 8940 * MGIR register allows software to query the hardware and firmware general 8941 * information. 8942 */ 8943 #define MLXSW_REG_MGIR_ID 0x9020 8944 #define MLXSW_REG_MGIR_LEN 0x9C 8945 8946 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 8947 8948 /* reg_mgir_hw_info_device_hw_revision 8949 * Access: RO 8950 */ 8951 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 8952 8953 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 8954 8955 /* reg_mgir_fw_info_psid 8956 * PSID (ASCII string). 8957 * Access: RO 8958 */ 8959 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 8960 8961 /* reg_mgir_fw_info_extended_major 8962 * Access: RO 8963 */ 8964 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 8965 8966 /* reg_mgir_fw_info_extended_minor 8967 * Access: RO 8968 */ 8969 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 8970 8971 /* reg_mgir_fw_info_extended_sub_minor 8972 * Access: RO 8973 */ 8974 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 8975 8976 static inline void mlxsw_reg_mgir_pack(char *payload) 8977 { 8978 MLXSW_REG_ZERO(mgir, payload); 8979 } 8980 8981 static inline void 8982 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 8983 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 8984 { 8985 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 8986 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 8987 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 8988 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 8989 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 8990 } 8991 8992 /* MRSR - Management Reset and Shutdown Register 8993 * --------------------------------------------- 8994 * MRSR register is used to reset or shutdown the switch or 8995 * the entire system (when applicable). 8996 */ 8997 #define MLXSW_REG_MRSR_ID 0x9023 8998 #define MLXSW_REG_MRSR_LEN 0x08 8999 9000 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 9001 9002 /* reg_mrsr_command 9003 * Reset/shutdown command 9004 * 0 - do nothing 9005 * 1 - software reset 9006 * Access: WO 9007 */ 9008 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 9009 9010 static inline void mlxsw_reg_mrsr_pack(char *payload) 9011 { 9012 MLXSW_REG_ZERO(mrsr, payload); 9013 mlxsw_reg_mrsr_command_set(payload, 1); 9014 } 9015 9016 /* MLCR - Management LED Control Register 9017 * -------------------------------------- 9018 * Controls the system LEDs. 9019 */ 9020 #define MLXSW_REG_MLCR_ID 0x902B 9021 #define MLXSW_REG_MLCR_LEN 0x0C 9022 9023 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 9024 9025 /* reg_mlcr_local_port 9026 * Local port number. 9027 * Access: RW 9028 */ 9029 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 9030 9031 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 9032 9033 /* reg_mlcr_beacon_duration 9034 * Duration of the beacon to be active, in seconds. 9035 * 0x0 - Will turn off the beacon. 9036 * 0xFFFF - Will turn on the beacon until explicitly turned off. 9037 * Access: RW 9038 */ 9039 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 9040 9041 /* reg_mlcr_beacon_remain 9042 * Remaining duration of the beacon, in seconds. 9043 * 0xFFFF indicates an infinite amount of time. 9044 * Access: RO 9045 */ 9046 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 9047 9048 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 9049 bool active) 9050 { 9051 MLXSW_REG_ZERO(mlcr, payload); 9052 mlxsw_reg_mlcr_local_port_set(payload, local_port); 9053 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 9054 MLXSW_REG_MLCR_DURATION_MAX : 0); 9055 } 9056 9057 /* MTPPS - Management Pulse Per Second Register 9058 * -------------------------------------------- 9059 * This register provides the device PPS capabilities, configure the PPS in and 9060 * out modules and holds the PPS in time stamp. 9061 */ 9062 #define MLXSW_REG_MTPPS_ID 0x9053 9063 #define MLXSW_REG_MTPPS_LEN 0x3C 9064 9065 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 9066 9067 /* reg_mtpps_enable 9068 * Enables the PPS functionality the specific pin. 9069 * A boolean variable. 9070 * Access: RW 9071 */ 9072 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 9073 9074 enum mlxsw_reg_mtpps_pin_mode { 9075 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 9076 }; 9077 9078 /* reg_mtpps_pin_mode 9079 * Pin mode to be used. The mode must comply with the supported modes of the 9080 * requested pin. 9081 * Access: RW 9082 */ 9083 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 9084 9085 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 9086 9087 /* reg_mtpps_pin 9088 * Pin to be configured or queried out of the supported pins. 9089 * Access: Index 9090 */ 9091 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 9092 9093 /* reg_mtpps_time_stamp 9094 * When pin_mode = pps_in, the latched device time when it was triggered from 9095 * the external GPIO pin. 9096 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 9097 * time to generate next output signal. 9098 * Time is in units of device clock. 9099 * Access: RW 9100 */ 9101 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 9102 9103 static inline void 9104 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 9105 { 9106 MLXSW_REG_ZERO(mtpps, payload); 9107 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 9108 mlxsw_reg_mtpps_pin_mode_set(payload, 9109 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 9110 mlxsw_reg_mtpps_enable_set(payload, true); 9111 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 9112 } 9113 9114 /* MTUTC - Management UTC Register 9115 * ------------------------------- 9116 * Configures the HW UTC counter. 9117 */ 9118 #define MLXSW_REG_MTUTC_ID 0x9055 9119 #define MLXSW_REG_MTUTC_LEN 0x1C 9120 9121 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 9122 9123 enum mlxsw_reg_mtutc_operation { 9124 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 9125 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 9126 }; 9127 9128 /* reg_mtutc_operation 9129 * Operation. 9130 * Access: OP 9131 */ 9132 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 9133 9134 /* reg_mtutc_freq_adjustment 9135 * Frequency adjustment: Every PPS the HW frequency will be 9136 * adjusted by this value. Units of HW clock, where HW counts 9137 * 10^9 HW clocks for 1 HW second. 9138 * Access: RW 9139 */ 9140 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 9141 9142 /* reg_mtutc_utc_sec 9143 * UTC seconds. 9144 * Access: WO 9145 */ 9146 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 9147 9148 static inline void 9149 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 9150 u32 freq_adj, u32 utc_sec) 9151 { 9152 MLXSW_REG_ZERO(mtutc, payload); 9153 mlxsw_reg_mtutc_operation_set(payload, oper); 9154 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 9155 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 9156 } 9157 9158 /* MCQI - Management Component Query Information 9159 * --------------------------------------------- 9160 * This register allows querying information about firmware components. 9161 */ 9162 #define MLXSW_REG_MCQI_ID 0x9061 9163 #define MLXSW_REG_MCQI_BASE_LEN 0x18 9164 #define MLXSW_REG_MCQI_CAP_LEN 0x14 9165 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9166 9167 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9168 9169 /* reg_mcqi_component_index 9170 * Index of the accessed component. 9171 * Access: Index 9172 */ 9173 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9174 9175 enum mlxfw_reg_mcqi_info_type { 9176 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9177 }; 9178 9179 /* reg_mcqi_info_type 9180 * Component properties set. 9181 * Access: RW 9182 */ 9183 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9184 9185 /* reg_mcqi_offset 9186 * The requested/returned data offset from the section start, given in bytes. 9187 * Must be DWORD aligned. 9188 * Access: RW 9189 */ 9190 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9191 9192 /* reg_mcqi_data_size 9193 * The requested/returned data size, given in bytes. If data_size is not DWORD 9194 * aligned, the last bytes are zero padded. 9195 * Access: RW 9196 */ 9197 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9198 9199 /* reg_mcqi_cap_max_component_size 9200 * Maximum size for this component, given in bytes. 9201 * Access: RO 9202 */ 9203 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9204 9205 /* reg_mcqi_cap_log_mcda_word_size 9206 * Log 2 of the access word size in bytes. Read and write access must be aligned 9207 * to the word size. Write access must be done for an integer number of words. 9208 * Access: RO 9209 */ 9210 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9211 9212 /* reg_mcqi_cap_mcda_max_write_size 9213 * Maximal write size for MCDA register 9214 * Access: RO 9215 */ 9216 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9217 9218 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9219 { 9220 MLXSW_REG_ZERO(mcqi, payload); 9221 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9222 mlxsw_reg_mcqi_info_type_set(payload, 9223 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9224 mlxsw_reg_mcqi_offset_set(payload, 0); 9225 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9226 } 9227 9228 static inline void mlxsw_reg_mcqi_unpack(char *payload, 9229 u32 *p_cap_max_component_size, 9230 u8 *p_cap_log_mcda_word_size, 9231 u16 *p_cap_mcda_max_write_size) 9232 { 9233 *p_cap_max_component_size = 9234 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9235 *p_cap_log_mcda_word_size = 9236 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9237 *p_cap_mcda_max_write_size = 9238 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9239 } 9240 9241 /* MCC - Management Component Control 9242 * ---------------------------------- 9243 * Controls the firmware component and updates the FSM. 9244 */ 9245 #define MLXSW_REG_MCC_ID 0x9062 9246 #define MLXSW_REG_MCC_LEN 0x1C 9247 9248 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9249 9250 enum mlxsw_reg_mcc_instruction { 9251 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9252 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9253 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9254 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9255 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9256 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9257 }; 9258 9259 /* reg_mcc_instruction 9260 * Command to be executed by the FSM. 9261 * Applicable for write operation only. 9262 * Access: RW 9263 */ 9264 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9265 9266 /* reg_mcc_component_index 9267 * Index of the accessed component. Applicable only for commands that 9268 * refer to components. Otherwise, this field is reserved. 9269 * Access: Index 9270 */ 9271 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9272 9273 /* reg_mcc_update_handle 9274 * Token representing the current flow executed by the FSM. 9275 * Access: WO 9276 */ 9277 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9278 9279 /* reg_mcc_error_code 9280 * Indicates the successful completion of the instruction, or the reason it 9281 * failed 9282 * Access: RO 9283 */ 9284 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9285 9286 /* reg_mcc_control_state 9287 * Current FSM state 9288 * Access: RO 9289 */ 9290 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9291 9292 /* reg_mcc_component_size 9293 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9294 * the size may shorten the update time. Value 0x0 means that size is 9295 * unspecified. 9296 * Access: WO 9297 */ 9298 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9299 9300 static inline void mlxsw_reg_mcc_pack(char *payload, 9301 enum mlxsw_reg_mcc_instruction instr, 9302 u16 component_index, u32 update_handle, 9303 u32 component_size) 9304 { 9305 MLXSW_REG_ZERO(mcc, payload); 9306 mlxsw_reg_mcc_instruction_set(payload, instr); 9307 mlxsw_reg_mcc_component_index_set(payload, component_index); 9308 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9309 mlxsw_reg_mcc_component_size_set(payload, component_size); 9310 } 9311 9312 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9313 u8 *p_error_code, u8 *p_control_state) 9314 { 9315 if (p_update_handle) 9316 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9317 if (p_error_code) 9318 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9319 if (p_control_state) 9320 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9321 } 9322 9323 /* MCDA - Management Component Data Access 9324 * --------------------------------------- 9325 * This register allows reading and writing a firmware component. 9326 */ 9327 #define MLXSW_REG_MCDA_ID 0x9063 9328 #define MLXSW_REG_MCDA_BASE_LEN 0x10 9329 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9330 #define MLXSW_REG_MCDA_LEN \ 9331 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9332 9333 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9334 9335 /* reg_mcda_update_handle 9336 * Token representing the current flow executed by the FSM. 9337 * Access: RW 9338 */ 9339 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9340 9341 /* reg_mcda_offset 9342 * Offset of accessed address relative to component start. Accesses must be in 9343 * accordance to log_mcda_word_size in MCQI reg. 9344 * Access: RW 9345 */ 9346 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9347 9348 /* reg_mcda_size 9349 * Size of the data accessed, given in bytes. 9350 * Access: RW 9351 */ 9352 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9353 9354 /* reg_mcda_data 9355 * Data block accessed. 9356 * Access: RW 9357 */ 9358 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9359 9360 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9361 u32 offset, u16 size, u8 *data) 9362 { 9363 int i; 9364 9365 MLXSW_REG_ZERO(mcda, payload); 9366 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9367 mlxsw_reg_mcda_offset_set(payload, offset); 9368 mlxsw_reg_mcda_size_set(payload, size); 9369 9370 for (i = 0; i < size / 4; i++) 9371 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9372 } 9373 9374 /* MPSC - Monitoring Packet Sampling Configuration Register 9375 * -------------------------------------------------------- 9376 * MPSC Register is used to configure the Packet Sampling mechanism. 9377 */ 9378 #define MLXSW_REG_MPSC_ID 0x9080 9379 #define MLXSW_REG_MPSC_LEN 0x1C 9380 9381 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9382 9383 /* reg_mpsc_local_port 9384 * Local port number 9385 * Not supported for CPU port 9386 * Access: Index 9387 */ 9388 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9389 9390 /* reg_mpsc_e 9391 * Enable sampling on port local_port 9392 * Access: RW 9393 */ 9394 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9395 9396 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9397 9398 /* reg_mpsc_rate 9399 * Sampling rate = 1 out of rate packets (with randomization around 9400 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9401 * Access: RW 9402 */ 9403 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9404 9405 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9406 u32 rate) 9407 { 9408 MLXSW_REG_ZERO(mpsc, payload); 9409 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9410 mlxsw_reg_mpsc_e_set(payload, e); 9411 mlxsw_reg_mpsc_rate_set(payload, rate); 9412 } 9413 9414 /* MGPC - Monitoring General Purpose Counter Set Register 9415 * The MGPC register retrieves and sets the General Purpose Counter Set. 9416 */ 9417 #define MLXSW_REG_MGPC_ID 0x9081 9418 #define MLXSW_REG_MGPC_LEN 0x18 9419 9420 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9421 9422 /* reg_mgpc_counter_set_type 9423 * Counter set type. 9424 * Access: OP 9425 */ 9426 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9427 9428 /* reg_mgpc_counter_index 9429 * Counter index. 9430 * Access: Index 9431 */ 9432 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9433 9434 enum mlxsw_reg_mgpc_opcode { 9435 /* Nop */ 9436 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9437 /* Clear counters */ 9438 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9439 }; 9440 9441 /* reg_mgpc_opcode 9442 * Opcode. 9443 * Access: OP 9444 */ 9445 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9446 9447 /* reg_mgpc_byte_counter 9448 * Byte counter value. 9449 * Access: RW 9450 */ 9451 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9452 9453 /* reg_mgpc_packet_counter 9454 * Packet counter value. 9455 * Access: RW 9456 */ 9457 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9458 9459 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9460 enum mlxsw_reg_mgpc_opcode opcode, 9461 enum mlxsw_reg_flow_counter_set_type set_type) 9462 { 9463 MLXSW_REG_ZERO(mgpc, payload); 9464 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9465 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9466 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9467 } 9468 9469 /* MPRS - Monitoring Parsing State Register 9470 * ---------------------------------------- 9471 * The MPRS register is used for setting up the parsing for hash, 9472 * policy-engine and routing. 9473 */ 9474 #define MLXSW_REG_MPRS_ID 0x9083 9475 #define MLXSW_REG_MPRS_LEN 0x14 9476 9477 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9478 9479 /* reg_mprs_parsing_depth 9480 * Minimum parsing depth. 9481 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9482 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9483 * Access: RW 9484 */ 9485 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9486 9487 /* reg_mprs_parsing_en 9488 * Parsing enable. 9489 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9490 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9491 * Access: RW 9492 */ 9493 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9494 9495 /* reg_mprs_vxlan_udp_dport 9496 * VxLAN UDP destination port. 9497 * Used for identifying VxLAN packets and for dport field in 9498 * encapsulation. Default is 4789. 9499 * Access: RW 9500 */ 9501 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9502 9503 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9504 u16 vxlan_udp_dport) 9505 { 9506 MLXSW_REG_ZERO(mprs, payload); 9507 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9508 mlxsw_reg_mprs_parsing_en_set(payload, true); 9509 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9510 } 9511 9512 /* MOGCR - Monitoring Global Configuration Register 9513 * ------------------------------------------------ 9514 */ 9515 #define MLXSW_REG_MOGCR_ID 0x9086 9516 #define MLXSW_REG_MOGCR_LEN 0x20 9517 9518 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9519 9520 /* reg_mogcr_ptp_iftc 9521 * PTP Ingress FIFO Trap Clear 9522 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9523 * to this value. Default 0. 9524 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9525 * Access: RW 9526 */ 9527 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9528 9529 /* reg_mogcr_ptp_eftc 9530 * PTP Egress FIFO Trap Clear 9531 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9532 * to this value. Default 0. 9533 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9534 * Access: RW 9535 */ 9536 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9537 9538 /* reg_mogcr_mirroring_pid_base 9539 * Base policer id for mirroring policers. 9540 * Must have an even value (e.g. 1000, not 1001). 9541 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 9542 * Access: RW 9543 */ 9544 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 9545 9546 /* MPAGR - Monitoring Port Analyzer Global Register 9547 * ------------------------------------------------ 9548 * This register is used for global port analyzer configurations. 9549 * Note: This register is not supported by current FW versions for Spectrum-1. 9550 */ 9551 #define MLXSW_REG_MPAGR_ID 0x9089 9552 #define MLXSW_REG_MPAGR_LEN 0x0C 9553 9554 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 9555 9556 enum mlxsw_reg_mpagr_trigger { 9557 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 9558 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 9559 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 9560 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 9561 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 9562 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 9563 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 9564 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 9565 }; 9566 9567 /* reg_mpagr_trigger 9568 * Mirror trigger. 9569 * Access: Index 9570 */ 9571 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 9572 9573 /* reg_mpagr_pa_id 9574 * Port analyzer ID. 9575 * Access: RW 9576 */ 9577 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 9578 9579 /* reg_mpagr_probability_rate 9580 * Sampling rate. 9581 * Valid values are: 1 to 3.5*10^9 9582 * Value of 1 means "sample all". Default is 1. 9583 * Access: RW 9584 */ 9585 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 9586 9587 static inline void mlxsw_reg_mpagr_pack(char *payload, 9588 enum mlxsw_reg_mpagr_trigger trigger, 9589 u8 pa_id, u32 probability_rate) 9590 { 9591 MLXSW_REG_ZERO(mpagr, payload); 9592 mlxsw_reg_mpagr_trigger_set(payload, trigger); 9593 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 9594 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 9595 } 9596 9597 /* MOMTE - Monitoring Mirror Trigger Enable Register 9598 * ------------------------------------------------- 9599 * This register is used to configure the mirror enable for different mirror 9600 * reasons. 9601 */ 9602 #define MLXSW_REG_MOMTE_ID 0x908D 9603 #define MLXSW_REG_MOMTE_LEN 0x10 9604 9605 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 9606 9607 /* reg_momte_local_port 9608 * Local port number. 9609 * Access: Index 9610 */ 9611 MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8); 9612 9613 enum mlxsw_reg_momte_type { 9614 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 9615 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 9616 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 9617 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 9618 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 9619 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 9620 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 9621 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 9622 }; 9623 9624 /* reg_momte_type 9625 * Type of mirroring. 9626 * Access: Index 9627 */ 9628 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 9629 9630 /* reg_momte_tclass_en 9631 * TClass/PG mirror enable. Each bit represents corresponding tclass. 9632 * 0: disable (default) 9633 * 1: enable 9634 * Access: RW 9635 */ 9636 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 9637 9638 static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port, 9639 enum mlxsw_reg_momte_type type) 9640 { 9641 MLXSW_REG_ZERO(momte, payload); 9642 mlxsw_reg_momte_local_port_set(payload, local_port); 9643 mlxsw_reg_momte_type_set(payload, type); 9644 } 9645 9646 /* MTPPPC - Time Precision Packet Port Configuration 9647 * ------------------------------------------------- 9648 * This register serves for configuration of which PTP messages should be 9649 * timestamped. This is a global configuration, despite the register name. 9650 * 9651 * Reserved when Spectrum-2. 9652 */ 9653 #define MLXSW_REG_MTPPPC_ID 0x9090 9654 #define MLXSW_REG_MTPPPC_LEN 0x28 9655 9656 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 9657 9658 /* reg_mtpppc_ing_timestamp_message_type 9659 * Bitwise vector of PTP message types to timestamp at ingress. 9660 * MessageType field as defined by IEEE 1588 9661 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9662 * Default all 0 9663 * Access: RW 9664 */ 9665 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 9666 9667 /* reg_mtpppc_egr_timestamp_message_type 9668 * Bitwise vector of PTP message types to timestamp at egress. 9669 * MessageType field as defined by IEEE 1588 9670 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9671 * Default all 0 9672 * Access: RW 9673 */ 9674 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 9675 9676 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 9677 { 9678 MLXSW_REG_ZERO(mtpppc, payload); 9679 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 9680 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 9681 } 9682 9683 /* MTPPTR - Time Precision Packet Timestamping Reading 9684 * --------------------------------------------------- 9685 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 9686 * There is a trap for packets which are latched to the timestamp FIFO, thus the 9687 * SW knows which FIFO to read. Note that packets enter the FIFO before been 9688 * trapped. The sequence number is used to synchronize the timestamp FIFO 9689 * entries and the trapped packets. 9690 * Reserved when Spectrum-2. 9691 */ 9692 9693 #define MLXSW_REG_MTPPTR_ID 0x9091 9694 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 9695 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 9696 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 9697 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 9698 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 9699 9700 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 9701 9702 /* reg_mtpptr_local_port 9703 * Not supported for CPU port. 9704 * Access: Index 9705 */ 9706 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 9707 9708 enum mlxsw_reg_mtpptr_dir { 9709 MLXSW_REG_MTPPTR_DIR_INGRESS, 9710 MLXSW_REG_MTPPTR_DIR_EGRESS, 9711 }; 9712 9713 /* reg_mtpptr_dir 9714 * Direction. 9715 * Access: Index 9716 */ 9717 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 9718 9719 /* reg_mtpptr_clr 9720 * Clear the records. 9721 * Access: OP 9722 */ 9723 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 9724 9725 /* reg_mtpptr_num_rec 9726 * Number of valid records in the response 9727 * Range 0.. cap_ptp_timestamp_fifo 9728 * Access: RO 9729 */ 9730 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 9731 9732 /* reg_mtpptr_rec_message_type 9733 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 9734 * (e.g. Bit0: Sync, Bit1: Delay_Req) 9735 * Access: RO 9736 */ 9737 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 9738 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 9739 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9740 9741 /* reg_mtpptr_rec_domain_number 9742 * DomainNumber field as defined by IEEE 1588 9743 * Access: RO 9744 */ 9745 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 9746 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 9747 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9748 9749 /* reg_mtpptr_rec_sequence_id 9750 * SequenceId field as defined by IEEE 1588 9751 * Access: RO 9752 */ 9753 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 9754 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 9755 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 9756 9757 /* reg_mtpptr_rec_timestamp_high 9758 * Timestamp of when the PTP packet has passed through the port Units of PLL 9759 * clock time. 9760 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 9761 * Access: RO 9762 */ 9763 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 9764 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9765 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 9766 9767 /* reg_mtpptr_rec_timestamp_low 9768 * See rec_timestamp_high. 9769 * Access: RO 9770 */ 9771 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 9772 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9773 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 9774 9775 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 9776 unsigned int rec, 9777 u8 *p_message_type, 9778 u8 *p_domain_number, 9779 u16 *p_sequence_id, 9780 u64 *p_timestamp) 9781 { 9782 u32 timestamp_high, timestamp_low; 9783 9784 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 9785 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 9786 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 9787 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 9788 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 9789 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 9790 } 9791 9792 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 9793 * --------------------------------------------------------- 9794 * This register is used for configuring under which trap to deliver PTP 9795 * packets depending on type of the packet. 9796 */ 9797 #define MLXSW_REG_MTPTPT_ID 0x9092 9798 #define MLXSW_REG_MTPTPT_LEN 0x08 9799 9800 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 9801 9802 enum mlxsw_reg_mtptpt_trap_id { 9803 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 9804 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 9805 }; 9806 9807 /* reg_mtptpt_trap_id 9808 * Trap id. 9809 * Access: Index 9810 */ 9811 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 9812 9813 /* reg_mtptpt_message_type 9814 * Bitwise vector of PTP message types to trap. This is a necessary but 9815 * non-sufficient condition since need to enable also per port. See MTPPPC. 9816 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 9817 * Bit0: Sync, Bit1: Delay_Req) 9818 */ 9819 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 9820 9821 static inline void mlxsw_reg_mtptptp_pack(char *payload, 9822 enum mlxsw_reg_mtptpt_trap_id trap_id, 9823 u16 message_type) 9824 { 9825 MLXSW_REG_ZERO(mtptpt, payload); 9826 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 9827 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 9828 } 9829 9830 /* MGPIR - Management General Peripheral Information Register 9831 * ---------------------------------------------------------- 9832 * MGPIR register allows software to query the hardware and 9833 * firmware general information of peripheral entities. 9834 */ 9835 #define MLXSW_REG_MGPIR_ID 0x9100 9836 #define MLXSW_REG_MGPIR_LEN 0xA0 9837 9838 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 9839 9840 enum mlxsw_reg_mgpir_device_type { 9841 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 9842 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 9843 }; 9844 9845 /* device_type 9846 * Access: RO 9847 */ 9848 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 9849 9850 /* devices_per_flash 9851 * Number of devices of device_type per flash (can be shared by few devices). 9852 * Access: RO 9853 */ 9854 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 9855 9856 /* num_of_devices 9857 * Number of devices of device_type. 9858 * Access: RO 9859 */ 9860 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 9861 9862 /* num_of_modules 9863 * Number of modules. 9864 * Access: RO 9865 */ 9866 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 9867 9868 static inline void mlxsw_reg_mgpir_pack(char *payload) 9869 { 9870 MLXSW_REG_ZERO(mgpir, payload); 9871 } 9872 9873 static inline void 9874 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 9875 enum mlxsw_reg_mgpir_device_type *device_type, 9876 u8 *devices_per_flash, u8 *num_of_modules) 9877 { 9878 if (num_of_devices) 9879 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 9880 if (device_type) 9881 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 9882 if (devices_per_flash) 9883 *devices_per_flash = 9884 mlxsw_reg_mgpir_devices_per_flash_get(payload); 9885 if (num_of_modules) 9886 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 9887 } 9888 9889 /* TNGCR - Tunneling NVE General Configuration Register 9890 * ---------------------------------------------------- 9891 * The TNGCR register is used for setting up the NVE Tunneling configuration. 9892 */ 9893 #define MLXSW_REG_TNGCR_ID 0xA001 9894 #define MLXSW_REG_TNGCR_LEN 0x44 9895 9896 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 9897 9898 enum mlxsw_reg_tngcr_type { 9899 MLXSW_REG_TNGCR_TYPE_VXLAN, 9900 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 9901 MLXSW_REG_TNGCR_TYPE_GENEVE, 9902 MLXSW_REG_TNGCR_TYPE_NVGRE, 9903 }; 9904 9905 /* reg_tngcr_type 9906 * Tunnel type for encapsulation and decapsulation. The types are mutually 9907 * exclusive. 9908 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 9909 * Access: RW 9910 */ 9911 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 9912 9913 /* reg_tngcr_nve_valid 9914 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 9915 * Access: RW 9916 */ 9917 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 9918 9919 /* reg_tngcr_nve_ttl_uc 9920 * The TTL for NVE tunnel encapsulation underlay unicast packets. 9921 * Access: RW 9922 */ 9923 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 9924 9925 /* reg_tngcr_nve_ttl_mc 9926 * The TTL for NVE tunnel encapsulation underlay multicast packets. 9927 * Access: RW 9928 */ 9929 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 9930 9931 enum { 9932 /* Do not copy flow label. Calculate flow label using nve_flh. */ 9933 MLXSW_REG_TNGCR_FL_NO_COPY, 9934 /* Copy flow label from inner packet if packet is IPv6 and 9935 * encapsulation is by IPv6. Otherwise, calculate flow label using 9936 * nve_flh. 9937 */ 9938 MLXSW_REG_TNGCR_FL_COPY, 9939 }; 9940 9941 /* reg_tngcr_nve_flc 9942 * For NVE tunnel encapsulation: Flow label copy from inner packet. 9943 * Access: RW 9944 */ 9945 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 9946 9947 enum { 9948 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 9949 * uses {nve_fl_prefix, nve_fl_suffix}. 9950 */ 9951 MLXSW_REG_TNGCR_FL_NO_HASH, 9952 /* 8 LSBs of the flow label are calculated from ECMP hash of the 9953 * inner packet. 12 MSBs are configured by nve_fl_prefix. 9954 */ 9955 MLXSW_REG_TNGCR_FL_HASH, 9956 }; 9957 9958 /* reg_tngcr_nve_flh 9959 * NVE flow label hash. 9960 * Access: RW 9961 */ 9962 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 9963 9964 /* reg_tngcr_nve_fl_prefix 9965 * NVE flow label prefix. Constant 12 MSBs of the flow label. 9966 * Access: RW 9967 */ 9968 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 9969 9970 /* reg_tngcr_nve_fl_suffix 9971 * NVE flow label suffix. Constant 8 LSBs of the flow label. 9972 * Reserved when nve_flh=1 and for Spectrum. 9973 * Access: RW 9974 */ 9975 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 9976 9977 enum { 9978 /* Source UDP port is fixed (default '0') */ 9979 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 9980 /* Source UDP port is calculated based on hash */ 9981 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 9982 }; 9983 9984 /* reg_tngcr_nve_udp_sport_type 9985 * NVE UDP source port type. 9986 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 9987 * When the source UDP port is calculated based on hash, then the 8 LSBs 9988 * are calculated from hash the 8 MSBs are configured by 9989 * nve_udp_sport_prefix. 9990 * Access: RW 9991 */ 9992 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 9993 9994 /* reg_tngcr_nve_udp_sport_prefix 9995 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 9996 * Reserved when NVE type is NVGRE. 9997 * Access: RW 9998 */ 9999 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 10000 10001 /* reg_tngcr_nve_group_size_mc 10002 * The amount of sequential linked lists of MC entries. The first linked 10003 * list is configured by SFD.underlay_mc_ptr. 10004 * Valid values: 1, 2, 4, 8, 16, 32, 64 10005 * The linked list are configured by TNUMT. 10006 * The hash is set by LAG hash. 10007 * Access: RW 10008 */ 10009 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 10010 10011 /* reg_tngcr_nve_group_size_flood 10012 * The amount of sequential linked lists of flooding entries. The first 10013 * linked list is configured by SFMR.nve_tunnel_flood_ptr 10014 * Valid values: 1, 2, 4, 8, 16, 32, 64 10015 * The linked list are configured by TNUMT. 10016 * The hash is set by LAG hash. 10017 * Access: RW 10018 */ 10019 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 10020 10021 /* reg_tngcr_learn_enable 10022 * During decapsulation, whether to learn from NVE port. 10023 * Reserved when Spectrum-2. See TNPC. 10024 * Access: RW 10025 */ 10026 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 10027 10028 /* reg_tngcr_underlay_virtual_router 10029 * Underlay virtual router. 10030 * Reserved when Spectrum-2. 10031 * Access: RW 10032 */ 10033 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 10034 10035 /* reg_tngcr_underlay_rif 10036 * Underlay ingress router interface. RIF type should be loopback generic. 10037 * Reserved when Spectrum. 10038 * Access: RW 10039 */ 10040 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 10041 10042 /* reg_tngcr_usipv4 10043 * Underlay source IPv4 address of the NVE. 10044 * Access: RW 10045 */ 10046 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 10047 10048 /* reg_tngcr_usipv6 10049 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 10050 * modified under traffic of NVE tunneling encapsulation. 10051 * Access: RW 10052 */ 10053 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 10054 10055 static inline void mlxsw_reg_tngcr_pack(char *payload, 10056 enum mlxsw_reg_tngcr_type type, 10057 bool valid, u8 ttl) 10058 { 10059 MLXSW_REG_ZERO(tngcr, payload); 10060 mlxsw_reg_tngcr_type_set(payload, type); 10061 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 10062 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 10063 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 10064 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 10065 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 10066 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 10067 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 10068 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 10069 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 10070 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 10071 } 10072 10073 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 10074 * ------------------------------------------------------- 10075 * The TNUMT register is for building the underlay MC table. It is used 10076 * for MC, flooding and BC traffic into the NVE tunnel. 10077 */ 10078 #define MLXSW_REG_TNUMT_ID 0xA003 10079 #define MLXSW_REG_TNUMT_LEN 0x20 10080 10081 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 10082 10083 enum mlxsw_reg_tnumt_record_type { 10084 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 10085 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 10086 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 10087 }; 10088 10089 /* reg_tnumt_record_type 10090 * Record type. 10091 * Access: RW 10092 */ 10093 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 10094 10095 enum mlxsw_reg_tnumt_tunnel_port { 10096 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 10097 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 10098 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 10099 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 10100 }; 10101 10102 /* reg_tnumt_tunnel_port 10103 * Tunnel port. 10104 * Access: RW 10105 */ 10106 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 10107 10108 /* reg_tnumt_underlay_mc_ptr 10109 * Index to the underlay multicast table. 10110 * For Spectrum the index is to the KVD linear. 10111 * Access: Index 10112 */ 10113 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 10114 10115 /* reg_tnumt_vnext 10116 * The next_underlay_mc_ptr is valid. 10117 * Access: RW 10118 */ 10119 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 10120 10121 /* reg_tnumt_next_underlay_mc_ptr 10122 * The next index to the underlay multicast table. 10123 * Access: RW 10124 */ 10125 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 10126 10127 /* reg_tnumt_record_size 10128 * Number of IP addresses in the record. 10129 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 10130 * Access: RW 10131 */ 10132 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 10133 10134 /* reg_tnumt_udip 10135 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 10136 * Access: RW 10137 */ 10138 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 10139 10140 /* reg_tnumt_udip_ptr 10141 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 10142 * i >= size. The IPv6 addresses are configured by RIPS. 10143 * Access: RW 10144 */ 10145 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 10146 10147 static inline void mlxsw_reg_tnumt_pack(char *payload, 10148 enum mlxsw_reg_tnumt_record_type type, 10149 enum mlxsw_reg_tnumt_tunnel_port tport, 10150 u32 underlay_mc_ptr, bool vnext, 10151 u32 next_underlay_mc_ptr, 10152 u8 record_size) 10153 { 10154 MLXSW_REG_ZERO(tnumt, payload); 10155 mlxsw_reg_tnumt_record_type_set(payload, type); 10156 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 10157 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 10158 mlxsw_reg_tnumt_vnext_set(payload, vnext); 10159 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 10160 mlxsw_reg_tnumt_record_size_set(payload, record_size); 10161 } 10162 10163 /* TNQCR - Tunneling NVE QoS Configuration Register 10164 * ------------------------------------------------ 10165 * The TNQCR register configures how QoS is set in encapsulation into the 10166 * underlay network. 10167 */ 10168 #define MLXSW_REG_TNQCR_ID 0xA010 10169 #define MLXSW_REG_TNQCR_LEN 0x0C 10170 10171 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 10172 10173 /* reg_tnqcr_enc_set_dscp 10174 * For encapsulation: How to set DSCP field: 10175 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 10176 * (outer) IP header. If there is no IP header, use TNQDR.dscp 10177 * 1 - Set the DSCP field as TNQDR.dscp 10178 * Access: RW 10179 */ 10180 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 10181 10182 static inline void mlxsw_reg_tnqcr_pack(char *payload) 10183 { 10184 MLXSW_REG_ZERO(tnqcr, payload); 10185 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 10186 } 10187 10188 /* TNQDR - Tunneling NVE QoS Default Register 10189 * ------------------------------------------ 10190 * The TNQDR register configures the default QoS settings for NVE 10191 * encapsulation. 10192 */ 10193 #define MLXSW_REG_TNQDR_ID 0xA011 10194 #define MLXSW_REG_TNQDR_LEN 0x08 10195 10196 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 10197 10198 /* reg_tnqdr_local_port 10199 * Local port number (receive port). CPU port is supported. 10200 * Access: Index 10201 */ 10202 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 10203 10204 /* reg_tnqdr_dscp 10205 * For encapsulation, the default DSCP. 10206 * Access: RW 10207 */ 10208 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 10209 10210 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 10211 { 10212 MLXSW_REG_ZERO(tnqdr, payload); 10213 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 10214 mlxsw_reg_tnqdr_dscp_set(payload, 0); 10215 } 10216 10217 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 10218 * -------------------------------------------------------- 10219 * The TNEEM register maps ECN of the IP header at the ingress to the 10220 * encapsulation to the ECN of the underlay network. 10221 */ 10222 #define MLXSW_REG_TNEEM_ID 0xA012 10223 #define MLXSW_REG_TNEEM_LEN 0x0C 10224 10225 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 10226 10227 /* reg_tneem_overlay_ecn 10228 * ECN of the IP header in the overlay network. 10229 * Access: Index 10230 */ 10231 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 10232 10233 /* reg_tneem_underlay_ecn 10234 * ECN of the IP header in the underlay network. 10235 * Access: RW 10236 */ 10237 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 10238 10239 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 10240 u8 underlay_ecn) 10241 { 10242 MLXSW_REG_ZERO(tneem, payload); 10243 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 10244 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 10245 } 10246 10247 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 10248 * -------------------------------------------------------- 10249 * The TNDEM register configures the actions that are done in the 10250 * decapsulation. 10251 */ 10252 #define MLXSW_REG_TNDEM_ID 0xA013 10253 #define MLXSW_REG_TNDEM_LEN 0x0C 10254 10255 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 10256 10257 /* reg_tndem_underlay_ecn 10258 * ECN field of the IP header in the underlay network. 10259 * Access: Index 10260 */ 10261 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 10262 10263 /* reg_tndem_overlay_ecn 10264 * ECN field of the IP header in the overlay network. 10265 * Access: Index 10266 */ 10267 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10268 10269 /* reg_tndem_eip_ecn 10270 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10271 * from the decapsulation. 10272 * Access: RW 10273 */ 10274 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10275 10276 /* reg_tndem_trap_en 10277 * Trap enable: 10278 * 0 - No trap due to decap ECN 10279 * 1 - Trap enable with trap_id 10280 * Access: RW 10281 */ 10282 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10283 10284 /* reg_tndem_trap_id 10285 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10286 * Reserved when trap_en is '0'. 10287 * Access: RW 10288 */ 10289 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10290 10291 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10292 u8 overlay_ecn, u8 ecn, bool trap_en, 10293 u16 trap_id) 10294 { 10295 MLXSW_REG_ZERO(tndem, payload); 10296 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10297 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10298 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10299 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10300 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10301 } 10302 10303 /* TNPC - Tunnel Port Configuration Register 10304 * ----------------------------------------- 10305 * The TNPC register is used for tunnel port configuration. 10306 * Reserved when Spectrum. 10307 */ 10308 #define MLXSW_REG_TNPC_ID 0xA020 10309 #define MLXSW_REG_TNPC_LEN 0x18 10310 10311 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10312 10313 enum mlxsw_reg_tnpc_tunnel_port { 10314 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 10315 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 10316 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 10317 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 10318 }; 10319 10320 /* reg_tnpc_tunnel_port 10321 * Tunnel port. 10322 * Access: Index 10323 */ 10324 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10325 10326 /* reg_tnpc_learn_enable_v6 10327 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10328 * Access: RW 10329 */ 10330 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10331 10332 /* reg_tnpc_learn_enable_v4 10333 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10334 * Access: RW 10335 */ 10336 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10337 10338 static inline void mlxsw_reg_tnpc_pack(char *payload, 10339 enum mlxsw_reg_tnpc_tunnel_port tport, 10340 bool learn_enable) 10341 { 10342 MLXSW_REG_ZERO(tnpc, payload); 10343 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10344 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10345 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10346 } 10347 10348 /* TIGCR - Tunneling IPinIP General Configuration Register 10349 * ------------------------------------------------------- 10350 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10351 */ 10352 #define MLXSW_REG_TIGCR_ID 0xA801 10353 #define MLXSW_REG_TIGCR_LEN 0x10 10354 10355 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10356 10357 /* reg_tigcr_ipip_ttlc 10358 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10359 * header. 10360 * Access: RW 10361 */ 10362 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10363 10364 /* reg_tigcr_ipip_ttl_uc 10365 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10366 * reg_tigcr_ipip_ttlc is unset. 10367 * Access: RW 10368 */ 10369 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10370 10371 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10372 { 10373 MLXSW_REG_ZERO(tigcr, payload); 10374 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10375 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10376 } 10377 10378 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 10379 * ----------------------------------------------------------- 10380 * The TIEEM register maps ECN of the IP header at the ingress to the 10381 * encapsulation to the ECN of the underlay network. 10382 */ 10383 #define MLXSW_REG_TIEEM_ID 0xA812 10384 #define MLXSW_REG_TIEEM_LEN 0x0C 10385 10386 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 10387 10388 /* reg_tieem_overlay_ecn 10389 * ECN of the IP header in the overlay network. 10390 * Access: Index 10391 */ 10392 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 10393 10394 /* reg_tineem_underlay_ecn 10395 * ECN of the IP header in the underlay network. 10396 * Access: RW 10397 */ 10398 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 10399 10400 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 10401 u8 underlay_ecn) 10402 { 10403 MLXSW_REG_ZERO(tieem, payload); 10404 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 10405 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 10406 } 10407 10408 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 10409 * ----------------------------------------------------------- 10410 * The TIDEM register configures the actions that are done in the 10411 * decapsulation. 10412 */ 10413 #define MLXSW_REG_TIDEM_ID 0xA813 10414 #define MLXSW_REG_TIDEM_LEN 0x0C 10415 10416 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 10417 10418 /* reg_tidem_underlay_ecn 10419 * ECN field of the IP header in the underlay network. 10420 * Access: Index 10421 */ 10422 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 10423 10424 /* reg_tidem_overlay_ecn 10425 * ECN field of the IP header in the overlay network. 10426 * Access: Index 10427 */ 10428 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 10429 10430 /* reg_tidem_eip_ecn 10431 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10432 * from the decapsulation. 10433 * Access: RW 10434 */ 10435 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 10436 10437 /* reg_tidem_trap_en 10438 * Trap enable: 10439 * 0 - No trap due to decap ECN 10440 * 1 - Trap enable with trap_id 10441 * Access: RW 10442 */ 10443 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 10444 10445 /* reg_tidem_trap_id 10446 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10447 * Reserved when trap_en is '0'. 10448 * Access: RW 10449 */ 10450 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 10451 10452 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 10453 u8 overlay_ecn, u8 eip_ecn, 10454 bool trap_en, u16 trap_id) 10455 { 10456 MLXSW_REG_ZERO(tidem, payload); 10457 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 10458 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 10459 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 10460 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 10461 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 10462 } 10463 10464 /* SBPR - Shared Buffer Pools Register 10465 * ----------------------------------- 10466 * The SBPR configures and retrieves the shared buffer pools and configuration. 10467 */ 10468 #define MLXSW_REG_SBPR_ID 0xB001 10469 #define MLXSW_REG_SBPR_LEN 0x14 10470 10471 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10472 10473 /* shared direstion enum for SBPR, SBCM, SBPM */ 10474 enum mlxsw_reg_sbxx_dir { 10475 MLXSW_REG_SBXX_DIR_INGRESS, 10476 MLXSW_REG_SBXX_DIR_EGRESS, 10477 }; 10478 10479 /* reg_sbpr_dir 10480 * Direction. 10481 * Access: Index 10482 */ 10483 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10484 10485 /* reg_sbpr_pool 10486 * Pool index. 10487 * Access: Index 10488 */ 10489 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 10490 10491 /* reg_sbpr_infi_size 10492 * Size is infinite. 10493 * Access: RW 10494 */ 10495 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 10496 10497 /* reg_sbpr_size 10498 * Pool size in buffer cells. 10499 * Reserved when infi_size = 1. 10500 * Access: RW 10501 */ 10502 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 10503 10504 enum mlxsw_reg_sbpr_mode { 10505 MLXSW_REG_SBPR_MODE_STATIC, 10506 MLXSW_REG_SBPR_MODE_DYNAMIC, 10507 }; 10508 10509 /* reg_sbpr_mode 10510 * Pool quota calculation mode. 10511 * Access: RW 10512 */ 10513 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 10514 10515 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 10516 enum mlxsw_reg_sbxx_dir dir, 10517 enum mlxsw_reg_sbpr_mode mode, u32 size, 10518 bool infi_size) 10519 { 10520 MLXSW_REG_ZERO(sbpr, payload); 10521 mlxsw_reg_sbpr_pool_set(payload, pool); 10522 mlxsw_reg_sbpr_dir_set(payload, dir); 10523 mlxsw_reg_sbpr_mode_set(payload, mode); 10524 mlxsw_reg_sbpr_size_set(payload, size); 10525 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 10526 } 10527 10528 /* SBCM - Shared Buffer Class Management Register 10529 * ---------------------------------------------- 10530 * The SBCM register configures and retrieves the shared buffer allocation 10531 * and configuration according to Port-PG, including the binding to pool 10532 * and definition of the associated quota. 10533 */ 10534 #define MLXSW_REG_SBCM_ID 0xB002 10535 #define MLXSW_REG_SBCM_LEN 0x28 10536 10537 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 10538 10539 /* reg_sbcm_local_port 10540 * Local port number. 10541 * For Ingress: excludes CPU port and Router port 10542 * For Egress: excludes IP Router 10543 * Access: Index 10544 */ 10545 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 10546 10547 /* reg_sbcm_pg_buff 10548 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 10549 * For PG buffer: range is 0..cap_max_pg_buffers - 1 10550 * For traffic class: range is 0..cap_max_tclass - 1 10551 * Note that when traffic class is in MC aware mode then the traffic 10552 * classes which are MC aware cannot be configured. 10553 * Access: Index 10554 */ 10555 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 10556 10557 /* reg_sbcm_dir 10558 * Direction. 10559 * Access: Index 10560 */ 10561 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 10562 10563 /* reg_sbcm_min_buff 10564 * Minimum buffer size for the limiter, in cells. 10565 * Access: RW 10566 */ 10567 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 10568 10569 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 10570 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 10571 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 10572 10573 /* reg_sbcm_infi_max 10574 * Max buffer is infinite. 10575 * Access: RW 10576 */ 10577 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 10578 10579 /* reg_sbcm_max_buff 10580 * When the pool associated to the port-pg/tclass is configured to 10581 * static, Maximum buffer size for the limiter configured in cells. 10582 * When the pool associated to the port-pg/tclass is configured to 10583 * dynamic, the max_buff holds the "alpha" parameter, supporting 10584 * the following values: 10585 * 0: 0 10586 * i: (1/128)*2^(i-1), for i=1..14 10587 * 0xFF: Infinity 10588 * Reserved when infi_max = 1. 10589 * Access: RW 10590 */ 10591 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 10592 10593 /* reg_sbcm_pool 10594 * Association of the port-priority to a pool. 10595 * Access: RW 10596 */ 10597 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 10598 10599 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 10600 enum mlxsw_reg_sbxx_dir dir, 10601 u32 min_buff, u32 max_buff, 10602 bool infi_max, u8 pool) 10603 { 10604 MLXSW_REG_ZERO(sbcm, payload); 10605 mlxsw_reg_sbcm_local_port_set(payload, local_port); 10606 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 10607 mlxsw_reg_sbcm_dir_set(payload, dir); 10608 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 10609 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 10610 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 10611 mlxsw_reg_sbcm_pool_set(payload, pool); 10612 } 10613 10614 /* SBPM - Shared Buffer Port Management Register 10615 * --------------------------------------------- 10616 * The SBPM register configures and retrieves the shared buffer allocation 10617 * and configuration according to Port-Pool, including the definition 10618 * of the associated quota. 10619 */ 10620 #define MLXSW_REG_SBPM_ID 0xB003 10621 #define MLXSW_REG_SBPM_LEN 0x28 10622 10623 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 10624 10625 /* reg_sbpm_local_port 10626 * Local port number. 10627 * For Ingress: excludes CPU port and Router port 10628 * For Egress: excludes IP Router 10629 * Access: Index 10630 */ 10631 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 10632 10633 /* reg_sbpm_pool 10634 * The pool associated to quota counting on the local_port. 10635 * Access: Index 10636 */ 10637 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 10638 10639 /* reg_sbpm_dir 10640 * Direction. 10641 * Access: Index 10642 */ 10643 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 10644 10645 /* reg_sbpm_buff_occupancy 10646 * Current buffer occupancy in cells. 10647 * Access: RO 10648 */ 10649 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 10650 10651 /* reg_sbpm_clr 10652 * Clear Max Buffer Occupancy 10653 * When this bit is set, max_buff_occupancy field is cleared (and a 10654 * new max value is tracked from the time the clear was performed). 10655 * Access: OP 10656 */ 10657 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 10658 10659 /* reg_sbpm_max_buff_occupancy 10660 * Maximum value of buffer occupancy in cells monitored. Cleared by 10661 * writing to the clr field. 10662 * Access: RO 10663 */ 10664 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 10665 10666 /* reg_sbpm_min_buff 10667 * Minimum buffer size for the limiter, in cells. 10668 * Access: RW 10669 */ 10670 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 10671 10672 /* reg_sbpm_max_buff 10673 * When the pool associated to the port-pg/tclass is configured to 10674 * static, Maximum buffer size for the limiter configured in cells. 10675 * When the pool associated to the port-pg/tclass is configured to 10676 * dynamic, the max_buff holds the "alpha" parameter, supporting 10677 * the following values: 10678 * 0: 0 10679 * i: (1/128)*2^(i-1), for i=1..14 10680 * 0xFF: Infinity 10681 * Access: RW 10682 */ 10683 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 10684 10685 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 10686 enum mlxsw_reg_sbxx_dir dir, bool clr, 10687 u32 min_buff, u32 max_buff) 10688 { 10689 MLXSW_REG_ZERO(sbpm, payload); 10690 mlxsw_reg_sbpm_local_port_set(payload, local_port); 10691 mlxsw_reg_sbpm_pool_set(payload, pool); 10692 mlxsw_reg_sbpm_dir_set(payload, dir); 10693 mlxsw_reg_sbpm_clr_set(payload, clr); 10694 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 10695 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 10696 } 10697 10698 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 10699 u32 *p_max_buff_occupancy) 10700 { 10701 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 10702 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 10703 } 10704 10705 /* SBMM - Shared Buffer Multicast Management Register 10706 * -------------------------------------------------- 10707 * The SBMM register configures and retrieves the shared buffer allocation 10708 * and configuration for MC packets according to Switch-Priority, including 10709 * the binding to pool and definition of the associated quota. 10710 */ 10711 #define MLXSW_REG_SBMM_ID 0xB004 10712 #define MLXSW_REG_SBMM_LEN 0x28 10713 10714 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 10715 10716 /* reg_sbmm_prio 10717 * Switch Priority. 10718 * Access: Index 10719 */ 10720 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 10721 10722 /* reg_sbmm_min_buff 10723 * Minimum buffer size for the limiter, in cells. 10724 * Access: RW 10725 */ 10726 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 10727 10728 /* reg_sbmm_max_buff 10729 * When the pool associated to the port-pg/tclass is configured to 10730 * static, Maximum buffer size for the limiter configured in cells. 10731 * When the pool associated to the port-pg/tclass is configured to 10732 * dynamic, the max_buff holds the "alpha" parameter, supporting 10733 * the following values: 10734 * 0: 0 10735 * i: (1/128)*2^(i-1), for i=1..14 10736 * 0xFF: Infinity 10737 * Access: RW 10738 */ 10739 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 10740 10741 /* reg_sbmm_pool 10742 * Association of the port-priority to a pool. 10743 * Access: RW 10744 */ 10745 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 10746 10747 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 10748 u32 max_buff, u8 pool) 10749 { 10750 MLXSW_REG_ZERO(sbmm, payload); 10751 mlxsw_reg_sbmm_prio_set(payload, prio); 10752 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 10753 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 10754 mlxsw_reg_sbmm_pool_set(payload, pool); 10755 } 10756 10757 /* SBSR - Shared Buffer Status Register 10758 * ------------------------------------ 10759 * The SBSR register retrieves the shared buffer occupancy according to 10760 * Port-Pool. Note that this register enables reading a large amount of data. 10761 * It is the user's responsibility to limit the amount of data to ensure the 10762 * response can match the maximum transfer unit. In case the response exceeds 10763 * the maximum transport unit, it will be truncated with no special notice. 10764 */ 10765 #define MLXSW_REG_SBSR_ID 0xB005 10766 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 10767 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 10768 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 10769 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 10770 MLXSW_REG_SBSR_REC_LEN * \ 10771 MLXSW_REG_SBSR_REC_MAX_COUNT) 10772 10773 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 10774 10775 /* reg_sbsr_clr 10776 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 10777 * field is cleared (and a new max value is tracked from the time the clear 10778 * was performed). 10779 * Access: OP 10780 */ 10781 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 10782 10783 /* reg_sbsr_ingress_port_mask 10784 * Bit vector for all ingress network ports. 10785 * Indicates which of the ports (for which the relevant bit is set) 10786 * are affected by the set operation. Configuration of any other port 10787 * does not change. 10788 * Access: Index 10789 */ 10790 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 10791 10792 /* reg_sbsr_pg_buff_mask 10793 * Bit vector for all switch priority groups. 10794 * Indicates which of the priorities (for which the relevant bit is set) 10795 * are affected by the set operation. Configuration of any other priority 10796 * does not change. 10797 * Range is 0..cap_max_pg_buffers - 1 10798 * Access: Index 10799 */ 10800 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 10801 10802 /* reg_sbsr_egress_port_mask 10803 * Bit vector for all egress network ports. 10804 * Indicates which of the ports (for which the relevant bit is set) 10805 * are affected by the set operation. Configuration of any other port 10806 * does not change. 10807 * Access: Index 10808 */ 10809 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 10810 10811 /* reg_sbsr_tclass_mask 10812 * Bit vector for all traffic classes. 10813 * Indicates which of the traffic classes (for which the relevant bit is 10814 * set) are affected by the set operation. Configuration of any other 10815 * traffic class does not change. 10816 * Range is 0..cap_max_tclass - 1 10817 * Access: Index 10818 */ 10819 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 10820 10821 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 10822 { 10823 MLXSW_REG_ZERO(sbsr, payload); 10824 mlxsw_reg_sbsr_clr_set(payload, clr); 10825 } 10826 10827 /* reg_sbsr_rec_buff_occupancy 10828 * Current buffer occupancy in cells. 10829 * Access: RO 10830 */ 10831 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10832 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 10833 10834 /* reg_sbsr_rec_max_buff_occupancy 10835 * Maximum value of buffer occupancy in cells monitored. Cleared by 10836 * writing to the clr field. 10837 * Access: RO 10838 */ 10839 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10840 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 10841 10842 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 10843 u32 *p_buff_occupancy, 10844 u32 *p_max_buff_occupancy) 10845 { 10846 *p_buff_occupancy = 10847 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 10848 *p_max_buff_occupancy = 10849 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 10850 } 10851 10852 /* SBIB - Shared Buffer Internal Buffer Register 10853 * --------------------------------------------- 10854 * The SBIB register configures per port buffers for internal use. The internal 10855 * buffers consume memory on the port buffers (note that the port buffers are 10856 * used also by PBMC). 10857 * 10858 * For Spectrum this is used for egress mirroring. 10859 */ 10860 #define MLXSW_REG_SBIB_ID 0xB006 10861 #define MLXSW_REG_SBIB_LEN 0x10 10862 10863 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 10864 10865 /* reg_sbib_local_port 10866 * Local port number 10867 * Not supported for CPU port and router port 10868 * Access: Index 10869 */ 10870 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 10871 10872 /* reg_sbib_buff_size 10873 * Units represented in cells 10874 * Allowed range is 0 to (cap_max_headroom_size - 1) 10875 * Default is 0 10876 * Access: RW 10877 */ 10878 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 10879 10880 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 10881 u32 buff_size) 10882 { 10883 MLXSW_REG_ZERO(sbib, payload); 10884 mlxsw_reg_sbib_local_port_set(payload, local_port); 10885 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 10886 } 10887 10888 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 10889 MLXSW_REG(sgcr), 10890 MLXSW_REG(spad), 10891 MLXSW_REG(smid), 10892 MLXSW_REG(sspr), 10893 MLXSW_REG(sfdat), 10894 MLXSW_REG(sfd), 10895 MLXSW_REG(sfn), 10896 MLXSW_REG(spms), 10897 MLXSW_REG(spvid), 10898 MLXSW_REG(spvm), 10899 MLXSW_REG(spaft), 10900 MLXSW_REG(sfgc), 10901 MLXSW_REG(sftr), 10902 MLXSW_REG(sfdf), 10903 MLXSW_REG(sldr), 10904 MLXSW_REG(slcr), 10905 MLXSW_REG(slcor), 10906 MLXSW_REG(spmlr), 10907 MLXSW_REG(svfa), 10908 MLXSW_REG(svpe), 10909 MLXSW_REG(sfmr), 10910 MLXSW_REG(spvmlr), 10911 MLXSW_REG(cwtp), 10912 MLXSW_REG(cwtpm), 10913 MLXSW_REG(pgcr), 10914 MLXSW_REG(ppbt), 10915 MLXSW_REG(pacl), 10916 MLXSW_REG(pagt), 10917 MLXSW_REG(ptar), 10918 MLXSW_REG(ppbs), 10919 MLXSW_REG(prcr), 10920 MLXSW_REG(pefa), 10921 MLXSW_REG(pemrbt), 10922 MLXSW_REG(ptce2), 10923 MLXSW_REG(perpt), 10924 MLXSW_REG(peabfe), 10925 MLXSW_REG(perar), 10926 MLXSW_REG(ptce3), 10927 MLXSW_REG(percr), 10928 MLXSW_REG(pererp), 10929 MLXSW_REG(iedr), 10930 MLXSW_REG(qpts), 10931 MLXSW_REG(qpcr), 10932 MLXSW_REG(qtct), 10933 MLXSW_REG(qeec), 10934 MLXSW_REG(qrwe), 10935 MLXSW_REG(qpdsm), 10936 MLXSW_REG(qpdp), 10937 MLXSW_REG(qpdpm), 10938 MLXSW_REG(qtctm), 10939 MLXSW_REG(qpsc), 10940 MLXSW_REG(pmlp), 10941 MLXSW_REG(pmtu), 10942 MLXSW_REG(ptys), 10943 MLXSW_REG(ppad), 10944 MLXSW_REG(paos), 10945 MLXSW_REG(pfcc), 10946 MLXSW_REG(ppcnt), 10947 MLXSW_REG(plib), 10948 MLXSW_REG(pptb), 10949 MLXSW_REG(pbmc), 10950 MLXSW_REG(pspa), 10951 MLXSW_REG(pplr), 10952 MLXSW_REG(pddr), 10953 MLXSW_REG(pmtm), 10954 MLXSW_REG(htgt), 10955 MLXSW_REG(hpkt), 10956 MLXSW_REG(rgcr), 10957 MLXSW_REG(ritr), 10958 MLXSW_REG(rtar), 10959 MLXSW_REG(ratr), 10960 MLXSW_REG(rtdp), 10961 MLXSW_REG(rdpm), 10962 MLXSW_REG(ricnt), 10963 MLXSW_REG(rrcr), 10964 MLXSW_REG(ralta), 10965 MLXSW_REG(ralst), 10966 MLXSW_REG(raltb), 10967 MLXSW_REG(ralue), 10968 MLXSW_REG(rauht), 10969 MLXSW_REG(raleu), 10970 MLXSW_REG(rauhtd), 10971 MLXSW_REG(rigr2), 10972 MLXSW_REG(recr2), 10973 MLXSW_REG(rmft2), 10974 MLXSW_REG(mfcr), 10975 MLXSW_REG(mfsc), 10976 MLXSW_REG(mfsm), 10977 MLXSW_REG(mfsl), 10978 MLXSW_REG(fore), 10979 MLXSW_REG(mtcap), 10980 MLXSW_REG(mtmp), 10981 MLXSW_REG(mtbr), 10982 MLXSW_REG(mcia), 10983 MLXSW_REG(mpat), 10984 MLXSW_REG(mpar), 10985 MLXSW_REG(mgir), 10986 MLXSW_REG(mrsr), 10987 MLXSW_REG(mlcr), 10988 MLXSW_REG(mtpps), 10989 MLXSW_REG(mtutc), 10990 MLXSW_REG(mpsc), 10991 MLXSW_REG(mcqi), 10992 MLXSW_REG(mcc), 10993 MLXSW_REG(mcda), 10994 MLXSW_REG(mgpc), 10995 MLXSW_REG(mprs), 10996 MLXSW_REG(mogcr), 10997 MLXSW_REG(mpagr), 10998 MLXSW_REG(momte), 10999 MLXSW_REG(mtpppc), 11000 MLXSW_REG(mtpptr), 11001 MLXSW_REG(mtptpt), 11002 MLXSW_REG(mgpir), 11003 MLXSW_REG(tngcr), 11004 MLXSW_REG(tnumt), 11005 MLXSW_REG(tnqcr), 11006 MLXSW_REG(tnqdr), 11007 MLXSW_REG(tneem), 11008 MLXSW_REG(tndem), 11009 MLXSW_REG(tnpc), 11010 MLXSW_REG(tigcr), 11011 MLXSW_REG(tieem), 11012 MLXSW_REG(tidem), 11013 MLXSW_REG(sbpr), 11014 MLXSW_REG(sbcm), 11015 MLXSW_REG(sbpm), 11016 MLXSW_REG(sbmm), 11017 MLXSW_REG(sbsr), 11018 MLXSW_REG(sbib), 11019 }; 11020 11021 static inline const char *mlxsw_reg_id_str(u16 reg_id) 11022 { 11023 const struct mlxsw_reg_info *reg_info; 11024 int i; 11025 11026 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 11027 reg_info = mlxsw_reg_infos[i]; 11028 if (reg_info->id == reg_id) 11029 return reg_info->name; 11030 } 11031 return "*UNKNOWN*"; 11032 } 11033 11034 /* PUDE - Port Up / Down Event 11035 * --------------------------- 11036 * Reports the operational state change of a port. 11037 */ 11038 #define MLXSW_REG_PUDE_LEN 0x10 11039 11040 /* reg_pude_swid 11041 * Switch partition ID with which to associate the port. 11042 * Access: Index 11043 */ 11044 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 11045 11046 /* reg_pude_local_port 11047 * Local port number. 11048 * Access: Index 11049 */ 11050 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 11051 11052 /* reg_pude_admin_status 11053 * Port administrative state (the desired state). 11054 * 1 - Up. 11055 * 2 - Down. 11056 * 3 - Up once. This means that in case of link failure, the port won't go 11057 * into polling mode, but will wait to be re-enabled by software. 11058 * 4 - Disabled by system. Can only be set by hardware. 11059 * Access: RO 11060 */ 11061 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 11062 11063 /* reg_pude_oper_status 11064 * Port operatioanl state. 11065 * 1 - Up. 11066 * 2 - Down. 11067 * 3 - Down by port failure. This means that the device will not let the 11068 * port up again until explicitly specified by software. 11069 * Access: RO 11070 */ 11071 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 11072 11073 #endif 11074