1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 1); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_acl_id 2203 * ACL identifier 2204 * Access: RW 2205 */ 2206 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2207 2208 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2209 { 2210 MLXSW_REG_ZERO(pagt, payload); 2211 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2212 } 2213 2214 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2215 u16 acl_id) 2216 { 2217 u8 size = mlxsw_reg_pagt_size_get(payload); 2218 2219 if (index >= size) 2220 mlxsw_reg_pagt_size_set(payload, index + 1); 2221 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2222 } 2223 2224 /* PTAR - Policy-Engine TCAM Allocation Register 2225 * --------------------------------------------- 2226 * This register is used for allocation of regions in the TCAM. 2227 * Note: Query method is not supported on this register. 2228 */ 2229 #define MLXSW_REG_PTAR_ID 0x3006 2230 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2231 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2232 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2233 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2234 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2235 2236 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2237 2238 enum mlxsw_reg_ptar_op { 2239 /* allocate a TCAM region */ 2240 MLXSW_REG_PTAR_OP_ALLOC, 2241 /* resize a TCAM region */ 2242 MLXSW_REG_PTAR_OP_RESIZE, 2243 /* deallocate TCAM region */ 2244 MLXSW_REG_PTAR_OP_FREE, 2245 /* test allocation */ 2246 MLXSW_REG_PTAR_OP_TEST, 2247 }; 2248 2249 /* reg_ptar_op 2250 * Access: OP 2251 */ 2252 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2253 2254 /* reg_ptar_action_set_type 2255 * Type of action set to be used on this region. 2256 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2257 * Access: WO 2258 */ 2259 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2260 2261 enum mlxsw_reg_ptar_key_type { 2262 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2263 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2264 }; 2265 2266 /* reg_ptar_key_type 2267 * TCAM key type for the region. 2268 * Access: WO 2269 */ 2270 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2271 2272 /* reg_ptar_region_size 2273 * TCAM region size. When allocating/resizing this is the requested size, 2274 * the response is the actual size. Note that actual size may be 2275 * larger than requested. 2276 * Allowed range 1 .. cap_max_rules-1 2277 * Reserved during op deallocate. 2278 * Access: WO 2279 */ 2280 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2281 2282 /* reg_ptar_region_id 2283 * Region identifier 2284 * Range 0 .. cap_max_regions-1 2285 * Access: Index 2286 */ 2287 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2288 2289 /* reg_ptar_tcam_region_info 2290 * Opaque object that represents the TCAM region. 2291 * Returned when allocating a region. 2292 * Provided by software for ACL generation and region deallocation and resize. 2293 * Access: RW 2294 */ 2295 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2296 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2297 2298 /* reg_ptar_flexible_key_id 2299 * Identifier of the Flexible Key. 2300 * Only valid if key_type == "FLEX_KEY" 2301 * The key size will be rounded up to one of the following values: 2302 * 9B, 18B, 36B, 54B. 2303 * This field is reserved for in resize operation. 2304 * Access: WO 2305 */ 2306 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2307 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2308 2309 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2310 enum mlxsw_reg_ptar_key_type key_type, 2311 u16 region_size, u16 region_id, 2312 const char *tcam_region_info) 2313 { 2314 MLXSW_REG_ZERO(ptar, payload); 2315 mlxsw_reg_ptar_op_set(payload, op); 2316 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2317 mlxsw_reg_ptar_key_type_set(payload, key_type); 2318 mlxsw_reg_ptar_region_size_set(payload, region_size); 2319 mlxsw_reg_ptar_region_id_set(payload, region_id); 2320 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2321 } 2322 2323 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2324 u16 key_id) 2325 { 2326 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2327 } 2328 2329 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2330 { 2331 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2332 } 2333 2334 /* PPBS - Policy-Engine Policy Based Switching Register 2335 * ---------------------------------------------------- 2336 * This register retrieves and sets Policy Based Switching Table entries. 2337 */ 2338 #define MLXSW_REG_PPBS_ID 0x300C 2339 #define MLXSW_REG_PPBS_LEN 0x14 2340 2341 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2342 2343 /* reg_ppbs_pbs_ptr 2344 * Index into the PBS table. 2345 * For Spectrum, the index points to the KVD Linear. 2346 * Access: Index 2347 */ 2348 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2349 2350 /* reg_ppbs_system_port 2351 * Unique port identifier for the final destination of the packet. 2352 * Access: RW 2353 */ 2354 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2355 2356 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2357 u16 system_port) 2358 { 2359 MLXSW_REG_ZERO(ppbs, payload); 2360 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2361 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2362 } 2363 2364 /* PRCR - Policy-Engine Rules Copy Register 2365 * ---------------------------------------- 2366 * This register is used for accessing rules within a TCAM region. 2367 */ 2368 #define MLXSW_REG_PRCR_ID 0x300D 2369 #define MLXSW_REG_PRCR_LEN 0x40 2370 2371 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2372 2373 enum mlxsw_reg_prcr_op { 2374 /* Move rules. Moves the rules from "tcam_region_info" starting 2375 * at offset "offset" to "dest_tcam_region_info" 2376 * at offset "dest_offset." 2377 */ 2378 MLXSW_REG_PRCR_OP_MOVE, 2379 /* Copy rules. Copies the rules from "tcam_region_info" starting 2380 * at offset "offset" to "dest_tcam_region_info" 2381 * at offset "dest_offset." 2382 */ 2383 MLXSW_REG_PRCR_OP_COPY, 2384 }; 2385 2386 /* reg_prcr_op 2387 * Access: OP 2388 */ 2389 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2390 2391 /* reg_prcr_offset 2392 * Offset within the source region to copy/move from. 2393 * Access: Index 2394 */ 2395 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2396 2397 /* reg_prcr_size 2398 * The number of rules to copy/move. 2399 * Access: WO 2400 */ 2401 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2402 2403 /* reg_prcr_tcam_region_info 2404 * Opaque object that represents the source TCAM region. 2405 * Access: Index 2406 */ 2407 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2408 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2409 2410 /* reg_prcr_dest_offset 2411 * Offset within the source region to copy/move to. 2412 * Access: Index 2413 */ 2414 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2415 2416 /* reg_prcr_dest_tcam_region_info 2417 * Opaque object that represents the destination TCAM region. 2418 * Access: Index 2419 */ 2420 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2421 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2422 2423 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2424 const char *src_tcam_region_info, 2425 u16 src_offset, 2426 const char *dest_tcam_region_info, 2427 u16 dest_offset, u16 size) 2428 { 2429 MLXSW_REG_ZERO(prcr, payload); 2430 mlxsw_reg_prcr_op_set(payload, op); 2431 mlxsw_reg_prcr_offset_set(payload, src_offset); 2432 mlxsw_reg_prcr_size_set(payload, size); 2433 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2434 src_tcam_region_info); 2435 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2436 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2437 dest_tcam_region_info); 2438 } 2439 2440 /* PEFA - Policy-Engine Extended Flexible Action Register 2441 * ------------------------------------------------------ 2442 * This register is used for accessing an extended flexible action entry 2443 * in the central KVD Linear Database. 2444 */ 2445 #define MLXSW_REG_PEFA_ID 0x300F 2446 #define MLXSW_REG_PEFA_LEN 0xB0 2447 2448 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2449 2450 /* reg_pefa_index 2451 * Index in the KVD Linear Centralized Database. 2452 * Access: Index 2453 */ 2454 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2455 2456 /* reg_pefa_a 2457 * Index in the KVD Linear Centralized Database. 2458 * Activity 2459 * For a new entry: set if ca=0, clear if ca=1 2460 * Set if a packet lookup has hit on the specific entry 2461 * Access: RO 2462 */ 2463 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2464 2465 /* reg_pefa_ca 2466 * Clear activity 2467 * When write: activity is according to this field 2468 * When read: after reading the activity is cleared according to ca 2469 * Access: OP 2470 */ 2471 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2472 2473 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2474 2475 /* reg_pefa_flex_action_set 2476 * Action-set to perform when rule is matched. 2477 * Must be zero padded if action set is shorter. 2478 * Access: RW 2479 */ 2480 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2481 2482 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2483 const char *flex_action_set) 2484 { 2485 MLXSW_REG_ZERO(pefa, payload); 2486 mlxsw_reg_pefa_index_set(payload, index); 2487 mlxsw_reg_pefa_ca_set(payload, ca); 2488 if (flex_action_set) 2489 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2490 flex_action_set); 2491 } 2492 2493 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2494 { 2495 *p_a = mlxsw_reg_pefa_a_get(payload); 2496 } 2497 2498 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2499 * -------------------------------------------------------------- 2500 * This register is used for binding Multicast router to an ACL group 2501 * that serves the MC router. 2502 * This register is not supported by SwitchX/-2 and Spectrum. 2503 */ 2504 #define MLXSW_REG_PEMRBT_ID 0x3014 2505 #define MLXSW_REG_PEMRBT_LEN 0x14 2506 2507 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2508 2509 enum mlxsw_reg_pemrbt_protocol { 2510 MLXSW_REG_PEMRBT_PROTO_IPV4, 2511 MLXSW_REG_PEMRBT_PROTO_IPV6, 2512 }; 2513 2514 /* reg_pemrbt_protocol 2515 * Access: Index 2516 */ 2517 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2518 2519 /* reg_pemrbt_group_id 2520 * ACL group identifier. 2521 * Range 0..cap_max_acl_groups-1 2522 * Access: RW 2523 */ 2524 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2525 2526 static inline void 2527 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2528 u16 group_id) 2529 { 2530 MLXSW_REG_ZERO(pemrbt, payload); 2531 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2532 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2533 } 2534 2535 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2536 * ----------------------------------------------------- 2537 * This register is used for accessing rules within a TCAM region. 2538 * It is a new version of PTCE in order to support wider key, 2539 * mask and action within a TCAM region. This register is not supported 2540 * by SwitchX and SwitchX-2. 2541 */ 2542 #define MLXSW_REG_PTCE2_ID 0x3017 2543 #define MLXSW_REG_PTCE2_LEN 0x1D8 2544 2545 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2546 2547 /* reg_ptce2_v 2548 * Valid. 2549 * Access: RW 2550 */ 2551 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2552 2553 /* reg_ptce2_a 2554 * Activity. Set if a packet lookup has hit on the specific entry. 2555 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2556 * Access: RO 2557 */ 2558 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2559 2560 enum mlxsw_reg_ptce2_op { 2561 /* Read operation. */ 2562 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2563 /* clear on read operation. Used to read entry 2564 * and clear Activity bit. 2565 */ 2566 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2567 /* Write operation. Used to write a new entry to the table. 2568 * All R/W fields are relevant for new entry. Activity bit is set 2569 * for new entries - Note write with v = 0 will delete the entry. 2570 */ 2571 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2572 /* Update action. Only action set will be updated. */ 2573 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2574 /* Clear activity. A bit is cleared for the entry. */ 2575 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2576 }; 2577 2578 /* reg_ptce2_op 2579 * Access: OP 2580 */ 2581 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2582 2583 /* reg_ptce2_offset 2584 * Access: Index 2585 */ 2586 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2587 2588 /* reg_ptce2_priority 2589 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2590 * Note: priority does not have to be unique per rule. 2591 * Within a region, higher priority should have lower offset (no limitation 2592 * between regions in a multi-region). 2593 * Access: RW 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2596 2597 /* reg_ptce2_tcam_region_info 2598 * Opaque object that represents the TCAM region. 2599 * Access: Index 2600 */ 2601 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2602 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2603 2604 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2605 2606 /* reg_ptce2_flex_key_blocks 2607 * ACL Key. 2608 * Access: RW 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2611 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2612 2613 /* reg_ptce2_mask 2614 * mask- in the same size as key. A bit that is set directs the TCAM 2615 * to compare the corresponding bit in key. A bit that is clear directs 2616 * the TCAM to ignore the corresponding bit in key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_flex_action_set 2623 * ACL action set. 2624 * Access: RW 2625 */ 2626 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2627 MLXSW_REG_FLEX_ACTION_SET_LEN); 2628 2629 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2630 enum mlxsw_reg_ptce2_op op, 2631 const char *tcam_region_info, 2632 u16 offset, u32 priority) 2633 { 2634 MLXSW_REG_ZERO(ptce2, payload); 2635 mlxsw_reg_ptce2_v_set(payload, valid); 2636 mlxsw_reg_ptce2_op_set(payload, op); 2637 mlxsw_reg_ptce2_offset_set(payload, offset); 2638 mlxsw_reg_ptce2_priority_set(payload, priority); 2639 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2640 } 2641 2642 /* PERPT - Policy-Engine ERP Table Register 2643 * ---------------------------------------- 2644 * This register adds and removes eRPs from the eRP table. 2645 */ 2646 #define MLXSW_REG_PERPT_ID 0x3021 2647 #define MLXSW_REG_PERPT_LEN 0x80 2648 2649 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2650 2651 /* reg_perpt_erpt_bank 2652 * eRP table bank. 2653 * Range 0 .. cap_max_erp_table_banks - 1 2654 * Access: Index 2655 */ 2656 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2657 2658 /* reg_perpt_erpt_index 2659 * Index to eRP table within the eRP bank. 2660 * Range is 0 .. cap_max_erp_table_bank_size - 1 2661 * Access: Index 2662 */ 2663 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2664 2665 enum mlxsw_reg_perpt_key_size { 2666 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2667 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2668 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2669 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2670 }; 2671 2672 /* reg_perpt_key_size 2673 * Access: OP 2674 */ 2675 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2676 2677 /* reg_perpt_bf_bypass 2678 * 0 - The eRP is used only if bloom filter state is set for the given 2679 * rule. 2680 * 1 - The eRP is used regardless of bloom filter state. 2681 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2682 * Access: RW 2683 */ 2684 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2685 2686 /* reg_perpt_erp_id 2687 * eRP ID for use by the rules. 2688 * Access: RW 2689 */ 2690 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2691 2692 /* reg_perpt_erpt_base_bank 2693 * Base eRP table bank, points to head of erp_vector 2694 * Range is 0 .. cap_max_erp_table_banks - 1 2695 * Access: OP 2696 */ 2697 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2698 2699 /* reg_perpt_erpt_base_index 2700 * Base index to eRP table within the eRP bank 2701 * Range is 0 .. cap_max_erp_table_bank_size - 1 2702 * Access: OP 2703 */ 2704 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2705 2706 /* reg_perpt_erp_index_in_vector 2707 * eRP index in the vector. 2708 * Access: OP 2709 */ 2710 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2711 2712 /* reg_perpt_erp_vector 2713 * eRP vector. 2714 * Access: OP 2715 */ 2716 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2717 2718 /* reg_perpt_mask 2719 * Mask 2720 * 0 - A-TCAM will ignore the bit in key 2721 * 1 - A-TCAM will compare the bit in key 2722 * Access: RW 2723 */ 2724 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2725 2726 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2727 unsigned long *erp_vector, 2728 unsigned long size) 2729 { 2730 unsigned long bit; 2731 2732 for_each_set_bit(bit, erp_vector, size) 2733 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2734 } 2735 2736 static inline void 2737 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2738 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2739 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2740 char *mask) 2741 { 2742 MLXSW_REG_ZERO(perpt, payload); 2743 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2744 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2745 mlxsw_reg_perpt_key_size_set(payload, key_size); 2746 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2747 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2748 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2749 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2750 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2751 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2752 } 2753 2754 /* PERAR - Policy-Engine Region Association Register 2755 * ------------------------------------------------- 2756 * This register associates a hw region for region_id's. Changing on the fly 2757 * is supported by the device. 2758 */ 2759 #define MLXSW_REG_PERAR_ID 0x3026 2760 #define MLXSW_REG_PERAR_LEN 0x08 2761 2762 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2763 2764 /* reg_perar_region_id 2765 * Region identifier 2766 * Range 0 .. cap_max_regions-1 2767 * Access: Index 2768 */ 2769 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2770 2771 static inline unsigned int 2772 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2773 { 2774 return DIV_ROUND_UP(block_num, 4); 2775 } 2776 2777 /* reg_perar_hw_region 2778 * HW Region 2779 * Range 0 .. cap_max_regions-1 2780 * Default: hw_region = region_id 2781 * For a 8 key block region, 2 consecutive regions are used 2782 * For a 12 key block region, 3 consecutive regions are used 2783 * Access: RW 2784 */ 2785 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2786 2787 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2788 u16 hw_region) 2789 { 2790 MLXSW_REG_ZERO(perar, payload); 2791 mlxsw_reg_perar_region_id_set(payload, region_id); 2792 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2793 } 2794 2795 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2796 * ----------------------------------------------------- 2797 * This register is a new version of PTCE-V2 in order to support the 2798 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2799 */ 2800 #define MLXSW_REG_PTCE3_ID 0x3027 2801 #define MLXSW_REG_PTCE3_LEN 0xF0 2802 2803 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2804 2805 /* reg_ptce3_v 2806 * Valid. 2807 * Access: RW 2808 */ 2809 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2810 2811 enum mlxsw_reg_ptce3_op { 2812 /* Write operation. Used to write a new entry to the table. 2813 * All R/W fields are relevant for new entry. Activity bit is set 2814 * for new entries. Write with v = 0 will delete the entry. Must 2815 * not be used if an entry exists. 2816 */ 2817 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2818 /* Update operation */ 2819 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2820 /* Read operation */ 2821 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2822 }; 2823 2824 /* reg_ptce3_op 2825 * Access: OP 2826 */ 2827 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2828 2829 /* reg_ptce3_priority 2830 * Priority of the rule. Higher values win. 2831 * For Spectrum-2 range is 1..cap_kvd_size - 1 2832 * Note: Priority does not have to be unique per rule. 2833 * Access: RW 2834 */ 2835 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2836 2837 /* reg_ptce3_tcam_region_info 2838 * Opaque object that represents the TCAM region. 2839 * Access: Index 2840 */ 2841 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2842 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2843 2844 /* reg_ptce3_flex2_key_blocks 2845 * ACL key. The key must be masked according to eRP (if exists) or 2846 * according to master mask. 2847 * Access: Index 2848 */ 2849 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2850 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2851 2852 /* reg_ptce3_erp_id 2853 * eRP ID. 2854 * Access: Index 2855 */ 2856 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2857 2858 /* reg_ptce3_delta_start 2859 * Start point of delta_value and delta_mask, in bits. Must not exceed 2860 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2861 * Access: Index 2862 */ 2863 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2864 2865 /* reg_ptce3_delta_mask 2866 * Delta mask. 2867 * 0 - Ignore relevant bit in delta_value 2868 * 1 - Compare relevant bit in delta_value 2869 * Delta mask must not be set for reserved fields in the key blocks. 2870 * Note: No delta when no eRPs. Thus, for regions with 2871 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2872 * Access: Index 2873 */ 2874 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2875 2876 /* reg_ptce3_delta_value 2877 * Delta value. 2878 * Bits which are masked by delta_mask must be 0. 2879 * Access: Index 2880 */ 2881 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2882 2883 /* reg_ptce3_prune_vector 2884 * Pruning vector relative to the PERPT.erp_id. 2885 * Used for reducing lookups. 2886 * 0 - NEED: Do a lookup using the eRP. 2887 * 1 - PRUNE: Do not perform a lookup using the eRP. 2888 * Maybe be modified by PEAPBL and PEAPBM. 2889 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2890 * all 1's or all 0's. 2891 * Access: RW 2892 */ 2893 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2894 2895 /* reg_ptce3_prune_ctcam 2896 * Pruning on C-TCAM. Used for reducing lookups. 2897 * 0 - NEED: Do a lookup in the C-TCAM. 2898 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2899 * Access: RW 2900 */ 2901 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2902 2903 /* reg_ptce3_large_exists 2904 * Large entry key ID exists. 2905 * Within the region: 2906 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2907 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2908 * For rule delete: The MSB of the key will be removed. 2909 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2910 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2911 * For rule delete: The MSB of the key will not be removed. 2912 * Access: WO 2913 */ 2914 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2915 2916 /* reg_ptce3_large_entry_key_id 2917 * Large entry key ID. 2918 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2919 * blocks. Must be different for different keys which have the same common 2920 * 6 key blocks (MSB, blocks 6..11) key within a region. 2921 * Range is 0..cap_max_pe_large_key_id - 1 2922 * Access: RW 2923 */ 2924 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2925 2926 /* reg_ptce3_action_pointer 2927 * Pointer to action. 2928 * Range is 0..cap_max_kvd_action_sets - 1 2929 * Access: RW 2930 */ 2931 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2932 2933 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2934 enum mlxsw_reg_ptce3_op op, 2935 u32 priority, 2936 const char *tcam_region_info, 2937 const char *key, u8 erp_id, 2938 u16 delta_start, u8 delta_mask, 2939 u8 delta_value, bool large_exists, 2940 u32 lkey_id, u32 action_pointer) 2941 { 2942 MLXSW_REG_ZERO(ptce3, payload); 2943 mlxsw_reg_ptce3_v_set(payload, valid); 2944 mlxsw_reg_ptce3_op_set(payload, op); 2945 mlxsw_reg_ptce3_priority_set(payload, priority); 2946 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2947 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2948 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2949 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2950 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2951 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2952 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2953 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2954 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2955 } 2956 2957 /* PERCR - Policy-Engine Region Configuration Register 2958 * --------------------------------------------------- 2959 * This register configures the region parameters. The region_id must be 2960 * allocated. 2961 */ 2962 #define MLXSW_REG_PERCR_ID 0x302A 2963 #define MLXSW_REG_PERCR_LEN 0x80 2964 2965 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2966 2967 /* reg_percr_region_id 2968 * Region identifier. 2969 * Range 0..cap_max_regions-1 2970 * Access: Index 2971 */ 2972 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2973 2974 /* reg_percr_atcam_ignore_prune 2975 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2976 * Access: RW 2977 */ 2978 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2979 2980 /* reg_percr_ctcam_ignore_prune 2981 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2982 * Access: RW 2983 */ 2984 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2985 2986 /* reg_percr_bf_bypass 2987 * Bloom filter bypass. 2988 * 0 - Bloom filter is used (default) 2989 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2990 * region_id or eRP. See PERPT.bf_bypass 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 2994 2995 /* reg_percr_master_mask 2996 * Master mask. Logical OR mask of all masks of all rules of a region 2997 * (both A-TCAM and C-TCAM). When there are no eRPs 2998 * (erpt_pointer_valid = 0), then this provides the mask. 2999 * Access: RW 3000 */ 3001 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3002 3003 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3004 { 3005 MLXSW_REG_ZERO(percr, payload); 3006 mlxsw_reg_percr_region_id_set(payload, region_id); 3007 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3008 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3009 mlxsw_reg_percr_bf_bypass_set(payload, false); 3010 } 3011 3012 /* PERERP - Policy-Engine Region eRP Register 3013 * ------------------------------------------ 3014 * This register configures the region eRP. The region_id must be 3015 * allocated. 3016 */ 3017 #define MLXSW_REG_PERERP_ID 0x302B 3018 #define MLXSW_REG_PERERP_LEN 0x1C 3019 3020 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3021 3022 /* reg_pererp_region_id 3023 * Region identifier. 3024 * Range 0..cap_max_regions-1 3025 * Access: Index 3026 */ 3027 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3028 3029 /* reg_pererp_ctcam_le 3030 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3031 * Access: RW 3032 */ 3033 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3034 3035 /* reg_pererp_erpt_pointer_valid 3036 * erpt_pointer is valid. 3037 * Access: RW 3038 */ 3039 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3040 3041 /* reg_pererp_erpt_bank_pointer 3042 * Pointer to eRP table bank. May be modified at any time. 3043 * Range 0..cap_max_erp_table_banks-1 3044 * Reserved when erpt_pointer_valid = 0 3045 */ 3046 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3047 3048 /* reg_pererp_erpt_pointer 3049 * Pointer to eRP table within the eRP bank. Can be changed for an 3050 * existing region. 3051 * Range 0..cap_max_erp_table_size-1 3052 * Reserved when erpt_pointer_valid = 0 3053 * Access: RW 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3056 3057 /* reg_pererp_erpt_vector 3058 * Vector of allowed eRP indexes starting from erpt_pointer within the 3059 * erpt_bank_pointer. Next entries will be in next bank. 3060 * Note that eRP index is used and not eRP ID. 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3065 3066 /* reg_pererp_master_rp_id 3067 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3068 * for the lookup. Can be changed for an existing region. 3069 * Reserved when erpt_pointer_valid = 1 3070 * Access: RW 3071 */ 3072 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3073 3074 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3075 unsigned long *erp_vector, 3076 unsigned long size) 3077 { 3078 unsigned long bit; 3079 3080 for_each_set_bit(bit, erp_vector, size) 3081 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3082 } 3083 3084 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3085 bool ctcam_le, bool erpt_pointer_valid, 3086 u8 erpt_bank_pointer, u8 erpt_pointer, 3087 u8 master_rp_id) 3088 { 3089 MLXSW_REG_ZERO(pererp, payload); 3090 mlxsw_reg_pererp_region_id_set(payload, region_id); 3091 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3092 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3093 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3094 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3095 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3096 } 3097 3098 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3099 * ---------------------------------------------------------------- 3100 * This register configures the Bloom filter entries. 3101 */ 3102 #define MLXSW_REG_PEABFE_ID 0x3022 3103 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3104 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3105 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3106 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3107 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3108 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3109 3110 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3111 3112 /* reg_peabfe_size 3113 * Number of BF entries to be updated. 3114 * Range 1..256 3115 * Access: Op 3116 */ 3117 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3118 3119 /* reg_peabfe_bf_entry_state 3120 * Bloom filter state 3121 * 0 - Clear 3122 * 1 - Set 3123 * Access: RW 3124 */ 3125 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3126 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3127 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3128 3129 /* reg_peabfe_bf_entry_bank 3130 * Bloom filter bank ID 3131 * Range 0..cap_max_erp_table_banks-1 3132 * Access: Index 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3135 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_index 3139 * Bloom filter entry index 3140 * Range 0..2^cap_max_bf_log-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3144 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 static inline void mlxsw_reg_peabfe_pack(char *payload) 3148 { 3149 MLXSW_REG_ZERO(peabfe, payload); 3150 } 3151 3152 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3153 u8 state, u8 bank, u32 bf_index) 3154 { 3155 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3156 3157 if (rec_index >= num_rec) 3158 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3159 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3160 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3161 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3162 } 3163 3164 /* IEDR - Infrastructure Entry Delete Register 3165 * ---------------------------------------------------- 3166 * This register is used for deleting entries from the entry tables. 3167 * It is legitimate to attempt to delete a nonexisting entry (the device will 3168 * respond as a good flow). 3169 */ 3170 #define MLXSW_REG_IEDR_ID 0x3804 3171 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3172 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3173 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3174 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3175 MLXSW_REG_IEDR_REC_LEN * \ 3176 MLXSW_REG_IEDR_REC_MAX_COUNT) 3177 3178 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3179 3180 /* reg_iedr_num_rec 3181 * Number of records. 3182 * Access: OP 3183 */ 3184 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3185 3186 /* reg_iedr_rec_type 3187 * Resource type. 3188 * Access: OP 3189 */ 3190 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3191 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3192 3193 /* reg_iedr_rec_size 3194 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3195 * Access: OP 3196 */ 3197 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3198 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3199 3200 /* reg_iedr_rec_index_start 3201 * Resource index start. 3202 * Access: OP 3203 */ 3204 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3205 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3206 3207 static inline void mlxsw_reg_iedr_pack(char *payload) 3208 { 3209 MLXSW_REG_ZERO(iedr, payload); 3210 } 3211 3212 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3213 u8 rec_type, u16 rec_size, 3214 u32 rec_index_start) 3215 { 3216 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3217 3218 if (rec_index >= num_rec) 3219 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3220 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3221 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3222 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3223 } 3224 3225 /* QPTS - QoS Priority Trust State Register 3226 * ---------------------------------------- 3227 * This register controls the port policy to calculate the switch priority and 3228 * packet color based on incoming packet fields. 3229 */ 3230 #define MLXSW_REG_QPTS_ID 0x4002 3231 #define MLXSW_REG_QPTS_LEN 0x8 3232 3233 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3234 3235 /* reg_qpts_local_port 3236 * Local port number. 3237 * Access: Index 3238 * 3239 * Note: CPU port is supported. 3240 */ 3241 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3242 3243 enum mlxsw_reg_qpts_trust_state { 3244 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3245 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3246 }; 3247 3248 /* reg_qpts_trust_state 3249 * Trust state for a given port. 3250 * Access: RW 3251 */ 3252 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3253 3254 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3255 enum mlxsw_reg_qpts_trust_state ts) 3256 { 3257 MLXSW_REG_ZERO(qpts, payload); 3258 3259 mlxsw_reg_qpts_local_port_set(payload, local_port); 3260 mlxsw_reg_qpts_trust_state_set(payload, ts); 3261 } 3262 3263 /* QPCR - QoS Policer Configuration Register 3264 * ----------------------------------------- 3265 * The QPCR register is used to create policers - that limit 3266 * the rate of bytes or packets via some trap group. 3267 */ 3268 #define MLXSW_REG_QPCR_ID 0x4004 3269 #define MLXSW_REG_QPCR_LEN 0x28 3270 3271 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3272 3273 enum mlxsw_reg_qpcr_g { 3274 MLXSW_REG_QPCR_G_GLOBAL = 2, 3275 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3276 }; 3277 3278 /* reg_qpcr_g 3279 * The policer type. 3280 * Access: Index 3281 */ 3282 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3283 3284 /* reg_qpcr_pid 3285 * Policer ID. 3286 * Access: Index 3287 */ 3288 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3289 3290 /* reg_qpcr_color_aware 3291 * Is the policer aware of colors. 3292 * Must be 0 (unaware) for cpu port. 3293 * Access: RW for unbounded policer. RO for bounded policer. 3294 */ 3295 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3296 3297 /* reg_qpcr_bytes 3298 * Is policer limit is for bytes per sec or packets per sec. 3299 * 0 - packets 3300 * 1 - bytes 3301 * Access: RW for unbounded policer. RO for bounded policer. 3302 */ 3303 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3304 3305 enum mlxsw_reg_qpcr_ir_units { 3306 MLXSW_REG_QPCR_IR_UNITS_M, 3307 MLXSW_REG_QPCR_IR_UNITS_K, 3308 }; 3309 3310 /* reg_qpcr_ir_units 3311 * Policer's units for cir and eir fields (for bytes limits only) 3312 * 1 - 10^3 3313 * 0 - 10^6 3314 * Access: OP 3315 */ 3316 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3317 3318 enum mlxsw_reg_qpcr_rate_type { 3319 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3320 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3321 }; 3322 3323 /* reg_qpcr_rate_type 3324 * Policer can have one limit (single rate) or 2 limits with specific operation 3325 * for packets that exceed the lower rate but not the upper one. 3326 * (For cpu port must be single rate) 3327 * Access: RW for unbounded policer. RO for bounded policer. 3328 */ 3329 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3330 3331 /* reg_qpc_cbs 3332 * Policer's committed burst size. 3333 * The policer is working with time slices of 50 nano sec. By default every 3334 * slice is granted the proportionate share of the committed rate. If we want to 3335 * allow a slice to exceed that share (while still keeping the rate per sec) we 3336 * can allow burst. The burst size is between the default proportionate share 3337 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3338 * committed rate will result in exceeding the rate). The burst size must be a 3339 * log of 2 and will be determined by 2^cbs. 3340 * Access: RW 3341 */ 3342 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3343 3344 /* reg_qpcr_cir 3345 * Policer's committed rate. 3346 * The rate used for sungle rate, the lower rate for double rate. 3347 * For bytes limits, the rate will be this value * the unit from ir_units. 3348 * (Resolution error is up to 1%). 3349 * Access: RW 3350 */ 3351 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3352 3353 /* reg_qpcr_eir 3354 * Policer's exceed rate. 3355 * The higher rate for double rate, reserved for single rate. 3356 * Lower rate for double rate policer. 3357 * For bytes limits, the rate will be this value * the unit from ir_units. 3358 * (Resolution error is up to 1%). 3359 * Access: RW 3360 */ 3361 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3362 3363 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3364 3365 /* reg_qpcr_exceed_action. 3366 * What to do with packets between the 2 limits for double rate. 3367 * Access: RW for unbounded policer. RO for bounded policer. 3368 */ 3369 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3370 3371 enum mlxsw_reg_qpcr_action { 3372 /* Discard */ 3373 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3374 /* Forward and set color to red. 3375 * If the packet is intended to cpu port, it will be dropped. 3376 */ 3377 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3378 }; 3379 3380 /* reg_qpcr_violate_action 3381 * What to do with packets that cross the cir limit (for single rate) or the eir 3382 * limit (for double rate). 3383 * Access: RW for unbounded policer. RO for bounded policer. 3384 */ 3385 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3386 3387 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3388 enum mlxsw_reg_qpcr_ir_units ir_units, 3389 bool bytes, u32 cir, u16 cbs) 3390 { 3391 MLXSW_REG_ZERO(qpcr, payload); 3392 mlxsw_reg_qpcr_pid_set(payload, pid); 3393 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3394 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3395 mlxsw_reg_qpcr_violate_action_set(payload, 3396 MLXSW_REG_QPCR_ACTION_DISCARD); 3397 mlxsw_reg_qpcr_cir_set(payload, cir); 3398 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3399 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3400 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3401 } 3402 3403 /* QTCT - QoS Switch Traffic Class Table 3404 * ------------------------------------- 3405 * Configures the mapping between the packet switch priority and the 3406 * traffic class on the transmit port. 3407 */ 3408 #define MLXSW_REG_QTCT_ID 0x400A 3409 #define MLXSW_REG_QTCT_LEN 0x08 3410 3411 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3412 3413 /* reg_qtct_local_port 3414 * Local port number. 3415 * Access: Index 3416 * 3417 * Note: CPU port is not supported. 3418 */ 3419 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3420 3421 /* reg_qtct_sub_port 3422 * Virtual port within the physical port. 3423 * Should be set to 0 when virtual ports are not enabled on the port. 3424 * Access: Index 3425 */ 3426 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3427 3428 /* reg_qtct_switch_prio 3429 * Switch priority. 3430 * Access: Index 3431 */ 3432 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3433 3434 /* reg_qtct_tclass 3435 * Traffic class. 3436 * Default values: 3437 * switch_prio 0 : tclass 1 3438 * switch_prio 1 : tclass 0 3439 * switch_prio i : tclass i, for i > 1 3440 * Access: RW 3441 */ 3442 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3443 3444 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3445 u8 switch_prio, u8 tclass) 3446 { 3447 MLXSW_REG_ZERO(qtct, payload); 3448 mlxsw_reg_qtct_local_port_set(payload, local_port); 3449 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3450 mlxsw_reg_qtct_tclass_set(payload, tclass); 3451 } 3452 3453 /* QEEC - QoS ETS Element Configuration Register 3454 * --------------------------------------------- 3455 * Configures the ETS elements. 3456 */ 3457 #define MLXSW_REG_QEEC_ID 0x400D 3458 #define MLXSW_REG_QEEC_LEN 0x20 3459 3460 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3461 3462 /* reg_qeec_local_port 3463 * Local port number. 3464 * Access: Index 3465 * 3466 * Note: CPU port is supported. 3467 */ 3468 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3469 3470 enum mlxsw_reg_qeec_hr { 3471 MLXSW_REG_QEEC_HIERARCY_PORT, 3472 MLXSW_REG_QEEC_HIERARCY_GROUP, 3473 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3474 MLXSW_REG_QEEC_HIERARCY_TC, 3475 }; 3476 3477 /* reg_qeec_element_hierarchy 3478 * 0 - Port 3479 * 1 - Group 3480 * 2 - Subgroup 3481 * 3 - Traffic Class 3482 * Access: Index 3483 */ 3484 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3485 3486 /* reg_qeec_element_index 3487 * The index of the element in the hierarchy. 3488 * Access: Index 3489 */ 3490 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3491 3492 /* reg_qeec_next_element_index 3493 * The index of the next (lower) element in the hierarchy. 3494 * Access: RW 3495 * 3496 * Note: Reserved for element_hierarchy 0. 3497 */ 3498 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3499 3500 /* reg_qeec_mise 3501 * Min shaper configuration enable. Enables configuration of the min 3502 * shaper on this ETS element 3503 * 0 - Disable 3504 * 1 - Enable 3505 * Access: RW 3506 */ 3507 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3508 3509 enum { 3510 MLXSW_REG_QEEC_BYTES_MODE, 3511 MLXSW_REG_QEEC_PACKETS_MODE, 3512 }; 3513 3514 /* reg_qeec_pb 3515 * Packets or bytes mode. 3516 * 0 - Bytes mode 3517 * 1 - Packets mode 3518 * Access: RW 3519 * 3520 * Note: Used for max shaper configuration. For Spectrum, packets mode 3521 * is supported only for traffic classes of CPU port. 3522 */ 3523 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3524 3525 /* The smallest permitted min shaper rate. */ 3526 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3527 3528 /* reg_qeec_min_shaper_rate 3529 * Min shaper information rate. 3530 * For CPU port, can only be configured for port hierarchy. 3531 * When in bytes mode, value is specified in units of 1000bps. 3532 * Access: RW 3533 */ 3534 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3535 3536 /* reg_qeec_mase 3537 * Max shaper configuration enable. Enables configuration of the max 3538 * shaper on this ETS element. 3539 * 0 - Disable 3540 * 1 - Enable 3541 * Access: RW 3542 */ 3543 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3544 3545 /* A large max rate will disable the max shaper. */ 3546 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3547 3548 /* reg_qeec_max_shaper_rate 3549 * Max shaper information rate. 3550 * For CPU port, can only be configured for port hierarchy. 3551 * When in bytes mode, value is specified in units of 1000bps. 3552 * Access: RW 3553 */ 3554 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3555 3556 /* reg_qeec_de 3557 * DWRR configuration enable. Enables configuration of the dwrr and 3558 * dwrr_weight. 3559 * 0 - Disable 3560 * 1 - Enable 3561 * Access: RW 3562 */ 3563 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3564 3565 /* reg_qeec_dwrr 3566 * Transmission selection algorithm to use on the link going down from 3567 * the ETS element. 3568 * 0 - Strict priority 3569 * 1 - DWRR 3570 * Access: RW 3571 */ 3572 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3573 3574 /* reg_qeec_dwrr_weight 3575 * DWRR weight on the link going down from the ETS element. The 3576 * percentage of bandwidth guaranteed to an ETS element within 3577 * its hierarchy. The sum of all weights across all ETS elements 3578 * within one hierarchy should be equal to 100. Reserved when 3579 * transmission selection algorithm is strict priority. 3580 * Access: RW 3581 */ 3582 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3583 3584 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3585 enum mlxsw_reg_qeec_hr hr, u8 index, 3586 u8 next_index) 3587 { 3588 MLXSW_REG_ZERO(qeec, payload); 3589 mlxsw_reg_qeec_local_port_set(payload, local_port); 3590 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3591 mlxsw_reg_qeec_element_index_set(payload, index); 3592 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3593 } 3594 3595 /* QRWE - QoS ReWrite Enable 3596 * ------------------------- 3597 * This register configures the rewrite enable per receive port. 3598 */ 3599 #define MLXSW_REG_QRWE_ID 0x400F 3600 #define MLXSW_REG_QRWE_LEN 0x08 3601 3602 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3603 3604 /* reg_qrwe_local_port 3605 * Local port number. 3606 * Access: Index 3607 * 3608 * Note: CPU port is supported. No support for router port. 3609 */ 3610 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3611 3612 /* reg_qrwe_dscp 3613 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3614 * Access: RW 3615 */ 3616 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3617 3618 /* reg_qrwe_pcp 3619 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3620 * Access: RW 3621 */ 3622 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3623 3624 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3625 bool rewrite_pcp, bool rewrite_dscp) 3626 { 3627 MLXSW_REG_ZERO(qrwe, payload); 3628 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3629 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3630 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3631 } 3632 3633 /* QPDSM - QoS Priority to DSCP Mapping 3634 * ------------------------------------ 3635 * QoS Priority to DSCP Mapping Register 3636 */ 3637 #define MLXSW_REG_QPDSM_ID 0x4011 3638 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3639 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3640 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3641 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3642 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3643 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3644 3645 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3646 3647 /* reg_qpdsm_local_port 3648 * Local Port. Supported for data packets from CPU port. 3649 * Access: Index 3650 */ 3651 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3652 3653 /* reg_qpdsm_prio_entry_color0_e 3654 * Enable update of the entry for color 0 and a given port. 3655 * Access: WO 3656 */ 3657 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3658 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3659 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3660 3661 /* reg_qpdsm_prio_entry_color0_dscp 3662 * DSCP field in the outer label of the packet for color 0 and a given port. 3663 * Reserved when e=0. 3664 * Access: RW 3665 */ 3666 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3667 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3668 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3669 3670 /* reg_qpdsm_prio_entry_color1_e 3671 * Enable update of the entry for color 1 and a given port. 3672 * Access: WO 3673 */ 3674 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3675 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3676 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3677 3678 /* reg_qpdsm_prio_entry_color1_dscp 3679 * DSCP field in the outer label of the packet for color 1 and a given port. 3680 * Reserved when e=0. 3681 * Access: RW 3682 */ 3683 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3684 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3685 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3686 3687 /* reg_qpdsm_prio_entry_color2_e 3688 * Enable update of the entry for color 2 and a given port. 3689 * Access: WO 3690 */ 3691 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3692 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3693 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3694 3695 /* reg_qpdsm_prio_entry_color2_dscp 3696 * DSCP field in the outer label of the packet for color 2 and a given port. 3697 * Reserved when e=0. 3698 * Access: RW 3699 */ 3700 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3701 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3702 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3703 3704 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3705 { 3706 MLXSW_REG_ZERO(qpdsm, payload); 3707 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3708 } 3709 3710 static inline void 3711 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3712 { 3713 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3714 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3715 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3716 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3717 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3718 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3719 } 3720 3721 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3722 * -------------------------------------------------- 3723 * This register controls the mapping from DSCP field to 3724 * Switch Priority for IP packets. 3725 */ 3726 #define MLXSW_REG_QPDPM_ID 0x4013 3727 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3728 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3729 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3730 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3731 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3732 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3733 3734 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3735 3736 /* reg_qpdpm_local_port 3737 * Local Port. Supported for data packets from CPU port. 3738 * Access: Index 3739 */ 3740 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3741 3742 /* reg_qpdpm_dscp_e 3743 * Enable update of the specific entry. When cleared, the switch_prio and color 3744 * fields are ignored and the previous switch_prio and color values are 3745 * preserved. 3746 * Access: WO 3747 */ 3748 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3749 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3750 3751 /* reg_qpdpm_dscp_prio 3752 * The new Switch Priority value for the relevant DSCP value. 3753 * Access: RW 3754 */ 3755 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3756 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3757 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3758 3759 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3760 { 3761 MLXSW_REG_ZERO(qpdpm, payload); 3762 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3763 } 3764 3765 static inline void 3766 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3767 { 3768 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3769 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3770 } 3771 3772 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3773 * ------------------------------------------------------------------ 3774 * This register configures if the Switch Priority to Traffic Class mapping is 3775 * based on Multicast packet indication. If so, then multicast packets will get 3776 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3777 * QTCT. 3778 * By default, Switch Priority to Traffic Class mapping is not based on 3779 * Multicast packet indication. 3780 */ 3781 #define MLXSW_REG_QTCTM_ID 0x401A 3782 #define MLXSW_REG_QTCTM_LEN 0x08 3783 3784 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3785 3786 /* reg_qtctm_local_port 3787 * Local port number. 3788 * No support for CPU port. 3789 * Access: Index 3790 */ 3791 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3792 3793 /* reg_qtctm_mc 3794 * Multicast Mode 3795 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3796 * indication (default is 0, not based on Multicast packet indication). 3797 */ 3798 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3799 3800 static inline void 3801 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3802 { 3803 MLXSW_REG_ZERO(qtctm, payload); 3804 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3805 mlxsw_reg_qtctm_mc_set(payload, mc); 3806 } 3807 3808 /* PMLP - Ports Module to Local Port Register 3809 * ------------------------------------------ 3810 * Configures the assignment of modules to local ports. 3811 */ 3812 #define MLXSW_REG_PMLP_ID 0x5002 3813 #define MLXSW_REG_PMLP_LEN 0x40 3814 3815 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3816 3817 /* reg_pmlp_rxtx 3818 * 0 - Tx value is used for both Tx and Rx. 3819 * 1 - Rx value is taken from a separte field. 3820 * Access: RW 3821 */ 3822 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3823 3824 /* reg_pmlp_local_port 3825 * Local port number. 3826 * Access: Index 3827 */ 3828 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3829 3830 /* reg_pmlp_width 3831 * 0 - Unmap local port. 3832 * 1 - Lane 0 is used. 3833 * 2 - Lanes 0 and 1 are used. 3834 * 4 - Lanes 0, 1, 2 and 3 are used. 3835 * Access: RW 3836 */ 3837 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3838 3839 /* reg_pmlp_module 3840 * Module number. 3841 * Access: RW 3842 */ 3843 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3844 3845 /* reg_pmlp_tx_lane 3846 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3847 * Access: RW 3848 */ 3849 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3850 3851 /* reg_pmlp_rx_lane 3852 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3853 * equal to Tx lane. 3854 * Access: RW 3855 */ 3856 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3857 3858 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3859 { 3860 MLXSW_REG_ZERO(pmlp, payload); 3861 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3862 } 3863 3864 /* PMTU - Port MTU Register 3865 * ------------------------ 3866 * Configures and reports the port MTU. 3867 */ 3868 #define MLXSW_REG_PMTU_ID 0x5003 3869 #define MLXSW_REG_PMTU_LEN 0x10 3870 3871 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3872 3873 /* reg_pmtu_local_port 3874 * Local port number. 3875 * Access: Index 3876 */ 3877 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3878 3879 /* reg_pmtu_max_mtu 3880 * Maximum MTU. 3881 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3882 * reported, otherwise the minimum between the max_mtu of the different 3883 * types is reported. 3884 * Access: RO 3885 */ 3886 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3887 3888 /* reg_pmtu_admin_mtu 3889 * MTU value to set port to. Must be smaller or equal to max_mtu. 3890 * Note: If port type is Infiniband, then port must be disabled, when its 3891 * MTU is set. 3892 * Access: RW 3893 */ 3894 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3895 3896 /* reg_pmtu_oper_mtu 3897 * The actual MTU configured on the port. Packets exceeding this size 3898 * will be dropped. 3899 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3900 * oper_mtu might be smaller than admin_mtu. 3901 * Access: RO 3902 */ 3903 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3904 3905 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3906 u16 new_mtu) 3907 { 3908 MLXSW_REG_ZERO(pmtu, payload); 3909 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3910 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3911 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3912 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3913 } 3914 3915 /* PTYS - Port Type and Speed Register 3916 * ----------------------------------- 3917 * Configures and reports the port speed type. 3918 * 3919 * Note: When set while the link is up, the changes will not take effect 3920 * until the port transitions from down to up state. 3921 */ 3922 #define MLXSW_REG_PTYS_ID 0x5004 3923 #define MLXSW_REG_PTYS_LEN 0x40 3924 3925 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3926 3927 /* an_disable_admin 3928 * Auto negotiation disable administrative configuration 3929 * 0 - Device doesn't support AN disable. 3930 * 1 - Device supports AN disable. 3931 * Access: RW 3932 */ 3933 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3934 3935 /* reg_ptys_local_port 3936 * Local port number. 3937 * Access: Index 3938 */ 3939 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3940 3941 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3942 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3943 3944 /* reg_ptys_proto_mask 3945 * Protocol mask. Indicates which protocol is used. 3946 * 0 - Infiniband. 3947 * 1 - Fibre Channel. 3948 * 2 - Ethernet. 3949 * Access: Index 3950 */ 3951 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3952 3953 enum { 3954 MLXSW_REG_PTYS_AN_STATUS_NA, 3955 MLXSW_REG_PTYS_AN_STATUS_OK, 3956 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3957 }; 3958 3959 /* reg_ptys_an_status 3960 * Autonegotiation status. 3961 * Access: RO 3962 */ 3963 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3964 3965 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3966 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3967 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3968 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3969 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3970 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3971 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 3972 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 3973 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 3974 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 3975 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 3976 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 3977 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 3978 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 3979 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 3980 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 3981 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 3982 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 3983 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 3984 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 3985 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 3986 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 3987 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 3988 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 3989 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 3990 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 3991 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 3992 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 3993 3994 /* reg_ptys_eth_proto_cap 3995 * Ethernet port supported speeds and protocols. 3996 * Access: RO 3997 */ 3998 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 3999 4000 /* reg_ptys_ib_link_width_cap 4001 * IB port supported widths. 4002 * Access: RO 4003 */ 4004 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4005 4006 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4007 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4008 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4009 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4010 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4011 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4012 4013 /* reg_ptys_ib_proto_cap 4014 * IB port supported speeds and protocols. 4015 * Access: RO 4016 */ 4017 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4018 4019 /* reg_ptys_eth_proto_admin 4020 * Speed and protocol to set port to. 4021 * Access: RW 4022 */ 4023 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4024 4025 /* reg_ptys_ib_link_width_admin 4026 * IB width to set port to. 4027 * Access: RW 4028 */ 4029 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4030 4031 /* reg_ptys_ib_proto_admin 4032 * IB speeds and protocols to set port to. 4033 * Access: RW 4034 */ 4035 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4036 4037 /* reg_ptys_eth_proto_oper 4038 * The current speed and protocol configured for the port. 4039 * Access: RO 4040 */ 4041 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4042 4043 /* reg_ptys_ib_link_width_oper 4044 * The current IB width to set port to. 4045 * Access: RO 4046 */ 4047 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4048 4049 /* reg_ptys_ib_proto_oper 4050 * The current IB speed and protocol. 4051 * Access: RO 4052 */ 4053 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4054 4055 /* reg_ptys_eth_proto_lp_advertise 4056 * The protocols that were advertised by the link partner during 4057 * autonegotiation. 4058 * Access: RO 4059 */ 4060 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 4061 4062 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4063 u32 proto_admin, bool autoneg) 4064 { 4065 MLXSW_REG_ZERO(ptys, payload); 4066 mlxsw_reg_ptys_local_port_set(payload, local_port); 4067 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4068 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4069 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4070 } 4071 4072 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4073 u32 *p_eth_proto_cap, 4074 u32 *p_eth_proto_adm, 4075 u32 *p_eth_proto_oper) 4076 { 4077 if (p_eth_proto_cap) 4078 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 4079 if (p_eth_proto_adm) 4080 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 4081 if (p_eth_proto_oper) 4082 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 4083 } 4084 4085 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4086 u16 proto_admin, u16 link_width) 4087 { 4088 MLXSW_REG_ZERO(ptys, payload); 4089 mlxsw_reg_ptys_local_port_set(payload, local_port); 4090 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4091 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4092 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4093 } 4094 4095 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4096 u16 *p_ib_link_width_cap, 4097 u16 *p_ib_proto_oper, 4098 u16 *p_ib_link_width_oper) 4099 { 4100 if (p_ib_proto_cap) 4101 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4102 if (p_ib_link_width_cap) 4103 *p_ib_link_width_cap = 4104 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4105 if (p_ib_proto_oper) 4106 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4107 if (p_ib_link_width_oper) 4108 *p_ib_link_width_oper = 4109 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4110 } 4111 4112 /* PPAD - Port Physical Address Register 4113 * ------------------------------------- 4114 * The PPAD register configures the per port physical MAC address. 4115 */ 4116 #define MLXSW_REG_PPAD_ID 0x5005 4117 #define MLXSW_REG_PPAD_LEN 0x10 4118 4119 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4120 4121 /* reg_ppad_single_base_mac 4122 * 0: base_mac, local port should be 0 and mac[7:0] is 4123 * reserved. HW will set incremental 4124 * 1: single_mac - mac of the local_port 4125 * Access: RW 4126 */ 4127 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4128 4129 /* reg_ppad_local_port 4130 * port number, if single_base_mac = 0 then local_port is reserved 4131 * Access: RW 4132 */ 4133 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4134 4135 /* reg_ppad_mac 4136 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4137 * If single_base_mac = 1 - the per port MAC address 4138 * Access: RW 4139 */ 4140 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4141 4142 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4143 u8 local_port) 4144 { 4145 MLXSW_REG_ZERO(ppad, payload); 4146 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4147 mlxsw_reg_ppad_local_port_set(payload, local_port); 4148 } 4149 4150 /* PAOS - Ports Administrative and Operational Status Register 4151 * ----------------------------------------------------------- 4152 * Configures and retrieves per port administrative and operational status. 4153 */ 4154 #define MLXSW_REG_PAOS_ID 0x5006 4155 #define MLXSW_REG_PAOS_LEN 0x10 4156 4157 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4158 4159 /* reg_paos_swid 4160 * Switch partition ID with which to associate the port. 4161 * Note: while external ports uses unique local port numbers (and thus swid is 4162 * redundant), router ports use the same local port number where swid is the 4163 * only indication for the relevant port. 4164 * Access: Index 4165 */ 4166 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4167 4168 /* reg_paos_local_port 4169 * Local port number. 4170 * Access: Index 4171 */ 4172 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4173 4174 /* reg_paos_admin_status 4175 * Port administrative state (the desired state of the port): 4176 * 1 - Up. 4177 * 2 - Down. 4178 * 3 - Up once. This means that in case of link failure, the port won't go 4179 * into polling mode, but will wait to be re-enabled by software. 4180 * 4 - Disabled by system. Can only be set by hardware. 4181 * Access: RW 4182 */ 4183 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4184 4185 /* reg_paos_oper_status 4186 * Port operational state (the current state): 4187 * 1 - Up. 4188 * 2 - Down. 4189 * 3 - Down by port failure. This means that the device will not let the 4190 * port up again until explicitly specified by software. 4191 * Access: RO 4192 */ 4193 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4194 4195 /* reg_paos_ase 4196 * Admin state update enabled. 4197 * Access: WO 4198 */ 4199 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4200 4201 /* reg_paos_ee 4202 * Event update enable. If this bit is set, event generation will be 4203 * updated based on the e field. 4204 * Access: WO 4205 */ 4206 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4207 4208 /* reg_paos_e 4209 * Event generation on operational state change: 4210 * 0 - Do not generate event. 4211 * 1 - Generate Event. 4212 * 2 - Generate Single Event. 4213 * Access: RW 4214 */ 4215 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4216 4217 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4218 enum mlxsw_port_admin_status status) 4219 { 4220 MLXSW_REG_ZERO(paos, payload); 4221 mlxsw_reg_paos_swid_set(payload, 0); 4222 mlxsw_reg_paos_local_port_set(payload, local_port); 4223 mlxsw_reg_paos_admin_status_set(payload, status); 4224 mlxsw_reg_paos_oper_status_set(payload, 0); 4225 mlxsw_reg_paos_ase_set(payload, 1); 4226 mlxsw_reg_paos_ee_set(payload, 1); 4227 mlxsw_reg_paos_e_set(payload, 1); 4228 } 4229 4230 /* PFCC - Ports Flow Control Configuration Register 4231 * ------------------------------------------------ 4232 * Configures and retrieves the per port flow control configuration. 4233 */ 4234 #define MLXSW_REG_PFCC_ID 0x5007 4235 #define MLXSW_REG_PFCC_LEN 0x20 4236 4237 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4238 4239 /* reg_pfcc_local_port 4240 * Local port number. 4241 * Access: Index 4242 */ 4243 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4244 4245 /* reg_pfcc_pnat 4246 * Port number access type. Determines the way local_port is interpreted: 4247 * 0 - Local port number. 4248 * 1 - IB / label port number. 4249 * Access: Index 4250 */ 4251 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4252 4253 /* reg_pfcc_shl_cap 4254 * Send to higher layers capabilities: 4255 * 0 - No capability of sending Pause and PFC frames to higher layers. 4256 * 1 - Device has capability of sending Pause and PFC frames to higher 4257 * layers. 4258 * Access: RO 4259 */ 4260 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4261 4262 /* reg_pfcc_shl_opr 4263 * Send to higher layers operation: 4264 * 0 - Pause and PFC frames are handled by the port (default). 4265 * 1 - Pause and PFC frames are handled by the port and also sent to 4266 * higher layers. Only valid if shl_cap = 1. 4267 * Access: RW 4268 */ 4269 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4270 4271 /* reg_pfcc_ppan 4272 * Pause policy auto negotiation. 4273 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4274 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4275 * based on the auto-negotiation resolution. 4276 * Access: RW 4277 * 4278 * Note: The auto-negotiation advertisement is set according to pptx and 4279 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4280 */ 4281 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4282 4283 /* reg_pfcc_prio_mask_tx 4284 * Bit per priority indicating if Tx flow control policy should be 4285 * updated based on bit pfctx. 4286 * Access: WO 4287 */ 4288 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4289 4290 /* reg_pfcc_prio_mask_rx 4291 * Bit per priority indicating if Rx flow control policy should be 4292 * updated based on bit pfcrx. 4293 * Access: WO 4294 */ 4295 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4296 4297 /* reg_pfcc_pptx 4298 * Admin Pause policy on Tx. 4299 * 0 - Never generate Pause frames (default). 4300 * 1 - Generate Pause frames according to Rx buffer threshold. 4301 * Access: RW 4302 */ 4303 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4304 4305 /* reg_pfcc_aptx 4306 * Active (operational) Pause policy on Tx. 4307 * 0 - Never generate Pause frames. 4308 * 1 - Generate Pause frames according to Rx buffer threshold. 4309 * Access: RO 4310 */ 4311 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4312 4313 /* reg_pfcc_pfctx 4314 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4315 * 0 - Never generate priority Pause frames on the specified priority 4316 * (default). 4317 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4318 * the specified priority. 4319 * Access: RW 4320 * 4321 * Note: pfctx and pptx must be mutually exclusive. 4322 */ 4323 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4324 4325 /* reg_pfcc_pprx 4326 * Admin Pause policy on Rx. 4327 * 0 - Ignore received Pause frames (default). 4328 * 1 - Respect received Pause frames. 4329 * Access: RW 4330 */ 4331 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4332 4333 /* reg_pfcc_aprx 4334 * Active (operational) Pause policy on Rx. 4335 * 0 - Ignore received Pause frames. 4336 * 1 - Respect received Pause frames. 4337 * Access: RO 4338 */ 4339 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4340 4341 /* reg_pfcc_pfcrx 4342 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4343 * 0 - Ignore incoming priority Pause frames on the specified priority 4344 * (default). 4345 * 1 - Respect incoming priority Pause frames on the specified priority. 4346 * Access: RW 4347 */ 4348 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4349 4350 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4351 4352 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4353 { 4354 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4355 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4356 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4357 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4358 } 4359 4360 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4361 { 4362 MLXSW_REG_ZERO(pfcc, payload); 4363 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4364 } 4365 4366 /* PPCNT - Ports Performance Counters Register 4367 * ------------------------------------------- 4368 * The PPCNT register retrieves per port performance counters. 4369 */ 4370 #define MLXSW_REG_PPCNT_ID 0x5008 4371 #define MLXSW_REG_PPCNT_LEN 0x100 4372 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4373 4374 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4375 4376 /* reg_ppcnt_swid 4377 * For HCA: must be always 0. 4378 * Switch partition ID to associate port with. 4379 * Switch partitions are numbered from 0 to 7 inclusively. 4380 * Switch partition 254 indicates stacking ports. 4381 * Switch partition 255 indicates all switch partitions. 4382 * Only valid on Set() operation with local_port=255. 4383 * Access: Index 4384 */ 4385 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4386 4387 /* reg_ppcnt_local_port 4388 * Local port number. 4389 * 255 indicates all ports on the device, and is only allowed 4390 * for Set() operation. 4391 * Access: Index 4392 */ 4393 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4394 4395 /* reg_ppcnt_pnat 4396 * Port number access type: 4397 * 0 - Local port number 4398 * 1 - IB port number 4399 * Access: Index 4400 */ 4401 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4402 4403 enum mlxsw_reg_ppcnt_grp { 4404 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4405 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4406 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4407 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4408 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4409 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4410 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4411 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4412 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4413 }; 4414 4415 /* reg_ppcnt_grp 4416 * Performance counter group. 4417 * Group 63 indicates all groups. Only valid on Set() operation with 4418 * clr bit set. 4419 * 0x0: IEEE 802.3 Counters 4420 * 0x1: RFC 2863 Counters 4421 * 0x2: RFC 2819 Counters 4422 * 0x3: RFC 3635 Counters 4423 * 0x5: Ethernet Extended Counters 4424 * 0x6: Ethernet Discard Counters 4425 * 0x8: Link Level Retransmission Counters 4426 * 0x10: Per Priority Counters 4427 * 0x11: Per Traffic Class Counters 4428 * 0x12: Physical Layer Counters 4429 * 0x13: Per Traffic Class Congestion Counters 4430 * Access: Index 4431 */ 4432 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4433 4434 /* reg_ppcnt_clr 4435 * Clear counters. Setting the clr bit will reset the counter value 4436 * for all counters in the counter group. This bit can be set 4437 * for both Set() and Get() operation. 4438 * Access: OP 4439 */ 4440 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4441 4442 /* reg_ppcnt_prio_tc 4443 * Priority for counter set that support per priority, valid values: 0-7. 4444 * Traffic class for counter set that support per traffic class, 4445 * valid values: 0- cap_max_tclass-1 . 4446 * For HCA: cap_max_tclass is always 8. 4447 * Otherwise must be 0. 4448 * Access: Index 4449 */ 4450 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4451 4452 /* Ethernet IEEE 802.3 Counter Group */ 4453 4454 /* reg_ppcnt_a_frames_transmitted_ok 4455 * Access: RO 4456 */ 4457 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4458 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4459 4460 /* reg_ppcnt_a_frames_received_ok 4461 * Access: RO 4462 */ 4463 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4464 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4465 4466 /* reg_ppcnt_a_frame_check_sequence_errors 4467 * Access: RO 4468 */ 4469 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4470 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4471 4472 /* reg_ppcnt_a_alignment_errors 4473 * Access: RO 4474 */ 4475 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4476 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4477 4478 /* reg_ppcnt_a_octets_transmitted_ok 4479 * Access: RO 4480 */ 4481 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4482 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4483 4484 /* reg_ppcnt_a_octets_received_ok 4485 * Access: RO 4486 */ 4487 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4488 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4489 4490 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4491 * Access: RO 4492 */ 4493 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4494 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4495 4496 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4497 * Access: RO 4498 */ 4499 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4500 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4501 4502 /* reg_ppcnt_a_multicast_frames_received_ok 4503 * Access: RO 4504 */ 4505 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4506 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4507 4508 /* reg_ppcnt_a_broadcast_frames_received_ok 4509 * Access: RO 4510 */ 4511 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4512 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4513 4514 /* reg_ppcnt_a_in_range_length_errors 4515 * Access: RO 4516 */ 4517 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4518 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4519 4520 /* reg_ppcnt_a_out_of_range_length_field 4521 * Access: RO 4522 */ 4523 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4524 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4525 4526 /* reg_ppcnt_a_frame_too_long_errors 4527 * Access: RO 4528 */ 4529 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4530 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4531 4532 /* reg_ppcnt_a_symbol_error_during_carrier 4533 * Access: RO 4534 */ 4535 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4536 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4537 4538 /* reg_ppcnt_a_mac_control_frames_transmitted 4539 * Access: RO 4540 */ 4541 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4542 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4543 4544 /* reg_ppcnt_a_mac_control_frames_received 4545 * Access: RO 4546 */ 4547 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4548 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4549 4550 /* reg_ppcnt_a_unsupported_opcodes_received 4551 * Access: RO 4552 */ 4553 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4554 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4555 4556 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4557 * Access: RO 4558 */ 4559 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4560 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4561 4562 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4563 * Access: RO 4564 */ 4565 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4566 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4567 4568 /* Ethernet RFC 2863 Counter Group */ 4569 4570 /* reg_ppcnt_if_in_discards 4571 * Access: RO 4572 */ 4573 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4574 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4575 4576 /* reg_ppcnt_if_out_discards 4577 * Access: RO 4578 */ 4579 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4580 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4581 4582 /* reg_ppcnt_if_out_errors 4583 * Access: RO 4584 */ 4585 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4586 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4587 4588 /* Ethernet RFC 2819 Counter Group */ 4589 4590 /* reg_ppcnt_ether_stats_undersize_pkts 4591 * Access: RO 4592 */ 4593 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4594 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4595 4596 /* reg_ppcnt_ether_stats_oversize_pkts 4597 * Access: RO 4598 */ 4599 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4600 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4601 4602 /* reg_ppcnt_ether_stats_fragments 4603 * Access: RO 4604 */ 4605 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4606 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4607 4608 /* reg_ppcnt_ether_stats_pkts64octets 4609 * Access: RO 4610 */ 4611 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4612 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4613 4614 /* reg_ppcnt_ether_stats_pkts65to127octets 4615 * Access: RO 4616 */ 4617 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4618 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4619 4620 /* reg_ppcnt_ether_stats_pkts128to255octets 4621 * Access: RO 4622 */ 4623 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4624 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4625 4626 /* reg_ppcnt_ether_stats_pkts256to511octets 4627 * Access: RO 4628 */ 4629 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4630 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4631 4632 /* reg_ppcnt_ether_stats_pkts512to1023octets 4633 * Access: RO 4634 */ 4635 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4636 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4637 4638 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4639 * Access: RO 4640 */ 4641 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4642 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4643 4644 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4645 * Access: RO 4646 */ 4647 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4648 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4649 4650 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4651 * Access: RO 4652 */ 4653 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4654 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4655 4656 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4657 * Access: RO 4658 */ 4659 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4660 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4661 4662 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4663 * Access: RO 4664 */ 4665 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4666 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4667 4668 /* Ethernet RFC 3635 Counter Group */ 4669 4670 /* reg_ppcnt_dot3stats_fcs_errors 4671 * Access: RO 4672 */ 4673 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4674 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4675 4676 /* reg_ppcnt_dot3stats_symbol_errors 4677 * Access: RO 4678 */ 4679 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4680 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4681 4682 /* reg_ppcnt_dot3control_in_unknown_opcodes 4683 * Access: RO 4684 */ 4685 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4686 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4687 4688 /* reg_ppcnt_dot3in_pause_frames 4689 * Access: RO 4690 */ 4691 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4692 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4693 4694 /* Ethernet Extended Counter Group Counters */ 4695 4696 /* reg_ppcnt_ecn_marked 4697 * Access: RO 4698 */ 4699 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4700 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4701 4702 /* Ethernet Discard Counter Group Counters */ 4703 4704 /* reg_ppcnt_ingress_general 4705 * Access: RO 4706 */ 4707 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4708 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4709 4710 /* reg_ppcnt_ingress_policy_engine 4711 * Access: RO 4712 */ 4713 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4714 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4715 4716 /* reg_ppcnt_ingress_vlan_membership 4717 * Access: RO 4718 */ 4719 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4720 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4721 4722 /* reg_ppcnt_ingress_tag_frame_type 4723 * Access: RO 4724 */ 4725 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4726 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4727 4728 /* reg_ppcnt_egress_vlan_membership 4729 * Access: RO 4730 */ 4731 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 4732 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4733 4734 /* reg_ppcnt_loopback_filter 4735 * Access: RO 4736 */ 4737 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 4738 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4739 4740 /* reg_ppcnt_egress_general 4741 * Access: RO 4742 */ 4743 MLXSW_ITEM64(reg, ppcnt, egress_general, 4744 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4745 4746 /* reg_ppcnt_egress_hoq 4747 * Access: RO 4748 */ 4749 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 4750 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4751 4752 /* reg_ppcnt_egress_policy_engine 4753 * Access: RO 4754 */ 4755 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 4756 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4757 4758 /* reg_ppcnt_ingress_tx_link_down 4759 * Access: RO 4760 */ 4761 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 4762 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4763 4764 /* reg_ppcnt_egress_stp_filter 4765 * Access: RO 4766 */ 4767 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 4768 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4769 4770 /* reg_ppcnt_egress_sll 4771 * Access: RO 4772 */ 4773 MLXSW_ITEM64(reg, ppcnt, egress_sll, 4774 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4775 4776 /* Ethernet Per Priority Group Counters */ 4777 4778 /* reg_ppcnt_rx_octets 4779 * Access: RO 4780 */ 4781 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4782 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4783 4784 /* reg_ppcnt_rx_frames 4785 * Access: RO 4786 */ 4787 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4788 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4789 4790 /* reg_ppcnt_tx_octets 4791 * Access: RO 4792 */ 4793 MLXSW_ITEM64(reg, ppcnt, tx_octets, 4794 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4795 4796 /* reg_ppcnt_tx_frames 4797 * Access: RO 4798 */ 4799 MLXSW_ITEM64(reg, ppcnt, tx_frames, 4800 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4801 4802 /* reg_ppcnt_rx_pause 4803 * Access: RO 4804 */ 4805 MLXSW_ITEM64(reg, ppcnt, rx_pause, 4806 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4807 4808 /* reg_ppcnt_rx_pause_duration 4809 * Access: RO 4810 */ 4811 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 4812 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4813 4814 /* reg_ppcnt_tx_pause 4815 * Access: RO 4816 */ 4817 MLXSW_ITEM64(reg, ppcnt, tx_pause, 4818 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4819 4820 /* reg_ppcnt_tx_pause_duration 4821 * Access: RO 4822 */ 4823 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 4824 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4825 4826 /* reg_ppcnt_rx_pause_transition 4827 * Access: RO 4828 */ 4829 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 4830 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4831 4832 /* Ethernet Per Traffic Group Counters */ 4833 4834 /* reg_ppcnt_tc_transmit_queue 4835 * Contains the transmit queue depth in cells of traffic class 4836 * selected by prio_tc and the port selected by local_port. 4837 * The field cannot be cleared. 4838 * Access: RO 4839 */ 4840 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 4841 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4842 4843 /* reg_ppcnt_tc_no_buffer_discard_uc 4844 * The number of unicast packets dropped due to lack of shared 4845 * buffer resources. 4846 * Access: RO 4847 */ 4848 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 4849 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4850 4851 /* Ethernet Per Traffic Class Congestion Group Counters */ 4852 4853 /* reg_ppcnt_wred_discard 4854 * Access: RO 4855 */ 4856 MLXSW_ITEM64(reg, ppcnt, wred_discard, 4857 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4858 4859 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 4860 enum mlxsw_reg_ppcnt_grp grp, 4861 u8 prio_tc) 4862 { 4863 MLXSW_REG_ZERO(ppcnt, payload); 4864 mlxsw_reg_ppcnt_swid_set(payload, 0); 4865 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 4866 mlxsw_reg_ppcnt_pnat_set(payload, 0); 4867 mlxsw_reg_ppcnt_grp_set(payload, grp); 4868 mlxsw_reg_ppcnt_clr_set(payload, 0); 4869 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 4870 } 4871 4872 /* PLIB - Port Local to InfiniBand Port 4873 * ------------------------------------ 4874 * The PLIB register performs mapping from Local Port into InfiniBand Port. 4875 */ 4876 #define MLXSW_REG_PLIB_ID 0x500A 4877 #define MLXSW_REG_PLIB_LEN 0x10 4878 4879 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 4880 4881 /* reg_plib_local_port 4882 * Local port number. 4883 * Access: Index 4884 */ 4885 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 4886 4887 /* reg_plib_ib_port 4888 * InfiniBand port remapping for local_port. 4889 * Access: RW 4890 */ 4891 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 4892 4893 /* PPTB - Port Prio To Buffer Register 4894 * ----------------------------------- 4895 * Configures the switch priority to buffer table. 4896 */ 4897 #define MLXSW_REG_PPTB_ID 0x500B 4898 #define MLXSW_REG_PPTB_LEN 0x10 4899 4900 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 4901 4902 enum { 4903 MLXSW_REG_PPTB_MM_UM, 4904 MLXSW_REG_PPTB_MM_UNICAST, 4905 MLXSW_REG_PPTB_MM_MULTICAST, 4906 }; 4907 4908 /* reg_pptb_mm 4909 * Mapping mode. 4910 * 0 - Map both unicast and multicast packets to the same buffer. 4911 * 1 - Map only unicast packets. 4912 * 2 - Map only multicast packets. 4913 * Access: Index 4914 * 4915 * Note: SwitchX-2 only supports the first option. 4916 */ 4917 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4918 4919 /* reg_pptb_local_port 4920 * Local port number. 4921 * Access: Index 4922 */ 4923 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 4924 4925 /* reg_pptb_um 4926 * Enables the update of the untagged_buf field. 4927 * Access: RW 4928 */ 4929 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 4930 4931 /* reg_pptb_pm 4932 * Enables the update of the prio_to_buff field. 4933 * Bit <i> is a flag for updating the mapping for switch priority <i>. 4934 * Access: RW 4935 */ 4936 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 4937 4938 /* reg_pptb_prio_to_buff 4939 * Mapping of switch priority <i> to one of the allocated receive port 4940 * buffers. 4941 * Access: RW 4942 */ 4943 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 4944 4945 /* reg_pptb_pm_msb 4946 * Enables the update of the prio_to_buff field. 4947 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 4948 * Access: RW 4949 */ 4950 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 4951 4952 /* reg_pptb_untagged_buff 4953 * Mapping of untagged frames to one of the allocated receive port buffers. 4954 * Access: RW 4955 * 4956 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 4957 * Spectrum, as it maps untagged packets based on the default switch priority. 4958 */ 4959 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 4960 4961 /* reg_pptb_prio_to_buff_msb 4962 * Mapping of switch priority <i+8> to one of the allocated receive port 4963 * buffers. 4964 * Access: RW 4965 */ 4966 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 4967 4968 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 4969 4970 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 4971 { 4972 MLXSW_REG_ZERO(pptb, payload); 4973 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 4974 mlxsw_reg_pptb_local_port_set(payload, local_port); 4975 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4976 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4977 } 4978 4979 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 4980 u8 buff) 4981 { 4982 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 4983 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 4984 } 4985 4986 /* PBMC - Port Buffer Management Control Register 4987 * ---------------------------------------------- 4988 * The PBMC register configures and retrieves the port packet buffer 4989 * allocation for different Prios, and the Pause threshold management. 4990 */ 4991 #define MLXSW_REG_PBMC_ID 0x500C 4992 #define MLXSW_REG_PBMC_LEN 0x6C 4993 4994 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 4995 4996 /* reg_pbmc_local_port 4997 * Local port number. 4998 * Access: Index 4999 */ 5000 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5001 5002 /* reg_pbmc_xoff_timer_value 5003 * When device generates a pause frame, it uses this value as the pause 5004 * timer (time for the peer port to pause in quota-512 bit time). 5005 * Access: RW 5006 */ 5007 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5008 5009 /* reg_pbmc_xoff_refresh 5010 * The time before a new pause frame should be sent to refresh the pause RW 5011 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5012 * time). 5013 * Access: RW 5014 */ 5015 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5016 5017 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5018 5019 /* reg_pbmc_buf_lossy 5020 * The field indicates if the buffer is lossy. 5021 * 0 - Lossless 5022 * 1 - Lossy 5023 * Access: RW 5024 */ 5025 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5026 5027 /* reg_pbmc_buf_epsb 5028 * Eligible for Port Shared buffer. 5029 * If epsb is set, packets assigned to buffer are allowed to insert the port 5030 * shared buffer. 5031 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5032 * Access: RW 5033 */ 5034 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5035 5036 /* reg_pbmc_buf_size 5037 * The part of the packet buffer array is allocated for the specific buffer. 5038 * Units are represented in cells. 5039 * Access: RW 5040 */ 5041 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5042 5043 /* reg_pbmc_buf_xoff_threshold 5044 * Once the amount of data in the buffer goes above this value, device 5045 * starts sending PFC frames for all priorities associated with the 5046 * buffer. Units are represented in cells. Reserved in case of lossy 5047 * buffer. 5048 * Access: RW 5049 * 5050 * Note: In Spectrum, reserved for buffer[9]. 5051 */ 5052 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5053 0x08, 0x04, false); 5054 5055 /* reg_pbmc_buf_xon_threshold 5056 * When the amount of data in the buffer goes below this value, device 5057 * stops sending PFC frames for the priorities associated with the 5058 * buffer. Units are represented in cells. Reserved in case of lossy 5059 * buffer. 5060 * Access: RW 5061 * 5062 * Note: In Spectrum, reserved for buffer[9]. 5063 */ 5064 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5065 0x08, 0x04, false); 5066 5067 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5068 u16 xoff_timer_value, u16 xoff_refresh) 5069 { 5070 MLXSW_REG_ZERO(pbmc, payload); 5071 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5072 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5073 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5074 } 5075 5076 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5077 int buf_index, 5078 u16 size) 5079 { 5080 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5081 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5082 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5083 } 5084 5085 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5086 int buf_index, u16 size, 5087 u16 threshold) 5088 { 5089 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5090 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5091 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5092 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5093 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5094 } 5095 5096 /* PSPA - Port Switch Partition Allocation 5097 * --------------------------------------- 5098 * Controls the association of a port with a switch partition and enables 5099 * configuring ports as stacking ports. 5100 */ 5101 #define MLXSW_REG_PSPA_ID 0x500D 5102 #define MLXSW_REG_PSPA_LEN 0x8 5103 5104 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5105 5106 /* reg_pspa_swid 5107 * Switch partition ID. 5108 * Access: RW 5109 */ 5110 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5111 5112 /* reg_pspa_local_port 5113 * Local port number. 5114 * Access: Index 5115 */ 5116 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5117 5118 /* reg_pspa_sub_port 5119 * Virtual port within the local port. Set to 0 when virtual ports are 5120 * disabled on the local port. 5121 * Access: Index 5122 */ 5123 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5124 5125 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5126 { 5127 MLXSW_REG_ZERO(pspa, payload); 5128 mlxsw_reg_pspa_swid_set(payload, swid); 5129 mlxsw_reg_pspa_local_port_set(payload, local_port); 5130 mlxsw_reg_pspa_sub_port_set(payload, 0); 5131 } 5132 5133 /* HTGT - Host Trap Group Table 5134 * ---------------------------- 5135 * Configures the properties for forwarding to CPU. 5136 */ 5137 #define MLXSW_REG_HTGT_ID 0x7002 5138 #define MLXSW_REG_HTGT_LEN 0x20 5139 5140 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5141 5142 /* reg_htgt_swid 5143 * Switch partition ID. 5144 * Access: Index 5145 */ 5146 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5147 5148 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5149 5150 /* reg_htgt_type 5151 * CPU path type. 5152 * Access: RW 5153 */ 5154 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5155 5156 enum mlxsw_reg_htgt_trap_group { 5157 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5158 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 5159 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 5160 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5161 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5162 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5163 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 5164 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5165 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5166 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5167 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5168 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 5169 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 5170 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5171 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 5172 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5173 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5174 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 5175 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5176 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 5177 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 5178 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5179 }; 5180 5181 /* reg_htgt_trap_group 5182 * Trap group number. User defined number specifying which trap groups 5183 * should be forwarded to the CPU. The mapping between trap IDs and trap 5184 * groups is configured using HPKT register. 5185 * Access: Index 5186 */ 5187 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5188 5189 enum { 5190 MLXSW_REG_HTGT_POLICER_DISABLE, 5191 MLXSW_REG_HTGT_POLICER_ENABLE, 5192 }; 5193 5194 /* reg_htgt_pide 5195 * Enable policer ID specified using 'pid' field. 5196 * Access: RW 5197 */ 5198 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5199 5200 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5201 5202 /* reg_htgt_pid 5203 * Policer ID for the trap group. 5204 * Access: RW 5205 */ 5206 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5207 5208 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5209 5210 /* reg_htgt_mirror_action 5211 * Mirror action to use. 5212 * 0 - Trap to CPU. 5213 * 1 - Trap to CPU and mirror to a mirroring agent. 5214 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5215 * Access: RW 5216 * 5217 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5218 */ 5219 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5220 5221 /* reg_htgt_mirroring_agent 5222 * Mirroring agent. 5223 * Access: RW 5224 */ 5225 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5226 5227 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5228 5229 /* reg_htgt_priority 5230 * Trap group priority. 5231 * In case a packet matches multiple classification rules, the packet will 5232 * only be trapped once, based on the trap ID associated with the group (via 5233 * register HPKT) with the highest priority. 5234 * Supported values are 0-7, with 7 represnting the highest priority. 5235 * Access: RW 5236 * 5237 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5238 * by the 'trap_group' field. 5239 */ 5240 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5241 5242 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5243 5244 /* reg_htgt_local_path_cpu_tclass 5245 * CPU ingress traffic class for the trap group. 5246 * Access: RW 5247 */ 5248 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5249 5250 enum mlxsw_reg_htgt_local_path_rdq { 5251 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5252 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5253 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5254 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5255 }; 5256 /* reg_htgt_local_path_rdq 5257 * Receive descriptor queue (RDQ) to use for the trap group. 5258 * Access: RW 5259 */ 5260 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5261 5262 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5263 u8 priority, u8 tc) 5264 { 5265 MLXSW_REG_ZERO(htgt, payload); 5266 5267 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5268 mlxsw_reg_htgt_pide_set(payload, 5269 MLXSW_REG_HTGT_POLICER_DISABLE); 5270 } else { 5271 mlxsw_reg_htgt_pide_set(payload, 5272 MLXSW_REG_HTGT_POLICER_ENABLE); 5273 mlxsw_reg_htgt_pid_set(payload, policer_id); 5274 } 5275 5276 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5277 mlxsw_reg_htgt_trap_group_set(payload, group); 5278 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5279 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5280 mlxsw_reg_htgt_priority_set(payload, priority); 5281 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5282 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5283 } 5284 5285 /* HPKT - Host Packet Trap 5286 * ----------------------- 5287 * Configures trap IDs inside trap groups. 5288 */ 5289 #define MLXSW_REG_HPKT_ID 0x7003 5290 #define MLXSW_REG_HPKT_LEN 0x10 5291 5292 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5293 5294 enum { 5295 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5296 MLXSW_REG_HPKT_ACK_REQUIRED, 5297 }; 5298 5299 /* reg_hpkt_ack 5300 * Require acknowledgements from the host for events. 5301 * If set, then the device will wait for the event it sent to be acknowledged 5302 * by the host. This option is only relevant for event trap IDs. 5303 * Access: RW 5304 * 5305 * Note: Currently not supported by firmware. 5306 */ 5307 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5308 5309 enum mlxsw_reg_hpkt_action { 5310 MLXSW_REG_HPKT_ACTION_FORWARD, 5311 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5312 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5313 MLXSW_REG_HPKT_ACTION_DISCARD, 5314 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5315 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5316 }; 5317 5318 /* reg_hpkt_action 5319 * Action to perform on packet when trapped. 5320 * 0 - No action. Forward to CPU based on switching rules. 5321 * 1 - Trap to CPU (CPU receives sole copy). 5322 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5323 * 3 - Discard. 5324 * 4 - Soft discard (allow other traps to act on the packet). 5325 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5326 * Access: RW 5327 * 5328 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5329 * addressed to the CPU. 5330 */ 5331 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5332 5333 /* reg_hpkt_trap_group 5334 * Trap group to associate the trap with. 5335 * Access: RW 5336 */ 5337 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5338 5339 /* reg_hpkt_trap_id 5340 * Trap ID. 5341 * Access: Index 5342 * 5343 * Note: A trap ID can only be associated with a single trap group. The device 5344 * will associate the trap ID with the last trap group configured. 5345 */ 5346 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5347 5348 enum { 5349 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5350 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5351 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5352 }; 5353 5354 /* reg_hpkt_ctrl 5355 * Configure dedicated buffer resources for control packets. 5356 * Ignored by SwitchX-2. 5357 * 0 - Keep factory defaults. 5358 * 1 - Do not use control buffer for this trap ID. 5359 * 2 - Use control buffer for this trap ID. 5360 * Access: RW 5361 */ 5362 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5363 5364 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5365 enum mlxsw_reg_htgt_trap_group trap_group, 5366 bool is_ctrl) 5367 { 5368 MLXSW_REG_ZERO(hpkt, payload); 5369 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5370 mlxsw_reg_hpkt_action_set(payload, action); 5371 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5372 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5373 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5374 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5375 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5376 } 5377 5378 /* RGCR - Router General Configuration Register 5379 * -------------------------------------------- 5380 * The register is used for setting up the router configuration. 5381 */ 5382 #define MLXSW_REG_RGCR_ID 0x8001 5383 #define MLXSW_REG_RGCR_LEN 0x28 5384 5385 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5386 5387 /* reg_rgcr_ipv4_en 5388 * IPv4 router enable. 5389 * Access: RW 5390 */ 5391 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5392 5393 /* reg_rgcr_ipv6_en 5394 * IPv6 router enable. 5395 * Access: RW 5396 */ 5397 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5398 5399 /* reg_rgcr_max_router_interfaces 5400 * Defines the maximum number of active router interfaces for all virtual 5401 * routers. 5402 * Access: RW 5403 */ 5404 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5405 5406 /* reg_rgcr_usp 5407 * Update switch priority and packet color. 5408 * 0 - Preserve the value of Switch Priority and packet color. 5409 * 1 - Recalculate the value of Switch Priority and packet color. 5410 * Access: RW 5411 * 5412 * Note: Not supported by SwitchX and SwitchX-2. 5413 */ 5414 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5415 5416 /* reg_rgcr_pcp_rw 5417 * Indicates how to handle the pcp_rewrite_en value: 5418 * 0 - Preserve the value of pcp_rewrite_en. 5419 * 2 - Disable PCP rewrite. 5420 * 3 - Enable PCP rewrite. 5421 * Access: RW 5422 * 5423 * Note: Not supported by SwitchX and SwitchX-2. 5424 */ 5425 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5426 5427 /* reg_rgcr_activity_dis 5428 * Activity disable: 5429 * 0 - Activity will be set when an entry is hit (default). 5430 * 1 - Activity will not be set when an entry is hit. 5431 * 5432 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5433 * (RALUE). 5434 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5435 * Entry (RAUHT). 5436 * Bits 2:7 are reserved. 5437 * Access: RW 5438 * 5439 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5440 */ 5441 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5442 5443 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5444 bool ipv6_en) 5445 { 5446 MLXSW_REG_ZERO(rgcr, payload); 5447 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5448 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5449 } 5450 5451 /* RITR - Router Interface Table Register 5452 * -------------------------------------- 5453 * The register is used to configure the router interface table. 5454 */ 5455 #define MLXSW_REG_RITR_ID 0x8002 5456 #define MLXSW_REG_RITR_LEN 0x40 5457 5458 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5459 5460 /* reg_ritr_enable 5461 * Enables routing on the router interface. 5462 * Access: RW 5463 */ 5464 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5465 5466 /* reg_ritr_ipv4 5467 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5468 * interface. 5469 * Access: RW 5470 */ 5471 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5472 5473 /* reg_ritr_ipv6 5474 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5475 * interface. 5476 * Access: RW 5477 */ 5478 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5479 5480 /* reg_ritr_ipv4_mc 5481 * IPv4 multicast routing enable. 5482 * Access: RW 5483 */ 5484 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5485 5486 /* reg_ritr_ipv6_mc 5487 * IPv6 multicast routing enable. 5488 * Access: RW 5489 */ 5490 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5491 5492 enum mlxsw_reg_ritr_if_type { 5493 /* VLAN interface. */ 5494 MLXSW_REG_RITR_VLAN_IF, 5495 /* FID interface. */ 5496 MLXSW_REG_RITR_FID_IF, 5497 /* Sub-port interface. */ 5498 MLXSW_REG_RITR_SP_IF, 5499 /* Loopback Interface. */ 5500 MLXSW_REG_RITR_LOOPBACK_IF, 5501 }; 5502 5503 /* reg_ritr_type 5504 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5505 * Access: RW 5506 */ 5507 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5508 5509 enum { 5510 MLXSW_REG_RITR_RIF_CREATE, 5511 MLXSW_REG_RITR_RIF_DEL, 5512 }; 5513 5514 /* reg_ritr_op 5515 * Opcode: 5516 * 0 - Create or edit RIF. 5517 * 1 - Delete RIF. 5518 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5519 * is not supported. An interface must be deleted and re-created in order 5520 * to update properties. 5521 * Access: WO 5522 */ 5523 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5524 5525 /* reg_ritr_rif 5526 * Router interface index. A pointer to the Router Interface Table. 5527 * Access: Index 5528 */ 5529 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5530 5531 /* reg_ritr_ipv4_fe 5532 * IPv4 Forwarding Enable. 5533 * Enables routing of IPv4 traffic on the router interface. When disabled, 5534 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5535 * Not supported in SwitchX-2. 5536 * Access: RW 5537 */ 5538 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5539 5540 /* reg_ritr_ipv6_fe 5541 * IPv6 Forwarding Enable. 5542 * Enables routing of IPv6 traffic on the router interface. When disabled, 5543 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5544 * Not supported in SwitchX-2. 5545 * Access: RW 5546 */ 5547 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5548 5549 /* reg_ritr_ipv4_mc_fe 5550 * IPv4 Multicast Forwarding Enable. 5551 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5552 * will be enabled. 5553 * Access: RW 5554 */ 5555 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5556 5557 /* reg_ritr_ipv6_mc_fe 5558 * IPv6 Multicast Forwarding Enable. 5559 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5560 * will be enabled. 5561 * Access: RW 5562 */ 5563 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5564 5565 /* reg_ritr_lb_en 5566 * Loop-back filter enable for unicast packets. 5567 * If the flag is set then loop-back filter for unicast packets is 5568 * implemented on the RIF. Multicast packets are always subject to 5569 * loop-back filtering. 5570 * Access: RW 5571 */ 5572 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5573 5574 /* reg_ritr_virtual_router 5575 * Virtual router ID associated with the router interface. 5576 * Access: RW 5577 */ 5578 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5579 5580 /* reg_ritr_mtu 5581 * Router interface MTU. 5582 * Access: RW 5583 */ 5584 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5585 5586 /* reg_ritr_if_swid 5587 * Switch partition ID. 5588 * Access: RW 5589 */ 5590 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5591 5592 /* reg_ritr_if_mac 5593 * Router interface MAC address. 5594 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5595 * Access: RW 5596 */ 5597 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5598 5599 /* reg_ritr_if_vrrp_id_ipv6 5600 * VRRP ID for IPv6 5601 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5602 * Access: RW 5603 */ 5604 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5605 5606 /* reg_ritr_if_vrrp_id_ipv4 5607 * VRRP ID for IPv4 5608 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5609 * Access: RW 5610 */ 5611 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5612 5613 /* VLAN Interface */ 5614 5615 /* reg_ritr_vlan_if_vid 5616 * VLAN ID. 5617 * Access: RW 5618 */ 5619 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5620 5621 /* FID Interface */ 5622 5623 /* reg_ritr_fid_if_fid 5624 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5625 * the vFID range are supported. 5626 * Access: RW 5627 */ 5628 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5629 5630 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5631 enum mlxsw_reg_ritr_if_type rif_type, 5632 u16 fid) 5633 { 5634 if (rif_type == MLXSW_REG_RITR_FID_IF) 5635 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5636 else 5637 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5638 } 5639 5640 /* Sub-port Interface */ 5641 5642 /* reg_ritr_sp_if_lag 5643 * LAG indication. When this bit is set the system_port field holds the 5644 * LAG identifier. 5645 * Access: RW 5646 */ 5647 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5648 5649 /* reg_ritr_sp_system_port 5650 * Port unique indentifier. When lag bit is set, this field holds the 5651 * lag_id in bits 0:9. 5652 * Access: RW 5653 */ 5654 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5655 5656 /* reg_ritr_sp_if_vid 5657 * VLAN ID. 5658 * Access: RW 5659 */ 5660 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5661 5662 /* Loopback Interface */ 5663 5664 enum mlxsw_reg_ritr_loopback_protocol { 5665 /* IPinIP IPv4 underlay Unicast */ 5666 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5667 /* IPinIP IPv6 underlay Unicast */ 5668 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5669 }; 5670 5671 /* reg_ritr_loopback_protocol 5672 * Access: RW 5673 */ 5674 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5675 5676 enum mlxsw_reg_ritr_loopback_ipip_type { 5677 /* Tunnel is IPinIP. */ 5678 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5679 /* Tunnel is GRE, no key. */ 5680 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5681 /* Tunnel is GRE, with a key. */ 5682 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5683 }; 5684 5685 /* reg_ritr_loopback_ipip_type 5686 * Encapsulation type. 5687 * Access: RW 5688 */ 5689 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 5690 5691 enum mlxsw_reg_ritr_loopback_ipip_options { 5692 /* The key is defined by gre_key. */ 5693 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 5694 }; 5695 5696 /* reg_ritr_loopback_ipip_options 5697 * Access: RW 5698 */ 5699 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 5700 5701 /* reg_ritr_loopback_ipip_uvr 5702 * Underlay Virtual Router ID. 5703 * Range is 0..cap_max_virtual_routers-1. 5704 * Reserved for Spectrum-2. 5705 * Access: RW 5706 */ 5707 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 5708 5709 /* reg_ritr_loopback_ipip_usip* 5710 * Encapsulation Underlay source IP. 5711 * Access: RW 5712 */ 5713 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 5714 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 5715 5716 /* reg_ritr_loopback_ipip_gre_key 5717 * GRE Key. 5718 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 5719 * Access: RW 5720 */ 5721 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 5722 5723 /* Shared between ingress/egress */ 5724 enum mlxsw_reg_ritr_counter_set_type { 5725 /* No Count. */ 5726 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 5727 /* Basic. Used for router interfaces, counting the following: 5728 * - Error and Discard counters. 5729 * - Unicast, Multicast and Broadcast counters. Sharing the 5730 * same set of counters for the different type of traffic 5731 * (IPv4, IPv6 and mpls). 5732 */ 5733 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 5734 }; 5735 5736 /* reg_ritr_ingress_counter_index 5737 * Counter Index for flow counter. 5738 * Access: RW 5739 */ 5740 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 5741 5742 /* reg_ritr_ingress_counter_set_type 5743 * Igress Counter Set Type for router interface counter. 5744 * Access: RW 5745 */ 5746 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 5747 5748 /* reg_ritr_egress_counter_index 5749 * Counter Index for flow counter. 5750 * Access: RW 5751 */ 5752 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 5753 5754 /* reg_ritr_egress_counter_set_type 5755 * Egress Counter Set Type for router interface counter. 5756 * Access: RW 5757 */ 5758 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 5759 5760 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 5761 bool enable, bool egress) 5762 { 5763 enum mlxsw_reg_ritr_counter_set_type set_type; 5764 5765 if (enable) 5766 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 5767 else 5768 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 5769 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 5770 5771 if (egress) 5772 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 5773 else 5774 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 5775 } 5776 5777 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 5778 { 5779 MLXSW_REG_ZERO(ritr, payload); 5780 mlxsw_reg_ritr_rif_set(payload, rif); 5781 } 5782 5783 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 5784 u16 system_port, u16 vid) 5785 { 5786 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 5787 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 5788 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 5789 } 5790 5791 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 5792 enum mlxsw_reg_ritr_if_type type, 5793 u16 rif, u16 vr_id, u16 mtu) 5794 { 5795 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 5796 5797 MLXSW_REG_ZERO(ritr, payload); 5798 mlxsw_reg_ritr_enable_set(payload, enable); 5799 mlxsw_reg_ritr_ipv4_set(payload, 1); 5800 mlxsw_reg_ritr_ipv6_set(payload, 1); 5801 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 5802 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 5803 mlxsw_reg_ritr_type_set(payload, type); 5804 mlxsw_reg_ritr_op_set(payload, op); 5805 mlxsw_reg_ritr_rif_set(payload, rif); 5806 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 5807 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 5808 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 5809 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 5810 mlxsw_reg_ritr_lb_en_set(payload, 1); 5811 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 5812 mlxsw_reg_ritr_mtu_set(payload, mtu); 5813 } 5814 5815 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 5816 { 5817 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 5818 } 5819 5820 static inline void 5821 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 5822 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5823 enum mlxsw_reg_ritr_loopback_ipip_options options, 5824 u16 uvr_id, u32 gre_key) 5825 { 5826 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 5827 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 5828 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 5829 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 5830 } 5831 5832 static inline void 5833 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 5834 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5835 enum mlxsw_reg_ritr_loopback_ipip_options options, 5836 u16 uvr_id, u32 usip, u32 gre_key) 5837 { 5838 mlxsw_reg_ritr_loopback_protocol_set(payload, 5839 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 5840 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 5841 uvr_id, gre_key); 5842 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 5843 } 5844 5845 /* RTAR - Router TCAM Allocation Register 5846 * -------------------------------------- 5847 * This register is used for allocation of regions in the TCAM table. 5848 */ 5849 #define MLXSW_REG_RTAR_ID 0x8004 5850 #define MLXSW_REG_RTAR_LEN 0x20 5851 5852 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 5853 5854 enum mlxsw_reg_rtar_op { 5855 MLXSW_REG_RTAR_OP_ALLOCATE, 5856 MLXSW_REG_RTAR_OP_RESIZE, 5857 MLXSW_REG_RTAR_OP_DEALLOCATE, 5858 }; 5859 5860 /* reg_rtar_op 5861 * Access: WO 5862 */ 5863 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 5864 5865 enum mlxsw_reg_rtar_key_type { 5866 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 5867 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 5868 }; 5869 5870 /* reg_rtar_key_type 5871 * TCAM key type for the region. 5872 * Access: WO 5873 */ 5874 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 5875 5876 /* reg_rtar_region_size 5877 * TCAM region size. When allocating/resizing this is the requested 5878 * size, the response is the actual size. 5879 * Note: Actual size may be larger than requested. 5880 * Reserved for op = Deallocate 5881 * Access: WO 5882 */ 5883 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 5884 5885 static inline void mlxsw_reg_rtar_pack(char *payload, 5886 enum mlxsw_reg_rtar_op op, 5887 enum mlxsw_reg_rtar_key_type key_type, 5888 u16 region_size) 5889 { 5890 MLXSW_REG_ZERO(rtar, payload); 5891 mlxsw_reg_rtar_op_set(payload, op); 5892 mlxsw_reg_rtar_key_type_set(payload, key_type); 5893 mlxsw_reg_rtar_region_size_set(payload, region_size); 5894 } 5895 5896 /* RATR - Router Adjacency Table Register 5897 * -------------------------------------- 5898 * The RATR register is used to configure the Router Adjacency (next-hop) 5899 * Table. 5900 */ 5901 #define MLXSW_REG_RATR_ID 0x8008 5902 #define MLXSW_REG_RATR_LEN 0x2C 5903 5904 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5905 5906 enum mlxsw_reg_ratr_op { 5907 /* Read */ 5908 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5909 /* Read and clear activity */ 5910 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 5911 /* Write Adjacency entry */ 5912 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 5913 /* Write Adjacency entry only if the activity is cleared. 5914 * The write may not succeed if the activity is set. There is not 5915 * direct feedback if the write has succeeded or not, however 5916 * the get will reveal the actual entry (SW can compare the get 5917 * response to the set command). 5918 */ 5919 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 5920 }; 5921 5922 /* reg_ratr_op 5923 * Note that Write operation may also be used for updating 5924 * counter_set_type and counter_index. In this case all other 5925 * fields must not be updated. 5926 * Access: OP 5927 */ 5928 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 5929 5930 /* reg_ratr_v 5931 * Valid bit. Indicates if the adjacency entry is valid. 5932 * Note: the device may need some time before reusing an invalidated 5933 * entry. During this time the entry can not be reused. It is 5934 * recommended to use another entry before reusing an invalidated 5935 * entry (e.g. software can put it at the end of the list for 5936 * reusing). Trying to access an invalidated entry not yet cleared 5937 * by the device results with failure indicating "Try Again" status. 5938 * When valid is '0' then egress_router_interface,trap_action, 5939 * adjacency_parameters and counters are reserved 5940 * Access: RW 5941 */ 5942 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 5943 5944 /* reg_ratr_a 5945 * Activity. Set for new entries. Set if a packet lookup has hit on 5946 * the specific entry. To clear the a bit, use "clear activity". 5947 * Access: RO 5948 */ 5949 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 5950 5951 enum mlxsw_reg_ratr_type { 5952 /* Ethernet */ 5953 MLXSW_REG_RATR_TYPE_ETHERNET, 5954 /* IPoIB Unicast without GRH. 5955 * Reserved for Spectrum. 5956 */ 5957 MLXSW_REG_RATR_TYPE_IPOIB_UC, 5958 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 5959 * adjacency). 5960 * Reserved for Spectrum. 5961 */ 5962 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 5963 /* IPoIB Multicast. 5964 * Reserved for Spectrum. 5965 */ 5966 MLXSW_REG_RATR_TYPE_IPOIB_MC, 5967 /* MPLS. 5968 * Reserved for SwitchX/-2. 5969 */ 5970 MLXSW_REG_RATR_TYPE_MPLS, 5971 /* IPinIP Encap. 5972 * Reserved for SwitchX/-2. 5973 */ 5974 MLXSW_REG_RATR_TYPE_IPIP, 5975 }; 5976 5977 /* reg_ratr_type 5978 * Adjacency entry type. 5979 * Access: RW 5980 */ 5981 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 5982 5983 /* reg_ratr_adjacency_index_low 5984 * Bits 15:0 of index into the adjacency table. 5985 * For SwitchX and SwitchX-2, the adjacency table is linear and 5986 * used for adjacency entries only. 5987 * For Spectrum, the index is to the KVD linear. 5988 * Access: Index 5989 */ 5990 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 5991 5992 /* reg_ratr_egress_router_interface 5993 * Range is 0 .. cap_max_router_interfaces - 1 5994 * Access: RW 5995 */ 5996 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 5997 5998 enum mlxsw_reg_ratr_trap_action { 5999 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6000 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6001 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6002 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6003 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6004 }; 6005 6006 /* reg_ratr_trap_action 6007 * see mlxsw_reg_ratr_trap_action 6008 * Access: RW 6009 */ 6010 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6011 6012 /* reg_ratr_adjacency_index_high 6013 * Bits 23:16 of the adjacency_index. 6014 * Access: Index 6015 */ 6016 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6017 6018 enum mlxsw_reg_ratr_trap_id { 6019 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6020 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6021 }; 6022 6023 /* reg_ratr_trap_id 6024 * Trap ID to be reported to CPU. 6025 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6026 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6027 * Access: RW 6028 */ 6029 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6030 6031 /* reg_ratr_eth_destination_mac 6032 * MAC address of the destination next-hop. 6033 * Access: RW 6034 */ 6035 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6036 6037 enum mlxsw_reg_ratr_ipip_type { 6038 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6039 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6040 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6041 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6042 }; 6043 6044 /* reg_ratr_ipip_type 6045 * Underlay destination ip type. 6046 * Note: the type field must match the protocol of the router interface. 6047 * Access: RW 6048 */ 6049 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6050 6051 /* reg_ratr_ipip_ipv4_udip 6052 * Underlay ipv4 dip. 6053 * Reserved when ipip_type is IPv6. 6054 * Access: RW 6055 */ 6056 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6057 6058 /* reg_ratr_ipip_ipv6_ptr 6059 * Pointer to IPv6 underlay destination ip address. 6060 * For Spectrum: Pointer to KVD linear space. 6061 * Access: RW 6062 */ 6063 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6064 6065 enum mlxsw_reg_flow_counter_set_type { 6066 /* No count */ 6067 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6068 /* Count packets and bytes */ 6069 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6070 /* Count only packets */ 6071 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6072 }; 6073 6074 /* reg_ratr_counter_set_type 6075 * Counter set type for flow counters 6076 * Access: RW 6077 */ 6078 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6079 6080 /* reg_ratr_counter_index 6081 * Counter index for flow counters 6082 * Access: RW 6083 */ 6084 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6085 6086 static inline void 6087 mlxsw_reg_ratr_pack(char *payload, 6088 enum mlxsw_reg_ratr_op op, bool valid, 6089 enum mlxsw_reg_ratr_type type, 6090 u32 adjacency_index, u16 egress_rif) 6091 { 6092 MLXSW_REG_ZERO(ratr, payload); 6093 mlxsw_reg_ratr_op_set(payload, op); 6094 mlxsw_reg_ratr_v_set(payload, valid); 6095 mlxsw_reg_ratr_type_set(payload, type); 6096 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6097 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6098 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6099 } 6100 6101 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6102 const char *dest_mac) 6103 { 6104 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6105 } 6106 6107 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6108 { 6109 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6110 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6111 } 6112 6113 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6114 bool counter_enable) 6115 { 6116 enum mlxsw_reg_flow_counter_set_type set_type; 6117 6118 if (counter_enable) 6119 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6120 else 6121 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6122 6123 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6124 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6125 } 6126 6127 /* RDPM - Router DSCP to Priority Mapping 6128 * -------------------------------------- 6129 * Controls the mapping from DSCP field to switch priority on routed packets 6130 */ 6131 #define MLXSW_REG_RDPM_ID 0x8009 6132 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6133 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6134 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6135 #define MLXSW_REG_RDPM_LEN 0x40 6136 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6137 MLXSW_REG_RDPM_LEN - \ 6138 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6139 6140 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6141 6142 /* reg_dscp_entry_e 6143 * Enable update of the specific entry 6144 * Access: Index 6145 */ 6146 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6147 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6148 6149 /* reg_dscp_entry_prio 6150 * Switch Priority 6151 * Access: RW 6152 */ 6153 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6154 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6155 6156 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6157 u8 prio) 6158 { 6159 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6160 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6161 } 6162 6163 /* RICNT - Router Interface Counter Register 6164 * ----------------------------------------- 6165 * The RICNT register retrieves per port performance counters 6166 */ 6167 #define MLXSW_REG_RICNT_ID 0x800B 6168 #define MLXSW_REG_RICNT_LEN 0x100 6169 6170 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6171 6172 /* reg_ricnt_counter_index 6173 * Counter index 6174 * Access: RW 6175 */ 6176 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6177 6178 enum mlxsw_reg_ricnt_counter_set_type { 6179 /* No Count. */ 6180 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6181 /* Basic. Used for router interfaces, counting the following: 6182 * - Error and Discard counters. 6183 * - Unicast, Multicast and Broadcast counters. Sharing the 6184 * same set of counters for the different type of traffic 6185 * (IPv4, IPv6 and mpls). 6186 */ 6187 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6188 }; 6189 6190 /* reg_ricnt_counter_set_type 6191 * Counter Set Type for router interface counter 6192 * Access: RW 6193 */ 6194 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6195 6196 enum mlxsw_reg_ricnt_opcode { 6197 /* Nop. Supported only for read access*/ 6198 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6199 /* Clear. Setting the clr bit will reset the counter value for 6200 * all counters of the specified Router Interface. 6201 */ 6202 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6203 }; 6204 6205 /* reg_ricnt_opcode 6206 * Opcode 6207 * Access: RW 6208 */ 6209 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6210 6211 /* reg_ricnt_good_unicast_packets 6212 * good unicast packets. 6213 * Access: RW 6214 */ 6215 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6216 6217 /* reg_ricnt_good_multicast_packets 6218 * good multicast packets. 6219 * Access: RW 6220 */ 6221 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6222 6223 /* reg_ricnt_good_broadcast_packets 6224 * good broadcast packets 6225 * Access: RW 6226 */ 6227 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6228 6229 /* reg_ricnt_good_unicast_bytes 6230 * A count of L3 data and padding octets not including L2 headers 6231 * for good unicast frames. 6232 * Access: RW 6233 */ 6234 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6235 6236 /* reg_ricnt_good_multicast_bytes 6237 * A count of L3 data and padding octets not including L2 headers 6238 * for good multicast frames. 6239 * Access: RW 6240 */ 6241 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6242 6243 /* reg_ritr_good_broadcast_bytes 6244 * A count of L3 data and padding octets not including L2 headers 6245 * for good broadcast frames. 6246 * Access: RW 6247 */ 6248 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6249 6250 /* reg_ricnt_error_packets 6251 * A count of errored frames that do not pass the router checks. 6252 * Access: RW 6253 */ 6254 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6255 6256 /* reg_ricnt_discrad_packets 6257 * A count of non-errored frames that do not pass the router checks. 6258 * Access: RW 6259 */ 6260 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6261 6262 /* reg_ricnt_error_bytes 6263 * A count of L3 data and padding octets not including L2 headers 6264 * for errored frames. 6265 * Access: RW 6266 */ 6267 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6268 6269 /* reg_ricnt_discard_bytes 6270 * A count of L3 data and padding octets not including L2 headers 6271 * for non-errored frames that do not pass the router checks. 6272 * Access: RW 6273 */ 6274 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6275 6276 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6277 enum mlxsw_reg_ricnt_opcode op) 6278 { 6279 MLXSW_REG_ZERO(ricnt, payload); 6280 mlxsw_reg_ricnt_op_set(payload, op); 6281 mlxsw_reg_ricnt_counter_index_set(payload, index); 6282 mlxsw_reg_ricnt_counter_set_type_set(payload, 6283 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6284 } 6285 6286 /* RRCR - Router Rules Copy Register Layout 6287 * ---------------------------------------- 6288 * This register is used for moving and copying route entry rules. 6289 */ 6290 #define MLXSW_REG_RRCR_ID 0x800F 6291 #define MLXSW_REG_RRCR_LEN 0x24 6292 6293 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6294 6295 enum mlxsw_reg_rrcr_op { 6296 /* Move rules */ 6297 MLXSW_REG_RRCR_OP_MOVE, 6298 /* Copy rules */ 6299 MLXSW_REG_RRCR_OP_COPY, 6300 }; 6301 6302 /* reg_rrcr_op 6303 * Access: WO 6304 */ 6305 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6306 6307 /* reg_rrcr_offset 6308 * Offset within the region from which to copy/move. 6309 * Access: Index 6310 */ 6311 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6312 6313 /* reg_rrcr_size 6314 * The number of rules to copy/move. 6315 * Access: WO 6316 */ 6317 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6318 6319 /* reg_rrcr_table_id 6320 * Identifier of the table on which to perform the operation. Encoding is the 6321 * same as in RTAR.key_type 6322 * Access: Index 6323 */ 6324 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6325 6326 /* reg_rrcr_dest_offset 6327 * Offset within the region to which to copy/move 6328 * Access: Index 6329 */ 6330 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6331 6332 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6333 u16 offset, u16 size, 6334 enum mlxsw_reg_rtar_key_type table_id, 6335 u16 dest_offset) 6336 { 6337 MLXSW_REG_ZERO(rrcr, payload); 6338 mlxsw_reg_rrcr_op_set(payload, op); 6339 mlxsw_reg_rrcr_offset_set(payload, offset); 6340 mlxsw_reg_rrcr_size_set(payload, size); 6341 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6342 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6343 } 6344 6345 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6346 * ------------------------------------------------------- 6347 * RALTA is used to allocate the LPM trees of the SHSPM method. 6348 */ 6349 #define MLXSW_REG_RALTA_ID 0x8010 6350 #define MLXSW_REG_RALTA_LEN 0x04 6351 6352 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6353 6354 /* reg_ralta_op 6355 * opcode (valid for Write, must be 0 on Read) 6356 * 0 - allocate a tree 6357 * 1 - deallocate a tree 6358 * Access: OP 6359 */ 6360 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6361 6362 enum mlxsw_reg_ralxx_protocol { 6363 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6364 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6365 }; 6366 6367 /* reg_ralta_protocol 6368 * Protocol. 6369 * Deallocation opcode: Reserved. 6370 * Access: RW 6371 */ 6372 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6373 6374 /* reg_ralta_tree_id 6375 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6376 * the tree identifier (managed by software). 6377 * Note that tree_id 0 is allocated for a default-route tree. 6378 * Access: Index 6379 */ 6380 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6381 6382 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6383 enum mlxsw_reg_ralxx_protocol protocol, 6384 u8 tree_id) 6385 { 6386 MLXSW_REG_ZERO(ralta, payload); 6387 mlxsw_reg_ralta_op_set(payload, !alloc); 6388 mlxsw_reg_ralta_protocol_set(payload, protocol); 6389 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6390 } 6391 6392 /* RALST - Router Algorithmic LPM Structure Tree Register 6393 * ------------------------------------------------------ 6394 * RALST is used to set and query the structure of an LPM tree. 6395 * The structure of the tree must be sorted as a sorted binary tree, while 6396 * each node is a bin that is tagged as the length of the prefixes the lookup 6397 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6398 * of X bits to match with the destination address. The bin 0 indicates 6399 * the default action, when there is no match of any prefix. 6400 */ 6401 #define MLXSW_REG_RALST_ID 0x8011 6402 #define MLXSW_REG_RALST_LEN 0x104 6403 6404 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6405 6406 /* reg_ralst_root_bin 6407 * The bin number of the root bin. 6408 * 0<root_bin=<(length of IP address) 6409 * For a default-route tree configure 0xff 6410 * Access: RW 6411 */ 6412 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6413 6414 /* reg_ralst_tree_id 6415 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6416 * Access: Index 6417 */ 6418 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6419 6420 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6421 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6422 #define MLXSW_REG_RALST_BIN_COUNT 128 6423 6424 /* reg_ralst_left_child_bin 6425 * Holding the children of the bin according to the stored tree's structure. 6426 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6427 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6428 * Access: RW 6429 */ 6430 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6431 6432 /* reg_ralst_right_child_bin 6433 * Holding the children of the bin according to the stored tree's structure. 6434 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6435 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6436 * Access: RW 6437 */ 6438 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6439 false); 6440 6441 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6442 { 6443 MLXSW_REG_ZERO(ralst, payload); 6444 6445 /* Initialize all bins to have no left or right child */ 6446 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6447 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6448 6449 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6450 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6451 } 6452 6453 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6454 u8 left_child_bin, 6455 u8 right_child_bin) 6456 { 6457 int bin_index = bin_number - 1; 6458 6459 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6460 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6461 right_child_bin); 6462 } 6463 6464 /* RALTB - Router Algorithmic LPM Tree Binding Register 6465 * ---------------------------------------------------- 6466 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6467 */ 6468 #define MLXSW_REG_RALTB_ID 0x8012 6469 #define MLXSW_REG_RALTB_LEN 0x04 6470 6471 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6472 6473 /* reg_raltb_virtual_router 6474 * Virtual Router ID 6475 * Range is 0..cap_max_virtual_routers-1 6476 * Access: Index 6477 */ 6478 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6479 6480 /* reg_raltb_protocol 6481 * Protocol. 6482 * Access: Index 6483 */ 6484 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6485 6486 /* reg_raltb_tree_id 6487 * Tree to be used for the {virtual_router, protocol} 6488 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6489 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6490 * Access: RW 6491 */ 6492 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6493 6494 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6495 enum mlxsw_reg_ralxx_protocol protocol, 6496 u8 tree_id) 6497 { 6498 MLXSW_REG_ZERO(raltb, payload); 6499 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6500 mlxsw_reg_raltb_protocol_set(payload, protocol); 6501 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6502 } 6503 6504 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6505 * ----------------------------------------------------- 6506 * RALUE is used to configure and query LPM entries that serve 6507 * the Unicast protocols. 6508 */ 6509 #define MLXSW_REG_RALUE_ID 0x8013 6510 #define MLXSW_REG_RALUE_LEN 0x38 6511 6512 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6513 6514 /* reg_ralue_protocol 6515 * Protocol. 6516 * Access: Index 6517 */ 6518 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6519 6520 enum mlxsw_reg_ralue_op { 6521 /* Read operation. If entry doesn't exist, the operation fails. */ 6522 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6523 /* Clear on read operation. Used to read entry and 6524 * clear Activity bit. 6525 */ 6526 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6527 /* Write operation. Used to write a new entry to the table. All RW 6528 * fields are written for new entry. Activity bit is set 6529 * for new entries. 6530 */ 6531 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6532 /* Update operation. Used to update an existing route entry and 6533 * only update the RW fields that are detailed in the field 6534 * op_u_mask. If entry doesn't exist, the operation fails. 6535 */ 6536 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6537 /* Clear activity. The Activity bit (the field a) is cleared 6538 * for the entry. 6539 */ 6540 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6541 /* Delete operation. Used to delete an existing entry. If entry 6542 * doesn't exist, the operation fails. 6543 */ 6544 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6545 }; 6546 6547 /* reg_ralue_op 6548 * Operation. 6549 * Access: OP 6550 */ 6551 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6552 6553 /* reg_ralue_a 6554 * Activity. Set for new entries. Set if a packet lookup has hit on the 6555 * specific entry, only if the entry is a route. To clear the a bit, use 6556 * "clear activity" op. 6557 * Enabled by activity_dis in RGCR 6558 * Access: RO 6559 */ 6560 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6561 6562 /* reg_ralue_virtual_router 6563 * Virtual Router ID 6564 * Range is 0..cap_max_virtual_routers-1 6565 * Access: Index 6566 */ 6567 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6568 6569 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6570 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6571 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6572 6573 /* reg_ralue_op_u_mask 6574 * opcode update mask. 6575 * On read operation, this field is reserved. 6576 * This field is valid for update opcode, otherwise - reserved. 6577 * This field is a bitmask of the fields that should be updated. 6578 * Access: WO 6579 */ 6580 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6581 6582 /* reg_ralue_prefix_len 6583 * Number of bits in the prefix of the LPM route. 6584 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6585 * two entries in the physical HW table. 6586 * Access: Index 6587 */ 6588 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6589 6590 /* reg_ralue_dip* 6591 * The prefix of the route or of the marker that the object of the LPM 6592 * is compared with. The most significant bits of the dip are the prefix. 6593 * The least significant bits must be '0' if the prefix_len is smaller 6594 * than 128 for IPv6 or smaller than 32 for IPv4. 6595 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6596 * Access: Index 6597 */ 6598 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6599 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6600 6601 enum mlxsw_reg_ralue_entry_type { 6602 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6603 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6604 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6605 }; 6606 6607 /* reg_ralue_entry_type 6608 * Entry type. 6609 * Note - for Marker entries, the action_type and action fields are reserved. 6610 * Access: RW 6611 */ 6612 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6613 6614 /* reg_ralue_bmp_len 6615 * The best match prefix length in the case that there is no match for 6616 * longer prefixes. 6617 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6618 * Note for any update operation with entry_type modification this 6619 * field must be set. 6620 * Access: RW 6621 */ 6622 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6623 6624 enum mlxsw_reg_ralue_action_type { 6625 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6626 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6627 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6628 }; 6629 6630 /* reg_ralue_action_type 6631 * Action Type 6632 * Indicates how the IP address is connected. 6633 * It can be connected to a local subnet through local_erif or can be 6634 * on a remote subnet connected through a next-hop router, 6635 * or transmitted to the CPU. 6636 * Reserved when entry_type = MARKER_ENTRY 6637 * Access: RW 6638 */ 6639 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6640 6641 enum mlxsw_reg_ralue_trap_action { 6642 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6643 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6644 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6645 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6646 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6647 }; 6648 6649 /* reg_ralue_trap_action 6650 * Trap action. 6651 * For IP2ME action, only NOP and MIRROR are possible. 6652 * Access: RW 6653 */ 6654 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6655 6656 /* reg_ralue_trap_id 6657 * Trap ID to be reported to CPU. 6658 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6659 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6660 * Access: RW 6661 */ 6662 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6663 6664 /* reg_ralue_adjacency_index 6665 * Points to the first entry of the group-based ECMP. 6666 * Only relevant in case of REMOTE action. 6667 * Access: RW 6668 */ 6669 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6670 6671 /* reg_ralue_ecmp_size 6672 * Amount of sequential entries starting 6673 * from the adjacency_index (the number of ECMPs). 6674 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6675 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6676 * Only relevant in case of REMOTE action. 6677 * Access: RW 6678 */ 6679 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6680 6681 /* reg_ralue_local_erif 6682 * Egress Router Interface. 6683 * Only relevant in case of LOCAL action. 6684 * Access: RW 6685 */ 6686 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 6687 6688 /* reg_ralue_ip2me_v 6689 * Valid bit for the tunnel_ptr field. 6690 * If valid = 0 then trap to CPU as IP2ME trap ID. 6691 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 6692 * decapsulation then tunnel decapsulation is done. 6693 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 6694 * decapsulation then trap as IP2ME trap ID. 6695 * Only relevant in case of IP2ME action. 6696 * Access: RW 6697 */ 6698 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 6699 6700 /* reg_ralue_ip2me_tunnel_ptr 6701 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 6702 * For Spectrum, pointer to KVD Linear. 6703 * Only relevant in case of IP2ME action. 6704 * Access: RW 6705 */ 6706 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 6707 6708 static inline void mlxsw_reg_ralue_pack(char *payload, 6709 enum mlxsw_reg_ralxx_protocol protocol, 6710 enum mlxsw_reg_ralue_op op, 6711 u16 virtual_router, u8 prefix_len) 6712 { 6713 MLXSW_REG_ZERO(ralue, payload); 6714 mlxsw_reg_ralue_protocol_set(payload, protocol); 6715 mlxsw_reg_ralue_op_set(payload, op); 6716 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 6717 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 6718 mlxsw_reg_ralue_entry_type_set(payload, 6719 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 6720 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 6721 } 6722 6723 static inline void mlxsw_reg_ralue_pack4(char *payload, 6724 enum mlxsw_reg_ralxx_protocol protocol, 6725 enum mlxsw_reg_ralue_op op, 6726 u16 virtual_router, u8 prefix_len, 6727 u32 dip) 6728 { 6729 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6730 mlxsw_reg_ralue_dip4_set(payload, dip); 6731 } 6732 6733 static inline void mlxsw_reg_ralue_pack6(char *payload, 6734 enum mlxsw_reg_ralxx_protocol protocol, 6735 enum mlxsw_reg_ralue_op op, 6736 u16 virtual_router, u8 prefix_len, 6737 const void *dip) 6738 { 6739 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6740 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 6741 } 6742 6743 static inline void 6744 mlxsw_reg_ralue_act_remote_pack(char *payload, 6745 enum mlxsw_reg_ralue_trap_action trap_action, 6746 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 6747 { 6748 mlxsw_reg_ralue_action_type_set(payload, 6749 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 6750 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6751 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6752 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 6753 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 6754 } 6755 6756 static inline void 6757 mlxsw_reg_ralue_act_local_pack(char *payload, 6758 enum mlxsw_reg_ralue_trap_action trap_action, 6759 u16 trap_id, u16 local_erif) 6760 { 6761 mlxsw_reg_ralue_action_type_set(payload, 6762 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 6763 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6764 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6765 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 6766 } 6767 6768 static inline void 6769 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 6770 { 6771 mlxsw_reg_ralue_action_type_set(payload, 6772 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6773 } 6774 6775 static inline void 6776 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 6777 { 6778 mlxsw_reg_ralue_action_type_set(payload, 6779 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6780 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 6781 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 6782 } 6783 6784 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 6785 * ---------------------------------------------------------- 6786 * The RAUHT register is used to configure and query the Unicast Host table in 6787 * devices that implement the Algorithmic LPM. 6788 */ 6789 #define MLXSW_REG_RAUHT_ID 0x8014 6790 #define MLXSW_REG_RAUHT_LEN 0x74 6791 6792 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 6793 6794 enum mlxsw_reg_rauht_type { 6795 MLXSW_REG_RAUHT_TYPE_IPV4, 6796 MLXSW_REG_RAUHT_TYPE_IPV6, 6797 }; 6798 6799 /* reg_rauht_type 6800 * Access: Index 6801 */ 6802 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 6803 6804 enum mlxsw_reg_rauht_op { 6805 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 6806 /* Read operation */ 6807 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 6808 /* Clear on read operation. Used to read entry and clear 6809 * activity bit. 6810 */ 6811 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 6812 /* Add. Used to write a new entry to the table. All R/W fields are 6813 * relevant for new entry. Activity bit is set for new entries. 6814 */ 6815 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 6816 /* Update action. Used to update an existing route entry and 6817 * only update the following fields: 6818 * trap_action, trap_id, mac, counter_set_type, counter_index 6819 */ 6820 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 6821 /* Clear activity. A bit is cleared for the entry. */ 6822 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 6823 /* Delete entry */ 6824 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 6825 /* Delete all host entries on a RIF. In this command, dip 6826 * field is reserved. 6827 */ 6828 }; 6829 6830 /* reg_rauht_op 6831 * Access: OP 6832 */ 6833 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 6834 6835 /* reg_rauht_a 6836 * Activity. Set for new entries. Set if a packet lookup has hit on 6837 * the specific entry. 6838 * To clear the a bit, use "clear activity" op. 6839 * Enabled by activity_dis in RGCR 6840 * Access: RO 6841 */ 6842 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 6843 6844 /* reg_rauht_rif 6845 * Router Interface 6846 * Access: Index 6847 */ 6848 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 6849 6850 /* reg_rauht_dip* 6851 * Destination address. 6852 * Access: Index 6853 */ 6854 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 6855 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 6856 6857 enum mlxsw_reg_rauht_trap_action { 6858 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 6859 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 6860 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 6861 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 6862 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 6863 }; 6864 6865 /* reg_rauht_trap_action 6866 * Access: RW 6867 */ 6868 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 6869 6870 enum mlxsw_reg_rauht_trap_id { 6871 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 6872 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 6873 }; 6874 6875 /* reg_rauht_trap_id 6876 * Trap ID to be reported to CPU. 6877 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6878 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 6879 * trap_id is reserved. 6880 * Access: RW 6881 */ 6882 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 6883 6884 /* reg_rauht_counter_set_type 6885 * Counter set type for flow counters 6886 * Access: RW 6887 */ 6888 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 6889 6890 /* reg_rauht_counter_index 6891 * Counter index for flow counters 6892 * Access: RW 6893 */ 6894 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 6895 6896 /* reg_rauht_mac 6897 * MAC address. 6898 * Access: RW 6899 */ 6900 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 6901 6902 static inline void mlxsw_reg_rauht_pack(char *payload, 6903 enum mlxsw_reg_rauht_op op, u16 rif, 6904 const char *mac) 6905 { 6906 MLXSW_REG_ZERO(rauht, payload); 6907 mlxsw_reg_rauht_op_set(payload, op); 6908 mlxsw_reg_rauht_rif_set(payload, rif); 6909 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 6910 } 6911 6912 static inline void mlxsw_reg_rauht_pack4(char *payload, 6913 enum mlxsw_reg_rauht_op op, u16 rif, 6914 const char *mac, u32 dip) 6915 { 6916 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6917 mlxsw_reg_rauht_dip4_set(payload, dip); 6918 } 6919 6920 static inline void mlxsw_reg_rauht_pack6(char *payload, 6921 enum mlxsw_reg_rauht_op op, u16 rif, 6922 const char *mac, const char *dip) 6923 { 6924 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6925 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 6926 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 6927 } 6928 6929 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 6930 u64 counter_index) 6931 { 6932 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 6933 mlxsw_reg_rauht_counter_set_type_set(payload, 6934 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 6935 } 6936 6937 /* RALEU - Router Algorithmic LPM ECMP Update Register 6938 * --------------------------------------------------- 6939 * The register enables updating the ECMP section in the action for multiple 6940 * LPM Unicast entries in a single operation. The update is executed to 6941 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 6942 */ 6943 #define MLXSW_REG_RALEU_ID 0x8015 6944 #define MLXSW_REG_RALEU_LEN 0x28 6945 6946 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 6947 6948 /* reg_raleu_protocol 6949 * Protocol. 6950 * Access: Index 6951 */ 6952 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 6953 6954 /* reg_raleu_virtual_router 6955 * Virtual Router ID 6956 * Range is 0..cap_max_virtual_routers-1 6957 * Access: Index 6958 */ 6959 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 6960 6961 /* reg_raleu_adjacency_index 6962 * Adjacency Index used for matching on the existing entries. 6963 * Access: Index 6964 */ 6965 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 6966 6967 /* reg_raleu_ecmp_size 6968 * ECMP Size used for matching on the existing entries. 6969 * Access: Index 6970 */ 6971 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 6972 6973 /* reg_raleu_new_adjacency_index 6974 * New Adjacency Index. 6975 * Access: WO 6976 */ 6977 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 6978 6979 /* reg_raleu_new_ecmp_size 6980 * New ECMP Size. 6981 * Access: WO 6982 */ 6983 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 6984 6985 static inline void mlxsw_reg_raleu_pack(char *payload, 6986 enum mlxsw_reg_ralxx_protocol protocol, 6987 u16 virtual_router, 6988 u32 adjacency_index, u16 ecmp_size, 6989 u32 new_adjacency_index, 6990 u16 new_ecmp_size) 6991 { 6992 MLXSW_REG_ZERO(raleu, payload); 6993 mlxsw_reg_raleu_protocol_set(payload, protocol); 6994 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 6995 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 6996 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 6997 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 6998 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 6999 } 7000 7001 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7002 * ---------------------------------------------------------------- 7003 * The RAUHTD register allows dumping entries from the Router Unicast Host 7004 * Table. For a given session an entry is dumped no more than one time. The 7005 * first RAUHTD access after reset is a new session. A session ends when the 7006 * num_rec response is smaller than num_rec request or for IPv4 when the 7007 * num_entries is smaller than 4. The clear activity affect the current session 7008 * or the last session if a new session has not started. 7009 */ 7010 #define MLXSW_REG_RAUHTD_ID 0x8018 7011 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7012 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7013 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7014 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7015 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7016 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7017 7018 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7019 7020 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7021 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7022 7023 /* reg_rauhtd_filter_fields 7024 * if a bit is '0' then the relevant field is ignored and dump is done 7025 * regardless of the field value 7026 * Bit0 - filter by activity: entry_a 7027 * Bit3 - filter by entry rip: entry_rif 7028 * Access: Index 7029 */ 7030 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7031 7032 enum mlxsw_reg_rauhtd_op { 7033 MLXSW_REG_RAUHTD_OP_DUMP, 7034 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7035 }; 7036 7037 /* reg_rauhtd_op 7038 * Access: OP 7039 */ 7040 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7041 7042 /* reg_rauhtd_num_rec 7043 * At request: number of records requested 7044 * At response: number of records dumped 7045 * For IPv4, each record has 4 entries at request and up to 4 entries 7046 * at response 7047 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7048 * Access: Index 7049 */ 7050 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7051 7052 /* reg_rauhtd_entry_a 7053 * Dump only if activity has value of entry_a 7054 * Reserved if filter_fields bit0 is '0' 7055 * Access: Index 7056 */ 7057 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7058 7059 enum mlxsw_reg_rauhtd_type { 7060 MLXSW_REG_RAUHTD_TYPE_IPV4, 7061 MLXSW_REG_RAUHTD_TYPE_IPV6, 7062 }; 7063 7064 /* reg_rauhtd_type 7065 * Dump only if record type is: 7066 * 0 - IPv4 7067 * 1 - IPv6 7068 * Access: Index 7069 */ 7070 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7071 7072 /* reg_rauhtd_entry_rif 7073 * Dump only if RIF has value of entry_rif 7074 * Reserved if filter_fields bit3 is '0' 7075 * Access: Index 7076 */ 7077 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7078 7079 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7080 enum mlxsw_reg_rauhtd_type type) 7081 { 7082 MLXSW_REG_ZERO(rauhtd, payload); 7083 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7084 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7085 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7086 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7087 mlxsw_reg_rauhtd_type_set(payload, type); 7088 } 7089 7090 /* reg_rauhtd_ipv4_rec_num_entries 7091 * Number of valid entries in this record: 7092 * 0 - 1 valid entry 7093 * 1 - 2 valid entries 7094 * 2 - 3 valid entries 7095 * 3 - 4 valid entries 7096 * Access: RO 7097 */ 7098 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7099 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7100 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7101 7102 /* reg_rauhtd_rec_type 7103 * Record type. 7104 * 0 - IPv4 7105 * 1 - IPv6 7106 * Access: RO 7107 */ 7108 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7109 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7110 7111 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7112 7113 /* reg_rauhtd_ipv4_ent_a 7114 * Activity. Set for new entries. Set if a packet lookup has hit on the 7115 * specific entry. 7116 * Access: RO 7117 */ 7118 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7119 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7120 7121 /* reg_rauhtd_ipv4_ent_rif 7122 * Router interface. 7123 * Access: RO 7124 */ 7125 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7126 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7127 7128 /* reg_rauhtd_ipv4_ent_dip 7129 * Destination IPv4 address. 7130 * Access: RO 7131 */ 7132 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7133 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7134 7135 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7136 7137 /* reg_rauhtd_ipv6_ent_a 7138 * Activity. Set for new entries. Set if a packet lookup has hit on the 7139 * specific entry. 7140 * Access: RO 7141 */ 7142 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7143 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7144 7145 /* reg_rauhtd_ipv6_ent_rif 7146 * Router interface. 7147 * Access: RO 7148 */ 7149 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7150 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7151 7152 /* reg_rauhtd_ipv6_ent_dip 7153 * Destination IPv6 address. 7154 * Access: RO 7155 */ 7156 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7157 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7158 7159 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7160 int ent_index, u16 *p_rif, 7161 u32 *p_dip) 7162 { 7163 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7164 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7165 } 7166 7167 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7168 int rec_index, u16 *p_rif, 7169 char *p_dip) 7170 { 7171 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7172 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7173 } 7174 7175 /* RTDP - Routing Tunnel Decap Properties Register 7176 * ----------------------------------------------- 7177 * The RTDP register is used for configuring the tunnel decap properties of NVE 7178 * and IPinIP. 7179 */ 7180 #define MLXSW_REG_RTDP_ID 0x8020 7181 #define MLXSW_REG_RTDP_LEN 0x44 7182 7183 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7184 7185 enum mlxsw_reg_rtdp_type { 7186 MLXSW_REG_RTDP_TYPE_NVE, 7187 MLXSW_REG_RTDP_TYPE_IPIP, 7188 }; 7189 7190 /* reg_rtdp_type 7191 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7192 * Access: RW 7193 */ 7194 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7195 7196 /* reg_rtdp_tunnel_index 7197 * Index to the Decap entry. 7198 * For Spectrum, Index to KVD Linear. 7199 * Access: Index 7200 */ 7201 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7202 7203 /* IPinIP */ 7204 7205 /* reg_rtdp_ipip_irif 7206 * Ingress Router Interface for the overlay router 7207 * Access: RW 7208 */ 7209 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7210 7211 enum mlxsw_reg_rtdp_ipip_sip_check { 7212 /* No sip checks. */ 7213 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7214 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7215 * equal ipv4_usip. 7216 */ 7217 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7218 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7219 * equal ipv6_usip. 7220 */ 7221 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7222 }; 7223 7224 /* reg_rtdp_ipip_sip_check 7225 * SIP check to perform. If decapsulation failed due to these configurations 7226 * then trap_id is IPIP_DECAP_ERROR. 7227 * Access: RW 7228 */ 7229 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7230 7231 /* If set, allow decapsulation of IPinIP (without GRE). */ 7232 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7233 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7234 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7235 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7236 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7237 7238 /* reg_rtdp_ipip_type_check 7239 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7240 * these configurations then trap_id is IPIP_DECAP_ERROR. 7241 * Access: RW 7242 */ 7243 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7244 7245 /* reg_rtdp_ipip_gre_key_check 7246 * Whether GRE key should be checked. When check is enabled: 7247 * - A packet received as IPinIP (without GRE) will always pass. 7248 * - A packet received as IPinGREinIP without a key will not pass the check. 7249 * - A packet received as IPinGREinIP with a key will pass the check only if the 7250 * key in the packet is equal to expected_gre_key. 7251 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7252 * Access: RW 7253 */ 7254 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7255 7256 /* reg_rtdp_ipip_ipv4_usip 7257 * Underlay IPv4 address for ipv4 source address check. 7258 * Reserved when sip_check is not '1'. 7259 * Access: RW 7260 */ 7261 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7262 7263 /* reg_rtdp_ipip_ipv6_usip_ptr 7264 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7265 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7266 * is to the KVD linear. 7267 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7268 * Access: RW 7269 */ 7270 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7271 7272 /* reg_rtdp_ipip_expected_gre_key 7273 * GRE key for checking. 7274 * Reserved when gre_key_check is '0'. 7275 * Access: RW 7276 */ 7277 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7278 7279 static inline void mlxsw_reg_rtdp_pack(char *payload, 7280 enum mlxsw_reg_rtdp_type type, 7281 u32 tunnel_index) 7282 { 7283 MLXSW_REG_ZERO(rtdp, payload); 7284 mlxsw_reg_rtdp_type_set(payload, type); 7285 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7286 } 7287 7288 static inline void 7289 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7290 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7291 unsigned int type_check, bool gre_key_check, 7292 u32 ipv4_usip, u32 expected_gre_key) 7293 { 7294 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7295 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7296 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7297 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7298 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7299 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7300 } 7301 7302 /* RIGR-V2 - Router Interface Group Register Version 2 7303 * --------------------------------------------------- 7304 * The RIGR_V2 register is used to add, remove and query egress interface list 7305 * of a multicast forwarding entry. 7306 */ 7307 #define MLXSW_REG_RIGR2_ID 0x8023 7308 #define MLXSW_REG_RIGR2_LEN 0xB0 7309 7310 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7311 7312 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7313 7314 /* reg_rigr2_rigr_index 7315 * KVD Linear index. 7316 * Access: Index 7317 */ 7318 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7319 7320 /* reg_rigr2_vnext 7321 * Next RIGR Index is valid. 7322 * Access: RW 7323 */ 7324 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7325 7326 /* reg_rigr2_next_rigr_index 7327 * Next RIGR Index. The index is to the KVD linear. 7328 * Reserved when vnxet = '0'. 7329 * Access: RW 7330 */ 7331 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7332 7333 /* reg_rigr2_vrmid 7334 * RMID Index is valid. 7335 * Access: RW 7336 */ 7337 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7338 7339 /* reg_rigr2_rmid_index 7340 * RMID Index. 7341 * Range 0 .. max_mid - 1 7342 * Reserved when vrmid = '0'. 7343 * The index is to the Port Group Table (PGT) 7344 * Access: RW 7345 */ 7346 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7347 7348 /* reg_rigr2_erif_entry_v 7349 * Egress Router Interface is valid. 7350 * Note that low-entries must be set if high-entries are set. For 7351 * example: if erif_entry[2].v is set then erif_entry[1].v and 7352 * erif_entry[0].v must be set. 7353 * Index can be from 0 to cap_mc_erif_list_entries-1 7354 * Access: RW 7355 */ 7356 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7357 7358 /* reg_rigr2_erif_entry_erif 7359 * Egress Router Interface. 7360 * Valid range is from 0 to cap_max_router_interfaces - 1 7361 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7362 * Access: RW 7363 */ 7364 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7365 7366 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7367 bool vnext, u32 next_rigr_index) 7368 { 7369 MLXSW_REG_ZERO(rigr2, payload); 7370 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7371 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7372 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7373 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7374 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7375 } 7376 7377 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7378 bool v, u16 erif) 7379 { 7380 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7381 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7382 } 7383 7384 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7385 * ------------------------------------------------------ 7386 */ 7387 #define MLXSW_REG_RECR2_ID 0x8025 7388 #define MLXSW_REG_RECR2_LEN 0x38 7389 7390 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7391 7392 /* reg_recr2_pp 7393 * Per-port configuration 7394 * Access: Index 7395 */ 7396 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7397 7398 /* reg_recr2_sh 7399 * Symmetric hash 7400 * Access: RW 7401 */ 7402 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7403 7404 /* reg_recr2_seed 7405 * Seed 7406 * Access: RW 7407 */ 7408 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7409 7410 enum { 7411 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7412 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7413 /* Enable IPv4 fields if packet is TCP or UDP */ 7414 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7415 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7416 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7417 /* Enable IPv6 fields if packet is TCP or UDP */ 7418 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7419 /* Enable TCP/UDP header fields if packet is IPv4 */ 7420 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7421 /* Enable TCP/UDP header fields if packet is IPv6 */ 7422 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7423 }; 7424 7425 /* reg_recr2_outer_header_enables 7426 * Bit mask where each bit enables a specific layer to be included in 7427 * the hash calculation. 7428 * Access: RW 7429 */ 7430 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7431 7432 enum { 7433 /* IPv4 Source IP */ 7434 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7435 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7436 /* IPv4 Destination IP */ 7437 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7438 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7439 /* IP Protocol */ 7440 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7441 /* IPv6 Source IP */ 7442 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7443 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7444 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7445 /* IPv6 Destination IP */ 7446 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7447 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7448 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7449 /* IPv6 Next Header */ 7450 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7451 /* IPv6 Flow Label */ 7452 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7453 /* TCP/UDP Source Port */ 7454 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7455 /* TCP/UDP Destination Port */ 7456 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7457 }; 7458 7459 /* reg_recr2_outer_header_fields_enable 7460 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7461 * Access: RW 7462 */ 7463 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7464 7465 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7466 { 7467 int i; 7468 7469 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7470 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7471 true); 7472 } 7473 7474 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7475 { 7476 int i; 7477 7478 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7479 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7480 true); 7481 } 7482 7483 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7484 { 7485 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7486 7487 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7488 7489 i = MLXSW_REG_RECR2_IPV6_SIP8; 7490 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7491 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7492 true); 7493 } 7494 7495 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7496 { 7497 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7498 7499 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7500 7501 i = MLXSW_REG_RECR2_IPV6_DIP8; 7502 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7503 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7504 true); 7505 } 7506 7507 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7508 { 7509 MLXSW_REG_ZERO(recr2, payload); 7510 mlxsw_reg_recr2_pp_set(payload, false); 7511 mlxsw_reg_recr2_sh_set(payload, true); 7512 mlxsw_reg_recr2_seed_set(payload, seed); 7513 } 7514 7515 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7516 * -------------------------------------------------------------- 7517 * The RMFT_V2 register is used to configure and query the multicast table. 7518 */ 7519 #define MLXSW_REG_RMFT2_ID 0x8027 7520 #define MLXSW_REG_RMFT2_LEN 0x174 7521 7522 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7523 7524 /* reg_rmft2_v 7525 * Valid 7526 * Access: RW 7527 */ 7528 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7529 7530 enum mlxsw_reg_rmft2_type { 7531 MLXSW_REG_RMFT2_TYPE_IPV4, 7532 MLXSW_REG_RMFT2_TYPE_IPV6 7533 }; 7534 7535 /* reg_rmft2_type 7536 * Access: Index 7537 */ 7538 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7539 7540 enum mlxsw_sp_reg_rmft2_op { 7541 /* For Write: 7542 * Write operation. Used to write a new entry to the table. All RW 7543 * fields are relevant for new entry. Activity bit is set for new 7544 * entries - Note write with v (Valid) 0 will delete the entry. 7545 * For Query: 7546 * Read operation 7547 */ 7548 MLXSW_REG_RMFT2_OP_READ_WRITE, 7549 }; 7550 7551 /* reg_rmft2_op 7552 * Operation. 7553 * Access: OP 7554 */ 7555 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7556 7557 /* reg_rmft2_a 7558 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7559 * entry. 7560 * Access: RO 7561 */ 7562 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7563 7564 /* reg_rmft2_offset 7565 * Offset within the multicast forwarding table to write to. 7566 * Access: Index 7567 */ 7568 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7569 7570 /* reg_rmft2_virtual_router 7571 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7572 * Access: RW 7573 */ 7574 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7575 7576 enum mlxsw_reg_rmft2_irif_mask { 7577 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7578 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7579 }; 7580 7581 /* reg_rmft2_irif_mask 7582 * Ingress RIF mask. 7583 * Access: RW 7584 */ 7585 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7586 7587 /* reg_rmft2_irif 7588 * Ingress RIF index. 7589 * Access: RW 7590 */ 7591 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7592 7593 /* reg_rmft2_dip{4,6} 7594 * Destination IPv4/6 address 7595 * Access: RW 7596 */ 7597 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7598 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7599 7600 /* reg_rmft2_dip{4,6}_mask 7601 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7602 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7603 * Access: RW 7604 */ 7605 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7606 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7607 7608 /* reg_rmft2_sip{4,6} 7609 * Source IPv4/6 address 7610 * Access: RW 7611 */ 7612 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7613 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7614 7615 /* reg_rmft2_sip{4,6}_mask 7616 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7617 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7618 * Access: RW 7619 */ 7620 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7621 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7622 7623 /* reg_rmft2_flexible_action_set 7624 * ACL action set. The only supported action types in this field and in any 7625 * action-set pointed from here are as follows: 7626 * 00h: ACTION_NULL 7627 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7628 * 03h: ACTION_TRAP 7629 * 06h: ACTION_QOS 7630 * 08h: ACTION_POLICING_MONITORING 7631 * 10h: ACTION_ROUTER_MC 7632 * Access: RW 7633 */ 7634 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7635 MLXSW_REG_FLEX_ACTION_SET_LEN); 7636 7637 static inline void 7638 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7639 u16 virtual_router, 7640 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7641 const char *flex_action_set) 7642 { 7643 MLXSW_REG_ZERO(rmft2, payload); 7644 mlxsw_reg_rmft2_v_set(payload, v); 7645 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7646 mlxsw_reg_rmft2_offset_set(payload, offset); 7647 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7648 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7649 mlxsw_reg_rmft2_irif_set(payload, irif); 7650 if (flex_action_set) 7651 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7652 flex_action_set); 7653 } 7654 7655 static inline void 7656 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7657 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7658 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7659 const char *flexible_action_set) 7660 { 7661 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7662 irif_mask, irif, flexible_action_set); 7663 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7664 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7665 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7666 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7667 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7668 } 7669 7670 static inline void 7671 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7672 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7673 struct in6_addr dip6, struct in6_addr dip6_mask, 7674 struct in6_addr sip6, struct in6_addr sip6_mask, 7675 const char *flexible_action_set) 7676 { 7677 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7678 irif_mask, irif, flexible_action_set); 7679 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 7680 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 7681 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 7682 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 7683 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 7684 } 7685 7686 /* MFCR - Management Fan Control Register 7687 * -------------------------------------- 7688 * This register controls the settings of the Fan Speed PWM mechanism. 7689 */ 7690 #define MLXSW_REG_MFCR_ID 0x9001 7691 #define MLXSW_REG_MFCR_LEN 0x08 7692 7693 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 7694 7695 enum mlxsw_reg_mfcr_pwm_frequency { 7696 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 7697 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 7698 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 7699 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 7700 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 7701 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 7702 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 7703 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 7704 }; 7705 7706 /* reg_mfcr_pwm_frequency 7707 * Controls the frequency of the PWM signal. 7708 * Access: RW 7709 */ 7710 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 7711 7712 #define MLXSW_MFCR_TACHOS_MAX 10 7713 7714 /* reg_mfcr_tacho_active 7715 * Indicates which of the tachometer is active (bit per tachometer). 7716 * Access: RO 7717 */ 7718 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 7719 7720 #define MLXSW_MFCR_PWMS_MAX 5 7721 7722 /* reg_mfcr_pwm_active 7723 * Indicates which of the PWM control is active (bit per PWM). 7724 * Access: RO 7725 */ 7726 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 7727 7728 static inline void 7729 mlxsw_reg_mfcr_pack(char *payload, 7730 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 7731 { 7732 MLXSW_REG_ZERO(mfcr, payload); 7733 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 7734 } 7735 7736 static inline void 7737 mlxsw_reg_mfcr_unpack(char *payload, 7738 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 7739 u16 *p_tacho_active, u8 *p_pwm_active) 7740 { 7741 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 7742 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 7743 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 7744 } 7745 7746 /* MFSC - Management Fan Speed Control Register 7747 * -------------------------------------------- 7748 * This register controls the settings of the Fan Speed PWM mechanism. 7749 */ 7750 #define MLXSW_REG_MFSC_ID 0x9002 7751 #define MLXSW_REG_MFSC_LEN 0x08 7752 7753 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 7754 7755 /* reg_mfsc_pwm 7756 * Fan pwm to control / monitor. 7757 * Access: Index 7758 */ 7759 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 7760 7761 /* reg_mfsc_pwm_duty_cycle 7762 * Controls the duty cycle of the PWM. Value range from 0..255 to 7763 * represent duty cycle of 0%...100%. 7764 * Access: RW 7765 */ 7766 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 7767 7768 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 7769 u8 pwm_duty_cycle) 7770 { 7771 MLXSW_REG_ZERO(mfsc, payload); 7772 mlxsw_reg_mfsc_pwm_set(payload, pwm); 7773 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 7774 } 7775 7776 /* MFSM - Management Fan Speed Measurement 7777 * --------------------------------------- 7778 * This register controls the settings of the Tacho measurements and 7779 * enables reading the Tachometer measurements. 7780 */ 7781 #define MLXSW_REG_MFSM_ID 0x9003 7782 #define MLXSW_REG_MFSM_LEN 0x08 7783 7784 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 7785 7786 /* reg_mfsm_tacho 7787 * Fan tachometer index. 7788 * Access: Index 7789 */ 7790 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 7791 7792 /* reg_mfsm_rpm 7793 * Fan speed (round per minute). 7794 * Access: RO 7795 */ 7796 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 7797 7798 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 7799 { 7800 MLXSW_REG_ZERO(mfsm, payload); 7801 mlxsw_reg_mfsm_tacho_set(payload, tacho); 7802 } 7803 7804 /* MFSL - Management Fan Speed Limit Register 7805 * ------------------------------------------ 7806 * The Fan Speed Limit register is used to configure the fan speed 7807 * event / interrupt notification mechanism. Fan speed threshold are 7808 * defined for both under-speed and over-speed. 7809 */ 7810 #define MLXSW_REG_MFSL_ID 0x9004 7811 #define MLXSW_REG_MFSL_LEN 0x0C 7812 7813 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 7814 7815 /* reg_mfsl_tacho 7816 * Fan tachometer index. 7817 * Access: Index 7818 */ 7819 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 7820 7821 /* reg_mfsl_tach_min 7822 * Tachometer minimum value (minimum RPM). 7823 * Access: RW 7824 */ 7825 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 7826 7827 /* reg_mfsl_tach_max 7828 * Tachometer maximum value (maximum RPM). 7829 * Access: RW 7830 */ 7831 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 7832 7833 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 7834 u16 tach_min, u16 tach_max) 7835 { 7836 MLXSW_REG_ZERO(mfsl, payload); 7837 mlxsw_reg_mfsl_tacho_set(payload, tacho); 7838 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 7839 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 7840 } 7841 7842 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 7843 u16 *p_tach_min, u16 *p_tach_max) 7844 { 7845 if (p_tach_min) 7846 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 7847 7848 if (p_tach_max) 7849 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 7850 } 7851 7852 /* MTCAP - Management Temperature Capabilities 7853 * ------------------------------------------- 7854 * This register exposes the capabilities of the device and 7855 * system temperature sensing. 7856 */ 7857 #define MLXSW_REG_MTCAP_ID 0x9009 7858 #define MLXSW_REG_MTCAP_LEN 0x08 7859 7860 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 7861 7862 /* reg_mtcap_sensor_count 7863 * Number of sensors supported by the device. 7864 * This includes the QSFP module sensors (if exists in the QSFP module). 7865 * Access: RO 7866 */ 7867 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 7868 7869 /* MTMP - Management Temperature 7870 * ----------------------------- 7871 * This register controls the settings of the temperature measurements 7872 * and enables reading the temperature measurements. Note that temperature 7873 * is in 0.125 degrees Celsius. 7874 */ 7875 #define MLXSW_REG_MTMP_ID 0x900A 7876 #define MLXSW_REG_MTMP_LEN 0x20 7877 7878 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 7879 7880 /* reg_mtmp_sensor_index 7881 * Sensors index to access. 7882 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 7883 * (module 0 is mapped to sensor_index 64). 7884 * Access: Index 7885 */ 7886 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 7887 7888 /* Convert to milli degrees Celsius */ 7889 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 7890 7891 /* reg_mtmp_temperature 7892 * Temperature reading from the sensor. Reading is in 0.125 Celsius 7893 * degrees units. 7894 * Access: RO 7895 */ 7896 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 7897 7898 /* reg_mtmp_mte 7899 * Max Temperature Enable - enables measuring the max temperature on a sensor. 7900 * Access: RW 7901 */ 7902 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 7903 7904 /* reg_mtmp_mtr 7905 * Max Temperature Reset - clears the value of the max temperature register. 7906 * Access: WO 7907 */ 7908 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 7909 7910 /* reg_mtmp_max_temperature 7911 * The highest measured temperature from the sensor. 7912 * When the bit mte is cleared, the field max_temperature is reserved. 7913 * Access: RO 7914 */ 7915 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 7916 7917 /* reg_mtmp_tee 7918 * Temperature Event Enable. 7919 * 0 - Do not generate event 7920 * 1 - Generate event 7921 * 2 - Generate single event 7922 * Access: RW 7923 */ 7924 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 7925 7926 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 7927 7928 /* reg_mtmp_temperature_threshold_hi 7929 * High threshold for Temperature Warning Event. In 0.125 Celsius. 7930 * Access: RW 7931 */ 7932 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 7933 7934 /* reg_mtmp_temperature_threshold_lo 7935 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 7936 * Access: RW 7937 */ 7938 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 7939 7940 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 7941 7942 /* reg_mtmp_sensor_name 7943 * Sensor Name 7944 * Access: RO 7945 */ 7946 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 7947 7948 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 7949 bool max_temp_enable, 7950 bool max_temp_reset) 7951 { 7952 MLXSW_REG_ZERO(mtmp, payload); 7953 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 7954 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 7955 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 7956 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 7957 MLXSW_REG_MTMP_THRESH_HI); 7958 } 7959 7960 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 7961 unsigned int *p_max_temp, 7962 char *sensor_name) 7963 { 7964 u16 temp; 7965 7966 if (p_temp) { 7967 temp = mlxsw_reg_mtmp_temperature_get(payload); 7968 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7969 } 7970 if (p_max_temp) { 7971 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 7972 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7973 } 7974 if (sensor_name) 7975 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 7976 } 7977 7978 /* MCIA - Management Cable Info Access 7979 * ----------------------------------- 7980 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 7981 */ 7982 7983 #define MLXSW_REG_MCIA_ID 0x9014 7984 #define MLXSW_REG_MCIA_LEN 0x40 7985 7986 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 7987 7988 /* reg_mcia_l 7989 * Lock bit. Setting this bit will lock the access to the specific 7990 * cable. Used for updating a full page in a cable EPROM. Any access 7991 * other then subsequence writes will fail while the port is locked. 7992 * Access: RW 7993 */ 7994 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 7995 7996 /* reg_mcia_module 7997 * Module number. 7998 * Access: Index 7999 */ 8000 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8001 8002 /* reg_mcia_status 8003 * Module status. 8004 * Access: RO 8005 */ 8006 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8007 8008 /* reg_mcia_i2c_device_address 8009 * I2C device address. 8010 * Access: RW 8011 */ 8012 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8013 8014 /* reg_mcia_page_number 8015 * Page number. 8016 * Access: RW 8017 */ 8018 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8019 8020 /* reg_mcia_device_address 8021 * Device address. 8022 * Access: RW 8023 */ 8024 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8025 8026 /* reg_mcia_size 8027 * Number of bytes to read/write (up to 48 bytes). 8028 * Access: RW 8029 */ 8030 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8031 8032 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 8033 8034 /* reg_mcia_eeprom 8035 * Bytes to read/write. 8036 * Access: RW 8037 */ 8038 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 8039 8040 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8041 u8 page_number, u16 device_addr, 8042 u8 size, u8 i2c_device_addr) 8043 { 8044 MLXSW_REG_ZERO(mcia, payload); 8045 mlxsw_reg_mcia_module_set(payload, module); 8046 mlxsw_reg_mcia_l_set(payload, lock); 8047 mlxsw_reg_mcia_page_number_set(payload, page_number); 8048 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8049 mlxsw_reg_mcia_size_set(payload, size); 8050 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8051 } 8052 8053 /* MPAT - Monitoring Port Analyzer Table 8054 * ------------------------------------- 8055 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8056 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8057 */ 8058 #define MLXSW_REG_MPAT_ID 0x901A 8059 #define MLXSW_REG_MPAT_LEN 0x78 8060 8061 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8062 8063 /* reg_mpat_pa_id 8064 * Port Analyzer ID. 8065 * Access: Index 8066 */ 8067 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8068 8069 /* reg_mpat_system_port 8070 * A unique port identifier for the final destination of the packet. 8071 * Access: RW 8072 */ 8073 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8074 8075 /* reg_mpat_e 8076 * Enable. Indicating the Port Analyzer is enabled. 8077 * Access: RW 8078 */ 8079 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8080 8081 /* reg_mpat_qos 8082 * Quality Of Service Mode. 8083 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8084 * PCP, DEI, DSCP or VL) are configured. 8085 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8086 * same as in the original packet that has triggered the mirroring. For 8087 * SPAN also the pcp,dei are maintained. 8088 * Access: RW 8089 */ 8090 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8091 8092 /* reg_mpat_be 8093 * Best effort mode. Indicates mirroring traffic should not cause packet 8094 * drop or back pressure, but will discard the mirrored packets. Mirrored 8095 * packets will be forwarded on a best effort manner. 8096 * 0: Do not discard mirrored packets 8097 * 1: Discard mirrored packets if causing congestion 8098 * Access: RW 8099 */ 8100 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8101 8102 enum mlxsw_reg_mpat_span_type { 8103 /* Local SPAN Ethernet. 8104 * The original packet is not encapsulated. 8105 */ 8106 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8107 8108 /* Remote SPAN Ethernet VLAN. 8109 * The packet is forwarded to the monitoring port on the monitoring 8110 * VLAN. 8111 */ 8112 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8113 8114 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8115 * The packet is encapsulated with GRE header. 8116 */ 8117 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8118 }; 8119 8120 /* reg_mpat_span_type 8121 * SPAN type. 8122 * Access: RW 8123 */ 8124 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8125 8126 /* Remote SPAN - Ethernet VLAN 8127 * - - - - - - - - - - - - - - 8128 */ 8129 8130 /* reg_mpat_eth_rspan_vid 8131 * Encapsulation header VLAN ID. 8132 * Access: RW 8133 */ 8134 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8135 8136 /* Encapsulated Remote SPAN - Ethernet L2 8137 * - - - - - - - - - - - - - - - - - - - 8138 */ 8139 8140 enum mlxsw_reg_mpat_eth_rspan_version { 8141 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8142 }; 8143 8144 /* reg_mpat_eth_rspan_version 8145 * RSPAN mirror header version. 8146 * Access: RW 8147 */ 8148 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8149 8150 /* reg_mpat_eth_rspan_mac 8151 * Destination MAC address. 8152 * Access: RW 8153 */ 8154 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8155 8156 /* reg_mpat_eth_rspan_tp 8157 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8158 * Access: RW 8159 */ 8160 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8161 8162 /* Encapsulated Remote SPAN - Ethernet L3 8163 * - - - - - - - - - - - - - - - - - - - 8164 */ 8165 8166 enum mlxsw_reg_mpat_eth_rspan_protocol { 8167 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8168 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8169 }; 8170 8171 /* reg_mpat_eth_rspan_protocol 8172 * SPAN encapsulation protocol. 8173 * Access: RW 8174 */ 8175 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8176 8177 /* reg_mpat_eth_rspan_ttl 8178 * Encapsulation header Time-to-Live/HopLimit. 8179 * Access: RW 8180 */ 8181 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8182 8183 /* reg_mpat_eth_rspan_smac 8184 * Source MAC address 8185 * Access: RW 8186 */ 8187 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8188 8189 /* reg_mpat_eth_rspan_dip* 8190 * Destination IP address. The IP version is configured by protocol. 8191 * Access: RW 8192 */ 8193 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8194 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8195 8196 /* reg_mpat_eth_rspan_sip* 8197 * Source IP address. The IP version is configured by protocol. 8198 * Access: RW 8199 */ 8200 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8201 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8202 8203 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8204 u16 system_port, bool e, 8205 enum mlxsw_reg_mpat_span_type span_type) 8206 { 8207 MLXSW_REG_ZERO(mpat, payload); 8208 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8209 mlxsw_reg_mpat_system_port_set(payload, system_port); 8210 mlxsw_reg_mpat_e_set(payload, e); 8211 mlxsw_reg_mpat_qos_set(payload, 1); 8212 mlxsw_reg_mpat_be_set(payload, 1); 8213 mlxsw_reg_mpat_span_type_set(payload, span_type); 8214 } 8215 8216 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8217 { 8218 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8219 } 8220 8221 static inline void 8222 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8223 enum mlxsw_reg_mpat_eth_rspan_version version, 8224 const char *mac, 8225 bool tp) 8226 { 8227 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8228 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8229 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8230 } 8231 8232 static inline void 8233 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8234 const char *smac, 8235 u32 sip, u32 dip) 8236 { 8237 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8238 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8239 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8240 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8241 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8242 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8243 } 8244 8245 static inline void 8246 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8247 const char *smac, 8248 struct in6_addr sip, struct in6_addr dip) 8249 { 8250 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8251 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8252 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8253 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8254 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8255 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8256 } 8257 8258 /* MPAR - Monitoring Port Analyzer Register 8259 * ---------------------------------------- 8260 * MPAR register is used to query and configure the port analyzer port mirroring 8261 * properties. 8262 */ 8263 #define MLXSW_REG_MPAR_ID 0x901B 8264 #define MLXSW_REG_MPAR_LEN 0x08 8265 8266 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8267 8268 /* reg_mpar_local_port 8269 * The local port to mirror the packets from. 8270 * Access: Index 8271 */ 8272 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8273 8274 enum mlxsw_reg_mpar_i_e { 8275 MLXSW_REG_MPAR_TYPE_EGRESS, 8276 MLXSW_REG_MPAR_TYPE_INGRESS, 8277 }; 8278 8279 /* reg_mpar_i_e 8280 * Ingress/Egress 8281 * Access: Index 8282 */ 8283 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8284 8285 /* reg_mpar_enable 8286 * Enable mirroring 8287 * By default, port mirroring is disabled for all ports. 8288 * Access: RW 8289 */ 8290 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8291 8292 /* reg_mpar_pa_id 8293 * Port Analyzer ID. 8294 * Access: RW 8295 */ 8296 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8297 8298 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8299 enum mlxsw_reg_mpar_i_e i_e, 8300 bool enable, u8 pa_id) 8301 { 8302 MLXSW_REG_ZERO(mpar, payload); 8303 mlxsw_reg_mpar_local_port_set(payload, local_port); 8304 mlxsw_reg_mpar_enable_set(payload, enable); 8305 mlxsw_reg_mpar_i_e_set(payload, i_e); 8306 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8307 } 8308 8309 /* MRSR - Management Reset and Shutdown Register 8310 * --------------------------------------------- 8311 * MRSR register is used to reset or shutdown the switch or 8312 * the entire system (when applicable). 8313 */ 8314 #define MLXSW_REG_MRSR_ID 0x9023 8315 #define MLXSW_REG_MRSR_LEN 0x08 8316 8317 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8318 8319 /* reg_mrsr_command 8320 * Reset/shutdown command 8321 * 0 - do nothing 8322 * 1 - software reset 8323 * Access: WO 8324 */ 8325 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8326 8327 static inline void mlxsw_reg_mrsr_pack(char *payload) 8328 { 8329 MLXSW_REG_ZERO(mrsr, payload); 8330 mlxsw_reg_mrsr_command_set(payload, 1); 8331 } 8332 8333 /* MLCR - Management LED Control Register 8334 * -------------------------------------- 8335 * Controls the system LEDs. 8336 */ 8337 #define MLXSW_REG_MLCR_ID 0x902B 8338 #define MLXSW_REG_MLCR_LEN 0x0C 8339 8340 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8341 8342 /* reg_mlcr_local_port 8343 * Local port number. 8344 * Access: RW 8345 */ 8346 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8347 8348 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8349 8350 /* reg_mlcr_beacon_duration 8351 * Duration of the beacon to be active, in seconds. 8352 * 0x0 - Will turn off the beacon. 8353 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8354 * Access: RW 8355 */ 8356 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8357 8358 /* reg_mlcr_beacon_remain 8359 * Remaining duration of the beacon, in seconds. 8360 * 0xFFFF indicates an infinite amount of time. 8361 * Access: RO 8362 */ 8363 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8364 8365 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8366 bool active) 8367 { 8368 MLXSW_REG_ZERO(mlcr, payload); 8369 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8370 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8371 MLXSW_REG_MLCR_DURATION_MAX : 0); 8372 } 8373 8374 /* MCQI - Management Component Query Information 8375 * --------------------------------------------- 8376 * This register allows querying information about firmware components. 8377 */ 8378 #define MLXSW_REG_MCQI_ID 0x9061 8379 #define MLXSW_REG_MCQI_BASE_LEN 0x18 8380 #define MLXSW_REG_MCQI_CAP_LEN 0x14 8381 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 8382 8383 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 8384 8385 /* reg_mcqi_component_index 8386 * Index of the accessed component. 8387 * Access: Index 8388 */ 8389 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 8390 8391 enum mlxfw_reg_mcqi_info_type { 8392 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 8393 }; 8394 8395 /* reg_mcqi_info_type 8396 * Component properties set. 8397 * Access: RW 8398 */ 8399 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 8400 8401 /* reg_mcqi_offset 8402 * The requested/returned data offset from the section start, given in bytes. 8403 * Must be DWORD aligned. 8404 * Access: RW 8405 */ 8406 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 8407 8408 /* reg_mcqi_data_size 8409 * The requested/returned data size, given in bytes. If data_size is not DWORD 8410 * aligned, the last bytes are zero padded. 8411 * Access: RW 8412 */ 8413 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 8414 8415 /* reg_mcqi_cap_max_component_size 8416 * Maximum size for this component, given in bytes. 8417 * Access: RO 8418 */ 8419 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 8420 8421 /* reg_mcqi_cap_log_mcda_word_size 8422 * Log 2 of the access word size in bytes. Read and write access must be aligned 8423 * to the word size. Write access must be done for an integer number of words. 8424 * Access: RO 8425 */ 8426 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 8427 8428 /* reg_mcqi_cap_mcda_max_write_size 8429 * Maximal write size for MCDA register 8430 * Access: RO 8431 */ 8432 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 8433 8434 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 8435 { 8436 MLXSW_REG_ZERO(mcqi, payload); 8437 mlxsw_reg_mcqi_component_index_set(payload, component_index); 8438 mlxsw_reg_mcqi_info_type_set(payload, 8439 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 8440 mlxsw_reg_mcqi_offset_set(payload, 0); 8441 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 8442 } 8443 8444 static inline void mlxsw_reg_mcqi_unpack(char *payload, 8445 u32 *p_cap_max_component_size, 8446 u8 *p_cap_log_mcda_word_size, 8447 u16 *p_cap_mcda_max_write_size) 8448 { 8449 *p_cap_max_component_size = 8450 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 8451 *p_cap_log_mcda_word_size = 8452 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 8453 *p_cap_mcda_max_write_size = 8454 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 8455 } 8456 8457 /* MCC - Management Component Control 8458 * ---------------------------------- 8459 * Controls the firmware component and updates the FSM. 8460 */ 8461 #define MLXSW_REG_MCC_ID 0x9062 8462 #define MLXSW_REG_MCC_LEN 0x1C 8463 8464 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 8465 8466 enum mlxsw_reg_mcc_instruction { 8467 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 8468 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 8469 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 8470 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 8471 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 8472 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 8473 }; 8474 8475 /* reg_mcc_instruction 8476 * Command to be executed by the FSM. 8477 * Applicable for write operation only. 8478 * Access: RW 8479 */ 8480 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 8481 8482 /* reg_mcc_component_index 8483 * Index of the accessed component. Applicable only for commands that 8484 * refer to components. Otherwise, this field is reserved. 8485 * Access: Index 8486 */ 8487 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 8488 8489 /* reg_mcc_update_handle 8490 * Token representing the current flow executed by the FSM. 8491 * Access: WO 8492 */ 8493 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 8494 8495 /* reg_mcc_error_code 8496 * Indicates the successful completion of the instruction, or the reason it 8497 * failed 8498 * Access: RO 8499 */ 8500 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 8501 8502 /* reg_mcc_control_state 8503 * Current FSM state 8504 * Access: RO 8505 */ 8506 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 8507 8508 /* reg_mcc_component_size 8509 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 8510 * the size may shorten the update time. Value 0x0 means that size is 8511 * unspecified. 8512 * Access: WO 8513 */ 8514 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 8515 8516 static inline void mlxsw_reg_mcc_pack(char *payload, 8517 enum mlxsw_reg_mcc_instruction instr, 8518 u16 component_index, u32 update_handle, 8519 u32 component_size) 8520 { 8521 MLXSW_REG_ZERO(mcc, payload); 8522 mlxsw_reg_mcc_instruction_set(payload, instr); 8523 mlxsw_reg_mcc_component_index_set(payload, component_index); 8524 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 8525 mlxsw_reg_mcc_component_size_set(payload, component_size); 8526 } 8527 8528 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 8529 u8 *p_error_code, u8 *p_control_state) 8530 { 8531 if (p_update_handle) 8532 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 8533 if (p_error_code) 8534 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 8535 if (p_control_state) 8536 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 8537 } 8538 8539 /* MCDA - Management Component Data Access 8540 * --------------------------------------- 8541 * This register allows reading and writing a firmware component. 8542 */ 8543 #define MLXSW_REG_MCDA_ID 0x9063 8544 #define MLXSW_REG_MCDA_BASE_LEN 0x10 8545 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 8546 #define MLXSW_REG_MCDA_LEN \ 8547 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 8548 8549 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 8550 8551 /* reg_mcda_update_handle 8552 * Token representing the current flow executed by the FSM. 8553 * Access: RW 8554 */ 8555 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 8556 8557 /* reg_mcda_offset 8558 * Offset of accessed address relative to component start. Accesses must be in 8559 * accordance to log_mcda_word_size in MCQI reg. 8560 * Access: RW 8561 */ 8562 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 8563 8564 /* reg_mcda_size 8565 * Size of the data accessed, given in bytes. 8566 * Access: RW 8567 */ 8568 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 8569 8570 /* reg_mcda_data 8571 * Data block accessed. 8572 * Access: RW 8573 */ 8574 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 8575 8576 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 8577 u32 offset, u16 size, u8 *data) 8578 { 8579 int i; 8580 8581 MLXSW_REG_ZERO(mcda, payload); 8582 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 8583 mlxsw_reg_mcda_offset_set(payload, offset); 8584 mlxsw_reg_mcda_size_set(payload, size); 8585 8586 for (i = 0; i < size / 4; i++) 8587 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 8588 } 8589 8590 /* MPSC - Monitoring Packet Sampling Configuration Register 8591 * -------------------------------------------------------- 8592 * MPSC Register is used to configure the Packet Sampling mechanism. 8593 */ 8594 #define MLXSW_REG_MPSC_ID 0x9080 8595 #define MLXSW_REG_MPSC_LEN 0x1C 8596 8597 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 8598 8599 /* reg_mpsc_local_port 8600 * Local port number 8601 * Not supported for CPU port 8602 * Access: Index 8603 */ 8604 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 8605 8606 /* reg_mpsc_e 8607 * Enable sampling on port local_port 8608 * Access: RW 8609 */ 8610 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 8611 8612 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 8613 8614 /* reg_mpsc_rate 8615 * Sampling rate = 1 out of rate packets (with randomization around 8616 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 8617 * Access: RW 8618 */ 8619 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 8620 8621 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 8622 u32 rate) 8623 { 8624 MLXSW_REG_ZERO(mpsc, payload); 8625 mlxsw_reg_mpsc_local_port_set(payload, local_port); 8626 mlxsw_reg_mpsc_e_set(payload, e); 8627 mlxsw_reg_mpsc_rate_set(payload, rate); 8628 } 8629 8630 /* MGPC - Monitoring General Purpose Counter Set Register 8631 * The MGPC register retrieves and sets the General Purpose Counter Set. 8632 */ 8633 #define MLXSW_REG_MGPC_ID 0x9081 8634 #define MLXSW_REG_MGPC_LEN 0x18 8635 8636 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 8637 8638 /* reg_mgpc_counter_set_type 8639 * Counter set type. 8640 * Access: OP 8641 */ 8642 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 8643 8644 /* reg_mgpc_counter_index 8645 * Counter index. 8646 * Access: Index 8647 */ 8648 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 8649 8650 enum mlxsw_reg_mgpc_opcode { 8651 /* Nop */ 8652 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 8653 /* Clear counters */ 8654 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 8655 }; 8656 8657 /* reg_mgpc_opcode 8658 * Opcode. 8659 * Access: OP 8660 */ 8661 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 8662 8663 /* reg_mgpc_byte_counter 8664 * Byte counter value. 8665 * Access: RW 8666 */ 8667 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 8668 8669 /* reg_mgpc_packet_counter 8670 * Packet counter value. 8671 * Access: RW 8672 */ 8673 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 8674 8675 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 8676 enum mlxsw_reg_mgpc_opcode opcode, 8677 enum mlxsw_reg_flow_counter_set_type set_type) 8678 { 8679 MLXSW_REG_ZERO(mgpc, payload); 8680 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 8681 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 8682 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8683 } 8684 8685 /* MPRS - Monitoring Parsing State Register 8686 * ---------------------------------------- 8687 * The MPRS register is used for setting up the parsing for hash, 8688 * policy-engine and routing. 8689 */ 8690 #define MLXSW_REG_MPRS_ID 0x9083 8691 #define MLXSW_REG_MPRS_LEN 0x14 8692 8693 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 8694 8695 /* reg_mprs_parsing_depth 8696 * Minimum parsing depth. 8697 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 8698 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 8699 * Access: RW 8700 */ 8701 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 8702 8703 /* reg_mprs_parsing_en 8704 * Parsing enable. 8705 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 8706 * NVGRE. Default is enabled. Reserved when SwitchX-2. 8707 * Access: RW 8708 */ 8709 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 8710 8711 /* reg_mprs_vxlan_udp_dport 8712 * VxLAN UDP destination port. 8713 * Used for identifying VxLAN packets and for dport field in 8714 * encapsulation. Default is 4789. 8715 * Access: RW 8716 */ 8717 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 8718 8719 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 8720 u16 vxlan_udp_dport) 8721 { 8722 MLXSW_REG_ZERO(mprs, payload); 8723 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 8724 mlxsw_reg_mprs_parsing_en_set(payload, true); 8725 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 8726 } 8727 8728 /* TNGCR - Tunneling NVE General Configuration Register 8729 * ---------------------------------------------------- 8730 * The TNGCR register is used for setting up the NVE Tunneling configuration. 8731 */ 8732 #define MLXSW_REG_TNGCR_ID 0xA001 8733 #define MLXSW_REG_TNGCR_LEN 0x44 8734 8735 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 8736 8737 enum mlxsw_reg_tngcr_type { 8738 MLXSW_REG_TNGCR_TYPE_VXLAN, 8739 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 8740 MLXSW_REG_TNGCR_TYPE_GENEVE, 8741 MLXSW_REG_TNGCR_TYPE_NVGRE, 8742 }; 8743 8744 /* reg_tngcr_type 8745 * Tunnel type for encapsulation and decapsulation. The types are mutually 8746 * exclusive. 8747 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 8748 * Access: RW 8749 */ 8750 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 8751 8752 /* reg_tngcr_nve_valid 8753 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 8754 * Access: RW 8755 */ 8756 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 8757 8758 /* reg_tngcr_nve_ttl_uc 8759 * The TTL for NVE tunnel encapsulation underlay unicast packets. 8760 * Access: RW 8761 */ 8762 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 8763 8764 /* reg_tngcr_nve_ttl_mc 8765 * The TTL for NVE tunnel encapsulation underlay multicast packets. 8766 * Access: RW 8767 */ 8768 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 8769 8770 enum { 8771 /* Do not copy flow label. Calculate flow label using nve_flh. */ 8772 MLXSW_REG_TNGCR_FL_NO_COPY, 8773 /* Copy flow label from inner packet if packet is IPv6 and 8774 * encapsulation is by IPv6. Otherwise, calculate flow label using 8775 * nve_flh. 8776 */ 8777 MLXSW_REG_TNGCR_FL_COPY, 8778 }; 8779 8780 /* reg_tngcr_nve_flc 8781 * For NVE tunnel encapsulation: Flow label copy from inner packet. 8782 * Access: RW 8783 */ 8784 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 8785 8786 enum { 8787 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 8788 * uses {nve_fl_prefix, nve_fl_suffix}. 8789 */ 8790 MLXSW_REG_TNGCR_FL_NO_HASH, 8791 /* 8 LSBs of the flow label are calculated from ECMP hash of the 8792 * inner packet. 12 MSBs are configured by nve_fl_prefix. 8793 */ 8794 MLXSW_REG_TNGCR_FL_HASH, 8795 }; 8796 8797 /* reg_tngcr_nve_flh 8798 * NVE flow label hash. 8799 * Access: RW 8800 */ 8801 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 8802 8803 /* reg_tngcr_nve_fl_prefix 8804 * NVE flow label prefix. Constant 12 MSBs of the flow label. 8805 * Access: RW 8806 */ 8807 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 8808 8809 /* reg_tngcr_nve_fl_suffix 8810 * NVE flow label suffix. Constant 8 LSBs of the flow label. 8811 * Reserved when nve_flh=1 and for Spectrum. 8812 * Access: RW 8813 */ 8814 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 8815 8816 enum { 8817 /* Source UDP port is fixed (default '0') */ 8818 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 8819 /* Source UDP port is calculated based on hash */ 8820 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 8821 }; 8822 8823 /* reg_tngcr_nve_udp_sport_type 8824 * NVE UDP source port type. 8825 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 8826 * When the source UDP port is calculated based on hash, then the 8 LSBs 8827 * are calculated from hash the 8 MSBs are configured by 8828 * nve_udp_sport_prefix. 8829 * Access: RW 8830 */ 8831 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 8832 8833 /* reg_tngcr_nve_udp_sport_prefix 8834 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 8835 * Reserved when NVE type is NVGRE. 8836 * Access: RW 8837 */ 8838 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 8839 8840 /* reg_tngcr_nve_group_size_mc 8841 * The amount of sequential linked lists of MC entries. The first linked 8842 * list is configured by SFD.underlay_mc_ptr. 8843 * Valid values: 1, 2, 4, 8, 16, 32, 64 8844 * The linked list are configured by TNUMT. 8845 * The hash is set by LAG hash. 8846 * Access: RW 8847 */ 8848 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 8849 8850 /* reg_tngcr_nve_group_size_flood 8851 * The amount of sequential linked lists of flooding entries. The first 8852 * linked list is configured by SFMR.nve_tunnel_flood_ptr 8853 * Valid values: 1, 2, 4, 8, 16, 32, 64 8854 * The linked list are configured by TNUMT. 8855 * The hash is set by LAG hash. 8856 * Access: RW 8857 */ 8858 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 8859 8860 /* reg_tngcr_learn_enable 8861 * During decapsulation, whether to learn from NVE port. 8862 * Reserved when Spectrum-2. See TNPC. 8863 * Access: RW 8864 */ 8865 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 8866 8867 /* reg_tngcr_underlay_virtual_router 8868 * Underlay virtual router. 8869 * Reserved when Spectrum-2. 8870 * Access: RW 8871 */ 8872 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 8873 8874 /* reg_tngcr_underlay_rif 8875 * Underlay ingress router interface. RIF type should be loopback generic. 8876 * Reserved when Spectrum. 8877 * Access: RW 8878 */ 8879 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 8880 8881 /* reg_tngcr_usipv4 8882 * Underlay source IPv4 address of the NVE. 8883 * Access: RW 8884 */ 8885 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 8886 8887 /* reg_tngcr_usipv6 8888 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 8889 * modified under traffic of NVE tunneling encapsulation. 8890 * Access: RW 8891 */ 8892 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 8893 8894 static inline void mlxsw_reg_tngcr_pack(char *payload, 8895 enum mlxsw_reg_tngcr_type type, 8896 bool valid, u8 ttl) 8897 { 8898 MLXSW_REG_ZERO(tngcr, payload); 8899 mlxsw_reg_tngcr_type_set(payload, type); 8900 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 8901 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 8902 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 8903 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 8904 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 8905 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 8906 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 8907 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 8908 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 8909 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 8910 } 8911 8912 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 8913 * ------------------------------------------------------- 8914 * The TNUMT register is for building the underlay MC table. It is used 8915 * for MC, flooding and BC traffic into the NVE tunnel. 8916 */ 8917 #define MLXSW_REG_TNUMT_ID 0xA003 8918 #define MLXSW_REG_TNUMT_LEN 0x20 8919 8920 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 8921 8922 enum mlxsw_reg_tnumt_record_type { 8923 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 8924 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 8925 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 8926 }; 8927 8928 /* reg_tnumt_record_type 8929 * Record type. 8930 * Access: RW 8931 */ 8932 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 8933 8934 enum mlxsw_reg_tnumt_tunnel_port { 8935 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 8936 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 8937 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 8938 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 8939 }; 8940 8941 /* reg_tnumt_tunnel_port 8942 * Tunnel port. 8943 * Access: RW 8944 */ 8945 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 8946 8947 /* reg_tnumt_underlay_mc_ptr 8948 * Index to the underlay multicast table. 8949 * For Spectrum the index is to the KVD linear. 8950 * Access: Index 8951 */ 8952 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 8953 8954 /* reg_tnumt_vnext 8955 * The next_underlay_mc_ptr is valid. 8956 * Access: RW 8957 */ 8958 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 8959 8960 /* reg_tnumt_next_underlay_mc_ptr 8961 * The next index to the underlay multicast table. 8962 * Access: RW 8963 */ 8964 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 8965 8966 /* reg_tnumt_record_size 8967 * Number of IP addresses in the record. 8968 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 8969 * Access: RW 8970 */ 8971 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 8972 8973 /* reg_tnumt_udip 8974 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 8975 * Access: RW 8976 */ 8977 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 8978 8979 /* reg_tnumt_udip_ptr 8980 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 8981 * i >= size. The IPv6 addresses are configured by RIPS. 8982 * Access: RW 8983 */ 8984 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 8985 8986 static inline void mlxsw_reg_tnumt_pack(char *payload, 8987 enum mlxsw_reg_tnumt_record_type type, 8988 enum mlxsw_reg_tnumt_tunnel_port tport, 8989 u32 underlay_mc_ptr, bool vnext, 8990 u32 next_underlay_mc_ptr, 8991 u8 record_size) 8992 { 8993 MLXSW_REG_ZERO(tnumt, payload); 8994 mlxsw_reg_tnumt_record_type_set(payload, type); 8995 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 8996 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 8997 mlxsw_reg_tnumt_vnext_set(payload, vnext); 8998 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 8999 mlxsw_reg_tnumt_record_size_set(payload, record_size); 9000 } 9001 9002 /* TNQCR - Tunneling NVE QoS Configuration Register 9003 * ------------------------------------------------ 9004 * The TNQCR register configures how QoS is set in encapsulation into the 9005 * underlay network. 9006 */ 9007 #define MLXSW_REG_TNQCR_ID 0xA010 9008 #define MLXSW_REG_TNQCR_LEN 0x0C 9009 9010 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 9011 9012 /* reg_tnqcr_enc_set_dscp 9013 * For encapsulation: How to set DSCP field: 9014 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 9015 * (outer) IP header. If there is no IP header, use TNQDR.dscp 9016 * 1 - Set the DSCP field as TNQDR.dscp 9017 * Access: RW 9018 */ 9019 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 9020 9021 static inline void mlxsw_reg_tnqcr_pack(char *payload) 9022 { 9023 MLXSW_REG_ZERO(tnqcr, payload); 9024 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 9025 } 9026 9027 /* TNQDR - Tunneling NVE QoS Default Register 9028 * ------------------------------------------ 9029 * The TNQDR register configures the default QoS settings for NVE 9030 * encapsulation. 9031 */ 9032 #define MLXSW_REG_TNQDR_ID 0xA011 9033 #define MLXSW_REG_TNQDR_LEN 0x08 9034 9035 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 9036 9037 /* reg_tnqdr_local_port 9038 * Local port number (receive port). CPU port is supported. 9039 * Access: Index 9040 */ 9041 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 9042 9043 /* reg_tnqdr_dscp 9044 * For encapsulation, the default DSCP. 9045 * Access: RW 9046 */ 9047 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 9048 9049 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 9050 { 9051 MLXSW_REG_ZERO(tnqdr, payload); 9052 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 9053 mlxsw_reg_tnqdr_dscp_set(payload, 0); 9054 } 9055 9056 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 9057 * -------------------------------------------------------- 9058 * The TNEEM register maps ECN of the IP header at the ingress to the 9059 * encapsulation to the ECN of the underlay network. 9060 */ 9061 #define MLXSW_REG_TNEEM_ID 0xA012 9062 #define MLXSW_REG_TNEEM_LEN 0x0C 9063 9064 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 9065 9066 /* reg_tneem_overlay_ecn 9067 * ECN of the IP header in the overlay network. 9068 * Access: Index 9069 */ 9070 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 9071 9072 /* reg_tneem_underlay_ecn 9073 * ECN of the IP header in the underlay network. 9074 * Access: RW 9075 */ 9076 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 9077 9078 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 9079 u8 underlay_ecn) 9080 { 9081 MLXSW_REG_ZERO(tneem, payload); 9082 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 9083 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 9084 } 9085 9086 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 9087 * -------------------------------------------------------- 9088 * The TNDEM register configures the actions that are done in the 9089 * decapsulation. 9090 */ 9091 #define MLXSW_REG_TNDEM_ID 0xA013 9092 #define MLXSW_REG_TNDEM_LEN 0x0C 9093 9094 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 9095 9096 /* reg_tndem_underlay_ecn 9097 * ECN field of the IP header in the underlay network. 9098 * Access: Index 9099 */ 9100 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 9101 9102 /* reg_tndem_overlay_ecn 9103 * ECN field of the IP header in the overlay network. 9104 * Access: Index 9105 */ 9106 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 9107 9108 /* reg_tndem_eip_ecn 9109 * Egress IP ECN. ECN field of the IP header of the packet which goes out 9110 * from the decapsulation. 9111 * Access: RW 9112 */ 9113 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 9114 9115 /* reg_tndem_trap_en 9116 * Trap enable: 9117 * 0 - No trap due to decap ECN 9118 * 1 - Trap enable with trap_id 9119 * Access: RW 9120 */ 9121 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 9122 9123 /* reg_tndem_trap_id 9124 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 9125 * Reserved when trap_en is '0'. 9126 * Access: RW 9127 */ 9128 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 9129 9130 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 9131 u8 overlay_ecn, u8 ecn, bool trap_en, 9132 u16 trap_id) 9133 { 9134 MLXSW_REG_ZERO(tndem, payload); 9135 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 9136 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 9137 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 9138 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 9139 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 9140 } 9141 9142 /* TNPC - Tunnel Port Configuration Register 9143 * ----------------------------------------- 9144 * The TNPC register is used for tunnel port configuration. 9145 * Reserved when Spectrum. 9146 */ 9147 #define MLXSW_REG_TNPC_ID 0xA020 9148 #define MLXSW_REG_TNPC_LEN 0x18 9149 9150 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 9151 9152 enum mlxsw_reg_tnpc_tunnel_port { 9153 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 9154 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 9155 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 9156 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 9157 }; 9158 9159 /* reg_tnpc_tunnel_port 9160 * Tunnel port. 9161 * Access: Index 9162 */ 9163 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 9164 9165 /* reg_tnpc_learn_enable_v6 9166 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 9167 * Access: RW 9168 */ 9169 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 9170 9171 /* reg_tnpc_learn_enable_v4 9172 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 9173 * Access: RW 9174 */ 9175 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 9176 9177 static inline void mlxsw_reg_tnpc_pack(char *payload, 9178 enum mlxsw_reg_tnpc_tunnel_port tport, 9179 bool learn_enable) 9180 { 9181 MLXSW_REG_ZERO(tnpc, payload); 9182 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 9183 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 9184 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 9185 } 9186 9187 /* TIGCR - Tunneling IPinIP General Configuration Register 9188 * ------------------------------------------------------- 9189 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 9190 */ 9191 #define MLXSW_REG_TIGCR_ID 0xA801 9192 #define MLXSW_REG_TIGCR_LEN 0x10 9193 9194 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 9195 9196 /* reg_tigcr_ipip_ttlc 9197 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 9198 * header. 9199 * Access: RW 9200 */ 9201 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 9202 9203 /* reg_tigcr_ipip_ttl_uc 9204 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 9205 * reg_tigcr_ipip_ttlc is unset. 9206 * Access: RW 9207 */ 9208 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 9209 9210 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 9211 { 9212 MLXSW_REG_ZERO(tigcr, payload); 9213 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 9214 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 9215 } 9216 9217 /* SBPR - Shared Buffer Pools Register 9218 * ----------------------------------- 9219 * The SBPR configures and retrieves the shared buffer pools and configuration. 9220 */ 9221 #define MLXSW_REG_SBPR_ID 0xB001 9222 #define MLXSW_REG_SBPR_LEN 0x14 9223 9224 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 9225 9226 /* shared direstion enum for SBPR, SBCM, SBPM */ 9227 enum mlxsw_reg_sbxx_dir { 9228 MLXSW_REG_SBXX_DIR_INGRESS, 9229 MLXSW_REG_SBXX_DIR_EGRESS, 9230 }; 9231 9232 /* reg_sbpr_dir 9233 * Direction. 9234 * Access: Index 9235 */ 9236 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 9237 9238 /* reg_sbpr_pool 9239 * Pool index. 9240 * Access: Index 9241 */ 9242 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 9243 9244 /* reg_sbpr_infi_size 9245 * Size is infinite. 9246 * Access: RW 9247 */ 9248 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 9249 9250 /* reg_sbpr_size 9251 * Pool size in buffer cells. 9252 * Reserved when infi_size = 1. 9253 * Access: RW 9254 */ 9255 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 9256 9257 enum mlxsw_reg_sbpr_mode { 9258 MLXSW_REG_SBPR_MODE_STATIC, 9259 MLXSW_REG_SBPR_MODE_DYNAMIC, 9260 }; 9261 9262 /* reg_sbpr_mode 9263 * Pool quota calculation mode. 9264 * Access: RW 9265 */ 9266 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 9267 9268 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 9269 enum mlxsw_reg_sbxx_dir dir, 9270 enum mlxsw_reg_sbpr_mode mode, u32 size, 9271 bool infi_size) 9272 { 9273 MLXSW_REG_ZERO(sbpr, payload); 9274 mlxsw_reg_sbpr_pool_set(payload, pool); 9275 mlxsw_reg_sbpr_dir_set(payload, dir); 9276 mlxsw_reg_sbpr_mode_set(payload, mode); 9277 mlxsw_reg_sbpr_size_set(payload, size); 9278 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 9279 } 9280 9281 /* SBCM - Shared Buffer Class Management Register 9282 * ---------------------------------------------- 9283 * The SBCM register configures and retrieves the shared buffer allocation 9284 * and configuration according to Port-PG, including the binding to pool 9285 * and definition of the associated quota. 9286 */ 9287 #define MLXSW_REG_SBCM_ID 0xB002 9288 #define MLXSW_REG_SBCM_LEN 0x28 9289 9290 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 9291 9292 /* reg_sbcm_local_port 9293 * Local port number. 9294 * For Ingress: excludes CPU port and Router port 9295 * For Egress: excludes IP Router 9296 * Access: Index 9297 */ 9298 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 9299 9300 /* reg_sbcm_pg_buff 9301 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 9302 * For PG buffer: range is 0..cap_max_pg_buffers - 1 9303 * For traffic class: range is 0..cap_max_tclass - 1 9304 * Note that when traffic class is in MC aware mode then the traffic 9305 * classes which are MC aware cannot be configured. 9306 * Access: Index 9307 */ 9308 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 9309 9310 /* reg_sbcm_dir 9311 * Direction. 9312 * Access: Index 9313 */ 9314 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 9315 9316 /* reg_sbcm_min_buff 9317 * Minimum buffer size for the limiter, in cells. 9318 * Access: RW 9319 */ 9320 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 9321 9322 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 9323 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 9324 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 9325 9326 /* reg_sbcm_infi_max 9327 * Max buffer is infinite. 9328 * Access: RW 9329 */ 9330 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 9331 9332 /* reg_sbcm_max_buff 9333 * When the pool associated to the port-pg/tclass is configured to 9334 * static, Maximum buffer size for the limiter configured in cells. 9335 * When the pool associated to the port-pg/tclass is configured to 9336 * dynamic, the max_buff holds the "alpha" parameter, supporting 9337 * the following values: 9338 * 0: 0 9339 * i: (1/128)*2^(i-1), for i=1..14 9340 * 0xFF: Infinity 9341 * Reserved when infi_max = 1. 9342 * Access: RW 9343 */ 9344 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 9345 9346 /* reg_sbcm_pool 9347 * Association of the port-priority to a pool. 9348 * Access: RW 9349 */ 9350 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 9351 9352 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 9353 enum mlxsw_reg_sbxx_dir dir, 9354 u32 min_buff, u32 max_buff, 9355 bool infi_max, u8 pool) 9356 { 9357 MLXSW_REG_ZERO(sbcm, payload); 9358 mlxsw_reg_sbcm_local_port_set(payload, local_port); 9359 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 9360 mlxsw_reg_sbcm_dir_set(payload, dir); 9361 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 9362 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 9363 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 9364 mlxsw_reg_sbcm_pool_set(payload, pool); 9365 } 9366 9367 /* SBPM - Shared Buffer Port Management Register 9368 * --------------------------------------------- 9369 * The SBPM register configures and retrieves the shared buffer allocation 9370 * and configuration according to Port-Pool, including the definition 9371 * of the associated quota. 9372 */ 9373 #define MLXSW_REG_SBPM_ID 0xB003 9374 #define MLXSW_REG_SBPM_LEN 0x28 9375 9376 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 9377 9378 /* reg_sbpm_local_port 9379 * Local port number. 9380 * For Ingress: excludes CPU port and Router port 9381 * For Egress: excludes IP Router 9382 * Access: Index 9383 */ 9384 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 9385 9386 /* reg_sbpm_pool 9387 * The pool associated to quota counting on the local_port. 9388 * Access: Index 9389 */ 9390 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 9391 9392 /* reg_sbpm_dir 9393 * Direction. 9394 * Access: Index 9395 */ 9396 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 9397 9398 /* reg_sbpm_buff_occupancy 9399 * Current buffer occupancy in cells. 9400 * Access: RO 9401 */ 9402 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 9403 9404 /* reg_sbpm_clr 9405 * Clear Max Buffer Occupancy 9406 * When this bit is set, max_buff_occupancy field is cleared (and a 9407 * new max value is tracked from the time the clear was performed). 9408 * Access: OP 9409 */ 9410 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 9411 9412 /* reg_sbpm_max_buff_occupancy 9413 * Maximum value of buffer occupancy in cells monitored. Cleared by 9414 * writing to the clr field. 9415 * Access: RO 9416 */ 9417 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 9418 9419 /* reg_sbpm_min_buff 9420 * Minimum buffer size for the limiter, in cells. 9421 * Access: RW 9422 */ 9423 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 9424 9425 /* reg_sbpm_max_buff 9426 * When the pool associated to the port-pg/tclass is configured to 9427 * static, Maximum buffer size for the limiter configured in cells. 9428 * When the pool associated to the port-pg/tclass is configured to 9429 * dynamic, the max_buff holds the "alpha" parameter, supporting 9430 * the following values: 9431 * 0: 0 9432 * i: (1/128)*2^(i-1), for i=1..14 9433 * 0xFF: Infinity 9434 * Access: RW 9435 */ 9436 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 9437 9438 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 9439 enum mlxsw_reg_sbxx_dir dir, bool clr, 9440 u32 min_buff, u32 max_buff) 9441 { 9442 MLXSW_REG_ZERO(sbpm, payload); 9443 mlxsw_reg_sbpm_local_port_set(payload, local_port); 9444 mlxsw_reg_sbpm_pool_set(payload, pool); 9445 mlxsw_reg_sbpm_dir_set(payload, dir); 9446 mlxsw_reg_sbpm_clr_set(payload, clr); 9447 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 9448 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 9449 } 9450 9451 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 9452 u32 *p_max_buff_occupancy) 9453 { 9454 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 9455 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 9456 } 9457 9458 /* SBMM - Shared Buffer Multicast Management Register 9459 * -------------------------------------------------- 9460 * The SBMM register configures and retrieves the shared buffer allocation 9461 * and configuration for MC packets according to Switch-Priority, including 9462 * the binding to pool and definition of the associated quota. 9463 */ 9464 #define MLXSW_REG_SBMM_ID 0xB004 9465 #define MLXSW_REG_SBMM_LEN 0x28 9466 9467 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 9468 9469 /* reg_sbmm_prio 9470 * Switch Priority. 9471 * Access: Index 9472 */ 9473 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 9474 9475 /* reg_sbmm_min_buff 9476 * Minimum buffer size for the limiter, in cells. 9477 * Access: RW 9478 */ 9479 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 9480 9481 /* reg_sbmm_max_buff 9482 * When the pool associated to the port-pg/tclass is configured to 9483 * static, Maximum buffer size for the limiter configured in cells. 9484 * When the pool associated to the port-pg/tclass is configured to 9485 * dynamic, the max_buff holds the "alpha" parameter, supporting 9486 * the following values: 9487 * 0: 0 9488 * i: (1/128)*2^(i-1), for i=1..14 9489 * 0xFF: Infinity 9490 * Access: RW 9491 */ 9492 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 9493 9494 /* reg_sbmm_pool 9495 * Association of the port-priority to a pool. 9496 * Access: RW 9497 */ 9498 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 9499 9500 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 9501 u32 max_buff, u8 pool) 9502 { 9503 MLXSW_REG_ZERO(sbmm, payload); 9504 mlxsw_reg_sbmm_prio_set(payload, prio); 9505 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 9506 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 9507 mlxsw_reg_sbmm_pool_set(payload, pool); 9508 } 9509 9510 /* SBSR - Shared Buffer Status Register 9511 * ------------------------------------ 9512 * The SBSR register retrieves the shared buffer occupancy according to 9513 * Port-Pool. Note that this register enables reading a large amount of data. 9514 * It is the user's responsibility to limit the amount of data to ensure the 9515 * response can match the maximum transfer unit. In case the response exceeds 9516 * the maximum transport unit, it will be truncated with no special notice. 9517 */ 9518 #define MLXSW_REG_SBSR_ID 0xB005 9519 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 9520 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 9521 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 9522 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 9523 MLXSW_REG_SBSR_REC_LEN * \ 9524 MLXSW_REG_SBSR_REC_MAX_COUNT) 9525 9526 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 9527 9528 /* reg_sbsr_clr 9529 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 9530 * field is cleared (and a new max value is tracked from the time the clear 9531 * was performed). 9532 * Access: OP 9533 */ 9534 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 9535 9536 /* reg_sbsr_ingress_port_mask 9537 * Bit vector for all ingress network ports. 9538 * Indicates which of the ports (for which the relevant bit is set) 9539 * are affected by the set operation. Configuration of any other port 9540 * does not change. 9541 * Access: Index 9542 */ 9543 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 9544 9545 /* reg_sbsr_pg_buff_mask 9546 * Bit vector for all switch priority groups. 9547 * Indicates which of the priorities (for which the relevant bit is set) 9548 * are affected by the set operation. Configuration of any other priority 9549 * does not change. 9550 * Range is 0..cap_max_pg_buffers - 1 9551 * Access: Index 9552 */ 9553 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 9554 9555 /* reg_sbsr_egress_port_mask 9556 * Bit vector for all egress network ports. 9557 * Indicates which of the ports (for which the relevant bit is set) 9558 * are affected by the set operation. Configuration of any other port 9559 * does not change. 9560 * Access: Index 9561 */ 9562 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 9563 9564 /* reg_sbsr_tclass_mask 9565 * Bit vector for all traffic classes. 9566 * Indicates which of the traffic classes (for which the relevant bit is 9567 * set) are affected by the set operation. Configuration of any other 9568 * traffic class does not change. 9569 * Range is 0..cap_max_tclass - 1 9570 * Access: Index 9571 */ 9572 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 9573 9574 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 9575 { 9576 MLXSW_REG_ZERO(sbsr, payload); 9577 mlxsw_reg_sbsr_clr_set(payload, clr); 9578 } 9579 9580 /* reg_sbsr_rec_buff_occupancy 9581 * Current buffer occupancy in cells. 9582 * Access: RO 9583 */ 9584 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9585 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 9586 9587 /* reg_sbsr_rec_max_buff_occupancy 9588 * Maximum value of buffer occupancy in cells monitored. Cleared by 9589 * writing to the clr field. 9590 * Access: RO 9591 */ 9592 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9593 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 9594 9595 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 9596 u32 *p_buff_occupancy, 9597 u32 *p_max_buff_occupancy) 9598 { 9599 *p_buff_occupancy = 9600 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 9601 *p_max_buff_occupancy = 9602 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 9603 } 9604 9605 /* SBIB - Shared Buffer Internal Buffer Register 9606 * --------------------------------------------- 9607 * The SBIB register configures per port buffers for internal use. The internal 9608 * buffers consume memory on the port buffers (note that the port buffers are 9609 * used also by PBMC). 9610 * 9611 * For Spectrum this is used for egress mirroring. 9612 */ 9613 #define MLXSW_REG_SBIB_ID 0xB006 9614 #define MLXSW_REG_SBIB_LEN 0x10 9615 9616 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 9617 9618 /* reg_sbib_local_port 9619 * Local port number 9620 * Not supported for CPU port and router port 9621 * Access: Index 9622 */ 9623 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 9624 9625 /* reg_sbib_buff_size 9626 * Units represented in cells 9627 * Allowed range is 0 to (cap_max_headroom_size - 1) 9628 * Default is 0 9629 * Access: RW 9630 */ 9631 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 9632 9633 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 9634 u32 buff_size) 9635 { 9636 MLXSW_REG_ZERO(sbib, payload); 9637 mlxsw_reg_sbib_local_port_set(payload, local_port); 9638 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 9639 } 9640 9641 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 9642 MLXSW_REG(sgcr), 9643 MLXSW_REG(spad), 9644 MLXSW_REG(smid), 9645 MLXSW_REG(sspr), 9646 MLXSW_REG(sfdat), 9647 MLXSW_REG(sfd), 9648 MLXSW_REG(sfn), 9649 MLXSW_REG(spms), 9650 MLXSW_REG(spvid), 9651 MLXSW_REG(spvm), 9652 MLXSW_REG(spaft), 9653 MLXSW_REG(sfgc), 9654 MLXSW_REG(sftr), 9655 MLXSW_REG(sfdf), 9656 MLXSW_REG(sldr), 9657 MLXSW_REG(slcr), 9658 MLXSW_REG(slcor), 9659 MLXSW_REG(spmlr), 9660 MLXSW_REG(svfa), 9661 MLXSW_REG(svpe), 9662 MLXSW_REG(sfmr), 9663 MLXSW_REG(spvmlr), 9664 MLXSW_REG(cwtp), 9665 MLXSW_REG(cwtpm), 9666 MLXSW_REG(pgcr), 9667 MLXSW_REG(ppbt), 9668 MLXSW_REG(pacl), 9669 MLXSW_REG(pagt), 9670 MLXSW_REG(ptar), 9671 MLXSW_REG(ppbs), 9672 MLXSW_REG(prcr), 9673 MLXSW_REG(pefa), 9674 MLXSW_REG(pemrbt), 9675 MLXSW_REG(ptce2), 9676 MLXSW_REG(perpt), 9677 MLXSW_REG(peabfe), 9678 MLXSW_REG(perar), 9679 MLXSW_REG(ptce3), 9680 MLXSW_REG(percr), 9681 MLXSW_REG(pererp), 9682 MLXSW_REG(iedr), 9683 MLXSW_REG(qpts), 9684 MLXSW_REG(qpcr), 9685 MLXSW_REG(qtct), 9686 MLXSW_REG(qeec), 9687 MLXSW_REG(qrwe), 9688 MLXSW_REG(qpdsm), 9689 MLXSW_REG(qpdpm), 9690 MLXSW_REG(qtctm), 9691 MLXSW_REG(pmlp), 9692 MLXSW_REG(pmtu), 9693 MLXSW_REG(ptys), 9694 MLXSW_REG(ppad), 9695 MLXSW_REG(paos), 9696 MLXSW_REG(pfcc), 9697 MLXSW_REG(ppcnt), 9698 MLXSW_REG(plib), 9699 MLXSW_REG(pptb), 9700 MLXSW_REG(pbmc), 9701 MLXSW_REG(pspa), 9702 MLXSW_REG(htgt), 9703 MLXSW_REG(hpkt), 9704 MLXSW_REG(rgcr), 9705 MLXSW_REG(ritr), 9706 MLXSW_REG(rtar), 9707 MLXSW_REG(ratr), 9708 MLXSW_REG(rtdp), 9709 MLXSW_REG(rdpm), 9710 MLXSW_REG(ricnt), 9711 MLXSW_REG(rrcr), 9712 MLXSW_REG(ralta), 9713 MLXSW_REG(ralst), 9714 MLXSW_REG(raltb), 9715 MLXSW_REG(ralue), 9716 MLXSW_REG(rauht), 9717 MLXSW_REG(raleu), 9718 MLXSW_REG(rauhtd), 9719 MLXSW_REG(rigr2), 9720 MLXSW_REG(recr2), 9721 MLXSW_REG(rmft2), 9722 MLXSW_REG(mfcr), 9723 MLXSW_REG(mfsc), 9724 MLXSW_REG(mfsm), 9725 MLXSW_REG(mfsl), 9726 MLXSW_REG(mtcap), 9727 MLXSW_REG(mtmp), 9728 MLXSW_REG(mcia), 9729 MLXSW_REG(mpat), 9730 MLXSW_REG(mpar), 9731 MLXSW_REG(mrsr), 9732 MLXSW_REG(mlcr), 9733 MLXSW_REG(mpsc), 9734 MLXSW_REG(mcqi), 9735 MLXSW_REG(mcc), 9736 MLXSW_REG(mcda), 9737 MLXSW_REG(mgpc), 9738 MLXSW_REG(mprs), 9739 MLXSW_REG(tngcr), 9740 MLXSW_REG(tnumt), 9741 MLXSW_REG(tnqcr), 9742 MLXSW_REG(tnqdr), 9743 MLXSW_REG(tneem), 9744 MLXSW_REG(tndem), 9745 MLXSW_REG(tnpc), 9746 MLXSW_REG(tigcr), 9747 MLXSW_REG(sbpr), 9748 MLXSW_REG(sbcm), 9749 MLXSW_REG(sbpm), 9750 MLXSW_REG(sbmm), 9751 MLXSW_REG(sbsr), 9752 MLXSW_REG(sbib), 9753 }; 9754 9755 static inline const char *mlxsw_reg_id_str(u16 reg_id) 9756 { 9757 const struct mlxsw_reg_info *reg_info; 9758 int i; 9759 9760 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 9761 reg_info = mlxsw_reg_infos[i]; 9762 if (reg_info->id == reg_id) 9763 return reg_info->name; 9764 } 9765 return "*UNKNOWN*"; 9766 } 9767 9768 /* PUDE - Port Up / Down Event 9769 * --------------------------- 9770 * Reports the operational state change of a port. 9771 */ 9772 #define MLXSW_REG_PUDE_LEN 0x10 9773 9774 /* reg_pude_swid 9775 * Switch partition ID with which to associate the port. 9776 * Access: Index 9777 */ 9778 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 9779 9780 /* reg_pude_local_port 9781 * Local port number. 9782 * Access: Index 9783 */ 9784 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 9785 9786 /* reg_pude_admin_status 9787 * Port administrative state (the desired state). 9788 * 1 - Up. 9789 * 2 - Down. 9790 * 3 - Up once. This means that in case of link failure, the port won't go 9791 * into polling mode, but will wait to be re-enabled by software. 9792 * 4 - Disabled by system. Can only be set by hardware. 9793 * Access: RO 9794 */ 9795 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 9796 9797 /* reg_pude_oper_status 9798 * Port operatioanl state. 9799 * 1 - Up. 9800 * 2 - Down. 9801 * 3 - Down by port failure. This means that the device will not let the 9802 * port up again until explicitly specified by software. 9803 * Access: RO 9804 */ 9805 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 9806 9807 #endif 9808