1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_fid_vid 326 * Filtering ID or VLAN ID 327 * For SwitchX and SwitchX-2: 328 * - Dynamic entries (policy 2,3) use FID 329 * - Static entries (policy 0) use VID 330 * - When independent learning is configured, VID=FID 331 * For Spectrum: use FID for both Dynamic and Static entries. 332 * VID should not be used. 333 * Access: Index 334 */ 335 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 336 MLXSW_REG_SFD_REC_LEN, 0x08, false); 337 338 /* reg_sfd_uc_system_port 339 * Unique port identifier for the final destination of the packet. 340 * Access: RW 341 */ 342 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 343 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 344 345 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 346 enum mlxsw_reg_sfd_rec_type rec_type, 347 const char *mac, 348 enum mlxsw_reg_sfd_rec_action action) 349 { 350 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 351 352 if (rec_index >= num_rec) 353 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 354 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 355 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 356 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 357 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 358 } 359 360 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 361 enum mlxsw_reg_sfd_rec_policy policy, 362 const char *mac, u16 fid_vid, 363 enum mlxsw_reg_sfd_rec_action action, 364 u16 local_port) 365 { 366 mlxsw_reg_sfd_rec_pack(payload, rec_index, 367 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 368 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 369 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 370 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 371 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 372 } 373 374 /* reg_sfd_uc_lag_sub_port 375 * LAG sub port. 376 * Must be 0 if multichannel VEPA is not enabled. 377 * Access: RW 378 */ 379 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 380 MLXSW_REG_SFD_REC_LEN, 0x08, false); 381 382 /* reg_sfd_uc_lag_fid_vid 383 * Filtering ID or VLAN ID 384 * For SwitchX and SwitchX-2: 385 * - Dynamic entries (policy 2,3) use FID 386 * - Static entries (policy 0) use VID 387 * - When independent learning is configured, VID=FID 388 * For Spectrum: use FID for both Dynamic and Static entries. 389 * VID should not be used. 390 * Access: Index 391 */ 392 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 393 MLXSW_REG_SFD_REC_LEN, 0x08, false); 394 395 /* reg_sfd_uc_lag_lag_vid 396 * Indicates VID in case of vFIDs. Reserved for FIDs. 397 * Access: RW 398 */ 399 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 400 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 401 402 /* reg_sfd_uc_lag_lag_id 403 * LAG Identifier - pointer into the LAG descriptor table. 404 * Access: RW 405 */ 406 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 407 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 408 409 static inline void 410 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 411 enum mlxsw_reg_sfd_rec_policy policy, 412 const char *mac, u16 fid_vid, 413 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 414 u16 lag_id) 415 { 416 mlxsw_reg_sfd_rec_pack(payload, rec_index, 417 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 418 mac, action); 419 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 420 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 421 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 422 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 423 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 424 } 425 426 /* reg_sfd_mc_pgi 427 * 428 * Multicast port group index - index into the port group table. 429 * Value 0x1FFF indicates the pgi should point to the MID entry. 430 * For Spectrum this value must be set to 0x1FFF 431 * Access: RW 432 */ 433 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 434 MLXSW_REG_SFD_REC_LEN, 0x08, false); 435 436 /* reg_sfd_mc_fid_vid 437 * 438 * Filtering ID or VLAN ID 439 * Access: Index 440 */ 441 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 442 MLXSW_REG_SFD_REC_LEN, 0x08, false); 443 444 /* reg_sfd_mc_mid 445 * 446 * Multicast identifier - global identifier that represents the multicast 447 * group across all devices. 448 * Access: RW 449 */ 450 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 451 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 452 453 static inline void 454 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 455 const char *mac, u16 fid_vid, 456 enum mlxsw_reg_sfd_rec_action action, u16 mid) 457 { 458 mlxsw_reg_sfd_rec_pack(payload, rec_index, 459 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 460 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 461 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 462 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 463 } 464 465 /* reg_sfd_uc_tunnel_uip_msb 466 * When protocol is IPv4, the most significant byte of the underlay IPv4 467 * destination IP. 468 * When protocol is IPv6, reserved. 469 * Access: RW 470 */ 471 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 472 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 473 474 /* reg_sfd_uc_tunnel_fid 475 * Filtering ID. 476 * Access: Index 477 */ 478 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 479 MLXSW_REG_SFD_REC_LEN, 0x08, false); 480 481 enum mlxsw_reg_sfd_uc_tunnel_protocol { 482 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 483 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 484 }; 485 486 /* reg_sfd_uc_tunnel_protocol 487 * IP protocol. 488 * Access: RW 489 */ 490 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 491 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 492 493 /* reg_sfd_uc_tunnel_uip_lsb 494 * When protocol is IPv4, the least significant bytes of the underlay 495 * IPv4 destination IP. 496 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 497 * which is configured by RIPS. 498 * Access: RW 499 */ 500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 501 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 502 503 static inline void 504 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 505 enum mlxsw_reg_sfd_rec_policy policy, 506 const char *mac, u16 fid, 507 enum mlxsw_reg_sfd_rec_action action, 508 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 509 { 510 mlxsw_reg_sfd_rec_pack(payload, rec_index, 511 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 512 action); 513 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 514 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 515 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 516 } 517 518 static inline void 519 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 520 enum mlxsw_reg_sfd_rec_policy policy, 521 const char *mac, u16 fid, 522 enum mlxsw_reg_sfd_rec_action action, u32 uip) 523 { 524 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 525 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 526 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 527 action, 528 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 529 } 530 531 static inline void 532 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 533 u16 fid, enum mlxsw_reg_sfd_rec_action action, 534 u32 uip_ptr) 535 { 536 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 537 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 538 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 539 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 540 mac, fid, action, 541 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 542 } 543 544 enum mlxsw_reg_tunnel_port { 545 MLXSW_REG_TUNNEL_PORT_NVE, 546 MLXSW_REG_TUNNEL_PORT_VPLS, 547 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 548 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 549 }; 550 551 /* SFN - Switch FDB Notification Register 552 * ------------------------------------------- 553 * The switch provides notifications on newly learned FDB entries and 554 * aged out entries. The notifications can be polled by software. 555 */ 556 #define MLXSW_REG_SFN_ID 0x200B 557 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 558 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 559 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 560 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 561 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 562 563 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 564 565 /* reg_sfn_swid 566 * Switch partition ID. 567 * Access: Index 568 */ 569 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 570 571 /* reg_sfn_end 572 * Forces the current session to end. 573 * Access: OP 574 */ 575 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 576 577 /* reg_sfn_num_rec 578 * Request: Number of learned notifications and aged-out notification 579 * records requested. 580 * Response: Number of notification records returned (must be smaller 581 * than or equal to the value requested) 582 * Ranges 0..64 583 * Access: OP 584 */ 585 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 586 587 static inline void mlxsw_reg_sfn_pack(char *payload) 588 { 589 MLXSW_REG_ZERO(sfn, payload); 590 mlxsw_reg_sfn_swid_set(payload, 0); 591 mlxsw_reg_sfn_end_set(payload, 0); 592 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 593 } 594 595 /* reg_sfn_rec_swid 596 * Switch partition ID. 597 * Access: RO 598 */ 599 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 600 MLXSW_REG_SFN_REC_LEN, 0x00, false); 601 602 enum mlxsw_reg_sfn_rec_type { 603 /* MAC addresses learned on a regular port. */ 604 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 605 /* MAC addresses learned on a LAG port. */ 606 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 607 /* Aged-out MAC address on a regular port. */ 608 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 609 /* Aged-out MAC address on a LAG port. */ 610 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 611 /* Learned unicast tunnel record. */ 612 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 613 /* Aged-out unicast tunnel record. */ 614 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 615 }; 616 617 /* reg_sfn_rec_type 618 * Notification record type. 619 * Access: RO 620 */ 621 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 622 MLXSW_REG_SFN_REC_LEN, 0x00, false); 623 624 /* reg_sfn_rec_mac 625 * MAC address. 626 * Access: RO 627 */ 628 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 629 MLXSW_REG_SFN_REC_LEN, 0x02); 630 631 /* reg_sfn_mac_sub_port 632 * VEPA channel on the local port. 633 * 0 if multichannel VEPA is not enabled. 634 * Access: RO 635 */ 636 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 637 MLXSW_REG_SFN_REC_LEN, 0x08, false); 638 639 /* reg_sfn_mac_fid 640 * Filtering identifier. 641 * Access: RO 642 */ 643 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 644 MLXSW_REG_SFN_REC_LEN, 0x08, false); 645 646 /* reg_sfn_mac_system_port 647 * Unique port identifier for the final destination of the packet. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 651 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 652 653 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 654 char *mac, u16 *p_vid, 655 u16 *p_local_port) 656 { 657 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 658 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 659 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 660 } 661 662 /* reg_sfn_mac_lag_lag_id 663 * LAG ID (pointer into the LAG descriptor table). 664 * Access: RO 665 */ 666 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 667 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 668 669 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 670 char *mac, u16 *p_vid, 671 u16 *p_lag_id) 672 { 673 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 674 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 675 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 676 } 677 678 /* reg_sfn_uc_tunnel_uip_msb 679 * When protocol is IPv4, the most significant byte of the underlay IPv4 680 * address of the remote VTEP. 681 * When protocol is IPv6, reserved. 682 * Access: RO 683 */ 684 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 685 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 686 687 enum mlxsw_reg_sfn_uc_tunnel_protocol { 688 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 689 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 690 }; 691 692 /* reg_sfn_uc_tunnel_protocol 693 * IP protocol. 694 * Access: RO 695 */ 696 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 697 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 698 699 /* reg_sfn_uc_tunnel_uip_lsb 700 * When protocol is IPv4, the least significant bytes of the underlay 701 * IPv4 address of the remote VTEP. 702 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 703 * Access: RO 704 */ 705 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 706 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 707 708 /* reg_sfn_uc_tunnel_port 709 * Tunnel port. 710 * Reserved on Spectrum. 711 * Access: RO 712 */ 713 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 714 MLXSW_REG_SFN_REC_LEN, 0x10, false); 715 716 static inline void 717 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 718 u16 *p_fid, u32 *p_uip, 719 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 720 { 721 u32 uip_msb, uip_lsb; 722 723 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 724 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 725 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 726 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 727 *p_uip = uip_msb << 24 | uip_lsb; 728 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 729 } 730 731 /* SPMS - Switch Port MSTP/RSTP State Register 732 * ------------------------------------------- 733 * Configures the spanning tree state of a physical port. 734 */ 735 #define MLXSW_REG_SPMS_ID 0x200D 736 #define MLXSW_REG_SPMS_LEN 0x404 737 738 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 739 740 /* reg_spms_local_port 741 * Local port number. 742 * Access: Index 743 */ 744 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 745 746 enum mlxsw_reg_spms_state { 747 MLXSW_REG_SPMS_STATE_NO_CHANGE, 748 MLXSW_REG_SPMS_STATE_DISCARDING, 749 MLXSW_REG_SPMS_STATE_LEARNING, 750 MLXSW_REG_SPMS_STATE_FORWARDING, 751 }; 752 753 /* reg_spms_state 754 * Spanning tree state of each VLAN ID (VID) of the local port. 755 * 0 - Do not change spanning tree state (used only when writing). 756 * 1 - Discarding. No learning or forwarding to/from this port (default). 757 * 2 - Learning. Port is learning, but not forwarding. 758 * 3 - Forwarding. Port is learning and forwarding. 759 * Access: RW 760 */ 761 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 762 763 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 764 { 765 MLXSW_REG_ZERO(spms, payload); 766 mlxsw_reg_spms_local_port_set(payload, local_port); 767 } 768 769 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 770 enum mlxsw_reg_spms_state state) 771 { 772 mlxsw_reg_spms_state_set(payload, vid, state); 773 } 774 775 /* SPVID - Switch Port VID 776 * ----------------------- 777 * The switch port VID configures the default VID for a port. 778 */ 779 #define MLXSW_REG_SPVID_ID 0x200E 780 #define MLXSW_REG_SPVID_LEN 0x08 781 782 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 783 784 /* reg_spvid_tport 785 * Port is tunnel port. 786 * Reserved when SwitchX/-2 or Spectrum-1. 787 * Access: Index 788 */ 789 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 790 791 /* reg_spvid_local_port 792 * When tport = 0: Local port number. Not supported for CPU port. 793 * When tport = 1: Tunnel port. 794 * Access: Index 795 */ 796 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 797 798 /* reg_spvid_sub_port 799 * Virtual port within the physical port. 800 * Should be set to 0 when virtual ports are not enabled on the port. 801 * Access: Index 802 */ 803 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 804 805 /* reg_spvid_egr_et_set 806 * When VLAN is pushed at ingress (for untagged packets or for 807 * QinQ push mode) then the EtherType is decided at the egress port. 808 * Reserved when Spectrum-1. 809 * Access: RW 810 */ 811 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 812 813 /* reg_spvid_et_vlan 814 * EtherType used for when VLAN is pushed at ingress (for untagged 815 * packets or for QinQ push mode). 816 * 0: ether_type0 - (default) 817 * 1: ether_type1 818 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 819 * Ethertype IDs are configured by SVER. 820 * Reserved when egr_et_set = 1. 821 * Access: RW 822 */ 823 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 824 825 /* reg_spvid_pvid 826 * Port default VID 827 * Access: RW 828 */ 829 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 830 831 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 832 u8 et_vlan) 833 { 834 MLXSW_REG_ZERO(spvid, payload); 835 mlxsw_reg_spvid_local_port_set(payload, local_port); 836 mlxsw_reg_spvid_pvid_set(payload, pvid); 837 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 838 } 839 840 /* SPVM - Switch Port VLAN Membership 841 * ---------------------------------- 842 * The Switch Port VLAN Membership register configures the VLAN membership 843 * of a port in a VLAN denoted by VID. VLAN membership is managed per 844 * virtual port. The register can be used to add and remove VID(s) from a port. 845 */ 846 #define MLXSW_REG_SPVM_ID 0x200F 847 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 848 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 849 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 850 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 851 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 852 853 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 854 855 /* reg_spvm_pt 856 * Priority tagged. If this bit is set, packets forwarded to the port with 857 * untagged VLAN membership (u bit is set) will be tagged with priority tag 858 * (VID=0) 859 * Access: RW 860 */ 861 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 862 863 /* reg_spvm_pte 864 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 865 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 866 * Access: WO 867 */ 868 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 869 870 /* reg_spvm_local_port 871 * Local port number. 872 * Access: Index 873 */ 874 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 875 876 /* reg_spvm_sub_port 877 * Virtual port within the physical port. 878 * Should be set to 0 when virtual ports are not enabled on the port. 879 * Access: Index 880 */ 881 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 882 883 /* reg_spvm_num_rec 884 * Number of records to update. Each record contains: i, e, u, vid. 885 * Access: OP 886 */ 887 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 888 889 /* reg_spvm_rec_i 890 * Ingress membership in VLAN ID. 891 * Access: Index 892 */ 893 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 894 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 895 MLXSW_REG_SPVM_REC_LEN, 0, false); 896 897 /* reg_spvm_rec_e 898 * Egress membership in VLAN ID. 899 * Access: Index 900 */ 901 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 902 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 903 MLXSW_REG_SPVM_REC_LEN, 0, false); 904 905 /* reg_spvm_rec_u 906 * Untagged - port is an untagged member - egress transmission uses untagged 907 * frames on VID<n> 908 * Access: Index 909 */ 910 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 911 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 912 MLXSW_REG_SPVM_REC_LEN, 0, false); 913 914 /* reg_spvm_rec_vid 915 * Egress membership in VLAN ID. 916 * Access: Index 917 */ 918 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 919 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 920 MLXSW_REG_SPVM_REC_LEN, 0, false); 921 922 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 923 u16 vid_begin, u16 vid_end, 924 bool is_member, bool untagged) 925 { 926 int size = vid_end - vid_begin + 1; 927 int i; 928 929 MLXSW_REG_ZERO(spvm, payload); 930 mlxsw_reg_spvm_local_port_set(payload, local_port); 931 mlxsw_reg_spvm_num_rec_set(payload, size); 932 933 for (i = 0; i < size; i++) { 934 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 935 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 936 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 937 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 938 } 939 } 940 941 /* SPAFT - Switch Port Acceptable Frame Types 942 * ------------------------------------------ 943 * The Switch Port Acceptable Frame Types register configures the frame 944 * admittance of the port. 945 */ 946 #define MLXSW_REG_SPAFT_ID 0x2010 947 #define MLXSW_REG_SPAFT_LEN 0x08 948 949 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 950 951 /* reg_spaft_local_port 952 * Local port number. 953 * Access: Index 954 * 955 * Note: CPU port is not supported (all tag types are allowed). 956 */ 957 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 958 959 /* reg_spaft_sub_port 960 * Virtual port within the physical port. 961 * Should be set to 0 when virtual ports are not enabled on the port. 962 * Access: RW 963 */ 964 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 965 966 /* reg_spaft_allow_untagged 967 * When set, untagged frames on the ingress are allowed (default). 968 * Access: RW 969 */ 970 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 971 972 /* reg_spaft_allow_prio_tagged 973 * When set, priority tagged frames on the ingress are allowed (default). 974 * Access: RW 975 */ 976 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 977 978 /* reg_spaft_allow_tagged 979 * When set, tagged frames on the ingress are allowed (default). 980 * Access: RW 981 */ 982 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 983 984 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 985 bool allow_untagged) 986 { 987 MLXSW_REG_ZERO(spaft, payload); 988 mlxsw_reg_spaft_local_port_set(payload, local_port); 989 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 990 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 991 mlxsw_reg_spaft_allow_tagged_set(payload, true); 992 } 993 994 /* SFGC - Switch Flooding Group Configuration 995 * ------------------------------------------ 996 * The following register controls the association of flooding tables and MIDs 997 * to packet types used for flooding. 998 */ 999 #define MLXSW_REG_SFGC_ID 0x2011 1000 #define MLXSW_REG_SFGC_LEN 0x10 1001 1002 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1003 1004 enum mlxsw_reg_sfgc_type { 1005 MLXSW_REG_SFGC_TYPE_BROADCAST, 1006 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1007 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1008 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1009 MLXSW_REG_SFGC_TYPE_RESERVED, 1010 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1011 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1012 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1013 MLXSW_REG_SFGC_TYPE_MAX, 1014 }; 1015 1016 /* reg_sfgc_type 1017 * The traffic type to reach the flooding table. 1018 * Access: Index 1019 */ 1020 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1021 1022 enum mlxsw_reg_sfgc_bridge_type { 1023 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1024 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1025 }; 1026 1027 /* reg_sfgc_bridge_type 1028 * Access: Index 1029 * 1030 * Note: SwitchX-2 only supports 802.1Q mode. 1031 */ 1032 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1033 1034 enum mlxsw_flood_table_type { 1035 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1036 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1037 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1038 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1039 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1040 }; 1041 1042 /* reg_sfgc_table_type 1043 * See mlxsw_flood_table_type 1044 * Access: RW 1045 * 1046 * Note: FID offset and FID types are not supported in SwitchX-2. 1047 */ 1048 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1049 1050 /* reg_sfgc_flood_table 1051 * Flooding table index to associate with the specific type on the specific 1052 * switch partition. 1053 * Access: RW 1054 */ 1055 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1056 1057 /* reg_sfgc_mid 1058 * The multicast ID for the swid. Not supported for Spectrum 1059 * Access: RW 1060 */ 1061 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1062 1063 /* reg_sfgc_counter_set_type 1064 * Counter Set Type for flow counters. 1065 * Access: RW 1066 */ 1067 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1068 1069 /* reg_sfgc_counter_index 1070 * Counter Index for flow counters. 1071 * Access: RW 1072 */ 1073 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1074 1075 static inline void 1076 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1077 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1078 enum mlxsw_flood_table_type table_type, 1079 unsigned int flood_table) 1080 { 1081 MLXSW_REG_ZERO(sfgc, payload); 1082 mlxsw_reg_sfgc_type_set(payload, type); 1083 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1084 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1085 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1086 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1087 } 1088 1089 /* SFDF - Switch Filtering DB Flush 1090 * -------------------------------- 1091 * The switch filtering DB flush register is used to flush the FDB. 1092 * Note that FDB notifications are flushed as well. 1093 */ 1094 #define MLXSW_REG_SFDF_ID 0x2013 1095 #define MLXSW_REG_SFDF_LEN 0x14 1096 1097 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1098 1099 /* reg_sfdf_swid 1100 * Switch partition ID. 1101 * Access: Index 1102 */ 1103 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1104 1105 enum mlxsw_reg_sfdf_flush_type { 1106 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1107 MLXSW_REG_SFDF_FLUSH_PER_FID, 1108 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1109 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1110 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1111 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1112 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1113 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1114 }; 1115 1116 /* reg_sfdf_flush_type 1117 * Flush type. 1118 * 0 - All SWID dynamic entries are flushed. 1119 * 1 - All FID dynamic entries are flushed. 1120 * 2 - All dynamic entries pointing to port are flushed. 1121 * 3 - All FID dynamic entries pointing to port are flushed. 1122 * 4 - All dynamic entries pointing to LAG are flushed. 1123 * 5 - All FID dynamic entries pointing to LAG are flushed. 1124 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1125 * flushed. 1126 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1127 * flushed, per FID. 1128 * Access: RW 1129 */ 1130 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1131 1132 /* reg_sfdf_flush_static 1133 * Static. 1134 * 0 - Flush only dynamic entries. 1135 * 1 - Flush both dynamic and static entries. 1136 * Access: RW 1137 */ 1138 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1139 1140 static inline void mlxsw_reg_sfdf_pack(char *payload, 1141 enum mlxsw_reg_sfdf_flush_type type) 1142 { 1143 MLXSW_REG_ZERO(sfdf, payload); 1144 mlxsw_reg_sfdf_flush_type_set(payload, type); 1145 mlxsw_reg_sfdf_flush_static_set(payload, true); 1146 } 1147 1148 /* reg_sfdf_fid 1149 * FID to flush. 1150 * Access: RW 1151 */ 1152 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1153 1154 /* reg_sfdf_system_port 1155 * Port to flush. 1156 * Access: RW 1157 */ 1158 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1159 1160 /* reg_sfdf_port_fid_system_port 1161 * Port to flush, pointed to by FID. 1162 * Access: RW 1163 */ 1164 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1165 1166 /* reg_sfdf_lag_id 1167 * LAG ID to flush. 1168 * Access: RW 1169 */ 1170 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1171 1172 /* reg_sfdf_lag_fid_lag_id 1173 * LAG ID to flush, pointed to by FID. 1174 * Access: RW 1175 */ 1176 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1177 1178 /* SLDR - Switch LAG Descriptor Register 1179 * ----------------------------------------- 1180 * The switch LAG descriptor register is populated by LAG descriptors. 1181 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1182 * max_lag-1. 1183 */ 1184 #define MLXSW_REG_SLDR_ID 0x2014 1185 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1186 1187 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1188 1189 enum mlxsw_reg_sldr_op { 1190 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1191 MLXSW_REG_SLDR_OP_LAG_CREATE, 1192 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1193 /* Ports that appear in the list have the Distributor enabled */ 1194 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1195 /* Removes ports from the disributor list */ 1196 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1197 }; 1198 1199 /* reg_sldr_op 1200 * Operation. 1201 * Access: RW 1202 */ 1203 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1204 1205 /* reg_sldr_lag_id 1206 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1207 * Access: Index 1208 */ 1209 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1210 1211 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1212 { 1213 MLXSW_REG_ZERO(sldr, payload); 1214 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1215 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1216 } 1217 1218 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1219 { 1220 MLXSW_REG_ZERO(sldr, payload); 1221 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1222 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1223 } 1224 1225 /* reg_sldr_num_ports 1226 * The number of member ports of the LAG. 1227 * Reserved for Create / Destroy operations 1228 * For Add / Remove operations - indicates the number of ports in the list. 1229 * Access: RW 1230 */ 1231 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1232 1233 /* reg_sldr_system_port 1234 * System port. 1235 * Access: RW 1236 */ 1237 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1238 1239 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1240 u16 local_port) 1241 { 1242 MLXSW_REG_ZERO(sldr, payload); 1243 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1244 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1245 mlxsw_reg_sldr_num_ports_set(payload, 1); 1246 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1247 } 1248 1249 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1250 u16 local_port) 1251 { 1252 MLXSW_REG_ZERO(sldr, payload); 1253 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1254 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1255 mlxsw_reg_sldr_num_ports_set(payload, 1); 1256 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1257 } 1258 1259 /* SLCR - Switch LAG Configuration 2 Register 1260 * ------------------------------------------- 1261 * The Switch LAG Configuration register is used for configuring the 1262 * LAG properties of the switch. 1263 */ 1264 #define MLXSW_REG_SLCR_ID 0x2015 1265 #define MLXSW_REG_SLCR_LEN 0x10 1266 1267 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1268 1269 enum mlxsw_reg_slcr_pp { 1270 /* Global Configuration (for all ports) */ 1271 MLXSW_REG_SLCR_PP_GLOBAL, 1272 /* Per port configuration, based on local_port field */ 1273 MLXSW_REG_SLCR_PP_PER_PORT, 1274 }; 1275 1276 /* reg_slcr_pp 1277 * Per Port Configuration 1278 * Note: Reading at Global mode results in reading port 1 configuration. 1279 * Access: Index 1280 */ 1281 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1282 1283 /* reg_slcr_local_port 1284 * Local port number 1285 * Supported from CPU port 1286 * Not supported from router port 1287 * Reserved when pp = Global Configuration 1288 * Access: Index 1289 */ 1290 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1291 1292 enum mlxsw_reg_slcr_type { 1293 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1294 MLXSW_REG_SLCR_TYPE_XOR, 1295 MLXSW_REG_SLCR_TYPE_RANDOM, 1296 }; 1297 1298 /* reg_slcr_type 1299 * Hash type 1300 * Access: RW 1301 */ 1302 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1303 1304 /* Ingress port */ 1305 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1306 /* SMAC - for IPv4 and IPv6 packets */ 1307 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1308 /* SMAC - for non-IP packets */ 1309 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1310 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1311 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1312 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1313 /* DMAC - for IPv4 and IPv6 packets */ 1314 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1315 /* DMAC - for non-IP packets */ 1316 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1317 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1318 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1319 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1320 /* Ethertype - for IPv4 and IPv6 packets */ 1321 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1322 /* Ethertype - for non-IP packets */ 1323 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1324 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1325 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1326 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1327 /* VLAN ID - for IPv4 and IPv6 packets */ 1328 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1329 /* VLAN ID - for non-IP packets */ 1330 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1331 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1332 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1333 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1334 /* Source IP address (can be IPv4 or IPv6) */ 1335 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1336 /* Destination IP address (can be IPv4 or IPv6) */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1338 /* TCP/UDP source port */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1340 /* TCP/UDP destination port*/ 1341 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1342 /* IPv4 Protocol/IPv6 Next Header */ 1343 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1344 /* IPv6 Flow label */ 1345 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1346 /* SID - FCoE source ID */ 1347 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1348 /* DID - FCoE destination ID */ 1349 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1350 /* OXID - FCoE originator exchange ID */ 1351 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1352 /* Destination QP number - for RoCE packets */ 1353 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1354 1355 /* reg_slcr_lag_hash 1356 * LAG hashing configuration. This is a bitmask, in which each set 1357 * bit includes the corresponding item in the LAG hash calculation. 1358 * The default lag_hash contains SMAC, DMAC, VLANID and 1359 * Ethertype (for all packet types). 1360 * Access: RW 1361 */ 1362 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1363 1364 /* reg_slcr_seed 1365 * LAG seed value. The seed is the same for all ports. 1366 * Access: RW 1367 */ 1368 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1369 1370 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1371 { 1372 MLXSW_REG_ZERO(slcr, payload); 1373 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1374 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1375 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1376 mlxsw_reg_slcr_seed_set(payload, seed); 1377 } 1378 1379 /* SLCOR - Switch LAG Collector Register 1380 * ------------------------------------- 1381 * The Switch LAG Collector register controls the Local Port membership 1382 * in a LAG and enablement of the collector. 1383 */ 1384 #define MLXSW_REG_SLCOR_ID 0x2016 1385 #define MLXSW_REG_SLCOR_LEN 0x10 1386 1387 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1388 1389 enum mlxsw_reg_slcor_col { 1390 /* Port is added with collector disabled */ 1391 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1392 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1393 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1394 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1395 }; 1396 1397 /* reg_slcor_col 1398 * Collector configuration 1399 * Access: RW 1400 */ 1401 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1402 1403 /* reg_slcor_local_port 1404 * Local port number 1405 * Not supported for CPU port 1406 * Access: Index 1407 */ 1408 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1409 1410 /* reg_slcor_lag_id 1411 * LAG Identifier. Index into the LAG descriptor table. 1412 * Access: Index 1413 */ 1414 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1415 1416 /* reg_slcor_port_index 1417 * Port index in the LAG list. Only valid on Add Port to LAG col. 1418 * Valid range is from 0 to cap_max_lag_members-1 1419 * Access: RW 1420 */ 1421 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1422 1423 static inline void mlxsw_reg_slcor_pack(char *payload, 1424 u16 local_port, u16 lag_id, 1425 enum mlxsw_reg_slcor_col col) 1426 { 1427 MLXSW_REG_ZERO(slcor, payload); 1428 mlxsw_reg_slcor_col_set(payload, col); 1429 mlxsw_reg_slcor_local_port_set(payload, local_port); 1430 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1431 } 1432 1433 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1434 u16 local_port, u16 lag_id, 1435 u8 port_index) 1436 { 1437 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1438 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1439 mlxsw_reg_slcor_port_index_set(payload, port_index); 1440 } 1441 1442 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1443 u16 local_port, u16 lag_id) 1444 { 1445 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1446 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1447 } 1448 1449 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1450 u16 local_port, u16 lag_id) 1451 { 1452 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1453 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1454 } 1455 1456 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1457 u16 local_port, u16 lag_id) 1458 { 1459 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1460 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1461 } 1462 1463 /* SPMLR - Switch Port MAC Learning Register 1464 * ----------------------------------------- 1465 * Controls the Switch MAC learning policy per port. 1466 */ 1467 #define MLXSW_REG_SPMLR_ID 0x2018 1468 #define MLXSW_REG_SPMLR_LEN 0x8 1469 1470 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1471 1472 /* reg_spmlr_local_port 1473 * Local port number. 1474 * Access: Index 1475 */ 1476 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1477 1478 /* reg_spmlr_sub_port 1479 * Virtual port within the physical port. 1480 * Should be set to 0 when virtual ports are not enabled on the port. 1481 * Access: Index 1482 */ 1483 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1484 1485 enum mlxsw_reg_spmlr_learn_mode { 1486 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1487 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1488 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1489 }; 1490 1491 /* reg_spmlr_learn_mode 1492 * Learning mode on the port. 1493 * 0 - Learning disabled. 1494 * 2 - Learning enabled. 1495 * 3 - Security mode. 1496 * 1497 * In security mode the switch does not learn MACs on the port, but uses the 1498 * SMAC to see if it exists on another ingress port. If so, the packet is 1499 * classified as a bad packet and is discarded unless the software registers 1500 * to receive port security error packets usign HPKT. 1501 */ 1502 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1503 1504 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1505 enum mlxsw_reg_spmlr_learn_mode mode) 1506 { 1507 MLXSW_REG_ZERO(spmlr, payload); 1508 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1509 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1510 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1511 } 1512 1513 /* SVFA - Switch VID to FID Allocation Register 1514 * -------------------------------------------- 1515 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1516 * virtualized ports. 1517 */ 1518 #define MLXSW_REG_SVFA_ID 0x201C 1519 #define MLXSW_REG_SVFA_LEN 0x10 1520 1521 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1522 1523 /* reg_svfa_swid 1524 * Switch partition ID. 1525 * Access: Index 1526 */ 1527 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1528 1529 /* reg_svfa_local_port 1530 * Local port number. 1531 * Access: Index 1532 * 1533 * Note: Reserved for 802.1Q FIDs. 1534 */ 1535 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1536 1537 enum mlxsw_reg_svfa_mt { 1538 MLXSW_REG_SVFA_MT_VID_TO_FID, 1539 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1540 }; 1541 1542 /* reg_svfa_mapping_table 1543 * Mapping table: 1544 * 0 - VID to FID 1545 * 1 - {Port, VID} to FID 1546 * Access: Index 1547 * 1548 * Note: Reserved for SwitchX-2. 1549 */ 1550 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1551 1552 /* reg_svfa_v 1553 * Valid. 1554 * Valid if set. 1555 * Access: RW 1556 * 1557 * Note: Reserved for SwitchX-2. 1558 */ 1559 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1560 1561 /* reg_svfa_fid 1562 * Filtering ID. 1563 * Access: RW 1564 */ 1565 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1566 1567 /* reg_svfa_vid 1568 * VLAN ID. 1569 * Access: Index 1570 */ 1571 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1572 1573 /* reg_svfa_counter_set_type 1574 * Counter set type for flow counters. 1575 * Access: RW 1576 * 1577 * Note: Reserved for SwitchX-2. 1578 */ 1579 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1580 1581 /* reg_svfa_counter_index 1582 * Counter index for flow counters. 1583 * Access: RW 1584 * 1585 * Note: Reserved for SwitchX-2. 1586 */ 1587 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1588 1589 static inline void mlxsw_reg_svfa_pack(char *payload, u16 local_port, 1590 enum mlxsw_reg_svfa_mt mt, bool valid, 1591 u16 fid, u16 vid) 1592 { 1593 MLXSW_REG_ZERO(svfa, payload); 1594 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1595 mlxsw_reg_svfa_swid_set(payload, 0); 1596 mlxsw_reg_svfa_local_port_set(payload, local_port); 1597 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1598 mlxsw_reg_svfa_v_set(payload, valid); 1599 mlxsw_reg_svfa_fid_set(payload, fid); 1600 mlxsw_reg_svfa_vid_set(payload, vid); 1601 } 1602 1603 /* SPVTR - Switch Port VLAN Stacking Register 1604 * ------------------------------------------ 1605 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1606 * to enable VLAN stacking. 1607 */ 1608 #define MLXSW_REG_SPVTR_ID 0x201D 1609 #define MLXSW_REG_SPVTR_LEN 0x10 1610 1611 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1612 1613 /* reg_spvtr_tport 1614 * Port is tunnel port. 1615 * Access: Index 1616 * 1617 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1618 */ 1619 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1620 1621 /* reg_spvtr_local_port 1622 * When tport = 0: local port number (Not supported from/to CPU). 1623 * When tport = 1: tunnel port. 1624 * Access: Index 1625 */ 1626 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1627 1628 /* reg_spvtr_ippe 1629 * Ingress Port Prio Mode Update Enable. 1630 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1631 * Reserved on Get operations. 1632 * Access: OP 1633 */ 1634 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1635 1636 /* reg_spvtr_ipve 1637 * Ingress Port VID Mode Update Enable. 1638 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1639 * field. 1640 * Reserved on Get operations. 1641 * Access: OP 1642 */ 1643 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1644 1645 /* reg_spvtr_epve 1646 * Egress Port VID Mode Update Enable. 1647 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1648 * field. 1649 * Access: OP 1650 */ 1651 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1652 1653 /* reg_spvtr_ipprio_mode 1654 * Ingress Port Priority Mode. 1655 * This controls the PCP and DEI of the new outer VLAN 1656 * Note: for SwitchX/-2 the DEI is not affected. 1657 * 0: use port default PCP and DEI (configured by QPDPC). 1658 * 1: use C-VLAN PCP and DEI. 1659 * Has no effect when ipvid_mode = 0. 1660 * Reserved when tport = 1. 1661 * Access: RW 1662 */ 1663 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1664 1665 enum mlxsw_reg_spvtr_ipvid_mode { 1666 /* IEEE Compliant PVID (default) */ 1667 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1668 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1669 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1670 /* Always push VLAN (also for prio tagged packets) */ 1671 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1672 }; 1673 1674 /* reg_spvtr_ipvid_mode 1675 * Ingress Port VLAN-ID Mode. 1676 * For Spectrum family, this affects the values of SPVM.i 1677 * Access: RW 1678 */ 1679 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1680 1681 enum mlxsw_reg_spvtr_epvid_mode { 1682 /* IEEE Compliant VLAN membership */ 1683 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1684 /* Pop VLAN (for VLAN stacking) */ 1685 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1686 }; 1687 1688 /* reg_spvtr_epvid_mode 1689 * Egress Port VLAN-ID Mode. 1690 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1691 * Access: WO 1692 */ 1693 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1694 1695 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1696 u16 local_port, 1697 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1698 { 1699 MLXSW_REG_ZERO(spvtr, payload); 1700 mlxsw_reg_spvtr_tport_set(payload, tport); 1701 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1702 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1703 mlxsw_reg_spvtr_ipve_set(payload, true); 1704 } 1705 1706 /* SVPE - Switch Virtual-Port Enabling Register 1707 * -------------------------------------------- 1708 * Enables port virtualization. 1709 */ 1710 #define MLXSW_REG_SVPE_ID 0x201E 1711 #define MLXSW_REG_SVPE_LEN 0x4 1712 1713 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1714 1715 /* reg_svpe_local_port 1716 * Local port number 1717 * Access: Index 1718 * 1719 * Note: CPU port is not supported (uses VLAN mode only). 1720 */ 1721 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1722 1723 /* reg_svpe_vp_en 1724 * Virtual port enable. 1725 * 0 - Disable, VLAN mode (VID to FID). 1726 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1727 * Access: RW 1728 */ 1729 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1730 1731 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1732 bool enable) 1733 { 1734 MLXSW_REG_ZERO(svpe, payload); 1735 mlxsw_reg_svpe_local_port_set(payload, local_port); 1736 mlxsw_reg_svpe_vp_en_set(payload, enable); 1737 } 1738 1739 /* SFMR - Switch FID Management Register 1740 * ------------------------------------- 1741 * Creates and configures FIDs. 1742 */ 1743 #define MLXSW_REG_SFMR_ID 0x201F 1744 #define MLXSW_REG_SFMR_LEN 0x18 1745 1746 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1747 1748 enum mlxsw_reg_sfmr_op { 1749 MLXSW_REG_SFMR_OP_CREATE_FID, 1750 MLXSW_REG_SFMR_OP_DESTROY_FID, 1751 }; 1752 1753 /* reg_sfmr_op 1754 * Operation. 1755 * 0 - Create or edit FID. 1756 * 1 - Destroy FID. 1757 * Access: WO 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1760 1761 /* reg_sfmr_fid 1762 * Filtering ID. 1763 * Access: Index 1764 */ 1765 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1766 1767 /* reg_sfmr_fid_offset 1768 * FID offset. 1769 * Used to point into the flooding table selected by SFGC register if 1770 * the table is of type FID-Offset. Otherwise, this field is reserved. 1771 * Access: RW 1772 */ 1773 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1774 1775 /* reg_sfmr_vtfp 1776 * Valid Tunnel Flood Pointer. 1777 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1778 * Access: RW 1779 * 1780 * Note: Reserved for 802.1Q FIDs. 1781 */ 1782 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1783 1784 /* reg_sfmr_nve_tunnel_flood_ptr 1785 * Underlay Flooding and BC Pointer. 1786 * Used as a pointer to the first entry of the group based link lists of 1787 * flooding or BC entries (for NVE tunnels). 1788 * Access: RW 1789 */ 1790 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1791 1792 /* reg_sfmr_vv 1793 * VNI Valid. 1794 * If not set, then vni is reserved. 1795 * Access: RW 1796 * 1797 * Note: Reserved for 802.1Q FIDs. 1798 */ 1799 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1800 1801 /* reg_sfmr_vni 1802 * Virtual Network Identifier. 1803 * Access: RW 1804 * 1805 * Note: A given VNI can only be assigned to one FID. 1806 */ 1807 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1808 1809 static inline void mlxsw_reg_sfmr_pack(char *payload, 1810 enum mlxsw_reg_sfmr_op op, u16 fid, 1811 u16 fid_offset) 1812 { 1813 MLXSW_REG_ZERO(sfmr, payload); 1814 mlxsw_reg_sfmr_op_set(payload, op); 1815 mlxsw_reg_sfmr_fid_set(payload, fid); 1816 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1817 mlxsw_reg_sfmr_vtfp_set(payload, false); 1818 mlxsw_reg_sfmr_vv_set(payload, false); 1819 } 1820 1821 /* SPVMLR - Switch Port VLAN MAC Learning Register 1822 * ----------------------------------------------- 1823 * Controls the switch MAC learning policy per {Port, VID}. 1824 */ 1825 #define MLXSW_REG_SPVMLR_ID 0x2020 1826 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1827 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1828 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1829 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1830 MLXSW_REG_SPVMLR_REC_LEN * \ 1831 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1832 1833 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1834 1835 /* reg_spvmlr_local_port 1836 * Local ingress port. 1837 * Access: Index 1838 * 1839 * Note: CPU port is not supported. 1840 */ 1841 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 1842 1843 /* reg_spvmlr_num_rec 1844 * Number of records to update. 1845 * Access: OP 1846 */ 1847 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1848 1849 /* reg_spvmlr_rec_learn_enable 1850 * 0 - Disable learning for {Port, VID}. 1851 * 1 - Enable learning for {Port, VID}. 1852 * Access: RW 1853 */ 1854 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1855 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1856 1857 /* reg_spvmlr_rec_vid 1858 * VLAN ID to be added/removed from port or for querying. 1859 * Access: Index 1860 */ 1861 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1862 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1863 1864 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 1865 u16 vid_begin, u16 vid_end, 1866 bool learn_enable) 1867 { 1868 int num_rec = vid_end - vid_begin + 1; 1869 int i; 1870 1871 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1872 1873 MLXSW_REG_ZERO(spvmlr, payload); 1874 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1875 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1876 1877 for (i = 0; i < num_rec; i++) { 1878 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1879 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1880 } 1881 } 1882 1883 /* SPVC - Switch Port VLAN Classification Register 1884 * ----------------------------------------------- 1885 * Configures the port to identify packets as untagged / single tagged / 1886 * double packets based on the packet EtherTypes. 1887 * Ethertype IDs are configured by SVER. 1888 */ 1889 #define MLXSW_REG_SPVC_ID 0x2026 1890 #define MLXSW_REG_SPVC_LEN 0x0C 1891 1892 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 1893 1894 /* reg_spvc_local_port 1895 * Local port. 1896 * Access: Index 1897 * 1898 * Note: applies both to Rx port and Tx port, so if a packet traverses 1899 * through Rx port i and a Tx port j then port i and port j must have the 1900 * same configuration. 1901 */ 1902 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 1903 1904 /* reg_spvc_inner_et2 1905 * Vlan Tag1 EtherType2 enable. 1906 * Packet is initially classified as double VLAN Tag if in addition to 1907 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 1908 * equal to ether_type2. 1909 * 0: disable (default) 1910 * 1: enable 1911 * Access: RW 1912 */ 1913 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 1914 1915 /* reg_spvc_et2 1916 * Vlan Tag0 EtherType2 enable. 1917 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 1918 * equal to ether_type2. 1919 * 0: disable (default) 1920 * 1: enable 1921 * Access: RW 1922 */ 1923 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 1924 1925 /* reg_spvc_inner_et1 1926 * Vlan Tag1 EtherType1 enable. 1927 * Packet is initially classified as double VLAN Tag if in addition to 1928 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 1929 * equal to ether_type1. 1930 * 0: disable 1931 * 1: enable (default) 1932 * Access: RW 1933 */ 1934 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 1935 1936 /* reg_spvc_et1 1937 * Vlan Tag0 EtherType1 enable. 1938 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 1939 * equal to ether_type1. 1940 * 0: disable 1941 * 1: enable (default) 1942 * Access: RW 1943 */ 1944 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 1945 1946 /* reg_inner_et0 1947 * Vlan Tag1 EtherType0 enable. 1948 * Packet is initially classified as double VLAN Tag if in addition to 1949 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 1950 * equal to ether_type0. 1951 * 0: disable 1952 * 1: enable (default) 1953 * Access: RW 1954 */ 1955 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 1956 1957 /* reg_et0 1958 * Vlan Tag0 EtherType0 enable. 1959 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 1960 * equal to ether_type0. 1961 * 0: disable 1962 * 1: enable (default) 1963 * Access: RW 1964 */ 1965 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 1966 1967 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 1968 bool et0) 1969 { 1970 MLXSW_REG_ZERO(spvc, payload); 1971 mlxsw_reg_spvc_local_port_set(payload, local_port); 1972 /* Enable inner_et1 and inner_et0 to enable identification of double 1973 * tagged packets. 1974 */ 1975 mlxsw_reg_spvc_inner_et1_set(payload, 1); 1976 mlxsw_reg_spvc_inner_et0_set(payload, 1); 1977 mlxsw_reg_spvc_et1_set(payload, et1); 1978 mlxsw_reg_spvc_et0_set(payload, et0); 1979 } 1980 1981 /* SPEVET - Switch Port Egress VLAN EtherType 1982 * ------------------------------------------ 1983 * The switch port egress VLAN EtherType configures which EtherType to push at 1984 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 1985 * is set. 1986 */ 1987 #define MLXSW_REG_SPEVET_ID 0x202A 1988 #define MLXSW_REG_SPEVET_LEN 0x08 1989 1990 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 1991 1992 /* reg_spevet_local_port 1993 * Egress Local port number. 1994 * Not supported to CPU port. 1995 * Access: Index 1996 */ 1997 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 1998 1999 /* reg_spevet_et_vlan 2000 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2001 * 0: ether_type0 - (default) 2002 * 1: ether_type1 2003 * 2: ether_type2 2004 * Access: RW 2005 */ 2006 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2007 2008 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2009 u8 et_vlan) 2010 { 2011 MLXSW_REG_ZERO(spevet, payload); 2012 mlxsw_reg_spevet_local_port_set(payload, local_port); 2013 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2014 } 2015 2016 /* SFTR-V2 - Switch Flooding Table Version 2 Register 2017 * -------------------------------------------------- 2018 * The switch flooding table is used for flooding packet replication. The table 2019 * defines a bit mask of ports for packet replication. 2020 */ 2021 #define MLXSW_REG_SFTR2_ID 0x202F 2022 #define MLXSW_REG_SFTR2_LEN 0x120 2023 2024 MLXSW_REG_DEFINE(sftr2, MLXSW_REG_SFTR2_ID, MLXSW_REG_SFTR2_LEN); 2025 2026 /* reg_sftr2_swid 2027 * Switch partition ID with which to associate the port. 2028 * Access: Index 2029 */ 2030 MLXSW_ITEM32(reg, sftr2, swid, 0x00, 24, 8); 2031 2032 /* reg_sftr2_flood_table 2033 * Flooding table index to associate with the specific type on the specific 2034 * switch partition. 2035 * Access: Index 2036 */ 2037 MLXSW_ITEM32(reg, sftr2, flood_table, 0x00, 16, 6); 2038 2039 /* reg_sftr2_index 2040 * Index. Used as an index into the Flooding Table in case the table is 2041 * configured to use VID / FID or FID Offset. 2042 * Access: Index 2043 */ 2044 MLXSW_ITEM32(reg, sftr2, index, 0x00, 0, 16); 2045 2046 /* reg_sftr2_table_type 2047 * See mlxsw_flood_table_type 2048 * Access: RW 2049 */ 2050 MLXSW_ITEM32(reg, sftr2, table_type, 0x04, 16, 3); 2051 2052 /* reg_sftr2_range 2053 * Range of entries to update 2054 * Access: Index 2055 */ 2056 MLXSW_ITEM32(reg, sftr2, range, 0x04, 0, 16); 2057 2058 /* reg_sftr2_port 2059 * Local port membership (1 bit per port). 2060 * Access: RW 2061 */ 2062 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port, 0x20, 0x80, 1); 2063 2064 /* reg_sftr2_port_mask 2065 * Local port mask (1 bit per port). 2066 * Access: WO 2067 */ 2068 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port_mask, 0xA0, 0x80, 1); 2069 2070 static inline void mlxsw_reg_sftr2_pack(char *payload, 2071 unsigned int flood_table, 2072 unsigned int index, 2073 enum mlxsw_flood_table_type table_type, 2074 unsigned int range, u16 port, bool set) 2075 { 2076 MLXSW_REG_ZERO(sftr2, payload); 2077 mlxsw_reg_sftr2_swid_set(payload, 0); 2078 mlxsw_reg_sftr2_flood_table_set(payload, flood_table); 2079 mlxsw_reg_sftr2_index_set(payload, index); 2080 mlxsw_reg_sftr2_table_type_set(payload, table_type); 2081 mlxsw_reg_sftr2_range_set(payload, range); 2082 mlxsw_reg_sftr2_port_set(payload, port, set); 2083 mlxsw_reg_sftr2_port_mask_set(payload, port, 1); 2084 } 2085 2086 /* SMID-V2 - Switch Multicast ID Version 2 Register 2087 * ------------------------------------------------ 2088 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2089 * of the multicast group within the stacking domain, into a list of local 2090 * ports into which the packet is replicated. 2091 */ 2092 #define MLXSW_REG_SMID2_ID 0x2034 2093 #define MLXSW_REG_SMID2_LEN 0x120 2094 2095 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2096 2097 /* reg_smid2_swid 2098 * Switch partition ID. 2099 * Access: Index 2100 */ 2101 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2102 2103 /* reg_smid2_mid 2104 * Multicast identifier - global identifier that represents the multicast group 2105 * across all devices. 2106 * Access: Index 2107 */ 2108 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2109 2110 /* reg_smid2_port 2111 * Local port memebership (1 bit per port). 2112 * Access: RW 2113 */ 2114 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2115 2116 /* reg_smid2_port_mask 2117 * Local port mask (1 bit per port). 2118 * Access: WO 2119 */ 2120 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2121 2122 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2123 bool set) 2124 { 2125 MLXSW_REG_ZERO(smid2, payload); 2126 mlxsw_reg_smid2_swid_set(payload, 0); 2127 mlxsw_reg_smid2_mid_set(payload, mid); 2128 mlxsw_reg_smid2_port_set(payload, port, set); 2129 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2130 } 2131 2132 /* CWTP - Congetion WRED ECN TClass Profile 2133 * ---------------------------------------- 2134 * Configures the profiles for queues of egress port and traffic class 2135 */ 2136 #define MLXSW_REG_CWTP_ID 0x2802 2137 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2138 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2139 #define MLXSW_REG_CWTP_LEN 0x40 2140 2141 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2142 2143 /* reg_cwtp_local_port 2144 * Local port number 2145 * Not supported for CPU port 2146 * Access: Index 2147 */ 2148 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2149 2150 /* reg_cwtp_traffic_class 2151 * Traffic Class to configure 2152 * Access: Index 2153 */ 2154 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2155 2156 /* reg_cwtp_profile_min 2157 * Minimum Average Queue Size of the profile in cells. 2158 * Access: RW 2159 */ 2160 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2161 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2162 2163 /* reg_cwtp_profile_percent 2164 * Percentage of WRED and ECN marking for maximum Average Queue size 2165 * Range is 0 to 100, units of integer percentage 2166 * Access: RW 2167 */ 2168 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2169 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2170 2171 /* reg_cwtp_profile_max 2172 * Maximum Average Queue size of the profile in cells 2173 * Access: RW 2174 */ 2175 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2176 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2177 2178 #define MLXSW_REG_CWTP_MIN_VALUE 64 2179 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2180 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2181 2182 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2183 u8 traffic_class) 2184 { 2185 int i; 2186 2187 MLXSW_REG_ZERO(cwtp, payload); 2188 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2189 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2190 2191 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2192 mlxsw_reg_cwtp_profile_min_set(payload, i, 2193 MLXSW_REG_CWTP_MIN_VALUE); 2194 mlxsw_reg_cwtp_profile_max_set(payload, i, 2195 MLXSW_REG_CWTP_MIN_VALUE); 2196 } 2197 } 2198 2199 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2200 2201 static inline void 2202 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2203 u32 probability) 2204 { 2205 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2206 2207 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2208 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2209 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2210 } 2211 2212 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2213 * --------------------------------------------------- 2214 * The CWTPM register maps each egress port and traffic class to profile num. 2215 */ 2216 #define MLXSW_REG_CWTPM_ID 0x2803 2217 #define MLXSW_REG_CWTPM_LEN 0x44 2218 2219 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2220 2221 /* reg_cwtpm_local_port 2222 * Local port number 2223 * Not supported for CPU port 2224 * Access: Index 2225 */ 2226 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2227 2228 /* reg_cwtpm_traffic_class 2229 * Traffic Class to configure 2230 * Access: Index 2231 */ 2232 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2233 2234 /* reg_cwtpm_ew 2235 * Control enablement of WRED for traffic class: 2236 * 0 - Disable 2237 * 1 - Enable 2238 * Access: RW 2239 */ 2240 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2241 2242 /* reg_cwtpm_ee 2243 * Control enablement of ECN for traffic class: 2244 * 0 - Disable 2245 * 1 - Enable 2246 * Access: RW 2247 */ 2248 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2249 2250 /* reg_cwtpm_tcp_g 2251 * TCP Green Profile. 2252 * Index of the profile within {port, traffic class} to use. 2253 * 0 for disabling both WRED and ECN for this type of traffic. 2254 * Access: RW 2255 */ 2256 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2257 2258 /* reg_cwtpm_tcp_y 2259 * TCP Yellow Profile. 2260 * Index of the profile within {port, traffic class} to use. 2261 * 0 for disabling both WRED and ECN for this type of traffic. 2262 * Access: RW 2263 */ 2264 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2265 2266 /* reg_cwtpm_tcp_r 2267 * TCP Red Profile. 2268 * Index of the profile within {port, traffic class} to use. 2269 * 0 for disabling both WRED and ECN for this type of traffic. 2270 * Access: RW 2271 */ 2272 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2273 2274 /* reg_cwtpm_ntcp_g 2275 * Non-TCP Green Profile. 2276 * Index of the profile within {port, traffic class} to use. 2277 * 0 for disabling both WRED and ECN for this type of traffic. 2278 * Access: RW 2279 */ 2280 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2281 2282 /* reg_cwtpm_ntcp_y 2283 * Non-TCP Yellow Profile. 2284 * Index of the profile within {port, traffic class} to use. 2285 * 0 for disabling both WRED and ECN for this type of traffic. 2286 * Access: RW 2287 */ 2288 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2289 2290 /* reg_cwtpm_ntcp_r 2291 * Non-TCP Red Profile. 2292 * Index of the profile within {port, traffic class} to use. 2293 * 0 for disabling both WRED and ECN for this type of traffic. 2294 * Access: RW 2295 */ 2296 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2297 2298 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2299 2300 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2301 u8 traffic_class, u8 profile, 2302 bool wred, bool ecn) 2303 { 2304 MLXSW_REG_ZERO(cwtpm, payload); 2305 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2306 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2307 mlxsw_reg_cwtpm_ew_set(payload, wred); 2308 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2309 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2310 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2311 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2312 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2313 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2314 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2315 } 2316 2317 /* PGCR - Policy-Engine General Configuration Register 2318 * --------------------------------------------------- 2319 * This register configures general Policy-Engine settings. 2320 */ 2321 #define MLXSW_REG_PGCR_ID 0x3001 2322 #define MLXSW_REG_PGCR_LEN 0x20 2323 2324 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2325 2326 /* reg_pgcr_default_action_pointer_base 2327 * Default action pointer base. Each region has a default action pointer 2328 * which is equal to default_action_pointer_base + region_id. 2329 * Access: RW 2330 */ 2331 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2332 2333 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2334 { 2335 MLXSW_REG_ZERO(pgcr, payload); 2336 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2337 } 2338 2339 /* PPBT - Policy-Engine Port Binding Table 2340 * --------------------------------------- 2341 * This register is used for configuration of the Port Binding Table. 2342 */ 2343 #define MLXSW_REG_PPBT_ID 0x3002 2344 #define MLXSW_REG_PPBT_LEN 0x14 2345 2346 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2347 2348 enum mlxsw_reg_pxbt_e { 2349 MLXSW_REG_PXBT_E_IACL, 2350 MLXSW_REG_PXBT_E_EACL, 2351 }; 2352 2353 /* reg_ppbt_e 2354 * Access: Index 2355 */ 2356 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2357 2358 enum mlxsw_reg_pxbt_op { 2359 MLXSW_REG_PXBT_OP_BIND, 2360 MLXSW_REG_PXBT_OP_UNBIND, 2361 }; 2362 2363 /* reg_ppbt_op 2364 * Access: RW 2365 */ 2366 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2367 2368 /* reg_ppbt_local_port 2369 * Local port. Not including CPU port. 2370 * Access: Index 2371 */ 2372 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2373 2374 /* reg_ppbt_g 2375 * group - When set, the binding is of an ACL group. When cleared, 2376 * the binding is of an ACL. 2377 * Must be set to 1 for Spectrum. 2378 * Access: RW 2379 */ 2380 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2381 2382 /* reg_ppbt_acl_info 2383 * ACL/ACL group identifier. If the g bit is set, this field should hold 2384 * the acl_group_id, else it should hold the acl_id. 2385 * Access: RW 2386 */ 2387 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2388 2389 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2390 enum mlxsw_reg_pxbt_op op, 2391 u16 local_port, u16 acl_info) 2392 { 2393 MLXSW_REG_ZERO(ppbt, payload); 2394 mlxsw_reg_ppbt_e_set(payload, e); 2395 mlxsw_reg_ppbt_op_set(payload, op); 2396 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2397 mlxsw_reg_ppbt_g_set(payload, true); 2398 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2399 } 2400 2401 /* PACL - Policy-Engine ACL Register 2402 * --------------------------------- 2403 * This register is used for configuration of the ACL. 2404 */ 2405 #define MLXSW_REG_PACL_ID 0x3004 2406 #define MLXSW_REG_PACL_LEN 0x70 2407 2408 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2409 2410 /* reg_pacl_v 2411 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2412 * while the ACL is bounded to either a port, VLAN or ACL rule. 2413 * Access: RW 2414 */ 2415 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2416 2417 /* reg_pacl_acl_id 2418 * An identifier representing the ACL (managed by software) 2419 * Range 0 .. cap_max_acl_regions - 1 2420 * Access: Index 2421 */ 2422 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2423 2424 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2425 2426 /* reg_pacl_tcam_region_info 2427 * Opaque object that represents a TCAM region. 2428 * Obtained through PTAR register. 2429 * Access: RW 2430 */ 2431 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2432 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2433 2434 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2435 bool valid, const char *tcam_region_info) 2436 { 2437 MLXSW_REG_ZERO(pacl, payload); 2438 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2439 mlxsw_reg_pacl_v_set(payload, valid); 2440 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2441 } 2442 2443 /* PAGT - Policy-Engine ACL Group Table 2444 * ------------------------------------ 2445 * This register is used for configuration of the ACL Group Table. 2446 */ 2447 #define MLXSW_REG_PAGT_ID 0x3005 2448 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2449 #define MLXSW_REG_PAGT_ACL_LEN 4 2450 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2451 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2452 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2453 2454 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2455 2456 /* reg_pagt_size 2457 * Number of ACLs in the group. 2458 * Size 0 invalidates a group. 2459 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2460 * Total number of ACLs in all groups must be lower or equal 2461 * to cap_max_acl_tot_groups 2462 * Note: a group which is binded must not be invalidated 2463 * Access: Index 2464 */ 2465 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2466 2467 /* reg_pagt_acl_group_id 2468 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2469 * the ACL Group identifier (managed by software). 2470 * Access: Index 2471 */ 2472 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2473 2474 /* reg_pagt_multi 2475 * Multi-ACL 2476 * 0 - This ACL is the last ACL in the multi-ACL 2477 * 1 - This ACL is part of a multi-ACL 2478 * Access: RW 2479 */ 2480 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2481 2482 /* reg_pagt_acl_id 2483 * ACL identifier 2484 * Access: RW 2485 */ 2486 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2487 2488 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2489 { 2490 MLXSW_REG_ZERO(pagt, payload); 2491 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2492 } 2493 2494 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2495 u16 acl_id, bool multi) 2496 { 2497 u8 size = mlxsw_reg_pagt_size_get(payload); 2498 2499 if (index >= size) 2500 mlxsw_reg_pagt_size_set(payload, index + 1); 2501 mlxsw_reg_pagt_multi_set(payload, index, multi); 2502 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2503 } 2504 2505 /* PTAR - Policy-Engine TCAM Allocation Register 2506 * --------------------------------------------- 2507 * This register is used for allocation of regions in the TCAM. 2508 * Note: Query method is not supported on this register. 2509 */ 2510 #define MLXSW_REG_PTAR_ID 0x3006 2511 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2512 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2513 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2514 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2515 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2516 2517 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2518 2519 enum mlxsw_reg_ptar_op { 2520 /* allocate a TCAM region */ 2521 MLXSW_REG_PTAR_OP_ALLOC, 2522 /* resize a TCAM region */ 2523 MLXSW_REG_PTAR_OP_RESIZE, 2524 /* deallocate TCAM region */ 2525 MLXSW_REG_PTAR_OP_FREE, 2526 /* test allocation */ 2527 MLXSW_REG_PTAR_OP_TEST, 2528 }; 2529 2530 /* reg_ptar_op 2531 * Access: OP 2532 */ 2533 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2534 2535 /* reg_ptar_action_set_type 2536 * Type of action set to be used on this region. 2537 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2538 * Access: WO 2539 */ 2540 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2541 2542 enum mlxsw_reg_ptar_key_type { 2543 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2544 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2545 }; 2546 2547 /* reg_ptar_key_type 2548 * TCAM key type for the region. 2549 * Access: WO 2550 */ 2551 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2552 2553 /* reg_ptar_region_size 2554 * TCAM region size. When allocating/resizing this is the requested size, 2555 * the response is the actual size. Note that actual size may be 2556 * larger than requested. 2557 * Allowed range 1 .. cap_max_rules-1 2558 * Reserved during op deallocate. 2559 * Access: WO 2560 */ 2561 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2562 2563 /* reg_ptar_region_id 2564 * Region identifier 2565 * Range 0 .. cap_max_regions-1 2566 * Access: Index 2567 */ 2568 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2569 2570 /* reg_ptar_tcam_region_info 2571 * Opaque object that represents the TCAM region. 2572 * Returned when allocating a region. 2573 * Provided by software for ACL generation and region deallocation and resize. 2574 * Access: RW 2575 */ 2576 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2577 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2578 2579 /* reg_ptar_flexible_key_id 2580 * Identifier of the Flexible Key. 2581 * Only valid if key_type == "FLEX_KEY" 2582 * The key size will be rounded up to one of the following values: 2583 * 9B, 18B, 36B, 54B. 2584 * This field is reserved for in resize operation. 2585 * Access: WO 2586 */ 2587 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2588 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2589 2590 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2591 enum mlxsw_reg_ptar_key_type key_type, 2592 u16 region_size, u16 region_id, 2593 const char *tcam_region_info) 2594 { 2595 MLXSW_REG_ZERO(ptar, payload); 2596 mlxsw_reg_ptar_op_set(payload, op); 2597 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2598 mlxsw_reg_ptar_key_type_set(payload, key_type); 2599 mlxsw_reg_ptar_region_size_set(payload, region_size); 2600 mlxsw_reg_ptar_region_id_set(payload, region_id); 2601 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2602 } 2603 2604 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2605 u16 key_id) 2606 { 2607 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2608 } 2609 2610 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2611 { 2612 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2613 } 2614 2615 /* PPBS - Policy-Engine Policy Based Switching Register 2616 * ---------------------------------------------------- 2617 * This register retrieves and sets Policy Based Switching Table entries. 2618 */ 2619 #define MLXSW_REG_PPBS_ID 0x300C 2620 #define MLXSW_REG_PPBS_LEN 0x14 2621 2622 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2623 2624 /* reg_ppbs_pbs_ptr 2625 * Index into the PBS table. 2626 * For Spectrum, the index points to the KVD Linear. 2627 * Access: Index 2628 */ 2629 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2630 2631 /* reg_ppbs_system_port 2632 * Unique port identifier for the final destination of the packet. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2636 2637 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2638 u16 system_port) 2639 { 2640 MLXSW_REG_ZERO(ppbs, payload); 2641 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2642 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2643 } 2644 2645 /* PRCR - Policy-Engine Rules Copy Register 2646 * ---------------------------------------- 2647 * This register is used for accessing rules within a TCAM region. 2648 */ 2649 #define MLXSW_REG_PRCR_ID 0x300D 2650 #define MLXSW_REG_PRCR_LEN 0x40 2651 2652 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2653 2654 enum mlxsw_reg_prcr_op { 2655 /* Move rules. Moves the rules from "tcam_region_info" starting 2656 * at offset "offset" to "dest_tcam_region_info" 2657 * at offset "dest_offset." 2658 */ 2659 MLXSW_REG_PRCR_OP_MOVE, 2660 /* Copy rules. Copies the rules from "tcam_region_info" starting 2661 * at offset "offset" to "dest_tcam_region_info" 2662 * at offset "dest_offset." 2663 */ 2664 MLXSW_REG_PRCR_OP_COPY, 2665 }; 2666 2667 /* reg_prcr_op 2668 * Access: OP 2669 */ 2670 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2671 2672 /* reg_prcr_offset 2673 * Offset within the source region to copy/move from. 2674 * Access: Index 2675 */ 2676 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2677 2678 /* reg_prcr_size 2679 * The number of rules to copy/move. 2680 * Access: WO 2681 */ 2682 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2683 2684 /* reg_prcr_tcam_region_info 2685 * Opaque object that represents the source TCAM region. 2686 * Access: Index 2687 */ 2688 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2689 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2690 2691 /* reg_prcr_dest_offset 2692 * Offset within the source region to copy/move to. 2693 * Access: Index 2694 */ 2695 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2696 2697 /* reg_prcr_dest_tcam_region_info 2698 * Opaque object that represents the destination TCAM region. 2699 * Access: Index 2700 */ 2701 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2702 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2703 2704 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2705 const char *src_tcam_region_info, 2706 u16 src_offset, 2707 const char *dest_tcam_region_info, 2708 u16 dest_offset, u16 size) 2709 { 2710 MLXSW_REG_ZERO(prcr, payload); 2711 mlxsw_reg_prcr_op_set(payload, op); 2712 mlxsw_reg_prcr_offset_set(payload, src_offset); 2713 mlxsw_reg_prcr_size_set(payload, size); 2714 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2715 src_tcam_region_info); 2716 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2717 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2718 dest_tcam_region_info); 2719 } 2720 2721 /* PEFA - Policy-Engine Extended Flexible Action Register 2722 * ------------------------------------------------------ 2723 * This register is used for accessing an extended flexible action entry 2724 * in the central KVD Linear Database. 2725 */ 2726 #define MLXSW_REG_PEFA_ID 0x300F 2727 #define MLXSW_REG_PEFA_LEN 0xB0 2728 2729 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2730 2731 /* reg_pefa_index 2732 * Index in the KVD Linear Centralized Database. 2733 * Access: Index 2734 */ 2735 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2736 2737 /* reg_pefa_a 2738 * Index in the KVD Linear Centralized Database. 2739 * Activity 2740 * For a new entry: set if ca=0, clear if ca=1 2741 * Set if a packet lookup has hit on the specific entry 2742 * Access: RO 2743 */ 2744 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2745 2746 /* reg_pefa_ca 2747 * Clear activity 2748 * When write: activity is according to this field 2749 * When read: after reading the activity is cleared according to ca 2750 * Access: OP 2751 */ 2752 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2753 2754 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2755 2756 /* reg_pefa_flex_action_set 2757 * Action-set to perform when rule is matched. 2758 * Must be zero padded if action set is shorter. 2759 * Access: RW 2760 */ 2761 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2762 2763 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2764 const char *flex_action_set) 2765 { 2766 MLXSW_REG_ZERO(pefa, payload); 2767 mlxsw_reg_pefa_index_set(payload, index); 2768 mlxsw_reg_pefa_ca_set(payload, ca); 2769 if (flex_action_set) 2770 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2771 flex_action_set); 2772 } 2773 2774 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2775 { 2776 *p_a = mlxsw_reg_pefa_a_get(payload); 2777 } 2778 2779 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2780 * -------------------------------------------------------------- 2781 * This register is used for binding Multicast router to an ACL group 2782 * that serves the MC router. 2783 * This register is not supported by SwitchX/-2 and Spectrum. 2784 */ 2785 #define MLXSW_REG_PEMRBT_ID 0x3014 2786 #define MLXSW_REG_PEMRBT_LEN 0x14 2787 2788 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2789 2790 enum mlxsw_reg_pemrbt_protocol { 2791 MLXSW_REG_PEMRBT_PROTO_IPV4, 2792 MLXSW_REG_PEMRBT_PROTO_IPV6, 2793 }; 2794 2795 /* reg_pemrbt_protocol 2796 * Access: Index 2797 */ 2798 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2799 2800 /* reg_pemrbt_group_id 2801 * ACL group identifier. 2802 * Range 0..cap_max_acl_groups-1 2803 * Access: RW 2804 */ 2805 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2806 2807 static inline void 2808 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2809 u16 group_id) 2810 { 2811 MLXSW_REG_ZERO(pemrbt, payload); 2812 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2813 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2814 } 2815 2816 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2817 * ----------------------------------------------------- 2818 * This register is used for accessing rules within a TCAM region. 2819 * It is a new version of PTCE in order to support wider key, 2820 * mask and action within a TCAM region. This register is not supported 2821 * by SwitchX and SwitchX-2. 2822 */ 2823 #define MLXSW_REG_PTCE2_ID 0x3017 2824 #define MLXSW_REG_PTCE2_LEN 0x1D8 2825 2826 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2827 2828 /* reg_ptce2_v 2829 * Valid. 2830 * Access: RW 2831 */ 2832 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2833 2834 /* reg_ptce2_a 2835 * Activity. Set if a packet lookup has hit on the specific entry. 2836 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2837 * Access: RO 2838 */ 2839 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2840 2841 enum mlxsw_reg_ptce2_op { 2842 /* Read operation. */ 2843 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2844 /* clear on read operation. Used to read entry 2845 * and clear Activity bit. 2846 */ 2847 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2848 /* Write operation. Used to write a new entry to the table. 2849 * All R/W fields are relevant for new entry. Activity bit is set 2850 * for new entries - Note write with v = 0 will delete the entry. 2851 */ 2852 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2853 /* Update action. Only action set will be updated. */ 2854 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2855 /* Clear activity. A bit is cleared for the entry. */ 2856 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2857 }; 2858 2859 /* reg_ptce2_op 2860 * Access: OP 2861 */ 2862 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2863 2864 /* reg_ptce2_offset 2865 * Access: Index 2866 */ 2867 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2868 2869 /* reg_ptce2_priority 2870 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2871 * Note: priority does not have to be unique per rule. 2872 * Within a region, higher priority should have lower offset (no limitation 2873 * between regions in a multi-region). 2874 * Access: RW 2875 */ 2876 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2877 2878 /* reg_ptce2_tcam_region_info 2879 * Opaque object that represents the TCAM region. 2880 * Access: Index 2881 */ 2882 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2883 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2884 2885 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2886 2887 /* reg_ptce2_flex_key_blocks 2888 * ACL Key. 2889 * Access: RW 2890 */ 2891 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2892 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2893 2894 /* reg_ptce2_mask 2895 * mask- in the same size as key. A bit that is set directs the TCAM 2896 * to compare the corresponding bit in key. A bit that is clear directs 2897 * the TCAM to ignore the corresponding bit in key. 2898 * Access: RW 2899 */ 2900 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2901 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2902 2903 /* reg_ptce2_flex_action_set 2904 * ACL action set. 2905 * Access: RW 2906 */ 2907 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2908 MLXSW_REG_FLEX_ACTION_SET_LEN); 2909 2910 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2911 enum mlxsw_reg_ptce2_op op, 2912 const char *tcam_region_info, 2913 u16 offset, u32 priority) 2914 { 2915 MLXSW_REG_ZERO(ptce2, payload); 2916 mlxsw_reg_ptce2_v_set(payload, valid); 2917 mlxsw_reg_ptce2_op_set(payload, op); 2918 mlxsw_reg_ptce2_offset_set(payload, offset); 2919 mlxsw_reg_ptce2_priority_set(payload, priority); 2920 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2921 } 2922 2923 /* PERPT - Policy-Engine ERP Table Register 2924 * ---------------------------------------- 2925 * This register adds and removes eRPs from the eRP table. 2926 */ 2927 #define MLXSW_REG_PERPT_ID 0x3021 2928 #define MLXSW_REG_PERPT_LEN 0x80 2929 2930 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2931 2932 /* reg_perpt_erpt_bank 2933 * eRP table bank. 2934 * Range 0 .. cap_max_erp_table_banks - 1 2935 * Access: Index 2936 */ 2937 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2938 2939 /* reg_perpt_erpt_index 2940 * Index to eRP table within the eRP bank. 2941 * Range is 0 .. cap_max_erp_table_bank_size - 1 2942 * Access: Index 2943 */ 2944 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2945 2946 enum mlxsw_reg_perpt_key_size { 2947 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2948 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2949 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2950 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2951 }; 2952 2953 /* reg_perpt_key_size 2954 * Access: OP 2955 */ 2956 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2957 2958 /* reg_perpt_bf_bypass 2959 * 0 - The eRP is used only if bloom filter state is set for the given 2960 * rule. 2961 * 1 - The eRP is used regardless of bloom filter state. 2962 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2963 * Access: RW 2964 */ 2965 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2966 2967 /* reg_perpt_erp_id 2968 * eRP ID for use by the rules. 2969 * Access: RW 2970 */ 2971 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2972 2973 /* reg_perpt_erpt_base_bank 2974 * Base eRP table bank, points to head of erp_vector 2975 * Range is 0 .. cap_max_erp_table_banks - 1 2976 * Access: OP 2977 */ 2978 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2979 2980 /* reg_perpt_erpt_base_index 2981 * Base index to eRP table within the eRP bank 2982 * Range is 0 .. cap_max_erp_table_bank_size - 1 2983 * Access: OP 2984 */ 2985 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2986 2987 /* reg_perpt_erp_index_in_vector 2988 * eRP index in the vector. 2989 * Access: OP 2990 */ 2991 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2992 2993 /* reg_perpt_erp_vector 2994 * eRP vector. 2995 * Access: OP 2996 */ 2997 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2998 2999 /* reg_perpt_mask 3000 * Mask 3001 * 0 - A-TCAM will ignore the bit in key 3002 * 1 - A-TCAM will compare the bit in key 3003 * Access: RW 3004 */ 3005 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3006 3007 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3008 unsigned long *erp_vector, 3009 unsigned long size) 3010 { 3011 unsigned long bit; 3012 3013 for_each_set_bit(bit, erp_vector, size) 3014 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3015 } 3016 3017 static inline void 3018 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3019 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3020 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3021 char *mask) 3022 { 3023 MLXSW_REG_ZERO(perpt, payload); 3024 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3025 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3026 mlxsw_reg_perpt_key_size_set(payload, key_size); 3027 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3028 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3029 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3030 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3031 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3032 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3033 } 3034 3035 /* PERAR - Policy-Engine Region Association Register 3036 * ------------------------------------------------- 3037 * This register associates a hw region for region_id's. Changing on the fly 3038 * is supported by the device. 3039 */ 3040 #define MLXSW_REG_PERAR_ID 0x3026 3041 #define MLXSW_REG_PERAR_LEN 0x08 3042 3043 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3044 3045 /* reg_perar_region_id 3046 * Region identifier 3047 * Range 0 .. cap_max_regions-1 3048 * Access: Index 3049 */ 3050 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3051 3052 static inline unsigned int 3053 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3054 { 3055 return DIV_ROUND_UP(block_num, 4); 3056 } 3057 3058 /* reg_perar_hw_region 3059 * HW Region 3060 * Range 0 .. cap_max_regions-1 3061 * Default: hw_region = region_id 3062 * For a 8 key block region, 2 consecutive regions are used 3063 * For a 12 key block region, 3 consecutive regions are used 3064 * Access: RW 3065 */ 3066 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3067 3068 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3069 u16 hw_region) 3070 { 3071 MLXSW_REG_ZERO(perar, payload); 3072 mlxsw_reg_perar_region_id_set(payload, region_id); 3073 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3074 } 3075 3076 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3077 * ----------------------------------------------------- 3078 * This register is a new version of PTCE-V2 in order to support the 3079 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3080 */ 3081 #define MLXSW_REG_PTCE3_ID 0x3027 3082 #define MLXSW_REG_PTCE3_LEN 0xF0 3083 3084 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3085 3086 /* reg_ptce3_v 3087 * Valid. 3088 * Access: RW 3089 */ 3090 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3091 3092 enum mlxsw_reg_ptce3_op { 3093 /* Write operation. Used to write a new entry to the table. 3094 * All R/W fields are relevant for new entry. Activity bit is set 3095 * for new entries. Write with v = 0 will delete the entry. Must 3096 * not be used if an entry exists. 3097 */ 3098 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3099 /* Update operation */ 3100 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3101 /* Read operation */ 3102 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3103 }; 3104 3105 /* reg_ptce3_op 3106 * Access: OP 3107 */ 3108 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3109 3110 /* reg_ptce3_priority 3111 * Priority of the rule. Higher values win. 3112 * For Spectrum-2 range is 1..cap_kvd_size - 1 3113 * Note: Priority does not have to be unique per rule. 3114 * Access: RW 3115 */ 3116 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3117 3118 /* reg_ptce3_tcam_region_info 3119 * Opaque object that represents the TCAM region. 3120 * Access: Index 3121 */ 3122 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3123 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3124 3125 /* reg_ptce3_flex2_key_blocks 3126 * ACL key. The key must be masked according to eRP (if exists) or 3127 * according to master mask. 3128 * Access: Index 3129 */ 3130 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3131 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3132 3133 /* reg_ptce3_erp_id 3134 * eRP ID. 3135 * Access: Index 3136 */ 3137 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3138 3139 /* reg_ptce3_delta_start 3140 * Start point of delta_value and delta_mask, in bits. Must not exceed 3141 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3142 * Access: Index 3143 */ 3144 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3145 3146 /* reg_ptce3_delta_mask 3147 * Delta mask. 3148 * 0 - Ignore relevant bit in delta_value 3149 * 1 - Compare relevant bit in delta_value 3150 * Delta mask must not be set for reserved fields in the key blocks. 3151 * Note: No delta when no eRPs. Thus, for regions with 3152 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3153 * Access: Index 3154 */ 3155 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3156 3157 /* reg_ptce3_delta_value 3158 * Delta value. 3159 * Bits which are masked by delta_mask must be 0. 3160 * Access: Index 3161 */ 3162 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3163 3164 /* reg_ptce3_prune_vector 3165 * Pruning vector relative to the PERPT.erp_id. 3166 * Used for reducing lookups. 3167 * 0 - NEED: Do a lookup using the eRP. 3168 * 1 - PRUNE: Do not perform a lookup using the eRP. 3169 * Maybe be modified by PEAPBL and PEAPBM. 3170 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3171 * all 1's or all 0's. 3172 * Access: RW 3173 */ 3174 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3175 3176 /* reg_ptce3_prune_ctcam 3177 * Pruning on C-TCAM. Used for reducing lookups. 3178 * 0 - NEED: Do a lookup in the C-TCAM. 3179 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3180 * Access: RW 3181 */ 3182 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3183 3184 /* reg_ptce3_large_exists 3185 * Large entry key ID exists. 3186 * Within the region: 3187 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3188 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3189 * For rule delete: The MSB of the key will be removed. 3190 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3191 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3192 * For rule delete: The MSB of the key will not be removed. 3193 * Access: WO 3194 */ 3195 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3196 3197 /* reg_ptce3_large_entry_key_id 3198 * Large entry key ID. 3199 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3200 * blocks. Must be different for different keys which have the same common 3201 * 6 key blocks (MSB, blocks 6..11) key within a region. 3202 * Range is 0..cap_max_pe_large_key_id - 1 3203 * Access: RW 3204 */ 3205 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3206 3207 /* reg_ptce3_action_pointer 3208 * Pointer to action. 3209 * Range is 0..cap_max_kvd_action_sets - 1 3210 * Access: RW 3211 */ 3212 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3213 3214 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3215 enum mlxsw_reg_ptce3_op op, 3216 u32 priority, 3217 const char *tcam_region_info, 3218 const char *key, u8 erp_id, 3219 u16 delta_start, u8 delta_mask, 3220 u8 delta_value, bool large_exists, 3221 u32 lkey_id, u32 action_pointer) 3222 { 3223 MLXSW_REG_ZERO(ptce3, payload); 3224 mlxsw_reg_ptce3_v_set(payload, valid); 3225 mlxsw_reg_ptce3_op_set(payload, op); 3226 mlxsw_reg_ptce3_priority_set(payload, priority); 3227 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3228 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3229 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3230 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3231 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3232 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3233 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3234 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3235 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3236 } 3237 3238 /* PERCR - Policy-Engine Region Configuration Register 3239 * --------------------------------------------------- 3240 * This register configures the region parameters. The region_id must be 3241 * allocated. 3242 */ 3243 #define MLXSW_REG_PERCR_ID 0x302A 3244 #define MLXSW_REG_PERCR_LEN 0x80 3245 3246 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3247 3248 /* reg_percr_region_id 3249 * Region identifier. 3250 * Range 0..cap_max_regions-1 3251 * Access: Index 3252 */ 3253 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3254 3255 /* reg_percr_atcam_ignore_prune 3256 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3257 * Access: RW 3258 */ 3259 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3260 3261 /* reg_percr_ctcam_ignore_prune 3262 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3263 * Access: RW 3264 */ 3265 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3266 3267 /* reg_percr_bf_bypass 3268 * Bloom filter bypass. 3269 * 0 - Bloom filter is used (default) 3270 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3271 * region_id or eRP. See PERPT.bf_bypass 3272 * Access: RW 3273 */ 3274 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3275 3276 /* reg_percr_master_mask 3277 * Master mask. Logical OR mask of all masks of all rules of a region 3278 * (both A-TCAM and C-TCAM). When there are no eRPs 3279 * (erpt_pointer_valid = 0), then this provides the mask. 3280 * Access: RW 3281 */ 3282 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3283 3284 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3285 { 3286 MLXSW_REG_ZERO(percr, payload); 3287 mlxsw_reg_percr_region_id_set(payload, region_id); 3288 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3289 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3290 mlxsw_reg_percr_bf_bypass_set(payload, false); 3291 } 3292 3293 /* PERERP - Policy-Engine Region eRP Register 3294 * ------------------------------------------ 3295 * This register configures the region eRP. The region_id must be 3296 * allocated. 3297 */ 3298 #define MLXSW_REG_PERERP_ID 0x302B 3299 #define MLXSW_REG_PERERP_LEN 0x1C 3300 3301 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3302 3303 /* reg_pererp_region_id 3304 * Region identifier. 3305 * Range 0..cap_max_regions-1 3306 * Access: Index 3307 */ 3308 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3309 3310 /* reg_pererp_ctcam_le 3311 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3312 * Access: RW 3313 */ 3314 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3315 3316 /* reg_pererp_erpt_pointer_valid 3317 * erpt_pointer is valid. 3318 * Access: RW 3319 */ 3320 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3321 3322 /* reg_pererp_erpt_bank_pointer 3323 * Pointer to eRP table bank. May be modified at any time. 3324 * Range 0..cap_max_erp_table_banks-1 3325 * Reserved when erpt_pointer_valid = 0 3326 */ 3327 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3328 3329 /* reg_pererp_erpt_pointer 3330 * Pointer to eRP table within the eRP bank. Can be changed for an 3331 * existing region. 3332 * Range 0..cap_max_erp_table_size-1 3333 * Reserved when erpt_pointer_valid = 0 3334 * Access: RW 3335 */ 3336 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3337 3338 /* reg_pererp_erpt_vector 3339 * Vector of allowed eRP indexes starting from erpt_pointer within the 3340 * erpt_bank_pointer. Next entries will be in next bank. 3341 * Note that eRP index is used and not eRP ID. 3342 * Reserved when erpt_pointer_valid = 0 3343 * Access: RW 3344 */ 3345 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3346 3347 /* reg_pererp_master_rp_id 3348 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3349 * for the lookup. Can be changed for an existing region. 3350 * Reserved when erpt_pointer_valid = 1 3351 * Access: RW 3352 */ 3353 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3354 3355 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3356 unsigned long *erp_vector, 3357 unsigned long size) 3358 { 3359 unsigned long bit; 3360 3361 for_each_set_bit(bit, erp_vector, size) 3362 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3363 } 3364 3365 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3366 bool ctcam_le, bool erpt_pointer_valid, 3367 u8 erpt_bank_pointer, u8 erpt_pointer, 3368 u8 master_rp_id) 3369 { 3370 MLXSW_REG_ZERO(pererp, payload); 3371 mlxsw_reg_pererp_region_id_set(payload, region_id); 3372 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3373 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3374 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3375 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3376 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3377 } 3378 3379 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3380 * ---------------------------------------------------------------- 3381 * This register configures the Bloom filter entries. 3382 */ 3383 #define MLXSW_REG_PEABFE_ID 0x3022 3384 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3385 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3386 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3387 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3388 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3389 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3390 3391 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3392 3393 /* reg_peabfe_size 3394 * Number of BF entries to be updated. 3395 * Range 1..256 3396 * Access: Op 3397 */ 3398 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3399 3400 /* reg_peabfe_bf_entry_state 3401 * Bloom filter state 3402 * 0 - Clear 3403 * 1 - Set 3404 * Access: RW 3405 */ 3406 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3407 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3408 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3409 3410 /* reg_peabfe_bf_entry_bank 3411 * Bloom filter bank ID 3412 * Range 0..cap_max_erp_table_banks-1 3413 * Access: Index 3414 */ 3415 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3416 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3417 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3418 3419 /* reg_peabfe_bf_entry_index 3420 * Bloom filter entry index 3421 * Range 0..2^cap_max_bf_log-1 3422 * Access: Index 3423 */ 3424 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3425 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3426 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3427 3428 static inline void mlxsw_reg_peabfe_pack(char *payload) 3429 { 3430 MLXSW_REG_ZERO(peabfe, payload); 3431 } 3432 3433 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3434 u8 state, u8 bank, u32 bf_index) 3435 { 3436 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3437 3438 if (rec_index >= num_rec) 3439 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3440 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3441 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3442 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3443 } 3444 3445 /* IEDR - Infrastructure Entry Delete Register 3446 * ---------------------------------------------------- 3447 * This register is used for deleting entries from the entry tables. 3448 * It is legitimate to attempt to delete a nonexisting entry (the device will 3449 * respond as a good flow). 3450 */ 3451 #define MLXSW_REG_IEDR_ID 0x3804 3452 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3453 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3454 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3455 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3456 MLXSW_REG_IEDR_REC_LEN * \ 3457 MLXSW_REG_IEDR_REC_MAX_COUNT) 3458 3459 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3460 3461 /* reg_iedr_num_rec 3462 * Number of records. 3463 * Access: OP 3464 */ 3465 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3466 3467 /* reg_iedr_rec_type 3468 * Resource type. 3469 * Access: OP 3470 */ 3471 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3472 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3473 3474 /* reg_iedr_rec_size 3475 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3476 * Access: OP 3477 */ 3478 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3479 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3480 3481 /* reg_iedr_rec_index_start 3482 * Resource index start. 3483 * Access: OP 3484 */ 3485 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3486 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3487 3488 static inline void mlxsw_reg_iedr_pack(char *payload) 3489 { 3490 MLXSW_REG_ZERO(iedr, payload); 3491 } 3492 3493 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3494 u8 rec_type, u16 rec_size, 3495 u32 rec_index_start) 3496 { 3497 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3498 3499 if (rec_index >= num_rec) 3500 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3501 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3502 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3503 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3504 } 3505 3506 /* QPTS - QoS Priority Trust State Register 3507 * ---------------------------------------- 3508 * This register controls the port policy to calculate the switch priority and 3509 * packet color based on incoming packet fields. 3510 */ 3511 #define MLXSW_REG_QPTS_ID 0x4002 3512 #define MLXSW_REG_QPTS_LEN 0x8 3513 3514 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3515 3516 /* reg_qpts_local_port 3517 * Local port number. 3518 * Access: Index 3519 * 3520 * Note: CPU port is supported. 3521 */ 3522 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3523 3524 enum mlxsw_reg_qpts_trust_state { 3525 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3526 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3527 }; 3528 3529 /* reg_qpts_trust_state 3530 * Trust state for a given port. 3531 * Access: RW 3532 */ 3533 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3534 3535 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3536 enum mlxsw_reg_qpts_trust_state ts) 3537 { 3538 MLXSW_REG_ZERO(qpts, payload); 3539 3540 mlxsw_reg_qpts_local_port_set(payload, local_port); 3541 mlxsw_reg_qpts_trust_state_set(payload, ts); 3542 } 3543 3544 /* QPCR - QoS Policer Configuration Register 3545 * ----------------------------------------- 3546 * The QPCR register is used to create policers - that limit 3547 * the rate of bytes or packets via some trap group. 3548 */ 3549 #define MLXSW_REG_QPCR_ID 0x4004 3550 #define MLXSW_REG_QPCR_LEN 0x28 3551 3552 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3553 3554 enum mlxsw_reg_qpcr_g { 3555 MLXSW_REG_QPCR_G_GLOBAL = 2, 3556 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3557 }; 3558 3559 /* reg_qpcr_g 3560 * The policer type. 3561 * Access: Index 3562 */ 3563 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3564 3565 /* reg_qpcr_pid 3566 * Policer ID. 3567 * Access: Index 3568 */ 3569 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3570 3571 /* reg_qpcr_clear_counter 3572 * Clear counters. 3573 * Access: OP 3574 */ 3575 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3576 3577 /* reg_qpcr_color_aware 3578 * Is the policer aware of colors. 3579 * Must be 0 (unaware) for cpu port. 3580 * Access: RW for unbounded policer. RO for bounded policer. 3581 */ 3582 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3583 3584 /* reg_qpcr_bytes 3585 * Is policer limit is for bytes per sec or packets per sec. 3586 * 0 - packets 3587 * 1 - bytes 3588 * Access: RW for unbounded policer. RO for bounded policer. 3589 */ 3590 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3591 3592 enum mlxsw_reg_qpcr_ir_units { 3593 MLXSW_REG_QPCR_IR_UNITS_M, 3594 MLXSW_REG_QPCR_IR_UNITS_K, 3595 }; 3596 3597 /* reg_qpcr_ir_units 3598 * Policer's units for cir and eir fields (for bytes limits only) 3599 * 1 - 10^3 3600 * 0 - 10^6 3601 * Access: OP 3602 */ 3603 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3604 3605 enum mlxsw_reg_qpcr_rate_type { 3606 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3607 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3608 }; 3609 3610 /* reg_qpcr_rate_type 3611 * Policer can have one limit (single rate) or 2 limits with specific operation 3612 * for packets that exceed the lower rate but not the upper one. 3613 * (For cpu port must be single rate) 3614 * Access: RW for unbounded policer. RO for bounded policer. 3615 */ 3616 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3617 3618 /* reg_qpc_cbs 3619 * Policer's committed burst size. 3620 * The policer is working with time slices of 50 nano sec. By default every 3621 * slice is granted the proportionate share of the committed rate. If we want to 3622 * allow a slice to exceed that share (while still keeping the rate per sec) we 3623 * can allow burst. The burst size is between the default proportionate share 3624 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3625 * committed rate will result in exceeding the rate). The burst size must be a 3626 * log of 2 and will be determined by 2^cbs. 3627 * Access: RW 3628 */ 3629 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3630 3631 /* reg_qpcr_cir 3632 * Policer's committed rate. 3633 * The rate used for sungle rate, the lower rate for double rate. 3634 * For bytes limits, the rate will be this value * the unit from ir_units. 3635 * (Resolution error is up to 1%). 3636 * Access: RW 3637 */ 3638 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3639 3640 /* reg_qpcr_eir 3641 * Policer's exceed rate. 3642 * The higher rate for double rate, reserved for single rate. 3643 * Lower rate for double rate policer. 3644 * For bytes limits, the rate will be this value * the unit from ir_units. 3645 * (Resolution error is up to 1%). 3646 * Access: RW 3647 */ 3648 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3649 3650 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3651 3652 /* reg_qpcr_exceed_action. 3653 * What to do with packets between the 2 limits for double rate. 3654 * Access: RW for unbounded policer. RO for bounded policer. 3655 */ 3656 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3657 3658 enum mlxsw_reg_qpcr_action { 3659 /* Discard */ 3660 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3661 /* Forward and set color to red. 3662 * If the packet is intended to cpu port, it will be dropped. 3663 */ 3664 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3665 }; 3666 3667 /* reg_qpcr_violate_action 3668 * What to do with packets that cross the cir limit (for single rate) or the eir 3669 * limit (for double rate). 3670 * Access: RW for unbounded policer. RO for bounded policer. 3671 */ 3672 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3673 3674 /* reg_qpcr_violate_count 3675 * Counts the number of times violate_action happened on this PID. 3676 * Access: RW 3677 */ 3678 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3679 3680 /* Packets */ 3681 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3682 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3683 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3684 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3685 3686 /* Bandwidth */ 3687 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3688 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3689 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3690 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3691 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3692 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3693 3694 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3695 enum mlxsw_reg_qpcr_ir_units ir_units, 3696 bool bytes, u32 cir, u16 cbs) 3697 { 3698 MLXSW_REG_ZERO(qpcr, payload); 3699 mlxsw_reg_qpcr_pid_set(payload, pid); 3700 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3701 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3702 mlxsw_reg_qpcr_violate_action_set(payload, 3703 MLXSW_REG_QPCR_ACTION_DISCARD); 3704 mlxsw_reg_qpcr_cir_set(payload, cir); 3705 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3706 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3707 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3708 } 3709 3710 /* QTCT - QoS Switch Traffic Class Table 3711 * ------------------------------------- 3712 * Configures the mapping between the packet switch priority and the 3713 * traffic class on the transmit port. 3714 */ 3715 #define MLXSW_REG_QTCT_ID 0x400A 3716 #define MLXSW_REG_QTCT_LEN 0x08 3717 3718 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3719 3720 /* reg_qtct_local_port 3721 * Local port number. 3722 * Access: Index 3723 * 3724 * Note: CPU port is not supported. 3725 */ 3726 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3727 3728 /* reg_qtct_sub_port 3729 * Virtual port within the physical port. 3730 * Should be set to 0 when virtual ports are not enabled on the port. 3731 * Access: Index 3732 */ 3733 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3734 3735 /* reg_qtct_switch_prio 3736 * Switch priority. 3737 * Access: Index 3738 */ 3739 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3740 3741 /* reg_qtct_tclass 3742 * Traffic class. 3743 * Default values: 3744 * switch_prio 0 : tclass 1 3745 * switch_prio 1 : tclass 0 3746 * switch_prio i : tclass i, for i > 1 3747 * Access: RW 3748 */ 3749 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3750 3751 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3752 u8 switch_prio, u8 tclass) 3753 { 3754 MLXSW_REG_ZERO(qtct, payload); 3755 mlxsw_reg_qtct_local_port_set(payload, local_port); 3756 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3757 mlxsw_reg_qtct_tclass_set(payload, tclass); 3758 } 3759 3760 /* QEEC - QoS ETS Element Configuration Register 3761 * --------------------------------------------- 3762 * Configures the ETS elements. 3763 */ 3764 #define MLXSW_REG_QEEC_ID 0x400D 3765 #define MLXSW_REG_QEEC_LEN 0x20 3766 3767 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3768 3769 /* reg_qeec_local_port 3770 * Local port number. 3771 * Access: Index 3772 * 3773 * Note: CPU port is supported. 3774 */ 3775 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 3776 3777 enum mlxsw_reg_qeec_hr { 3778 MLXSW_REG_QEEC_HR_PORT, 3779 MLXSW_REG_QEEC_HR_GROUP, 3780 MLXSW_REG_QEEC_HR_SUBGROUP, 3781 MLXSW_REG_QEEC_HR_TC, 3782 }; 3783 3784 /* reg_qeec_element_hierarchy 3785 * 0 - Port 3786 * 1 - Group 3787 * 2 - Subgroup 3788 * 3 - Traffic Class 3789 * Access: Index 3790 */ 3791 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3792 3793 /* reg_qeec_element_index 3794 * The index of the element in the hierarchy. 3795 * Access: Index 3796 */ 3797 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3798 3799 /* reg_qeec_next_element_index 3800 * The index of the next (lower) element in the hierarchy. 3801 * Access: RW 3802 * 3803 * Note: Reserved for element_hierarchy 0. 3804 */ 3805 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3806 3807 /* reg_qeec_mise 3808 * Min shaper configuration enable. Enables configuration of the min 3809 * shaper on this ETS element 3810 * 0 - Disable 3811 * 1 - Enable 3812 * Access: RW 3813 */ 3814 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3815 3816 /* reg_qeec_ptps 3817 * PTP shaper 3818 * 0: regular shaper mode 3819 * 1: PTP oriented shaper 3820 * Allowed only for hierarchy 0 3821 * Not supported for CPU port 3822 * Note that ptps mode may affect the shaper rates of all hierarchies 3823 * Supported only on Spectrum-1 3824 * Access: RW 3825 */ 3826 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3827 3828 enum { 3829 MLXSW_REG_QEEC_BYTES_MODE, 3830 MLXSW_REG_QEEC_PACKETS_MODE, 3831 }; 3832 3833 /* reg_qeec_pb 3834 * Packets or bytes mode. 3835 * 0 - Bytes mode 3836 * 1 - Packets mode 3837 * Access: RW 3838 * 3839 * Note: Used for max shaper configuration. For Spectrum, packets mode 3840 * is supported only for traffic classes of CPU port. 3841 */ 3842 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3843 3844 /* The smallest permitted min shaper rate. */ 3845 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3846 3847 /* reg_qeec_min_shaper_rate 3848 * Min shaper information rate. 3849 * For CPU port, can only be configured for port hierarchy. 3850 * When in bytes mode, value is specified in units of 1000bps. 3851 * Access: RW 3852 */ 3853 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3854 3855 /* reg_qeec_mase 3856 * Max shaper configuration enable. Enables configuration of the max 3857 * shaper on this ETS element. 3858 * 0 - Disable 3859 * 1 - Enable 3860 * Access: RW 3861 */ 3862 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3863 3864 /* The largest max shaper value possible to disable the shaper. */ 3865 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3866 3867 /* reg_qeec_max_shaper_rate 3868 * Max shaper information rate. 3869 * For CPU port, can only be configured for port hierarchy. 3870 * When in bytes mode, value is specified in units of 1000bps. 3871 * Access: RW 3872 */ 3873 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3874 3875 /* reg_qeec_de 3876 * DWRR configuration enable. Enables configuration of the dwrr and 3877 * dwrr_weight. 3878 * 0 - Disable 3879 * 1 - Enable 3880 * Access: RW 3881 */ 3882 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3883 3884 /* reg_qeec_dwrr 3885 * Transmission selection algorithm to use on the link going down from 3886 * the ETS element. 3887 * 0 - Strict priority 3888 * 1 - DWRR 3889 * Access: RW 3890 */ 3891 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3892 3893 /* reg_qeec_dwrr_weight 3894 * DWRR weight on the link going down from the ETS element. The 3895 * percentage of bandwidth guaranteed to an ETS element within 3896 * its hierarchy. The sum of all weights across all ETS elements 3897 * within one hierarchy should be equal to 100. Reserved when 3898 * transmission selection algorithm is strict priority. 3899 * Access: RW 3900 */ 3901 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3902 3903 /* reg_qeec_max_shaper_bs 3904 * Max shaper burst size 3905 * Burst size is 2^max_shaper_bs * 512 bits 3906 * For Spectrum-1: Range is: 5..25 3907 * For Spectrum-2: Range is: 11..25 3908 * Reserved when ptps = 1 3909 * Access: RW 3910 */ 3911 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3912 3913 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3914 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3915 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3916 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 3917 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 3918 3919 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 3920 enum mlxsw_reg_qeec_hr hr, u8 index, 3921 u8 next_index) 3922 { 3923 MLXSW_REG_ZERO(qeec, payload); 3924 mlxsw_reg_qeec_local_port_set(payload, local_port); 3925 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3926 mlxsw_reg_qeec_element_index_set(payload, index); 3927 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3928 } 3929 3930 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 3931 bool ptps) 3932 { 3933 MLXSW_REG_ZERO(qeec, payload); 3934 mlxsw_reg_qeec_local_port_set(payload, local_port); 3935 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3936 mlxsw_reg_qeec_ptps_set(payload, ptps); 3937 } 3938 3939 /* QRWE - QoS ReWrite Enable 3940 * ------------------------- 3941 * This register configures the rewrite enable per receive port. 3942 */ 3943 #define MLXSW_REG_QRWE_ID 0x400F 3944 #define MLXSW_REG_QRWE_LEN 0x08 3945 3946 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3947 3948 /* reg_qrwe_local_port 3949 * Local port number. 3950 * Access: Index 3951 * 3952 * Note: CPU port is supported. No support for router port. 3953 */ 3954 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 3955 3956 /* reg_qrwe_dscp 3957 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3958 * Access: RW 3959 */ 3960 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3961 3962 /* reg_qrwe_pcp 3963 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3964 * Access: RW 3965 */ 3966 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3967 3968 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 3969 bool rewrite_pcp, bool rewrite_dscp) 3970 { 3971 MLXSW_REG_ZERO(qrwe, payload); 3972 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3973 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3974 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3975 } 3976 3977 /* QPDSM - QoS Priority to DSCP Mapping 3978 * ------------------------------------ 3979 * QoS Priority to DSCP Mapping Register 3980 */ 3981 #define MLXSW_REG_QPDSM_ID 0x4011 3982 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3983 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3984 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3985 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3986 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3987 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3988 3989 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3990 3991 /* reg_qpdsm_local_port 3992 * Local Port. Supported for data packets from CPU port. 3993 * Access: Index 3994 */ 3995 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 3996 3997 /* reg_qpdsm_prio_entry_color0_e 3998 * Enable update of the entry for color 0 and a given port. 3999 * Access: WO 4000 */ 4001 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4002 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4003 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4004 4005 /* reg_qpdsm_prio_entry_color0_dscp 4006 * DSCP field in the outer label of the packet for color 0 and a given port. 4007 * Reserved when e=0. 4008 * Access: RW 4009 */ 4010 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4011 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4012 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4013 4014 /* reg_qpdsm_prio_entry_color1_e 4015 * Enable update of the entry for color 1 and a given port. 4016 * Access: WO 4017 */ 4018 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4019 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4020 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4021 4022 /* reg_qpdsm_prio_entry_color1_dscp 4023 * DSCP field in the outer label of the packet for color 1 and a given port. 4024 * Reserved when e=0. 4025 * Access: RW 4026 */ 4027 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4028 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4029 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4030 4031 /* reg_qpdsm_prio_entry_color2_e 4032 * Enable update of the entry for color 2 and a given port. 4033 * Access: WO 4034 */ 4035 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4036 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4037 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4038 4039 /* reg_qpdsm_prio_entry_color2_dscp 4040 * DSCP field in the outer label of the packet for color 2 and a given port. 4041 * Reserved when e=0. 4042 * Access: RW 4043 */ 4044 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4045 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4046 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4047 4048 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4049 { 4050 MLXSW_REG_ZERO(qpdsm, payload); 4051 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4052 } 4053 4054 static inline void 4055 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4056 { 4057 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4058 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4059 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4060 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4061 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4062 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4063 } 4064 4065 /* QPDP - QoS Port DSCP to Priority Mapping Register 4066 * ------------------------------------------------- 4067 * This register controls the port default Switch Priority and Color. The 4068 * default Switch Priority and Color are used for frames where the trust state 4069 * uses default values. All member ports of a LAG should be configured with the 4070 * same default values. 4071 */ 4072 #define MLXSW_REG_QPDP_ID 0x4007 4073 #define MLXSW_REG_QPDP_LEN 0x8 4074 4075 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4076 4077 /* reg_qpdp_local_port 4078 * Local Port. Supported for data packets from CPU port. 4079 * Access: Index 4080 */ 4081 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4082 4083 /* reg_qpdp_switch_prio 4084 * Default port Switch Priority (default 0) 4085 * Access: RW 4086 */ 4087 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4088 4089 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4090 u8 switch_prio) 4091 { 4092 MLXSW_REG_ZERO(qpdp, payload); 4093 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4094 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4095 } 4096 4097 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4098 * -------------------------------------------------- 4099 * This register controls the mapping from DSCP field to 4100 * Switch Priority for IP packets. 4101 */ 4102 #define MLXSW_REG_QPDPM_ID 0x4013 4103 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4104 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4105 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4106 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4107 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4108 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4109 4110 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4111 4112 /* reg_qpdpm_local_port 4113 * Local Port. Supported for data packets from CPU port. 4114 * Access: Index 4115 */ 4116 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4117 4118 /* reg_qpdpm_dscp_e 4119 * Enable update of the specific entry. When cleared, the switch_prio and color 4120 * fields are ignored and the previous switch_prio and color values are 4121 * preserved. 4122 * Access: WO 4123 */ 4124 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4125 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4126 4127 /* reg_qpdpm_dscp_prio 4128 * The new Switch Priority value for the relevant DSCP value. 4129 * Access: RW 4130 */ 4131 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4132 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4133 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4134 4135 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4136 { 4137 MLXSW_REG_ZERO(qpdpm, payload); 4138 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4139 } 4140 4141 static inline void 4142 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4143 { 4144 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4145 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4146 } 4147 4148 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4149 * ------------------------------------------------------------------ 4150 * This register configures if the Switch Priority to Traffic Class mapping is 4151 * based on Multicast packet indication. If so, then multicast packets will get 4152 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4153 * QTCT. 4154 * By default, Switch Priority to Traffic Class mapping is not based on 4155 * Multicast packet indication. 4156 */ 4157 #define MLXSW_REG_QTCTM_ID 0x401A 4158 #define MLXSW_REG_QTCTM_LEN 0x08 4159 4160 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4161 4162 /* reg_qtctm_local_port 4163 * Local port number. 4164 * No support for CPU port. 4165 * Access: Index 4166 */ 4167 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4168 4169 /* reg_qtctm_mc 4170 * Multicast Mode 4171 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4172 * indication (default is 0, not based on Multicast packet indication). 4173 */ 4174 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4175 4176 static inline void 4177 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4178 { 4179 MLXSW_REG_ZERO(qtctm, payload); 4180 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4181 mlxsw_reg_qtctm_mc_set(payload, mc); 4182 } 4183 4184 /* QPSC - QoS PTP Shaper Configuration Register 4185 * -------------------------------------------- 4186 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4187 * Supported only on Spectrum-1. 4188 */ 4189 #define MLXSW_REG_QPSC_ID 0x401B 4190 #define MLXSW_REG_QPSC_LEN 0x28 4191 4192 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4193 4194 enum mlxsw_reg_qpsc_port_speed { 4195 MLXSW_REG_QPSC_PORT_SPEED_100M, 4196 MLXSW_REG_QPSC_PORT_SPEED_1G, 4197 MLXSW_REG_QPSC_PORT_SPEED_10G, 4198 MLXSW_REG_QPSC_PORT_SPEED_25G, 4199 }; 4200 4201 /* reg_qpsc_port_speed 4202 * Port speed. 4203 * Access: Index 4204 */ 4205 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4206 4207 /* reg_qpsc_shaper_time_exp 4208 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4209 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4210 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4211 * Access: RW 4212 */ 4213 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4214 4215 /* reg_qpsc_shaper_time_mantissa 4216 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4217 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4218 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4219 * Access: RW 4220 */ 4221 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4222 4223 /* reg_qpsc_shaper_inc 4224 * Number of tokens added to shaper on each update. 4225 * Units of 8B. 4226 * Access: RW 4227 */ 4228 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4229 4230 /* reg_qpsc_shaper_bs 4231 * Max shaper Burst size. 4232 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4233 * Range is: 5..25 (from 2KB..2GB) 4234 * Access: RW 4235 */ 4236 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4237 4238 /* reg_qpsc_ptsc_we 4239 * Write enable to port_to_shaper_credits. 4240 * Access: WO 4241 */ 4242 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4243 4244 /* reg_qpsc_port_to_shaper_credits 4245 * For split ports: range 1..57 4246 * For non-split ports: range 1..112 4247 * Written only when ptsc_we is set. 4248 * Access: RW 4249 */ 4250 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4251 4252 /* reg_qpsc_ing_timestamp_inc 4253 * Ingress timestamp increment. 4254 * 2's complement. 4255 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4256 * value for all ports. 4257 * Same units as used by MTPPTR. 4258 * Access: RW 4259 */ 4260 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4261 4262 /* reg_qpsc_egr_timestamp_inc 4263 * Egress timestamp increment. 4264 * 2's complement. 4265 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4266 * value for all ports. 4267 * Same units as used by MTPPTR. 4268 * Access: RW 4269 */ 4270 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4271 4272 static inline void 4273 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4274 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4275 u8 shaper_bs, u8 port_to_shaper_credits, 4276 int ing_timestamp_inc, int egr_timestamp_inc) 4277 { 4278 MLXSW_REG_ZERO(qpsc, payload); 4279 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4280 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4281 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4282 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4283 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4284 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4285 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4286 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4287 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4288 } 4289 4290 /* PMLP - Ports Module to Local Port Register 4291 * ------------------------------------------ 4292 * Configures the assignment of modules to local ports. 4293 */ 4294 #define MLXSW_REG_PMLP_ID 0x5002 4295 #define MLXSW_REG_PMLP_LEN 0x40 4296 4297 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4298 4299 /* reg_pmlp_rxtx 4300 * 0 - Tx value is used for both Tx and Rx. 4301 * 1 - Rx value is taken from a separte field. 4302 * Access: RW 4303 */ 4304 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4305 4306 /* reg_pmlp_local_port 4307 * Local port number. 4308 * Access: Index 4309 */ 4310 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4311 4312 /* reg_pmlp_width 4313 * 0 - Unmap local port. 4314 * 1 - Lane 0 is used. 4315 * 2 - Lanes 0 and 1 are used. 4316 * 4 - Lanes 0, 1, 2 and 3 are used. 4317 * 8 - Lanes 0-7 are used. 4318 * Access: RW 4319 */ 4320 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4321 4322 /* reg_pmlp_module 4323 * Module number. 4324 * Access: RW 4325 */ 4326 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4327 4328 /* reg_pmlp_tx_lane 4329 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4330 * Access: RW 4331 */ 4332 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4333 4334 /* reg_pmlp_rx_lane 4335 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4336 * equal to Tx lane. 4337 * Access: RW 4338 */ 4339 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4340 4341 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4342 { 4343 MLXSW_REG_ZERO(pmlp, payload); 4344 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4345 } 4346 4347 /* PMTU - Port MTU Register 4348 * ------------------------ 4349 * Configures and reports the port MTU. 4350 */ 4351 #define MLXSW_REG_PMTU_ID 0x5003 4352 #define MLXSW_REG_PMTU_LEN 0x10 4353 4354 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4355 4356 /* reg_pmtu_local_port 4357 * Local port number. 4358 * Access: Index 4359 */ 4360 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4361 4362 /* reg_pmtu_max_mtu 4363 * Maximum MTU. 4364 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4365 * reported, otherwise the minimum between the max_mtu of the different 4366 * types is reported. 4367 * Access: RO 4368 */ 4369 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4370 4371 /* reg_pmtu_admin_mtu 4372 * MTU value to set port to. Must be smaller or equal to max_mtu. 4373 * Note: If port type is Infiniband, then port must be disabled, when its 4374 * MTU is set. 4375 * Access: RW 4376 */ 4377 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4378 4379 /* reg_pmtu_oper_mtu 4380 * The actual MTU configured on the port. Packets exceeding this size 4381 * will be dropped. 4382 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4383 * oper_mtu might be smaller than admin_mtu. 4384 * Access: RO 4385 */ 4386 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4387 4388 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4389 u16 new_mtu) 4390 { 4391 MLXSW_REG_ZERO(pmtu, payload); 4392 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4393 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4394 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4395 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4396 } 4397 4398 /* PTYS - Port Type and Speed Register 4399 * ----------------------------------- 4400 * Configures and reports the port speed type. 4401 * 4402 * Note: When set while the link is up, the changes will not take effect 4403 * until the port transitions from down to up state. 4404 */ 4405 #define MLXSW_REG_PTYS_ID 0x5004 4406 #define MLXSW_REG_PTYS_LEN 0x40 4407 4408 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4409 4410 /* an_disable_admin 4411 * Auto negotiation disable administrative configuration 4412 * 0 - Device doesn't support AN disable. 4413 * 1 - Device supports AN disable. 4414 * Access: RW 4415 */ 4416 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4417 4418 /* reg_ptys_local_port 4419 * Local port number. 4420 * Access: Index 4421 */ 4422 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4423 4424 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4425 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4426 4427 /* reg_ptys_proto_mask 4428 * Protocol mask. Indicates which protocol is used. 4429 * 0 - Infiniband. 4430 * 1 - Fibre Channel. 4431 * 2 - Ethernet. 4432 * Access: Index 4433 */ 4434 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4435 4436 enum { 4437 MLXSW_REG_PTYS_AN_STATUS_NA, 4438 MLXSW_REG_PTYS_AN_STATUS_OK, 4439 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4440 }; 4441 4442 /* reg_ptys_an_status 4443 * Autonegotiation status. 4444 * Access: RO 4445 */ 4446 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4447 4448 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4449 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4450 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4451 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4452 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4453 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4454 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4455 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4456 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4457 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4458 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4459 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4460 4461 /* reg_ptys_ext_eth_proto_cap 4462 * Extended Ethernet port supported speeds and protocols. 4463 * Access: RO 4464 */ 4465 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4466 4467 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4468 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4469 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4470 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4471 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4472 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4473 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4474 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4475 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4476 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4477 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4478 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4479 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4480 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4481 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4482 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4483 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4484 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4485 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4486 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4487 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4488 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4489 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4490 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4491 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4492 4493 /* reg_ptys_eth_proto_cap 4494 * Ethernet port supported speeds and protocols. 4495 * Access: RO 4496 */ 4497 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4498 4499 /* reg_ptys_ib_link_width_cap 4500 * IB port supported widths. 4501 * Access: RO 4502 */ 4503 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4504 4505 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4506 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4507 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4508 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4509 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4510 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4511 4512 /* reg_ptys_ib_proto_cap 4513 * IB port supported speeds and protocols. 4514 * Access: RO 4515 */ 4516 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4517 4518 /* reg_ptys_ext_eth_proto_admin 4519 * Extended speed and protocol to set port to. 4520 * Access: RW 4521 */ 4522 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4523 4524 /* reg_ptys_eth_proto_admin 4525 * Speed and protocol to set port to. 4526 * Access: RW 4527 */ 4528 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4529 4530 /* reg_ptys_ib_link_width_admin 4531 * IB width to set port to. 4532 * Access: RW 4533 */ 4534 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4535 4536 /* reg_ptys_ib_proto_admin 4537 * IB speeds and protocols to set port to. 4538 * Access: RW 4539 */ 4540 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4541 4542 /* reg_ptys_ext_eth_proto_oper 4543 * The extended current speed and protocol configured for the port. 4544 * Access: RO 4545 */ 4546 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4547 4548 /* reg_ptys_eth_proto_oper 4549 * The current speed and protocol configured for the port. 4550 * Access: RO 4551 */ 4552 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4553 4554 /* reg_ptys_ib_link_width_oper 4555 * The current IB width to set port to. 4556 * Access: RO 4557 */ 4558 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4559 4560 /* reg_ptys_ib_proto_oper 4561 * The current IB speed and protocol. 4562 * Access: RO 4563 */ 4564 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4565 4566 enum mlxsw_reg_ptys_connector_type { 4567 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4568 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4569 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4570 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4571 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4572 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4573 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4574 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4575 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4576 }; 4577 4578 /* reg_ptys_connector_type 4579 * Connector type indication. 4580 * Access: RO 4581 */ 4582 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4583 4584 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4585 u32 proto_admin, bool autoneg) 4586 { 4587 MLXSW_REG_ZERO(ptys, payload); 4588 mlxsw_reg_ptys_local_port_set(payload, local_port); 4589 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4590 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4591 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4592 } 4593 4594 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4595 u32 proto_admin, bool autoneg) 4596 { 4597 MLXSW_REG_ZERO(ptys, payload); 4598 mlxsw_reg_ptys_local_port_set(payload, local_port); 4599 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4600 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4601 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4602 } 4603 4604 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4605 u32 *p_eth_proto_cap, 4606 u32 *p_eth_proto_admin, 4607 u32 *p_eth_proto_oper) 4608 { 4609 if (p_eth_proto_cap) 4610 *p_eth_proto_cap = 4611 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4612 if (p_eth_proto_admin) 4613 *p_eth_proto_admin = 4614 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4615 if (p_eth_proto_oper) 4616 *p_eth_proto_oper = 4617 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4618 } 4619 4620 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4621 u32 *p_eth_proto_cap, 4622 u32 *p_eth_proto_admin, 4623 u32 *p_eth_proto_oper) 4624 { 4625 if (p_eth_proto_cap) 4626 *p_eth_proto_cap = 4627 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4628 if (p_eth_proto_admin) 4629 *p_eth_proto_admin = 4630 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4631 if (p_eth_proto_oper) 4632 *p_eth_proto_oper = 4633 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4634 } 4635 4636 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port, 4637 u16 proto_admin, u16 link_width) 4638 { 4639 MLXSW_REG_ZERO(ptys, payload); 4640 mlxsw_reg_ptys_local_port_set(payload, local_port); 4641 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4642 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4643 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4644 } 4645 4646 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4647 u16 *p_ib_link_width_cap, 4648 u16 *p_ib_proto_oper, 4649 u16 *p_ib_link_width_oper) 4650 { 4651 if (p_ib_proto_cap) 4652 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4653 if (p_ib_link_width_cap) 4654 *p_ib_link_width_cap = 4655 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4656 if (p_ib_proto_oper) 4657 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4658 if (p_ib_link_width_oper) 4659 *p_ib_link_width_oper = 4660 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4661 } 4662 4663 /* PPAD - Port Physical Address Register 4664 * ------------------------------------- 4665 * The PPAD register configures the per port physical MAC address. 4666 */ 4667 #define MLXSW_REG_PPAD_ID 0x5005 4668 #define MLXSW_REG_PPAD_LEN 0x10 4669 4670 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4671 4672 /* reg_ppad_single_base_mac 4673 * 0: base_mac, local port should be 0 and mac[7:0] is 4674 * reserved. HW will set incremental 4675 * 1: single_mac - mac of the local_port 4676 * Access: RW 4677 */ 4678 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4679 4680 /* reg_ppad_local_port 4681 * port number, if single_base_mac = 0 then local_port is reserved 4682 * Access: RW 4683 */ 4684 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4685 4686 /* reg_ppad_mac 4687 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4688 * If single_base_mac = 1 - the per port MAC address 4689 * Access: RW 4690 */ 4691 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4692 4693 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4694 u16 local_port) 4695 { 4696 MLXSW_REG_ZERO(ppad, payload); 4697 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4698 mlxsw_reg_ppad_local_port_set(payload, local_port); 4699 } 4700 4701 /* PAOS - Ports Administrative and Operational Status Register 4702 * ----------------------------------------------------------- 4703 * Configures and retrieves per port administrative and operational status. 4704 */ 4705 #define MLXSW_REG_PAOS_ID 0x5006 4706 #define MLXSW_REG_PAOS_LEN 0x10 4707 4708 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4709 4710 /* reg_paos_swid 4711 * Switch partition ID with which to associate the port. 4712 * Note: while external ports uses unique local port numbers (and thus swid is 4713 * redundant), router ports use the same local port number where swid is the 4714 * only indication for the relevant port. 4715 * Access: Index 4716 */ 4717 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4718 4719 /* reg_paos_local_port 4720 * Local port number. 4721 * Access: Index 4722 */ 4723 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4724 4725 /* reg_paos_admin_status 4726 * Port administrative state (the desired state of the port): 4727 * 1 - Up. 4728 * 2 - Down. 4729 * 3 - Up once. This means that in case of link failure, the port won't go 4730 * into polling mode, but will wait to be re-enabled by software. 4731 * 4 - Disabled by system. Can only be set by hardware. 4732 * Access: RW 4733 */ 4734 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4735 4736 /* reg_paos_oper_status 4737 * Port operational state (the current state): 4738 * 1 - Up. 4739 * 2 - Down. 4740 * 3 - Down by port failure. This means that the device will not let the 4741 * port up again until explicitly specified by software. 4742 * Access: RO 4743 */ 4744 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4745 4746 /* reg_paos_ase 4747 * Admin state update enabled. 4748 * Access: WO 4749 */ 4750 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4751 4752 /* reg_paos_ee 4753 * Event update enable. If this bit is set, event generation will be 4754 * updated based on the e field. 4755 * Access: WO 4756 */ 4757 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4758 4759 /* reg_paos_e 4760 * Event generation on operational state change: 4761 * 0 - Do not generate event. 4762 * 1 - Generate Event. 4763 * 2 - Generate Single Event. 4764 * Access: RW 4765 */ 4766 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4767 4768 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4769 enum mlxsw_port_admin_status status) 4770 { 4771 MLXSW_REG_ZERO(paos, payload); 4772 mlxsw_reg_paos_swid_set(payload, 0); 4773 mlxsw_reg_paos_local_port_set(payload, local_port); 4774 mlxsw_reg_paos_admin_status_set(payload, status); 4775 mlxsw_reg_paos_oper_status_set(payload, 0); 4776 mlxsw_reg_paos_ase_set(payload, 1); 4777 mlxsw_reg_paos_ee_set(payload, 1); 4778 mlxsw_reg_paos_e_set(payload, 1); 4779 } 4780 4781 /* PFCC - Ports Flow Control Configuration Register 4782 * ------------------------------------------------ 4783 * Configures and retrieves the per port flow control configuration. 4784 */ 4785 #define MLXSW_REG_PFCC_ID 0x5007 4786 #define MLXSW_REG_PFCC_LEN 0x20 4787 4788 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4789 4790 /* reg_pfcc_local_port 4791 * Local port number. 4792 * Access: Index 4793 */ 4794 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 4795 4796 /* reg_pfcc_pnat 4797 * Port number access type. Determines the way local_port is interpreted: 4798 * 0 - Local port number. 4799 * 1 - IB / label port number. 4800 * Access: Index 4801 */ 4802 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4803 4804 /* reg_pfcc_shl_cap 4805 * Send to higher layers capabilities: 4806 * 0 - No capability of sending Pause and PFC frames to higher layers. 4807 * 1 - Device has capability of sending Pause and PFC frames to higher 4808 * layers. 4809 * Access: RO 4810 */ 4811 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4812 4813 /* reg_pfcc_shl_opr 4814 * Send to higher layers operation: 4815 * 0 - Pause and PFC frames are handled by the port (default). 4816 * 1 - Pause and PFC frames are handled by the port and also sent to 4817 * higher layers. Only valid if shl_cap = 1. 4818 * Access: RW 4819 */ 4820 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4821 4822 /* reg_pfcc_ppan 4823 * Pause policy auto negotiation. 4824 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4825 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4826 * based on the auto-negotiation resolution. 4827 * Access: RW 4828 * 4829 * Note: The auto-negotiation advertisement is set according to pptx and 4830 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4831 */ 4832 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4833 4834 /* reg_pfcc_prio_mask_tx 4835 * Bit per priority indicating if Tx flow control policy should be 4836 * updated based on bit pfctx. 4837 * Access: WO 4838 */ 4839 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4840 4841 /* reg_pfcc_prio_mask_rx 4842 * Bit per priority indicating if Rx flow control policy should be 4843 * updated based on bit pfcrx. 4844 * Access: WO 4845 */ 4846 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4847 4848 /* reg_pfcc_pptx 4849 * Admin Pause policy on Tx. 4850 * 0 - Never generate Pause frames (default). 4851 * 1 - Generate Pause frames according to Rx buffer threshold. 4852 * Access: RW 4853 */ 4854 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4855 4856 /* reg_pfcc_aptx 4857 * Active (operational) Pause policy on Tx. 4858 * 0 - Never generate Pause frames. 4859 * 1 - Generate Pause frames according to Rx buffer threshold. 4860 * Access: RO 4861 */ 4862 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4863 4864 /* reg_pfcc_pfctx 4865 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4866 * 0 - Never generate priority Pause frames on the specified priority 4867 * (default). 4868 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4869 * the specified priority. 4870 * Access: RW 4871 * 4872 * Note: pfctx and pptx must be mutually exclusive. 4873 */ 4874 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4875 4876 /* reg_pfcc_pprx 4877 * Admin Pause policy on Rx. 4878 * 0 - Ignore received Pause frames (default). 4879 * 1 - Respect received Pause frames. 4880 * Access: RW 4881 */ 4882 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4883 4884 /* reg_pfcc_aprx 4885 * Active (operational) Pause policy on Rx. 4886 * 0 - Ignore received Pause frames. 4887 * 1 - Respect received Pause frames. 4888 * Access: RO 4889 */ 4890 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4891 4892 /* reg_pfcc_pfcrx 4893 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4894 * 0 - Ignore incoming priority Pause frames on the specified priority 4895 * (default). 4896 * 1 - Respect incoming priority Pause frames on the specified priority. 4897 * Access: RW 4898 */ 4899 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4900 4901 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4902 4903 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4904 { 4905 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4906 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4907 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4908 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4909 } 4910 4911 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 4912 { 4913 MLXSW_REG_ZERO(pfcc, payload); 4914 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4915 } 4916 4917 /* PPCNT - Ports Performance Counters Register 4918 * ------------------------------------------- 4919 * The PPCNT register retrieves per port performance counters. 4920 */ 4921 #define MLXSW_REG_PPCNT_ID 0x5008 4922 #define MLXSW_REG_PPCNT_LEN 0x100 4923 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4924 4925 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4926 4927 /* reg_ppcnt_swid 4928 * For HCA: must be always 0. 4929 * Switch partition ID to associate port with. 4930 * Switch partitions are numbered from 0 to 7 inclusively. 4931 * Switch partition 254 indicates stacking ports. 4932 * Switch partition 255 indicates all switch partitions. 4933 * Only valid on Set() operation with local_port=255. 4934 * Access: Index 4935 */ 4936 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4937 4938 /* reg_ppcnt_local_port 4939 * Local port number. 4940 * Access: Index 4941 */ 4942 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 4943 4944 /* reg_ppcnt_pnat 4945 * Port number access type: 4946 * 0 - Local port number 4947 * 1 - IB port number 4948 * Access: Index 4949 */ 4950 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4951 4952 enum mlxsw_reg_ppcnt_grp { 4953 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4954 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4955 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4956 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4957 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4958 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4959 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4960 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4961 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 4962 }; 4963 4964 /* reg_ppcnt_grp 4965 * Performance counter group. 4966 * Group 63 indicates all groups. Only valid on Set() operation with 4967 * clr bit set. 4968 * 0x0: IEEE 802.3 Counters 4969 * 0x1: RFC 2863 Counters 4970 * 0x2: RFC 2819 Counters 4971 * 0x3: RFC 3635 Counters 4972 * 0x5: Ethernet Extended Counters 4973 * 0x6: Ethernet Discard Counters 4974 * 0x8: Link Level Retransmission Counters 4975 * 0x10: Per Priority Counters 4976 * 0x11: Per Traffic Class Counters 4977 * 0x12: Physical Layer Counters 4978 * 0x13: Per Traffic Class Congestion Counters 4979 * Access: Index 4980 */ 4981 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4982 4983 /* reg_ppcnt_clr 4984 * Clear counters. Setting the clr bit will reset the counter value 4985 * for all counters in the counter group. This bit can be set 4986 * for both Set() and Get() operation. 4987 * Access: OP 4988 */ 4989 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4990 4991 /* reg_ppcnt_lp_gl 4992 * Local port global variable. 4993 * 0: local_port 255 = all ports of the device. 4994 * 1: local_port indicates local port number for all ports. 4995 * Access: OP 4996 */ 4997 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 4998 4999 /* reg_ppcnt_prio_tc 5000 * Priority for counter set that support per priority, valid values: 0-7. 5001 * Traffic class for counter set that support per traffic class, 5002 * valid values: 0- cap_max_tclass-1 . 5003 * For HCA: cap_max_tclass is always 8. 5004 * Otherwise must be 0. 5005 * Access: Index 5006 */ 5007 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5008 5009 /* Ethernet IEEE 802.3 Counter Group */ 5010 5011 /* reg_ppcnt_a_frames_transmitted_ok 5012 * Access: RO 5013 */ 5014 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5015 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5016 5017 /* reg_ppcnt_a_frames_received_ok 5018 * Access: RO 5019 */ 5020 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5021 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5022 5023 /* reg_ppcnt_a_frame_check_sequence_errors 5024 * Access: RO 5025 */ 5026 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5027 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5028 5029 /* reg_ppcnt_a_alignment_errors 5030 * Access: RO 5031 */ 5032 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5033 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5034 5035 /* reg_ppcnt_a_octets_transmitted_ok 5036 * Access: RO 5037 */ 5038 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5039 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5040 5041 /* reg_ppcnt_a_octets_received_ok 5042 * Access: RO 5043 */ 5044 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5045 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5046 5047 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5048 * Access: RO 5049 */ 5050 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5051 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5052 5053 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5054 * Access: RO 5055 */ 5056 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5057 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5058 5059 /* reg_ppcnt_a_multicast_frames_received_ok 5060 * Access: RO 5061 */ 5062 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5063 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5064 5065 /* reg_ppcnt_a_broadcast_frames_received_ok 5066 * Access: RO 5067 */ 5068 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5069 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5070 5071 /* reg_ppcnt_a_in_range_length_errors 5072 * Access: RO 5073 */ 5074 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5075 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5076 5077 /* reg_ppcnt_a_out_of_range_length_field 5078 * Access: RO 5079 */ 5080 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5081 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5082 5083 /* reg_ppcnt_a_frame_too_long_errors 5084 * Access: RO 5085 */ 5086 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5087 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5088 5089 /* reg_ppcnt_a_symbol_error_during_carrier 5090 * Access: RO 5091 */ 5092 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5093 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5094 5095 /* reg_ppcnt_a_mac_control_frames_transmitted 5096 * Access: RO 5097 */ 5098 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5099 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5100 5101 /* reg_ppcnt_a_mac_control_frames_received 5102 * Access: RO 5103 */ 5104 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5105 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5106 5107 /* reg_ppcnt_a_unsupported_opcodes_received 5108 * Access: RO 5109 */ 5110 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5111 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5112 5113 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5114 * Access: RO 5115 */ 5116 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5117 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5118 5119 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5120 * Access: RO 5121 */ 5122 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5123 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5124 5125 /* Ethernet RFC 2863 Counter Group */ 5126 5127 /* reg_ppcnt_if_in_discards 5128 * Access: RO 5129 */ 5130 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5131 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5132 5133 /* reg_ppcnt_if_out_discards 5134 * Access: RO 5135 */ 5136 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5137 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5138 5139 /* reg_ppcnt_if_out_errors 5140 * Access: RO 5141 */ 5142 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5143 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5144 5145 /* Ethernet RFC 2819 Counter Group */ 5146 5147 /* reg_ppcnt_ether_stats_undersize_pkts 5148 * Access: RO 5149 */ 5150 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5151 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5152 5153 /* reg_ppcnt_ether_stats_oversize_pkts 5154 * Access: RO 5155 */ 5156 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5157 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5158 5159 /* reg_ppcnt_ether_stats_fragments 5160 * Access: RO 5161 */ 5162 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5163 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5164 5165 /* reg_ppcnt_ether_stats_pkts64octets 5166 * Access: RO 5167 */ 5168 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5169 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5170 5171 /* reg_ppcnt_ether_stats_pkts65to127octets 5172 * Access: RO 5173 */ 5174 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5175 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5176 5177 /* reg_ppcnt_ether_stats_pkts128to255octets 5178 * Access: RO 5179 */ 5180 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5181 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5182 5183 /* reg_ppcnt_ether_stats_pkts256to511octets 5184 * Access: RO 5185 */ 5186 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5187 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5188 5189 /* reg_ppcnt_ether_stats_pkts512to1023octets 5190 * Access: RO 5191 */ 5192 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5193 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5194 5195 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5196 * Access: RO 5197 */ 5198 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5199 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5200 5201 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5202 * Access: RO 5203 */ 5204 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5205 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5206 5207 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5208 * Access: RO 5209 */ 5210 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5211 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5212 5213 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5214 * Access: RO 5215 */ 5216 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5217 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5218 5219 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5220 * Access: RO 5221 */ 5222 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5223 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5224 5225 /* Ethernet RFC 3635 Counter Group */ 5226 5227 /* reg_ppcnt_dot3stats_fcs_errors 5228 * Access: RO 5229 */ 5230 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5231 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5232 5233 /* reg_ppcnt_dot3stats_symbol_errors 5234 * Access: RO 5235 */ 5236 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5237 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5238 5239 /* reg_ppcnt_dot3control_in_unknown_opcodes 5240 * Access: RO 5241 */ 5242 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5243 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5244 5245 /* reg_ppcnt_dot3in_pause_frames 5246 * Access: RO 5247 */ 5248 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5249 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5250 5251 /* Ethernet Extended Counter Group Counters */ 5252 5253 /* reg_ppcnt_ecn_marked 5254 * Access: RO 5255 */ 5256 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5257 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5258 5259 /* Ethernet Discard Counter Group Counters */ 5260 5261 /* reg_ppcnt_ingress_general 5262 * Access: RO 5263 */ 5264 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5265 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5266 5267 /* reg_ppcnt_ingress_policy_engine 5268 * Access: RO 5269 */ 5270 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5271 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5272 5273 /* reg_ppcnt_ingress_vlan_membership 5274 * Access: RO 5275 */ 5276 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5277 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5278 5279 /* reg_ppcnt_ingress_tag_frame_type 5280 * Access: RO 5281 */ 5282 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5283 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5284 5285 /* reg_ppcnt_egress_vlan_membership 5286 * Access: RO 5287 */ 5288 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5289 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5290 5291 /* reg_ppcnt_loopback_filter 5292 * Access: RO 5293 */ 5294 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5295 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5296 5297 /* reg_ppcnt_egress_general 5298 * Access: RO 5299 */ 5300 MLXSW_ITEM64(reg, ppcnt, egress_general, 5301 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5302 5303 /* reg_ppcnt_egress_hoq 5304 * Access: RO 5305 */ 5306 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5307 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5308 5309 /* reg_ppcnt_egress_policy_engine 5310 * Access: RO 5311 */ 5312 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5313 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5314 5315 /* reg_ppcnt_ingress_tx_link_down 5316 * Access: RO 5317 */ 5318 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5319 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5320 5321 /* reg_ppcnt_egress_stp_filter 5322 * Access: RO 5323 */ 5324 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5325 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5326 5327 /* reg_ppcnt_egress_sll 5328 * Access: RO 5329 */ 5330 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5331 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5332 5333 /* Ethernet Per Priority Group Counters */ 5334 5335 /* reg_ppcnt_rx_octets 5336 * Access: RO 5337 */ 5338 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5339 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5340 5341 /* reg_ppcnt_rx_frames 5342 * Access: RO 5343 */ 5344 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5345 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5346 5347 /* reg_ppcnt_tx_octets 5348 * Access: RO 5349 */ 5350 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5351 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5352 5353 /* reg_ppcnt_tx_frames 5354 * Access: RO 5355 */ 5356 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5357 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5358 5359 /* reg_ppcnt_rx_pause 5360 * Access: RO 5361 */ 5362 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5363 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5364 5365 /* reg_ppcnt_rx_pause_duration 5366 * Access: RO 5367 */ 5368 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5369 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5370 5371 /* reg_ppcnt_tx_pause 5372 * Access: RO 5373 */ 5374 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5375 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5376 5377 /* reg_ppcnt_tx_pause_duration 5378 * Access: RO 5379 */ 5380 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5381 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5382 5383 /* reg_ppcnt_rx_pause_transition 5384 * Access: RO 5385 */ 5386 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5387 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5388 5389 /* Ethernet Per Traffic Class Counters */ 5390 5391 /* reg_ppcnt_tc_transmit_queue 5392 * Contains the transmit queue depth in cells of traffic class 5393 * selected by prio_tc and the port selected by local_port. 5394 * The field cannot be cleared. 5395 * Access: RO 5396 */ 5397 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5398 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5399 5400 /* reg_ppcnt_tc_no_buffer_discard_uc 5401 * The number of unicast packets dropped due to lack of shared 5402 * buffer resources. 5403 * Access: RO 5404 */ 5405 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5406 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5407 5408 /* Ethernet Per Traffic Class Congestion Group Counters */ 5409 5410 /* reg_ppcnt_wred_discard 5411 * Access: RO 5412 */ 5413 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5414 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5415 5416 /* reg_ppcnt_ecn_marked_tc 5417 * Access: RO 5418 */ 5419 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5420 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5421 5422 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5423 enum mlxsw_reg_ppcnt_grp grp, 5424 u8 prio_tc) 5425 { 5426 MLXSW_REG_ZERO(ppcnt, payload); 5427 mlxsw_reg_ppcnt_swid_set(payload, 0); 5428 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5429 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5430 mlxsw_reg_ppcnt_grp_set(payload, grp); 5431 mlxsw_reg_ppcnt_clr_set(payload, 0); 5432 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5433 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5434 } 5435 5436 /* PLIB - Port Local to InfiniBand Port 5437 * ------------------------------------ 5438 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5439 */ 5440 #define MLXSW_REG_PLIB_ID 0x500A 5441 #define MLXSW_REG_PLIB_LEN 0x10 5442 5443 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5444 5445 /* reg_plib_local_port 5446 * Local port number. 5447 * Access: Index 5448 */ 5449 MLXSW_ITEM32_LP(reg, plib, 0x00, 16, 0x00, 12); 5450 5451 /* reg_plib_ib_port 5452 * InfiniBand port remapping for local_port. 5453 * Access: RW 5454 */ 5455 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5456 5457 /* PPTB - Port Prio To Buffer Register 5458 * ----------------------------------- 5459 * Configures the switch priority to buffer table. 5460 */ 5461 #define MLXSW_REG_PPTB_ID 0x500B 5462 #define MLXSW_REG_PPTB_LEN 0x10 5463 5464 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5465 5466 enum { 5467 MLXSW_REG_PPTB_MM_UM, 5468 MLXSW_REG_PPTB_MM_UNICAST, 5469 MLXSW_REG_PPTB_MM_MULTICAST, 5470 }; 5471 5472 /* reg_pptb_mm 5473 * Mapping mode. 5474 * 0 - Map both unicast and multicast packets to the same buffer. 5475 * 1 - Map only unicast packets. 5476 * 2 - Map only multicast packets. 5477 * Access: Index 5478 * 5479 * Note: SwitchX-2 only supports the first option. 5480 */ 5481 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5482 5483 /* reg_pptb_local_port 5484 * Local port number. 5485 * Access: Index 5486 */ 5487 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5488 5489 /* reg_pptb_um 5490 * Enables the update of the untagged_buf field. 5491 * Access: RW 5492 */ 5493 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5494 5495 /* reg_pptb_pm 5496 * Enables the update of the prio_to_buff field. 5497 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5498 * Access: RW 5499 */ 5500 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5501 5502 /* reg_pptb_prio_to_buff 5503 * Mapping of switch priority <i> to one of the allocated receive port 5504 * buffers. 5505 * Access: RW 5506 */ 5507 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5508 5509 /* reg_pptb_pm_msb 5510 * Enables the update of the prio_to_buff field. 5511 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5512 * Access: RW 5513 */ 5514 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5515 5516 /* reg_pptb_untagged_buff 5517 * Mapping of untagged frames to one of the allocated receive port buffers. 5518 * Access: RW 5519 * 5520 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5521 * Spectrum, as it maps untagged packets based on the default switch priority. 5522 */ 5523 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5524 5525 /* reg_pptb_prio_to_buff_msb 5526 * Mapping of switch priority <i+8> to one of the allocated receive port 5527 * buffers. 5528 * Access: RW 5529 */ 5530 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5531 5532 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5533 5534 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5535 { 5536 MLXSW_REG_ZERO(pptb, payload); 5537 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5538 mlxsw_reg_pptb_local_port_set(payload, local_port); 5539 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5540 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5541 } 5542 5543 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5544 u8 buff) 5545 { 5546 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5547 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5548 } 5549 5550 /* PBMC - Port Buffer Management Control Register 5551 * ---------------------------------------------- 5552 * The PBMC register configures and retrieves the port packet buffer 5553 * allocation for different Prios, and the Pause threshold management. 5554 */ 5555 #define MLXSW_REG_PBMC_ID 0x500C 5556 #define MLXSW_REG_PBMC_LEN 0x6C 5557 5558 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5559 5560 /* reg_pbmc_local_port 5561 * Local port number. 5562 * Access: Index 5563 */ 5564 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5565 5566 /* reg_pbmc_xoff_timer_value 5567 * When device generates a pause frame, it uses this value as the pause 5568 * timer (time for the peer port to pause in quota-512 bit time). 5569 * Access: RW 5570 */ 5571 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5572 5573 /* reg_pbmc_xoff_refresh 5574 * The time before a new pause frame should be sent to refresh the pause RW 5575 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5576 * time). 5577 * Access: RW 5578 */ 5579 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5580 5581 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5582 5583 /* reg_pbmc_buf_lossy 5584 * The field indicates if the buffer is lossy. 5585 * 0 - Lossless 5586 * 1 - Lossy 5587 * Access: RW 5588 */ 5589 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5590 5591 /* reg_pbmc_buf_epsb 5592 * Eligible for Port Shared buffer. 5593 * If epsb is set, packets assigned to buffer are allowed to insert the port 5594 * shared buffer. 5595 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5596 * Access: RW 5597 */ 5598 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5599 5600 /* reg_pbmc_buf_size 5601 * The part of the packet buffer array is allocated for the specific buffer. 5602 * Units are represented in cells. 5603 * Access: RW 5604 */ 5605 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5606 5607 /* reg_pbmc_buf_xoff_threshold 5608 * Once the amount of data in the buffer goes above this value, device 5609 * starts sending PFC frames for all priorities associated with the 5610 * buffer. Units are represented in cells. Reserved in case of lossy 5611 * buffer. 5612 * Access: RW 5613 * 5614 * Note: In Spectrum, reserved for buffer[9]. 5615 */ 5616 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5617 0x08, 0x04, false); 5618 5619 /* reg_pbmc_buf_xon_threshold 5620 * When the amount of data in the buffer goes below this value, device 5621 * stops sending PFC frames for the priorities associated with the 5622 * buffer. Units are represented in cells. Reserved in case of lossy 5623 * buffer. 5624 * Access: RW 5625 * 5626 * Note: In Spectrum, reserved for buffer[9]. 5627 */ 5628 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5629 0x08, 0x04, false); 5630 5631 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5632 u16 xoff_timer_value, u16 xoff_refresh) 5633 { 5634 MLXSW_REG_ZERO(pbmc, payload); 5635 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5636 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5637 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5638 } 5639 5640 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5641 int buf_index, 5642 u16 size) 5643 { 5644 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5645 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5646 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5647 } 5648 5649 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5650 int buf_index, u16 size, 5651 u16 threshold) 5652 { 5653 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5654 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5655 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5656 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5657 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5658 } 5659 5660 /* PSPA - Port Switch Partition Allocation 5661 * --------------------------------------- 5662 * Controls the association of a port with a switch partition and enables 5663 * configuring ports as stacking ports. 5664 */ 5665 #define MLXSW_REG_PSPA_ID 0x500D 5666 #define MLXSW_REG_PSPA_LEN 0x8 5667 5668 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5669 5670 /* reg_pspa_swid 5671 * Switch partition ID. 5672 * Access: RW 5673 */ 5674 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5675 5676 /* reg_pspa_local_port 5677 * Local port number. 5678 * Access: Index 5679 */ 5680 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5681 5682 /* reg_pspa_sub_port 5683 * Virtual port within the local port. Set to 0 when virtual ports are 5684 * disabled on the local port. 5685 * Access: Index 5686 */ 5687 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5688 5689 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5690 { 5691 MLXSW_REG_ZERO(pspa, payload); 5692 mlxsw_reg_pspa_swid_set(payload, swid); 5693 mlxsw_reg_pspa_local_port_set(payload, local_port); 5694 mlxsw_reg_pspa_sub_port_set(payload, 0); 5695 } 5696 5697 /* PMAOS - Ports Module Administrative and Operational Status 5698 * ---------------------------------------------------------- 5699 * This register configures and retrieves the per module status. 5700 */ 5701 #define MLXSW_REG_PMAOS_ID 0x5012 5702 #define MLXSW_REG_PMAOS_LEN 0x10 5703 5704 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5705 5706 /* reg_pmaos_rst 5707 * Module reset toggle. 5708 * Note: Setting reset while module is plugged-in will result in transition to 5709 * "initializing" operational state. 5710 * Access: OP 5711 */ 5712 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5713 5714 /* reg_pmaos_slot_index 5715 * Slot index. 5716 * Access: Index 5717 */ 5718 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5719 5720 /* reg_pmaos_module 5721 * Module number. 5722 * Access: Index 5723 */ 5724 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5725 5726 enum mlxsw_reg_pmaos_admin_status { 5727 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5728 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5729 /* If the module is active and then unplugged, or experienced an error 5730 * event, the operational status should go to "disabled" and can only 5731 * be enabled upon explicit enable command. 5732 */ 5733 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5734 }; 5735 5736 /* reg_pmaos_admin_status 5737 * Module administrative state (the desired state of the module). 5738 * Note: To disable a module, all ports associated with the port must be 5739 * administatively down first. 5740 * Access: RW 5741 */ 5742 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5743 5744 /* reg_pmaos_ase 5745 * Admin state update enable. 5746 * If this bit is set, admin state will be updated based on admin_state field. 5747 * Only relevant on Set() operations. 5748 * Access: WO 5749 */ 5750 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5751 5752 /* reg_pmaos_ee 5753 * Event update enable. 5754 * If this bit is set, event generation will be updated based on the e field. 5755 * Only relevant on Set operations. 5756 * Access: WO 5757 */ 5758 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5759 5760 enum mlxsw_reg_pmaos_e { 5761 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5762 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5763 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5764 }; 5765 5766 /* reg_pmaos_e 5767 * Event Generation on operational state change. 5768 * Access: RW 5769 */ 5770 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5771 5772 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module) 5773 { 5774 MLXSW_REG_ZERO(pmaos, payload); 5775 mlxsw_reg_pmaos_module_set(payload, module); 5776 } 5777 5778 /* PPLR - Port Physical Loopback Register 5779 * -------------------------------------- 5780 * This register allows configuration of the port's loopback mode. 5781 */ 5782 #define MLXSW_REG_PPLR_ID 0x5018 5783 #define MLXSW_REG_PPLR_LEN 0x8 5784 5785 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5786 5787 /* reg_pplr_local_port 5788 * Local port number. 5789 * Access: Index 5790 */ 5791 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 5792 5793 /* Phy local loopback. When set the port's egress traffic is looped back 5794 * to the receiver and the port transmitter is disabled. 5795 */ 5796 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5797 5798 /* reg_pplr_lb_en 5799 * Loopback enable. 5800 * Access: RW 5801 */ 5802 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5803 5804 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 5805 bool phy_local) 5806 { 5807 MLXSW_REG_ZERO(pplr, payload); 5808 mlxsw_reg_pplr_local_port_set(payload, local_port); 5809 mlxsw_reg_pplr_lb_en_set(payload, 5810 phy_local ? 5811 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5812 } 5813 5814 /* PMTDB - Port Module To local DataBase Register 5815 * ---------------------------------------------- 5816 * The PMTDB register allows to query the possible module<->local port 5817 * mapping than can be used in PMLP. It does not represent the actual/current 5818 * mapping of the local to module. Actual mapping is only defined by PMLP. 5819 */ 5820 #define MLXSW_REG_PMTDB_ID 0x501A 5821 #define MLXSW_REG_PMTDB_LEN 0x40 5822 5823 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 5824 5825 /* reg_pmtdb_slot_index 5826 * Slot index (0: Main board). 5827 * Access: Index 5828 */ 5829 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 5830 5831 /* reg_pmtdb_module 5832 * Module number. 5833 * Access: Index 5834 */ 5835 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 5836 5837 /* reg_pmtdb_ports_width 5838 * Port's width 5839 * Access: Index 5840 */ 5841 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 5842 5843 /* reg_pmtdb_num_ports 5844 * Number of ports in a single module (split/breakout) 5845 * Access: Index 5846 */ 5847 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 5848 5849 enum mlxsw_reg_pmtdb_status { 5850 MLXSW_REG_PMTDB_STATUS_SUCCESS, 5851 }; 5852 5853 /* reg_pmtdb_status 5854 * Status 5855 * Access: RO 5856 */ 5857 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 5858 5859 /* reg_pmtdb_port_num 5860 * The local_port value which can be assigned to the module. 5861 * In case of more than one port, port<x> represent the /<x> port of 5862 * the module. 5863 * Access: RO 5864 */ 5865 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 5866 5867 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 5868 u8 ports_width, u8 num_ports) 5869 { 5870 MLXSW_REG_ZERO(pmtdb, payload); 5871 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 5872 mlxsw_reg_pmtdb_module_set(payload, module); 5873 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 5874 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 5875 } 5876 5877 /* PMPE - Port Module Plug/Unplug Event Register 5878 * --------------------------------------------- 5879 * This register reports any operational status change of a module. 5880 * A change in the module’s state will generate an event only if the change 5881 * happens after arming the event mechanism. Any changes to the module state 5882 * while the event mechanism is not armed will not be reported. Software can 5883 * query the PMPE register for module status. 5884 */ 5885 #define MLXSW_REG_PMPE_ID 0x5024 5886 #define MLXSW_REG_PMPE_LEN 0x10 5887 5888 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 5889 5890 /* reg_pmpe_slot_index 5891 * Slot index. 5892 * Access: Index 5893 */ 5894 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 5895 5896 /* reg_pmpe_module 5897 * Module number. 5898 * Access: Index 5899 */ 5900 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 5901 5902 enum mlxsw_reg_pmpe_module_status { 5903 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 5904 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 5905 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 5906 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 5907 }; 5908 5909 /* reg_pmpe_module_status 5910 * Module status. 5911 * Access: RO 5912 */ 5913 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 5914 5915 /* reg_pmpe_error_type 5916 * Module error details. 5917 * Access: RO 5918 */ 5919 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 5920 5921 /* PDDR - Port Diagnostics Database Register 5922 * ----------------------------------------- 5923 * The PDDR enables to read the Phy debug database 5924 */ 5925 #define MLXSW_REG_PDDR_ID 0x5031 5926 #define MLXSW_REG_PDDR_LEN 0x100 5927 5928 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 5929 5930 /* reg_pddr_local_port 5931 * Local port number. 5932 * Access: Index 5933 */ 5934 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 5935 5936 enum mlxsw_reg_pddr_page_select { 5937 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 5938 }; 5939 5940 /* reg_pddr_page_select 5941 * Page select index. 5942 * Access: Index 5943 */ 5944 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 5945 5946 enum mlxsw_reg_pddr_trblsh_group_opcode { 5947 /* Monitor opcodes */ 5948 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 5949 }; 5950 5951 /* reg_pddr_group_opcode 5952 * Group selector. 5953 * Access: Index 5954 */ 5955 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 5956 5957 /* reg_pddr_status_opcode 5958 * Group selector. 5959 * Access: RO 5960 */ 5961 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 5962 5963 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 5964 u8 page_select) 5965 { 5966 MLXSW_REG_ZERO(pddr, payload); 5967 mlxsw_reg_pddr_local_port_set(payload, local_port); 5968 mlxsw_reg_pddr_page_select_set(payload, page_select); 5969 } 5970 5971 /* PMMP - Port Module Memory Map Properties Register 5972 * ------------------------------------------------- 5973 * The PMMP register allows to override the module memory map advertisement. 5974 * The register can only be set when the module is disabled by PMAOS register. 5975 */ 5976 #define MLXSW_REG_PMMP_ID 0x5044 5977 #define MLXSW_REG_PMMP_LEN 0x2C 5978 5979 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 5980 5981 /* reg_pmmp_module 5982 * Module number. 5983 * Access: Index 5984 */ 5985 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 5986 5987 /* reg_pmmp_sticky 5988 * When set, will keep eeprom_override values after plug-out event. 5989 * Access: OP 5990 */ 5991 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 5992 5993 /* reg_pmmp_eeprom_override_mask 5994 * Write mask bit (negative polarity). 5995 * 0 - Allow write 5996 * 1 - Ignore write 5997 * On write, indicates which of the bits from eeprom_override field are 5998 * updated. 5999 * Access: WO 6000 */ 6001 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6002 6003 enum { 6004 /* Set module to low power mode */ 6005 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6006 }; 6007 6008 /* reg_pmmp_eeprom_override 6009 * Override / ignore EEPROM advertisement properties bitmask 6010 * Access: RW 6011 */ 6012 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6013 6014 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 module) 6015 { 6016 MLXSW_REG_ZERO(pmmp, payload); 6017 mlxsw_reg_pmmp_module_set(payload, module); 6018 } 6019 6020 /* PLLP - Port Local port to Label Port mapping Register 6021 * ----------------------------------------------------- 6022 * The PLLP register returns the mapping from Local Port into Label Port. 6023 */ 6024 #define MLXSW_REG_PLLP_ID 0x504A 6025 #define MLXSW_REG_PLLP_LEN 0x10 6026 6027 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6028 6029 /* reg_pllp_local_port 6030 * Local port number. 6031 * Access: Index 6032 */ 6033 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6034 6035 /* reg_pllp_label_port 6036 * Front panel label of the port. 6037 * Access: RO 6038 */ 6039 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6040 6041 /* reg_pllp_split_num 6042 * Label split mapping for local_port. 6043 * Access: RO 6044 */ 6045 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6046 6047 /* reg_pllp_slot_index 6048 * Slot index (0: Main board). 6049 * Access: RO 6050 */ 6051 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6052 6053 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6054 { 6055 MLXSW_REG_ZERO(pllp, payload); 6056 mlxsw_reg_pllp_local_port_set(payload, local_port); 6057 } 6058 6059 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6060 u8 *split_num, u8 *slot_index) 6061 { 6062 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6063 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6064 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6065 } 6066 6067 /* PMTM - Port Module Type Mapping Register 6068 * ---------------------------------------- 6069 * The PMTM register allows query or configuration of module types. 6070 * The register can only be set when the module is disabled by PMAOS register 6071 */ 6072 #define MLXSW_REG_PMTM_ID 0x5067 6073 #define MLXSW_REG_PMTM_LEN 0x10 6074 6075 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6076 6077 /* reg_pmtm_slot_index 6078 * Slot index. 6079 * Access: Index 6080 */ 6081 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6082 6083 /* reg_pmtm_module 6084 * Module number. 6085 * Access: Index 6086 */ 6087 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6088 6089 enum mlxsw_reg_pmtm_module_type { 6090 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6091 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6092 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6093 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6094 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6095 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6096 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6097 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6098 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6099 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6100 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6101 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6102 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6103 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6104 }; 6105 6106 /* reg_pmtm_module_type 6107 * Module type. 6108 * Access: RW 6109 */ 6110 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6111 6112 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6113 { 6114 MLXSW_REG_ZERO(pmtm, payload); 6115 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6116 mlxsw_reg_pmtm_module_set(payload, module); 6117 } 6118 6119 /* HTGT - Host Trap Group Table 6120 * ---------------------------- 6121 * Configures the properties for forwarding to CPU. 6122 */ 6123 #define MLXSW_REG_HTGT_ID 0x7002 6124 #define MLXSW_REG_HTGT_LEN 0x20 6125 6126 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6127 6128 /* reg_htgt_swid 6129 * Switch partition ID. 6130 * Access: Index 6131 */ 6132 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6133 6134 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6135 6136 /* reg_htgt_type 6137 * CPU path type. 6138 * Access: RW 6139 */ 6140 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6141 6142 enum mlxsw_reg_htgt_trap_group { 6143 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6144 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6145 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6146 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6147 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6148 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6149 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6150 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6151 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6152 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6153 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6154 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6155 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6156 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6157 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6158 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6159 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6160 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6161 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6162 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6163 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6164 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6165 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6166 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6167 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6168 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6169 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6170 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6171 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6172 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6173 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6174 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6175 6176 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6177 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6178 }; 6179 6180 /* reg_htgt_trap_group 6181 * Trap group number. User defined number specifying which trap groups 6182 * should be forwarded to the CPU. The mapping between trap IDs and trap 6183 * groups is configured using HPKT register. 6184 * Access: Index 6185 */ 6186 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6187 6188 enum { 6189 MLXSW_REG_HTGT_POLICER_DISABLE, 6190 MLXSW_REG_HTGT_POLICER_ENABLE, 6191 }; 6192 6193 /* reg_htgt_pide 6194 * Enable policer ID specified using 'pid' field. 6195 * Access: RW 6196 */ 6197 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6198 6199 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6200 6201 /* reg_htgt_pid 6202 * Policer ID for the trap group. 6203 * Access: RW 6204 */ 6205 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6206 6207 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6208 6209 /* reg_htgt_mirror_action 6210 * Mirror action to use. 6211 * 0 - Trap to CPU. 6212 * 1 - Trap to CPU and mirror to a mirroring agent. 6213 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6214 * Access: RW 6215 * 6216 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6217 */ 6218 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6219 6220 /* reg_htgt_mirroring_agent 6221 * Mirroring agent. 6222 * Access: RW 6223 */ 6224 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6225 6226 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6227 6228 /* reg_htgt_priority 6229 * Trap group priority. 6230 * In case a packet matches multiple classification rules, the packet will 6231 * only be trapped once, based on the trap ID associated with the group (via 6232 * register HPKT) with the highest priority. 6233 * Supported values are 0-7, with 7 represnting the highest priority. 6234 * Access: RW 6235 * 6236 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6237 * by the 'trap_group' field. 6238 */ 6239 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6240 6241 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6242 6243 /* reg_htgt_local_path_cpu_tclass 6244 * CPU ingress traffic class for the trap group. 6245 * Access: RW 6246 */ 6247 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6248 6249 enum mlxsw_reg_htgt_local_path_rdq { 6250 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6251 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6252 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6253 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6254 }; 6255 /* reg_htgt_local_path_rdq 6256 * Receive descriptor queue (RDQ) to use for the trap group. 6257 * Access: RW 6258 */ 6259 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6260 6261 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6262 u8 priority, u8 tc) 6263 { 6264 MLXSW_REG_ZERO(htgt, payload); 6265 6266 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6267 mlxsw_reg_htgt_pide_set(payload, 6268 MLXSW_REG_HTGT_POLICER_DISABLE); 6269 } else { 6270 mlxsw_reg_htgt_pide_set(payload, 6271 MLXSW_REG_HTGT_POLICER_ENABLE); 6272 mlxsw_reg_htgt_pid_set(payload, policer_id); 6273 } 6274 6275 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6276 mlxsw_reg_htgt_trap_group_set(payload, group); 6277 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6278 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6279 mlxsw_reg_htgt_priority_set(payload, priority); 6280 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6281 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6282 } 6283 6284 /* HPKT - Host Packet Trap 6285 * ----------------------- 6286 * Configures trap IDs inside trap groups. 6287 */ 6288 #define MLXSW_REG_HPKT_ID 0x7003 6289 #define MLXSW_REG_HPKT_LEN 0x10 6290 6291 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6292 6293 enum { 6294 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6295 MLXSW_REG_HPKT_ACK_REQUIRED, 6296 }; 6297 6298 /* reg_hpkt_ack 6299 * Require acknowledgements from the host for events. 6300 * If set, then the device will wait for the event it sent to be acknowledged 6301 * by the host. This option is only relevant for event trap IDs. 6302 * Access: RW 6303 * 6304 * Note: Currently not supported by firmware. 6305 */ 6306 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6307 6308 enum mlxsw_reg_hpkt_action { 6309 MLXSW_REG_HPKT_ACTION_FORWARD, 6310 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6311 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6312 MLXSW_REG_HPKT_ACTION_DISCARD, 6313 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6314 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6315 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6316 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6317 }; 6318 6319 /* reg_hpkt_action 6320 * Action to perform on packet when trapped. 6321 * 0 - No action. Forward to CPU based on switching rules. 6322 * 1 - Trap to CPU (CPU receives sole copy). 6323 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6324 * 3 - Discard. 6325 * 4 - Soft discard (allow other traps to act on the packet). 6326 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6327 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6328 * 15 - Restore the firmware's default action. 6329 * Access: RW 6330 * 6331 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6332 * addressed to the CPU. 6333 */ 6334 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6335 6336 /* reg_hpkt_trap_group 6337 * Trap group to associate the trap with. 6338 * Access: RW 6339 */ 6340 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6341 6342 /* reg_hpkt_trap_id 6343 * Trap ID. 6344 * Access: Index 6345 * 6346 * Note: A trap ID can only be associated with a single trap group. The device 6347 * will associate the trap ID with the last trap group configured. 6348 */ 6349 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6350 6351 enum { 6352 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6353 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6354 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6355 }; 6356 6357 /* reg_hpkt_ctrl 6358 * Configure dedicated buffer resources for control packets. 6359 * Ignored by SwitchX-2. 6360 * 0 - Keep factory defaults. 6361 * 1 - Do not use control buffer for this trap ID. 6362 * 2 - Use control buffer for this trap ID. 6363 * Access: RW 6364 */ 6365 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6366 6367 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6368 enum mlxsw_reg_htgt_trap_group trap_group, 6369 bool is_ctrl) 6370 { 6371 MLXSW_REG_ZERO(hpkt, payload); 6372 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6373 mlxsw_reg_hpkt_action_set(payload, action); 6374 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6375 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6376 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6377 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6378 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6379 } 6380 6381 /* RGCR - Router General Configuration Register 6382 * -------------------------------------------- 6383 * The register is used for setting up the router configuration. 6384 */ 6385 #define MLXSW_REG_RGCR_ID 0x8001 6386 #define MLXSW_REG_RGCR_LEN 0x28 6387 6388 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6389 6390 /* reg_rgcr_ipv4_en 6391 * IPv4 router enable. 6392 * Access: RW 6393 */ 6394 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6395 6396 /* reg_rgcr_ipv6_en 6397 * IPv6 router enable. 6398 * Access: RW 6399 */ 6400 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6401 6402 /* reg_rgcr_max_router_interfaces 6403 * Defines the maximum number of active router interfaces for all virtual 6404 * routers. 6405 * Access: RW 6406 */ 6407 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6408 6409 /* reg_rgcr_usp 6410 * Update switch priority and packet color. 6411 * 0 - Preserve the value of Switch Priority and packet color. 6412 * 1 - Recalculate the value of Switch Priority and packet color. 6413 * Access: RW 6414 * 6415 * Note: Not supported by SwitchX and SwitchX-2. 6416 */ 6417 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6418 6419 /* reg_rgcr_pcp_rw 6420 * Indicates how to handle the pcp_rewrite_en value: 6421 * 0 - Preserve the value of pcp_rewrite_en. 6422 * 2 - Disable PCP rewrite. 6423 * 3 - Enable PCP rewrite. 6424 * Access: RW 6425 * 6426 * Note: Not supported by SwitchX and SwitchX-2. 6427 */ 6428 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6429 6430 /* reg_rgcr_activity_dis 6431 * Activity disable: 6432 * 0 - Activity will be set when an entry is hit (default). 6433 * 1 - Activity will not be set when an entry is hit. 6434 * 6435 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6436 * (RALUE). 6437 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6438 * Entry (RAUHT). 6439 * Bits 2:7 are reserved. 6440 * Access: RW 6441 * 6442 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6443 */ 6444 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6445 6446 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6447 bool ipv6_en) 6448 { 6449 MLXSW_REG_ZERO(rgcr, payload); 6450 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6451 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6452 } 6453 6454 /* RITR - Router Interface Table Register 6455 * -------------------------------------- 6456 * The register is used to configure the router interface table. 6457 */ 6458 #define MLXSW_REG_RITR_ID 0x8002 6459 #define MLXSW_REG_RITR_LEN 0x40 6460 6461 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6462 6463 /* reg_ritr_enable 6464 * Enables routing on the router interface. 6465 * Access: RW 6466 */ 6467 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6468 6469 /* reg_ritr_ipv4 6470 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6471 * interface. 6472 * Access: RW 6473 */ 6474 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6475 6476 /* reg_ritr_ipv6 6477 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6478 * interface. 6479 * Access: RW 6480 */ 6481 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6482 6483 /* reg_ritr_ipv4_mc 6484 * IPv4 multicast routing enable. 6485 * Access: RW 6486 */ 6487 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6488 6489 /* reg_ritr_ipv6_mc 6490 * IPv6 multicast routing enable. 6491 * Access: RW 6492 */ 6493 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6494 6495 enum mlxsw_reg_ritr_if_type { 6496 /* VLAN interface. */ 6497 MLXSW_REG_RITR_VLAN_IF, 6498 /* FID interface. */ 6499 MLXSW_REG_RITR_FID_IF, 6500 /* Sub-port interface. */ 6501 MLXSW_REG_RITR_SP_IF, 6502 /* Loopback Interface. */ 6503 MLXSW_REG_RITR_LOOPBACK_IF, 6504 }; 6505 6506 /* reg_ritr_type 6507 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6508 * Access: RW 6509 */ 6510 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6511 6512 enum { 6513 MLXSW_REG_RITR_RIF_CREATE, 6514 MLXSW_REG_RITR_RIF_DEL, 6515 }; 6516 6517 /* reg_ritr_op 6518 * Opcode: 6519 * 0 - Create or edit RIF. 6520 * 1 - Delete RIF. 6521 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6522 * is not supported. An interface must be deleted and re-created in order 6523 * to update properties. 6524 * Access: WO 6525 */ 6526 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6527 6528 /* reg_ritr_rif 6529 * Router interface index. A pointer to the Router Interface Table. 6530 * Access: Index 6531 */ 6532 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6533 6534 /* reg_ritr_ipv4_fe 6535 * IPv4 Forwarding Enable. 6536 * Enables routing of IPv4 traffic on the router interface. When disabled, 6537 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6538 * Not supported in SwitchX-2. 6539 * Access: RW 6540 */ 6541 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6542 6543 /* reg_ritr_ipv6_fe 6544 * IPv6 Forwarding Enable. 6545 * Enables routing of IPv6 traffic on the router interface. When disabled, 6546 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6547 * Not supported in SwitchX-2. 6548 * Access: RW 6549 */ 6550 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6551 6552 /* reg_ritr_ipv4_mc_fe 6553 * IPv4 Multicast Forwarding Enable. 6554 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6555 * will be enabled. 6556 * Access: RW 6557 */ 6558 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6559 6560 /* reg_ritr_ipv6_mc_fe 6561 * IPv6 Multicast Forwarding Enable. 6562 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6563 * will be enabled. 6564 * Access: RW 6565 */ 6566 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6567 6568 /* reg_ritr_lb_en 6569 * Loop-back filter enable for unicast packets. 6570 * If the flag is set then loop-back filter for unicast packets is 6571 * implemented on the RIF. Multicast packets are always subject to 6572 * loop-back filtering. 6573 * Access: RW 6574 */ 6575 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6576 6577 /* reg_ritr_virtual_router 6578 * Virtual router ID associated with the router interface. 6579 * Access: RW 6580 */ 6581 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6582 6583 /* reg_ritr_mtu 6584 * Router interface MTU. 6585 * Access: RW 6586 */ 6587 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6588 6589 /* reg_ritr_if_swid 6590 * Switch partition ID. 6591 * Access: RW 6592 */ 6593 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6594 6595 /* reg_ritr_if_mac_profile_id 6596 * MAC msb profile ID. 6597 * Access: RW 6598 */ 6599 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6600 6601 /* reg_ritr_if_mac 6602 * Router interface MAC address. 6603 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6604 * Access: RW 6605 */ 6606 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6607 6608 /* reg_ritr_if_vrrp_id_ipv6 6609 * VRRP ID for IPv6 6610 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6611 * Access: RW 6612 */ 6613 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6614 6615 /* reg_ritr_if_vrrp_id_ipv4 6616 * VRRP ID for IPv4 6617 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6618 * Access: RW 6619 */ 6620 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6621 6622 /* VLAN Interface */ 6623 6624 /* reg_ritr_vlan_if_vid 6625 * VLAN ID. 6626 * Access: RW 6627 */ 6628 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6629 6630 /* FID Interface */ 6631 6632 /* reg_ritr_fid_if_fid 6633 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6634 * the vFID range are supported. 6635 * Access: RW 6636 */ 6637 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6638 6639 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6640 enum mlxsw_reg_ritr_if_type rif_type, 6641 u16 fid) 6642 { 6643 if (rif_type == MLXSW_REG_RITR_FID_IF) 6644 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6645 else 6646 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6647 } 6648 6649 /* Sub-port Interface */ 6650 6651 /* reg_ritr_sp_if_lag 6652 * LAG indication. When this bit is set the system_port field holds the 6653 * LAG identifier. 6654 * Access: RW 6655 */ 6656 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6657 6658 /* reg_ritr_sp_system_port 6659 * Port unique indentifier. When lag bit is set, this field holds the 6660 * lag_id in bits 0:9. 6661 * Access: RW 6662 */ 6663 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6664 6665 /* reg_ritr_sp_if_vid 6666 * VLAN ID. 6667 * Access: RW 6668 */ 6669 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6670 6671 /* Loopback Interface */ 6672 6673 enum mlxsw_reg_ritr_loopback_protocol { 6674 /* IPinIP IPv4 underlay Unicast */ 6675 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6676 /* IPinIP IPv6 underlay Unicast */ 6677 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6678 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6679 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6680 }; 6681 6682 /* reg_ritr_loopback_protocol 6683 * Access: RW 6684 */ 6685 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6686 6687 enum mlxsw_reg_ritr_loopback_ipip_type { 6688 /* Tunnel is IPinIP. */ 6689 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6690 /* Tunnel is GRE, no key. */ 6691 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6692 /* Tunnel is GRE, with a key. */ 6693 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6694 }; 6695 6696 /* reg_ritr_loopback_ipip_type 6697 * Encapsulation type. 6698 * Access: RW 6699 */ 6700 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6701 6702 enum mlxsw_reg_ritr_loopback_ipip_options { 6703 /* The key is defined by gre_key. */ 6704 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6705 }; 6706 6707 /* reg_ritr_loopback_ipip_options 6708 * Access: RW 6709 */ 6710 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6711 6712 /* reg_ritr_loopback_ipip_uvr 6713 * Underlay Virtual Router ID. 6714 * Range is 0..cap_max_virtual_routers-1. 6715 * Reserved for Spectrum-2. 6716 * Access: RW 6717 */ 6718 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6719 6720 /* reg_ritr_loopback_ipip_underlay_rif 6721 * Underlay ingress router interface. 6722 * Reserved for Spectrum. 6723 * Access: RW 6724 */ 6725 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6726 6727 /* reg_ritr_loopback_ipip_usip* 6728 * Encapsulation Underlay source IP. 6729 * Access: RW 6730 */ 6731 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6732 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6733 6734 /* reg_ritr_loopback_ipip_gre_key 6735 * GRE Key. 6736 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6737 * Access: RW 6738 */ 6739 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6740 6741 /* Shared between ingress/egress */ 6742 enum mlxsw_reg_ritr_counter_set_type { 6743 /* No Count. */ 6744 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6745 /* Basic. Used for router interfaces, counting the following: 6746 * - Error and Discard counters. 6747 * - Unicast, Multicast and Broadcast counters. Sharing the 6748 * same set of counters for the different type of traffic 6749 * (IPv4, IPv6 and mpls). 6750 */ 6751 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6752 }; 6753 6754 /* reg_ritr_ingress_counter_index 6755 * Counter Index for flow counter. 6756 * Access: RW 6757 */ 6758 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6759 6760 /* reg_ritr_ingress_counter_set_type 6761 * Igress Counter Set Type for router interface counter. 6762 * Access: RW 6763 */ 6764 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6765 6766 /* reg_ritr_egress_counter_index 6767 * Counter Index for flow counter. 6768 * Access: RW 6769 */ 6770 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6771 6772 /* reg_ritr_egress_counter_set_type 6773 * Egress Counter Set Type for router interface counter. 6774 * Access: RW 6775 */ 6776 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6777 6778 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6779 bool enable, bool egress) 6780 { 6781 enum mlxsw_reg_ritr_counter_set_type set_type; 6782 6783 if (enable) 6784 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6785 else 6786 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6787 6788 if (egress) { 6789 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6790 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6791 } else { 6792 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 6793 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6794 } 6795 } 6796 6797 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6798 { 6799 MLXSW_REG_ZERO(ritr, payload); 6800 mlxsw_reg_ritr_rif_set(payload, rif); 6801 } 6802 6803 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6804 u16 system_port, u16 vid) 6805 { 6806 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6807 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6808 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6809 } 6810 6811 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6812 enum mlxsw_reg_ritr_if_type type, 6813 u16 rif, u16 vr_id, u16 mtu) 6814 { 6815 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6816 6817 MLXSW_REG_ZERO(ritr, payload); 6818 mlxsw_reg_ritr_enable_set(payload, enable); 6819 mlxsw_reg_ritr_ipv4_set(payload, 1); 6820 mlxsw_reg_ritr_ipv6_set(payload, 1); 6821 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6822 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6823 mlxsw_reg_ritr_type_set(payload, type); 6824 mlxsw_reg_ritr_op_set(payload, op); 6825 mlxsw_reg_ritr_rif_set(payload, rif); 6826 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6827 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6828 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6829 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6830 mlxsw_reg_ritr_lb_en_set(payload, 1); 6831 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6832 mlxsw_reg_ritr_mtu_set(payload, mtu); 6833 } 6834 6835 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6836 { 6837 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6838 } 6839 6840 static inline void 6841 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6842 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6843 enum mlxsw_reg_ritr_loopback_ipip_options options, 6844 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6845 { 6846 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6847 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6848 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6849 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6850 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6851 } 6852 6853 static inline void 6854 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6855 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6856 enum mlxsw_reg_ritr_loopback_ipip_options options, 6857 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6858 { 6859 mlxsw_reg_ritr_loopback_protocol_set(payload, 6860 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6861 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6862 uvr_id, underlay_rif, gre_key); 6863 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6864 } 6865 6866 static inline void 6867 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 6868 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6869 enum mlxsw_reg_ritr_loopback_ipip_options options, 6870 u16 uvr_id, u16 underlay_rif, 6871 const struct in6_addr *usip, u32 gre_key) 6872 { 6873 enum mlxsw_reg_ritr_loopback_protocol protocol = 6874 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 6875 6876 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 6877 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6878 uvr_id, underlay_rif, gre_key); 6879 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 6880 (const char *)usip); 6881 } 6882 6883 /* RTAR - Router TCAM Allocation Register 6884 * -------------------------------------- 6885 * This register is used for allocation of regions in the TCAM table. 6886 */ 6887 #define MLXSW_REG_RTAR_ID 0x8004 6888 #define MLXSW_REG_RTAR_LEN 0x20 6889 6890 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6891 6892 enum mlxsw_reg_rtar_op { 6893 MLXSW_REG_RTAR_OP_ALLOCATE, 6894 MLXSW_REG_RTAR_OP_RESIZE, 6895 MLXSW_REG_RTAR_OP_DEALLOCATE, 6896 }; 6897 6898 /* reg_rtar_op 6899 * Access: WO 6900 */ 6901 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6902 6903 enum mlxsw_reg_rtar_key_type { 6904 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6905 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6906 }; 6907 6908 /* reg_rtar_key_type 6909 * TCAM key type for the region. 6910 * Access: WO 6911 */ 6912 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6913 6914 /* reg_rtar_region_size 6915 * TCAM region size. When allocating/resizing this is the requested 6916 * size, the response is the actual size. 6917 * Note: Actual size may be larger than requested. 6918 * Reserved for op = Deallocate 6919 * Access: WO 6920 */ 6921 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6922 6923 static inline void mlxsw_reg_rtar_pack(char *payload, 6924 enum mlxsw_reg_rtar_op op, 6925 enum mlxsw_reg_rtar_key_type key_type, 6926 u16 region_size) 6927 { 6928 MLXSW_REG_ZERO(rtar, payload); 6929 mlxsw_reg_rtar_op_set(payload, op); 6930 mlxsw_reg_rtar_key_type_set(payload, key_type); 6931 mlxsw_reg_rtar_region_size_set(payload, region_size); 6932 } 6933 6934 /* RATR - Router Adjacency Table Register 6935 * -------------------------------------- 6936 * The RATR register is used to configure the Router Adjacency (next-hop) 6937 * Table. 6938 */ 6939 #define MLXSW_REG_RATR_ID 0x8008 6940 #define MLXSW_REG_RATR_LEN 0x2C 6941 6942 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6943 6944 enum mlxsw_reg_ratr_op { 6945 /* Read */ 6946 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6947 /* Read and clear activity */ 6948 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6949 /* Write Adjacency entry */ 6950 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6951 /* Write Adjacency entry only if the activity is cleared. 6952 * The write may not succeed if the activity is set. There is not 6953 * direct feedback if the write has succeeded or not, however 6954 * the get will reveal the actual entry (SW can compare the get 6955 * response to the set command). 6956 */ 6957 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6958 }; 6959 6960 /* reg_ratr_op 6961 * Note that Write operation may also be used for updating 6962 * counter_set_type and counter_index. In this case all other 6963 * fields must not be updated. 6964 * Access: OP 6965 */ 6966 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6967 6968 /* reg_ratr_v 6969 * Valid bit. Indicates if the adjacency entry is valid. 6970 * Note: the device may need some time before reusing an invalidated 6971 * entry. During this time the entry can not be reused. It is 6972 * recommended to use another entry before reusing an invalidated 6973 * entry (e.g. software can put it at the end of the list for 6974 * reusing). Trying to access an invalidated entry not yet cleared 6975 * by the device results with failure indicating "Try Again" status. 6976 * When valid is '0' then egress_router_interface,trap_action, 6977 * adjacency_parameters and counters are reserved 6978 * Access: RW 6979 */ 6980 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6981 6982 /* reg_ratr_a 6983 * Activity. Set for new entries. Set if a packet lookup has hit on 6984 * the specific entry. To clear the a bit, use "clear activity". 6985 * Access: RO 6986 */ 6987 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6988 6989 enum mlxsw_reg_ratr_type { 6990 /* Ethernet */ 6991 MLXSW_REG_RATR_TYPE_ETHERNET, 6992 /* IPoIB Unicast without GRH. 6993 * Reserved for Spectrum. 6994 */ 6995 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6996 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6997 * adjacency). 6998 * Reserved for Spectrum. 6999 */ 7000 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7001 /* IPoIB Multicast. 7002 * Reserved for Spectrum. 7003 */ 7004 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7005 /* MPLS. 7006 * Reserved for SwitchX/-2. 7007 */ 7008 MLXSW_REG_RATR_TYPE_MPLS, 7009 /* IPinIP Encap. 7010 * Reserved for SwitchX/-2. 7011 */ 7012 MLXSW_REG_RATR_TYPE_IPIP, 7013 }; 7014 7015 /* reg_ratr_type 7016 * Adjacency entry type. 7017 * Access: RW 7018 */ 7019 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7020 7021 /* reg_ratr_adjacency_index_low 7022 * Bits 15:0 of index into the adjacency table. 7023 * For SwitchX and SwitchX-2, the adjacency table is linear and 7024 * used for adjacency entries only. 7025 * For Spectrum, the index is to the KVD linear. 7026 * Access: Index 7027 */ 7028 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7029 7030 /* reg_ratr_egress_router_interface 7031 * Range is 0 .. cap_max_router_interfaces - 1 7032 * Access: RW 7033 */ 7034 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7035 7036 enum mlxsw_reg_ratr_trap_action { 7037 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7038 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7039 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7040 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7041 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7042 }; 7043 7044 /* reg_ratr_trap_action 7045 * see mlxsw_reg_ratr_trap_action 7046 * Access: RW 7047 */ 7048 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7049 7050 /* reg_ratr_adjacency_index_high 7051 * Bits 23:16 of the adjacency_index. 7052 * Access: Index 7053 */ 7054 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7055 7056 enum mlxsw_reg_ratr_trap_id { 7057 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7058 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7059 }; 7060 7061 /* reg_ratr_trap_id 7062 * Trap ID to be reported to CPU. 7063 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7064 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7065 * Access: RW 7066 */ 7067 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7068 7069 /* reg_ratr_eth_destination_mac 7070 * MAC address of the destination next-hop. 7071 * Access: RW 7072 */ 7073 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7074 7075 enum mlxsw_reg_ratr_ipip_type { 7076 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7077 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7078 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7079 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7080 }; 7081 7082 /* reg_ratr_ipip_type 7083 * Underlay destination ip type. 7084 * Note: the type field must match the protocol of the router interface. 7085 * Access: RW 7086 */ 7087 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7088 7089 /* reg_ratr_ipip_ipv4_udip 7090 * Underlay ipv4 dip. 7091 * Reserved when ipip_type is IPv6. 7092 * Access: RW 7093 */ 7094 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7095 7096 /* reg_ratr_ipip_ipv6_ptr 7097 * Pointer to IPv6 underlay destination ip address. 7098 * For Spectrum: Pointer to KVD linear space. 7099 * Access: RW 7100 */ 7101 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7102 7103 enum mlxsw_reg_flow_counter_set_type { 7104 /* No count */ 7105 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7106 /* Count packets and bytes */ 7107 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7108 /* Count only packets */ 7109 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7110 }; 7111 7112 /* reg_ratr_counter_set_type 7113 * Counter set type for flow counters 7114 * Access: RW 7115 */ 7116 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7117 7118 /* reg_ratr_counter_index 7119 * Counter index for flow counters 7120 * Access: RW 7121 */ 7122 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7123 7124 static inline void 7125 mlxsw_reg_ratr_pack(char *payload, 7126 enum mlxsw_reg_ratr_op op, bool valid, 7127 enum mlxsw_reg_ratr_type type, 7128 u32 adjacency_index, u16 egress_rif) 7129 { 7130 MLXSW_REG_ZERO(ratr, payload); 7131 mlxsw_reg_ratr_op_set(payload, op); 7132 mlxsw_reg_ratr_v_set(payload, valid); 7133 mlxsw_reg_ratr_type_set(payload, type); 7134 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7135 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7136 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7137 } 7138 7139 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7140 const char *dest_mac) 7141 { 7142 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7143 } 7144 7145 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7146 { 7147 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7148 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7149 } 7150 7151 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7152 { 7153 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7154 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7155 } 7156 7157 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7158 bool counter_enable) 7159 { 7160 enum mlxsw_reg_flow_counter_set_type set_type; 7161 7162 if (counter_enable) 7163 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7164 else 7165 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7166 7167 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7168 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7169 } 7170 7171 /* RDPM - Router DSCP to Priority Mapping 7172 * -------------------------------------- 7173 * Controls the mapping from DSCP field to switch priority on routed packets 7174 */ 7175 #define MLXSW_REG_RDPM_ID 0x8009 7176 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7177 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7178 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7179 #define MLXSW_REG_RDPM_LEN 0x40 7180 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7181 MLXSW_REG_RDPM_LEN - \ 7182 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7183 7184 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7185 7186 /* reg_dscp_entry_e 7187 * Enable update of the specific entry 7188 * Access: Index 7189 */ 7190 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7191 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7192 7193 /* reg_dscp_entry_prio 7194 * Switch Priority 7195 * Access: RW 7196 */ 7197 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7198 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7199 7200 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7201 u8 prio) 7202 { 7203 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7204 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7205 } 7206 7207 /* RICNT - Router Interface Counter Register 7208 * ----------------------------------------- 7209 * The RICNT register retrieves per port performance counters 7210 */ 7211 #define MLXSW_REG_RICNT_ID 0x800B 7212 #define MLXSW_REG_RICNT_LEN 0x100 7213 7214 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7215 7216 /* reg_ricnt_counter_index 7217 * Counter index 7218 * Access: RW 7219 */ 7220 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7221 7222 enum mlxsw_reg_ricnt_counter_set_type { 7223 /* No Count. */ 7224 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7225 /* Basic. Used for router interfaces, counting the following: 7226 * - Error and Discard counters. 7227 * - Unicast, Multicast and Broadcast counters. Sharing the 7228 * same set of counters for the different type of traffic 7229 * (IPv4, IPv6 and mpls). 7230 */ 7231 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7232 }; 7233 7234 /* reg_ricnt_counter_set_type 7235 * Counter Set Type for router interface counter 7236 * Access: RW 7237 */ 7238 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7239 7240 enum mlxsw_reg_ricnt_opcode { 7241 /* Nop. Supported only for read access*/ 7242 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7243 /* Clear. Setting the clr bit will reset the counter value for 7244 * all counters of the specified Router Interface. 7245 */ 7246 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7247 }; 7248 7249 /* reg_ricnt_opcode 7250 * Opcode 7251 * Access: RW 7252 */ 7253 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7254 7255 /* reg_ricnt_good_unicast_packets 7256 * good unicast packets. 7257 * Access: RW 7258 */ 7259 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7260 7261 /* reg_ricnt_good_multicast_packets 7262 * good multicast packets. 7263 * Access: RW 7264 */ 7265 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7266 7267 /* reg_ricnt_good_broadcast_packets 7268 * good broadcast packets 7269 * Access: RW 7270 */ 7271 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7272 7273 /* reg_ricnt_good_unicast_bytes 7274 * A count of L3 data and padding octets not including L2 headers 7275 * for good unicast frames. 7276 * Access: RW 7277 */ 7278 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7279 7280 /* reg_ricnt_good_multicast_bytes 7281 * A count of L3 data and padding octets not including L2 headers 7282 * for good multicast frames. 7283 * Access: RW 7284 */ 7285 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7286 7287 /* reg_ritr_good_broadcast_bytes 7288 * A count of L3 data and padding octets not including L2 headers 7289 * for good broadcast frames. 7290 * Access: RW 7291 */ 7292 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7293 7294 /* reg_ricnt_error_packets 7295 * A count of errored frames that do not pass the router checks. 7296 * Access: RW 7297 */ 7298 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7299 7300 /* reg_ricnt_discrad_packets 7301 * A count of non-errored frames that do not pass the router checks. 7302 * Access: RW 7303 */ 7304 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7305 7306 /* reg_ricnt_error_bytes 7307 * A count of L3 data and padding octets not including L2 headers 7308 * for errored frames. 7309 * Access: RW 7310 */ 7311 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7312 7313 /* reg_ricnt_discard_bytes 7314 * A count of L3 data and padding octets not including L2 headers 7315 * for non-errored frames that do not pass the router checks. 7316 * Access: RW 7317 */ 7318 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7319 7320 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7321 enum mlxsw_reg_ricnt_opcode op) 7322 { 7323 MLXSW_REG_ZERO(ricnt, payload); 7324 mlxsw_reg_ricnt_op_set(payload, op); 7325 mlxsw_reg_ricnt_counter_index_set(payload, index); 7326 mlxsw_reg_ricnt_counter_set_type_set(payload, 7327 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7328 } 7329 7330 /* RRCR - Router Rules Copy Register Layout 7331 * ---------------------------------------- 7332 * This register is used for moving and copying route entry rules. 7333 */ 7334 #define MLXSW_REG_RRCR_ID 0x800F 7335 #define MLXSW_REG_RRCR_LEN 0x24 7336 7337 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7338 7339 enum mlxsw_reg_rrcr_op { 7340 /* Move rules */ 7341 MLXSW_REG_RRCR_OP_MOVE, 7342 /* Copy rules */ 7343 MLXSW_REG_RRCR_OP_COPY, 7344 }; 7345 7346 /* reg_rrcr_op 7347 * Access: WO 7348 */ 7349 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7350 7351 /* reg_rrcr_offset 7352 * Offset within the region from which to copy/move. 7353 * Access: Index 7354 */ 7355 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7356 7357 /* reg_rrcr_size 7358 * The number of rules to copy/move. 7359 * Access: WO 7360 */ 7361 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7362 7363 /* reg_rrcr_table_id 7364 * Identifier of the table on which to perform the operation. Encoding is the 7365 * same as in RTAR.key_type 7366 * Access: Index 7367 */ 7368 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7369 7370 /* reg_rrcr_dest_offset 7371 * Offset within the region to which to copy/move 7372 * Access: Index 7373 */ 7374 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7375 7376 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7377 u16 offset, u16 size, 7378 enum mlxsw_reg_rtar_key_type table_id, 7379 u16 dest_offset) 7380 { 7381 MLXSW_REG_ZERO(rrcr, payload); 7382 mlxsw_reg_rrcr_op_set(payload, op); 7383 mlxsw_reg_rrcr_offset_set(payload, offset); 7384 mlxsw_reg_rrcr_size_set(payload, size); 7385 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7386 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7387 } 7388 7389 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7390 * ------------------------------------------------------- 7391 * RALTA is used to allocate the LPM trees of the SHSPM method. 7392 */ 7393 #define MLXSW_REG_RALTA_ID 0x8010 7394 #define MLXSW_REG_RALTA_LEN 0x04 7395 7396 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7397 7398 /* reg_ralta_op 7399 * opcode (valid for Write, must be 0 on Read) 7400 * 0 - allocate a tree 7401 * 1 - deallocate a tree 7402 * Access: OP 7403 */ 7404 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7405 7406 enum mlxsw_reg_ralxx_protocol { 7407 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7408 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7409 }; 7410 7411 /* reg_ralta_protocol 7412 * Protocol. 7413 * Deallocation opcode: Reserved. 7414 * Access: RW 7415 */ 7416 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7417 7418 /* reg_ralta_tree_id 7419 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7420 * the tree identifier (managed by software). 7421 * Note that tree_id 0 is allocated for a default-route tree. 7422 * Access: Index 7423 */ 7424 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7425 7426 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7427 enum mlxsw_reg_ralxx_protocol protocol, 7428 u8 tree_id) 7429 { 7430 MLXSW_REG_ZERO(ralta, payload); 7431 mlxsw_reg_ralta_op_set(payload, !alloc); 7432 mlxsw_reg_ralta_protocol_set(payload, protocol); 7433 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7434 } 7435 7436 /* RALST - Router Algorithmic LPM Structure Tree Register 7437 * ------------------------------------------------------ 7438 * RALST is used to set and query the structure of an LPM tree. 7439 * The structure of the tree must be sorted as a sorted binary tree, while 7440 * each node is a bin that is tagged as the length of the prefixes the lookup 7441 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7442 * of X bits to match with the destination address. The bin 0 indicates 7443 * the default action, when there is no match of any prefix. 7444 */ 7445 #define MLXSW_REG_RALST_ID 0x8011 7446 #define MLXSW_REG_RALST_LEN 0x104 7447 7448 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7449 7450 /* reg_ralst_root_bin 7451 * The bin number of the root bin. 7452 * 0<root_bin=<(length of IP address) 7453 * For a default-route tree configure 0xff 7454 * Access: RW 7455 */ 7456 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7457 7458 /* reg_ralst_tree_id 7459 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7460 * Access: Index 7461 */ 7462 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7463 7464 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7465 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7466 #define MLXSW_REG_RALST_BIN_COUNT 128 7467 7468 /* reg_ralst_left_child_bin 7469 * Holding the children of the bin according to the stored tree's structure. 7470 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7471 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7472 * Access: RW 7473 */ 7474 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7475 7476 /* reg_ralst_right_child_bin 7477 * Holding the children of the bin according to the stored tree's structure. 7478 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7479 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7480 * Access: RW 7481 */ 7482 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7483 false); 7484 7485 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7486 { 7487 MLXSW_REG_ZERO(ralst, payload); 7488 7489 /* Initialize all bins to have no left or right child */ 7490 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7491 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7492 7493 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7494 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7495 } 7496 7497 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7498 u8 left_child_bin, 7499 u8 right_child_bin) 7500 { 7501 int bin_index = bin_number - 1; 7502 7503 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7504 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7505 right_child_bin); 7506 } 7507 7508 /* RALTB - Router Algorithmic LPM Tree Binding Register 7509 * ---------------------------------------------------- 7510 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7511 */ 7512 #define MLXSW_REG_RALTB_ID 0x8012 7513 #define MLXSW_REG_RALTB_LEN 0x04 7514 7515 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7516 7517 /* reg_raltb_virtual_router 7518 * Virtual Router ID 7519 * Range is 0..cap_max_virtual_routers-1 7520 * Access: Index 7521 */ 7522 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7523 7524 /* reg_raltb_protocol 7525 * Protocol. 7526 * Access: Index 7527 */ 7528 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7529 7530 /* reg_raltb_tree_id 7531 * Tree to be used for the {virtual_router, protocol} 7532 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7533 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7534 * Access: RW 7535 */ 7536 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7537 7538 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7539 enum mlxsw_reg_ralxx_protocol protocol, 7540 u8 tree_id) 7541 { 7542 MLXSW_REG_ZERO(raltb, payload); 7543 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7544 mlxsw_reg_raltb_protocol_set(payload, protocol); 7545 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7546 } 7547 7548 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7549 * ----------------------------------------------------- 7550 * RALUE is used to configure and query LPM entries that serve 7551 * the Unicast protocols. 7552 */ 7553 #define MLXSW_REG_RALUE_ID 0x8013 7554 #define MLXSW_REG_RALUE_LEN 0x38 7555 7556 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7557 7558 /* reg_ralue_protocol 7559 * Protocol. 7560 * Access: Index 7561 */ 7562 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7563 7564 enum mlxsw_reg_ralue_op { 7565 /* Read operation. If entry doesn't exist, the operation fails. */ 7566 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7567 /* Clear on read operation. Used to read entry and 7568 * clear Activity bit. 7569 */ 7570 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7571 /* Write operation. Used to write a new entry to the table. All RW 7572 * fields are written for new entry. Activity bit is set 7573 * for new entries. 7574 */ 7575 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7576 /* Update operation. Used to update an existing route entry and 7577 * only update the RW fields that are detailed in the field 7578 * op_u_mask. If entry doesn't exist, the operation fails. 7579 */ 7580 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7581 /* Clear activity. The Activity bit (the field a) is cleared 7582 * for the entry. 7583 */ 7584 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7585 /* Delete operation. Used to delete an existing entry. If entry 7586 * doesn't exist, the operation fails. 7587 */ 7588 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7589 }; 7590 7591 /* reg_ralue_op 7592 * Operation. 7593 * Access: OP 7594 */ 7595 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7596 7597 /* reg_ralue_a 7598 * Activity. Set for new entries. Set if a packet lookup has hit on the 7599 * specific entry, only if the entry is a route. To clear the a bit, use 7600 * "clear activity" op. 7601 * Enabled by activity_dis in RGCR 7602 * Access: RO 7603 */ 7604 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7605 7606 /* reg_ralue_virtual_router 7607 * Virtual Router ID 7608 * Range is 0..cap_max_virtual_routers-1 7609 * Access: Index 7610 */ 7611 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7612 7613 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7614 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7615 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7616 7617 /* reg_ralue_op_u_mask 7618 * opcode update mask. 7619 * On read operation, this field is reserved. 7620 * This field is valid for update opcode, otherwise - reserved. 7621 * This field is a bitmask of the fields that should be updated. 7622 * Access: WO 7623 */ 7624 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7625 7626 /* reg_ralue_prefix_len 7627 * Number of bits in the prefix of the LPM route. 7628 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7629 * two entries in the physical HW table. 7630 * Access: Index 7631 */ 7632 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7633 7634 /* reg_ralue_dip* 7635 * The prefix of the route or of the marker that the object of the LPM 7636 * is compared with. The most significant bits of the dip are the prefix. 7637 * The least significant bits must be '0' if the prefix_len is smaller 7638 * than 128 for IPv6 or smaller than 32 for IPv4. 7639 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7640 * Access: Index 7641 */ 7642 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7643 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7644 7645 enum mlxsw_reg_ralue_entry_type { 7646 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7647 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7648 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7649 }; 7650 7651 /* reg_ralue_entry_type 7652 * Entry type. 7653 * Note - for Marker entries, the action_type and action fields are reserved. 7654 * Access: RW 7655 */ 7656 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7657 7658 /* reg_ralue_bmp_len 7659 * The best match prefix length in the case that there is no match for 7660 * longer prefixes. 7661 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7662 * Note for any update operation with entry_type modification this 7663 * field must be set. 7664 * Access: RW 7665 */ 7666 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7667 7668 enum mlxsw_reg_ralue_action_type { 7669 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7670 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7671 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7672 }; 7673 7674 /* reg_ralue_action_type 7675 * Action Type 7676 * Indicates how the IP address is connected. 7677 * It can be connected to a local subnet through local_erif or can be 7678 * on a remote subnet connected through a next-hop router, 7679 * or transmitted to the CPU. 7680 * Reserved when entry_type = MARKER_ENTRY 7681 * Access: RW 7682 */ 7683 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7684 7685 enum mlxsw_reg_ralue_trap_action { 7686 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7687 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7688 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7689 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7690 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7691 }; 7692 7693 /* reg_ralue_trap_action 7694 * Trap action. 7695 * For IP2ME action, only NOP and MIRROR are possible. 7696 * Access: RW 7697 */ 7698 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7699 7700 /* reg_ralue_trap_id 7701 * Trap ID to be reported to CPU. 7702 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7703 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7704 * Access: RW 7705 */ 7706 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7707 7708 /* reg_ralue_adjacency_index 7709 * Points to the first entry of the group-based ECMP. 7710 * Only relevant in case of REMOTE action. 7711 * Access: RW 7712 */ 7713 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7714 7715 /* reg_ralue_ecmp_size 7716 * Amount of sequential entries starting 7717 * from the adjacency_index (the number of ECMPs). 7718 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7719 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7720 * Only relevant in case of REMOTE action. 7721 * Access: RW 7722 */ 7723 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7724 7725 /* reg_ralue_local_erif 7726 * Egress Router Interface. 7727 * Only relevant in case of LOCAL action. 7728 * Access: RW 7729 */ 7730 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7731 7732 /* reg_ralue_ip2me_v 7733 * Valid bit for the tunnel_ptr field. 7734 * If valid = 0 then trap to CPU as IP2ME trap ID. 7735 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7736 * decapsulation then tunnel decapsulation is done. 7737 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7738 * decapsulation then trap as IP2ME trap ID. 7739 * Only relevant in case of IP2ME action. 7740 * Access: RW 7741 */ 7742 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7743 7744 /* reg_ralue_ip2me_tunnel_ptr 7745 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7746 * For Spectrum, pointer to KVD Linear. 7747 * Only relevant in case of IP2ME action. 7748 * Access: RW 7749 */ 7750 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7751 7752 static inline void mlxsw_reg_ralue_pack(char *payload, 7753 enum mlxsw_reg_ralxx_protocol protocol, 7754 enum mlxsw_reg_ralue_op op, 7755 u16 virtual_router, u8 prefix_len) 7756 { 7757 MLXSW_REG_ZERO(ralue, payload); 7758 mlxsw_reg_ralue_protocol_set(payload, protocol); 7759 mlxsw_reg_ralue_op_set(payload, op); 7760 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7761 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7762 mlxsw_reg_ralue_entry_type_set(payload, 7763 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7764 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7765 } 7766 7767 static inline void mlxsw_reg_ralue_pack4(char *payload, 7768 enum mlxsw_reg_ralxx_protocol protocol, 7769 enum mlxsw_reg_ralue_op op, 7770 u16 virtual_router, u8 prefix_len, 7771 u32 *dip) 7772 { 7773 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7774 if (dip) 7775 mlxsw_reg_ralue_dip4_set(payload, *dip); 7776 } 7777 7778 static inline void mlxsw_reg_ralue_pack6(char *payload, 7779 enum mlxsw_reg_ralxx_protocol protocol, 7780 enum mlxsw_reg_ralue_op op, 7781 u16 virtual_router, u8 prefix_len, 7782 const void *dip) 7783 { 7784 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7785 if (dip) 7786 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7787 } 7788 7789 static inline void 7790 mlxsw_reg_ralue_act_remote_pack(char *payload, 7791 enum mlxsw_reg_ralue_trap_action trap_action, 7792 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7793 { 7794 mlxsw_reg_ralue_action_type_set(payload, 7795 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7796 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7797 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7798 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7799 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7800 } 7801 7802 static inline void 7803 mlxsw_reg_ralue_act_local_pack(char *payload, 7804 enum mlxsw_reg_ralue_trap_action trap_action, 7805 u16 trap_id, u16 local_erif) 7806 { 7807 mlxsw_reg_ralue_action_type_set(payload, 7808 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7809 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7810 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7811 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7812 } 7813 7814 static inline void 7815 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7816 { 7817 mlxsw_reg_ralue_action_type_set(payload, 7818 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7819 } 7820 7821 static inline void 7822 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7823 { 7824 mlxsw_reg_ralue_action_type_set(payload, 7825 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7826 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7827 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7828 } 7829 7830 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7831 * ---------------------------------------------------------- 7832 * The RAUHT register is used to configure and query the Unicast Host table in 7833 * devices that implement the Algorithmic LPM. 7834 */ 7835 #define MLXSW_REG_RAUHT_ID 0x8014 7836 #define MLXSW_REG_RAUHT_LEN 0x74 7837 7838 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7839 7840 enum mlxsw_reg_rauht_type { 7841 MLXSW_REG_RAUHT_TYPE_IPV4, 7842 MLXSW_REG_RAUHT_TYPE_IPV6, 7843 }; 7844 7845 /* reg_rauht_type 7846 * Access: Index 7847 */ 7848 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7849 7850 enum mlxsw_reg_rauht_op { 7851 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7852 /* Read operation */ 7853 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7854 /* Clear on read operation. Used to read entry and clear 7855 * activity bit. 7856 */ 7857 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7858 /* Add. Used to write a new entry to the table. All R/W fields are 7859 * relevant for new entry. Activity bit is set for new entries. 7860 */ 7861 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7862 /* Update action. Used to update an existing route entry and 7863 * only update the following fields: 7864 * trap_action, trap_id, mac, counter_set_type, counter_index 7865 */ 7866 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7867 /* Clear activity. A bit is cleared for the entry. */ 7868 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7869 /* Delete entry */ 7870 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7871 /* Delete all host entries on a RIF. In this command, dip 7872 * field is reserved. 7873 */ 7874 }; 7875 7876 /* reg_rauht_op 7877 * Access: OP 7878 */ 7879 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7880 7881 /* reg_rauht_a 7882 * Activity. Set for new entries. Set if a packet lookup has hit on 7883 * the specific entry. 7884 * To clear the a bit, use "clear activity" op. 7885 * Enabled by activity_dis in RGCR 7886 * Access: RO 7887 */ 7888 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7889 7890 /* reg_rauht_rif 7891 * Router Interface 7892 * Access: Index 7893 */ 7894 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7895 7896 /* reg_rauht_dip* 7897 * Destination address. 7898 * Access: Index 7899 */ 7900 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7901 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7902 7903 enum mlxsw_reg_rauht_trap_action { 7904 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7905 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7906 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7907 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7908 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7909 }; 7910 7911 /* reg_rauht_trap_action 7912 * Access: RW 7913 */ 7914 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7915 7916 enum mlxsw_reg_rauht_trap_id { 7917 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7918 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7919 }; 7920 7921 /* reg_rauht_trap_id 7922 * Trap ID to be reported to CPU. 7923 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7924 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7925 * trap_id is reserved. 7926 * Access: RW 7927 */ 7928 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7929 7930 /* reg_rauht_counter_set_type 7931 * Counter set type for flow counters 7932 * Access: RW 7933 */ 7934 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7935 7936 /* reg_rauht_counter_index 7937 * Counter index for flow counters 7938 * Access: RW 7939 */ 7940 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7941 7942 /* reg_rauht_mac 7943 * MAC address. 7944 * Access: RW 7945 */ 7946 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7947 7948 static inline void mlxsw_reg_rauht_pack(char *payload, 7949 enum mlxsw_reg_rauht_op op, u16 rif, 7950 const char *mac) 7951 { 7952 MLXSW_REG_ZERO(rauht, payload); 7953 mlxsw_reg_rauht_op_set(payload, op); 7954 mlxsw_reg_rauht_rif_set(payload, rif); 7955 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7956 } 7957 7958 static inline void mlxsw_reg_rauht_pack4(char *payload, 7959 enum mlxsw_reg_rauht_op op, u16 rif, 7960 const char *mac, u32 dip) 7961 { 7962 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7963 mlxsw_reg_rauht_dip4_set(payload, dip); 7964 } 7965 7966 static inline void mlxsw_reg_rauht_pack6(char *payload, 7967 enum mlxsw_reg_rauht_op op, u16 rif, 7968 const char *mac, const char *dip) 7969 { 7970 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7971 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7972 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7973 } 7974 7975 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7976 u64 counter_index) 7977 { 7978 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7979 mlxsw_reg_rauht_counter_set_type_set(payload, 7980 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7981 } 7982 7983 /* RALEU - Router Algorithmic LPM ECMP Update Register 7984 * --------------------------------------------------- 7985 * The register enables updating the ECMP section in the action for multiple 7986 * LPM Unicast entries in a single operation. The update is executed to 7987 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7988 */ 7989 #define MLXSW_REG_RALEU_ID 0x8015 7990 #define MLXSW_REG_RALEU_LEN 0x28 7991 7992 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7993 7994 /* reg_raleu_protocol 7995 * Protocol. 7996 * Access: Index 7997 */ 7998 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7999 8000 /* reg_raleu_virtual_router 8001 * Virtual Router ID 8002 * Range is 0..cap_max_virtual_routers-1 8003 * Access: Index 8004 */ 8005 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8006 8007 /* reg_raleu_adjacency_index 8008 * Adjacency Index used for matching on the existing entries. 8009 * Access: Index 8010 */ 8011 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8012 8013 /* reg_raleu_ecmp_size 8014 * ECMP Size used for matching on the existing entries. 8015 * Access: Index 8016 */ 8017 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8018 8019 /* reg_raleu_new_adjacency_index 8020 * New Adjacency Index. 8021 * Access: WO 8022 */ 8023 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8024 8025 /* reg_raleu_new_ecmp_size 8026 * New ECMP Size. 8027 * Access: WO 8028 */ 8029 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8030 8031 static inline void mlxsw_reg_raleu_pack(char *payload, 8032 enum mlxsw_reg_ralxx_protocol protocol, 8033 u16 virtual_router, 8034 u32 adjacency_index, u16 ecmp_size, 8035 u32 new_adjacency_index, 8036 u16 new_ecmp_size) 8037 { 8038 MLXSW_REG_ZERO(raleu, payload); 8039 mlxsw_reg_raleu_protocol_set(payload, protocol); 8040 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8041 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8042 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8043 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8044 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8045 } 8046 8047 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8048 * ---------------------------------------------------------------- 8049 * The RAUHTD register allows dumping entries from the Router Unicast Host 8050 * Table. For a given session an entry is dumped no more than one time. The 8051 * first RAUHTD access after reset is a new session. A session ends when the 8052 * num_rec response is smaller than num_rec request or for IPv4 when the 8053 * num_entries is smaller than 4. The clear activity affect the current session 8054 * or the last session if a new session has not started. 8055 */ 8056 #define MLXSW_REG_RAUHTD_ID 0x8018 8057 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8058 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8059 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8060 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8061 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8062 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8063 8064 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8065 8066 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8067 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8068 8069 /* reg_rauhtd_filter_fields 8070 * if a bit is '0' then the relevant field is ignored and dump is done 8071 * regardless of the field value 8072 * Bit0 - filter by activity: entry_a 8073 * Bit3 - filter by entry rip: entry_rif 8074 * Access: Index 8075 */ 8076 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8077 8078 enum mlxsw_reg_rauhtd_op { 8079 MLXSW_REG_RAUHTD_OP_DUMP, 8080 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8081 }; 8082 8083 /* reg_rauhtd_op 8084 * Access: OP 8085 */ 8086 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8087 8088 /* reg_rauhtd_num_rec 8089 * At request: number of records requested 8090 * At response: number of records dumped 8091 * For IPv4, each record has 4 entries at request and up to 4 entries 8092 * at response 8093 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8094 * Access: Index 8095 */ 8096 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8097 8098 /* reg_rauhtd_entry_a 8099 * Dump only if activity has value of entry_a 8100 * Reserved if filter_fields bit0 is '0' 8101 * Access: Index 8102 */ 8103 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8104 8105 enum mlxsw_reg_rauhtd_type { 8106 MLXSW_REG_RAUHTD_TYPE_IPV4, 8107 MLXSW_REG_RAUHTD_TYPE_IPV6, 8108 }; 8109 8110 /* reg_rauhtd_type 8111 * Dump only if record type is: 8112 * 0 - IPv4 8113 * 1 - IPv6 8114 * Access: Index 8115 */ 8116 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8117 8118 /* reg_rauhtd_entry_rif 8119 * Dump only if RIF has value of entry_rif 8120 * Reserved if filter_fields bit3 is '0' 8121 * Access: Index 8122 */ 8123 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8124 8125 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8126 enum mlxsw_reg_rauhtd_type type) 8127 { 8128 MLXSW_REG_ZERO(rauhtd, payload); 8129 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8130 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8131 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8132 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8133 mlxsw_reg_rauhtd_type_set(payload, type); 8134 } 8135 8136 /* reg_rauhtd_ipv4_rec_num_entries 8137 * Number of valid entries in this record: 8138 * 0 - 1 valid entry 8139 * 1 - 2 valid entries 8140 * 2 - 3 valid entries 8141 * 3 - 4 valid entries 8142 * Access: RO 8143 */ 8144 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8145 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8146 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8147 8148 /* reg_rauhtd_rec_type 8149 * Record type. 8150 * 0 - IPv4 8151 * 1 - IPv6 8152 * Access: RO 8153 */ 8154 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8155 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8156 8157 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8158 8159 /* reg_rauhtd_ipv4_ent_a 8160 * Activity. Set for new entries. Set if a packet lookup has hit on the 8161 * specific entry. 8162 * Access: RO 8163 */ 8164 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8165 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8166 8167 /* reg_rauhtd_ipv4_ent_rif 8168 * Router interface. 8169 * Access: RO 8170 */ 8171 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8172 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8173 8174 /* reg_rauhtd_ipv4_ent_dip 8175 * Destination IPv4 address. 8176 * Access: RO 8177 */ 8178 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8179 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8180 8181 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8182 8183 /* reg_rauhtd_ipv6_ent_a 8184 * Activity. Set for new entries. Set if a packet lookup has hit on the 8185 * specific entry. 8186 * Access: RO 8187 */ 8188 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8189 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8190 8191 /* reg_rauhtd_ipv6_ent_rif 8192 * Router interface. 8193 * Access: RO 8194 */ 8195 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8196 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8197 8198 /* reg_rauhtd_ipv6_ent_dip 8199 * Destination IPv6 address. 8200 * Access: RO 8201 */ 8202 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8203 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8204 8205 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8206 int ent_index, u16 *p_rif, 8207 u32 *p_dip) 8208 { 8209 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8210 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8211 } 8212 8213 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8214 int rec_index, u16 *p_rif, 8215 char *p_dip) 8216 { 8217 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8218 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8219 } 8220 8221 /* RTDP - Routing Tunnel Decap Properties Register 8222 * ----------------------------------------------- 8223 * The RTDP register is used for configuring the tunnel decap properties of NVE 8224 * and IPinIP. 8225 */ 8226 #define MLXSW_REG_RTDP_ID 0x8020 8227 #define MLXSW_REG_RTDP_LEN 0x44 8228 8229 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8230 8231 enum mlxsw_reg_rtdp_type { 8232 MLXSW_REG_RTDP_TYPE_NVE, 8233 MLXSW_REG_RTDP_TYPE_IPIP, 8234 }; 8235 8236 /* reg_rtdp_type 8237 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8238 * Access: RW 8239 */ 8240 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8241 8242 /* reg_rtdp_tunnel_index 8243 * Index to the Decap entry. 8244 * For Spectrum, Index to KVD Linear. 8245 * Access: Index 8246 */ 8247 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8248 8249 /* reg_rtdp_egress_router_interface 8250 * Underlay egress router interface. 8251 * Valid range is from 0 to cap_max_router_interfaces - 1 8252 * Access: RW 8253 */ 8254 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8255 8256 /* IPinIP */ 8257 8258 /* reg_rtdp_ipip_irif 8259 * Ingress Router Interface for the overlay router 8260 * Access: RW 8261 */ 8262 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8263 8264 enum mlxsw_reg_rtdp_ipip_sip_check { 8265 /* No sip checks. */ 8266 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8267 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8268 * equal ipv4_usip. 8269 */ 8270 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8271 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8272 * equal ipv6_usip. 8273 */ 8274 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8275 }; 8276 8277 /* reg_rtdp_ipip_sip_check 8278 * SIP check to perform. If decapsulation failed due to these configurations 8279 * then trap_id is IPIP_DECAP_ERROR. 8280 * Access: RW 8281 */ 8282 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8283 8284 /* If set, allow decapsulation of IPinIP (without GRE). */ 8285 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8286 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8287 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8288 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8289 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8290 8291 /* reg_rtdp_ipip_type_check 8292 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8293 * these configurations then trap_id is IPIP_DECAP_ERROR. 8294 * Access: RW 8295 */ 8296 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8297 8298 /* reg_rtdp_ipip_gre_key_check 8299 * Whether GRE key should be checked. When check is enabled: 8300 * - A packet received as IPinIP (without GRE) will always pass. 8301 * - A packet received as IPinGREinIP without a key will not pass the check. 8302 * - A packet received as IPinGREinIP with a key will pass the check only if the 8303 * key in the packet is equal to expected_gre_key. 8304 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8305 * Access: RW 8306 */ 8307 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8308 8309 /* reg_rtdp_ipip_ipv4_usip 8310 * Underlay IPv4 address for ipv4 source address check. 8311 * Reserved when sip_check is not '1'. 8312 * Access: RW 8313 */ 8314 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8315 8316 /* reg_rtdp_ipip_ipv6_usip_ptr 8317 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8318 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8319 * is to the KVD linear. 8320 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8321 * Access: RW 8322 */ 8323 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8324 8325 /* reg_rtdp_ipip_expected_gre_key 8326 * GRE key for checking. 8327 * Reserved when gre_key_check is '0'. 8328 * Access: RW 8329 */ 8330 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8331 8332 static inline void mlxsw_reg_rtdp_pack(char *payload, 8333 enum mlxsw_reg_rtdp_type type, 8334 u32 tunnel_index) 8335 { 8336 MLXSW_REG_ZERO(rtdp, payload); 8337 mlxsw_reg_rtdp_type_set(payload, type); 8338 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8339 } 8340 8341 static inline void 8342 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8343 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8344 unsigned int type_check, bool gre_key_check, 8345 u32 expected_gre_key) 8346 { 8347 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8348 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8349 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8350 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8351 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8352 } 8353 8354 static inline void 8355 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8356 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8357 unsigned int type_check, bool gre_key_check, 8358 u32 ipv4_usip, u32 expected_gre_key) 8359 { 8360 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8361 gre_key_check, expected_gre_key); 8362 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8363 } 8364 8365 static inline void 8366 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8367 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8368 unsigned int type_check, bool gre_key_check, 8369 u32 ipv6_usip_ptr, u32 expected_gre_key) 8370 { 8371 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8372 gre_key_check, expected_gre_key); 8373 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8374 } 8375 8376 /* RIPS - Router IP version Six Register 8377 * ------------------------------------- 8378 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8379 * IPinIP 8380 */ 8381 #define MLXSW_REG_RIPS_ID 0x8021 8382 #define MLXSW_REG_RIPS_LEN 0x14 8383 8384 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8385 8386 /* reg_rips_index 8387 * Index to IPv6 address. 8388 * For Spectrum, the index is to the KVD linear. 8389 * Access: Index 8390 */ 8391 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8392 8393 /* reg_rips_ipv6 8394 * IPv6 address 8395 * Access: RW 8396 */ 8397 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8398 8399 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8400 const struct in6_addr *ipv6) 8401 { 8402 MLXSW_REG_ZERO(rips, payload); 8403 mlxsw_reg_rips_index_set(payload, index); 8404 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8405 } 8406 8407 /* RATRAD - Router Adjacency Table Activity Dump Register 8408 * ------------------------------------------------------ 8409 * The RATRAD register is used to dump and optionally clear activity bits of 8410 * router adjacency table entries. 8411 */ 8412 #define MLXSW_REG_RATRAD_ID 0x8022 8413 #define MLXSW_REG_RATRAD_LEN 0x210 8414 8415 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8416 8417 enum { 8418 /* Read activity */ 8419 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8420 /* Read and clear activity */ 8421 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8422 }; 8423 8424 /* reg_ratrad_op 8425 * Access: Operation 8426 */ 8427 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8428 8429 /* reg_ratrad_ecmp_size 8430 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8431 * ranges: 8432 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8433 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8434 * Access: Index 8435 */ 8436 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8437 8438 /* reg_ratrad_adjacency_index 8439 * Index into the adjacency table. 8440 * Access: Index 8441 */ 8442 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8443 8444 /* reg_ratrad_activity_vector 8445 * Activity bit per adjacency index. 8446 * Bits higher than ecmp_size are reserved. 8447 * Access: RO 8448 */ 8449 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8450 8451 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8452 u16 ecmp_size) 8453 { 8454 MLXSW_REG_ZERO(ratrad, payload); 8455 mlxsw_reg_ratrad_op_set(payload, 8456 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8457 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8458 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8459 } 8460 8461 /* RIGR-V2 - Router Interface Group Register Version 2 8462 * --------------------------------------------------- 8463 * The RIGR_V2 register is used to add, remove and query egress interface list 8464 * of a multicast forwarding entry. 8465 */ 8466 #define MLXSW_REG_RIGR2_ID 0x8023 8467 #define MLXSW_REG_RIGR2_LEN 0xB0 8468 8469 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8470 8471 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8472 8473 /* reg_rigr2_rigr_index 8474 * KVD Linear index. 8475 * Access: Index 8476 */ 8477 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8478 8479 /* reg_rigr2_vnext 8480 * Next RIGR Index is valid. 8481 * Access: RW 8482 */ 8483 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8484 8485 /* reg_rigr2_next_rigr_index 8486 * Next RIGR Index. The index is to the KVD linear. 8487 * Reserved when vnxet = '0'. 8488 * Access: RW 8489 */ 8490 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8491 8492 /* reg_rigr2_vrmid 8493 * RMID Index is valid. 8494 * Access: RW 8495 */ 8496 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8497 8498 /* reg_rigr2_rmid_index 8499 * RMID Index. 8500 * Range 0 .. max_mid - 1 8501 * Reserved when vrmid = '0'. 8502 * The index is to the Port Group Table (PGT) 8503 * Access: RW 8504 */ 8505 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8506 8507 /* reg_rigr2_erif_entry_v 8508 * Egress Router Interface is valid. 8509 * Note that low-entries must be set if high-entries are set. For 8510 * example: if erif_entry[2].v is set then erif_entry[1].v and 8511 * erif_entry[0].v must be set. 8512 * Index can be from 0 to cap_mc_erif_list_entries-1 8513 * Access: RW 8514 */ 8515 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8516 8517 /* reg_rigr2_erif_entry_erif 8518 * Egress Router Interface. 8519 * Valid range is from 0 to cap_max_router_interfaces - 1 8520 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8521 * Access: RW 8522 */ 8523 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8524 8525 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8526 bool vnext, u32 next_rigr_index) 8527 { 8528 MLXSW_REG_ZERO(rigr2, payload); 8529 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8530 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8531 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8532 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8533 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8534 } 8535 8536 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8537 bool v, u16 erif) 8538 { 8539 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8540 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8541 } 8542 8543 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8544 * ------------------------------------------------------ 8545 */ 8546 #define MLXSW_REG_RECR2_ID 0x8025 8547 #define MLXSW_REG_RECR2_LEN 0x38 8548 8549 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8550 8551 /* reg_recr2_pp 8552 * Per-port configuration 8553 * Access: Index 8554 */ 8555 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8556 8557 /* reg_recr2_sh 8558 * Symmetric hash 8559 * Access: RW 8560 */ 8561 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8562 8563 /* reg_recr2_seed 8564 * Seed 8565 * Access: RW 8566 */ 8567 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8568 8569 enum { 8570 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8571 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8572 /* Enable IPv4 fields if packet is TCP or UDP */ 8573 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8574 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8575 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8576 /* Enable IPv6 fields if packet is TCP or UDP */ 8577 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8578 /* Enable TCP/UDP header fields if packet is IPv4 */ 8579 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8580 /* Enable TCP/UDP header fields if packet is IPv6 */ 8581 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8582 8583 __MLXSW_REG_RECR2_HEADER_CNT, 8584 }; 8585 8586 /* reg_recr2_outer_header_enables 8587 * Bit mask where each bit enables a specific layer to be included in 8588 * the hash calculation. 8589 * Access: RW 8590 */ 8591 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8592 8593 enum { 8594 /* IPv4 Source IP */ 8595 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8596 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8597 /* IPv4 Destination IP */ 8598 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8599 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8600 /* IP Protocol */ 8601 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8602 /* IPv6 Source IP */ 8603 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8604 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8605 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8606 /* IPv6 Destination IP */ 8607 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8608 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8609 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8610 /* IPv6 Next Header */ 8611 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8612 /* IPv6 Flow Label */ 8613 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8614 /* TCP/UDP Source Port */ 8615 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8616 /* TCP/UDP Destination Port */ 8617 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8618 8619 __MLXSW_REG_RECR2_FIELD_CNT, 8620 }; 8621 8622 /* reg_recr2_outer_header_fields_enable 8623 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8624 * Access: RW 8625 */ 8626 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8627 8628 /* reg_recr2_inner_header_enables 8629 * Bit mask where each bit enables a specific inner layer to be included in the 8630 * hash calculation. Same values as reg_recr2_outer_header_enables. 8631 * Access: RW 8632 */ 8633 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8634 8635 enum { 8636 /* Inner IPv4 Source IP */ 8637 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8638 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8639 /* Inner IPv4 Destination IP */ 8640 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8641 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8642 /* Inner IP Protocol */ 8643 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8644 /* Inner IPv6 Source IP */ 8645 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8646 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8647 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8648 /* Inner IPv6 Destination IP */ 8649 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8650 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8651 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8652 /* Inner IPv6 Next Header */ 8653 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8654 /* Inner IPv6 Flow Label */ 8655 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8656 /* Inner TCP/UDP Source Port */ 8657 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8658 /* Inner TCP/UDP Destination Port */ 8659 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8660 8661 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8662 }; 8663 8664 /* reg_recr2_inner_header_fields_enable 8665 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8666 * Access: RW 8667 */ 8668 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8669 8670 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8671 { 8672 MLXSW_REG_ZERO(recr2, payload); 8673 mlxsw_reg_recr2_pp_set(payload, false); 8674 mlxsw_reg_recr2_sh_set(payload, true); 8675 mlxsw_reg_recr2_seed_set(payload, seed); 8676 } 8677 8678 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8679 * -------------------------------------------------------------- 8680 * The RMFT_V2 register is used to configure and query the multicast table. 8681 */ 8682 #define MLXSW_REG_RMFT2_ID 0x8027 8683 #define MLXSW_REG_RMFT2_LEN 0x174 8684 8685 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8686 8687 /* reg_rmft2_v 8688 * Valid 8689 * Access: RW 8690 */ 8691 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8692 8693 enum mlxsw_reg_rmft2_type { 8694 MLXSW_REG_RMFT2_TYPE_IPV4, 8695 MLXSW_REG_RMFT2_TYPE_IPV6 8696 }; 8697 8698 /* reg_rmft2_type 8699 * Access: Index 8700 */ 8701 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8702 8703 enum mlxsw_sp_reg_rmft2_op { 8704 /* For Write: 8705 * Write operation. Used to write a new entry to the table. All RW 8706 * fields are relevant for new entry. Activity bit is set for new 8707 * entries - Note write with v (Valid) 0 will delete the entry. 8708 * For Query: 8709 * Read operation 8710 */ 8711 MLXSW_REG_RMFT2_OP_READ_WRITE, 8712 }; 8713 8714 /* reg_rmft2_op 8715 * Operation. 8716 * Access: OP 8717 */ 8718 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8719 8720 /* reg_rmft2_a 8721 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8722 * entry. 8723 * Access: RO 8724 */ 8725 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8726 8727 /* reg_rmft2_offset 8728 * Offset within the multicast forwarding table to write to. 8729 * Access: Index 8730 */ 8731 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8732 8733 /* reg_rmft2_virtual_router 8734 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8735 * Access: RW 8736 */ 8737 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8738 8739 enum mlxsw_reg_rmft2_irif_mask { 8740 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8741 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8742 }; 8743 8744 /* reg_rmft2_irif_mask 8745 * Ingress RIF mask. 8746 * Access: RW 8747 */ 8748 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8749 8750 /* reg_rmft2_irif 8751 * Ingress RIF index. 8752 * Access: RW 8753 */ 8754 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8755 8756 /* reg_rmft2_dip{4,6} 8757 * Destination IPv4/6 address 8758 * Access: RW 8759 */ 8760 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8761 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8762 8763 /* reg_rmft2_dip{4,6}_mask 8764 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8765 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8766 * Access: RW 8767 */ 8768 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8769 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8770 8771 /* reg_rmft2_sip{4,6} 8772 * Source IPv4/6 address 8773 * Access: RW 8774 */ 8775 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8776 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8777 8778 /* reg_rmft2_sip{4,6}_mask 8779 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8780 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8781 * Access: RW 8782 */ 8783 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8784 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8785 8786 /* reg_rmft2_flexible_action_set 8787 * ACL action set. The only supported action types in this field and in any 8788 * action-set pointed from here are as follows: 8789 * 00h: ACTION_NULL 8790 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8791 * 03h: ACTION_TRAP 8792 * 06h: ACTION_QOS 8793 * 08h: ACTION_POLICING_MONITORING 8794 * 10h: ACTION_ROUTER_MC 8795 * Access: RW 8796 */ 8797 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8798 MLXSW_REG_FLEX_ACTION_SET_LEN); 8799 8800 static inline void 8801 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8802 u16 virtual_router, 8803 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8804 const char *flex_action_set) 8805 { 8806 MLXSW_REG_ZERO(rmft2, payload); 8807 mlxsw_reg_rmft2_v_set(payload, v); 8808 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8809 mlxsw_reg_rmft2_offset_set(payload, offset); 8810 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8811 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8812 mlxsw_reg_rmft2_irif_set(payload, irif); 8813 if (flex_action_set) 8814 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8815 flex_action_set); 8816 } 8817 8818 static inline void 8819 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8820 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8821 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8822 const char *flexible_action_set) 8823 { 8824 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8825 irif_mask, irif, flexible_action_set); 8826 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8827 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8828 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8829 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8830 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8831 } 8832 8833 static inline void 8834 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8835 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8836 struct in6_addr dip6, struct in6_addr dip6_mask, 8837 struct in6_addr sip6, struct in6_addr sip6_mask, 8838 const char *flexible_action_set) 8839 { 8840 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8841 irif_mask, irif, flexible_action_set); 8842 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8843 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8844 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8845 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8846 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8847 } 8848 8849 /* RXLTE - Router XLT Enable Register 8850 * ---------------------------------- 8851 * The RXLTE enables XLT (eXtended Lookup Table) LPM lookups if a capable 8852 * XM is present on the system. 8853 */ 8854 8855 #define MLXSW_REG_RXLTE_ID 0x8050 8856 #define MLXSW_REG_RXLTE_LEN 0x0C 8857 8858 MLXSW_REG_DEFINE(rxlte, MLXSW_REG_RXLTE_ID, MLXSW_REG_RXLTE_LEN); 8859 8860 /* reg_rxlte_virtual_router 8861 * Virtual router ID associated with the router interface. 8862 * Range is 0..cap_max_virtual_routers-1 8863 * Access: Index 8864 */ 8865 MLXSW_ITEM32(reg, rxlte, virtual_router, 0x00, 0, 16); 8866 8867 enum mlxsw_reg_rxlte_protocol { 8868 MLXSW_REG_RXLTE_PROTOCOL_IPV4, 8869 MLXSW_REG_RXLTE_PROTOCOL_IPV6, 8870 }; 8871 8872 /* reg_rxlte_protocol 8873 * Access: Index 8874 */ 8875 MLXSW_ITEM32(reg, rxlte, protocol, 0x04, 0, 4); 8876 8877 /* reg_rxlte_lpm_xlt_en 8878 * Access: RW 8879 */ 8880 MLXSW_ITEM32(reg, rxlte, lpm_xlt_en, 0x08, 0, 1); 8881 8882 static inline void mlxsw_reg_rxlte_pack(char *payload, u16 virtual_router, 8883 enum mlxsw_reg_rxlte_protocol protocol, 8884 bool lpm_xlt_en) 8885 { 8886 MLXSW_REG_ZERO(rxlte, payload); 8887 mlxsw_reg_rxlte_virtual_router_set(payload, virtual_router); 8888 mlxsw_reg_rxlte_protocol_set(payload, protocol); 8889 mlxsw_reg_rxlte_lpm_xlt_en_set(payload, lpm_xlt_en); 8890 } 8891 8892 /* RXLTM - Router XLT M select Register 8893 * ------------------------------------ 8894 * The RXLTM configures and selects the M for the XM lookups. 8895 */ 8896 8897 #define MLXSW_REG_RXLTM_ID 0x8051 8898 #define MLXSW_REG_RXLTM_LEN 0x14 8899 8900 MLXSW_REG_DEFINE(rxltm, MLXSW_REG_RXLTM_ID, MLXSW_REG_RXLTM_LEN); 8901 8902 /* reg_rxltm_m0_val_v6 8903 * Global M0 value For IPv6. 8904 * Range 0..128 8905 * Access: RW 8906 */ 8907 MLXSW_ITEM32(reg, rxltm, m0_val_v6, 0x10, 16, 8); 8908 8909 /* reg_rxltm_m0_val_v4 8910 * Global M0 value For IPv4. 8911 * Range 0..32 8912 * Access: RW 8913 */ 8914 MLXSW_ITEM32(reg, rxltm, m0_val_v4, 0x10, 0, 6); 8915 8916 static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v6) 8917 { 8918 MLXSW_REG_ZERO(rxltm, payload); 8919 mlxsw_reg_rxltm_m0_val_v6_set(payload, m0_val_v6); 8920 mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4); 8921 } 8922 8923 /* RLCMLD - Router LPM Cache ML Delete Register 8924 * -------------------------------------------- 8925 * The RLCMLD register is used to bulk delete the XLT-LPM cache ML entries. 8926 * This can be used by SW when L is increased or decreased, thus need to 8927 * remove entries with old ML values. 8928 */ 8929 8930 #define MLXSW_REG_RLCMLD_ID 0x8055 8931 #define MLXSW_REG_RLCMLD_LEN 0x30 8932 8933 MLXSW_REG_DEFINE(rlcmld, MLXSW_REG_RLCMLD_ID, MLXSW_REG_RLCMLD_LEN); 8934 8935 enum mlxsw_reg_rlcmld_select { 8936 MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES, 8937 MLXSW_REG_RLCMLD_SELECT_M_ENTRIES, 8938 MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES, 8939 }; 8940 8941 /* reg_rlcmld_select 8942 * Which entries to delete. 8943 * Access: Index 8944 */ 8945 MLXSW_ITEM32(reg, rlcmld, select, 0x00, 16, 2); 8946 8947 enum mlxsw_reg_rlcmld_filter_fields { 8948 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL = 0x04, 8949 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER = 0x08, 8950 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP = 0x10, 8951 }; 8952 8953 /* reg_rlcmld_filter_fields 8954 * If a bit is '0' then the relevant field is ignored. 8955 * Access: Index 8956 */ 8957 MLXSW_ITEM32(reg, rlcmld, filter_fields, 0x00, 0, 8); 8958 8959 enum mlxsw_reg_rlcmld_protocol { 8960 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, 8961 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, 8962 }; 8963 8964 /* reg_rlcmld_protocol 8965 * Access: Index 8966 */ 8967 MLXSW_ITEM32(reg, rlcmld, protocol, 0x08, 0, 4); 8968 8969 /* reg_rlcmld_virtual_router 8970 * Virtual router ID. 8971 * Range is 0..cap_max_virtual_routers-1 8972 * Access: Index 8973 */ 8974 MLXSW_ITEM32(reg, rlcmld, virtual_router, 0x0C, 0, 16); 8975 8976 /* reg_rlcmld_dip 8977 * The prefix of the route or of the marker that the object of the LPM 8978 * is compared with. The most significant bits of the dip are the prefix. 8979 * Access: Index 8980 */ 8981 MLXSW_ITEM32(reg, rlcmld, dip4, 0x1C, 0, 32); 8982 MLXSW_ITEM_BUF(reg, rlcmld, dip6, 0x10, 16); 8983 8984 /* reg_rlcmld_dip_mask 8985 * per bit: 8986 * 0: no match 8987 * 1: match 8988 * Access: Index 8989 */ 8990 MLXSW_ITEM32(reg, rlcmld, dip_mask4, 0x2C, 0, 32); 8991 MLXSW_ITEM_BUF(reg, rlcmld, dip_mask6, 0x20, 16); 8992 8993 static inline void __mlxsw_reg_rlcmld_pack(char *payload, 8994 enum mlxsw_reg_rlcmld_select select, 8995 enum mlxsw_reg_rlcmld_protocol protocol, 8996 u16 virtual_router) 8997 { 8998 u8 filter_fields = MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL | 8999 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER | 9000 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP; 9001 9002 MLXSW_REG_ZERO(rlcmld, payload); 9003 mlxsw_reg_rlcmld_select_set(payload, select); 9004 mlxsw_reg_rlcmld_filter_fields_set(payload, filter_fields); 9005 mlxsw_reg_rlcmld_protocol_set(payload, protocol); 9006 mlxsw_reg_rlcmld_virtual_router_set(payload, virtual_router); 9007 } 9008 9009 static inline void mlxsw_reg_rlcmld_pack4(char *payload, 9010 enum mlxsw_reg_rlcmld_select select, 9011 u16 virtual_router, 9012 u32 dip, u32 dip_mask) 9013 { 9014 __mlxsw_reg_rlcmld_pack(payload, select, 9015 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4, 9016 virtual_router); 9017 mlxsw_reg_rlcmld_dip4_set(payload, dip); 9018 mlxsw_reg_rlcmld_dip_mask4_set(payload, dip_mask); 9019 } 9020 9021 static inline void mlxsw_reg_rlcmld_pack6(char *payload, 9022 enum mlxsw_reg_rlcmld_select select, 9023 u16 virtual_router, 9024 const void *dip, const void *dip_mask) 9025 { 9026 __mlxsw_reg_rlcmld_pack(payload, select, 9027 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6, 9028 virtual_router); 9029 mlxsw_reg_rlcmld_dip6_memcpy_to(payload, dip); 9030 mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask); 9031 } 9032 9033 /* RLPMCE - Router LPM Cache Enable Register 9034 * ----------------------------------------- 9035 * Allows disabling the LPM cache. Can be changed on the fly. 9036 */ 9037 9038 #define MLXSW_REG_RLPMCE_ID 0x8056 9039 #define MLXSW_REG_RLPMCE_LEN 0x4 9040 9041 MLXSW_REG_DEFINE(rlpmce, MLXSW_REG_RLPMCE_ID, MLXSW_REG_RLPMCE_LEN); 9042 9043 /* reg_rlpmce_flush 9044 * Flush: 9045 * 0: do not flush the cache (default) 9046 * 1: flush (clear) the cache 9047 * Access: WO 9048 */ 9049 MLXSW_ITEM32(reg, rlpmce, flush, 0x00, 4, 1); 9050 9051 /* reg_rlpmce_disable 9052 * LPM cache: 9053 * 0: enabled (default) 9054 * 1: disabled 9055 * Access: RW 9056 */ 9057 MLXSW_ITEM32(reg, rlpmce, disable, 0x00, 0, 1); 9058 9059 static inline void mlxsw_reg_rlpmce_pack(char *payload, bool flush, 9060 bool disable) 9061 { 9062 MLXSW_REG_ZERO(rlpmce, payload); 9063 mlxsw_reg_rlpmce_flush_set(payload, flush); 9064 mlxsw_reg_rlpmce_disable_set(payload, disable); 9065 } 9066 9067 /* Note that XLTQ, XMDR, XRMT and XRALXX register positions violate the rule 9068 * of ordering register definitions by the ID. However, XRALXX pack helpers are 9069 * using RALXX pack helpers, RALXX registers have higher IDs. 9070 * Also XMDR is using RALUE enums. XLRQ and XRMT are just put alongside with the 9071 * related registers. 9072 */ 9073 9074 /* XLTQ - XM Lookup Table Query Register 9075 * ------------------------------------- 9076 */ 9077 #define MLXSW_REG_XLTQ_ID 0x7802 9078 #define MLXSW_REG_XLTQ_LEN 0x2C 9079 9080 MLXSW_REG_DEFINE(xltq, MLXSW_REG_XLTQ_ID, MLXSW_REG_XLTQ_LEN); 9081 9082 enum mlxsw_reg_xltq_xm_device_id { 9083 MLXSW_REG_XLTQ_XM_DEVICE_ID_UNKNOWN, 9084 MLXSW_REG_XLTQ_XM_DEVICE_ID_XLT = 0xCF71, 9085 }; 9086 9087 /* reg_xltq_xm_device_id 9088 * XM device ID. 9089 * Access: RO 9090 */ 9091 MLXSW_ITEM32(reg, xltq, xm_device_id, 0x04, 0, 16); 9092 9093 /* reg_xltq_xlt_cap_ipv4_lpm 9094 * Access: RO 9095 */ 9096 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv4_lpm, 0x10, 0, 1); 9097 9098 /* reg_xltq_xlt_cap_ipv6_lpm 9099 * Access: RO 9100 */ 9101 MLXSW_ITEM32(reg, xltq, xlt_cap_ipv6_lpm, 0x10, 1, 1); 9102 9103 /* reg_xltq_cap_xlt_entries 9104 * Number of XLT entries 9105 * Note: SW must not fill more than 80% in order to avoid overflow 9106 * Access: RO 9107 */ 9108 MLXSW_ITEM32(reg, xltq, cap_xlt_entries, 0x20, 0, 32); 9109 9110 /* reg_xltq_cap_xlt_mtable 9111 * XLT M-Table max size 9112 * Access: RO 9113 */ 9114 MLXSW_ITEM32(reg, xltq, cap_xlt_mtable, 0x24, 0, 32); 9115 9116 static inline void mlxsw_reg_xltq_pack(char *payload) 9117 { 9118 MLXSW_REG_ZERO(xltq, payload); 9119 } 9120 9121 static inline void mlxsw_reg_xltq_unpack(char *payload, u16 *xm_device_id, bool *xlt_cap_ipv4_lpm, 9122 bool *xlt_cap_ipv6_lpm, u32 *cap_xlt_entries, 9123 u32 *cap_xlt_mtable) 9124 { 9125 *xm_device_id = mlxsw_reg_xltq_xm_device_id_get(payload); 9126 *xlt_cap_ipv4_lpm = mlxsw_reg_xltq_xlt_cap_ipv4_lpm_get(payload); 9127 *xlt_cap_ipv6_lpm = mlxsw_reg_xltq_xlt_cap_ipv6_lpm_get(payload); 9128 *cap_xlt_entries = mlxsw_reg_xltq_cap_xlt_entries_get(payload); 9129 *cap_xlt_mtable = mlxsw_reg_xltq_cap_xlt_mtable_get(payload); 9130 } 9131 9132 /* XMDR - XM Direct Register 9133 * ------------------------- 9134 * The XMDR allows direct access to the XM device via the switch. 9135 * Working in synchronous mode. FW waits for response from the XLT 9136 * for each command. FW acks the XMDR accordingly. 9137 */ 9138 #define MLXSW_REG_XMDR_ID 0x7803 9139 #define MLXSW_REG_XMDR_BASE_LEN 0x20 9140 #define MLXSW_REG_XMDR_TRANS_LEN 0x80 9141 #define MLXSW_REG_XMDR_LEN (MLXSW_REG_XMDR_BASE_LEN + \ 9142 MLXSW_REG_XMDR_TRANS_LEN) 9143 9144 MLXSW_REG_DEFINE(xmdr, MLXSW_REG_XMDR_ID, MLXSW_REG_XMDR_LEN); 9145 9146 /* reg_xmdr_bulk_entry 9147 * Bulk_entry 9148 * 0: Last entry - immediate flush of XRT-cache 9149 * 1: Bulk entry - do not flush the XRT-cache 9150 * Access: OP 9151 */ 9152 MLXSW_ITEM32(reg, xmdr, bulk_entry, 0x04, 8, 1); 9153 9154 /* reg_xmdr_num_rec 9155 * Number of records for Direct access to XM 9156 * Supported: 0..4 commands (except NOP which is a filler) 9157 * 0 commands is reserved when bulk_entry = 1. 9158 * 0 commands is allowed when bulk_entry = 0 for immediate XRT-cache flush. 9159 * Access: OP 9160 */ 9161 MLXSW_ITEM32(reg, xmdr, num_rec, 0x04, 0, 4); 9162 9163 /* reg_xmdr_reply_vect 9164 * Reply Vector 9165 * Bit i for command index i+1 9166 * values per bit: 9167 * 0: failed 9168 * 1: succeeded 9169 * e.g. if commands 1, 2, 4 succeeded and command 3 failed then binary 9170 * value will be 0b1011 9171 * Access: RO 9172 */ 9173 MLXSW_ITEM_BIT_ARRAY(reg, xmdr, reply_vect, 0x08, 4, 1); 9174 9175 static inline void mlxsw_reg_xmdr_pack(char *payload, bool bulk_entry) 9176 { 9177 MLXSW_REG_ZERO(xmdr, payload); 9178 mlxsw_reg_xmdr_bulk_entry_set(payload, bulk_entry); 9179 } 9180 9181 enum mlxsw_reg_xmdr_c_cmd_id { 9182 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4 = 0x30, 9183 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6 = 0x31, 9184 }; 9185 9186 #define MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN 32 9187 #define MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN 48 9188 9189 /* reg_xmdr_c_cmd_id 9190 */ 9191 MLXSW_ITEM32(reg, xmdr_c, cmd_id, 0x00, 24, 8); 9192 9193 /* reg_xmdr_c_seq_number 9194 */ 9195 MLXSW_ITEM32(reg, xmdr_c, seq_number, 0x00, 12, 12); 9196 9197 enum mlxsw_reg_xmdr_c_ltr_op { 9198 /* Activity is set */ 9199 MLXSW_REG_XMDR_C_LTR_OP_WRITE = 0, 9200 /* There is no update mask. All fields are updated. */ 9201 MLXSW_REG_XMDR_C_LTR_OP_UPDATE = 1, 9202 MLXSW_REG_XMDR_C_LTR_OP_DELETE = 2, 9203 }; 9204 9205 /* reg_xmdr_c_ltr_op 9206 * Operation. 9207 */ 9208 MLXSW_ITEM32(reg, xmdr_c, ltr_op, 0x04, 24, 8); 9209 9210 /* reg_xmdr_c_ltr_trap_action 9211 * Trap action. 9212 * Values are defined in enum mlxsw_reg_ralue_trap_action. 9213 */ 9214 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_action, 0x04, 20, 4); 9215 9216 enum mlxsw_reg_xmdr_c_ltr_trap_id_num { 9217 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS0, 9218 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS1, 9219 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS2, 9220 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS3, 9221 }; 9222 9223 /* reg_xmdr_c_ltr_trap_id_num 9224 * Trap-ID number. 9225 */ 9226 MLXSW_ITEM32(reg, xmdr_c, ltr_trap_id_num, 0x04, 16, 4); 9227 9228 /* reg_xmdr_c_ltr_virtual_router 9229 * Virtual Router ID. 9230 * Range is 0..cap_max_virtual_routers-1 9231 */ 9232 MLXSW_ITEM32(reg, xmdr_c, ltr_virtual_router, 0x04, 0, 16); 9233 9234 /* reg_xmdr_c_ltr_prefix_len 9235 * Number of bits in the prefix of the LPM route. 9236 */ 9237 MLXSW_ITEM32(reg, xmdr_c, ltr_prefix_len, 0x08, 24, 8); 9238 9239 /* reg_xmdr_c_ltr_bmp_len 9240 * The best match prefix length in the case that there is no match for 9241 * longer prefixes. 9242 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 9243 */ 9244 MLXSW_ITEM32(reg, xmdr_c, ltr_bmp_len, 0x08, 16, 8); 9245 9246 /* reg_xmdr_c_ltr_entry_type 9247 * Entry type. 9248 * Values are defined in enum mlxsw_reg_ralue_entry_type. 9249 */ 9250 MLXSW_ITEM32(reg, xmdr_c, ltr_entry_type, 0x08, 4, 4); 9251 9252 enum mlxsw_reg_xmdr_c_ltr_action_type { 9253 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL, 9254 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE, 9255 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME, 9256 }; 9257 9258 /* reg_xmdr_c_ltr_action_type 9259 * Action Type. 9260 */ 9261 MLXSW_ITEM32(reg, xmdr_c, ltr_action_type, 0x08, 0, 4); 9262 9263 /* reg_xmdr_c_ltr_erif 9264 * Egress Router Interface. 9265 * Only relevant in case of LOCAL action. 9266 */ 9267 MLXSW_ITEM32(reg, xmdr_c, ltr_erif, 0x10, 0, 16); 9268 9269 /* reg_xmdr_c_ltr_adjacency_index 9270 * Points to the first entry of the group-based ECMP. 9271 * Only relevant in case of REMOTE action. 9272 */ 9273 MLXSW_ITEM32(reg, xmdr_c, ltr_adjacency_index, 0x10, 0, 24); 9274 9275 #define MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC 0xFFFFFF 9276 9277 /* reg_xmdr_c_ltr_pointer_to_tunnel 9278 * Only relevant in case of IP2ME action. 9279 */ 9280 MLXSW_ITEM32(reg, xmdr_c, ltr_pointer_to_tunnel, 0x10, 0, 24); 9281 9282 /* reg_xmdr_c_ltr_ecmp_size 9283 * Amount of sequential entries starting 9284 * from the adjacency_index (the number of ECMPs). 9285 * The valid range is 1-64, 512, 1024, 2048 and 4096. 9286 * Only relevant in case of REMOTE action. 9287 */ 9288 MLXSW_ITEM32(reg, xmdr_c, ltr_ecmp_size, 0x14, 0, 32); 9289 9290 /* reg_xmdr_c_ltr_dip* 9291 * The prefix of the route or of the marker that the object of the LPM 9292 * is compared with. The most significant bits of the dip are the prefix. 9293 * The least significant bits must be '0' if the prefix_len is smaller 9294 * than 128 for IPv6 or smaller than 32 for IPv4. 9295 */ 9296 MLXSW_ITEM32(reg, xmdr_c, ltr_dip4, 0x1C, 0, 32); 9297 MLXSW_ITEM_BUF(reg, xmdr_c, ltr_dip6, 0x1C, 16); 9298 9299 static inline void 9300 mlxsw_reg_xmdr_c_ltr_pack(char *xmdr_payload, unsigned int trans_offset, 9301 enum mlxsw_reg_xmdr_c_cmd_id cmd_id, u16 seq_number, 9302 enum mlxsw_reg_xmdr_c_ltr_op op, u16 virtual_router, 9303 u8 prefix_len) 9304 { 9305 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9306 u8 num_rec = mlxsw_reg_xmdr_num_rec_get(xmdr_payload); 9307 9308 mlxsw_reg_xmdr_num_rec_set(xmdr_payload, num_rec + 1); 9309 9310 mlxsw_reg_xmdr_c_cmd_id_set(payload, cmd_id); 9311 mlxsw_reg_xmdr_c_seq_number_set(payload, seq_number); 9312 mlxsw_reg_xmdr_c_ltr_op_set(payload, op); 9313 mlxsw_reg_xmdr_c_ltr_virtual_router_set(payload, virtual_router); 9314 mlxsw_reg_xmdr_c_ltr_prefix_len_set(payload, prefix_len); 9315 mlxsw_reg_xmdr_c_ltr_entry_type_set(payload, 9316 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 9317 mlxsw_reg_xmdr_c_ltr_bmp_len_set(payload, prefix_len); 9318 } 9319 9320 static inline unsigned int 9321 mlxsw_reg_xmdr_c_ltr_pack4(char *xmdr_payload, unsigned int trans_offset, 9322 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op, 9323 u16 virtual_router, u8 prefix_len, u32 *dip) 9324 { 9325 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9326 9327 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset, 9328 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4, 9329 seq_number, op, virtual_router, prefix_len); 9330 if (dip) 9331 mlxsw_reg_xmdr_c_ltr_dip4_set(payload, *dip); 9332 return MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN; 9333 } 9334 9335 static inline unsigned int 9336 mlxsw_reg_xmdr_c_ltr_pack6(char *xmdr_payload, unsigned int trans_offset, 9337 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op, 9338 u16 virtual_router, u8 prefix_len, const void *dip) 9339 { 9340 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9341 9342 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset, 9343 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6, 9344 seq_number, op, virtual_router, prefix_len); 9345 if (dip) 9346 mlxsw_reg_xmdr_c_ltr_dip6_memcpy_to(payload, dip); 9347 return MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN; 9348 } 9349 9350 static inline void 9351 mlxsw_reg_xmdr_c_ltr_act_remote_pack(char *xmdr_payload, unsigned int trans_offset, 9352 enum mlxsw_reg_ralue_trap_action trap_action, 9353 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, 9354 u32 adjacency_index, u16 ecmp_size) 9355 { 9356 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9357 9358 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE); 9359 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action); 9360 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num); 9361 mlxsw_reg_xmdr_c_ltr_adjacency_index_set(payload, adjacency_index); 9362 mlxsw_reg_xmdr_c_ltr_ecmp_size_set(payload, ecmp_size); 9363 } 9364 9365 static inline void 9366 mlxsw_reg_xmdr_c_ltr_act_local_pack(char *xmdr_payload, unsigned int trans_offset, 9367 enum mlxsw_reg_ralue_trap_action trap_action, 9368 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, u16 erif) 9369 { 9370 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9371 9372 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL); 9373 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action); 9374 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num); 9375 mlxsw_reg_xmdr_c_ltr_erif_set(payload, erif); 9376 } 9377 9378 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char *xmdr_payload, 9379 unsigned int trans_offset) 9380 { 9381 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9382 9383 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME); 9384 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, 9385 MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC); 9386 } 9387 9388 static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload, 9389 unsigned int trans_offset, 9390 u32 pointer_to_tunnel) 9391 { 9392 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset; 9393 9394 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME); 9395 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel); 9396 } 9397 9398 /* XRMT - XM Router M Table Register 9399 * --------------------------------- 9400 * The XRMT configures the M-Table for the XLT-LPM. 9401 */ 9402 #define MLXSW_REG_XRMT_ID 0x7810 9403 #define MLXSW_REG_XRMT_LEN 0x14 9404 9405 MLXSW_REG_DEFINE(xrmt, MLXSW_REG_XRMT_ID, MLXSW_REG_XRMT_LEN); 9406 9407 /* reg_xrmt_index 9408 * Index in M-Table. 9409 * Range 0..cap_xlt_mtable-1 9410 * Access: Index 9411 */ 9412 MLXSW_ITEM32(reg, xrmt, index, 0x04, 0, 20); 9413 9414 /* reg_xrmt_l0_val 9415 * Access: RW 9416 */ 9417 MLXSW_ITEM32(reg, xrmt, l0_val, 0x10, 24, 8); 9418 9419 static inline void mlxsw_reg_xrmt_pack(char *payload, u32 index, u8 l0_val) 9420 { 9421 MLXSW_REG_ZERO(xrmt, payload); 9422 mlxsw_reg_xrmt_index_set(payload, index); 9423 mlxsw_reg_xrmt_l0_val_set(payload, l0_val); 9424 } 9425 9426 /* XRALTA - XM Router Algorithmic LPM Tree Allocation Register 9427 * ----------------------------------------------------------- 9428 * The XRALTA is used to allocate the XLT LPM trees. 9429 * 9430 * This register embeds original RALTA register. 9431 */ 9432 #define MLXSW_REG_XRALTA_ID 0x7811 9433 #define MLXSW_REG_XRALTA_LEN 0x08 9434 #define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04 9435 9436 MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN); 9437 9438 static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc, 9439 enum mlxsw_reg_ralxx_protocol protocol, 9440 u8 tree_id) 9441 { 9442 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET; 9443 9444 MLXSW_REG_ZERO(xralta, payload); 9445 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id); 9446 } 9447 9448 /* XRALST - XM Router Algorithmic LPM Structure Tree Register 9449 * ---------------------------------------------------------- 9450 * The XRALST is used to set and query the structure of an XLT LPM tree. 9451 * 9452 * This register embeds original RALST register. 9453 */ 9454 #define MLXSW_REG_XRALST_ID 0x7812 9455 #define MLXSW_REG_XRALST_LEN 0x108 9456 #define MLXSW_REG_XRALST_RALST_OFFSET 0x04 9457 9458 MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN); 9459 9460 static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id) 9461 { 9462 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 9463 9464 MLXSW_REG_ZERO(xralst, payload); 9465 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id); 9466 } 9467 9468 static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number, 9469 u8 left_child_bin, 9470 u8 right_child_bin) 9471 { 9472 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 9473 9474 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin, 9475 right_child_bin); 9476 } 9477 9478 /* XRALTB - XM Router Algorithmic LPM Tree Binding Register 9479 * -------------------------------------------------------- 9480 * The XRALTB register is used to bind virtual router and protocol 9481 * to an allocated LPM tree. 9482 * 9483 * This register embeds original RALTB register. 9484 */ 9485 #define MLXSW_REG_XRALTB_ID 0x7813 9486 #define MLXSW_REG_XRALTB_LEN 0x08 9487 #define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04 9488 9489 MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN); 9490 9491 static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router, 9492 enum mlxsw_reg_ralxx_protocol protocol, 9493 u8 tree_id) 9494 { 9495 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET; 9496 9497 MLXSW_REG_ZERO(xraltb, payload); 9498 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id); 9499 } 9500 9501 /* MFCR - Management Fan Control Register 9502 * -------------------------------------- 9503 * This register controls the settings of the Fan Speed PWM mechanism. 9504 */ 9505 #define MLXSW_REG_MFCR_ID 0x9001 9506 #define MLXSW_REG_MFCR_LEN 0x08 9507 9508 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9509 9510 enum mlxsw_reg_mfcr_pwm_frequency { 9511 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9512 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9513 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9514 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9515 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9516 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9517 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9518 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9519 }; 9520 9521 /* reg_mfcr_pwm_frequency 9522 * Controls the frequency of the PWM signal. 9523 * Access: RW 9524 */ 9525 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9526 9527 #define MLXSW_MFCR_TACHOS_MAX 10 9528 9529 /* reg_mfcr_tacho_active 9530 * Indicates which of the tachometer is active (bit per tachometer). 9531 * Access: RO 9532 */ 9533 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9534 9535 #define MLXSW_MFCR_PWMS_MAX 5 9536 9537 /* reg_mfcr_pwm_active 9538 * Indicates which of the PWM control is active (bit per PWM). 9539 * Access: RO 9540 */ 9541 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9542 9543 static inline void 9544 mlxsw_reg_mfcr_pack(char *payload, 9545 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9546 { 9547 MLXSW_REG_ZERO(mfcr, payload); 9548 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9549 } 9550 9551 static inline void 9552 mlxsw_reg_mfcr_unpack(char *payload, 9553 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9554 u16 *p_tacho_active, u8 *p_pwm_active) 9555 { 9556 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9557 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9558 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9559 } 9560 9561 /* MFSC - Management Fan Speed Control Register 9562 * -------------------------------------------- 9563 * This register controls the settings of the Fan Speed PWM mechanism. 9564 */ 9565 #define MLXSW_REG_MFSC_ID 0x9002 9566 #define MLXSW_REG_MFSC_LEN 0x08 9567 9568 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9569 9570 /* reg_mfsc_pwm 9571 * Fan pwm to control / monitor. 9572 * Access: Index 9573 */ 9574 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9575 9576 /* reg_mfsc_pwm_duty_cycle 9577 * Controls the duty cycle of the PWM. Value range from 0..255 to 9578 * represent duty cycle of 0%...100%. 9579 * Access: RW 9580 */ 9581 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9582 9583 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9584 u8 pwm_duty_cycle) 9585 { 9586 MLXSW_REG_ZERO(mfsc, payload); 9587 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9588 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9589 } 9590 9591 /* MFSM - Management Fan Speed Measurement 9592 * --------------------------------------- 9593 * This register controls the settings of the Tacho measurements and 9594 * enables reading the Tachometer measurements. 9595 */ 9596 #define MLXSW_REG_MFSM_ID 0x9003 9597 #define MLXSW_REG_MFSM_LEN 0x08 9598 9599 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9600 9601 /* reg_mfsm_tacho 9602 * Fan tachometer index. 9603 * Access: Index 9604 */ 9605 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9606 9607 /* reg_mfsm_rpm 9608 * Fan speed (round per minute). 9609 * Access: RO 9610 */ 9611 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9612 9613 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9614 { 9615 MLXSW_REG_ZERO(mfsm, payload); 9616 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9617 } 9618 9619 /* MFSL - Management Fan Speed Limit Register 9620 * ------------------------------------------ 9621 * The Fan Speed Limit register is used to configure the fan speed 9622 * event / interrupt notification mechanism. Fan speed threshold are 9623 * defined for both under-speed and over-speed. 9624 */ 9625 #define MLXSW_REG_MFSL_ID 0x9004 9626 #define MLXSW_REG_MFSL_LEN 0x0C 9627 9628 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9629 9630 /* reg_mfsl_tacho 9631 * Fan tachometer index. 9632 * Access: Index 9633 */ 9634 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9635 9636 /* reg_mfsl_tach_min 9637 * Tachometer minimum value (minimum RPM). 9638 * Access: RW 9639 */ 9640 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9641 9642 /* reg_mfsl_tach_max 9643 * Tachometer maximum value (maximum RPM). 9644 * Access: RW 9645 */ 9646 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9647 9648 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9649 u16 tach_min, u16 tach_max) 9650 { 9651 MLXSW_REG_ZERO(mfsl, payload); 9652 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9653 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9654 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9655 } 9656 9657 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9658 u16 *p_tach_min, u16 *p_tach_max) 9659 { 9660 if (p_tach_min) 9661 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9662 9663 if (p_tach_max) 9664 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9665 } 9666 9667 /* FORE - Fan Out of Range Event Register 9668 * -------------------------------------- 9669 * This register reports the status of the controlled fans compared to the 9670 * range defined by the MFSL register. 9671 */ 9672 #define MLXSW_REG_FORE_ID 0x9007 9673 #define MLXSW_REG_FORE_LEN 0x0C 9674 9675 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9676 9677 /* fan_under_limit 9678 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9679 * to a single tachometer and indicates the specific tachometer reading is 9680 * below the threshold. 9681 * Access: RO 9682 */ 9683 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9684 9685 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9686 bool *fault) 9687 { 9688 u16 limit; 9689 9690 if (fault) { 9691 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9692 *fault = limit & BIT(tacho); 9693 } 9694 } 9695 9696 /* MTCAP - Management Temperature Capabilities 9697 * ------------------------------------------- 9698 * This register exposes the capabilities of the device and 9699 * system temperature sensing. 9700 */ 9701 #define MLXSW_REG_MTCAP_ID 0x9009 9702 #define MLXSW_REG_MTCAP_LEN 0x08 9703 9704 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9705 9706 /* reg_mtcap_sensor_count 9707 * Number of sensors supported by the device. 9708 * This includes the QSFP module sensors (if exists in the QSFP module). 9709 * Access: RO 9710 */ 9711 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9712 9713 /* MTMP - Management Temperature 9714 * ----------------------------- 9715 * This register controls the settings of the temperature measurements 9716 * and enables reading the temperature measurements. Note that temperature 9717 * is in 0.125 degrees Celsius. 9718 */ 9719 #define MLXSW_REG_MTMP_ID 0x900A 9720 #define MLXSW_REG_MTMP_LEN 0x20 9721 9722 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9723 9724 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9725 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9726 /* reg_mtmp_sensor_index 9727 * Sensors index to access. 9728 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9729 * (module 0 is mapped to sensor_index 64). 9730 * Access: Index 9731 */ 9732 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9733 9734 /* Convert to milli degrees Celsius */ 9735 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9736 ((v_) >= 0) ? ((v_) * 125) : \ 9737 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9738 * 125)); }) 9739 9740 /* reg_mtmp_max_operational_temperature 9741 * The highest temperature in the nominal operational range. Reading is in 9742 * 0.125 Celsius degrees units. 9743 * In case of module this is SFF critical temperature threshold. 9744 * Access: RO 9745 */ 9746 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9747 9748 /* reg_mtmp_temperature 9749 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9750 * degrees units. 9751 * Access: RO 9752 */ 9753 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9754 9755 /* reg_mtmp_mte 9756 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9757 * Access: RW 9758 */ 9759 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9760 9761 /* reg_mtmp_mtr 9762 * Max Temperature Reset - clears the value of the max temperature register. 9763 * Access: WO 9764 */ 9765 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9766 9767 /* reg_mtmp_max_temperature 9768 * The highest measured temperature from the sensor. 9769 * When the bit mte is cleared, the field max_temperature is reserved. 9770 * Access: RO 9771 */ 9772 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9773 9774 /* reg_mtmp_tee 9775 * Temperature Event Enable. 9776 * 0 - Do not generate event 9777 * 1 - Generate event 9778 * 2 - Generate single event 9779 * Access: RW 9780 */ 9781 9782 enum mlxsw_reg_mtmp_tee { 9783 MLXSW_REG_MTMP_TEE_NO_EVENT, 9784 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9785 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9786 }; 9787 9788 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9789 9790 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9791 9792 /* reg_mtmp_temperature_threshold_hi 9793 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9794 * Access: RW 9795 */ 9796 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9797 9798 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9799 /* reg_mtmp_temperature_threshold_lo 9800 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9801 * Access: RW 9802 */ 9803 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9804 9805 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9806 9807 /* reg_mtmp_sensor_name 9808 * Sensor Name 9809 * Access: RO 9810 */ 9811 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9812 9813 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 9814 bool max_temp_enable, 9815 bool max_temp_reset) 9816 { 9817 MLXSW_REG_ZERO(mtmp, payload); 9818 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9819 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9820 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9821 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9822 MLXSW_REG_MTMP_THRESH_HI); 9823 } 9824 9825 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9826 int *p_max_temp, int *p_temp_hi, 9827 int *p_max_oper_temp, 9828 char *sensor_name) 9829 { 9830 s16 temp; 9831 9832 if (p_temp) { 9833 temp = mlxsw_reg_mtmp_temperature_get(payload); 9834 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9835 } 9836 if (p_max_temp) { 9837 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9838 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9839 } 9840 if (p_temp_hi) { 9841 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9842 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9843 } 9844 if (p_max_oper_temp) { 9845 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9846 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9847 } 9848 if (sensor_name) 9849 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9850 } 9851 9852 /* MTWE - Management Temperature Warning Event 9853 * ------------------------------------------- 9854 * This register is used for over temperature warning. 9855 */ 9856 #define MLXSW_REG_MTWE_ID 0x900B 9857 #define MLXSW_REG_MTWE_LEN 0x10 9858 9859 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9860 9861 /* reg_mtwe_sensor_warning 9862 * Bit vector indicating which of the sensor reading is above threshold. 9863 * Address 00h bit31 is sensor_warning[127]. 9864 * Address 0Ch bit0 is sensor_warning[0]. 9865 * Access: RO 9866 */ 9867 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9868 9869 /* MTBR - Management Temperature Bulk Register 9870 * ------------------------------------------- 9871 * This register is used for bulk temperature reading. 9872 */ 9873 #define MLXSW_REG_MTBR_ID 0x900F 9874 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9875 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9876 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9877 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9878 MLXSW_REG_MTBR_REC_LEN * \ 9879 MLXSW_REG_MTBR_REC_MAX_COUNT) 9880 9881 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9882 9883 /* reg_mtbr_base_sensor_index 9884 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9885 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9886 * Access: Index 9887 */ 9888 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9889 9890 /* reg_mtbr_num_rec 9891 * Request: Number of records to read 9892 * Response: Number of records read 9893 * See above description for more details. 9894 * Range 1..255 9895 * Access: RW 9896 */ 9897 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9898 9899 /* reg_mtbr_rec_max_temp 9900 * The highest measured temperature from the sensor. 9901 * When the bit mte is cleared, the field max_temperature is reserved. 9902 * Access: RO 9903 */ 9904 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9905 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9906 9907 /* reg_mtbr_rec_temp 9908 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9909 * degrees units. 9910 * Access: RO 9911 */ 9912 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9913 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9914 9915 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 9916 u8 num_rec) 9917 { 9918 MLXSW_REG_ZERO(mtbr, payload); 9919 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9920 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9921 } 9922 9923 /* Error codes from temperatute reading */ 9924 enum mlxsw_reg_mtbr_temp_status { 9925 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9926 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9927 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9928 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9929 }; 9930 9931 /* Base index for reading modules temperature */ 9932 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9933 9934 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9935 u16 *p_temp, u16 *p_max_temp) 9936 { 9937 if (p_temp) 9938 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9939 if (p_max_temp) 9940 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9941 } 9942 9943 /* MCIA - Management Cable Info Access 9944 * ----------------------------------- 9945 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9946 */ 9947 9948 #define MLXSW_REG_MCIA_ID 0x9014 9949 #define MLXSW_REG_MCIA_LEN 0x40 9950 9951 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9952 9953 /* reg_mcia_l 9954 * Lock bit. Setting this bit will lock the access to the specific 9955 * cable. Used for updating a full page in a cable EPROM. Any access 9956 * other then subsequence writes will fail while the port is locked. 9957 * Access: RW 9958 */ 9959 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9960 9961 /* reg_mcia_module 9962 * Module number. 9963 * Access: Index 9964 */ 9965 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9966 9967 enum { 9968 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9969 /* No response from module's EEPROM. */ 9970 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9971 /* Module type not supported by the device. */ 9972 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9973 /* No module present indication. */ 9974 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9975 /* Error occurred while trying to access module's EEPROM using I2C. */ 9976 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9977 /* Module is disabled. */ 9978 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9979 }; 9980 9981 /* reg_mcia_status 9982 * Module status. 9983 * Access: RO 9984 */ 9985 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9986 9987 /* reg_mcia_i2c_device_address 9988 * I2C device address. 9989 * Access: RW 9990 */ 9991 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9992 9993 /* reg_mcia_page_number 9994 * Page number. 9995 * Access: RW 9996 */ 9997 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9998 9999 /* reg_mcia_device_address 10000 * Device address. 10001 * Access: RW 10002 */ 10003 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 10004 10005 /* reg_mcia_bank_number 10006 * Bank number. 10007 * Access: Index 10008 */ 10009 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 10010 10011 /* reg_mcia_size 10012 * Number of bytes to read/write (up to 48 bytes). 10013 * Access: RW 10014 */ 10015 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 10016 10017 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 10018 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 10019 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 10020 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 10021 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 10022 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 10023 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 10024 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 10025 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 10026 #define MLXSW_REG_MCIA_PAGE0_LO 0 10027 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 10028 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 10029 10030 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 10031 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 10032 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 10033 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 10034 }; 10035 10036 enum mlxsw_reg_mcia_eeprom_module_info_id { 10037 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 10038 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 10039 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 10040 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 10041 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 10042 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 10043 }; 10044 10045 enum mlxsw_reg_mcia_eeprom_module_info { 10046 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 10047 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 10048 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 10049 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 10050 }; 10051 10052 /* reg_mcia_eeprom 10053 * Bytes to read/write. 10054 * Access: RW 10055 */ 10056 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 10057 10058 /* This is used to access the optional upper pages (1-3) in the QSFP+ 10059 * memory map. Page 1 is available on offset 256 through 383, page 2 - 10060 * on offset 384 through 511, page 3 - on offset 512 through 639. 10061 */ 10062 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 10063 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 10064 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 10065 10066 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 10067 u8 page_number, u16 device_addr, 10068 u8 size, u8 i2c_device_addr) 10069 { 10070 MLXSW_REG_ZERO(mcia, payload); 10071 mlxsw_reg_mcia_module_set(payload, module); 10072 mlxsw_reg_mcia_l_set(payload, lock); 10073 mlxsw_reg_mcia_page_number_set(payload, page_number); 10074 mlxsw_reg_mcia_device_address_set(payload, device_addr); 10075 mlxsw_reg_mcia_size_set(payload, size); 10076 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 10077 } 10078 10079 /* MPAT - Monitoring Port Analyzer Table 10080 * ------------------------------------- 10081 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 10082 * For an enabled analyzer, all fields except e (enable) cannot be modified. 10083 */ 10084 #define MLXSW_REG_MPAT_ID 0x901A 10085 #define MLXSW_REG_MPAT_LEN 0x78 10086 10087 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 10088 10089 /* reg_mpat_pa_id 10090 * Port Analyzer ID. 10091 * Access: Index 10092 */ 10093 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 10094 10095 /* reg_mpat_session_id 10096 * Mirror Session ID. 10097 * Used for MIRROR_SESSION<i> trap. 10098 * Access: RW 10099 */ 10100 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 10101 10102 /* reg_mpat_system_port 10103 * A unique port identifier for the final destination of the packet. 10104 * Access: RW 10105 */ 10106 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 10107 10108 /* reg_mpat_e 10109 * Enable. Indicating the Port Analyzer is enabled. 10110 * Access: RW 10111 */ 10112 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 10113 10114 /* reg_mpat_qos 10115 * Quality Of Service Mode. 10116 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 10117 * PCP, DEI, DSCP or VL) are configured. 10118 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 10119 * same as in the original packet that has triggered the mirroring. For 10120 * SPAN also the pcp,dei are maintained. 10121 * Access: RW 10122 */ 10123 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 10124 10125 /* reg_mpat_be 10126 * Best effort mode. Indicates mirroring traffic should not cause packet 10127 * drop or back pressure, but will discard the mirrored packets. Mirrored 10128 * packets will be forwarded on a best effort manner. 10129 * 0: Do not discard mirrored packets 10130 * 1: Discard mirrored packets if causing congestion 10131 * Access: RW 10132 */ 10133 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 10134 10135 enum mlxsw_reg_mpat_span_type { 10136 /* Local SPAN Ethernet. 10137 * The original packet is not encapsulated. 10138 */ 10139 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 10140 10141 /* Remote SPAN Ethernet VLAN. 10142 * The packet is forwarded to the monitoring port on the monitoring 10143 * VLAN. 10144 */ 10145 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 10146 10147 /* Encapsulated Remote SPAN Ethernet L3 GRE. 10148 * The packet is encapsulated with GRE header. 10149 */ 10150 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 10151 }; 10152 10153 /* reg_mpat_span_type 10154 * SPAN type. 10155 * Access: RW 10156 */ 10157 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 10158 10159 /* reg_mpat_pide 10160 * Policer enable. 10161 * Access: RW 10162 */ 10163 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 10164 10165 /* reg_mpat_pid 10166 * Policer ID. 10167 * Access: RW 10168 */ 10169 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 10170 10171 /* Remote SPAN - Ethernet VLAN 10172 * - - - - - - - - - - - - - - 10173 */ 10174 10175 /* reg_mpat_eth_rspan_vid 10176 * Encapsulation header VLAN ID. 10177 * Access: RW 10178 */ 10179 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 10180 10181 /* Encapsulated Remote SPAN - Ethernet L2 10182 * - - - - - - - - - - - - - - - - - - - 10183 */ 10184 10185 enum mlxsw_reg_mpat_eth_rspan_version { 10186 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 10187 }; 10188 10189 /* reg_mpat_eth_rspan_version 10190 * RSPAN mirror header version. 10191 * Access: RW 10192 */ 10193 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 10194 10195 /* reg_mpat_eth_rspan_mac 10196 * Destination MAC address. 10197 * Access: RW 10198 */ 10199 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 10200 10201 /* reg_mpat_eth_rspan_tp 10202 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 10203 * Access: RW 10204 */ 10205 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 10206 10207 /* Encapsulated Remote SPAN - Ethernet L3 10208 * - - - - - - - - - - - - - - - - - - - 10209 */ 10210 10211 enum mlxsw_reg_mpat_eth_rspan_protocol { 10212 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 10213 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 10214 }; 10215 10216 /* reg_mpat_eth_rspan_protocol 10217 * SPAN encapsulation protocol. 10218 * Access: RW 10219 */ 10220 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 10221 10222 /* reg_mpat_eth_rspan_ttl 10223 * Encapsulation header Time-to-Live/HopLimit. 10224 * Access: RW 10225 */ 10226 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 10227 10228 /* reg_mpat_eth_rspan_smac 10229 * Source MAC address 10230 * Access: RW 10231 */ 10232 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 10233 10234 /* reg_mpat_eth_rspan_dip* 10235 * Destination IP address. The IP version is configured by protocol. 10236 * Access: RW 10237 */ 10238 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 10239 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 10240 10241 /* reg_mpat_eth_rspan_sip* 10242 * Source IP address. The IP version is configured by protocol. 10243 * Access: RW 10244 */ 10245 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 10246 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 10247 10248 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 10249 u16 system_port, bool e, 10250 enum mlxsw_reg_mpat_span_type span_type) 10251 { 10252 MLXSW_REG_ZERO(mpat, payload); 10253 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 10254 mlxsw_reg_mpat_system_port_set(payload, system_port); 10255 mlxsw_reg_mpat_e_set(payload, e); 10256 mlxsw_reg_mpat_qos_set(payload, 1); 10257 mlxsw_reg_mpat_be_set(payload, 1); 10258 mlxsw_reg_mpat_span_type_set(payload, span_type); 10259 } 10260 10261 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 10262 { 10263 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 10264 } 10265 10266 static inline void 10267 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 10268 enum mlxsw_reg_mpat_eth_rspan_version version, 10269 const char *mac, 10270 bool tp) 10271 { 10272 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 10273 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 10274 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 10275 } 10276 10277 static inline void 10278 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 10279 const char *smac, 10280 u32 sip, u32 dip) 10281 { 10282 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10283 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10284 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10285 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 10286 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 10287 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 10288 } 10289 10290 static inline void 10291 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 10292 const char *smac, 10293 struct in6_addr sip, struct in6_addr dip) 10294 { 10295 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10296 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10297 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10298 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 10299 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 10300 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 10301 } 10302 10303 /* MPAR - Monitoring Port Analyzer Register 10304 * ---------------------------------------- 10305 * MPAR register is used to query and configure the port analyzer port mirroring 10306 * properties. 10307 */ 10308 #define MLXSW_REG_MPAR_ID 0x901B 10309 #define MLXSW_REG_MPAR_LEN 0x0C 10310 10311 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 10312 10313 /* reg_mpar_local_port 10314 * The local port to mirror the packets from. 10315 * Access: Index 10316 */ 10317 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 10318 10319 enum mlxsw_reg_mpar_i_e { 10320 MLXSW_REG_MPAR_TYPE_EGRESS, 10321 MLXSW_REG_MPAR_TYPE_INGRESS, 10322 }; 10323 10324 /* reg_mpar_i_e 10325 * Ingress/Egress 10326 * Access: Index 10327 */ 10328 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10329 10330 /* reg_mpar_enable 10331 * Enable mirroring 10332 * By default, port mirroring is disabled for all ports. 10333 * Access: RW 10334 */ 10335 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10336 10337 /* reg_mpar_pa_id 10338 * Port Analyzer ID. 10339 * Access: RW 10340 */ 10341 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10342 10343 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10344 10345 /* reg_mpar_probability_rate 10346 * Sampling rate. 10347 * Valid values are: 1 to 3.5*10^9 10348 * Value of 1 means "sample all". Default is 1. 10349 * Reserved when Spectrum-1. 10350 * Access: RW 10351 */ 10352 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10353 10354 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 10355 enum mlxsw_reg_mpar_i_e i_e, 10356 bool enable, u8 pa_id, 10357 u32 probability_rate) 10358 { 10359 MLXSW_REG_ZERO(mpar, payload); 10360 mlxsw_reg_mpar_local_port_set(payload, local_port); 10361 mlxsw_reg_mpar_enable_set(payload, enable); 10362 mlxsw_reg_mpar_i_e_set(payload, i_e); 10363 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10364 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10365 } 10366 10367 /* MGIR - Management General Information Register 10368 * ---------------------------------------------- 10369 * MGIR register allows software to query the hardware and firmware general 10370 * information. 10371 */ 10372 #define MLXSW_REG_MGIR_ID 0x9020 10373 #define MLXSW_REG_MGIR_LEN 0x9C 10374 10375 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10376 10377 /* reg_mgir_hw_info_device_hw_revision 10378 * Access: RO 10379 */ 10380 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10381 10382 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10383 10384 /* reg_mgir_fw_info_psid 10385 * PSID (ASCII string). 10386 * Access: RO 10387 */ 10388 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10389 10390 /* reg_mgir_fw_info_extended_major 10391 * Access: RO 10392 */ 10393 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10394 10395 /* reg_mgir_fw_info_extended_minor 10396 * Access: RO 10397 */ 10398 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10399 10400 /* reg_mgir_fw_info_extended_sub_minor 10401 * Access: RO 10402 */ 10403 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10404 10405 static inline void mlxsw_reg_mgir_pack(char *payload) 10406 { 10407 MLXSW_REG_ZERO(mgir, payload); 10408 } 10409 10410 static inline void 10411 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10412 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10413 { 10414 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10415 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10416 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10417 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10418 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10419 } 10420 10421 /* MRSR - Management Reset and Shutdown Register 10422 * --------------------------------------------- 10423 * MRSR register is used to reset or shutdown the switch or 10424 * the entire system (when applicable). 10425 */ 10426 #define MLXSW_REG_MRSR_ID 0x9023 10427 #define MLXSW_REG_MRSR_LEN 0x08 10428 10429 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10430 10431 /* reg_mrsr_command 10432 * Reset/shutdown command 10433 * 0 - do nothing 10434 * 1 - software reset 10435 * Access: WO 10436 */ 10437 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10438 10439 static inline void mlxsw_reg_mrsr_pack(char *payload) 10440 { 10441 MLXSW_REG_ZERO(mrsr, payload); 10442 mlxsw_reg_mrsr_command_set(payload, 1); 10443 } 10444 10445 /* MLCR - Management LED Control Register 10446 * -------------------------------------- 10447 * Controls the system LEDs. 10448 */ 10449 #define MLXSW_REG_MLCR_ID 0x902B 10450 #define MLXSW_REG_MLCR_LEN 0x0C 10451 10452 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10453 10454 /* reg_mlcr_local_port 10455 * Local port number. 10456 * Access: RW 10457 */ 10458 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10459 10460 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10461 10462 /* reg_mlcr_beacon_duration 10463 * Duration of the beacon to be active, in seconds. 10464 * 0x0 - Will turn off the beacon. 10465 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10466 * Access: RW 10467 */ 10468 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10469 10470 /* reg_mlcr_beacon_remain 10471 * Remaining duration of the beacon, in seconds. 10472 * 0xFFFF indicates an infinite amount of time. 10473 * Access: RO 10474 */ 10475 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10476 10477 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10478 bool active) 10479 { 10480 MLXSW_REG_ZERO(mlcr, payload); 10481 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10482 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10483 MLXSW_REG_MLCR_DURATION_MAX : 0); 10484 } 10485 10486 /* MCION - Management Cable IO and Notifications Register 10487 * ------------------------------------------------------ 10488 * The MCION register is used to query transceiver modules' IO pins and other 10489 * notifications. 10490 */ 10491 #define MLXSW_REG_MCION_ID 0x9052 10492 #define MLXSW_REG_MCION_LEN 0x18 10493 10494 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10495 10496 /* reg_mcion_module 10497 * Module number. 10498 * Access: Index 10499 */ 10500 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10501 10502 enum { 10503 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10504 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10505 }; 10506 10507 /* reg_mcion_module_status_bits 10508 * Module IO status as defined by SFF. 10509 * Access: RO 10510 */ 10511 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10512 10513 static inline void mlxsw_reg_mcion_pack(char *payload, u8 module) 10514 { 10515 MLXSW_REG_ZERO(mcion, payload); 10516 mlxsw_reg_mcion_module_set(payload, module); 10517 } 10518 10519 /* MTPPS - Management Pulse Per Second Register 10520 * -------------------------------------------- 10521 * This register provides the device PPS capabilities, configure the PPS in and 10522 * out modules and holds the PPS in time stamp. 10523 */ 10524 #define MLXSW_REG_MTPPS_ID 0x9053 10525 #define MLXSW_REG_MTPPS_LEN 0x3C 10526 10527 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10528 10529 /* reg_mtpps_enable 10530 * Enables the PPS functionality the specific pin. 10531 * A boolean variable. 10532 * Access: RW 10533 */ 10534 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10535 10536 enum mlxsw_reg_mtpps_pin_mode { 10537 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10538 }; 10539 10540 /* reg_mtpps_pin_mode 10541 * Pin mode to be used. The mode must comply with the supported modes of the 10542 * requested pin. 10543 * Access: RW 10544 */ 10545 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10546 10547 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10548 10549 /* reg_mtpps_pin 10550 * Pin to be configured or queried out of the supported pins. 10551 * Access: Index 10552 */ 10553 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10554 10555 /* reg_mtpps_time_stamp 10556 * When pin_mode = pps_in, the latched device time when it was triggered from 10557 * the external GPIO pin. 10558 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10559 * time to generate next output signal. 10560 * Time is in units of device clock. 10561 * Access: RW 10562 */ 10563 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10564 10565 static inline void 10566 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10567 { 10568 MLXSW_REG_ZERO(mtpps, payload); 10569 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10570 mlxsw_reg_mtpps_pin_mode_set(payload, 10571 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10572 mlxsw_reg_mtpps_enable_set(payload, true); 10573 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10574 } 10575 10576 /* MTUTC - Management UTC Register 10577 * ------------------------------- 10578 * Configures the HW UTC counter. 10579 */ 10580 #define MLXSW_REG_MTUTC_ID 0x9055 10581 #define MLXSW_REG_MTUTC_LEN 0x1C 10582 10583 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10584 10585 enum mlxsw_reg_mtutc_operation { 10586 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10587 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10588 }; 10589 10590 /* reg_mtutc_operation 10591 * Operation. 10592 * Access: OP 10593 */ 10594 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10595 10596 /* reg_mtutc_freq_adjustment 10597 * Frequency adjustment: Every PPS the HW frequency will be 10598 * adjusted by this value. Units of HW clock, where HW counts 10599 * 10^9 HW clocks for 1 HW second. 10600 * Access: RW 10601 */ 10602 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10603 10604 /* reg_mtutc_utc_sec 10605 * UTC seconds. 10606 * Access: WO 10607 */ 10608 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10609 10610 static inline void 10611 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10612 u32 freq_adj, u32 utc_sec) 10613 { 10614 MLXSW_REG_ZERO(mtutc, payload); 10615 mlxsw_reg_mtutc_operation_set(payload, oper); 10616 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10617 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10618 } 10619 10620 /* MCQI - Management Component Query Information 10621 * --------------------------------------------- 10622 * This register allows querying information about firmware components. 10623 */ 10624 #define MLXSW_REG_MCQI_ID 0x9061 10625 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10626 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10627 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10628 10629 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10630 10631 /* reg_mcqi_component_index 10632 * Index of the accessed component. 10633 * Access: Index 10634 */ 10635 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10636 10637 enum mlxfw_reg_mcqi_info_type { 10638 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10639 }; 10640 10641 /* reg_mcqi_info_type 10642 * Component properties set. 10643 * Access: RW 10644 */ 10645 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10646 10647 /* reg_mcqi_offset 10648 * The requested/returned data offset from the section start, given in bytes. 10649 * Must be DWORD aligned. 10650 * Access: RW 10651 */ 10652 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10653 10654 /* reg_mcqi_data_size 10655 * The requested/returned data size, given in bytes. If data_size is not DWORD 10656 * aligned, the last bytes are zero padded. 10657 * Access: RW 10658 */ 10659 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10660 10661 /* reg_mcqi_cap_max_component_size 10662 * Maximum size for this component, given in bytes. 10663 * Access: RO 10664 */ 10665 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10666 10667 /* reg_mcqi_cap_log_mcda_word_size 10668 * Log 2 of the access word size in bytes. Read and write access must be aligned 10669 * to the word size. Write access must be done for an integer number of words. 10670 * Access: RO 10671 */ 10672 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10673 10674 /* reg_mcqi_cap_mcda_max_write_size 10675 * Maximal write size for MCDA register 10676 * Access: RO 10677 */ 10678 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10679 10680 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10681 { 10682 MLXSW_REG_ZERO(mcqi, payload); 10683 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10684 mlxsw_reg_mcqi_info_type_set(payload, 10685 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10686 mlxsw_reg_mcqi_offset_set(payload, 0); 10687 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10688 } 10689 10690 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10691 u32 *p_cap_max_component_size, 10692 u8 *p_cap_log_mcda_word_size, 10693 u16 *p_cap_mcda_max_write_size) 10694 { 10695 *p_cap_max_component_size = 10696 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10697 *p_cap_log_mcda_word_size = 10698 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10699 *p_cap_mcda_max_write_size = 10700 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10701 } 10702 10703 /* MCC - Management Component Control 10704 * ---------------------------------- 10705 * Controls the firmware component and updates the FSM. 10706 */ 10707 #define MLXSW_REG_MCC_ID 0x9062 10708 #define MLXSW_REG_MCC_LEN 0x1C 10709 10710 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10711 10712 enum mlxsw_reg_mcc_instruction { 10713 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10714 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10715 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10716 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10717 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10718 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10719 }; 10720 10721 /* reg_mcc_instruction 10722 * Command to be executed by the FSM. 10723 * Applicable for write operation only. 10724 * Access: RW 10725 */ 10726 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10727 10728 /* reg_mcc_component_index 10729 * Index of the accessed component. Applicable only for commands that 10730 * refer to components. Otherwise, this field is reserved. 10731 * Access: Index 10732 */ 10733 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10734 10735 /* reg_mcc_update_handle 10736 * Token representing the current flow executed by the FSM. 10737 * Access: WO 10738 */ 10739 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10740 10741 /* reg_mcc_error_code 10742 * Indicates the successful completion of the instruction, or the reason it 10743 * failed 10744 * Access: RO 10745 */ 10746 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10747 10748 /* reg_mcc_control_state 10749 * Current FSM state 10750 * Access: RO 10751 */ 10752 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10753 10754 /* reg_mcc_component_size 10755 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10756 * the size may shorten the update time. Value 0x0 means that size is 10757 * unspecified. 10758 * Access: WO 10759 */ 10760 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10761 10762 static inline void mlxsw_reg_mcc_pack(char *payload, 10763 enum mlxsw_reg_mcc_instruction instr, 10764 u16 component_index, u32 update_handle, 10765 u32 component_size) 10766 { 10767 MLXSW_REG_ZERO(mcc, payload); 10768 mlxsw_reg_mcc_instruction_set(payload, instr); 10769 mlxsw_reg_mcc_component_index_set(payload, component_index); 10770 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10771 mlxsw_reg_mcc_component_size_set(payload, component_size); 10772 } 10773 10774 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10775 u8 *p_error_code, u8 *p_control_state) 10776 { 10777 if (p_update_handle) 10778 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10779 if (p_error_code) 10780 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10781 if (p_control_state) 10782 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10783 } 10784 10785 /* MCDA - Management Component Data Access 10786 * --------------------------------------- 10787 * This register allows reading and writing a firmware component. 10788 */ 10789 #define MLXSW_REG_MCDA_ID 0x9063 10790 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10791 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10792 #define MLXSW_REG_MCDA_LEN \ 10793 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10794 10795 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10796 10797 /* reg_mcda_update_handle 10798 * Token representing the current flow executed by the FSM. 10799 * Access: RW 10800 */ 10801 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10802 10803 /* reg_mcda_offset 10804 * Offset of accessed address relative to component start. Accesses must be in 10805 * accordance to log_mcda_word_size in MCQI reg. 10806 * Access: RW 10807 */ 10808 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10809 10810 /* reg_mcda_size 10811 * Size of the data accessed, given in bytes. 10812 * Access: RW 10813 */ 10814 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10815 10816 /* reg_mcda_data 10817 * Data block accessed. 10818 * Access: RW 10819 */ 10820 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10821 10822 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10823 u32 offset, u16 size, u8 *data) 10824 { 10825 int i; 10826 10827 MLXSW_REG_ZERO(mcda, payload); 10828 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10829 mlxsw_reg_mcda_offset_set(payload, offset); 10830 mlxsw_reg_mcda_size_set(payload, size); 10831 10832 for (i = 0; i < size / 4; i++) 10833 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10834 } 10835 10836 /* MPSC - Monitoring Packet Sampling Configuration Register 10837 * -------------------------------------------------------- 10838 * MPSC Register is used to configure the Packet Sampling mechanism. 10839 */ 10840 #define MLXSW_REG_MPSC_ID 0x9080 10841 #define MLXSW_REG_MPSC_LEN 0x1C 10842 10843 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10844 10845 /* reg_mpsc_local_port 10846 * Local port number 10847 * Not supported for CPU port 10848 * Access: Index 10849 */ 10850 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10851 10852 /* reg_mpsc_e 10853 * Enable sampling on port local_port 10854 * Access: RW 10855 */ 10856 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10857 10858 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10859 10860 /* reg_mpsc_rate 10861 * Sampling rate = 1 out of rate packets (with randomization around 10862 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10863 * Access: RW 10864 */ 10865 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10866 10867 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10868 u32 rate) 10869 { 10870 MLXSW_REG_ZERO(mpsc, payload); 10871 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10872 mlxsw_reg_mpsc_e_set(payload, e); 10873 mlxsw_reg_mpsc_rate_set(payload, rate); 10874 } 10875 10876 /* MGPC - Monitoring General Purpose Counter Set Register 10877 * The MGPC register retrieves and sets the General Purpose Counter Set. 10878 */ 10879 #define MLXSW_REG_MGPC_ID 0x9081 10880 #define MLXSW_REG_MGPC_LEN 0x18 10881 10882 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10883 10884 /* reg_mgpc_counter_set_type 10885 * Counter set type. 10886 * Access: OP 10887 */ 10888 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10889 10890 /* reg_mgpc_counter_index 10891 * Counter index. 10892 * Access: Index 10893 */ 10894 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10895 10896 enum mlxsw_reg_mgpc_opcode { 10897 /* Nop */ 10898 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10899 /* Clear counters */ 10900 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10901 }; 10902 10903 /* reg_mgpc_opcode 10904 * Opcode. 10905 * Access: OP 10906 */ 10907 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10908 10909 /* reg_mgpc_byte_counter 10910 * Byte counter value. 10911 * Access: RW 10912 */ 10913 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10914 10915 /* reg_mgpc_packet_counter 10916 * Packet counter value. 10917 * Access: RW 10918 */ 10919 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10920 10921 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10922 enum mlxsw_reg_mgpc_opcode opcode, 10923 enum mlxsw_reg_flow_counter_set_type set_type) 10924 { 10925 MLXSW_REG_ZERO(mgpc, payload); 10926 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10927 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10928 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10929 } 10930 10931 /* MPRS - Monitoring Parsing State Register 10932 * ---------------------------------------- 10933 * The MPRS register is used for setting up the parsing for hash, 10934 * policy-engine and routing. 10935 */ 10936 #define MLXSW_REG_MPRS_ID 0x9083 10937 #define MLXSW_REG_MPRS_LEN 0x14 10938 10939 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10940 10941 /* reg_mprs_parsing_depth 10942 * Minimum parsing depth. 10943 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10944 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10945 * Access: RW 10946 */ 10947 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10948 10949 /* reg_mprs_parsing_en 10950 * Parsing enable. 10951 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10952 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10953 * Access: RW 10954 */ 10955 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10956 10957 /* reg_mprs_vxlan_udp_dport 10958 * VxLAN UDP destination port. 10959 * Used for identifying VxLAN packets and for dport field in 10960 * encapsulation. Default is 4789. 10961 * Access: RW 10962 */ 10963 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10964 10965 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10966 u16 vxlan_udp_dport) 10967 { 10968 MLXSW_REG_ZERO(mprs, payload); 10969 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10970 mlxsw_reg_mprs_parsing_en_set(payload, true); 10971 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10972 } 10973 10974 /* MOGCR - Monitoring Global Configuration Register 10975 * ------------------------------------------------ 10976 */ 10977 #define MLXSW_REG_MOGCR_ID 0x9086 10978 #define MLXSW_REG_MOGCR_LEN 0x20 10979 10980 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10981 10982 /* reg_mogcr_ptp_iftc 10983 * PTP Ingress FIFO Trap Clear 10984 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10985 * to this value. Default 0. 10986 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10987 * Access: RW 10988 */ 10989 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10990 10991 /* reg_mogcr_ptp_eftc 10992 * PTP Egress FIFO Trap Clear 10993 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10994 * to this value. Default 0. 10995 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10996 * Access: RW 10997 */ 10998 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10999 11000 /* reg_mogcr_mirroring_pid_base 11001 * Base policer id for mirroring policers. 11002 * Must have an even value (e.g. 1000, not 1001). 11003 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 11004 * Access: RW 11005 */ 11006 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 11007 11008 /* MPAGR - Monitoring Port Analyzer Global Register 11009 * ------------------------------------------------ 11010 * This register is used for global port analyzer configurations. 11011 * Note: This register is not supported by current FW versions for Spectrum-1. 11012 */ 11013 #define MLXSW_REG_MPAGR_ID 0x9089 11014 #define MLXSW_REG_MPAGR_LEN 0x0C 11015 11016 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 11017 11018 enum mlxsw_reg_mpagr_trigger { 11019 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 11020 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 11021 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 11022 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 11023 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 11024 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 11025 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 11026 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 11027 }; 11028 11029 /* reg_mpagr_trigger 11030 * Mirror trigger. 11031 * Access: Index 11032 */ 11033 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 11034 11035 /* reg_mpagr_pa_id 11036 * Port analyzer ID. 11037 * Access: RW 11038 */ 11039 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 11040 11041 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 11042 11043 /* reg_mpagr_probability_rate 11044 * Sampling rate. 11045 * Valid values are: 1 to 3.5*10^9 11046 * Value of 1 means "sample all". Default is 1. 11047 * Access: RW 11048 */ 11049 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 11050 11051 static inline void mlxsw_reg_mpagr_pack(char *payload, 11052 enum mlxsw_reg_mpagr_trigger trigger, 11053 u8 pa_id, u32 probability_rate) 11054 { 11055 MLXSW_REG_ZERO(mpagr, payload); 11056 mlxsw_reg_mpagr_trigger_set(payload, trigger); 11057 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 11058 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 11059 } 11060 11061 /* MOMTE - Monitoring Mirror Trigger Enable Register 11062 * ------------------------------------------------- 11063 * This register is used to configure the mirror enable for different mirror 11064 * reasons. 11065 */ 11066 #define MLXSW_REG_MOMTE_ID 0x908D 11067 #define MLXSW_REG_MOMTE_LEN 0x10 11068 11069 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 11070 11071 /* reg_momte_local_port 11072 * Local port number. 11073 * Access: Index 11074 */ 11075 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 11076 11077 enum mlxsw_reg_momte_type { 11078 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 11079 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 11080 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 11081 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 11082 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 11083 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 11084 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 11085 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 11086 }; 11087 11088 /* reg_momte_type 11089 * Type of mirroring. 11090 * Access: Index 11091 */ 11092 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 11093 11094 /* reg_momte_tclass_en 11095 * TClass/PG mirror enable. Each bit represents corresponding tclass. 11096 * 0: disable (default) 11097 * 1: enable 11098 * Access: RW 11099 */ 11100 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 11101 11102 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 11103 enum mlxsw_reg_momte_type type) 11104 { 11105 MLXSW_REG_ZERO(momte, payload); 11106 mlxsw_reg_momte_local_port_set(payload, local_port); 11107 mlxsw_reg_momte_type_set(payload, type); 11108 } 11109 11110 /* MTPPPC - Time Precision Packet Port Configuration 11111 * ------------------------------------------------- 11112 * This register serves for configuration of which PTP messages should be 11113 * timestamped. This is a global configuration, despite the register name. 11114 * 11115 * Reserved when Spectrum-2. 11116 */ 11117 #define MLXSW_REG_MTPPPC_ID 0x9090 11118 #define MLXSW_REG_MTPPPC_LEN 0x28 11119 11120 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 11121 11122 /* reg_mtpppc_ing_timestamp_message_type 11123 * Bitwise vector of PTP message types to timestamp at ingress. 11124 * MessageType field as defined by IEEE 1588 11125 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 11126 * Default all 0 11127 * Access: RW 11128 */ 11129 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 11130 11131 /* reg_mtpppc_egr_timestamp_message_type 11132 * Bitwise vector of PTP message types to timestamp at egress. 11133 * MessageType field as defined by IEEE 1588 11134 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 11135 * Default all 0 11136 * Access: RW 11137 */ 11138 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 11139 11140 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 11141 { 11142 MLXSW_REG_ZERO(mtpppc, payload); 11143 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 11144 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 11145 } 11146 11147 /* MTPPTR - Time Precision Packet Timestamping Reading 11148 * --------------------------------------------------- 11149 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 11150 * There is a trap for packets which are latched to the timestamp FIFO, thus the 11151 * SW knows which FIFO to read. Note that packets enter the FIFO before been 11152 * trapped. The sequence number is used to synchronize the timestamp FIFO 11153 * entries and the trapped packets. 11154 * Reserved when Spectrum-2. 11155 */ 11156 11157 #define MLXSW_REG_MTPPTR_ID 0x9091 11158 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 11159 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 11160 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 11161 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 11162 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 11163 11164 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 11165 11166 /* reg_mtpptr_local_port 11167 * Not supported for CPU port. 11168 * Access: Index 11169 */ 11170 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 11171 11172 enum mlxsw_reg_mtpptr_dir { 11173 MLXSW_REG_MTPPTR_DIR_INGRESS, 11174 MLXSW_REG_MTPPTR_DIR_EGRESS, 11175 }; 11176 11177 /* reg_mtpptr_dir 11178 * Direction. 11179 * Access: Index 11180 */ 11181 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 11182 11183 /* reg_mtpptr_clr 11184 * Clear the records. 11185 * Access: OP 11186 */ 11187 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 11188 11189 /* reg_mtpptr_num_rec 11190 * Number of valid records in the response 11191 * Range 0.. cap_ptp_timestamp_fifo 11192 * Access: RO 11193 */ 11194 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 11195 11196 /* reg_mtpptr_rec_message_type 11197 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11198 * (e.g. Bit0: Sync, Bit1: Delay_Req) 11199 * Access: RO 11200 */ 11201 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 11202 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 11203 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11204 11205 /* reg_mtpptr_rec_domain_number 11206 * DomainNumber field as defined by IEEE 1588 11207 * Access: RO 11208 */ 11209 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 11210 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 11211 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11212 11213 /* reg_mtpptr_rec_sequence_id 11214 * SequenceId field as defined by IEEE 1588 11215 * Access: RO 11216 */ 11217 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 11218 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 11219 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 11220 11221 /* reg_mtpptr_rec_timestamp_high 11222 * Timestamp of when the PTP packet has passed through the port Units of PLL 11223 * clock time. 11224 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 11225 * Access: RO 11226 */ 11227 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 11228 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11229 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 11230 11231 /* reg_mtpptr_rec_timestamp_low 11232 * See rec_timestamp_high. 11233 * Access: RO 11234 */ 11235 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 11236 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11237 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 11238 11239 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 11240 unsigned int rec, 11241 u8 *p_message_type, 11242 u8 *p_domain_number, 11243 u16 *p_sequence_id, 11244 u64 *p_timestamp) 11245 { 11246 u32 timestamp_high, timestamp_low; 11247 11248 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 11249 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 11250 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 11251 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 11252 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 11253 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 11254 } 11255 11256 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 11257 * --------------------------------------------------------- 11258 * This register is used for configuring under which trap to deliver PTP 11259 * packets depending on type of the packet. 11260 */ 11261 #define MLXSW_REG_MTPTPT_ID 0x9092 11262 #define MLXSW_REG_MTPTPT_LEN 0x08 11263 11264 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 11265 11266 enum mlxsw_reg_mtptpt_trap_id { 11267 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 11268 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 11269 }; 11270 11271 /* reg_mtptpt_trap_id 11272 * Trap id. 11273 * Access: Index 11274 */ 11275 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 11276 11277 /* reg_mtptpt_message_type 11278 * Bitwise vector of PTP message types to trap. This is a necessary but 11279 * non-sufficient condition since need to enable also per port. See MTPPPC. 11280 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 11281 * Bit0: Sync, Bit1: Delay_Req) 11282 */ 11283 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 11284 11285 static inline void mlxsw_reg_mtptptp_pack(char *payload, 11286 enum mlxsw_reg_mtptpt_trap_id trap_id, 11287 u16 message_type) 11288 { 11289 MLXSW_REG_ZERO(mtptpt, payload); 11290 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 11291 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 11292 } 11293 11294 /* MFGD - Monitoring FW General Debug Register 11295 * ------------------------------------------- 11296 */ 11297 #define MLXSW_REG_MFGD_ID 0x90F0 11298 #define MLXSW_REG_MFGD_LEN 0x0C 11299 11300 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11301 11302 /* reg_mfgd_fw_fatal_event_mode 11303 * 0 - don't check FW fatal (default) 11304 * 1 - check FW fatal - enable MFDE trap 11305 * Access: RW 11306 */ 11307 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11308 11309 /* reg_mfgd_trigger_test 11310 * Access: WO 11311 */ 11312 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11313 11314 /* MGPIR - Management General Peripheral Information Register 11315 * ---------------------------------------------------------- 11316 * MGPIR register allows software to query the hardware and 11317 * firmware general information of peripheral entities. 11318 */ 11319 #define MLXSW_REG_MGPIR_ID 0x9100 11320 #define MLXSW_REG_MGPIR_LEN 0xA0 11321 11322 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11323 11324 enum mlxsw_reg_mgpir_device_type { 11325 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11326 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11327 }; 11328 11329 /* mgpir_device_type 11330 * Access: RO 11331 */ 11332 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11333 11334 /* mgpir_devices_per_flash 11335 * Number of devices of device_type per flash (can be shared by few devices). 11336 * Access: RO 11337 */ 11338 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11339 11340 /* mgpir_num_of_devices 11341 * Number of devices of device_type. 11342 * Access: RO 11343 */ 11344 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11345 11346 /* mgpir_num_of_modules 11347 * Number of modules. 11348 * Access: RO 11349 */ 11350 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11351 11352 static inline void mlxsw_reg_mgpir_pack(char *payload) 11353 { 11354 MLXSW_REG_ZERO(mgpir, payload); 11355 } 11356 11357 static inline void 11358 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11359 enum mlxsw_reg_mgpir_device_type *device_type, 11360 u8 *devices_per_flash, u8 *num_of_modules) 11361 { 11362 if (num_of_devices) 11363 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11364 if (device_type) 11365 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11366 if (devices_per_flash) 11367 *devices_per_flash = 11368 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11369 if (num_of_modules) 11370 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11371 } 11372 11373 /* MFDE - Monitoring FW Debug Register 11374 * ----------------------------------- 11375 */ 11376 #define MLXSW_REG_MFDE_ID 0x9200 11377 #define MLXSW_REG_MFDE_LEN 0x30 11378 11379 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11380 11381 /* reg_mfde_irisc_id 11382 * Which irisc triggered the event 11383 * Access: RO 11384 */ 11385 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11386 11387 enum mlxsw_reg_mfde_severity { 11388 /* Unrecoverable switch behavior */ 11389 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11390 /* Unexpected state with possible systemic failure */ 11391 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11392 /* Unexpected state without systemic failure */ 11393 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11394 }; 11395 11396 /* reg_mfde_severity 11397 * The severity of the event. 11398 * Access: RO 11399 */ 11400 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11401 11402 enum mlxsw_reg_mfde_event_id { 11403 /* CRspace timeout */ 11404 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11405 /* KVD insertion machine stopped */ 11406 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11407 /* Triggered by MFGD.trigger_test */ 11408 MLXSW_REG_MFDE_EVENT_ID_TEST, 11409 /* Triggered when firmware hits an assert */ 11410 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11411 /* Fatal error interrupt from hardware */ 11412 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11413 }; 11414 11415 /* reg_mfde_event_id 11416 * Access: RO 11417 */ 11418 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11419 11420 enum mlxsw_reg_mfde_method { 11421 MLXSW_REG_MFDE_METHOD_QUERY, 11422 MLXSW_REG_MFDE_METHOD_WRITE, 11423 }; 11424 11425 /* reg_mfde_method 11426 * Access: RO 11427 */ 11428 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11429 11430 /* reg_mfde_long_process 11431 * Indicates if the command is in long_process mode. 11432 * Access: RO 11433 */ 11434 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11435 11436 enum mlxsw_reg_mfde_command_type { 11437 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11438 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11439 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11440 }; 11441 11442 /* reg_mfde_command_type 11443 * Access: RO 11444 */ 11445 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11446 11447 /* reg_mfde_reg_attr_id 11448 * EMAD - register id, MAD - attibute id 11449 * Access: RO 11450 */ 11451 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11452 11453 /* reg_mfde_crspace_to_log_address 11454 * crspace address accessed, which resulted in timeout. 11455 * Access: RO 11456 */ 11457 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11458 11459 /* reg_mfde_crspace_to_oe 11460 * 0 - New event 11461 * 1 - Old event, occurred before MFGD activation. 11462 * Access: RO 11463 */ 11464 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11465 11466 /* reg_mfde_crspace_to_log_id 11467 * Which irisc triggered the timeout. 11468 * Access: RO 11469 */ 11470 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11471 11472 /* reg_mfde_crspace_to_log_ip 11473 * IP (instruction pointer) that triggered the timeout. 11474 * Access: RO 11475 */ 11476 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11477 11478 /* reg_mfde_kvd_im_stop_oe 11479 * 0 - New event 11480 * 1 - Old event, occurred before MFGD activation. 11481 * Access: RO 11482 */ 11483 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11484 11485 /* reg_mfde_kvd_im_stop_pipes_mask 11486 * Bit per kvh pipe. 11487 * Access: RO 11488 */ 11489 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11490 11491 /* reg_mfde_fw_assert_var0-4 11492 * Variables passed to assert. 11493 * Access: RO 11494 */ 11495 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11496 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11497 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11498 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11499 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11500 11501 /* reg_mfde_fw_assert_existptr 11502 * The instruction pointer when assert was triggered. 11503 * Access: RO 11504 */ 11505 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11506 11507 /* reg_mfde_fw_assert_callra 11508 * The return address after triggering assert. 11509 * Access: RO 11510 */ 11511 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11512 11513 /* reg_mfde_fw_assert_oe 11514 * 0 - New event 11515 * 1 - Old event, occurred before MFGD activation. 11516 * Access: RO 11517 */ 11518 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11519 11520 /* reg_mfde_fw_assert_tile_v 11521 * 0: The assert was from main 11522 * 1: The assert was from a tile 11523 * Access: RO 11524 */ 11525 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11526 11527 /* reg_mfde_fw_assert_tile_index 11528 * When tile_v=1, the tile_index that caused the assert. 11529 * Access: RO 11530 */ 11531 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11532 11533 /* reg_mfde_fw_assert_ext_synd 11534 * A generated one-to-one identifier which is specific per-assert. 11535 * Access: RO 11536 */ 11537 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11538 11539 /* reg_mfde_fatal_cause_id 11540 * HW interrupt cause id. 11541 * Access: RO 11542 */ 11543 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11544 11545 /* reg_mfde_fatal_cause_tile_v 11546 * 0: The assert was from main 11547 * 1: The assert was from a tile 11548 * Access: RO 11549 */ 11550 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11551 11552 /* reg_mfde_fatal_cause_tile_index 11553 * When tile_v=1, the tile_index that caused the assert. 11554 * Access: RO 11555 */ 11556 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11557 11558 /* TNGCR - Tunneling NVE General Configuration Register 11559 * ---------------------------------------------------- 11560 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11561 */ 11562 #define MLXSW_REG_TNGCR_ID 0xA001 11563 #define MLXSW_REG_TNGCR_LEN 0x44 11564 11565 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11566 11567 enum mlxsw_reg_tngcr_type { 11568 MLXSW_REG_TNGCR_TYPE_VXLAN, 11569 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11570 MLXSW_REG_TNGCR_TYPE_GENEVE, 11571 MLXSW_REG_TNGCR_TYPE_NVGRE, 11572 }; 11573 11574 /* reg_tngcr_type 11575 * Tunnel type for encapsulation and decapsulation. The types are mutually 11576 * exclusive. 11577 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11578 * Access: RW 11579 */ 11580 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11581 11582 /* reg_tngcr_nve_valid 11583 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11584 * Access: RW 11585 */ 11586 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11587 11588 /* reg_tngcr_nve_ttl_uc 11589 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11590 * Access: RW 11591 */ 11592 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11593 11594 /* reg_tngcr_nve_ttl_mc 11595 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11596 * Access: RW 11597 */ 11598 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11599 11600 enum { 11601 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11602 MLXSW_REG_TNGCR_FL_NO_COPY, 11603 /* Copy flow label from inner packet if packet is IPv6 and 11604 * encapsulation is by IPv6. Otherwise, calculate flow label using 11605 * nve_flh. 11606 */ 11607 MLXSW_REG_TNGCR_FL_COPY, 11608 }; 11609 11610 /* reg_tngcr_nve_flc 11611 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11612 * Access: RW 11613 */ 11614 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11615 11616 enum { 11617 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11618 * uses {nve_fl_prefix, nve_fl_suffix}. 11619 */ 11620 MLXSW_REG_TNGCR_FL_NO_HASH, 11621 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11622 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11623 */ 11624 MLXSW_REG_TNGCR_FL_HASH, 11625 }; 11626 11627 /* reg_tngcr_nve_flh 11628 * NVE flow label hash. 11629 * Access: RW 11630 */ 11631 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11632 11633 /* reg_tngcr_nve_fl_prefix 11634 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11635 * Access: RW 11636 */ 11637 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11638 11639 /* reg_tngcr_nve_fl_suffix 11640 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11641 * Reserved when nve_flh=1 and for Spectrum. 11642 * Access: RW 11643 */ 11644 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11645 11646 enum { 11647 /* Source UDP port is fixed (default '0') */ 11648 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11649 /* Source UDP port is calculated based on hash */ 11650 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11651 }; 11652 11653 /* reg_tngcr_nve_udp_sport_type 11654 * NVE UDP source port type. 11655 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11656 * When the source UDP port is calculated based on hash, then the 8 LSBs 11657 * are calculated from hash the 8 MSBs are configured by 11658 * nve_udp_sport_prefix. 11659 * Access: RW 11660 */ 11661 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11662 11663 /* reg_tngcr_nve_udp_sport_prefix 11664 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11665 * Reserved when NVE type is NVGRE. 11666 * Access: RW 11667 */ 11668 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11669 11670 /* reg_tngcr_nve_group_size_mc 11671 * The amount of sequential linked lists of MC entries. The first linked 11672 * list is configured by SFD.underlay_mc_ptr. 11673 * Valid values: 1, 2, 4, 8, 16, 32, 64 11674 * The linked list are configured by TNUMT. 11675 * The hash is set by LAG hash. 11676 * Access: RW 11677 */ 11678 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11679 11680 /* reg_tngcr_nve_group_size_flood 11681 * The amount of sequential linked lists of flooding entries. The first 11682 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11683 * Valid values: 1, 2, 4, 8, 16, 32, 64 11684 * The linked list are configured by TNUMT. 11685 * The hash is set by LAG hash. 11686 * Access: RW 11687 */ 11688 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11689 11690 /* reg_tngcr_learn_enable 11691 * During decapsulation, whether to learn from NVE port. 11692 * Reserved when Spectrum-2. See TNPC. 11693 * Access: RW 11694 */ 11695 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11696 11697 /* reg_tngcr_underlay_virtual_router 11698 * Underlay virtual router. 11699 * Reserved when Spectrum-2. 11700 * Access: RW 11701 */ 11702 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11703 11704 /* reg_tngcr_underlay_rif 11705 * Underlay ingress router interface. RIF type should be loopback generic. 11706 * Reserved when Spectrum. 11707 * Access: RW 11708 */ 11709 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11710 11711 /* reg_tngcr_usipv4 11712 * Underlay source IPv4 address of the NVE. 11713 * Access: RW 11714 */ 11715 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11716 11717 /* reg_tngcr_usipv6 11718 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11719 * modified under traffic of NVE tunneling encapsulation. 11720 * Access: RW 11721 */ 11722 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11723 11724 static inline void mlxsw_reg_tngcr_pack(char *payload, 11725 enum mlxsw_reg_tngcr_type type, 11726 bool valid, u8 ttl) 11727 { 11728 MLXSW_REG_ZERO(tngcr, payload); 11729 mlxsw_reg_tngcr_type_set(payload, type); 11730 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11731 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11732 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11733 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11734 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11735 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11736 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11737 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11738 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11739 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11740 } 11741 11742 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11743 * ------------------------------------------------------- 11744 * The TNUMT register is for building the underlay MC table. It is used 11745 * for MC, flooding and BC traffic into the NVE tunnel. 11746 */ 11747 #define MLXSW_REG_TNUMT_ID 0xA003 11748 #define MLXSW_REG_TNUMT_LEN 0x20 11749 11750 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11751 11752 enum mlxsw_reg_tnumt_record_type { 11753 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11754 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11755 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11756 }; 11757 11758 /* reg_tnumt_record_type 11759 * Record type. 11760 * Access: RW 11761 */ 11762 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11763 11764 /* reg_tnumt_tunnel_port 11765 * Tunnel port. 11766 * Access: RW 11767 */ 11768 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11769 11770 /* reg_tnumt_underlay_mc_ptr 11771 * Index to the underlay multicast table. 11772 * For Spectrum the index is to the KVD linear. 11773 * Access: Index 11774 */ 11775 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11776 11777 /* reg_tnumt_vnext 11778 * The next_underlay_mc_ptr is valid. 11779 * Access: RW 11780 */ 11781 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11782 11783 /* reg_tnumt_next_underlay_mc_ptr 11784 * The next index to the underlay multicast table. 11785 * Access: RW 11786 */ 11787 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11788 11789 /* reg_tnumt_record_size 11790 * Number of IP addresses in the record. 11791 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11792 * Access: RW 11793 */ 11794 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11795 11796 /* reg_tnumt_udip 11797 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11798 * Access: RW 11799 */ 11800 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11801 11802 /* reg_tnumt_udip_ptr 11803 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11804 * i >= size. The IPv6 addresses are configured by RIPS. 11805 * Access: RW 11806 */ 11807 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11808 11809 static inline void mlxsw_reg_tnumt_pack(char *payload, 11810 enum mlxsw_reg_tnumt_record_type type, 11811 enum mlxsw_reg_tunnel_port tport, 11812 u32 underlay_mc_ptr, bool vnext, 11813 u32 next_underlay_mc_ptr, 11814 u8 record_size) 11815 { 11816 MLXSW_REG_ZERO(tnumt, payload); 11817 mlxsw_reg_tnumt_record_type_set(payload, type); 11818 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 11819 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 11820 mlxsw_reg_tnumt_vnext_set(payload, vnext); 11821 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 11822 mlxsw_reg_tnumt_record_size_set(payload, record_size); 11823 } 11824 11825 /* TNQCR - Tunneling NVE QoS Configuration Register 11826 * ------------------------------------------------ 11827 * The TNQCR register configures how QoS is set in encapsulation into the 11828 * underlay network. 11829 */ 11830 #define MLXSW_REG_TNQCR_ID 0xA010 11831 #define MLXSW_REG_TNQCR_LEN 0x0C 11832 11833 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 11834 11835 /* reg_tnqcr_enc_set_dscp 11836 * For encapsulation: How to set DSCP field: 11837 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 11838 * (outer) IP header. If there is no IP header, use TNQDR.dscp 11839 * 1 - Set the DSCP field as TNQDR.dscp 11840 * Access: RW 11841 */ 11842 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 11843 11844 static inline void mlxsw_reg_tnqcr_pack(char *payload) 11845 { 11846 MLXSW_REG_ZERO(tnqcr, payload); 11847 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 11848 } 11849 11850 /* TNQDR - Tunneling NVE QoS Default Register 11851 * ------------------------------------------ 11852 * The TNQDR register configures the default QoS settings for NVE 11853 * encapsulation. 11854 */ 11855 #define MLXSW_REG_TNQDR_ID 0xA011 11856 #define MLXSW_REG_TNQDR_LEN 0x08 11857 11858 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 11859 11860 /* reg_tnqdr_local_port 11861 * Local port number (receive port). CPU port is supported. 11862 * Access: Index 11863 */ 11864 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 11865 11866 /* reg_tnqdr_dscp 11867 * For encapsulation, the default DSCP. 11868 * Access: RW 11869 */ 11870 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 11871 11872 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 11873 { 11874 MLXSW_REG_ZERO(tnqdr, payload); 11875 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 11876 mlxsw_reg_tnqdr_dscp_set(payload, 0); 11877 } 11878 11879 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 11880 * -------------------------------------------------------- 11881 * The TNEEM register maps ECN of the IP header at the ingress to the 11882 * encapsulation to the ECN of the underlay network. 11883 */ 11884 #define MLXSW_REG_TNEEM_ID 0xA012 11885 #define MLXSW_REG_TNEEM_LEN 0x0C 11886 11887 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 11888 11889 /* reg_tneem_overlay_ecn 11890 * ECN of the IP header in the overlay network. 11891 * Access: Index 11892 */ 11893 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 11894 11895 /* reg_tneem_underlay_ecn 11896 * ECN of the IP header in the underlay network. 11897 * Access: RW 11898 */ 11899 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 11900 11901 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 11902 u8 underlay_ecn) 11903 { 11904 MLXSW_REG_ZERO(tneem, payload); 11905 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 11906 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 11907 } 11908 11909 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 11910 * -------------------------------------------------------- 11911 * The TNDEM register configures the actions that are done in the 11912 * decapsulation. 11913 */ 11914 #define MLXSW_REG_TNDEM_ID 0xA013 11915 #define MLXSW_REG_TNDEM_LEN 0x0C 11916 11917 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 11918 11919 /* reg_tndem_underlay_ecn 11920 * ECN field of the IP header in the underlay network. 11921 * Access: Index 11922 */ 11923 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 11924 11925 /* reg_tndem_overlay_ecn 11926 * ECN field of the IP header in the overlay network. 11927 * Access: Index 11928 */ 11929 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 11930 11931 /* reg_tndem_eip_ecn 11932 * Egress IP ECN. ECN field of the IP header of the packet which goes out 11933 * from the decapsulation. 11934 * Access: RW 11935 */ 11936 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 11937 11938 /* reg_tndem_trap_en 11939 * Trap enable: 11940 * 0 - No trap due to decap ECN 11941 * 1 - Trap enable with trap_id 11942 * Access: RW 11943 */ 11944 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 11945 11946 /* reg_tndem_trap_id 11947 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 11948 * Reserved when trap_en is '0'. 11949 * Access: RW 11950 */ 11951 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 11952 11953 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 11954 u8 overlay_ecn, u8 ecn, bool trap_en, 11955 u16 trap_id) 11956 { 11957 MLXSW_REG_ZERO(tndem, payload); 11958 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 11959 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 11960 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 11961 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 11962 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 11963 } 11964 11965 /* TNPC - Tunnel Port Configuration Register 11966 * ----------------------------------------- 11967 * The TNPC register is used for tunnel port configuration. 11968 * Reserved when Spectrum. 11969 */ 11970 #define MLXSW_REG_TNPC_ID 0xA020 11971 #define MLXSW_REG_TNPC_LEN 0x18 11972 11973 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 11974 11975 /* reg_tnpc_tunnel_port 11976 * Tunnel port. 11977 * Access: Index 11978 */ 11979 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 11980 11981 /* reg_tnpc_learn_enable_v6 11982 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 11983 * Access: RW 11984 */ 11985 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 11986 11987 /* reg_tnpc_learn_enable_v4 11988 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 11989 * Access: RW 11990 */ 11991 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 11992 11993 static inline void mlxsw_reg_tnpc_pack(char *payload, 11994 enum mlxsw_reg_tunnel_port tport, 11995 bool learn_enable) 11996 { 11997 MLXSW_REG_ZERO(tnpc, payload); 11998 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 11999 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12000 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12001 } 12002 12003 /* TIGCR - Tunneling IPinIP General Configuration Register 12004 * ------------------------------------------------------- 12005 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12006 */ 12007 #define MLXSW_REG_TIGCR_ID 0xA801 12008 #define MLXSW_REG_TIGCR_LEN 0x10 12009 12010 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12011 12012 /* reg_tigcr_ipip_ttlc 12013 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12014 * header. 12015 * Access: RW 12016 */ 12017 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12018 12019 /* reg_tigcr_ipip_ttl_uc 12020 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12021 * reg_tigcr_ipip_ttlc is unset. 12022 * Access: RW 12023 */ 12024 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12025 12026 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12027 { 12028 MLXSW_REG_ZERO(tigcr, payload); 12029 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12030 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12031 } 12032 12033 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12034 * ----------------------------------------------------------- 12035 * The TIEEM register maps ECN of the IP header at the ingress to the 12036 * encapsulation to the ECN of the underlay network. 12037 */ 12038 #define MLXSW_REG_TIEEM_ID 0xA812 12039 #define MLXSW_REG_TIEEM_LEN 0x0C 12040 12041 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12042 12043 /* reg_tieem_overlay_ecn 12044 * ECN of the IP header in the overlay network. 12045 * Access: Index 12046 */ 12047 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12048 12049 /* reg_tineem_underlay_ecn 12050 * ECN of the IP header in the underlay network. 12051 * Access: RW 12052 */ 12053 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12054 12055 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12056 u8 underlay_ecn) 12057 { 12058 MLXSW_REG_ZERO(tieem, payload); 12059 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12060 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12061 } 12062 12063 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12064 * ----------------------------------------------------------- 12065 * The TIDEM register configures the actions that are done in the 12066 * decapsulation. 12067 */ 12068 #define MLXSW_REG_TIDEM_ID 0xA813 12069 #define MLXSW_REG_TIDEM_LEN 0x0C 12070 12071 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12072 12073 /* reg_tidem_underlay_ecn 12074 * ECN field of the IP header in the underlay network. 12075 * Access: Index 12076 */ 12077 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12078 12079 /* reg_tidem_overlay_ecn 12080 * ECN field of the IP header in the overlay network. 12081 * Access: Index 12082 */ 12083 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12084 12085 /* reg_tidem_eip_ecn 12086 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12087 * from the decapsulation. 12088 * Access: RW 12089 */ 12090 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12091 12092 /* reg_tidem_trap_en 12093 * Trap enable: 12094 * 0 - No trap due to decap ECN 12095 * 1 - Trap enable with trap_id 12096 * Access: RW 12097 */ 12098 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12099 12100 /* reg_tidem_trap_id 12101 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12102 * Reserved when trap_en is '0'. 12103 * Access: RW 12104 */ 12105 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12106 12107 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12108 u8 overlay_ecn, u8 eip_ecn, 12109 bool trap_en, u16 trap_id) 12110 { 12111 MLXSW_REG_ZERO(tidem, payload); 12112 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12113 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12114 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12115 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12116 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12117 } 12118 12119 /* SBPR - Shared Buffer Pools Register 12120 * ----------------------------------- 12121 * The SBPR configures and retrieves the shared buffer pools and configuration. 12122 */ 12123 #define MLXSW_REG_SBPR_ID 0xB001 12124 #define MLXSW_REG_SBPR_LEN 0x14 12125 12126 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12127 12128 /* shared direstion enum for SBPR, SBCM, SBPM */ 12129 enum mlxsw_reg_sbxx_dir { 12130 MLXSW_REG_SBXX_DIR_INGRESS, 12131 MLXSW_REG_SBXX_DIR_EGRESS, 12132 }; 12133 12134 /* reg_sbpr_dir 12135 * Direction. 12136 * Access: Index 12137 */ 12138 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12139 12140 /* reg_sbpr_pool 12141 * Pool index. 12142 * Access: Index 12143 */ 12144 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12145 12146 /* reg_sbpr_infi_size 12147 * Size is infinite. 12148 * Access: RW 12149 */ 12150 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12151 12152 /* reg_sbpr_size 12153 * Pool size in buffer cells. 12154 * Reserved when infi_size = 1. 12155 * Access: RW 12156 */ 12157 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12158 12159 enum mlxsw_reg_sbpr_mode { 12160 MLXSW_REG_SBPR_MODE_STATIC, 12161 MLXSW_REG_SBPR_MODE_DYNAMIC, 12162 }; 12163 12164 /* reg_sbpr_mode 12165 * Pool quota calculation mode. 12166 * Access: RW 12167 */ 12168 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12169 12170 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12171 enum mlxsw_reg_sbxx_dir dir, 12172 enum mlxsw_reg_sbpr_mode mode, u32 size, 12173 bool infi_size) 12174 { 12175 MLXSW_REG_ZERO(sbpr, payload); 12176 mlxsw_reg_sbpr_pool_set(payload, pool); 12177 mlxsw_reg_sbpr_dir_set(payload, dir); 12178 mlxsw_reg_sbpr_mode_set(payload, mode); 12179 mlxsw_reg_sbpr_size_set(payload, size); 12180 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12181 } 12182 12183 /* SBCM - Shared Buffer Class Management Register 12184 * ---------------------------------------------- 12185 * The SBCM register configures and retrieves the shared buffer allocation 12186 * and configuration according to Port-PG, including the binding to pool 12187 * and definition of the associated quota. 12188 */ 12189 #define MLXSW_REG_SBCM_ID 0xB002 12190 #define MLXSW_REG_SBCM_LEN 0x28 12191 12192 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12193 12194 /* reg_sbcm_local_port 12195 * Local port number. 12196 * For Ingress: excludes CPU port and Router port 12197 * For Egress: excludes IP Router 12198 * Access: Index 12199 */ 12200 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12201 12202 /* reg_sbcm_pg_buff 12203 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12204 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12205 * For traffic class: range is 0..cap_max_tclass - 1 12206 * Note that when traffic class is in MC aware mode then the traffic 12207 * classes which are MC aware cannot be configured. 12208 * Access: Index 12209 */ 12210 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12211 12212 /* reg_sbcm_dir 12213 * Direction. 12214 * Access: Index 12215 */ 12216 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12217 12218 /* reg_sbcm_min_buff 12219 * Minimum buffer size for the limiter, in cells. 12220 * Access: RW 12221 */ 12222 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12223 12224 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12225 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12226 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12227 12228 /* reg_sbcm_infi_max 12229 * Max buffer is infinite. 12230 * Access: RW 12231 */ 12232 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12233 12234 /* reg_sbcm_max_buff 12235 * When the pool associated to the port-pg/tclass is configured to 12236 * static, Maximum buffer size for the limiter configured in cells. 12237 * When the pool associated to the port-pg/tclass is configured to 12238 * dynamic, the max_buff holds the "alpha" parameter, supporting 12239 * the following values: 12240 * 0: 0 12241 * i: (1/128)*2^(i-1), for i=1..14 12242 * 0xFF: Infinity 12243 * Reserved when infi_max = 1. 12244 * Access: RW 12245 */ 12246 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12247 12248 /* reg_sbcm_pool 12249 * Association of the port-priority to a pool. 12250 * Access: RW 12251 */ 12252 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12253 12254 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12255 enum mlxsw_reg_sbxx_dir dir, 12256 u32 min_buff, u32 max_buff, 12257 bool infi_max, u8 pool) 12258 { 12259 MLXSW_REG_ZERO(sbcm, payload); 12260 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12261 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12262 mlxsw_reg_sbcm_dir_set(payload, dir); 12263 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12264 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12265 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12266 mlxsw_reg_sbcm_pool_set(payload, pool); 12267 } 12268 12269 /* SBPM - Shared Buffer Port Management Register 12270 * --------------------------------------------- 12271 * The SBPM register configures and retrieves the shared buffer allocation 12272 * and configuration according to Port-Pool, including the definition 12273 * of the associated quota. 12274 */ 12275 #define MLXSW_REG_SBPM_ID 0xB003 12276 #define MLXSW_REG_SBPM_LEN 0x28 12277 12278 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12279 12280 /* reg_sbpm_local_port 12281 * Local port number. 12282 * For Ingress: excludes CPU port and Router port 12283 * For Egress: excludes IP Router 12284 * Access: Index 12285 */ 12286 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12287 12288 /* reg_sbpm_pool 12289 * The pool associated to quota counting on the local_port. 12290 * Access: Index 12291 */ 12292 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12293 12294 /* reg_sbpm_dir 12295 * Direction. 12296 * Access: Index 12297 */ 12298 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12299 12300 /* reg_sbpm_buff_occupancy 12301 * Current buffer occupancy in cells. 12302 * Access: RO 12303 */ 12304 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12305 12306 /* reg_sbpm_clr 12307 * Clear Max Buffer Occupancy 12308 * When this bit is set, max_buff_occupancy field is cleared (and a 12309 * new max value is tracked from the time the clear was performed). 12310 * Access: OP 12311 */ 12312 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12313 12314 /* reg_sbpm_max_buff_occupancy 12315 * Maximum value of buffer occupancy in cells monitored. Cleared by 12316 * writing to the clr field. 12317 * Access: RO 12318 */ 12319 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12320 12321 /* reg_sbpm_min_buff 12322 * Minimum buffer size for the limiter, in cells. 12323 * Access: RW 12324 */ 12325 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12326 12327 /* reg_sbpm_max_buff 12328 * When the pool associated to the port-pg/tclass is configured to 12329 * static, Maximum buffer size for the limiter configured in cells. 12330 * When the pool associated to the port-pg/tclass is configured to 12331 * dynamic, the max_buff holds the "alpha" parameter, supporting 12332 * the following values: 12333 * 0: 0 12334 * i: (1/128)*2^(i-1), for i=1..14 12335 * 0xFF: Infinity 12336 * Access: RW 12337 */ 12338 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12339 12340 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12341 enum mlxsw_reg_sbxx_dir dir, bool clr, 12342 u32 min_buff, u32 max_buff) 12343 { 12344 MLXSW_REG_ZERO(sbpm, payload); 12345 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12346 mlxsw_reg_sbpm_pool_set(payload, pool); 12347 mlxsw_reg_sbpm_dir_set(payload, dir); 12348 mlxsw_reg_sbpm_clr_set(payload, clr); 12349 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12350 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12351 } 12352 12353 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12354 u32 *p_max_buff_occupancy) 12355 { 12356 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12357 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12358 } 12359 12360 /* SBMM - Shared Buffer Multicast Management Register 12361 * -------------------------------------------------- 12362 * The SBMM register configures and retrieves the shared buffer allocation 12363 * and configuration for MC packets according to Switch-Priority, including 12364 * the binding to pool and definition of the associated quota. 12365 */ 12366 #define MLXSW_REG_SBMM_ID 0xB004 12367 #define MLXSW_REG_SBMM_LEN 0x28 12368 12369 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12370 12371 /* reg_sbmm_prio 12372 * Switch Priority. 12373 * Access: Index 12374 */ 12375 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12376 12377 /* reg_sbmm_min_buff 12378 * Minimum buffer size for the limiter, in cells. 12379 * Access: RW 12380 */ 12381 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12382 12383 /* reg_sbmm_max_buff 12384 * When the pool associated to the port-pg/tclass is configured to 12385 * static, Maximum buffer size for the limiter configured in cells. 12386 * When the pool associated to the port-pg/tclass is configured to 12387 * dynamic, the max_buff holds the "alpha" parameter, supporting 12388 * the following values: 12389 * 0: 0 12390 * i: (1/128)*2^(i-1), for i=1..14 12391 * 0xFF: Infinity 12392 * Access: RW 12393 */ 12394 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12395 12396 /* reg_sbmm_pool 12397 * Association of the port-priority to a pool. 12398 * Access: RW 12399 */ 12400 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12401 12402 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12403 u32 max_buff, u8 pool) 12404 { 12405 MLXSW_REG_ZERO(sbmm, payload); 12406 mlxsw_reg_sbmm_prio_set(payload, prio); 12407 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12408 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12409 mlxsw_reg_sbmm_pool_set(payload, pool); 12410 } 12411 12412 /* SBSR - Shared Buffer Status Register 12413 * ------------------------------------ 12414 * The SBSR register retrieves the shared buffer occupancy according to 12415 * Port-Pool. Note that this register enables reading a large amount of data. 12416 * It is the user's responsibility to limit the amount of data to ensure the 12417 * response can match the maximum transfer unit. In case the response exceeds 12418 * the maximum transport unit, it will be truncated with no special notice. 12419 */ 12420 #define MLXSW_REG_SBSR_ID 0xB005 12421 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12422 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12423 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12424 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12425 MLXSW_REG_SBSR_REC_LEN * \ 12426 MLXSW_REG_SBSR_REC_MAX_COUNT) 12427 12428 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12429 12430 /* reg_sbsr_clr 12431 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12432 * field is cleared (and a new max value is tracked from the time the clear 12433 * was performed). 12434 * Access: OP 12435 */ 12436 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12437 12438 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12439 12440 /* reg_sbsr_port_page 12441 * Determines the range of the ports specified in the 'ingress_port_mask' 12442 * and 'egress_port_mask' bit masks. 12443 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12444 * Access: Index 12445 */ 12446 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12447 12448 /* reg_sbsr_ingress_port_mask 12449 * Bit vector for all ingress network ports. 12450 * Indicates which of the ports (for which the relevant bit is set) 12451 * are affected by the set operation. Configuration of any other port 12452 * does not change. 12453 * Access: Index 12454 */ 12455 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12456 12457 /* reg_sbsr_pg_buff_mask 12458 * Bit vector for all switch priority groups. 12459 * Indicates which of the priorities (for which the relevant bit is set) 12460 * are affected by the set operation. Configuration of any other priority 12461 * does not change. 12462 * Range is 0..cap_max_pg_buffers - 1 12463 * Access: Index 12464 */ 12465 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12466 12467 /* reg_sbsr_egress_port_mask 12468 * Bit vector for all egress network ports. 12469 * Indicates which of the ports (for which the relevant bit is set) 12470 * are affected by the set operation. Configuration of any other port 12471 * does not change. 12472 * Access: Index 12473 */ 12474 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12475 12476 /* reg_sbsr_tclass_mask 12477 * Bit vector for all traffic classes. 12478 * Indicates which of the traffic classes (for which the relevant bit is 12479 * set) are affected by the set operation. Configuration of any other 12480 * traffic class does not change. 12481 * Range is 0..cap_max_tclass - 1 12482 * Access: Index 12483 */ 12484 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12485 12486 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12487 { 12488 MLXSW_REG_ZERO(sbsr, payload); 12489 mlxsw_reg_sbsr_clr_set(payload, clr); 12490 } 12491 12492 /* reg_sbsr_rec_buff_occupancy 12493 * Current buffer occupancy in cells. 12494 * Access: RO 12495 */ 12496 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12497 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12498 12499 /* reg_sbsr_rec_max_buff_occupancy 12500 * Maximum value of buffer occupancy in cells monitored. Cleared by 12501 * writing to the clr field. 12502 * Access: RO 12503 */ 12504 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12505 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12506 12507 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12508 u32 *p_buff_occupancy, 12509 u32 *p_max_buff_occupancy) 12510 { 12511 *p_buff_occupancy = 12512 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12513 *p_max_buff_occupancy = 12514 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12515 } 12516 12517 /* SBIB - Shared Buffer Internal Buffer Register 12518 * --------------------------------------------- 12519 * The SBIB register configures per port buffers for internal use. The internal 12520 * buffers consume memory on the port buffers (note that the port buffers are 12521 * used also by PBMC). 12522 * 12523 * For Spectrum this is used for egress mirroring. 12524 */ 12525 #define MLXSW_REG_SBIB_ID 0xB006 12526 #define MLXSW_REG_SBIB_LEN 0x10 12527 12528 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12529 12530 /* reg_sbib_local_port 12531 * Local port number 12532 * Not supported for CPU port and router port 12533 * Access: Index 12534 */ 12535 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12536 12537 /* reg_sbib_buff_size 12538 * Units represented in cells 12539 * Allowed range is 0 to (cap_max_headroom_size - 1) 12540 * Default is 0 12541 * Access: RW 12542 */ 12543 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12544 12545 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12546 u32 buff_size) 12547 { 12548 MLXSW_REG_ZERO(sbib, payload); 12549 mlxsw_reg_sbib_local_port_set(payload, local_port); 12550 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12551 } 12552 12553 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12554 MLXSW_REG(sgcr), 12555 MLXSW_REG(spad), 12556 MLXSW_REG(sspr), 12557 MLXSW_REG(sfdat), 12558 MLXSW_REG(sfd), 12559 MLXSW_REG(sfn), 12560 MLXSW_REG(spms), 12561 MLXSW_REG(spvid), 12562 MLXSW_REG(spvm), 12563 MLXSW_REG(spaft), 12564 MLXSW_REG(sfgc), 12565 MLXSW_REG(sfdf), 12566 MLXSW_REG(sldr), 12567 MLXSW_REG(slcr), 12568 MLXSW_REG(slcor), 12569 MLXSW_REG(spmlr), 12570 MLXSW_REG(svfa), 12571 MLXSW_REG(spvtr), 12572 MLXSW_REG(svpe), 12573 MLXSW_REG(sfmr), 12574 MLXSW_REG(spvmlr), 12575 MLXSW_REG(spvc), 12576 MLXSW_REG(spevet), 12577 MLXSW_REG(sftr2), 12578 MLXSW_REG(smid2), 12579 MLXSW_REG(cwtp), 12580 MLXSW_REG(cwtpm), 12581 MLXSW_REG(pgcr), 12582 MLXSW_REG(ppbt), 12583 MLXSW_REG(pacl), 12584 MLXSW_REG(pagt), 12585 MLXSW_REG(ptar), 12586 MLXSW_REG(ppbs), 12587 MLXSW_REG(prcr), 12588 MLXSW_REG(pefa), 12589 MLXSW_REG(pemrbt), 12590 MLXSW_REG(ptce2), 12591 MLXSW_REG(perpt), 12592 MLXSW_REG(peabfe), 12593 MLXSW_REG(perar), 12594 MLXSW_REG(ptce3), 12595 MLXSW_REG(percr), 12596 MLXSW_REG(pererp), 12597 MLXSW_REG(iedr), 12598 MLXSW_REG(qpts), 12599 MLXSW_REG(qpcr), 12600 MLXSW_REG(qtct), 12601 MLXSW_REG(qeec), 12602 MLXSW_REG(qrwe), 12603 MLXSW_REG(qpdsm), 12604 MLXSW_REG(qpdp), 12605 MLXSW_REG(qpdpm), 12606 MLXSW_REG(qtctm), 12607 MLXSW_REG(qpsc), 12608 MLXSW_REG(pmlp), 12609 MLXSW_REG(pmtu), 12610 MLXSW_REG(ptys), 12611 MLXSW_REG(ppad), 12612 MLXSW_REG(paos), 12613 MLXSW_REG(pfcc), 12614 MLXSW_REG(ppcnt), 12615 MLXSW_REG(plib), 12616 MLXSW_REG(pptb), 12617 MLXSW_REG(pbmc), 12618 MLXSW_REG(pspa), 12619 MLXSW_REG(pmaos), 12620 MLXSW_REG(pplr), 12621 MLXSW_REG(pmtdb), 12622 MLXSW_REG(pmpe), 12623 MLXSW_REG(pddr), 12624 MLXSW_REG(pmmp), 12625 MLXSW_REG(pllp), 12626 MLXSW_REG(pmtm), 12627 MLXSW_REG(htgt), 12628 MLXSW_REG(hpkt), 12629 MLXSW_REG(rgcr), 12630 MLXSW_REG(ritr), 12631 MLXSW_REG(rtar), 12632 MLXSW_REG(ratr), 12633 MLXSW_REG(rtdp), 12634 MLXSW_REG(rips), 12635 MLXSW_REG(ratrad), 12636 MLXSW_REG(rdpm), 12637 MLXSW_REG(ricnt), 12638 MLXSW_REG(rrcr), 12639 MLXSW_REG(ralta), 12640 MLXSW_REG(ralst), 12641 MLXSW_REG(raltb), 12642 MLXSW_REG(ralue), 12643 MLXSW_REG(rauht), 12644 MLXSW_REG(raleu), 12645 MLXSW_REG(rauhtd), 12646 MLXSW_REG(rigr2), 12647 MLXSW_REG(recr2), 12648 MLXSW_REG(rmft2), 12649 MLXSW_REG(rxlte), 12650 MLXSW_REG(rxltm), 12651 MLXSW_REG(rlcmld), 12652 MLXSW_REG(rlpmce), 12653 MLXSW_REG(xltq), 12654 MLXSW_REG(xmdr), 12655 MLXSW_REG(xrmt), 12656 MLXSW_REG(xralta), 12657 MLXSW_REG(xralst), 12658 MLXSW_REG(xraltb), 12659 MLXSW_REG(mfcr), 12660 MLXSW_REG(mfsc), 12661 MLXSW_REG(mfsm), 12662 MLXSW_REG(mfsl), 12663 MLXSW_REG(fore), 12664 MLXSW_REG(mtcap), 12665 MLXSW_REG(mtmp), 12666 MLXSW_REG(mtwe), 12667 MLXSW_REG(mtbr), 12668 MLXSW_REG(mcia), 12669 MLXSW_REG(mpat), 12670 MLXSW_REG(mpar), 12671 MLXSW_REG(mgir), 12672 MLXSW_REG(mrsr), 12673 MLXSW_REG(mlcr), 12674 MLXSW_REG(mcion), 12675 MLXSW_REG(mtpps), 12676 MLXSW_REG(mtutc), 12677 MLXSW_REG(mpsc), 12678 MLXSW_REG(mcqi), 12679 MLXSW_REG(mcc), 12680 MLXSW_REG(mcda), 12681 MLXSW_REG(mgpc), 12682 MLXSW_REG(mprs), 12683 MLXSW_REG(mogcr), 12684 MLXSW_REG(mpagr), 12685 MLXSW_REG(momte), 12686 MLXSW_REG(mtpppc), 12687 MLXSW_REG(mtpptr), 12688 MLXSW_REG(mtptpt), 12689 MLXSW_REG(mfgd), 12690 MLXSW_REG(mgpir), 12691 MLXSW_REG(mfde), 12692 MLXSW_REG(tngcr), 12693 MLXSW_REG(tnumt), 12694 MLXSW_REG(tnqcr), 12695 MLXSW_REG(tnqdr), 12696 MLXSW_REG(tneem), 12697 MLXSW_REG(tndem), 12698 MLXSW_REG(tnpc), 12699 MLXSW_REG(tigcr), 12700 MLXSW_REG(tieem), 12701 MLXSW_REG(tidem), 12702 MLXSW_REG(sbpr), 12703 MLXSW_REG(sbcm), 12704 MLXSW_REG(sbpm), 12705 MLXSW_REG(sbmm), 12706 MLXSW_REG(sbsr), 12707 MLXSW_REG(sbib), 12708 }; 12709 12710 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12711 { 12712 const struct mlxsw_reg_info *reg_info; 12713 int i; 12714 12715 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12716 reg_info = mlxsw_reg_infos[i]; 12717 if (reg_info->id == reg_id) 12718 return reg_info->name; 12719 } 12720 return "*UNKNOWN*"; 12721 } 12722 12723 /* PUDE - Port Up / Down Event 12724 * --------------------------- 12725 * Reports the operational state change of a port. 12726 */ 12727 #define MLXSW_REG_PUDE_LEN 0x10 12728 12729 /* reg_pude_swid 12730 * Switch partition ID with which to associate the port. 12731 * Access: Index 12732 */ 12733 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12734 12735 /* reg_pude_local_port 12736 * Local port number. 12737 * Access: Index 12738 */ 12739 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12740 12741 /* reg_pude_admin_status 12742 * Port administrative state (the desired state). 12743 * 1 - Up. 12744 * 2 - Down. 12745 * 3 - Up once. This means that in case of link failure, the port won't go 12746 * into polling mode, but will wait to be re-enabled by software. 12747 * 4 - Disabled by system. Can only be set by hardware. 12748 * Access: RO 12749 */ 12750 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12751 12752 /* reg_pude_oper_status 12753 * Port operatioanl state. 12754 * 1 - Up. 12755 * 2 - Down. 12756 * 3 - Down by port failure. This means that the device will not let the 12757 * port up again until explicitly specified by software. 12758 * Access: RO 12759 */ 12760 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12761 12762 #endif 12763