1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_set_vid 326 * Set VID. 327 * 0 - Do not update VID. 328 * 1 - Set VID. 329 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 330 * Access: RW 331 * 332 * Note: Reserved when legacy bridge model is used. 333 */ 334 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 335 MLXSW_REG_SFD_REC_LEN, 0x08, false); 336 337 /* reg_sfd_uc_fid_vid 338 * Filtering ID or VLAN ID 339 * For SwitchX and SwitchX-2: 340 * - Dynamic entries (policy 2,3) use FID 341 * - Static entries (policy 0) use VID 342 * - When independent learning is configured, VID=FID 343 * For Spectrum: use FID for both Dynamic and Static entries. 344 * VID should not be used. 345 * Access: Index 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 348 MLXSW_REG_SFD_REC_LEN, 0x08, false); 349 350 /* reg_sfd_uc_vid 351 * New VID when set_vid=1. 352 * Access: RW 353 * 354 * Note: Reserved when legacy bridge model is used and when set_vid=0. 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 357 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 358 359 /* reg_sfd_uc_system_port 360 * Unique port identifier for the final destination of the packet. 361 * Access: RW 362 */ 363 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 364 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 365 366 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 367 enum mlxsw_reg_sfd_rec_type rec_type, 368 const char *mac, 369 enum mlxsw_reg_sfd_rec_action action) 370 { 371 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 372 373 if (rec_index >= num_rec) 374 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 375 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 376 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 377 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 378 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 379 } 380 381 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 382 enum mlxsw_reg_sfd_rec_policy policy, 383 const char *mac, u16 fid_vid, u16 vid, 384 enum mlxsw_reg_sfd_rec_action action, 385 u16 local_port) 386 { 387 mlxsw_reg_sfd_rec_pack(payload, rec_index, 388 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 389 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 390 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 391 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 392 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 393 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 394 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 395 } 396 397 /* reg_sfd_uc_lag_sub_port 398 * LAG sub port. 399 * Must be 0 if multichannel VEPA is not enabled. 400 * Access: RW 401 */ 402 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 403 MLXSW_REG_SFD_REC_LEN, 0x08, false); 404 405 /* reg_sfd_uc_lag_set_vid 406 * Set VID. 407 * 0 - Do not update VID. 408 * 1 - Set VID. 409 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 410 * Access: RW 411 * 412 * Note: Reserved when legacy bridge model is used. 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_lag_fid_vid 418 * Filtering ID or VLAN ID 419 * For SwitchX and SwitchX-2: 420 * - Dynamic entries (policy 2,3) use FID 421 * - Static entries (policy 0) use VID 422 * - When independent learning is configured, VID=FID 423 * For Spectrum: use FID for both Dynamic and Static entries. 424 * VID should not be used. 425 * Access: Index 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 428 MLXSW_REG_SFD_REC_LEN, 0x08, false); 429 430 /* reg_sfd_uc_lag_lag_vid 431 * New vlan ID. 432 * Access: RW 433 * 434 * Note: Reserved when legacy bridge model is used and set_vid=0. 435 */ 436 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 437 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 438 439 /* reg_sfd_uc_lag_lag_id 440 * LAG Identifier - pointer into the LAG descriptor table. 441 * Access: RW 442 */ 443 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 444 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 445 446 static inline void 447 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 448 enum mlxsw_reg_sfd_rec_policy policy, 449 const char *mac, u16 fid_vid, 450 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 451 u16 lag_id) 452 { 453 mlxsw_reg_sfd_rec_pack(payload, rec_index, 454 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 455 mac, action); 456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 457 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 458 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 459 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 460 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 461 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 462 } 463 464 /* reg_sfd_mc_pgi 465 * 466 * Multicast port group index - index into the port group table. 467 * Value 0x1FFF indicates the pgi should point to the MID entry. 468 * For Spectrum this value must be set to 0x1FFF 469 * Access: RW 470 */ 471 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 472 MLXSW_REG_SFD_REC_LEN, 0x08, false); 473 474 /* reg_sfd_mc_fid_vid 475 * 476 * Filtering ID or VLAN ID 477 * Access: Index 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x08, false); 481 482 /* reg_sfd_mc_mid 483 * 484 * Multicast identifier - global identifier that represents the multicast 485 * group across all devices. 486 * Access: RW 487 */ 488 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 489 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 490 491 static inline void 492 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 493 const char *mac, u16 fid_vid, 494 enum mlxsw_reg_sfd_rec_action action, u16 mid) 495 { 496 mlxsw_reg_sfd_rec_pack(payload, rec_index, 497 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 498 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 499 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 500 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 501 } 502 503 /* reg_sfd_uc_tunnel_uip_msb 504 * When protocol is IPv4, the most significant byte of the underlay IPv4 505 * destination IP. 506 * When protocol is IPv6, reserved. 507 * Access: RW 508 */ 509 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 510 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 511 512 /* reg_sfd_uc_tunnel_fid 513 * Filtering ID. 514 * Access: Index 515 */ 516 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 517 MLXSW_REG_SFD_REC_LEN, 0x08, false); 518 519 enum mlxsw_reg_sfd_uc_tunnel_protocol { 520 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 521 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 522 }; 523 524 /* reg_sfd_uc_tunnel_protocol 525 * IP protocol. 526 * Access: RW 527 */ 528 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 529 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 530 531 /* reg_sfd_uc_tunnel_uip_lsb 532 * When protocol is IPv4, the least significant bytes of the underlay 533 * IPv4 destination IP. 534 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 535 * which is configured by RIPS. 536 * Access: RW 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 539 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 540 541 static inline void 542 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 543 enum mlxsw_reg_sfd_rec_policy policy, 544 const char *mac, u16 fid, 545 enum mlxsw_reg_sfd_rec_action action, 546 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 547 { 548 mlxsw_reg_sfd_rec_pack(payload, rec_index, 549 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 550 action); 551 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 552 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 553 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 554 } 555 556 static inline void 557 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 558 enum mlxsw_reg_sfd_rec_policy policy, 559 const char *mac, u16 fid, 560 enum mlxsw_reg_sfd_rec_action action, u32 uip) 561 { 562 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 563 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 564 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 565 action, 566 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 567 } 568 569 static inline void 570 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 571 u16 fid, enum mlxsw_reg_sfd_rec_action action, 572 u32 uip_ptr) 573 { 574 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 575 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 576 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 577 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 578 mac, fid, action, 579 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 580 } 581 582 enum mlxsw_reg_tunnel_port { 583 MLXSW_REG_TUNNEL_PORT_NVE, 584 MLXSW_REG_TUNNEL_PORT_VPLS, 585 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 586 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 587 }; 588 589 /* SFN - Switch FDB Notification Register 590 * ------------------------------------------- 591 * The switch provides notifications on newly learned FDB entries and 592 * aged out entries. The notifications can be polled by software. 593 */ 594 #define MLXSW_REG_SFN_ID 0x200B 595 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 596 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 597 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 598 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 599 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 600 601 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 602 603 /* reg_sfn_swid 604 * Switch partition ID. 605 * Access: Index 606 */ 607 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 608 609 /* reg_sfn_end 610 * Forces the current session to end. 611 * Access: OP 612 */ 613 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 614 615 /* reg_sfn_num_rec 616 * Request: Number of learned notifications and aged-out notification 617 * records requested. 618 * Response: Number of notification records returned (must be smaller 619 * than or equal to the value requested) 620 * Ranges 0..64 621 * Access: OP 622 */ 623 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 624 625 static inline void mlxsw_reg_sfn_pack(char *payload) 626 { 627 MLXSW_REG_ZERO(sfn, payload); 628 mlxsw_reg_sfn_swid_set(payload, 0); 629 mlxsw_reg_sfn_end_set(payload, 0); 630 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 631 } 632 633 /* reg_sfn_rec_swid 634 * Switch partition ID. 635 * Access: RO 636 */ 637 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 638 MLXSW_REG_SFN_REC_LEN, 0x00, false); 639 640 enum mlxsw_reg_sfn_rec_type { 641 /* MAC addresses learned on a regular port. */ 642 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 643 /* MAC addresses learned on a LAG port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 645 /* Aged-out MAC address on a regular port. */ 646 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 647 /* Aged-out MAC address on a LAG port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 649 /* Learned unicast tunnel record. */ 650 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 651 /* Aged-out unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 653 }; 654 655 /* reg_sfn_rec_type 656 * Notification record type. 657 * Access: RO 658 */ 659 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 660 MLXSW_REG_SFN_REC_LEN, 0x00, false); 661 662 /* reg_sfn_rec_mac 663 * MAC address. 664 * Access: RO 665 */ 666 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 667 MLXSW_REG_SFN_REC_LEN, 0x02); 668 669 /* reg_sfn_mac_sub_port 670 * VEPA channel on the local port. 671 * 0 if multichannel VEPA is not enabled. 672 * Access: RO 673 */ 674 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 675 MLXSW_REG_SFN_REC_LEN, 0x08, false); 676 677 /* reg_sfn_mac_fid 678 * Filtering identifier. 679 * Access: RO 680 */ 681 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 682 MLXSW_REG_SFN_REC_LEN, 0x08, false); 683 684 /* reg_sfn_mac_system_port 685 * Unique port identifier for the final destination of the packet. 686 * Access: RO 687 */ 688 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 689 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 690 691 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 692 char *mac, u16 *p_vid, 693 u16 *p_local_port) 694 { 695 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 696 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 697 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 698 } 699 700 /* reg_sfn_mac_lag_lag_id 701 * LAG ID (pointer into the LAG descriptor table). 702 * Access: RO 703 */ 704 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 705 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 706 707 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 708 char *mac, u16 *p_vid, 709 u16 *p_lag_id) 710 { 711 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 712 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 713 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 714 } 715 716 /* reg_sfn_uc_tunnel_uip_msb 717 * When protocol is IPv4, the most significant byte of the underlay IPv4 718 * address of the remote VTEP. 719 * When protocol is IPv6, reserved. 720 * Access: RO 721 */ 722 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 723 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 724 725 enum mlxsw_reg_sfn_uc_tunnel_protocol { 726 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 727 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 728 }; 729 730 /* reg_sfn_uc_tunnel_protocol 731 * IP protocol. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 735 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_uip_lsb 738 * When protocol is IPv4, the least significant bytes of the underlay 739 * IPv4 address of the remote VTEP. 740 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 741 * Access: RO 742 */ 743 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 744 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 745 746 /* reg_sfn_uc_tunnel_port 747 * Tunnel port. 748 * Reserved on Spectrum. 749 * Access: RO 750 */ 751 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 752 MLXSW_REG_SFN_REC_LEN, 0x10, false); 753 754 static inline void 755 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 756 u16 *p_fid, u32 *p_uip, 757 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 758 { 759 u32 uip_msb, uip_lsb; 760 761 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 762 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 763 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 764 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 765 *p_uip = uip_msb << 24 | uip_lsb; 766 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 767 } 768 769 /* SPMS - Switch Port MSTP/RSTP State Register 770 * ------------------------------------------- 771 * Configures the spanning tree state of a physical port. 772 */ 773 #define MLXSW_REG_SPMS_ID 0x200D 774 #define MLXSW_REG_SPMS_LEN 0x404 775 776 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 777 778 /* reg_spms_local_port 779 * Local port number. 780 * Access: Index 781 */ 782 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 783 784 enum mlxsw_reg_spms_state { 785 MLXSW_REG_SPMS_STATE_NO_CHANGE, 786 MLXSW_REG_SPMS_STATE_DISCARDING, 787 MLXSW_REG_SPMS_STATE_LEARNING, 788 MLXSW_REG_SPMS_STATE_FORWARDING, 789 }; 790 791 /* reg_spms_state 792 * Spanning tree state of each VLAN ID (VID) of the local port. 793 * 0 - Do not change spanning tree state (used only when writing). 794 * 1 - Discarding. No learning or forwarding to/from this port (default). 795 * 2 - Learning. Port is learning, but not forwarding. 796 * 3 - Forwarding. Port is learning and forwarding. 797 * Access: RW 798 */ 799 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 800 801 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 802 { 803 MLXSW_REG_ZERO(spms, payload); 804 mlxsw_reg_spms_local_port_set(payload, local_port); 805 } 806 807 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 808 enum mlxsw_reg_spms_state state) 809 { 810 mlxsw_reg_spms_state_set(payload, vid, state); 811 } 812 813 /* SPVID - Switch Port VID 814 * ----------------------- 815 * The switch port VID configures the default VID for a port. 816 */ 817 #define MLXSW_REG_SPVID_ID 0x200E 818 #define MLXSW_REG_SPVID_LEN 0x08 819 820 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 821 822 /* reg_spvid_tport 823 * Port is tunnel port. 824 * Reserved when SwitchX/-2 or Spectrum-1. 825 * Access: Index 826 */ 827 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 828 829 /* reg_spvid_local_port 830 * When tport = 0: Local port number. Not supported for CPU port. 831 * When tport = 1: Tunnel port. 832 * Access: Index 833 */ 834 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 835 836 /* reg_spvid_sub_port 837 * Virtual port within the physical port. 838 * Should be set to 0 when virtual ports are not enabled on the port. 839 * Access: Index 840 */ 841 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 842 843 /* reg_spvid_egr_et_set 844 * When VLAN is pushed at ingress (for untagged packets or for 845 * QinQ push mode) then the EtherType is decided at the egress port. 846 * Reserved when Spectrum-1. 847 * Access: RW 848 */ 849 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 850 851 /* reg_spvid_et_vlan 852 * EtherType used for when VLAN is pushed at ingress (for untagged 853 * packets or for QinQ push mode). 854 * 0: ether_type0 - (default) 855 * 1: ether_type1 856 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 857 * Ethertype IDs are configured by SVER. 858 * Reserved when egr_et_set = 1. 859 * Access: RW 860 */ 861 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 862 863 /* reg_spvid_pvid 864 * Port default VID 865 * Access: RW 866 */ 867 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 868 869 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 870 u8 et_vlan) 871 { 872 MLXSW_REG_ZERO(spvid, payload); 873 mlxsw_reg_spvid_local_port_set(payload, local_port); 874 mlxsw_reg_spvid_pvid_set(payload, pvid); 875 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 876 } 877 878 /* SPVM - Switch Port VLAN Membership 879 * ---------------------------------- 880 * The Switch Port VLAN Membership register configures the VLAN membership 881 * of a port in a VLAN denoted by VID. VLAN membership is managed per 882 * virtual port. The register can be used to add and remove VID(s) from a port. 883 */ 884 #define MLXSW_REG_SPVM_ID 0x200F 885 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 886 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 887 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 888 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 889 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 890 891 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 892 893 /* reg_spvm_pt 894 * Priority tagged. If this bit is set, packets forwarded to the port with 895 * untagged VLAN membership (u bit is set) will be tagged with priority tag 896 * (VID=0) 897 * Access: RW 898 */ 899 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 900 901 /* reg_spvm_pte 902 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 903 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 904 * Access: WO 905 */ 906 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 907 908 /* reg_spvm_local_port 909 * Local port number. 910 * Access: Index 911 */ 912 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 913 914 /* reg_spvm_sub_port 915 * Virtual port within the physical port. 916 * Should be set to 0 when virtual ports are not enabled on the port. 917 * Access: Index 918 */ 919 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 920 921 /* reg_spvm_num_rec 922 * Number of records to update. Each record contains: i, e, u, vid. 923 * Access: OP 924 */ 925 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 926 927 /* reg_spvm_rec_i 928 * Ingress membership in VLAN ID. 929 * Access: Index 930 */ 931 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 932 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 933 MLXSW_REG_SPVM_REC_LEN, 0, false); 934 935 /* reg_spvm_rec_e 936 * Egress membership in VLAN ID. 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 940 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_u 944 * Untagged - port is an untagged member - egress transmission uses untagged 945 * frames on VID<n> 946 * Access: Index 947 */ 948 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 949 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 950 MLXSW_REG_SPVM_REC_LEN, 0, false); 951 952 /* reg_spvm_rec_vid 953 * Egress membership in VLAN ID. 954 * Access: Index 955 */ 956 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 957 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 958 MLXSW_REG_SPVM_REC_LEN, 0, false); 959 960 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 961 u16 vid_begin, u16 vid_end, 962 bool is_member, bool untagged) 963 { 964 int size = vid_end - vid_begin + 1; 965 int i; 966 967 MLXSW_REG_ZERO(spvm, payload); 968 mlxsw_reg_spvm_local_port_set(payload, local_port); 969 mlxsw_reg_spvm_num_rec_set(payload, size); 970 971 for (i = 0; i < size; i++) { 972 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 973 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 974 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 975 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 976 } 977 } 978 979 /* SPAFT - Switch Port Acceptable Frame Types 980 * ------------------------------------------ 981 * The Switch Port Acceptable Frame Types register configures the frame 982 * admittance of the port. 983 */ 984 #define MLXSW_REG_SPAFT_ID 0x2010 985 #define MLXSW_REG_SPAFT_LEN 0x08 986 987 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 988 989 /* reg_spaft_local_port 990 * Local port number. 991 * Access: Index 992 * 993 * Note: CPU port is not supported (all tag types are allowed). 994 */ 995 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 996 997 /* reg_spaft_sub_port 998 * Virtual port within the physical port. 999 * Should be set to 0 when virtual ports are not enabled on the port. 1000 * Access: RW 1001 */ 1002 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1003 1004 /* reg_spaft_allow_untagged 1005 * When set, untagged frames on the ingress are allowed (default). 1006 * Access: RW 1007 */ 1008 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1009 1010 /* reg_spaft_allow_prio_tagged 1011 * When set, priority tagged frames on the ingress are allowed (default). 1012 * Access: RW 1013 */ 1014 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1015 1016 /* reg_spaft_allow_tagged 1017 * When set, tagged frames on the ingress are allowed (default). 1018 * Access: RW 1019 */ 1020 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1021 1022 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1023 bool allow_untagged) 1024 { 1025 MLXSW_REG_ZERO(spaft, payload); 1026 mlxsw_reg_spaft_local_port_set(payload, local_port); 1027 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1028 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1029 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1030 } 1031 1032 /* SFGC - Switch Flooding Group Configuration 1033 * ------------------------------------------ 1034 * The following register controls the association of flooding tables and MIDs 1035 * to packet types used for flooding. 1036 */ 1037 #define MLXSW_REG_SFGC_ID 0x2011 1038 #define MLXSW_REG_SFGC_LEN 0x14 1039 1040 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1041 1042 enum mlxsw_reg_sfgc_type { 1043 MLXSW_REG_SFGC_TYPE_BROADCAST, 1044 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1045 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1046 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1047 MLXSW_REG_SFGC_TYPE_RESERVED, 1048 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1049 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1050 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1051 MLXSW_REG_SFGC_TYPE_MAX, 1052 }; 1053 1054 /* reg_sfgc_type 1055 * The traffic type to reach the flooding table. 1056 * Access: Index 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1059 1060 /* bridge_type is used in SFGC and SFMR. */ 1061 enum mlxsw_reg_bridge_type { 1062 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1063 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1064 }; 1065 1066 /* reg_sfgc_bridge_type 1067 * Access: Index 1068 * 1069 * Note: SwitchX-2 only supports 802.1Q mode. 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1072 1073 enum mlxsw_flood_table_type { 1074 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1075 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1076 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1077 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1078 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1079 }; 1080 1081 /* reg_sfgc_table_type 1082 * See mlxsw_flood_table_type 1083 * Access: RW 1084 * 1085 * Note: FID offset and FID types are not supported in SwitchX-2. 1086 */ 1087 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1088 1089 /* reg_sfgc_flood_table 1090 * Flooding table index to associate with the specific type on the specific 1091 * switch partition. 1092 * Access: RW 1093 */ 1094 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1095 1096 /* reg_sfgc_counter_set_type 1097 * Counter Set Type for flow counters. 1098 * Access: RW 1099 */ 1100 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1101 1102 /* reg_sfgc_counter_index 1103 * Counter Index for flow counters. 1104 * Access: RW 1105 */ 1106 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1107 1108 /* reg_sfgc_mid_base 1109 * MID Base. 1110 * Access: RW 1111 * 1112 * Note: Reserved when legacy bridge model is used. 1113 */ 1114 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1115 1116 static inline void 1117 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1118 enum mlxsw_reg_bridge_type bridge_type, 1119 enum mlxsw_flood_table_type table_type, 1120 unsigned int flood_table, u16 mid_base) 1121 { 1122 MLXSW_REG_ZERO(sfgc, payload); 1123 mlxsw_reg_sfgc_type_set(payload, type); 1124 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1125 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1126 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1127 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1128 } 1129 1130 /* SFDF - Switch Filtering DB Flush 1131 * -------------------------------- 1132 * The switch filtering DB flush register is used to flush the FDB. 1133 * Note that FDB notifications are flushed as well. 1134 */ 1135 #define MLXSW_REG_SFDF_ID 0x2013 1136 #define MLXSW_REG_SFDF_LEN 0x14 1137 1138 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1139 1140 /* reg_sfdf_swid 1141 * Switch partition ID. 1142 * Access: Index 1143 */ 1144 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1145 1146 enum mlxsw_reg_sfdf_flush_type { 1147 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1148 MLXSW_REG_SFDF_FLUSH_PER_FID, 1149 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1150 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1151 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1152 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1153 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1154 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1155 }; 1156 1157 /* reg_sfdf_flush_type 1158 * Flush type. 1159 * 0 - All SWID dynamic entries are flushed. 1160 * 1 - All FID dynamic entries are flushed. 1161 * 2 - All dynamic entries pointing to port are flushed. 1162 * 3 - All FID dynamic entries pointing to port are flushed. 1163 * 4 - All dynamic entries pointing to LAG are flushed. 1164 * 5 - All FID dynamic entries pointing to LAG are flushed. 1165 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1166 * flushed. 1167 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1168 * flushed, per FID. 1169 * Access: RW 1170 */ 1171 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1172 1173 /* reg_sfdf_flush_static 1174 * Static. 1175 * 0 - Flush only dynamic entries. 1176 * 1 - Flush both dynamic and static entries. 1177 * Access: RW 1178 */ 1179 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1180 1181 static inline void mlxsw_reg_sfdf_pack(char *payload, 1182 enum mlxsw_reg_sfdf_flush_type type) 1183 { 1184 MLXSW_REG_ZERO(sfdf, payload); 1185 mlxsw_reg_sfdf_flush_type_set(payload, type); 1186 mlxsw_reg_sfdf_flush_static_set(payload, true); 1187 } 1188 1189 /* reg_sfdf_fid 1190 * FID to flush. 1191 * Access: RW 1192 */ 1193 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1194 1195 /* reg_sfdf_system_port 1196 * Port to flush. 1197 * Access: RW 1198 */ 1199 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1200 1201 /* reg_sfdf_port_fid_system_port 1202 * Port to flush, pointed to by FID. 1203 * Access: RW 1204 */ 1205 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1206 1207 /* reg_sfdf_lag_id 1208 * LAG ID to flush. 1209 * Access: RW 1210 */ 1211 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1212 1213 /* reg_sfdf_lag_fid_lag_id 1214 * LAG ID to flush, pointed to by FID. 1215 * Access: RW 1216 */ 1217 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1218 1219 /* SLDR - Switch LAG Descriptor Register 1220 * ----------------------------------------- 1221 * The switch LAG descriptor register is populated by LAG descriptors. 1222 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1223 * max_lag-1. 1224 */ 1225 #define MLXSW_REG_SLDR_ID 0x2014 1226 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1227 1228 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1229 1230 enum mlxsw_reg_sldr_op { 1231 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1232 MLXSW_REG_SLDR_OP_LAG_CREATE, 1233 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1234 /* Ports that appear in the list have the Distributor enabled */ 1235 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1236 /* Removes ports from the disributor list */ 1237 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1238 }; 1239 1240 /* reg_sldr_op 1241 * Operation. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1245 1246 /* reg_sldr_lag_id 1247 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1248 * Access: Index 1249 */ 1250 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1251 1252 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1253 { 1254 MLXSW_REG_ZERO(sldr, payload); 1255 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1256 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1257 } 1258 1259 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1260 { 1261 MLXSW_REG_ZERO(sldr, payload); 1262 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1263 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1264 } 1265 1266 /* reg_sldr_num_ports 1267 * The number of member ports of the LAG. 1268 * Reserved for Create / Destroy operations 1269 * For Add / Remove operations - indicates the number of ports in the list. 1270 * Access: RW 1271 */ 1272 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1273 1274 /* reg_sldr_system_port 1275 * System port. 1276 * Access: RW 1277 */ 1278 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1279 1280 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1281 u16 local_port) 1282 { 1283 MLXSW_REG_ZERO(sldr, payload); 1284 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1285 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1286 mlxsw_reg_sldr_num_ports_set(payload, 1); 1287 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1288 } 1289 1290 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1291 u16 local_port) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 mlxsw_reg_sldr_num_ports_set(payload, 1); 1297 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1298 } 1299 1300 /* SLCR - Switch LAG Configuration 2 Register 1301 * ------------------------------------------- 1302 * The Switch LAG Configuration register is used for configuring the 1303 * LAG properties of the switch. 1304 */ 1305 #define MLXSW_REG_SLCR_ID 0x2015 1306 #define MLXSW_REG_SLCR_LEN 0x10 1307 1308 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1309 1310 enum mlxsw_reg_slcr_pp { 1311 /* Global Configuration (for all ports) */ 1312 MLXSW_REG_SLCR_PP_GLOBAL, 1313 /* Per port configuration, based on local_port field */ 1314 MLXSW_REG_SLCR_PP_PER_PORT, 1315 }; 1316 1317 /* reg_slcr_pp 1318 * Per Port Configuration 1319 * Note: Reading at Global mode results in reading port 1 configuration. 1320 * Access: Index 1321 */ 1322 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1323 1324 /* reg_slcr_local_port 1325 * Local port number 1326 * Supported from CPU port 1327 * Not supported from router port 1328 * Reserved when pp = Global Configuration 1329 * Access: Index 1330 */ 1331 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1332 1333 enum mlxsw_reg_slcr_type { 1334 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1335 MLXSW_REG_SLCR_TYPE_XOR, 1336 MLXSW_REG_SLCR_TYPE_RANDOM, 1337 }; 1338 1339 /* reg_slcr_type 1340 * Hash type 1341 * Access: RW 1342 */ 1343 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1344 1345 /* Ingress port */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1347 /* SMAC - for IPv4 and IPv6 packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1349 /* SMAC - for non-IP packets */ 1350 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1351 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1352 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1353 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1354 /* DMAC - for IPv4 and IPv6 packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1356 /* DMAC - for non-IP packets */ 1357 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1358 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1359 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1360 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1361 /* Ethertype - for IPv4 and IPv6 packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1363 /* Ethertype - for non-IP packets */ 1364 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1365 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1366 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1367 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1368 /* VLAN ID - for IPv4 and IPv6 packets */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1370 /* VLAN ID - for non-IP packets */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1372 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1373 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1374 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1375 /* Source IP address (can be IPv4 or IPv6) */ 1376 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1377 /* Destination IP address (can be IPv4 or IPv6) */ 1378 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1379 /* TCP/UDP source port */ 1380 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1381 /* TCP/UDP destination port*/ 1382 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1383 /* IPv4 Protocol/IPv6 Next Header */ 1384 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1385 /* IPv6 Flow label */ 1386 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1387 /* SID - FCoE source ID */ 1388 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1389 /* DID - FCoE destination ID */ 1390 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1391 /* OXID - FCoE originator exchange ID */ 1392 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1393 /* Destination QP number - for RoCE packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1395 1396 /* reg_slcr_lag_hash 1397 * LAG hashing configuration. This is a bitmask, in which each set 1398 * bit includes the corresponding item in the LAG hash calculation. 1399 * The default lag_hash contains SMAC, DMAC, VLANID and 1400 * Ethertype (for all packet types). 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1404 1405 /* reg_slcr_seed 1406 * LAG seed value. The seed is the same for all ports. 1407 * Access: RW 1408 */ 1409 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1410 1411 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1412 { 1413 MLXSW_REG_ZERO(slcr, payload); 1414 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1415 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1416 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1417 mlxsw_reg_slcr_seed_set(payload, seed); 1418 } 1419 1420 /* SLCOR - Switch LAG Collector Register 1421 * ------------------------------------- 1422 * The Switch LAG Collector register controls the Local Port membership 1423 * in a LAG and enablement of the collector. 1424 */ 1425 #define MLXSW_REG_SLCOR_ID 0x2016 1426 #define MLXSW_REG_SLCOR_LEN 0x10 1427 1428 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1429 1430 enum mlxsw_reg_slcor_col { 1431 /* Port is added with collector disabled */ 1432 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1433 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1435 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1436 }; 1437 1438 /* reg_slcor_col 1439 * Collector configuration 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1443 1444 /* reg_slcor_local_port 1445 * Local port number 1446 * Not supported for CPU port 1447 * Access: Index 1448 */ 1449 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1450 1451 /* reg_slcor_lag_id 1452 * LAG Identifier. Index into the LAG descriptor table. 1453 * Access: Index 1454 */ 1455 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1456 1457 /* reg_slcor_port_index 1458 * Port index in the LAG list. Only valid on Add Port to LAG col. 1459 * Valid range is from 0 to cap_max_lag_members-1 1460 * Access: RW 1461 */ 1462 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1463 1464 static inline void mlxsw_reg_slcor_pack(char *payload, 1465 u16 local_port, u16 lag_id, 1466 enum mlxsw_reg_slcor_col col) 1467 { 1468 MLXSW_REG_ZERO(slcor, payload); 1469 mlxsw_reg_slcor_col_set(payload, col); 1470 mlxsw_reg_slcor_local_port_set(payload, local_port); 1471 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1472 } 1473 1474 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1475 u16 local_port, u16 lag_id, 1476 u8 port_index) 1477 { 1478 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1479 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1480 mlxsw_reg_slcor_port_index_set(payload, port_index); 1481 } 1482 1483 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1484 u16 local_port, u16 lag_id) 1485 { 1486 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1487 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1488 } 1489 1490 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1491 u16 local_port, u16 lag_id) 1492 { 1493 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1495 } 1496 1497 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1498 u16 local_port, u16 lag_id) 1499 { 1500 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1501 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1502 } 1503 1504 /* SPMLR - Switch Port MAC Learning Register 1505 * ----------------------------------------- 1506 * Controls the Switch MAC learning policy per port. 1507 */ 1508 #define MLXSW_REG_SPMLR_ID 0x2018 1509 #define MLXSW_REG_SPMLR_LEN 0x8 1510 1511 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1512 1513 /* reg_spmlr_local_port 1514 * Local port number. 1515 * Access: Index 1516 */ 1517 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1518 1519 /* reg_spmlr_sub_port 1520 * Virtual port within the physical port. 1521 * Should be set to 0 when virtual ports are not enabled on the port. 1522 * Access: Index 1523 */ 1524 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1525 1526 enum mlxsw_reg_spmlr_learn_mode { 1527 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1528 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1529 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1530 }; 1531 1532 /* reg_spmlr_learn_mode 1533 * Learning mode on the port. 1534 * 0 - Learning disabled. 1535 * 2 - Learning enabled. 1536 * 3 - Security mode. 1537 * 1538 * In security mode the switch does not learn MACs on the port, but uses the 1539 * SMAC to see if it exists on another ingress port. If so, the packet is 1540 * classified as a bad packet and is discarded unless the software registers 1541 * to receive port security error packets usign HPKT. 1542 */ 1543 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1544 1545 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1546 enum mlxsw_reg_spmlr_learn_mode mode) 1547 { 1548 MLXSW_REG_ZERO(spmlr, payload); 1549 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1550 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1551 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1552 } 1553 1554 /* SVFA - Switch VID to FID Allocation Register 1555 * -------------------------------------------- 1556 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1557 * virtualized ports. 1558 */ 1559 #define MLXSW_REG_SVFA_ID 0x201C 1560 #define MLXSW_REG_SVFA_LEN 0x18 1561 1562 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1563 1564 /* reg_svfa_swid 1565 * Switch partition ID. 1566 * Access: Index 1567 */ 1568 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1569 1570 /* reg_svfa_local_port 1571 * Local port number. 1572 * Access: Index 1573 * 1574 * Note: Reserved for 802.1Q FIDs. 1575 */ 1576 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1577 1578 enum mlxsw_reg_svfa_mt { 1579 MLXSW_REG_SVFA_MT_VID_TO_FID, 1580 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1581 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1582 }; 1583 1584 /* reg_svfa_mapping_table 1585 * Mapping table: 1586 * 0 - VID to FID 1587 * 1 - {Port, VID} to FID 1588 * Access: Index 1589 * 1590 * Note: Reserved for SwitchX-2. 1591 */ 1592 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1593 1594 /* reg_svfa_v 1595 * Valid. 1596 * Valid if set. 1597 * Access: RW 1598 * 1599 * Note: Reserved for SwitchX-2. 1600 */ 1601 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1602 1603 /* reg_svfa_fid 1604 * Filtering ID. 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1608 1609 /* reg_svfa_vid 1610 * VLAN ID. 1611 * Access: Index 1612 */ 1613 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1614 1615 /* reg_svfa_counter_set_type 1616 * Counter set type for flow counters. 1617 * Access: RW 1618 * 1619 * Note: Reserved for SwitchX-2. 1620 */ 1621 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1622 1623 /* reg_svfa_counter_index 1624 * Counter index for flow counters. 1625 * Access: RW 1626 * 1627 * Note: Reserved for SwitchX-2. 1628 */ 1629 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1630 1631 /* reg_svfa_vni 1632 * Virtual Network Identifier. 1633 * Access: Index 1634 * 1635 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1636 */ 1637 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1638 1639 /* reg_svfa_irif_v 1640 * Ingress RIF valid. 1641 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1642 * 1 - Ingress RIF valid. 1643 * Must not be set for a non enabled RIF. 1644 * Access: RW 1645 * 1646 * Note: Reserved when legacy bridge model is used. 1647 */ 1648 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1649 1650 /* reg_svfa_irif 1651 * Ingress RIF (Router Interface). 1652 * Range is 0..cap_max_router_interfaces-1. 1653 * Access: RW 1654 * 1655 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1656 */ 1657 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1658 1659 static inline void __mlxsw_reg_svfa_pack(char *payload, 1660 enum mlxsw_reg_svfa_mt mt, bool valid, 1661 u16 fid, bool irif_v, u16 irif) 1662 { 1663 MLXSW_REG_ZERO(svfa, payload); 1664 mlxsw_reg_svfa_swid_set(payload, 0); 1665 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1666 mlxsw_reg_svfa_v_set(payload, valid); 1667 mlxsw_reg_svfa_fid_set(payload, fid); 1668 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1669 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1670 } 1671 1672 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1673 bool valid, u16 fid, u16 vid, 1674 bool irif_v, u16 irif) 1675 { 1676 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1677 1678 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1679 mlxsw_reg_svfa_local_port_set(payload, local_port); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1684 u16 vid, bool irif_v, u16 irif) 1685 { 1686 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1687 1688 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1689 mlxsw_reg_svfa_vid_set(payload, vid); 1690 } 1691 1692 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1693 u32 vni, bool irif_v, u16 irif) 1694 { 1695 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1696 1697 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1698 mlxsw_reg_svfa_vni_set(payload, vni); 1699 } 1700 1701 /* SPVTR - Switch Port VLAN Stacking Register 1702 * ------------------------------------------ 1703 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1704 * to enable VLAN stacking. 1705 */ 1706 #define MLXSW_REG_SPVTR_ID 0x201D 1707 #define MLXSW_REG_SPVTR_LEN 0x10 1708 1709 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1710 1711 /* reg_spvtr_tport 1712 * Port is tunnel port. 1713 * Access: Index 1714 * 1715 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1716 */ 1717 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1718 1719 /* reg_spvtr_local_port 1720 * When tport = 0: local port number (Not supported from/to CPU). 1721 * When tport = 1: tunnel port. 1722 * Access: Index 1723 */ 1724 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1725 1726 /* reg_spvtr_ippe 1727 * Ingress Port Prio Mode Update Enable. 1728 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1729 * Reserved on Get operations. 1730 * Access: OP 1731 */ 1732 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1733 1734 /* reg_spvtr_ipve 1735 * Ingress Port VID Mode Update Enable. 1736 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1737 * field. 1738 * Reserved on Get operations. 1739 * Access: OP 1740 */ 1741 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1742 1743 /* reg_spvtr_epve 1744 * Egress Port VID Mode Update Enable. 1745 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1746 * field. 1747 * Access: OP 1748 */ 1749 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1750 1751 /* reg_spvtr_ipprio_mode 1752 * Ingress Port Priority Mode. 1753 * This controls the PCP and DEI of the new outer VLAN 1754 * Note: for SwitchX/-2 the DEI is not affected. 1755 * 0: use port default PCP and DEI (configured by QPDPC). 1756 * 1: use C-VLAN PCP and DEI. 1757 * Has no effect when ipvid_mode = 0. 1758 * Reserved when tport = 1. 1759 * Access: RW 1760 */ 1761 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1762 1763 enum mlxsw_reg_spvtr_ipvid_mode { 1764 /* IEEE Compliant PVID (default) */ 1765 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1766 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1767 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1768 /* Always push VLAN (also for prio tagged packets) */ 1769 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1770 }; 1771 1772 /* reg_spvtr_ipvid_mode 1773 * Ingress Port VLAN-ID Mode. 1774 * For Spectrum family, this affects the values of SPVM.i 1775 * Access: RW 1776 */ 1777 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1778 1779 enum mlxsw_reg_spvtr_epvid_mode { 1780 /* IEEE Compliant VLAN membership */ 1781 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1782 /* Pop VLAN (for VLAN stacking) */ 1783 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1784 }; 1785 1786 /* reg_spvtr_epvid_mode 1787 * Egress Port VLAN-ID Mode. 1788 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1789 * Access: WO 1790 */ 1791 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1792 1793 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1794 u16 local_port, 1795 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1796 { 1797 MLXSW_REG_ZERO(spvtr, payload); 1798 mlxsw_reg_spvtr_tport_set(payload, tport); 1799 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1800 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1801 mlxsw_reg_spvtr_ipve_set(payload, true); 1802 } 1803 1804 /* SVPE - Switch Virtual-Port Enabling Register 1805 * -------------------------------------------- 1806 * Enables port virtualization. 1807 */ 1808 #define MLXSW_REG_SVPE_ID 0x201E 1809 #define MLXSW_REG_SVPE_LEN 0x4 1810 1811 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1812 1813 /* reg_svpe_local_port 1814 * Local port number 1815 * Access: Index 1816 * 1817 * Note: CPU port is not supported (uses VLAN mode only). 1818 */ 1819 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1820 1821 /* reg_svpe_vp_en 1822 * Virtual port enable. 1823 * 0 - Disable, VLAN mode (VID to FID). 1824 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1825 * Access: RW 1826 */ 1827 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1828 1829 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1830 bool enable) 1831 { 1832 MLXSW_REG_ZERO(svpe, payload); 1833 mlxsw_reg_svpe_local_port_set(payload, local_port); 1834 mlxsw_reg_svpe_vp_en_set(payload, enable); 1835 } 1836 1837 /* SFMR - Switch FID Management Register 1838 * ------------------------------------- 1839 * Creates and configures FIDs. 1840 */ 1841 #define MLXSW_REG_SFMR_ID 0x201F 1842 #define MLXSW_REG_SFMR_LEN 0x30 1843 1844 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1845 1846 enum mlxsw_reg_sfmr_op { 1847 MLXSW_REG_SFMR_OP_CREATE_FID, 1848 MLXSW_REG_SFMR_OP_DESTROY_FID, 1849 }; 1850 1851 /* reg_sfmr_op 1852 * Operation. 1853 * 0 - Create or edit FID. 1854 * 1 - Destroy FID. 1855 * Access: WO 1856 */ 1857 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1858 1859 /* reg_sfmr_fid 1860 * Filtering ID. 1861 * Access: Index 1862 */ 1863 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1864 1865 /* reg_sfmr_flood_rsp 1866 * Router sub-port flooding table. 1867 * 0 - Regular flooding table. 1868 * 1 - Router sub-port flooding table. For this FID the flooding is per 1869 * router-sub-port local_port. Must not be set for a FID which is not a 1870 * router-sub-port and must be set prior to enabling the relevant RIF. 1871 * Access: RW 1872 * 1873 * Note: Reserved when legacy bridge model is used. 1874 */ 1875 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1876 1877 /* reg_sfmr_flood_bridge_type 1878 * Flood bridge type (see SFGC.bridge_type). 1879 * 0 - type_0. 1880 * 1 - type_1. 1881 * Access: RW 1882 * 1883 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1884 */ 1885 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1886 1887 /* reg_sfmr_fid_offset 1888 * FID offset. 1889 * Used to point into the flooding table selected by SFGC register if 1890 * the table is of type FID-Offset. Otherwise, this field is reserved. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1894 1895 /* reg_sfmr_vtfp 1896 * Valid Tunnel Flood Pointer. 1897 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1898 * Access: RW 1899 * 1900 * Note: Reserved for 802.1Q FIDs. 1901 */ 1902 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1903 1904 /* reg_sfmr_nve_tunnel_flood_ptr 1905 * Underlay Flooding and BC Pointer. 1906 * Used as a pointer to the first entry of the group based link lists of 1907 * flooding or BC entries (for NVE tunnels). 1908 * Access: RW 1909 */ 1910 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1911 1912 /* reg_sfmr_vv 1913 * VNI Valid. 1914 * If not set, then vni is reserved. 1915 * Access: RW 1916 * 1917 * Note: Reserved for 802.1Q FIDs. 1918 */ 1919 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1920 1921 /* reg_sfmr_vni 1922 * Virtual Network Identifier. 1923 * When legacy bridge model is used, a given VNI can only be assigned to one 1924 * FID. When unified bridge model is used, it configures only the FID->VNI, 1925 * the VNI->FID is done by SVFA. 1926 * Access: RW 1927 */ 1928 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1929 1930 /* reg_sfmr_irif_v 1931 * Ingress RIF valid. 1932 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1933 * 1 - Ingress RIF valid. 1934 * Must not be set for a non valid RIF. 1935 * Access: RW 1936 * 1937 * Note: Reserved when legacy bridge model is used. 1938 */ 1939 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1940 1941 /* reg_sfmr_irif 1942 * Ingress RIF (Router Interface). 1943 * Range is 0..cap_max_router_interfaces-1. 1944 * Access: RW 1945 * 1946 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1947 */ 1948 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1949 1950 /* reg_sfmr_smpe_valid 1951 * SMPE is valid. 1952 * Access: RW 1953 * 1954 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1955 * Spectrum-1. 1956 */ 1957 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1958 1959 /* reg_sfmr_smpe 1960 * Switch multicast port to egress VID. 1961 * Range is 0..cap_max_rmpe-1 1962 * Access: RW 1963 * 1964 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1965 * Spectrum-1. 1966 */ 1967 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1968 1969 static inline void mlxsw_reg_sfmr_pack(char *payload, 1970 enum mlxsw_reg_sfmr_op op, u16 fid, 1971 u16 fid_offset, bool flood_rsp, 1972 enum mlxsw_reg_bridge_type bridge_type, 1973 bool smpe_valid, u16 smpe) 1974 { 1975 MLXSW_REG_ZERO(sfmr, payload); 1976 mlxsw_reg_sfmr_op_set(payload, op); 1977 mlxsw_reg_sfmr_fid_set(payload, fid); 1978 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1979 mlxsw_reg_sfmr_vtfp_set(payload, false); 1980 mlxsw_reg_sfmr_vv_set(payload, false); 1981 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1982 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1983 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 1984 mlxsw_reg_sfmr_smpe_set(payload, smpe); 1985 } 1986 1987 /* SPVMLR - Switch Port VLAN MAC Learning Register 1988 * ----------------------------------------------- 1989 * Controls the switch MAC learning policy per {Port, VID}. 1990 */ 1991 #define MLXSW_REG_SPVMLR_ID 0x2020 1992 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1993 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1994 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1995 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1996 MLXSW_REG_SPVMLR_REC_LEN * \ 1997 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1998 1999 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 2000 2001 /* reg_spvmlr_local_port 2002 * Local ingress port. 2003 * Access: Index 2004 * 2005 * Note: CPU port is not supported. 2006 */ 2007 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 2008 2009 /* reg_spvmlr_num_rec 2010 * Number of records to update. 2011 * Access: OP 2012 */ 2013 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2014 2015 /* reg_spvmlr_rec_learn_enable 2016 * 0 - Disable learning for {Port, VID}. 2017 * 1 - Enable learning for {Port, VID}. 2018 * Access: RW 2019 */ 2020 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2021 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2022 2023 /* reg_spvmlr_rec_vid 2024 * VLAN ID to be added/removed from port or for querying. 2025 * Access: Index 2026 */ 2027 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2028 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2029 2030 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2031 u16 vid_begin, u16 vid_end, 2032 bool learn_enable) 2033 { 2034 int num_rec = vid_end - vid_begin + 1; 2035 int i; 2036 2037 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2038 2039 MLXSW_REG_ZERO(spvmlr, payload); 2040 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2041 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2042 2043 for (i = 0; i < num_rec; i++) { 2044 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2045 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2046 } 2047 } 2048 2049 /* SPVC - Switch Port VLAN Classification Register 2050 * ----------------------------------------------- 2051 * Configures the port to identify packets as untagged / single tagged / 2052 * double packets based on the packet EtherTypes. 2053 * Ethertype IDs are configured by SVER. 2054 */ 2055 #define MLXSW_REG_SPVC_ID 0x2026 2056 #define MLXSW_REG_SPVC_LEN 0x0C 2057 2058 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2059 2060 /* reg_spvc_local_port 2061 * Local port. 2062 * Access: Index 2063 * 2064 * Note: applies both to Rx port and Tx port, so if a packet traverses 2065 * through Rx port i and a Tx port j then port i and port j must have the 2066 * same configuration. 2067 */ 2068 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2069 2070 /* reg_spvc_inner_et2 2071 * Vlan Tag1 EtherType2 enable. 2072 * Packet is initially classified as double VLAN Tag if in addition to 2073 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2074 * equal to ether_type2. 2075 * 0: disable (default) 2076 * 1: enable 2077 * Access: RW 2078 */ 2079 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2080 2081 /* reg_spvc_et2 2082 * Vlan Tag0 EtherType2 enable. 2083 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2084 * equal to ether_type2. 2085 * 0: disable (default) 2086 * 1: enable 2087 * Access: RW 2088 */ 2089 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2090 2091 /* reg_spvc_inner_et1 2092 * Vlan Tag1 EtherType1 enable. 2093 * Packet is initially classified as double VLAN Tag if in addition to 2094 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2095 * equal to ether_type1. 2096 * 0: disable 2097 * 1: enable (default) 2098 * Access: RW 2099 */ 2100 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2101 2102 /* reg_spvc_et1 2103 * Vlan Tag0 EtherType1 enable. 2104 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2105 * equal to ether_type1. 2106 * 0: disable 2107 * 1: enable (default) 2108 * Access: RW 2109 */ 2110 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2111 2112 /* reg_inner_et0 2113 * Vlan Tag1 EtherType0 enable. 2114 * Packet is initially classified as double VLAN Tag if in addition to 2115 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2116 * equal to ether_type0. 2117 * 0: disable 2118 * 1: enable (default) 2119 * Access: RW 2120 */ 2121 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2122 2123 /* reg_et0 2124 * Vlan Tag0 EtherType0 enable. 2125 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2126 * equal to ether_type0. 2127 * 0: disable 2128 * 1: enable (default) 2129 * Access: RW 2130 */ 2131 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2132 2133 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2134 bool et0) 2135 { 2136 MLXSW_REG_ZERO(spvc, payload); 2137 mlxsw_reg_spvc_local_port_set(payload, local_port); 2138 /* Enable inner_et1 and inner_et0 to enable identification of double 2139 * tagged packets. 2140 */ 2141 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2142 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2143 mlxsw_reg_spvc_et1_set(payload, et1); 2144 mlxsw_reg_spvc_et0_set(payload, et0); 2145 } 2146 2147 /* SPEVET - Switch Port Egress VLAN EtherType 2148 * ------------------------------------------ 2149 * The switch port egress VLAN EtherType configures which EtherType to push at 2150 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2151 * is set. 2152 */ 2153 #define MLXSW_REG_SPEVET_ID 0x202A 2154 #define MLXSW_REG_SPEVET_LEN 0x08 2155 2156 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2157 2158 /* reg_spevet_local_port 2159 * Egress Local port number. 2160 * Not supported to CPU port. 2161 * Access: Index 2162 */ 2163 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2164 2165 /* reg_spevet_et_vlan 2166 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2167 * 0: ether_type0 - (default) 2168 * 1: ether_type1 2169 * 2: ether_type2 2170 * Access: RW 2171 */ 2172 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2173 2174 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2175 u8 et_vlan) 2176 { 2177 MLXSW_REG_ZERO(spevet, payload); 2178 mlxsw_reg_spevet_local_port_set(payload, local_port); 2179 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2180 } 2181 2182 /* SMPE - Switch Multicast Port to Egress VID 2183 * ------------------------------------------ 2184 * The switch multicast port to egress VID maps 2185 * {egress_port, SMPE index} -> {VID}. 2186 */ 2187 #define MLXSW_REG_SMPE_ID 0x202B 2188 #define MLXSW_REG_SMPE_LEN 0x0C 2189 2190 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2191 2192 /* reg_smpe_local_port 2193 * Local port number. 2194 * CPU port is not supported. 2195 * Access: Index 2196 */ 2197 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2198 2199 /* reg_smpe_smpe_index 2200 * Switch multicast port to egress VID. 2201 * Range is 0..cap_max_rmpe-1. 2202 * Access: Index 2203 */ 2204 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2205 2206 /* reg_smpe_evid 2207 * Egress VID. 2208 * Access: RW 2209 */ 2210 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2211 2212 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2213 u16 smpe_index, u16 evid) 2214 { 2215 MLXSW_REG_ZERO(smpe, payload); 2216 mlxsw_reg_smpe_local_port_set(payload, local_port); 2217 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2218 mlxsw_reg_smpe_evid_set(payload, evid); 2219 } 2220 2221 /* SMID-V2 - Switch Multicast ID Version 2 Register 2222 * ------------------------------------------------ 2223 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2224 * of the multicast group within the stacking domain, into a list of local 2225 * ports into which the packet is replicated. 2226 */ 2227 #define MLXSW_REG_SMID2_ID 0x2034 2228 #define MLXSW_REG_SMID2_LEN 0x120 2229 2230 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2231 2232 /* reg_smid2_swid 2233 * Switch partition ID. 2234 * Access: Index 2235 */ 2236 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2237 2238 /* reg_smid2_mid 2239 * Multicast identifier - global identifier that represents the multicast group 2240 * across all devices. 2241 * Access: Index 2242 */ 2243 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2244 2245 /* reg_smid2_smpe_valid 2246 * SMPE is valid. 2247 * When not valid, the egress VID will not be modified by the SMPE table. 2248 * Access: RW 2249 * 2250 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2251 */ 2252 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2253 2254 /* reg_smid2_smpe 2255 * Switch multicast port to egress VID. 2256 * Access: RW 2257 * 2258 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2259 */ 2260 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2261 2262 /* reg_smid2_port 2263 * Local port memebership (1 bit per port). 2264 * Access: RW 2265 */ 2266 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2267 2268 /* reg_smid2_port_mask 2269 * Local port mask (1 bit per port). 2270 * Access: WO 2271 */ 2272 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2273 2274 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2275 bool set, bool smpe_valid, u16 smpe) 2276 { 2277 MLXSW_REG_ZERO(smid2, payload); 2278 mlxsw_reg_smid2_swid_set(payload, 0); 2279 mlxsw_reg_smid2_mid_set(payload, mid); 2280 mlxsw_reg_smid2_port_set(payload, port, set); 2281 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2282 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2283 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2284 } 2285 2286 /* CWTP - Congetion WRED ECN TClass Profile 2287 * ---------------------------------------- 2288 * Configures the profiles for queues of egress port and traffic class 2289 */ 2290 #define MLXSW_REG_CWTP_ID 0x2802 2291 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2292 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2293 #define MLXSW_REG_CWTP_LEN 0x40 2294 2295 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2296 2297 /* reg_cwtp_local_port 2298 * Local port number 2299 * Not supported for CPU port 2300 * Access: Index 2301 */ 2302 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2303 2304 /* reg_cwtp_traffic_class 2305 * Traffic Class to configure 2306 * Access: Index 2307 */ 2308 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2309 2310 /* reg_cwtp_profile_min 2311 * Minimum Average Queue Size of the profile in cells. 2312 * Access: RW 2313 */ 2314 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2315 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2316 2317 /* reg_cwtp_profile_percent 2318 * Percentage of WRED and ECN marking for maximum Average Queue size 2319 * Range is 0 to 100, units of integer percentage 2320 * Access: RW 2321 */ 2322 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2323 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2324 2325 /* reg_cwtp_profile_max 2326 * Maximum Average Queue size of the profile in cells 2327 * Access: RW 2328 */ 2329 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2330 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2331 2332 #define MLXSW_REG_CWTP_MIN_VALUE 64 2333 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2334 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2335 2336 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2337 u8 traffic_class) 2338 { 2339 int i; 2340 2341 MLXSW_REG_ZERO(cwtp, payload); 2342 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2343 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2344 2345 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2346 mlxsw_reg_cwtp_profile_min_set(payload, i, 2347 MLXSW_REG_CWTP_MIN_VALUE); 2348 mlxsw_reg_cwtp_profile_max_set(payload, i, 2349 MLXSW_REG_CWTP_MIN_VALUE); 2350 } 2351 } 2352 2353 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2354 2355 static inline void 2356 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2357 u32 probability) 2358 { 2359 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2360 2361 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2362 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2363 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2364 } 2365 2366 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2367 * --------------------------------------------------- 2368 * The CWTPM register maps each egress port and traffic class to profile num. 2369 */ 2370 #define MLXSW_REG_CWTPM_ID 0x2803 2371 #define MLXSW_REG_CWTPM_LEN 0x44 2372 2373 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2374 2375 /* reg_cwtpm_local_port 2376 * Local port number 2377 * Not supported for CPU port 2378 * Access: Index 2379 */ 2380 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2381 2382 /* reg_cwtpm_traffic_class 2383 * Traffic Class to configure 2384 * Access: Index 2385 */ 2386 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2387 2388 /* reg_cwtpm_ew 2389 * Control enablement of WRED for traffic class: 2390 * 0 - Disable 2391 * 1 - Enable 2392 * Access: RW 2393 */ 2394 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2395 2396 /* reg_cwtpm_ee 2397 * Control enablement of ECN for traffic class: 2398 * 0 - Disable 2399 * 1 - Enable 2400 * Access: RW 2401 */ 2402 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2403 2404 /* reg_cwtpm_tcp_g 2405 * TCP Green Profile. 2406 * Index of the profile within {port, traffic class} to use. 2407 * 0 for disabling both WRED and ECN for this type of traffic. 2408 * Access: RW 2409 */ 2410 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2411 2412 /* reg_cwtpm_tcp_y 2413 * TCP Yellow Profile. 2414 * Index of the profile within {port, traffic class} to use. 2415 * 0 for disabling both WRED and ECN for this type of traffic. 2416 * Access: RW 2417 */ 2418 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2419 2420 /* reg_cwtpm_tcp_r 2421 * TCP Red Profile. 2422 * Index of the profile within {port, traffic class} to use. 2423 * 0 for disabling both WRED and ECN for this type of traffic. 2424 * Access: RW 2425 */ 2426 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2427 2428 /* reg_cwtpm_ntcp_g 2429 * Non-TCP Green Profile. 2430 * Index of the profile within {port, traffic class} to use. 2431 * 0 for disabling both WRED and ECN for this type of traffic. 2432 * Access: RW 2433 */ 2434 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2435 2436 /* reg_cwtpm_ntcp_y 2437 * Non-TCP Yellow Profile. 2438 * Index of the profile within {port, traffic class} to use. 2439 * 0 for disabling both WRED and ECN for this type of traffic. 2440 * Access: RW 2441 */ 2442 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2443 2444 /* reg_cwtpm_ntcp_r 2445 * Non-TCP Red Profile. 2446 * Index of the profile within {port, traffic class} to use. 2447 * 0 for disabling both WRED and ECN for this type of traffic. 2448 * Access: RW 2449 */ 2450 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2451 2452 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2453 2454 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2455 u8 traffic_class, u8 profile, 2456 bool wred, bool ecn) 2457 { 2458 MLXSW_REG_ZERO(cwtpm, payload); 2459 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2460 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2461 mlxsw_reg_cwtpm_ew_set(payload, wred); 2462 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2463 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2464 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2465 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2466 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2467 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2468 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2469 } 2470 2471 /* PGCR - Policy-Engine General Configuration Register 2472 * --------------------------------------------------- 2473 * This register configures general Policy-Engine settings. 2474 */ 2475 #define MLXSW_REG_PGCR_ID 0x3001 2476 #define MLXSW_REG_PGCR_LEN 0x20 2477 2478 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2479 2480 /* reg_pgcr_default_action_pointer_base 2481 * Default action pointer base. Each region has a default action pointer 2482 * which is equal to default_action_pointer_base + region_id. 2483 * Access: RW 2484 */ 2485 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2486 2487 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2488 { 2489 MLXSW_REG_ZERO(pgcr, payload); 2490 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2491 } 2492 2493 /* PPBT - Policy-Engine Port Binding Table 2494 * --------------------------------------- 2495 * This register is used for configuration of the Port Binding Table. 2496 */ 2497 #define MLXSW_REG_PPBT_ID 0x3002 2498 #define MLXSW_REG_PPBT_LEN 0x14 2499 2500 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2501 2502 enum mlxsw_reg_pxbt_e { 2503 MLXSW_REG_PXBT_E_IACL, 2504 MLXSW_REG_PXBT_E_EACL, 2505 }; 2506 2507 /* reg_ppbt_e 2508 * Access: Index 2509 */ 2510 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2511 2512 enum mlxsw_reg_pxbt_op { 2513 MLXSW_REG_PXBT_OP_BIND, 2514 MLXSW_REG_PXBT_OP_UNBIND, 2515 }; 2516 2517 /* reg_ppbt_op 2518 * Access: RW 2519 */ 2520 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2521 2522 /* reg_ppbt_local_port 2523 * Local port. Not including CPU port. 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2527 2528 /* reg_ppbt_g 2529 * group - When set, the binding is of an ACL group. When cleared, 2530 * the binding is of an ACL. 2531 * Must be set to 1 for Spectrum. 2532 * Access: RW 2533 */ 2534 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2535 2536 /* reg_ppbt_acl_info 2537 * ACL/ACL group identifier. If the g bit is set, this field should hold 2538 * the acl_group_id, else it should hold the acl_id. 2539 * Access: RW 2540 */ 2541 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2542 2543 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2544 enum mlxsw_reg_pxbt_op op, 2545 u16 local_port, u16 acl_info) 2546 { 2547 MLXSW_REG_ZERO(ppbt, payload); 2548 mlxsw_reg_ppbt_e_set(payload, e); 2549 mlxsw_reg_ppbt_op_set(payload, op); 2550 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2551 mlxsw_reg_ppbt_g_set(payload, true); 2552 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2553 } 2554 2555 /* PACL - Policy-Engine ACL Register 2556 * --------------------------------- 2557 * This register is used for configuration of the ACL. 2558 */ 2559 #define MLXSW_REG_PACL_ID 0x3004 2560 #define MLXSW_REG_PACL_LEN 0x70 2561 2562 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2563 2564 /* reg_pacl_v 2565 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2566 * while the ACL is bounded to either a port, VLAN or ACL rule. 2567 * Access: RW 2568 */ 2569 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2570 2571 /* reg_pacl_acl_id 2572 * An identifier representing the ACL (managed by software) 2573 * Range 0 .. cap_max_acl_regions - 1 2574 * Access: Index 2575 */ 2576 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2577 2578 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2579 2580 /* reg_pacl_tcam_region_info 2581 * Opaque object that represents a TCAM region. 2582 * Obtained through PTAR register. 2583 * Access: RW 2584 */ 2585 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2586 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2587 2588 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2589 bool valid, const char *tcam_region_info) 2590 { 2591 MLXSW_REG_ZERO(pacl, payload); 2592 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2593 mlxsw_reg_pacl_v_set(payload, valid); 2594 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2595 } 2596 2597 /* PAGT - Policy-Engine ACL Group Table 2598 * ------------------------------------ 2599 * This register is used for configuration of the ACL Group Table. 2600 */ 2601 #define MLXSW_REG_PAGT_ID 0x3005 2602 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2603 #define MLXSW_REG_PAGT_ACL_LEN 4 2604 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2605 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2606 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2607 2608 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2609 2610 /* reg_pagt_size 2611 * Number of ACLs in the group. 2612 * Size 0 invalidates a group. 2613 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2614 * Total number of ACLs in all groups must be lower or equal 2615 * to cap_max_acl_tot_groups 2616 * Note: a group which is binded must not be invalidated 2617 * Access: Index 2618 */ 2619 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2620 2621 /* reg_pagt_acl_group_id 2622 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2623 * the ACL Group identifier (managed by software). 2624 * Access: Index 2625 */ 2626 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2627 2628 /* reg_pagt_multi 2629 * Multi-ACL 2630 * 0 - This ACL is the last ACL in the multi-ACL 2631 * 1 - This ACL is part of a multi-ACL 2632 * Access: RW 2633 */ 2634 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2635 2636 /* reg_pagt_acl_id 2637 * ACL identifier 2638 * Access: RW 2639 */ 2640 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2641 2642 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2643 { 2644 MLXSW_REG_ZERO(pagt, payload); 2645 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2646 } 2647 2648 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2649 u16 acl_id, bool multi) 2650 { 2651 u8 size = mlxsw_reg_pagt_size_get(payload); 2652 2653 if (index >= size) 2654 mlxsw_reg_pagt_size_set(payload, index + 1); 2655 mlxsw_reg_pagt_multi_set(payload, index, multi); 2656 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2657 } 2658 2659 /* PTAR - Policy-Engine TCAM Allocation Register 2660 * --------------------------------------------- 2661 * This register is used for allocation of regions in the TCAM. 2662 * Note: Query method is not supported on this register. 2663 */ 2664 #define MLXSW_REG_PTAR_ID 0x3006 2665 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2666 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2667 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2668 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2669 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2670 2671 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2672 2673 enum mlxsw_reg_ptar_op { 2674 /* allocate a TCAM region */ 2675 MLXSW_REG_PTAR_OP_ALLOC, 2676 /* resize a TCAM region */ 2677 MLXSW_REG_PTAR_OP_RESIZE, 2678 /* deallocate TCAM region */ 2679 MLXSW_REG_PTAR_OP_FREE, 2680 /* test allocation */ 2681 MLXSW_REG_PTAR_OP_TEST, 2682 }; 2683 2684 /* reg_ptar_op 2685 * Access: OP 2686 */ 2687 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2688 2689 /* reg_ptar_action_set_type 2690 * Type of action set to be used on this region. 2691 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2692 * Access: WO 2693 */ 2694 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2695 2696 enum mlxsw_reg_ptar_key_type { 2697 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2698 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2699 }; 2700 2701 /* reg_ptar_key_type 2702 * TCAM key type for the region. 2703 * Access: WO 2704 */ 2705 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2706 2707 /* reg_ptar_region_size 2708 * TCAM region size. When allocating/resizing this is the requested size, 2709 * the response is the actual size. Note that actual size may be 2710 * larger than requested. 2711 * Allowed range 1 .. cap_max_rules-1 2712 * Reserved during op deallocate. 2713 * Access: WO 2714 */ 2715 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2716 2717 /* reg_ptar_region_id 2718 * Region identifier 2719 * Range 0 .. cap_max_regions-1 2720 * Access: Index 2721 */ 2722 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2723 2724 /* reg_ptar_tcam_region_info 2725 * Opaque object that represents the TCAM region. 2726 * Returned when allocating a region. 2727 * Provided by software for ACL generation and region deallocation and resize. 2728 * Access: RW 2729 */ 2730 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2731 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2732 2733 /* reg_ptar_flexible_key_id 2734 * Identifier of the Flexible Key. 2735 * Only valid if key_type == "FLEX_KEY" 2736 * The key size will be rounded up to one of the following values: 2737 * 9B, 18B, 36B, 54B. 2738 * This field is reserved for in resize operation. 2739 * Access: WO 2740 */ 2741 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2742 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2743 2744 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2745 enum mlxsw_reg_ptar_key_type key_type, 2746 u16 region_size, u16 region_id, 2747 const char *tcam_region_info) 2748 { 2749 MLXSW_REG_ZERO(ptar, payload); 2750 mlxsw_reg_ptar_op_set(payload, op); 2751 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2752 mlxsw_reg_ptar_key_type_set(payload, key_type); 2753 mlxsw_reg_ptar_region_size_set(payload, region_size); 2754 mlxsw_reg_ptar_region_id_set(payload, region_id); 2755 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2756 } 2757 2758 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2759 u16 key_id) 2760 { 2761 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2762 } 2763 2764 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2765 { 2766 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2767 } 2768 2769 /* PPBS - Policy-Engine Policy Based Switching Register 2770 * ---------------------------------------------------- 2771 * This register retrieves and sets Policy Based Switching Table entries. 2772 */ 2773 #define MLXSW_REG_PPBS_ID 0x300C 2774 #define MLXSW_REG_PPBS_LEN 0x14 2775 2776 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2777 2778 /* reg_ppbs_pbs_ptr 2779 * Index into the PBS table. 2780 * For Spectrum, the index points to the KVD Linear. 2781 * Access: Index 2782 */ 2783 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2784 2785 /* reg_ppbs_system_port 2786 * Unique port identifier for the final destination of the packet. 2787 * Access: RW 2788 */ 2789 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2790 2791 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2792 u16 system_port) 2793 { 2794 MLXSW_REG_ZERO(ppbs, payload); 2795 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2796 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2797 } 2798 2799 /* PRCR - Policy-Engine Rules Copy Register 2800 * ---------------------------------------- 2801 * This register is used for accessing rules within a TCAM region. 2802 */ 2803 #define MLXSW_REG_PRCR_ID 0x300D 2804 #define MLXSW_REG_PRCR_LEN 0x40 2805 2806 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2807 2808 enum mlxsw_reg_prcr_op { 2809 /* Move rules. Moves the rules from "tcam_region_info" starting 2810 * at offset "offset" to "dest_tcam_region_info" 2811 * at offset "dest_offset." 2812 */ 2813 MLXSW_REG_PRCR_OP_MOVE, 2814 /* Copy rules. Copies the rules from "tcam_region_info" starting 2815 * at offset "offset" to "dest_tcam_region_info" 2816 * at offset "dest_offset." 2817 */ 2818 MLXSW_REG_PRCR_OP_COPY, 2819 }; 2820 2821 /* reg_prcr_op 2822 * Access: OP 2823 */ 2824 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2825 2826 /* reg_prcr_offset 2827 * Offset within the source region to copy/move from. 2828 * Access: Index 2829 */ 2830 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2831 2832 /* reg_prcr_size 2833 * The number of rules to copy/move. 2834 * Access: WO 2835 */ 2836 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2837 2838 /* reg_prcr_tcam_region_info 2839 * Opaque object that represents the source TCAM region. 2840 * Access: Index 2841 */ 2842 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2843 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2844 2845 /* reg_prcr_dest_offset 2846 * Offset within the source region to copy/move to. 2847 * Access: Index 2848 */ 2849 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2850 2851 /* reg_prcr_dest_tcam_region_info 2852 * Opaque object that represents the destination TCAM region. 2853 * Access: Index 2854 */ 2855 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2856 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2857 2858 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2859 const char *src_tcam_region_info, 2860 u16 src_offset, 2861 const char *dest_tcam_region_info, 2862 u16 dest_offset, u16 size) 2863 { 2864 MLXSW_REG_ZERO(prcr, payload); 2865 mlxsw_reg_prcr_op_set(payload, op); 2866 mlxsw_reg_prcr_offset_set(payload, src_offset); 2867 mlxsw_reg_prcr_size_set(payload, size); 2868 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2869 src_tcam_region_info); 2870 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2871 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2872 dest_tcam_region_info); 2873 } 2874 2875 /* PEFA - Policy-Engine Extended Flexible Action Register 2876 * ------------------------------------------------------ 2877 * This register is used for accessing an extended flexible action entry 2878 * in the central KVD Linear Database. 2879 */ 2880 #define MLXSW_REG_PEFA_ID 0x300F 2881 #define MLXSW_REG_PEFA_LEN 0xB0 2882 2883 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2884 2885 /* reg_pefa_index 2886 * Index in the KVD Linear Centralized Database. 2887 * Access: Index 2888 */ 2889 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2890 2891 /* reg_pefa_a 2892 * Index in the KVD Linear Centralized Database. 2893 * Activity 2894 * For a new entry: set if ca=0, clear if ca=1 2895 * Set if a packet lookup has hit on the specific entry 2896 * Access: RO 2897 */ 2898 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2899 2900 /* reg_pefa_ca 2901 * Clear activity 2902 * When write: activity is according to this field 2903 * When read: after reading the activity is cleared according to ca 2904 * Access: OP 2905 */ 2906 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2907 2908 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2909 2910 /* reg_pefa_flex_action_set 2911 * Action-set to perform when rule is matched. 2912 * Must be zero padded if action set is shorter. 2913 * Access: RW 2914 */ 2915 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2916 2917 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2918 const char *flex_action_set) 2919 { 2920 MLXSW_REG_ZERO(pefa, payload); 2921 mlxsw_reg_pefa_index_set(payload, index); 2922 mlxsw_reg_pefa_ca_set(payload, ca); 2923 if (flex_action_set) 2924 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2925 flex_action_set); 2926 } 2927 2928 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2929 { 2930 *p_a = mlxsw_reg_pefa_a_get(payload); 2931 } 2932 2933 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2934 * -------------------------------------------------------------- 2935 * This register is used for binding Multicast router to an ACL group 2936 * that serves the MC router. 2937 * This register is not supported by SwitchX/-2 and Spectrum. 2938 */ 2939 #define MLXSW_REG_PEMRBT_ID 0x3014 2940 #define MLXSW_REG_PEMRBT_LEN 0x14 2941 2942 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2943 2944 enum mlxsw_reg_pemrbt_protocol { 2945 MLXSW_REG_PEMRBT_PROTO_IPV4, 2946 MLXSW_REG_PEMRBT_PROTO_IPV6, 2947 }; 2948 2949 /* reg_pemrbt_protocol 2950 * Access: Index 2951 */ 2952 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2953 2954 /* reg_pemrbt_group_id 2955 * ACL group identifier. 2956 * Range 0..cap_max_acl_groups-1 2957 * Access: RW 2958 */ 2959 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2960 2961 static inline void 2962 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2963 u16 group_id) 2964 { 2965 MLXSW_REG_ZERO(pemrbt, payload); 2966 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2967 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2968 } 2969 2970 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2971 * ----------------------------------------------------- 2972 * This register is used for accessing rules within a TCAM region. 2973 * It is a new version of PTCE in order to support wider key, 2974 * mask and action within a TCAM region. This register is not supported 2975 * by SwitchX and SwitchX-2. 2976 */ 2977 #define MLXSW_REG_PTCE2_ID 0x3017 2978 #define MLXSW_REG_PTCE2_LEN 0x1D8 2979 2980 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2981 2982 /* reg_ptce2_v 2983 * Valid. 2984 * Access: RW 2985 */ 2986 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2987 2988 /* reg_ptce2_a 2989 * Activity. Set if a packet lookup has hit on the specific entry. 2990 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2991 * Access: RO 2992 */ 2993 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2994 2995 enum mlxsw_reg_ptce2_op { 2996 /* Read operation. */ 2997 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2998 /* clear on read operation. Used to read entry 2999 * and clear Activity bit. 3000 */ 3001 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3002 /* Write operation. Used to write a new entry to the table. 3003 * All R/W fields are relevant for new entry. Activity bit is set 3004 * for new entries - Note write with v = 0 will delete the entry. 3005 */ 3006 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3007 /* Update action. Only action set will be updated. */ 3008 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3009 /* Clear activity. A bit is cleared for the entry. */ 3010 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3011 }; 3012 3013 /* reg_ptce2_op 3014 * Access: OP 3015 */ 3016 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3017 3018 /* reg_ptce2_offset 3019 * Access: Index 3020 */ 3021 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3022 3023 /* reg_ptce2_priority 3024 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3025 * Note: priority does not have to be unique per rule. 3026 * Within a region, higher priority should have lower offset (no limitation 3027 * between regions in a multi-region). 3028 * Access: RW 3029 */ 3030 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3031 3032 /* reg_ptce2_tcam_region_info 3033 * Opaque object that represents the TCAM region. 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3037 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3038 3039 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3040 3041 /* reg_ptce2_flex_key_blocks 3042 * ACL Key. 3043 * Access: RW 3044 */ 3045 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3046 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3047 3048 /* reg_ptce2_mask 3049 * mask- in the same size as key. A bit that is set directs the TCAM 3050 * to compare the corresponding bit in key. A bit that is clear directs 3051 * the TCAM to ignore the corresponding bit in key. 3052 * Access: RW 3053 */ 3054 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3055 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3056 3057 /* reg_ptce2_flex_action_set 3058 * ACL action set. 3059 * Access: RW 3060 */ 3061 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3062 MLXSW_REG_FLEX_ACTION_SET_LEN); 3063 3064 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3065 enum mlxsw_reg_ptce2_op op, 3066 const char *tcam_region_info, 3067 u16 offset, u32 priority) 3068 { 3069 MLXSW_REG_ZERO(ptce2, payload); 3070 mlxsw_reg_ptce2_v_set(payload, valid); 3071 mlxsw_reg_ptce2_op_set(payload, op); 3072 mlxsw_reg_ptce2_offset_set(payload, offset); 3073 mlxsw_reg_ptce2_priority_set(payload, priority); 3074 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3075 } 3076 3077 /* PERPT - Policy-Engine ERP Table Register 3078 * ---------------------------------------- 3079 * This register adds and removes eRPs from the eRP table. 3080 */ 3081 #define MLXSW_REG_PERPT_ID 0x3021 3082 #define MLXSW_REG_PERPT_LEN 0x80 3083 3084 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3085 3086 /* reg_perpt_erpt_bank 3087 * eRP table bank. 3088 * Range 0 .. cap_max_erp_table_banks - 1 3089 * Access: Index 3090 */ 3091 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3092 3093 /* reg_perpt_erpt_index 3094 * Index to eRP table within the eRP bank. 3095 * Range is 0 .. cap_max_erp_table_bank_size - 1 3096 * Access: Index 3097 */ 3098 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3099 3100 enum mlxsw_reg_perpt_key_size { 3101 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3102 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3103 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3104 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3105 }; 3106 3107 /* reg_perpt_key_size 3108 * Access: OP 3109 */ 3110 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3111 3112 /* reg_perpt_bf_bypass 3113 * 0 - The eRP is used only if bloom filter state is set for the given 3114 * rule. 3115 * 1 - The eRP is used regardless of bloom filter state. 3116 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3117 * Access: RW 3118 */ 3119 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3120 3121 /* reg_perpt_erp_id 3122 * eRP ID for use by the rules. 3123 * Access: RW 3124 */ 3125 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3126 3127 /* reg_perpt_erpt_base_bank 3128 * Base eRP table bank, points to head of erp_vector 3129 * Range is 0 .. cap_max_erp_table_banks - 1 3130 * Access: OP 3131 */ 3132 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3133 3134 /* reg_perpt_erpt_base_index 3135 * Base index to eRP table within the eRP bank 3136 * Range is 0 .. cap_max_erp_table_bank_size - 1 3137 * Access: OP 3138 */ 3139 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3140 3141 /* reg_perpt_erp_index_in_vector 3142 * eRP index in the vector. 3143 * Access: OP 3144 */ 3145 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3146 3147 /* reg_perpt_erp_vector 3148 * eRP vector. 3149 * Access: OP 3150 */ 3151 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3152 3153 /* reg_perpt_mask 3154 * Mask 3155 * 0 - A-TCAM will ignore the bit in key 3156 * 1 - A-TCAM will compare the bit in key 3157 * Access: RW 3158 */ 3159 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3160 3161 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3162 unsigned long *erp_vector, 3163 unsigned long size) 3164 { 3165 unsigned long bit; 3166 3167 for_each_set_bit(bit, erp_vector, size) 3168 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3169 } 3170 3171 static inline void 3172 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3173 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3174 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3175 char *mask) 3176 { 3177 MLXSW_REG_ZERO(perpt, payload); 3178 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3179 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3180 mlxsw_reg_perpt_key_size_set(payload, key_size); 3181 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3182 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3183 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3184 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3185 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3186 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3187 } 3188 3189 /* PERAR - Policy-Engine Region Association Register 3190 * ------------------------------------------------- 3191 * This register associates a hw region for region_id's. Changing on the fly 3192 * is supported by the device. 3193 */ 3194 #define MLXSW_REG_PERAR_ID 0x3026 3195 #define MLXSW_REG_PERAR_LEN 0x08 3196 3197 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3198 3199 /* reg_perar_region_id 3200 * Region identifier 3201 * Range 0 .. cap_max_regions-1 3202 * Access: Index 3203 */ 3204 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3205 3206 static inline unsigned int 3207 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3208 { 3209 return DIV_ROUND_UP(block_num, 4); 3210 } 3211 3212 /* reg_perar_hw_region 3213 * HW Region 3214 * Range 0 .. cap_max_regions-1 3215 * Default: hw_region = region_id 3216 * For a 8 key block region, 2 consecutive regions are used 3217 * For a 12 key block region, 3 consecutive regions are used 3218 * Access: RW 3219 */ 3220 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3221 3222 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3223 u16 hw_region) 3224 { 3225 MLXSW_REG_ZERO(perar, payload); 3226 mlxsw_reg_perar_region_id_set(payload, region_id); 3227 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3228 } 3229 3230 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3231 * ----------------------------------------------------- 3232 * This register is a new version of PTCE-V2 in order to support the 3233 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3234 */ 3235 #define MLXSW_REG_PTCE3_ID 0x3027 3236 #define MLXSW_REG_PTCE3_LEN 0xF0 3237 3238 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3239 3240 /* reg_ptce3_v 3241 * Valid. 3242 * Access: RW 3243 */ 3244 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3245 3246 enum mlxsw_reg_ptce3_op { 3247 /* Write operation. Used to write a new entry to the table. 3248 * All R/W fields are relevant for new entry. Activity bit is set 3249 * for new entries. Write with v = 0 will delete the entry. Must 3250 * not be used if an entry exists. 3251 */ 3252 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3253 /* Update operation */ 3254 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3255 /* Read operation */ 3256 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3257 }; 3258 3259 /* reg_ptce3_op 3260 * Access: OP 3261 */ 3262 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3263 3264 /* reg_ptce3_priority 3265 * Priority of the rule. Higher values win. 3266 * For Spectrum-2 range is 1..cap_kvd_size - 1 3267 * Note: Priority does not have to be unique per rule. 3268 * Access: RW 3269 */ 3270 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3271 3272 /* reg_ptce3_tcam_region_info 3273 * Opaque object that represents the TCAM region. 3274 * Access: Index 3275 */ 3276 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3277 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3278 3279 /* reg_ptce3_flex2_key_blocks 3280 * ACL key. The key must be masked according to eRP (if exists) or 3281 * according to master mask. 3282 * Access: Index 3283 */ 3284 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3285 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3286 3287 /* reg_ptce3_erp_id 3288 * eRP ID. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3292 3293 /* reg_ptce3_delta_start 3294 * Start point of delta_value and delta_mask, in bits. Must not exceed 3295 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3296 * Access: Index 3297 */ 3298 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3299 3300 /* reg_ptce3_delta_mask 3301 * Delta mask. 3302 * 0 - Ignore relevant bit in delta_value 3303 * 1 - Compare relevant bit in delta_value 3304 * Delta mask must not be set for reserved fields in the key blocks. 3305 * Note: No delta when no eRPs. Thus, for regions with 3306 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3307 * Access: Index 3308 */ 3309 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3310 3311 /* reg_ptce3_delta_value 3312 * Delta value. 3313 * Bits which are masked by delta_mask must be 0. 3314 * Access: Index 3315 */ 3316 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3317 3318 /* reg_ptce3_prune_vector 3319 * Pruning vector relative to the PERPT.erp_id. 3320 * Used for reducing lookups. 3321 * 0 - NEED: Do a lookup using the eRP. 3322 * 1 - PRUNE: Do not perform a lookup using the eRP. 3323 * Maybe be modified by PEAPBL and PEAPBM. 3324 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3325 * all 1's or all 0's. 3326 * Access: RW 3327 */ 3328 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3329 3330 /* reg_ptce3_prune_ctcam 3331 * Pruning on C-TCAM. Used for reducing lookups. 3332 * 0 - NEED: Do a lookup in the C-TCAM. 3333 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3334 * Access: RW 3335 */ 3336 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3337 3338 /* reg_ptce3_large_exists 3339 * Large entry key ID exists. 3340 * Within the region: 3341 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3342 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3343 * For rule delete: The MSB of the key will be removed. 3344 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3345 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3346 * For rule delete: The MSB of the key will not be removed. 3347 * Access: WO 3348 */ 3349 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3350 3351 /* reg_ptce3_large_entry_key_id 3352 * Large entry key ID. 3353 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3354 * blocks. Must be different for different keys which have the same common 3355 * 6 key blocks (MSB, blocks 6..11) key within a region. 3356 * Range is 0..cap_max_pe_large_key_id - 1 3357 * Access: RW 3358 */ 3359 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3360 3361 /* reg_ptce3_action_pointer 3362 * Pointer to action. 3363 * Range is 0..cap_max_kvd_action_sets - 1 3364 * Access: RW 3365 */ 3366 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3367 3368 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3369 enum mlxsw_reg_ptce3_op op, 3370 u32 priority, 3371 const char *tcam_region_info, 3372 const char *key, u8 erp_id, 3373 u16 delta_start, u8 delta_mask, 3374 u8 delta_value, bool large_exists, 3375 u32 lkey_id, u32 action_pointer) 3376 { 3377 MLXSW_REG_ZERO(ptce3, payload); 3378 mlxsw_reg_ptce3_v_set(payload, valid); 3379 mlxsw_reg_ptce3_op_set(payload, op); 3380 mlxsw_reg_ptce3_priority_set(payload, priority); 3381 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3382 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3383 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3384 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3385 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3386 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3387 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3388 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3389 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3390 } 3391 3392 /* PERCR - Policy-Engine Region Configuration Register 3393 * --------------------------------------------------- 3394 * This register configures the region parameters. The region_id must be 3395 * allocated. 3396 */ 3397 #define MLXSW_REG_PERCR_ID 0x302A 3398 #define MLXSW_REG_PERCR_LEN 0x80 3399 3400 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3401 3402 /* reg_percr_region_id 3403 * Region identifier. 3404 * Range 0..cap_max_regions-1 3405 * Access: Index 3406 */ 3407 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3408 3409 /* reg_percr_atcam_ignore_prune 3410 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3411 * Access: RW 3412 */ 3413 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3414 3415 /* reg_percr_ctcam_ignore_prune 3416 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3417 * Access: RW 3418 */ 3419 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3420 3421 /* reg_percr_bf_bypass 3422 * Bloom filter bypass. 3423 * 0 - Bloom filter is used (default) 3424 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3425 * region_id or eRP. See PERPT.bf_bypass 3426 * Access: RW 3427 */ 3428 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3429 3430 /* reg_percr_master_mask 3431 * Master mask. Logical OR mask of all masks of all rules of a region 3432 * (both A-TCAM and C-TCAM). When there are no eRPs 3433 * (erpt_pointer_valid = 0), then this provides the mask. 3434 * Access: RW 3435 */ 3436 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3437 3438 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3439 { 3440 MLXSW_REG_ZERO(percr, payload); 3441 mlxsw_reg_percr_region_id_set(payload, region_id); 3442 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3443 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3444 mlxsw_reg_percr_bf_bypass_set(payload, false); 3445 } 3446 3447 /* PERERP - Policy-Engine Region eRP Register 3448 * ------------------------------------------ 3449 * This register configures the region eRP. The region_id must be 3450 * allocated. 3451 */ 3452 #define MLXSW_REG_PERERP_ID 0x302B 3453 #define MLXSW_REG_PERERP_LEN 0x1C 3454 3455 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3456 3457 /* reg_pererp_region_id 3458 * Region identifier. 3459 * Range 0..cap_max_regions-1 3460 * Access: Index 3461 */ 3462 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3463 3464 /* reg_pererp_ctcam_le 3465 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3469 3470 /* reg_pererp_erpt_pointer_valid 3471 * erpt_pointer is valid. 3472 * Access: RW 3473 */ 3474 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3475 3476 /* reg_pererp_erpt_bank_pointer 3477 * Pointer to eRP table bank. May be modified at any time. 3478 * Range 0..cap_max_erp_table_banks-1 3479 * Reserved when erpt_pointer_valid = 0 3480 */ 3481 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3482 3483 /* reg_pererp_erpt_pointer 3484 * Pointer to eRP table within the eRP bank. Can be changed for an 3485 * existing region. 3486 * Range 0..cap_max_erp_table_size-1 3487 * Reserved when erpt_pointer_valid = 0 3488 * Access: RW 3489 */ 3490 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3491 3492 /* reg_pererp_erpt_vector 3493 * Vector of allowed eRP indexes starting from erpt_pointer within the 3494 * erpt_bank_pointer. Next entries will be in next bank. 3495 * Note that eRP index is used and not eRP ID. 3496 * Reserved when erpt_pointer_valid = 0 3497 * Access: RW 3498 */ 3499 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3500 3501 /* reg_pererp_master_rp_id 3502 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3503 * for the lookup. Can be changed for an existing region. 3504 * Reserved when erpt_pointer_valid = 1 3505 * Access: RW 3506 */ 3507 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3508 3509 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3510 unsigned long *erp_vector, 3511 unsigned long size) 3512 { 3513 unsigned long bit; 3514 3515 for_each_set_bit(bit, erp_vector, size) 3516 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3517 } 3518 3519 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3520 bool ctcam_le, bool erpt_pointer_valid, 3521 u8 erpt_bank_pointer, u8 erpt_pointer, 3522 u8 master_rp_id) 3523 { 3524 MLXSW_REG_ZERO(pererp, payload); 3525 mlxsw_reg_pererp_region_id_set(payload, region_id); 3526 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3527 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3528 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3529 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3530 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3531 } 3532 3533 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3534 * ---------------------------------------------------------------- 3535 * This register configures the Bloom filter entries. 3536 */ 3537 #define MLXSW_REG_PEABFE_ID 0x3022 3538 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3539 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3540 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3541 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3542 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3543 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3544 3545 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3546 3547 /* reg_peabfe_size 3548 * Number of BF entries to be updated. 3549 * Range 1..256 3550 * Access: Op 3551 */ 3552 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3553 3554 /* reg_peabfe_bf_entry_state 3555 * Bloom filter state 3556 * 0 - Clear 3557 * 1 - Set 3558 * Access: RW 3559 */ 3560 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3561 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3562 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3563 3564 /* reg_peabfe_bf_entry_bank 3565 * Bloom filter bank ID 3566 * Range 0..cap_max_erp_table_banks-1 3567 * Access: Index 3568 */ 3569 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3570 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3571 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3572 3573 /* reg_peabfe_bf_entry_index 3574 * Bloom filter entry index 3575 * Range 0..2^cap_max_bf_log-1 3576 * Access: Index 3577 */ 3578 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3579 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3580 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3581 3582 static inline void mlxsw_reg_peabfe_pack(char *payload) 3583 { 3584 MLXSW_REG_ZERO(peabfe, payload); 3585 } 3586 3587 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3588 u8 state, u8 bank, u32 bf_index) 3589 { 3590 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3591 3592 if (rec_index >= num_rec) 3593 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3594 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3595 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3596 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3597 } 3598 3599 /* IEDR - Infrastructure Entry Delete Register 3600 * ---------------------------------------------------- 3601 * This register is used for deleting entries from the entry tables. 3602 * It is legitimate to attempt to delete a nonexisting entry (the device will 3603 * respond as a good flow). 3604 */ 3605 #define MLXSW_REG_IEDR_ID 0x3804 3606 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3607 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3608 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3609 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3610 MLXSW_REG_IEDR_REC_LEN * \ 3611 MLXSW_REG_IEDR_REC_MAX_COUNT) 3612 3613 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3614 3615 /* reg_iedr_num_rec 3616 * Number of records. 3617 * Access: OP 3618 */ 3619 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3620 3621 /* reg_iedr_rec_type 3622 * Resource type. 3623 * Access: OP 3624 */ 3625 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3626 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3627 3628 /* reg_iedr_rec_size 3629 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3630 * Access: OP 3631 */ 3632 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3633 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3634 3635 /* reg_iedr_rec_index_start 3636 * Resource index start. 3637 * Access: OP 3638 */ 3639 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3640 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3641 3642 static inline void mlxsw_reg_iedr_pack(char *payload) 3643 { 3644 MLXSW_REG_ZERO(iedr, payload); 3645 } 3646 3647 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3648 u8 rec_type, u16 rec_size, 3649 u32 rec_index_start) 3650 { 3651 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3652 3653 if (rec_index >= num_rec) 3654 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3655 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3656 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3657 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3658 } 3659 3660 /* QPTS - QoS Priority Trust State Register 3661 * ---------------------------------------- 3662 * This register controls the port policy to calculate the switch priority and 3663 * packet color based on incoming packet fields. 3664 */ 3665 #define MLXSW_REG_QPTS_ID 0x4002 3666 #define MLXSW_REG_QPTS_LEN 0x8 3667 3668 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3669 3670 /* reg_qpts_local_port 3671 * Local port number. 3672 * Access: Index 3673 * 3674 * Note: CPU port is supported. 3675 */ 3676 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3677 3678 enum mlxsw_reg_qpts_trust_state { 3679 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3680 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3681 }; 3682 3683 /* reg_qpts_trust_state 3684 * Trust state for a given port. 3685 * Access: RW 3686 */ 3687 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3688 3689 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3690 enum mlxsw_reg_qpts_trust_state ts) 3691 { 3692 MLXSW_REG_ZERO(qpts, payload); 3693 3694 mlxsw_reg_qpts_local_port_set(payload, local_port); 3695 mlxsw_reg_qpts_trust_state_set(payload, ts); 3696 } 3697 3698 /* QPCR - QoS Policer Configuration Register 3699 * ----------------------------------------- 3700 * The QPCR register is used to create policers - that limit 3701 * the rate of bytes or packets via some trap group. 3702 */ 3703 #define MLXSW_REG_QPCR_ID 0x4004 3704 #define MLXSW_REG_QPCR_LEN 0x28 3705 3706 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3707 3708 enum mlxsw_reg_qpcr_g { 3709 MLXSW_REG_QPCR_G_GLOBAL = 2, 3710 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3711 }; 3712 3713 /* reg_qpcr_g 3714 * The policer type. 3715 * Access: Index 3716 */ 3717 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3718 3719 /* reg_qpcr_pid 3720 * Policer ID. 3721 * Access: Index 3722 */ 3723 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3724 3725 /* reg_qpcr_clear_counter 3726 * Clear counters. 3727 * Access: OP 3728 */ 3729 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3730 3731 /* reg_qpcr_color_aware 3732 * Is the policer aware of colors. 3733 * Must be 0 (unaware) for cpu port. 3734 * Access: RW for unbounded policer. RO for bounded policer. 3735 */ 3736 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3737 3738 /* reg_qpcr_bytes 3739 * Is policer limit is for bytes per sec or packets per sec. 3740 * 0 - packets 3741 * 1 - bytes 3742 * Access: RW for unbounded policer. RO for bounded policer. 3743 */ 3744 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3745 3746 enum mlxsw_reg_qpcr_ir_units { 3747 MLXSW_REG_QPCR_IR_UNITS_M, 3748 MLXSW_REG_QPCR_IR_UNITS_K, 3749 }; 3750 3751 /* reg_qpcr_ir_units 3752 * Policer's units for cir and eir fields (for bytes limits only) 3753 * 1 - 10^3 3754 * 0 - 10^6 3755 * Access: OP 3756 */ 3757 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3758 3759 enum mlxsw_reg_qpcr_rate_type { 3760 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3761 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3762 }; 3763 3764 /* reg_qpcr_rate_type 3765 * Policer can have one limit (single rate) or 2 limits with specific operation 3766 * for packets that exceed the lower rate but not the upper one. 3767 * (For cpu port must be single rate) 3768 * Access: RW for unbounded policer. RO for bounded policer. 3769 */ 3770 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3771 3772 /* reg_qpc_cbs 3773 * Policer's committed burst size. 3774 * The policer is working with time slices of 50 nano sec. By default every 3775 * slice is granted the proportionate share of the committed rate. If we want to 3776 * allow a slice to exceed that share (while still keeping the rate per sec) we 3777 * can allow burst. The burst size is between the default proportionate share 3778 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3779 * committed rate will result in exceeding the rate). The burst size must be a 3780 * log of 2 and will be determined by 2^cbs. 3781 * Access: RW 3782 */ 3783 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3784 3785 /* reg_qpcr_cir 3786 * Policer's committed rate. 3787 * The rate used for sungle rate, the lower rate for double rate. 3788 * For bytes limits, the rate will be this value * the unit from ir_units. 3789 * (Resolution error is up to 1%). 3790 * Access: RW 3791 */ 3792 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3793 3794 /* reg_qpcr_eir 3795 * Policer's exceed rate. 3796 * The higher rate for double rate, reserved for single rate. 3797 * Lower rate for double rate policer. 3798 * For bytes limits, the rate will be this value * the unit from ir_units. 3799 * (Resolution error is up to 1%). 3800 * Access: RW 3801 */ 3802 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3803 3804 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3805 3806 /* reg_qpcr_exceed_action. 3807 * What to do with packets between the 2 limits for double rate. 3808 * Access: RW for unbounded policer. RO for bounded policer. 3809 */ 3810 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3811 3812 enum mlxsw_reg_qpcr_action { 3813 /* Discard */ 3814 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3815 /* Forward and set color to red. 3816 * If the packet is intended to cpu port, it will be dropped. 3817 */ 3818 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3819 }; 3820 3821 /* reg_qpcr_violate_action 3822 * What to do with packets that cross the cir limit (for single rate) or the eir 3823 * limit (for double rate). 3824 * Access: RW for unbounded policer. RO for bounded policer. 3825 */ 3826 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3827 3828 /* reg_qpcr_violate_count 3829 * Counts the number of times violate_action happened on this PID. 3830 * Access: RW 3831 */ 3832 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3833 3834 /* Packets */ 3835 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3836 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3837 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3838 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3839 3840 /* Bandwidth */ 3841 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3842 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3843 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3844 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3845 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3846 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3847 3848 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3849 enum mlxsw_reg_qpcr_ir_units ir_units, 3850 bool bytes, u32 cir, u16 cbs) 3851 { 3852 MLXSW_REG_ZERO(qpcr, payload); 3853 mlxsw_reg_qpcr_pid_set(payload, pid); 3854 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3855 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3856 mlxsw_reg_qpcr_violate_action_set(payload, 3857 MLXSW_REG_QPCR_ACTION_DISCARD); 3858 mlxsw_reg_qpcr_cir_set(payload, cir); 3859 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3860 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3861 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3862 } 3863 3864 /* QTCT - QoS Switch Traffic Class Table 3865 * ------------------------------------- 3866 * Configures the mapping between the packet switch priority and the 3867 * traffic class on the transmit port. 3868 */ 3869 #define MLXSW_REG_QTCT_ID 0x400A 3870 #define MLXSW_REG_QTCT_LEN 0x08 3871 3872 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3873 3874 /* reg_qtct_local_port 3875 * Local port number. 3876 * Access: Index 3877 * 3878 * Note: CPU port is not supported. 3879 */ 3880 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3881 3882 /* reg_qtct_sub_port 3883 * Virtual port within the physical port. 3884 * Should be set to 0 when virtual ports are not enabled on the port. 3885 * Access: Index 3886 */ 3887 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3888 3889 /* reg_qtct_switch_prio 3890 * Switch priority. 3891 * Access: Index 3892 */ 3893 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3894 3895 /* reg_qtct_tclass 3896 * Traffic class. 3897 * Default values: 3898 * switch_prio 0 : tclass 1 3899 * switch_prio 1 : tclass 0 3900 * switch_prio i : tclass i, for i > 1 3901 * Access: RW 3902 */ 3903 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3904 3905 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3906 u8 switch_prio, u8 tclass) 3907 { 3908 MLXSW_REG_ZERO(qtct, payload); 3909 mlxsw_reg_qtct_local_port_set(payload, local_port); 3910 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3911 mlxsw_reg_qtct_tclass_set(payload, tclass); 3912 } 3913 3914 /* QEEC - QoS ETS Element Configuration Register 3915 * --------------------------------------------- 3916 * Configures the ETS elements. 3917 */ 3918 #define MLXSW_REG_QEEC_ID 0x400D 3919 #define MLXSW_REG_QEEC_LEN 0x20 3920 3921 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3922 3923 /* reg_qeec_local_port 3924 * Local port number. 3925 * Access: Index 3926 * 3927 * Note: CPU port is supported. 3928 */ 3929 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 3930 3931 enum mlxsw_reg_qeec_hr { 3932 MLXSW_REG_QEEC_HR_PORT, 3933 MLXSW_REG_QEEC_HR_GROUP, 3934 MLXSW_REG_QEEC_HR_SUBGROUP, 3935 MLXSW_REG_QEEC_HR_TC, 3936 }; 3937 3938 /* reg_qeec_element_hierarchy 3939 * 0 - Port 3940 * 1 - Group 3941 * 2 - Subgroup 3942 * 3 - Traffic Class 3943 * Access: Index 3944 */ 3945 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3946 3947 /* reg_qeec_element_index 3948 * The index of the element in the hierarchy. 3949 * Access: Index 3950 */ 3951 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3952 3953 /* reg_qeec_next_element_index 3954 * The index of the next (lower) element in the hierarchy. 3955 * Access: RW 3956 * 3957 * Note: Reserved for element_hierarchy 0. 3958 */ 3959 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3960 3961 /* reg_qeec_mise 3962 * Min shaper configuration enable. Enables configuration of the min 3963 * shaper on this ETS element 3964 * 0 - Disable 3965 * 1 - Enable 3966 * Access: RW 3967 */ 3968 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3969 3970 /* reg_qeec_ptps 3971 * PTP shaper 3972 * 0: regular shaper mode 3973 * 1: PTP oriented shaper 3974 * Allowed only for hierarchy 0 3975 * Not supported for CPU port 3976 * Note that ptps mode may affect the shaper rates of all hierarchies 3977 * Supported only on Spectrum-1 3978 * Access: RW 3979 */ 3980 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3981 3982 enum { 3983 MLXSW_REG_QEEC_BYTES_MODE, 3984 MLXSW_REG_QEEC_PACKETS_MODE, 3985 }; 3986 3987 /* reg_qeec_pb 3988 * Packets or bytes mode. 3989 * 0 - Bytes mode 3990 * 1 - Packets mode 3991 * Access: RW 3992 * 3993 * Note: Used for max shaper configuration. For Spectrum, packets mode 3994 * is supported only for traffic classes of CPU port. 3995 */ 3996 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3997 3998 /* The smallest permitted min shaper rate. */ 3999 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4000 4001 /* reg_qeec_min_shaper_rate 4002 * Min shaper information rate. 4003 * For CPU port, can only be configured for port hierarchy. 4004 * When in bytes mode, value is specified in units of 1000bps. 4005 * Access: RW 4006 */ 4007 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4008 4009 /* reg_qeec_mase 4010 * Max shaper configuration enable. Enables configuration of the max 4011 * shaper on this ETS element. 4012 * 0 - Disable 4013 * 1 - Enable 4014 * Access: RW 4015 */ 4016 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4017 4018 /* The largest max shaper value possible to disable the shaper. */ 4019 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4020 4021 /* reg_qeec_max_shaper_rate 4022 * Max shaper information rate. 4023 * For CPU port, can only be configured for port hierarchy. 4024 * When in bytes mode, value is specified in units of 1000bps. 4025 * Access: RW 4026 */ 4027 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4028 4029 /* reg_qeec_de 4030 * DWRR configuration enable. Enables configuration of the dwrr and 4031 * dwrr_weight. 4032 * 0 - Disable 4033 * 1 - Enable 4034 * Access: RW 4035 */ 4036 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4037 4038 /* reg_qeec_dwrr 4039 * Transmission selection algorithm to use on the link going down from 4040 * the ETS element. 4041 * 0 - Strict priority 4042 * 1 - DWRR 4043 * Access: RW 4044 */ 4045 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4046 4047 /* reg_qeec_dwrr_weight 4048 * DWRR weight on the link going down from the ETS element. The 4049 * percentage of bandwidth guaranteed to an ETS element within 4050 * its hierarchy. The sum of all weights across all ETS elements 4051 * within one hierarchy should be equal to 100. Reserved when 4052 * transmission selection algorithm is strict priority. 4053 * Access: RW 4054 */ 4055 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4056 4057 /* reg_qeec_max_shaper_bs 4058 * Max shaper burst size 4059 * Burst size is 2^max_shaper_bs * 512 bits 4060 * For Spectrum-1: Range is: 5..25 4061 * For Spectrum-2: Range is: 11..25 4062 * Reserved when ptps = 1 4063 * Access: RW 4064 */ 4065 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4066 4067 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4068 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4069 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4070 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4071 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4072 4073 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4074 enum mlxsw_reg_qeec_hr hr, u8 index, 4075 u8 next_index) 4076 { 4077 MLXSW_REG_ZERO(qeec, payload); 4078 mlxsw_reg_qeec_local_port_set(payload, local_port); 4079 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4080 mlxsw_reg_qeec_element_index_set(payload, index); 4081 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4082 } 4083 4084 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4085 bool ptps) 4086 { 4087 MLXSW_REG_ZERO(qeec, payload); 4088 mlxsw_reg_qeec_local_port_set(payload, local_port); 4089 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4090 mlxsw_reg_qeec_ptps_set(payload, ptps); 4091 } 4092 4093 /* QRWE - QoS ReWrite Enable 4094 * ------------------------- 4095 * This register configures the rewrite enable per receive port. 4096 */ 4097 #define MLXSW_REG_QRWE_ID 0x400F 4098 #define MLXSW_REG_QRWE_LEN 0x08 4099 4100 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4101 4102 /* reg_qrwe_local_port 4103 * Local port number. 4104 * Access: Index 4105 * 4106 * Note: CPU port is supported. No support for router port. 4107 */ 4108 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4109 4110 /* reg_qrwe_dscp 4111 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4112 * Access: RW 4113 */ 4114 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4115 4116 /* reg_qrwe_pcp 4117 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4118 * Access: RW 4119 */ 4120 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4121 4122 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4123 bool rewrite_pcp, bool rewrite_dscp) 4124 { 4125 MLXSW_REG_ZERO(qrwe, payload); 4126 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4127 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4128 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4129 } 4130 4131 /* QPDSM - QoS Priority to DSCP Mapping 4132 * ------------------------------------ 4133 * QoS Priority to DSCP Mapping Register 4134 */ 4135 #define MLXSW_REG_QPDSM_ID 0x4011 4136 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4137 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4138 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4139 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4140 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4141 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4142 4143 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4144 4145 /* reg_qpdsm_local_port 4146 * Local Port. Supported for data packets from CPU port. 4147 * Access: Index 4148 */ 4149 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4150 4151 /* reg_qpdsm_prio_entry_color0_e 4152 * Enable update of the entry for color 0 and a given port. 4153 * Access: WO 4154 */ 4155 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4156 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4157 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4158 4159 /* reg_qpdsm_prio_entry_color0_dscp 4160 * DSCP field in the outer label of the packet for color 0 and a given port. 4161 * Reserved when e=0. 4162 * Access: RW 4163 */ 4164 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4165 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4166 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4167 4168 /* reg_qpdsm_prio_entry_color1_e 4169 * Enable update of the entry for color 1 and a given port. 4170 * Access: WO 4171 */ 4172 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4173 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4174 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4175 4176 /* reg_qpdsm_prio_entry_color1_dscp 4177 * DSCP field in the outer label of the packet for color 1 and a given port. 4178 * Reserved when e=0. 4179 * Access: RW 4180 */ 4181 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4182 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4183 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4184 4185 /* reg_qpdsm_prio_entry_color2_e 4186 * Enable update of the entry for color 2 and a given port. 4187 * Access: WO 4188 */ 4189 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4190 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4191 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4192 4193 /* reg_qpdsm_prio_entry_color2_dscp 4194 * DSCP field in the outer label of the packet for color 2 and a given port. 4195 * Reserved when e=0. 4196 * Access: RW 4197 */ 4198 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4199 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4200 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4201 4202 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4203 { 4204 MLXSW_REG_ZERO(qpdsm, payload); 4205 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4206 } 4207 4208 static inline void 4209 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4210 { 4211 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4212 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4213 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4214 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4215 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4216 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4217 } 4218 4219 /* QPDP - QoS Port DSCP to Priority Mapping Register 4220 * ------------------------------------------------- 4221 * This register controls the port default Switch Priority and Color. The 4222 * default Switch Priority and Color are used for frames where the trust state 4223 * uses default values. All member ports of a LAG should be configured with the 4224 * same default values. 4225 */ 4226 #define MLXSW_REG_QPDP_ID 0x4007 4227 #define MLXSW_REG_QPDP_LEN 0x8 4228 4229 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4230 4231 /* reg_qpdp_local_port 4232 * Local Port. Supported for data packets from CPU port. 4233 * Access: Index 4234 */ 4235 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4236 4237 /* reg_qpdp_switch_prio 4238 * Default port Switch Priority (default 0) 4239 * Access: RW 4240 */ 4241 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4242 4243 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4244 u8 switch_prio) 4245 { 4246 MLXSW_REG_ZERO(qpdp, payload); 4247 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4248 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4249 } 4250 4251 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4252 * -------------------------------------------------- 4253 * This register controls the mapping from DSCP field to 4254 * Switch Priority for IP packets. 4255 */ 4256 #define MLXSW_REG_QPDPM_ID 0x4013 4257 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4258 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4259 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4260 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4261 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4262 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4263 4264 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4265 4266 /* reg_qpdpm_local_port 4267 * Local Port. Supported for data packets from CPU port. 4268 * Access: Index 4269 */ 4270 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4271 4272 /* reg_qpdpm_dscp_e 4273 * Enable update of the specific entry. When cleared, the switch_prio and color 4274 * fields are ignored and the previous switch_prio and color values are 4275 * preserved. 4276 * Access: WO 4277 */ 4278 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4279 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4280 4281 /* reg_qpdpm_dscp_prio 4282 * The new Switch Priority value for the relevant DSCP value. 4283 * Access: RW 4284 */ 4285 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4286 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4287 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4288 4289 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4290 { 4291 MLXSW_REG_ZERO(qpdpm, payload); 4292 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4293 } 4294 4295 static inline void 4296 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4297 { 4298 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4299 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4300 } 4301 4302 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4303 * ------------------------------------------------------------------ 4304 * This register configures if the Switch Priority to Traffic Class mapping is 4305 * based on Multicast packet indication. If so, then multicast packets will get 4306 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4307 * QTCT. 4308 * By default, Switch Priority to Traffic Class mapping is not based on 4309 * Multicast packet indication. 4310 */ 4311 #define MLXSW_REG_QTCTM_ID 0x401A 4312 #define MLXSW_REG_QTCTM_LEN 0x08 4313 4314 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4315 4316 /* reg_qtctm_local_port 4317 * Local port number. 4318 * No support for CPU port. 4319 * Access: Index 4320 */ 4321 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4322 4323 /* reg_qtctm_mc 4324 * Multicast Mode 4325 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4326 * indication (default is 0, not based on Multicast packet indication). 4327 */ 4328 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4329 4330 static inline void 4331 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4332 { 4333 MLXSW_REG_ZERO(qtctm, payload); 4334 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4335 mlxsw_reg_qtctm_mc_set(payload, mc); 4336 } 4337 4338 /* QPSC - QoS PTP Shaper Configuration Register 4339 * -------------------------------------------- 4340 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4341 * Supported only on Spectrum-1. 4342 */ 4343 #define MLXSW_REG_QPSC_ID 0x401B 4344 #define MLXSW_REG_QPSC_LEN 0x28 4345 4346 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4347 4348 enum mlxsw_reg_qpsc_port_speed { 4349 MLXSW_REG_QPSC_PORT_SPEED_100M, 4350 MLXSW_REG_QPSC_PORT_SPEED_1G, 4351 MLXSW_REG_QPSC_PORT_SPEED_10G, 4352 MLXSW_REG_QPSC_PORT_SPEED_25G, 4353 }; 4354 4355 /* reg_qpsc_port_speed 4356 * Port speed. 4357 * Access: Index 4358 */ 4359 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4360 4361 /* reg_qpsc_shaper_time_exp 4362 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4363 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4364 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4365 * Access: RW 4366 */ 4367 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4368 4369 /* reg_qpsc_shaper_time_mantissa 4370 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4371 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4372 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4373 * Access: RW 4374 */ 4375 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4376 4377 /* reg_qpsc_shaper_inc 4378 * Number of tokens added to shaper on each update. 4379 * Units of 8B. 4380 * Access: RW 4381 */ 4382 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4383 4384 /* reg_qpsc_shaper_bs 4385 * Max shaper Burst size. 4386 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4387 * Range is: 5..25 (from 2KB..2GB) 4388 * Access: RW 4389 */ 4390 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4391 4392 /* reg_qpsc_ptsc_we 4393 * Write enable to port_to_shaper_credits. 4394 * Access: WO 4395 */ 4396 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4397 4398 /* reg_qpsc_port_to_shaper_credits 4399 * For split ports: range 1..57 4400 * For non-split ports: range 1..112 4401 * Written only when ptsc_we is set. 4402 * Access: RW 4403 */ 4404 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4405 4406 /* reg_qpsc_ing_timestamp_inc 4407 * Ingress timestamp increment. 4408 * 2's complement. 4409 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4410 * value for all ports. 4411 * Same units as used by MTPPTR. 4412 * Access: RW 4413 */ 4414 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4415 4416 /* reg_qpsc_egr_timestamp_inc 4417 * Egress timestamp increment. 4418 * 2's complement. 4419 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4420 * value for all ports. 4421 * Same units as used by MTPPTR. 4422 * Access: RW 4423 */ 4424 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4425 4426 static inline void 4427 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4428 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4429 u8 shaper_bs, u8 port_to_shaper_credits, 4430 int ing_timestamp_inc, int egr_timestamp_inc) 4431 { 4432 MLXSW_REG_ZERO(qpsc, payload); 4433 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4434 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4435 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4436 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4437 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4438 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4439 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4440 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4441 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4442 } 4443 4444 /* PMLP - Ports Module to Local Port Register 4445 * ------------------------------------------ 4446 * Configures the assignment of modules to local ports. 4447 */ 4448 #define MLXSW_REG_PMLP_ID 0x5002 4449 #define MLXSW_REG_PMLP_LEN 0x40 4450 4451 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4452 4453 /* reg_pmlp_rxtx 4454 * 0 - Tx value is used for both Tx and Rx. 4455 * 1 - Rx value is taken from a separte field. 4456 * Access: RW 4457 */ 4458 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4459 4460 /* reg_pmlp_local_port 4461 * Local port number. 4462 * Access: Index 4463 */ 4464 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4465 4466 /* reg_pmlp_width 4467 * 0 - Unmap local port. 4468 * 1 - Lane 0 is used. 4469 * 2 - Lanes 0 and 1 are used. 4470 * 4 - Lanes 0, 1, 2 and 3 are used. 4471 * 8 - Lanes 0-7 are used. 4472 * Access: RW 4473 */ 4474 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4475 4476 /* reg_pmlp_module 4477 * Module number. 4478 * Access: RW 4479 */ 4480 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4481 4482 /* reg_pmlp_slot_index 4483 * Module number. 4484 * Slot_index 4485 * Slot_index = 0 represent the onboard (motherboard). 4486 * In case of non-modular system only slot_index = 0 is available. 4487 * Access: RW 4488 */ 4489 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4490 4491 /* reg_pmlp_tx_lane 4492 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4493 * Access: RW 4494 */ 4495 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4496 4497 /* reg_pmlp_rx_lane 4498 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4499 * equal to Tx lane. 4500 * Access: RW 4501 */ 4502 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4503 4504 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4505 { 4506 MLXSW_REG_ZERO(pmlp, payload); 4507 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4508 } 4509 4510 /* PMTU - Port MTU Register 4511 * ------------------------ 4512 * Configures and reports the port MTU. 4513 */ 4514 #define MLXSW_REG_PMTU_ID 0x5003 4515 #define MLXSW_REG_PMTU_LEN 0x10 4516 4517 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4518 4519 /* reg_pmtu_local_port 4520 * Local port number. 4521 * Access: Index 4522 */ 4523 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4524 4525 /* reg_pmtu_max_mtu 4526 * Maximum MTU. 4527 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4528 * reported, otherwise the minimum between the max_mtu of the different 4529 * types is reported. 4530 * Access: RO 4531 */ 4532 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4533 4534 /* reg_pmtu_admin_mtu 4535 * MTU value to set port to. Must be smaller or equal to max_mtu. 4536 * Note: If port type is Infiniband, then port must be disabled, when its 4537 * MTU is set. 4538 * Access: RW 4539 */ 4540 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4541 4542 /* reg_pmtu_oper_mtu 4543 * The actual MTU configured on the port. Packets exceeding this size 4544 * will be dropped. 4545 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4546 * oper_mtu might be smaller than admin_mtu. 4547 * Access: RO 4548 */ 4549 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4550 4551 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4552 u16 new_mtu) 4553 { 4554 MLXSW_REG_ZERO(pmtu, payload); 4555 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4556 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4557 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4558 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4559 } 4560 4561 /* PTYS - Port Type and Speed Register 4562 * ----------------------------------- 4563 * Configures and reports the port speed type. 4564 * 4565 * Note: When set while the link is up, the changes will not take effect 4566 * until the port transitions from down to up state. 4567 */ 4568 #define MLXSW_REG_PTYS_ID 0x5004 4569 #define MLXSW_REG_PTYS_LEN 0x40 4570 4571 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4572 4573 /* an_disable_admin 4574 * Auto negotiation disable administrative configuration 4575 * 0 - Device doesn't support AN disable. 4576 * 1 - Device supports AN disable. 4577 * Access: RW 4578 */ 4579 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4580 4581 /* reg_ptys_local_port 4582 * Local port number. 4583 * Access: Index 4584 */ 4585 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4586 4587 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4588 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4589 4590 /* reg_ptys_proto_mask 4591 * Protocol mask. Indicates which protocol is used. 4592 * 0 - Infiniband. 4593 * 1 - Fibre Channel. 4594 * 2 - Ethernet. 4595 * Access: Index 4596 */ 4597 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4598 4599 enum { 4600 MLXSW_REG_PTYS_AN_STATUS_NA, 4601 MLXSW_REG_PTYS_AN_STATUS_OK, 4602 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4603 }; 4604 4605 /* reg_ptys_an_status 4606 * Autonegotiation status. 4607 * Access: RO 4608 */ 4609 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4610 4611 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4612 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4613 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4614 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4615 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4616 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4617 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4618 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4619 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4620 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4621 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4622 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4623 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19) 4624 4625 /* reg_ptys_ext_eth_proto_cap 4626 * Extended Ethernet port supported speeds and protocols. 4627 * Access: RO 4628 */ 4629 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4630 4631 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4632 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4633 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4634 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4635 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4636 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4637 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4638 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4639 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4640 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4641 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4642 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4643 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4644 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4645 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4646 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4647 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4648 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4649 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4650 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4651 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4652 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4653 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4654 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4655 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4656 4657 /* reg_ptys_eth_proto_cap 4658 * Ethernet port supported speeds and protocols. 4659 * Access: RO 4660 */ 4661 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4662 4663 /* reg_ptys_ext_eth_proto_admin 4664 * Extended speed and protocol to set port to. 4665 * Access: RW 4666 */ 4667 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4668 4669 /* reg_ptys_eth_proto_admin 4670 * Speed and protocol to set port to. 4671 * Access: RW 4672 */ 4673 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4674 4675 /* reg_ptys_ext_eth_proto_oper 4676 * The extended current speed and protocol configured for the port. 4677 * Access: RO 4678 */ 4679 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4680 4681 /* reg_ptys_eth_proto_oper 4682 * The current speed and protocol configured for the port. 4683 * Access: RO 4684 */ 4685 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4686 4687 enum mlxsw_reg_ptys_connector_type { 4688 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4689 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4690 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4691 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4692 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4693 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4694 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4695 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4696 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4697 }; 4698 4699 /* reg_ptys_connector_type 4700 * Connector type indication. 4701 * Access: RO 4702 */ 4703 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4704 4705 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4706 u32 proto_admin, bool autoneg) 4707 { 4708 MLXSW_REG_ZERO(ptys, payload); 4709 mlxsw_reg_ptys_local_port_set(payload, local_port); 4710 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4711 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4712 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4713 } 4714 4715 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4716 u32 proto_admin, bool autoneg) 4717 { 4718 MLXSW_REG_ZERO(ptys, payload); 4719 mlxsw_reg_ptys_local_port_set(payload, local_port); 4720 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4721 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4722 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4723 } 4724 4725 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4726 u32 *p_eth_proto_cap, 4727 u32 *p_eth_proto_admin, 4728 u32 *p_eth_proto_oper) 4729 { 4730 if (p_eth_proto_cap) 4731 *p_eth_proto_cap = 4732 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4733 if (p_eth_proto_admin) 4734 *p_eth_proto_admin = 4735 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4736 if (p_eth_proto_oper) 4737 *p_eth_proto_oper = 4738 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4739 } 4740 4741 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4742 u32 *p_eth_proto_cap, 4743 u32 *p_eth_proto_admin, 4744 u32 *p_eth_proto_oper) 4745 { 4746 if (p_eth_proto_cap) 4747 *p_eth_proto_cap = 4748 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4749 if (p_eth_proto_admin) 4750 *p_eth_proto_admin = 4751 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4752 if (p_eth_proto_oper) 4753 *p_eth_proto_oper = 4754 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4755 } 4756 4757 /* PPAD - Port Physical Address Register 4758 * ------------------------------------- 4759 * The PPAD register configures the per port physical MAC address. 4760 */ 4761 #define MLXSW_REG_PPAD_ID 0x5005 4762 #define MLXSW_REG_PPAD_LEN 0x10 4763 4764 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4765 4766 /* reg_ppad_single_base_mac 4767 * 0: base_mac, local port should be 0 and mac[7:0] is 4768 * reserved. HW will set incremental 4769 * 1: single_mac - mac of the local_port 4770 * Access: RW 4771 */ 4772 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4773 4774 /* reg_ppad_local_port 4775 * port number, if single_base_mac = 0 then local_port is reserved 4776 * Access: RW 4777 */ 4778 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4779 4780 /* reg_ppad_mac 4781 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4782 * If single_base_mac = 1 - the per port MAC address 4783 * Access: RW 4784 */ 4785 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4786 4787 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4788 u16 local_port) 4789 { 4790 MLXSW_REG_ZERO(ppad, payload); 4791 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4792 mlxsw_reg_ppad_local_port_set(payload, local_port); 4793 } 4794 4795 /* PAOS - Ports Administrative and Operational Status Register 4796 * ----------------------------------------------------------- 4797 * Configures and retrieves per port administrative and operational status. 4798 */ 4799 #define MLXSW_REG_PAOS_ID 0x5006 4800 #define MLXSW_REG_PAOS_LEN 0x10 4801 4802 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4803 4804 /* reg_paos_swid 4805 * Switch partition ID with which to associate the port. 4806 * Note: while external ports uses unique local port numbers (and thus swid is 4807 * redundant), router ports use the same local port number where swid is the 4808 * only indication for the relevant port. 4809 * Access: Index 4810 */ 4811 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4812 4813 /* reg_paos_local_port 4814 * Local port number. 4815 * Access: Index 4816 */ 4817 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4818 4819 /* reg_paos_admin_status 4820 * Port administrative state (the desired state of the port): 4821 * 1 - Up. 4822 * 2 - Down. 4823 * 3 - Up once. This means that in case of link failure, the port won't go 4824 * into polling mode, but will wait to be re-enabled by software. 4825 * 4 - Disabled by system. Can only be set by hardware. 4826 * Access: RW 4827 */ 4828 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4829 4830 /* reg_paos_oper_status 4831 * Port operational state (the current state): 4832 * 1 - Up. 4833 * 2 - Down. 4834 * 3 - Down by port failure. This means that the device will not let the 4835 * port up again until explicitly specified by software. 4836 * Access: RO 4837 */ 4838 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4839 4840 /* reg_paos_ase 4841 * Admin state update enabled. 4842 * Access: WO 4843 */ 4844 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4845 4846 /* reg_paos_ee 4847 * Event update enable. If this bit is set, event generation will be 4848 * updated based on the e field. 4849 * Access: WO 4850 */ 4851 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4852 4853 /* reg_paos_e 4854 * Event generation on operational state change: 4855 * 0 - Do not generate event. 4856 * 1 - Generate Event. 4857 * 2 - Generate Single Event. 4858 * Access: RW 4859 */ 4860 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4861 4862 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4863 enum mlxsw_port_admin_status status) 4864 { 4865 MLXSW_REG_ZERO(paos, payload); 4866 mlxsw_reg_paos_swid_set(payload, 0); 4867 mlxsw_reg_paos_local_port_set(payload, local_port); 4868 mlxsw_reg_paos_admin_status_set(payload, status); 4869 mlxsw_reg_paos_oper_status_set(payload, 0); 4870 mlxsw_reg_paos_ase_set(payload, 1); 4871 mlxsw_reg_paos_ee_set(payload, 1); 4872 mlxsw_reg_paos_e_set(payload, 1); 4873 } 4874 4875 /* PFCC - Ports Flow Control Configuration Register 4876 * ------------------------------------------------ 4877 * Configures and retrieves the per port flow control configuration. 4878 */ 4879 #define MLXSW_REG_PFCC_ID 0x5007 4880 #define MLXSW_REG_PFCC_LEN 0x20 4881 4882 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4883 4884 /* reg_pfcc_local_port 4885 * Local port number. 4886 * Access: Index 4887 */ 4888 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 4889 4890 /* reg_pfcc_pnat 4891 * Port number access type. Determines the way local_port is interpreted: 4892 * 0 - Local port number. 4893 * 1 - IB / label port number. 4894 * Access: Index 4895 */ 4896 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4897 4898 /* reg_pfcc_shl_cap 4899 * Send to higher layers capabilities: 4900 * 0 - No capability of sending Pause and PFC frames to higher layers. 4901 * 1 - Device has capability of sending Pause and PFC frames to higher 4902 * layers. 4903 * Access: RO 4904 */ 4905 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4906 4907 /* reg_pfcc_shl_opr 4908 * Send to higher layers operation: 4909 * 0 - Pause and PFC frames are handled by the port (default). 4910 * 1 - Pause and PFC frames are handled by the port and also sent to 4911 * higher layers. Only valid if shl_cap = 1. 4912 * Access: RW 4913 */ 4914 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4915 4916 /* reg_pfcc_ppan 4917 * Pause policy auto negotiation. 4918 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4919 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4920 * based on the auto-negotiation resolution. 4921 * Access: RW 4922 * 4923 * Note: The auto-negotiation advertisement is set according to pptx and 4924 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4925 */ 4926 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4927 4928 /* reg_pfcc_prio_mask_tx 4929 * Bit per priority indicating if Tx flow control policy should be 4930 * updated based on bit pfctx. 4931 * Access: WO 4932 */ 4933 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4934 4935 /* reg_pfcc_prio_mask_rx 4936 * Bit per priority indicating if Rx flow control policy should be 4937 * updated based on bit pfcrx. 4938 * Access: WO 4939 */ 4940 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4941 4942 /* reg_pfcc_pptx 4943 * Admin Pause policy on Tx. 4944 * 0 - Never generate Pause frames (default). 4945 * 1 - Generate Pause frames according to Rx buffer threshold. 4946 * Access: RW 4947 */ 4948 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4949 4950 /* reg_pfcc_aptx 4951 * Active (operational) Pause policy on Tx. 4952 * 0 - Never generate Pause frames. 4953 * 1 - Generate Pause frames according to Rx buffer threshold. 4954 * Access: RO 4955 */ 4956 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4957 4958 /* reg_pfcc_pfctx 4959 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4960 * 0 - Never generate priority Pause frames on the specified priority 4961 * (default). 4962 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4963 * the specified priority. 4964 * Access: RW 4965 * 4966 * Note: pfctx and pptx must be mutually exclusive. 4967 */ 4968 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4969 4970 /* reg_pfcc_pprx 4971 * Admin Pause policy on Rx. 4972 * 0 - Ignore received Pause frames (default). 4973 * 1 - Respect received Pause frames. 4974 * Access: RW 4975 */ 4976 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4977 4978 /* reg_pfcc_aprx 4979 * Active (operational) Pause policy on Rx. 4980 * 0 - Ignore received Pause frames. 4981 * 1 - Respect received Pause frames. 4982 * Access: RO 4983 */ 4984 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4985 4986 /* reg_pfcc_pfcrx 4987 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4988 * 0 - Ignore incoming priority Pause frames on the specified priority 4989 * (default). 4990 * 1 - Respect incoming priority Pause frames on the specified priority. 4991 * Access: RW 4992 */ 4993 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4994 4995 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4996 4997 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4998 { 4999 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5000 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5001 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5002 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5003 } 5004 5005 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5006 { 5007 MLXSW_REG_ZERO(pfcc, payload); 5008 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5009 } 5010 5011 /* PPCNT - Ports Performance Counters Register 5012 * ------------------------------------------- 5013 * The PPCNT register retrieves per port performance counters. 5014 */ 5015 #define MLXSW_REG_PPCNT_ID 0x5008 5016 #define MLXSW_REG_PPCNT_LEN 0x100 5017 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5018 5019 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5020 5021 /* reg_ppcnt_swid 5022 * For HCA: must be always 0. 5023 * Switch partition ID to associate port with. 5024 * Switch partitions are numbered from 0 to 7 inclusively. 5025 * Switch partition 254 indicates stacking ports. 5026 * Switch partition 255 indicates all switch partitions. 5027 * Only valid on Set() operation with local_port=255. 5028 * Access: Index 5029 */ 5030 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5031 5032 /* reg_ppcnt_local_port 5033 * Local port number. 5034 * Access: Index 5035 */ 5036 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5037 5038 /* reg_ppcnt_pnat 5039 * Port number access type: 5040 * 0 - Local port number 5041 * 1 - IB port number 5042 * Access: Index 5043 */ 5044 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5045 5046 enum mlxsw_reg_ppcnt_grp { 5047 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5048 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5049 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5050 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5051 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5052 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5053 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5054 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5055 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5056 }; 5057 5058 /* reg_ppcnt_grp 5059 * Performance counter group. 5060 * Group 63 indicates all groups. Only valid on Set() operation with 5061 * clr bit set. 5062 * 0x0: IEEE 802.3 Counters 5063 * 0x1: RFC 2863 Counters 5064 * 0x2: RFC 2819 Counters 5065 * 0x3: RFC 3635 Counters 5066 * 0x5: Ethernet Extended Counters 5067 * 0x6: Ethernet Discard Counters 5068 * 0x8: Link Level Retransmission Counters 5069 * 0x10: Per Priority Counters 5070 * 0x11: Per Traffic Class Counters 5071 * 0x12: Physical Layer Counters 5072 * 0x13: Per Traffic Class Congestion Counters 5073 * Access: Index 5074 */ 5075 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5076 5077 /* reg_ppcnt_clr 5078 * Clear counters. Setting the clr bit will reset the counter value 5079 * for all counters in the counter group. This bit can be set 5080 * for both Set() and Get() operation. 5081 * Access: OP 5082 */ 5083 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5084 5085 /* reg_ppcnt_lp_gl 5086 * Local port global variable. 5087 * 0: local_port 255 = all ports of the device. 5088 * 1: local_port indicates local port number for all ports. 5089 * Access: OP 5090 */ 5091 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5092 5093 /* reg_ppcnt_prio_tc 5094 * Priority for counter set that support per priority, valid values: 0-7. 5095 * Traffic class for counter set that support per traffic class, 5096 * valid values: 0- cap_max_tclass-1 . 5097 * For HCA: cap_max_tclass is always 8. 5098 * Otherwise must be 0. 5099 * Access: Index 5100 */ 5101 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5102 5103 /* Ethernet IEEE 802.3 Counter Group */ 5104 5105 /* reg_ppcnt_a_frames_transmitted_ok 5106 * Access: RO 5107 */ 5108 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5109 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5110 5111 /* reg_ppcnt_a_frames_received_ok 5112 * Access: RO 5113 */ 5114 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5115 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5116 5117 /* reg_ppcnt_a_frame_check_sequence_errors 5118 * Access: RO 5119 */ 5120 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5121 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5122 5123 /* reg_ppcnt_a_alignment_errors 5124 * Access: RO 5125 */ 5126 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5127 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5128 5129 /* reg_ppcnt_a_octets_transmitted_ok 5130 * Access: RO 5131 */ 5132 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5133 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5134 5135 /* reg_ppcnt_a_octets_received_ok 5136 * Access: RO 5137 */ 5138 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5139 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5140 5141 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5142 * Access: RO 5143 */ 5144 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5145 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5146 5147 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5148 * Access: RO 5149 */ 5150 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5151 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5152 5153 /* reg_ppcnt_a_multicast_frames_received_ok 5154 * Access: RO 5155 */ 5156 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5157 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5158 5159 /* reg_ppcnt_a_broadcast_frames_received_ok 5160 * Access: RO 5161 */ 5162 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5163 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5164 5165 /* reg_ppcnt_a_in_range_length_errors 5166 * Access: RO 5167 */ 5168 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5169 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5170 5171 /* reg_ppcnt_a_out_of_range_length_field 5172 * Access: RO 5173 */ 5174 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5175 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5176 5177 /* reg_ppcnt_a_frame_too_long_errors 5178 * Access: RO 5179 */ 5180 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5181 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5182 5183 /* reg_ppcnt_a_symbol_error_during_carrier 5184 * Access: RO 5185 */ 5186 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5187 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5188 5189 /* reg_ppcnt_a_mac_control_frames_transmitted 5190 * Access: RO 5191 */ 5192 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5193 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5194 5195 /* reg_ppcnt_a_mac_control_frames_received 5196 * Access: RO 5197 */ 5198 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5199 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5200 5201 /* reg_ppcnt_a_unsupported_opcodes_received 5202 * Access: RO 5203 */ 5204 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5205 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5206 5207 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5208 * Access: RO 5209 */ 5210 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5211 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5212 5213 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5214 * Access: RO 5215 */ 5216 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5217 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5218 5219 /* Ethernet RFC 2863 Counter Group */ 5220 5221 /* reg_ppcnt_if_in_discards 5222 * Access: RO 5223 */ 5224 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5225 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5226 5227 /* reg_ppcnt_if_out_discards 5228 * Access: RO 5229 */ 5230 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5231 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5232 5233 /* reg_ppcnt_if_out_errors 5234 * Access: RO 5235 */ 5236 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5237 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5238 5239 /* Ethernet RFC 2819 Counter Group */ 5240 5241 /* reg_ppcnt_ether_stats_undersize_pkts 5242 * Access: RO 5243 */ 5244 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5245 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5246 5247 /* reg_ppcnt_ether_stats_oversize_pkts 5248 * Access: RO 5249 */ 5250 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5251 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5252 5253 /* reg_ppcnt_ether_stats_fragments 5254 * Access: RO 5255 */ 5256 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5257 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5258 5259 /* reg_ppcnt_ether_stats_pkts64octets 5260 * Access: RO 5261 */ 5262 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5263 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5264 5265 /* reg_ppcnt_ether_stats_pkts65to127octets 5266 * Access: RO 5267 */ 5268 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5269 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5270 5271 /* reg_ppcnt_ether_stats_pkts128to255octets 5272 * Access: RO 5273 */ 5274 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5275 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5276 5277 /* reg_ppcnt_ether_stats_pkts256to511octets 5278 * Access: RO 5279 */ 5280 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5281 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5282 5283 /* reg_ppcnt_ether_stats_pkts512to1023octets 5284 * Access: RO 5285 */ 5286 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5287 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5288 5289 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5290 * Access: RO 5291 */ 5292 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5293 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5294 5295 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5296 * Access: RO 5297 */ 5298 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5299 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5300 5301 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5302 * Access: RO 5303 */ 5304 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5305 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5306 5307 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5308 * Access: RO 5309 */ 5310 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5311 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5312 5313 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5314 * Access: RO 5315 */ 5316 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5317 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5318 5319 /* Ethernet RFC 3635 Counter Group */ 5320 5321 /* reg_ppcnt_dot3stats_fcs_errors 5322 * Access: RO 5323 */ 5324 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5325 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5326 5327 /* reg_ppcnt_dot3stats_symbol_errors 5328 * Access: RO 5329 */ 5330 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5331 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5332 5333 /* reg_ppcnt_dot3control_in_unknown_opcodes 5334 * Access: RO 5335 */ 5336 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5337 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5338 5339 /* reg_ppcnt_dot3in_pause_frames 5340 * Access: RO 5341 */ 5342 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5343 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5344 5345 /* Ethernet Extended Counter Group Counters */ 5346 5347 /* reg_ppcnt_ecn_marked 5348 * Access: RO 5349 */ 5350 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5351 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5352 5353 /* Ethernet Discard Counter Group Counters */ 5354 5355 /* reg_ppcnt_ingress_general 5356 * Access: RO 5357 */ 5358 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5359 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5360 5361 /* reg_ppcnt_ingress_policy_engine 5362 * Access: RO 5363 */ 5364 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5365 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5366 5367 /* reg_ppcnt_ingress_vlan_membership 5368 * Access: RO 5369 */ 5370 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5371 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5372 5373 /* reg_ppcnt_ingress_tag_frame_type 5374 * Access: RO 5375 */ 5376 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5377 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5378 5379 /* reg_ppcnt_egress_vlan_membership 5380 * Access: RO 5381 */ 5382 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5383 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5384 5385 /* reg_ppcnt_loopback_filter 5386 * Access: RO 5387 */ 5388 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5389 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5390 5391 /* reg_ppcnt_egress_general 5392 * Access: RO 5393 */ 5394 MLXSW_ITEM64(reg, ppcnt, egress_general, 5395 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5396 5397 /* reg_ppcnt_egress_hoq 5398 * Access: RO 5399 */ 5400 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5401 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5402 5403 /* reg_ppcnt_egress_policy_engine 5404 * Access: RO 5405 */ 5406 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5407 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5408 5409 /* reg_ppcnt_ingress_tx_link_down 5410 * Access: RO 5411 */ 5412 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5413 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5414 5415 /* reg_ppcnt_egress_stp_filter 5416 * Access: RO 5417 */ 5418 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5419 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5420 5421 /* reg_ppcnt_egress_sll 5422 * Access: RO 5423 */ 5424 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5425 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5426 5427 /* Ethernet Per Priority Group Counters */ 5428 5429 /* reg_ppcnt_rx_octets 5430 * Access: RO 5431 */ 5432 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5433 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5434 5435 /* reg_ppcnt_rx_frames 5436 * Access: RO 5437 */ 5438 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5439 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5440 5441 /* reg_ppcnt_tx_octets 5442 * Access: RO 5443 */ 5444 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5445 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5446 5447 /* reg_ppcnt_tx_frames 5448 * Access: RO 5449 */ 5450 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5451 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5452 5453 /* reg_ppcnt_rx_pause 5454 * Access: RO 5455 */ 5456 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5457 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5458 5459 /* reg_ppcnt_rx_pause_duration 5460 * Access: RO 5461 */ 5462 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5463 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5464 5465 /* reg_ppcnt_tx_pause 5466 * Access: RO 5467 */ 5468 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5469 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5470 5471 /* reg_ppcnt_tx_pause_duration 5472 * Access: RO 5473 */ 5474 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5475 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5476 5477 /* reg_ppcnt_rx_pause_transition 5478 * Access: RO 5479 */ 5480 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5481 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5482 5483 /* Ethernet Per Traffic Class Counters */ 5484 5485 /* reg_ppcnt_tc_transmit_queue 5486 * Contains the transmit queue depth in cells of traffic class 5487 * selected by prio_tc and the port selected by local_port. 5488 * The field cannot be cleared. 5489 * Access: RO 5490 */ 5491 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5492 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5493 5494 /* reg_ppcnt_tc_no_buffer_discard_uc 5495 * The number of unicast packets dropped due to lack of shared 5496 * buffer resources. 5497 * Access: RO 5498 */ 5499 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5500 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5501 5502 /* Ethernet Per Traffic Class Congestion Group Counters */ 5503 5504 /* reg_ppcnt_wred_discard 5505 * Access: RO 5506 */ 5507 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5508 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5509 5510 /* reg_ppcnt_ecn_marked_tc 5511 * Access: RO 5512 */ 5513 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5514 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5515 5516 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5517 enum mlxsw_reg_ppcnt_grp grp, 5518 u8 prio_tc) 5519 { 5520 MLXSW_REG_ZERO(ppcnt, payload); 5521 mlxsw_reg_ppcnt_swid_set(payload, 0); 5522 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5523 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5524 mlxsw_reg_ppcnt_grp_set(payload, grp); 5525 mlxsw_reg_ppcnt_clr_set(payload, 0); 5526 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5527 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5528 } 5529 5530 /* PPTB - Port Prio To Buffer Register 5531 * ----------------------------------- 5532 * Configures the switch priority to buffer table. 5533 */ 5534 #define MLXSW_REG_PPTB_ID 0x500B 5535 #define MLXSW_REG_PPTB_LEN 0x10 5536 5537 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5538 5539 enum { 5540 MLXSW_REG_PPTB_MM_UM, 5541 MLXSW_REG_PPTB_MM_UNICAST, 5542 MLXSW_REG_PPTB_MM_MULTICAST, 5543 }; 5544 5545 /* reg_pptb_mm 5546 * Mapping mode. 5547 * 0 - Map both unicast and multicast packets to the same buffer. 5548 * 1 - Map only unicast packets. 5549 * 2 - Map only multicast packets. 5550 * Access: Index 5551 * 5552 * Note: SwitchX-2 only supports the first option. 5553 */ 5554 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5555 5556 /* reg_pptb_local_port 5557 * Local port number. 5558 * Access: Index 5559 */ 5560 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5561 5562 /* reg_pptb_um 5563 * Enables the update of the untagged_buf field. 5564 * Access: RW 5565 */ 5566 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5567 5568 /* reg_pptb_pm 5569 * Enables the update of the prio_to_buff field. 5570 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5571 * Access: RW 5572 */ 5573 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5574 5575 /* reg_pptb_prio_to_buff 5576 * Mapping of switch priority <i> to one of the allocated receive port 5577 * buffers. 5578 * Access: RW 5579 */ 5580 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5581 5582 /* reg_pptb_pm_msb 5583 * Enables the update of the prio_to_buff field. 5584 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5585 * Access: RW 5586 */ 5587 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5588 5589 /* reg_pptb_untagged_buff 5590 * Mapping of untagged frames to one of the allocated receive port buffers. 5591 * Access: RW 5592 * 5593 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5594 * Spectrum, as it maps untagged packets based on the default switch priority. 5595 */ 5596 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5597 5598 /* reg_pptb_prio_to_buff_msb 5599 * Mapping of switch priority <i+8> to one of the allocated receive port 5600 * buffers. 5601 * Access: RW 5602 */ 5603 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5604 5605 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5606 5607 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5608 { 5609 MLXSW_REG_ZERO(pptb, payload); 5610 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5611 mlxsw_reg_pptb_local_port_set(payload, local_port); 5612 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5613 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5614 } 5615 5616 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5617 u8 buff) 5618 { 5619 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5620 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5621 } 5622 5623 /* PBMC - Port Buffer Management Control Register 5624 * ---------------------------------------------- 5625 * The PBMC register configures and retrieves the port packet buffer 5626 * allocation for different Prios, and the Pause threshold management. 5627 */ 5628 #define MLXSW_REG_PBMC_ID 0x500C 5629 #define MLXSW_REG_PBMC_LEN 0x6C 5630 5631 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5632 5633 /* reg_pbmc_local_port 5634 * Local port number. 5635 * Access: Index 5636 */ 5637 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5638 5639 /* reg_pbmc_xoff_timer_value 5640 * When device generates a pause frame, it uses this value as the pause 5641 * timer (time for the peer port to pause in quota-512 bit time). 5642 * Access: RW 5643 */ 5644 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5645 5646 /* reg_pbmc_xoff_refresh 5647 * The time before a new pause frame should be sent to refresh the pause RW 5648 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5649 * time). 5650 * Access: RW 5651 */ 5652 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5653 5654 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5655 5656 /* reg_pbmc_buf_lossy 5657 * The field indicates if the buffer is lossy. 5658 * 0 - Lossless 5659 * 1 - Lossy 5660 * Access: RW 5661 */ 5662 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5663 5664 /* reg_pbmc_buf_epsb 5665 * Eligible for Port Shared buffer. 5666 * If epsb is set, packets assigned to buffer are allowed to insert the port 5667 * shared buffer. 5668 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5669 * Access: RW 5670 */ 5671 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5672 5673 /* reg_pbmc_buf_size 5674 * The part of the packet buffer array is allocated for the specific buffer. 5675 * Units are represented in cells. 5676 * Access: RW 5677 */ 5678 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5679 5680 /* reg_pbmc_buf_xoff_threshold 5681 * Once the amount of data in the buffer goes above this value, device 5682 * starts sending PFC frames for all priorities associated with the 5683 * buffer. Units are represented in cells. Reserved in case of lossy 5684 * buffer. 5685 * Access: RW 5686 * 5687 * Note: In Spectrum, reserved for buffer[9]. 5688 */ 5689 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5690 0x08, 0x04, false); 5691 5692 /* reg_pbmc_buf_xon_threshold 5693 * When the amount of data in the buffer goes below this value, device 5694 * stops sending PFC frames for the priorities associated with the 5695 * buffer. Units are represented in cells. Reserved in case of lossy 5696 * buffer. 5697 * Access: RW 5698 * 5699 * Note: In Spectrum, reserved for buffer[9]. 5700 */ 5701 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5702 0x08, 0x04, false); 5703 5704 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5705 u16 xoff_timer_value, u16 xoff_refresh) 5706 { 5707 MLXSW_REG_ZERO(pbmc, payload); 5708 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5709 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5710 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5711 } 5712 5713 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5714 int buf_index, 5715 u16 size) 5716 { 5717 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5718 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5719 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5720 } 5721 5722 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5723 int buf_index, u16 size, 5724 u16 threshold) 5725 { 5726 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5727 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5728 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5729 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5730 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5731 } 5732 5733 /* PSPA - Port Switch Partition Allocation 5734 * --------------------------------------- 5735 * Controls the association of a port with a switch partition and enables 5736 * configuring ports as stacking ports. 5737 */ 5738 #define MLXSW_REG_PSPA_ID 0x500D 5739 #define MLXSW_REG_PSPA_LEN 0x8 5740 5741 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5742 5743 /* reg_pspa_swid 5744 * Switch partition ID. 5745 * Access: RW 5746 */ 5747 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5748 5749 /* reg_pspa_local_port 5750 * Local port number. 5751 * Access: Index 5752 */ 5753 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5754 5755 /* reg_pspa_sub_port 5756 * Virtual port within the local port. Set to 0 when virtual ports are 5757 * disabled on the local port. 5758 * Access: Index 5759 */ 5760 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5761 5762 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5763 { 5764 MLXSW_REG_ZERO(pspa, payload); 5765 mlxsw_reg_pspa_swid_set(payload, swid); 5766 mlxsw_reg_pspa_local_port_set(payload, local_port); 5767 mlxsw_reg_pspa_sub_port_set(payload, 0); 5768 } 5769 5770 /* PMAOS - Ports Module Administrative and Operational Status 5771 * ---------------------------------------------------------- 5772 * This register configures and retrieves the per module status. 5773 */ 5774 #define MLXSW_REG_PMAOS_ID 0x5012 5775 #define MLXSW_REG_PMAOS_LEN 0x10 5776 5777 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5778 5779 /* reg_pmaos_rst 5780 * Module reset toggle. 5781 * Note: Setting reset while module is plugged-in will result in transition to 5782 * "initializing" operational state. 5783 * Access: OP 5784 */ 5785 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5786 5787 /* reg_pmaos_slot_index 5788 * Slot index. 5789 * Access: Index 5790 */ 5791 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5792 5793 /* reg_pmaos_module 5794 * Module number. 5795 * Access: Index 5796 */ 5797 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5798 5799 enum mlxsw_reg_pmaos_admin_status { 5800 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5801 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5802 /* If the module is active and then unplugged, or experienced an error 5803 * event, the operational status should go to "disabled" and can only 5804 * be enabled upon explicit enable command. 5805 */ 5806 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5807 }; 5808 5809 /* reg_pmaos_admin_status 5810 * Module administrative state (the desired state of the module). 5811 * Note: To disable a module, all ports associated with the port must be 5812 * administatively down first. 5813 * Access: RW 5814 */ 5815 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5816 5817 /* reg_pmaos_ase 5818 * Admin state update enable. 5819 * If this bit is set, admin state will be updated based on admin_state field. 5820 * Only relevant on Set() operations. 5821 * Access: WO 5822 */ 5823 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5824 5825 /* reg_pmaos_ee 5826 * Event update enable. 5827 * If this bit is set, event generation will be updated based on the e field. 5828 * Only relevant on Set operations. 5829 * Access: WO 5830 */ 5831 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5832 5833 enum mlxsw_reg_pmaos_e { 5834 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5835 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5836 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5837 }; 5838 5839 /* reg_pmaos_e 5840 * Event Generation on operational state change. 5841 * Access: RW 5842 */ 5843 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5844 5845 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5846 { 5847 MLXSW_REG_ZERO(pmaos, payload); 5848 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 5849 mlxsw_reg_pmaos_module_set(payload, module); 5850 } 5851 5852 /* PPLR - Port Physical Loopback Register 5853 * -------------------------------------- 5854 * This register allows configuration of the port's loopback mode. 5855 */ 5856 #define MLXSW_REG_PPLR_ID 0x5018 5857 #define MLXSW_REG_PPLR_LEN 0x8 5858 5859 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5860 5861 /* reg_pplr_local_port 5862 * Local port number. 5863 * Access: Index 5864 */ 5865 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 5866 5867 /* Phy local loopback. When set the port's egress traffic is looped back 5868 * to the receiver and the port transmitter is disabled. 5869 */ 5870 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5871 5872 /* reg_pplr_lb_en 5873 * Loopback enable. 5874 * Access: RW 5875 */ 5876 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5877 5878 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 5879 bool phy_local) 5880 { 5881 MLXSW_REG_ZERO(pplr, payload); 5882 mlxsw_reg_pplr_local_port_set(payload, local_port); 5883 mlxsw_reg_pplr_lb_en_set(payload, 5884 phy_local ? 5885 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5886 } 5887 5888 /* PMTDB - Port Module To local DataBase Register 5889 * ---------------------------------------------- 5890 * The PMTDB register allows to query the possible module<->local port 5891 * mapping than can be used in PMLP. It does not represent the actual/current 5892 * mapping of the local to module. Actual mapping is only defined by PMLP. 5893 */ 5894 #define MLXSW_REG_PMTDB_ID 0x501A 5895 #define MLXSW_REG_PMTDB_LEN 0x40 5896 5897 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 5898 5899 /* reg_pmtdb_slot_index 5900 * Slot index (0: Main board). 5901 * Access: Index 5902 */ 5903 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 5904 5905 /* reg_pmtdb_module 5906 * Module number. 5907 * Access: Index 5908 */ 5909 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 5910 5911 /* reg_pmtdb_ports_width 5912 * Port's width 5913 * Access: Index 5914 */ 5915 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 5916 5917 /* reg_pmtdb_num_ports 5918 * Number of ports in a single module (split/breakout) 5919 * Access: Index 5920 */ 5921 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 5922 5923 enum mlxsw_reg_pmtdb_status { 5924 MLXSW_REG_PMTDB_STATUS_SUCCESS, 5925 }; 5926 5927 /* reg_pmtdb_status 5928 * Status 5929 * Access: RO 5930 */ 5931 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 5932 5933 /* reg_pmtdb_port_num 5934 * The local_port value which can be assigned to the module. 5935 * In case of more than one port, port<x> represent the /<x> port of 5936 * the module. 5937 * Access: RO 5938 */ 5939 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 5940 5941 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 5942 u8 ports_width, u8 num_ports) 5943 { 5944 MLXSW_REG_ZERO(pmtdb, payload); 5945 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 5946 mlxsw_reg_pmtdb_module_set(payload, module); 5947 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 5948 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 5949 } 5950 5951 /* PMECR - Ports Mapping Event Configuration Register 5952 * -------------------------------------------------- 5953 * The PMECR register is used to enable/disable event triggering 5954 * in case of local port mapping change. 5955 */ 5956 #define MLXSW_REG_PMECR_ID 0x501B 5957 #define MLXSW_REG_PMECR_LEN 0x20 5958 5959 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 5960 5961 /* reg_pmecr_local_port 5962 * Local port number. 5963 * Access: Index 5964 */ 5965 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 5966 5967 /* reg_pmecr_ee 5968 * Event update enable. If this bit is set, event generation will be updated 5969 * based on the e field. Only relevant on Set operations. 5970 * Access: WO 5971 */ 5972 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 5973 5974 /* reg_pmecr_eswi 5975 * Software ignore enable bit. If this bit is set, the value of swi is used. 5976 * If this bit is clear, the value of swi is ignored. 5977 * Only relevant on Set operations. 5978 * Access: WO 5979 */ 5980 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 5981 5982 /* reg_pmecr_swi 5983 * Software ignore. If this bit is set, the device shouldn't generate events 5984 * in case of PMLP SET operation but only upon self local port mapping change 5985 * (if applicable according to e configuration). This is supplementary 5986 * configuration on top of e value. 5987 * Access: RW 5988 */ 5989 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 5990 5991 enum mlxsw_reg_pmecr_e { 5992 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 5993 MLXSW_REG_PMECR_E_GENERATE_EVENT, 5994 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 5995 }; 5996 5997 /* reg_pmecr_e 5998 * Event generation on local port mapping change. 5999 * Access: RW 6000 */ 6001 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6002 6003 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6004 enum mlxsw_reg_pmecr_e e) 6005 { 6006 MLXSW_REG_ZERO(pmecr, payload); 6007 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6008 mlxsw_reg_pmecr_e_set(payload, e); 6009 mlxsw_reg_pmecr_ee_set(payload, true); 6010 mlxsw_reg_pmecr_swi_set(payload, true); 6011 mlxsw_reg_pmecr_eswi_set(payload, true); 6012 } 6013 6014 /* PMPE - Port Module Plug/Unplug Event Register 6015 * --------------------------------------------- 6016 * This register reports any operational status change of a module. 6017 * A change in the module’s state will generate an event only if the change 6018 * happens after arming the event mechanism. Any changes to the module state 6019 * while the event mechanism is not armed will not be reported. Software can 6020 * query the PMPE register for module status. 6021 */ 6022 #define MLXSW_REG_PMPE_ID 0x5024 6023 #define MLXSW_REG_PMPE_LEN 0x10 6024 6025 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6026 6027 /* reg_pmpe_slot_index 6028 * Slot index. 6029 * Access: Index 6030 */ 6031 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6032 6033 /* reg_pmpe_module 6034 * Module number. 6035 * Access: Index 6036 */ 6037 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6038 6039 enum mlxsw_reg_pmpe_module_status { 6040 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6041 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6042 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6043 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6044 }; 6045 6046 /* reg_pmpe_module_status 6047 * Module status. 6048 * Access: RO 6049 */ 6050 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6051 6052 /* reg_pmpe_error_type 6053 * Module error details. 6054 * Access: RO 6055 */ 6056 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6057 6058 /* PDDR - Port Diagnostics Database Register 6059 * ----------------------------------------- 6060 * The PDDR enables to read the Phy debug database 6061 */ 6062 #define MLXSW_REG_PDDR_ID 0x5031 6063 #define MLXSW_REG_PDDR_LEN 0x100 6064 6065 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6066 6067 /* reg_pddr_local_port 6068 * Local port number. 6069 * Access: Index 6070 */ 6071 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6072 6073 enum mlxsw_reg_pddr_page_select { 6074 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6075 }; 6076 6077 /* reg_pddr_page_select 6078 * Page select index. 6079 * Access: Index 6080 */ 6081 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6082 6083 enum mlxsw_reg_pddr_trblsh_group_opcode { 6084 /* Monitor opcodes */ 6085 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6086 }; 6087 6088 /* reg_pddr_group_opcode 6089 * Group selector. 6090 * Access: Index 6091 */ 6092 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6093 6094 /* reg_pddr_status_opcode 6095 * Group selector. 6096 * Access: RO 6097 */ 6098 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6099 6100 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6101 u8 page_select) 6102 { 6103 MLXSW_REG_ZERO(pddr, payload); 6104 mlxsw_reg_pddr_local_port_set(payload, local_port); 6105 mlxsw_reg_pddr_page_select_set(payload, page_select); 6106 } 6107 6108 /* PMMP - Port Module Memory Map Properties Register 6109 * ------------------------------------------------- 6110 * The PMMP register allows to override the module memory map advertisement. 6111 * The register can only be set when the module is disabled by PMAOS register. 6112 */ 6113 #define MLXSW_REG_PMMP_ID 0x5044 6114 #define MLXSW_REG_PMMP_LEN 0x2C 6115 6116 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6117 6118 /* reg_pmmp_module 6119 * Module number. 6120 * Access: Index 6121 */ 6122 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6123 6124 /* reg_pmmp_slot_index 6125 * Slot index. 6126 * Access: Index 6127 */ 6128 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6129 6130 /* reg_pmmp_sticky 6131 * When set, will keep eeprom_override values after plug-out event. 6132 * Access: OP 6133 */ 6134 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6135 6136 /* reg_pmmp_eeprom_override_mask 6137 * Write mask bit (negative polarity). 6138 * 0 - Allow write 6139 * 1 - Ignore write 6140 * On write, indicates which of the bits from eeprom_override field are 6141 * updated. 6142 * Access: WO 6143 */ 6144 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6145 6146 enum { 6147 /* Set module to low power mode */ 6148 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6149 }; 6150 6151 /* reg_pmmp_eeprom_override 6152 * Override / ignore EEPROM advertisement properties bitmask 6153 * Access: RW 6154 */ 6155 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6156 6157 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6158 { 6159 MLXSW_REG_ZERO(pmmp, payload); 6160 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6161 mlxsw_reg_pmmp_module_set(payload, module); 6162 } 6163 6164 /* PLLP - Port Local port to Label Port mapping Register 6165 * ----------------------------------------------------- 6166 * The PLLP register returns the mapping from Local Port into Label Port. 6167 */ 6168 #define MLXSW_REG_PLLP_ID 0x504A 6169 #define MLXSW_REG_PLLP_LEN 0x10 6170 6171 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6172 6173 /* reg_pllp_local_port 6174 * Local port number. 6175 * Access: Index 6176 */ 6177 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6178 6179 /* reg_pllp_label_port 6180 * Front panel label of the port. 6181 * Access: RO 6182 */ 6183 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6184 6185 /* reg_pllp_split_num 6186 * Label split mapping for local_port. 6187 * Access: RO 6188 */ 6189 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6190 6191 /* reg_pllp_slot_index 6192 * Slot index (0: Main board). 6193 * Access: RO 6194 */ 6195 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6196 6197 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6198 { 6199 MLXSW_REG_ZERO(pllp, payload); 6200 mlxsw_reg_pllp_local_port_set(payload, local_port); 6201 } 6202 6203 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6204 u8 *split_num, u8 *slot_index) 6205 { 6206 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6207 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6208 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6209 } 6210 6211 /* PMTM - Port Module Type Mapping Register 6212 * ---------------------------------------- 6213 * The PMTM register allows query or configuration of module types. 6214 * The register can only be set when the module is disabled by PMAOS register 6215 */ 6216 #define MLXSW_REG_PMTM_ID 0x5067 6217 #define MLXSW_REG_PMTM_LEN 0x10 6218 6219 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6220 6221 /* reg_pmtm_slot_index 6222 * Slot index. 6223 * Access: Index 6224 */ 6225 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6226 6227 /* reg_pmtm_module 6228 * Module number. 6229 * Access: Index 6230 */ 6231 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6232 6233 enum mlxsw_reg_pmtm_module_type { 6234 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6235 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6236 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6237 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6238 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6239 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6240 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6241 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6242 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6243 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6244 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6245 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6246 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6247 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6248 }; 6249 6250 /* reg_pmtm_module_type 6251 * Module type. 6252 * Access: RW 6253 */ 6254 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6255 6256 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6257 { 6258 MLXSW_REG_ZERO(pmtm, payload); 6259 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6260 mlxsw_reg_pmtm_module_set(payload, module); 6261 } 6262 6263 /* HTGT - Host Trap Group Table 6264 * ---------------------------- 6265 * Configures the properties for forwarding to CPU. 6266 */ 6267 #define MLXSW_REG_HTGT_ID 0x7002 6268 #define MLXSW_REG_HTGT_LEN 0x20 6269 6270 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6271 6272 /* reg_htgt_swid 6273 * Switch partition ID. 6274 * Access: Index 6275 */ 6276 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6277 6278 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6279 6280 /* reg_htgt_type 6281 * CPU path type. 6282 * Access: RW 6283 */ 6284 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6285 6286 enum mlxsw_reg_htgt_trap_group { 6287 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6288 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6289 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6290 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6291 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6292 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6293 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6294 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6295 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6296 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6297 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6298 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6299 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6300 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6301 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6302 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6303 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6304 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6305 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6306 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6307 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6308 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6309 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6310 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6311 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6312 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6313 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6314 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6315 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6316 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6317 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6318 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6319 6320 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6321 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6322 }; 6323 6324 /* reg_htgt_trap_group 6325 * Trap group number. User defined number specifying which trap groups 6326 * should be forwarded to the CPU. The mapping between trap IDs and trap 6327 * groups is configured using HPKT register. 6328 * Access: Index 6329 */ 6330 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6331 6332 enum { 6333 MLXSW_REG_HTGT_POLICER_DISABLE, 6334 MLXSW_REG_HTGT_POLICER_ENABLE, 6335 }; 6336 6337 /* reg_htgt_pide 6338 * Enable policer ID specified using 'pid' field. 6339 * Access: RW 6340 */ 6341 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6342 6343 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6344 6345 /* reg_htgt_pid 6346 * Policer ID for the trap group. 6347 * Access: RW 6348 */ 6349 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6350 6351 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6352 6353 /* reg_htgt_mirror_action 6354 * Mirror action to use. 6355 * 0 - Trap to CPU. 6356 * 1 - Trap to CPU and mirror to a mirroring agent. 6357 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6358 * Access: RW 6359 * 6360 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6361 */ 6362 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6363 6364 /* reg_htgt_mirroring_agent 6365 * Mirroring agent. 6366 * Access: RW 6367 */ 6368 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6369 6370 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6371 6372 /* reg_htgt_priority 6373 * Trap group priority. 6374 * In case a packet matches multiple classification rules, the packet will 6375 * only be trapped once, based on the trap ID associated with the group (via 6376 * register HPKT) with the highest priority. 6377 * Supported values are 0-7, with 7 represnting the highest priority. 6378 * Access: RW 6379 * 6380 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6381 * by the 'trap_group' field. 6382 */ 6383 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6384 6385 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6386 6387 /* reg_htgt_local_path_cpu_tclass 6388 * CPU ingress traffic class for the trap group. 6389 * Access: RW 6390 */ 6391 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6392 6393 enum mlxsw_reg_htgt_local_path_rdq { 6394 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6395 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6396 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6397 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6398 }; 6399 /* reg_htgt_local_path_rdq 6400 * Receive descriptor queue (RDQ) to use for the trap group. 6401 * Access: RW 6402 */ 6403 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6404 6405 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6406 u8 priority, u8 tc) 6407 { 6408 MLXSW_REG_ZERO(htgt, payload); 6409 6410 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6411 mlxsw_reg_htgt_pide_set(payload, 6412 MLXSW_REG_HTGT_POLICER_DISABLE); 6413 } else { 6414 mlxsw_reg_htgt_pide_set(payload, 6415 MLXSW_REG_HTGT_POLICER_ENABLE); 6416 mlxsw_reg_htgt_pid_set(payload, policer_id); 6417 } 6418 6419 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6420 mlxsw_reg_htgt_trap_group_set(payload, group); 6421 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6422 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6423 mlxsw_reg_htgt_priority_set(payload, priority); 6424 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6425 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6426 } 6427 6428 /* HPKT - Host Packet Trap 6429 * ----------------------- 6430 * Configures trap IDs inside trap groups. 6431 */ 6432 #define MLXSW_REG_HPKT_ID 0x7003 6433 #define MLXSW_REG_HPKT_LEN 0x10 6434 6435 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6436 6437 enum { 6438 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6439 MLXSW_REG_HPKT_ACK_REQUIRED, 6440 }; 6441 6442 /* reg_hpkt_ack 6443 * Require acknowledgements from the host for events. 6444 * If set, then the device will wait for the event it sent to be acknowledged 6445 * by the host. This option is only relevant for event trap IDs. 6446 * Access: RW 6447 * 6448 * Note: Currently not supported by firmware. 6449 */ 6450 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6451 6452 enum mlxsw_reg_hpkt_action { 6453 MLXSW_REG_HPKT_ACTION_FORWARD, 6454 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6455 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6456 MLXSW_REG_HPKT_ACTION_DISCARD, 6457 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6458 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6459 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6460 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6461 }; 6462 6463 /* reg_hpkt_action 6464 * Action to perform on packet when trapped. 6465 * 0 - No action. Forward to CPU based on switching rules. 6466 * 1 - Trap to CPU (CPU receives sole copy). 6467 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6468 * 3 - Discard. 6469 * 4 - Soft discard (allow other traps to act on the packet). 6470 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6471 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6472 * 15 - Restore the firmware's default action. 6473 * Access: RW 6474 * 6475 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6476 * addressed to the CPU. 6477 */ 6478 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6479 6480 /* reg_hpkt_trap_group 6481 * Trap group to associate the trap with. 6482 * Access: RW 6483 */ 6484 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6485 6486 /* reg_hpkt_trap_id 6487 * Trap ID. 6488 * Access: Index 6489 * 6490 * Note: A trap ID can only be associated with a single trap group. The device 6491 * will associate the trap ID with the last trap group configured. 6492 */ 6493 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6494 6495 enum { 6496 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6497 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6498 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6499 }; 6500 6501 /* reg_hpkt_ctrl 6502 * Configure dedicated buffer resources for control packets. 6503 * Ignored by SwitchX-2. 6504 * 0 - Keep factory defaults. 6505 * 1 - Do not use control buffer for this trap ID. 6506 * 2 - Use control buffer for this trap ID. 6507 * Access: RW 6508 */ 6509 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6510 6511 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6512 enum mlxsw_reg_htgt_trap_group trap_group, 6513 bool is_ctrl) 6514 { 6515 MLXSW_REG_ZERO(hpkt, payload); 6516 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6517 mlxsw_reg_hpkt_action_set(payload, action); 6518 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6519 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6520 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6521 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6522 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6523 } 6524 6525 /* RGCR - Router General Configuration Register 6526 * -------------------------------------------- 6527 * The register is used for setting up the router configuration. 6528 */ 6529 #define MLXSW_REG_RGCR_ID 0x8001 6530 #define MLXSW_REG_RGCR_LEN 0x28 6531 6532 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6533 6534 /* reg_rgcr_ipv4_en 6535 * IPv4 router enable. 6536 * Access: RW 6537 */ 6538 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6539 6540 /* reg_rgcr_ipv6_en 6541 * IPv6 router enable. 6542 * Access: RW 6543 */ 6544 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6545 6546 /* reg_rgcr_max_router_interfaces 6547 * Defines the maximum number of active router interfaces for all virtual 6548 * routers. 6549 * Access: RW 6550 */ 6551 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6552 6553 /* reg_rgcr_usp 6554 * Update switch priority and packet color. 6555 * 0 - Preserve the value of Switch Priority and packet color. 6556 * 1 - Recalculate the value of Switch Priority and packet color. 6557 * Access: RW 6558 * 6559 * Note: Not supported by SwitchX and SwitchX-2. 6560 */ 6561 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6562 6563 /* reg_rgcr_pcp_rw 6564 * Indicates how to handle the pcp_rewrite_en value: 6565 * 0 - Preserve the value of pcp_rewrite_en. 6566 * 2 - Disable PCP rewrite. 6567 * 3 - Enable PCP rewrite. 6568 * Access: RW 6569 * 6570 * Note: Not supported by SwitchX and SwitchX-2. 6571 */ 6572 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6573 6574 /* reg_rgcr_activity_dis 6575 * Activity disable: 6576 * 0 - Activity will be set when an entry is hit (default). 6577 * 1 - Activity will not be set when an entry is hit. 6578 * 6579 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6580 * (RALUE). 6581 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6582 * Entry (RAUHT). 6583 * Bits 2:7 are reserved. 6584 * Access: RW 6585 * 6586 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6587 */ 6588 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6589 6590 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6591 bool ipv6_en) 6592 { 6593 MLXSW_REG_ZERO(rgcr, payload); 6594 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6595 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6596 } 6597 6598 /* RITR - Router Interface Table Register 6599 * -------------------------------------- 6600 * The register is used to configure the router interface table. 6601 */ 6602 #define MLXSW_REG_RITR_ID 0x8002 6603 #define MLXSW_REG_RITR_LEN 0x40 6604 6605 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6606 6607 /* reg_ritr_enable 6608 * Enables routing on the router interface. 6609 * Access: RW 6610 */ 6611 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6612 6613 /* reg_ritr_ipv4 6614 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6615 * interface. 6616 * Access: RW 6617 */ 6618 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6619 6620 /* reg_ritr_ipv6 6621 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6622 * interface. 6623 * Access: RW 6624 */ 6625 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6626 6627 /* reg_ritr_ipv4_mc 6628 * IPv4 multicast routing enable. 6629 * Access: RW 6630 */ 6631 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6632 6633 /* reg_ritr_ipv6_mc 6634 * IPv6 multicast routing enable. 6635 * Access: RW 6636 */ 6637 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6638 6639 enum mlxsw_reg_ritr_if_type { 6640 /* VLAN interface. */ 6641 MLXSW_REG_RITR_VLAN_IF, 6642 /* FID interface. */ 6643 MLXSW_REG_RITR_FID_IF, 6644 /* Sub-port interface. */ 6645 MLXSW_REG_RITR_SP_IF, 6646 /* Loopback Interface. */ 6647 MLXSW_REG_RITR_LOOPBACK_IF, 6648 }; 6649 6650 /* reg_ritr_type 6651 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6652 * Access: RW 6653 */ 6654 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6655 6656 enum { 6657 MLXSW_REG_RITR_RIF_CREATE, 6658 MLXSW_REG_RITR_RIF_DEL, 6659 }; 6660 6661 /* reg_ritr_op 6662 * Opcode: 6663 * 0 - Create or edit RIF. 6664 * 1 - Delete RIF. 6665 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6666 * is not supported. An interface must be deleted and re-created in order 6667 * to update properties. 6668 * Access: WO 6669 */ 6670 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6671 6672 /* reg_ritr_rif 6673 * Router interface index. A pointer to the Router Interface Table. 6674 * Access: Index 6675 */ 6676 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6677 6678 /* reg_ritr_ipv4_fe 6679 * IPv4 Forwarding Enable. 6680 * Enables routing of IPv4 traffic on the router interface. When disabled, 6681 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6682 * Not supported in SwitchX-2. 6683 * Access: RW 6684 */ 6685 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6686 6687 /* reg_ritr_ipv6_fe 6688 * IPv6 Forwarding Enable. 6689 * Enables routing of IPv6 traffic on the router interface. When disabled, 6690 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6691 * Not supported in SwitchX-2. 6692 * Access: RW 6693 */ 6694 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6695 6696 /* reg_ritr_ipv4_mc_fe 6697 * IPv4 Multicast Forwarding Enable. 6698 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6699 * will be enabled. 6700 * Access: RW 6701 */ 6702 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6703 6704 /* reg_ritr_ipv6_mc_fe 6705 * IPv6 Multicast Forwarding Enable. 6706 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6707 * will be enabled. 6708 * Access: RW 6709 */ 6710 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6711 6712 /* reg_ritr_lb_en 6713 * Loop-back filter enable for unicast packets. 6714 * If the flag is set then loop-back filter for unicast packets is 6715 * implemented on the RIF. Multicast packets are always subject to 6716 * loop-back filtering. 6717 * Access: RW 6718 */ 6719 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6720 6721 /* reg_ritr_virtual_router 6722 * Virtual router ID associated with the router interface. 6723 * Access: RW 6724 */ 6725 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6726 6727 /* reg_ritr_mtu 6728 * Router interface MTU. 6729 * Access: RW 6730 */ 6731 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6732 6733 /* reg_ritr_if_swid 6734 * Switch partition ID. 6735 * Access: RW 6736 */ 6737 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6738 6739 /* reg_ritr_if_mac_profile_id 6740 * MAC msb profile ID. 6741 * Access: RW 6742 */ 6743 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6744 6745 /* reg_ritr_if_mac 6746 * Router interface MAC address. 6747 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6748 * Access: RW 6749 */ 6750 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6751 6752 /* reg_ritr_if_vrrp_id_ipv6 6753 * VRRP ID for IPv6 6754 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6755 * Access: RW 6756 */ 6757 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6758 6759 /* reg_ritr_if_vrrp_id_ipv4 6760 * VRRP ID for IPv4 6761 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6762 * Access: RW 6763 */ 6764 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6765 6766 /* VLAN Interface */ 6767 6768 /* reg_ritr_vlan_if_vlan_id 6769 * VLAN ID. 6770 * Access: RW 6771 */ 6772 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6773 6774 /* reg_ritr_vlan_if_efid 6775 * Egress FID. 6776 * Used to connect the RIF to a bridge. 6777 * Access: RW 6778 * 6779 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6780 */ 6781 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6782 6783 /* FID Interface */ 6784 6785 /* reg_ritr_fid_if_fid 6786 * Filtering ID. Used to connect a bridge to the router. 6787 * When legacy bridge model is used, only FIDs from the vFID range are 6788 * supported. When unified bridge model is used, this is the egress FID for 6789 * router to bridge. 6790 * Access: RW 6791 */ 6792 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6793 6794 /* Sub-port Interface */ 6795 6796 /* reg_ritr_sp_if_lag 6797 * LAG indication. When this bit is set the system_port field holds the 6798 * LAG identifier. 6799 * Access: RW 6800 */ 6801 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6802 6803 /* reg_ritr_sp_system_port 6804 * Port unique indentifier. When lag bit is set, this field holds the 6805 * lag_id in bits 0:9. 6806 * Access: RW 6807 */ 6808 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6809 6810 /* reg_ritr_sp_if_efid 6811 * Egress filtering ID. 6812 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6813 * the VID. 6814 * Access: RW 6815 * 6816 * Note: Reserved when legacy bridge model is used. 6817 */ 6818 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6819 6820 /* reg_ritr_sp_if_vid 6821 * VLAN ID. 6822 * Access: RW 6823 */ 6824 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6825 6826 /* Loopback Interface */ 6827 6828 enum mlxsw_reg_ritr_loopback_protocol { 6829 /* IPinIP IPv4 underlay Unicast */ 6830 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6831 /* IPinIP IPv6 underlay Unicast */ 6832 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6833 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6834 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6835 }; 6836 6837 /* reg_ritr_loopback_protocol 6838 * Access: RW 6839 */ 6840 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6841 6842 enum mlxsw_reg_ritr_loopback_ipip_type { 6843 /* Tunnel is IPinIP. */ 6844 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6845 /* Tunnel is GRE, no key. */ 6846 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6847 /* Tunnel is GRE, with a key. */ 6848 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6849 }; 6850 6851 /* reg_ritr_loopback_ipip_type 6852 * Encapsulation type. 6853 * Access: RW 6854 */ 6855 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6856 6857 enum mlxsw_reg_ritr_loopback_ipip_options { 6858 /* The key is defined by gre_key. */ 6859 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6860 }; 6861 6862 /* reg_ritr_loopback_ipip_options 6863 * Access: RW 6864 */ 6865 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6866 6867 /* reg_ritr_loopback_ipip_uvr 6868 * Underlay Virtual Router ID. 6869 * Range is 0..cap_max_virtual_routers-1. 6870 * Reserved for Spectrum-2. 6871 * Access: RW 6872 */ 6873 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6874 6875 /* reg_ritr_loopback_ipip_underlay_rif 6876 * Underlay ingress router interface. 6877 * Reserved for Spectrum. 6878 * Access: RW 6879 */ 6880 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6881 6882 /* reg_ritr_loopback_ipip_usip* 6883 * Encapsulation Underlay source IP. 6884 * Access: RW 6885 */ 6886 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6887 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6888 6889 /* reg_ritr_loopback_ipip_gre_key 6890 * GRE Key. 6891 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6892 * Access: RW 6893 */ 6894 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6895 6896 /* Shared between ingress/egress */ 6897 enum mlxsw_reg_ritr_counter_set_type { 6898 /* No Count. */ 6899 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6900 /* Basic. Used for router interfaces, counting the following: 6901 * - Error and Discard counters. 6902 * - Unicast, Multicast and Broadcast counters. Sharing the 6903 * same set of counters for the different type of traffic 6904 * (IPv4, IPv6 and mpls). 6905 */ 6906 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6907 }; 6908 6909 /* reg_ritr_ingress_counter_index 6910 * Counter Index for flow counter. 6911 * Access: RW 6912 */ 6913 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6914 6915 /* reg_ritr_ingress_counter_set_type 6916 * Igress Counter Set Type for router interface counter. 6917 * Access: RW 6918 */ 6919 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6920 6921 /* reg_ritr_egress_counter_index 6922 * Counter Index for flow counter. 6923 * Access: RW 6924 */ 6925 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6926 6927 /* reg_ritr_egress_counter_set_type 6928 * Egress Counter Set Type for router interface counter. 6929 * Access: RW 6930 */ 6931 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6932 6933 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6934 bool enable, bool egress) 6935 { 6936 enum mlxsw_reg_ritr_counter_set_type set_type; 6937 6938 if (enable) 6939 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6940 else 6941 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6942 6943 if (egress) { 6944 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6945 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6946 } else { 6947 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 6948 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6949 } 6950 } 6951 6952 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6953 { 6954 MLXSW_REG_ZERO(ritr, payload); 6955 mlxsw_reg_ritr_rif_set(payload, rif); 6956 } 6957 6958 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6959 u16 system_port, u16 efid, u16 vid) 6960 { 6961 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6962 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6963 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 6964 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6965 } 6966 6967 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6968 enum mlxsw_reg_ritr_if_type type, 6969 u16 rif, u16 vr_id, u16 mtu) 6970 { 6971 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6972 6973 MLXSW_REG_ZERO(ritr, payload); 6974 mlxsw_reg_ritr_enable_set(payload, enable); 6975 mlxsw_reg_ritr_ipv4_set(payload, 1); 6976 mlxsw_reg_ritr_ipv6_set(payload, 1); 6977 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6978 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6979 mlxsw_reg_ritr_type_set(payload, type); 6980 mlxsw_reg_ritr_op_set(payload, op); 6981 mlxsw_reg_ritr_rif_set(payload, rif); 6982 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6983 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6984 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6985 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6986 mlxsw_reg_ritr_lb_en_set(payload, 1); 6987 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6988 mlxsw_reg_ritr_mtu_set(payload, mtu); 6989 } 6990 6991 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6992 { 6993 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6994 } 6995 6996 static inline void 6997 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 6998 u16 mtu, const char *mac, u8 mac_profile_id, 6999 u16 vlan_id, u16 efid) 7000 { 7001 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7002 7003 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7004 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7005 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7006 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7007 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7008 } 7009 7010 static inline void 7011 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7012 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7013 enum mlxsw_reg_ritr_loopback_ipip_options options, 7014 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7015 { 7016 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7017 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7018 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7019 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7020 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7021 } 7022 7023 static inline void 7024 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7025 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7026 enum mlxsw_reg_ritr_loopback_ipip_options options, 7027 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7028 { 7029 mlxsw_reg_ritr_loopback_protocol_set(payload, 7030 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7031 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7032 uvr_id, underlay_rif, gre_key); 7033 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7034 } 7035 7036 static inline void 7037 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7038 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7039 enum mlxsw_reg_ritr_loopback_ipip_options options, 7040 u16 uvr_id, u16 underlay_rif, 7041 const struct in6_addr *usip, u32 gre_key) 7042 { 7043 enum mlxsw_reg_ritr_loopback_protocol protocol = 7044 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7045 7046 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7047 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7048 uvr_id, underlay_rif, gre_key); 7049 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7050 (const char *)usip); 7051 } 7052 7053 /* RTAR - Router TCAM Allocation Register 7054 * -------------------------------------- 7055 * This register is used for allocation of regions in the TCAM table. 7056 */ 7057 #define MLXSW_REG_RTAR_ID 0x8004 7058 #define MLXSW_REG_RTAR_LEN 0x20 7059 7060 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7061 7062 enum mlxsw_reg_rtar_op { 7063 MLXSW_REG_RTAR_OP_ALLOCATE, 7064 MLXSW_REG_RTAR_OP_RESIZE, 7065 MLXSW_REG_RTAR_OP_DEALLOCATE, 7066 }; 7067 7068 /* reg_rtar_op 7069 * Access: WO 7070 */ 7071 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7072 7073 enum mlxsw_reg_rtar_key_type { 7074 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7075 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7076 }; 7077 7078 /* reg_rtar_key_type 7079 * TCAM key type for the region. 7080 * Access: WO 7081 */ 7082 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7083 7084 /* reg_rtar_region_size 7085 * TCAM region size. When allocating/resizing this is the requested 7086 * size, the response is the actual size. 7087 * Note: Actual size may be larger than requested. 7088 * Reserved for op = Deallocate 7089 * Access: WO 7090 */ 7091 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7092 7093 static inline void mlxsw_reg_rtar_pack(char *payload, 7094 enum mlxsw_reg_rtar_op op, 7095 enum mlxsw_reg_rtar_key_type key_type, 7096 u16 region_size) 7097 { 7098 MLXSW_REG_ZERO(rtar, payload); 7099 mlxsw_reg_rtar_op_set(payload, op); 7100 mlxsw_reg_rtar_key_type_set(payload, key_type); 7101 mlxsw_reg_rtar_region_size_set(payload, region_size); 7102 } 7103 7104 /* RATR - Router Adjacency Table Register 7105 * -------------------------------------- 7106 * The RATR register is used to configure the Router Adjacency (next-hop) 7107 * Table. 7108 */ 7109 #define MLXSW_REG_RATR_ID 0x8008 7110 #define MLXSW_REG_RATR_LEN 0x2C 7111 7112 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7113 7114 enum mlxsw_reg_ratr_op { 7115 /* Read */ 7116 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7117 /* Read and clear activity */ 7118 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7119 /* Write Adjacency entry */ 7120 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7121 /* Write Adjacency entry only if the activity is cleared. 7122 * The write may not succeed if the activity is set. There is not 7123 * direct feedback if the write has succeeded or not, however 7124 * the get will reveal the actual entry (SW can compare the get 7125 * response to the set command). 7126 */ 7127 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7128 }; 7129 7130 /* reg_ratr_op 7131 * Note that Write operation may also be used for updating 7132 * counter_set_type and counter_index. In this case all other 7133 * fields must not be updated. 7134 * Access: OP 7135 */ 7136 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7137 7138 /* reg_ratr_v 7139 * Valid bit. Indicates if the adjacency entry is valid. 7140 * Note: the device may need some time before reusing an invalidated 7141 * entry. During this time the entry can not be reused. It is 7142 * recommended to use another entry before reusing an invalidated 7143 * entry (e.g. software can put it at the end of the list for 7144 * reusing). Trying to access an invalidated entry not yet cleared 7145 * by the device results with failure indicating "Try Again" status. 7146 * When valid is '0' then egress_router_interface,trap_action, 7147 * adjacency_parameters and counters are reserved 7148 * Access: RW 7149 */ 7150 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7151 7152 /* reg_ratr_a 7153 * Activity. Set for new entries. Set if a packet lookup has hit on 7154 * the specific entry. To clear the a bit, use "clear activity". 7155 * Access: RO 7156 */ 7157 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7158 7159 enum mlxsw_reg_ratr_type { 7160 /* Ethernet */ 7161 MLXSW_REG_RATR_TYPE_ETHERNET, 7162 /* IPoIB Unicast without GRH. 7163 * Reserved for Spectrum. 7164 */ 7165 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7166 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7167 * adjacency). 7168 * Reserved for Spectrum. 7169 */ 7170 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7171 /* IPoIB Multicast. 7172 * Reserved for Spectrum. 7173 */ 7174 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7175 /* MPLS. 7176 * Reserved for SwitchX/-2. 7177 */ 7178 MLXSW_REG_RATR_TYPE_MPLS, 7179 /* IPinIP Encap. 7180 * Reserved for SwitchX/-2. 7181 */ 7182 MLXSW_REG_RATR_TYPE_IPIP, 7183 }; 7184 7185 /* reg_ratr_type 7186 * Adjacency entry type. 7187 * Access: RW 7188 */ 7189 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7190 7191 /* reg_ratr_adjacency_index_low 7192 * Bits 15:0 of index into the adjacency table. 7193 * For SwitchX and SwitchX-2, the adjacency table is linear and 7194 * used for adjacency entries only. 7195 * For Spectrum, the index is to the KVD linear. 7196 * Access: Index 7197 */ 7198 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7199 7200 /* reg_ratr_egress_router_interface 7201 * Range is 0 .. cap_max_router_interfaces - 1 7202 * Access: RW 7203 */ 7204 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7205 7206 enum mlxsw_reg_ratr_trap_action { 7207 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7208 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7209 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7210 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7211 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7212 }; 7213 7214 /* reg_ratr_trap_action 7215 * see mlxsw_reg_ratr_trap_action 7216 * Access: RW 7217 */ 7218 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7219 7220 /* reg_ratr_adjacency_index_high 7221 * Bits 23:16 of the adjacency_index. 7222 * Access: Index 7223 */ 7224 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7225 7226 enum mlxsw_reg_ratr_trap_id { 7227 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7228 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7229 }; 7230 7231 /* reg_ratr_trap_id 7232 * Trap ID to be reported to CPU. 7233 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7234 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7235 * Access: RW 7236 */ 7237 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7238 7239 /* reg_ratr_eth_destination_mac 7240 * MAC address of the destination next-hop. 7241 * Access: RW 7242 */ 7243 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7244 7245 enum mlxsw_reg_ratr_ipip_type { 7246 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7247 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7248 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7249 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7250 }; 7251 7252 /* reg_ratr_ipip_type 7253 * Underlay destination ip type. 7254 * Note: the type field must match the protocol of the router interface. 7255 * Access: RW 7256 */ 7257 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7258 7259 /* reg_ratr_ipip_ipv4_udip 7260 * Underlay ipv4 dip. 7261 * Reserved when ipip_type is IPv6. 7262 * Access: RW 7263 */ 7264 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7265 7266 /* reg_ratr_ipip_ipv6_ptr 7267 * Pointer to IPv6 underlay destination ip address. 7268 * For Spectrum: Pointer to KVD linear space. 7269 * Access: RW 7270 */ 7271 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7272 7273 enum mlxsw_reg_flow_counter_set_type { 7274 /* No count */ 7275 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7276 /* Count packets and bytes */ 7277 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7278 /* Count only packets */ 7279 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7280 }; 7281 7282 /* reg_ratr_counter_set_type 7283 * Counter set type for flow counters 7284 * Access: RW 7285 */ 7286 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7287 7288 /* reg_ratr_counter_index 7289 * Counter index for flow counters 7290 * Access: RW 7291 */ 7292 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7293 7294 static inline void 7295 mlxsw_reg_ratr_pack(char *payload, 7296 enum mlxsw_reg_ratr_op op, bool valid, 7297 enum mlxsw_reg_ratr_type type, 7298 u32 adjacency_index, u16 egress_rif) 7299 { 7300 MLXSW_REG_ZERO(ratr, payload); 7301 mlxsw_reg_ratr_op_set(payload, op); 7302 mlxsw_reg_ratr_v_set(payload, valid); 7303 mlxsw_reg_ratr_type_set(payload, type); 7304 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7305 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7306 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7307 } 7308 7309 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7310 const char *dest_mac) 7311 { 7312 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7313 } 7314 7315 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7316 { 7317 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7318 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7319 } 7320 7321 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7322 { 7323 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7324 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7325 } 7326 7327 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7328 bool counter_enable) 7329 { 7330 enum mlxsw_reg_flow_counter_set_type set_type; 7331 7332 if (counter_enable) 7333 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7334 else 7335 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7336 7337 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7338 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7339 } 7340 7341 /* RDPM - Router DSCP to Priority Mapping 7342 * -------------------------------------- 7343 * Controls the mapping from DSCP field to switch priority on routed packets 7344 */ 7345 #define MLXSW_REG_RDPM_ID 0x8009 7346 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7347 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7348 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7349 #define MLXSW_REG_RDPM_LEN 0x40 7350 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7351 MLXSW_REG_RDPM_LEN - \ 7352 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7353 7354 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7355 7356 /* reg_dscp_entry_e 7357 * Enable update of the specific entry 7358 * Access: Index 7359 */ 7360 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7361 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7362 7363 /* reg_dscp_entry_prio 7364 * Switch Priority 7365 * Access: RW 7366 */ 7367 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7368 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7369 7370 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7371 u8 prio) 7372 { 7373 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7374 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7375 } 7376 7377 /* RICNT - Router Interface Counter Register 7378 * ----------------------------------------- 7379 * The RICNT register retrieves per port performance counters 7380 */ 7381 #define MLXSW_REG_RICNT_ID 0x800B 7382 #define MLXSW_REG_RICNT_LEN 0x100 7383 7384 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7385 7386 /* reg_ricnt_counter_index 7387 * Counter index 7388 * Access: RW 7389 */ 7390 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7391 7392 enum mlxsw_reg_ricnt_counter_set_type { 7393 /* No Count. */ 7394 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7395 /* Basic. Used for router interfaces, counting the following: 7396 * - Error and Discard counters. 7397 * - Unicast, Multicast and Broadcast counters. Sharing the 7398 * same set of counters for the different type of traffic 7399 * (IPv4, IPv6 and mpls). 7400 */ 7401 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7402 }; 7403 7404 /* reg_ricnt_counter_set_type 7405 * Counter Set Type for router interface counter 7406 * Access: RW 7407 */ 7408 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7409 7410 enum mlxsw_reg_ricnt_opcode { 7411 /* Nop. Supported only for read access*/ 7412 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7413 /* Clear. Setting the clr bit will reset the counter value for 7414 * all counters of the specified Router Interface. 7415 */ 7416 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7417 }; 7418 7419 /* reg_ricnt_opcode 7420 * Opcode 7421 * Access: RW 7422 */ 7423 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7424 7425 /* reg_ricnt_good_unicast_packets 7426 * good unicast packets. 7427 * Access: RW 7428 */ 7429 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7430 7431 /* reg_ricnt_good_multicast_packets 7432 * good multicast packets. 7433 * Access: RW 7434 */ 7435 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7436 7437 /* reg_ricnt_good_broadcast_packets 7438 * good broadcast packets 7439 * Access: RW 7440 */ 7441 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7442 7443 /* reg_ricnt_good_unicast_bytes 7444 * A count of L3 data and padding octets not including L2 headers 7445 * for good unicast frames. 7446 * Access: RW 7447 */ 7448 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7449 7450 /* reg_ricnt_good_multicast_bytes 7451 * A count of L3 data and padding octets not including L2 headers 7452 * for good multicast frames. 7453 * Access: RW 7454 */ 7455 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7456 7457 /* reg_ritr_good_broadcast_bytes 7458 * A count of L3 data and padding octets not including L2 headers 7459 * for good broadcast frames. 7460 * Access: RW 7461 */ 7462 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7463 7464 /* reg_ricnt_error_packets 7465 * A count of errored frames that do not pass the router checks. 7466 * Access: RW 7467 */ 7468 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7469 7470 /* reg_ricnt_discrad_packets 7471 * A count of non-errored frames that do not pass the router checks. 7472 * Access: RW 7473 */ 7474 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7475 7476 /* reg_ricnt_error_bytes 7477 * A count of L3 data and padding octets not including L2 headers 7478 * for errored frames. 7479 * Access: RW 7480 */ 7481 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7482 7483 /* reg_ricnt_discard_bytes 7484 * A count of L3 data and padding octets not including L2 headers 7485 * for non-errored frames that do not pass the router checks. 7486 * Access: RW 7487 */ 7488 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7489 7490 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7491 enum mlxsw_reg_ricnt_opcode op) 7492 { 7493 MLXSW_REG_ZERO(ricnt, payload); 7494 mlxsw_reg_ricnt_op_set(payload, op); 7495 mlxsw_reg_ricnt_counter_index_set(payload, index); 7496 mlxsw_reg_ricnt_counter_set_type_set(payload, 7497 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7498 } 7499 7500 /* RRCR - Router Rules Copy Register Layout 7501 * ---------------------------------------- 7502 * This register is used for moving and copying route entry rules. 7503 */ 7504 #define MLXSW_REG_RRCR_ID 0x800F 7505 #define MLXSW_REG_RRCR_LEN 0x24 7506 7507 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7508 7509 enum mlxsw_reg_rrcr_op { 7510 /* Move rules */ 7511 MLXSW_REG_RRCR_OP_MOVE, 7512 /* Copy rules */ 7513 MLXSW_REG_RRCR_OP_COPY, 7514 }; 7515 7516 /* reg_rrcr_op 7517 * Access: WO 7518 */ 7519 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7520 7521 /* reg_rrcr_offset 7522 * Offset within the region from which to copy/move. 7523 * Access: Index 7524 */ 7525 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7526 7527 /* reg_rrcr_size 7528 * The number of rules to copy/move. 7529 * Access: WO 7530 */ 7531 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7532 7533 /* reg_rrcr_table_id 7534 * Identifier of the table on which to perform the operation. Encoding is the 7535 * same as in RTAR.key_type 7536 * Access: Index 7537 */ 7538 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7539 7540 /* reg_rrcr_dest_offset 7541 * Offset within the region to which to copy/move 7542 * Access: Index 7543 */ 7544 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7545 7546 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7547 u16 offset, u16 size, 7548 enum mlxsw_reg_rtar_key_type table_id, 7549 u16 dest_offset) 7550 { 7551 MLXSW_REG_ZERO(rrcr, payload); 7552 mlxsw_reg_rrcr_op_set(payload, op); 7553 mlxsw_reg_rrcr_offset_set(payload, offset); 7554 mlxsw_reg_rrcr_size_set(payload, size); 7555 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7556 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7557 } 7558 7559 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7560 * ------------------------------------------------------- 7561 * RALTA is used to allocate the LPM trees of the SHSPM method. 7562 */ 7563 #define MLXSW_REG_RALTA_ID 0x8010 7564 #define MLXSW_REG_RALTA_LEN 0x04 7565 7566 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7567 7568 /* reg_ralta_op 7569 * opcode (valid for Write, must be 0 on Read) 7570 * 0 - allocate a tree 7571 * 1 - deallocate a tree 7572 * Access: OP 7573 */ 7574 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7575 7576 enum mlxsw_reg_ralxx_protocol { 7577 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7578 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7579 }; 7580 7581 /* reg_ralta_protocol 7582 * Protocol. 7583 * Deallocation opcode: Reserved. 7584 * Access: RW 7585 */ 7586 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7587 7588 /* reg_ralta_tree_id 7589 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7590 * the tree identifier (managed by software). 7591 * Note that tree_id 0 is allocated for a default-route tree. 7592 * Access: Index 7593 */ 7594 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7595 7596 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7597 enum mlxsw_reg_ralxx_protocol protocol, 7598 u8 tree_id) 7599 { 7600 MLXSW_REG_ZERO(ralta, payload); 7601 mlxsw_reg_ralta_op_set(payload, !alloc); 7602 mlxsw_reg_ralta_protocol_set(payload, protocol); 7603 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7604 } 7605 7606 /* RALST - Router Algorithmic LPM Structure Tree Register 7607 * ------------------------------------------------------ 7608 * RALST is used to set and query the structure of an LPM tree. 7609 * The structure of the tree must be sorted as a sorted binary tree, while 7610 * each node is a bin that is tagged as the length of the prefixes the lookup 7611 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7612 * of X bits to match with the destination address. The bin 0 indicates 7613 * the default action, when there is no match of any prefix. 7614 */ 7615 #define MLXSW_REG_RALST_ID 0x8011 7616 #define MLXSW_REG_RALST_LEN 0x104 7617 7618 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7619 7620 /* reg_ralst_root_bin 7621 * The bin number of the root bin. 7622 * 0<root_bin=<(length of IP address) 7623 * For a default-route tree configure 0xff 7624 * Access: RW 7625 */ 7626 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7627 7628 /* reg_ralst_tree_id 7629 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7630 * Access: Index 7631 */ 7632 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7633 7634 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7635 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7636 #define MLXSW_REG_RALST_BIN_COUNT 128 7637 7638 /* reg_ralst_left_child_bin 7639 * Holding the children of the bin according to the stored tree's structure. 7640 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7641 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7642 * Access: RW 7643 */ 7644 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7645 7646 /* reg_ralst_right_child_bin 7647 * Holding the children of the bin according to the stored tree's structure. 7648 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7649 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7650 * Access: RW 7651 */ 7652 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7653 false); 7654 7655 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7656 { 7657 MLXSW_REG_ZERO(ralst, payload); 7658 7659 /* Initialize all bins to have no left or right child */ 7660 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7661 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7662 7663 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7664 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7665 } 7666 7667 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7668 u8 left_child_bin, 7669 u8 right_child_bin) 7670 { 7671 int bin_index = bin_number - 1; 7672 7673 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7674 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7675 right_child_bin); 7676 } 7677 7678 /* RALTB - Router Algorithmic LPM Tree Binding Register 7679 * ---------------------------------------------------- 7680 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7681 */ 7682 #define MLXSW_REG_RALTB_ID 0x8012 7683 #define MLXSW_REG_RALTB_LEN 0x04 7684 7685 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7686 7687 /* reg_raltb_virtual_router 7688 * Virtual Router ID 7689 * Range is 0..cap_max_virtual_routers-1 7690 * Access: Index 7691 */ 7692 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7693 7694 /* reg_raltb_protocol 7695 * Protocol. 7696 * Access: Index 7697 */ 7698 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7699 7700 /* reg_raltb_tree_id 7701 * Tree to be used for the {virtual_router, protocol} 7702 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7703 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7704 * Access: RW 7705 */ 7706 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7707 7708 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7709 enum mlxsw_reg_ralxx_protocol protocol, 7710 u8 tree_id) 7711 { 7712 MLXSW_REG_ZERO(raltb, payload); 7713 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7714 mlxsw_reg_raltb_protocol_set(payload, protocol); 7715 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7716 } 7717 7718 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7719 * ----------------------------------------------------- 7720 * RALUE is used to configure and query LPM entries that serve 7721 * the Unicast protocols. 7722 */ 7723 #define MLXSW_REG_RALUE_ID 0x8013 7724 #define MLXSW_REG_RALUE_LEN 0x38 7725 7726 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7727 7728 /* reg_ralue_protocol 7729 * Protocol. 7730 * Access: Index 7731 */ 7732 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7733 7734 enum mlxsw_reg_ralue_op { 7735 /* Read operation. If entry doesn't exist, the operation fails. */ 7736 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7737 /* Clear on read operation. Used to read entry and 7738 * clear Activity bit. 7739 */ 7740 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7741 /* Write operation. Used to write a new entry to the table. All RW 7742 * fields are written for new entry. Activity bit is set 7743 * for new entries. 7744 */ 7745 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7746 /* Update operation. Used to update an existing route entry and 7747 * only update the RW fields that are detailed in the field 7748 * op_u_mask. If entry doesn't exist, the operation fails. 7749 */ 7750 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7751 /* Clear activity. The Activity bit (the field a) is cleared 7752 * for the entry. 7753 */ 7754 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7755 /* Delete operation. Used to delete an existing entry. If entry 7756 * doesn't exist, the operation fails. 7757 */ 7758 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7759 }; 7760 7761 /* reg_ralue_op 7762 * Operation. 7763 * Access: OP 7764 */ 7765 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7766 7767 /* reg_ralue_a 7768 * Activity. Set for new entries. Set if a packet lookup has hit on the 7769 * specific entry, only if the entry is a route. To clear the a bit, use 7770 * "clear activity" op. 7771 * Enabled by activity_dis in RGCR 7772 * Access: RO 7773 */ 7774 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7775 7776 /* reg_ralue_virtual_router 7777 * Virtual Router ID 7778 * Range is 0..cap_max_virtual_routers-1 7779 * Access: Index 7780 */ 7781 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7782 7783 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7784 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7785 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7786 7787 /* reg_ralue_op_u_mask 7788 * opcode update mask. 7789 * On read operation, this field is reserved. 7790 * This field is valid for update opcode, otherwise - reserved. 7791 * This field is a bitmask of the fields that should be updated. 7792 * Access: WO 7793 */ 7794 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7795 7796 /* reg_ralue_prefix_len 7797 * Number of bits in the prefix of the LPM route. 7798 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7799 * two entries in the physical HW table. 7800 * Access: Index 7801 */ 7802 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7803 7804 /* reg_ralue_dip* 7805 * The prefix of the route or of the marker that the object of the LPM 7806 * is compared with. The most significant bits of the dip are the prefix. 7807 * The least significant bits must be '0' if the prefix_len is smaller 7808 * than 128 for IPv6 or smaller than 32 for IPv4. 7809 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7810 * Access: Index 7811 */ 7812 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7813 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7814 7815 enum mlxsw_reg_ralue_entry_type { 7816 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7817 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7818 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7819 }; 7820 7821 /* reg_ralue_entry_type 7822 * Entry type. 7823 * Note - for Marker entries, the action_type and action fields are reserved. 7824 * Access: RW 7825 */ 7826 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7827 7828 /* reg_ralue_bmp_len 7829 * The best match prefix length in the case that there is no match for 7830 * longer prefixes. 7831 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7832 * Note for any update operation with entry_type modification this 7833 * field must be set. 7834 * Access: RW 7835 */ 7836 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7837 7838 enum mlxsw_reg_ralue_action_type { 7839 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7840 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7841 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7842 }; 7843 7844 /* reg_ralue_action_type 7845 * Action Type 7846 * Indicates how the IP address is connected. 7847 * It can be connected to a local subnet through local_erif or can be 7848 * on a remote subnet connected through a next-hop router, 7849 * or transmitted to the CPU. 7850 * Reserved when entry_type = MARKER_ENTRY 7851 * Access: RW 7852 */ 7853 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7854 7855 enum mlxsw_reg_ralue_trap_action { 7856 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7857 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7858 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7859 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7860 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7861 }; 7862 7863 /* reg_ralue_trap_action 7864 * Trap action. 7865 * For IP2ME action, only NOP and MIRROR are possible. 7866 * Access: RW 7867 */ 7868 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7869 7870 /* reg_ralue_trap_id 7871 * Trap ID to be reported to CPU. 7872 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7873 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7874 * Access: RW 7875 */ 7876 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7877 7878 /* reg_ralue_adjacency_index 7879 * Points to the first entry of the group-based ECMP. 7880 * Only relevant in case of REMOTE action. 7881 * Access: RW 7882 */ 7883 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7884 7885 /* reg_ralue_ecmp_size 7886 * Amount of sequential entries starting 7887 * from the adjacency_index (the number of ECMPs). 7888 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7889 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7890 * Only relevant in case of REMOTE action. 7891 * Access: RW 7892 */ 7893 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7894 7895 /* reg_ralue_local_erif 7896 * Egress Router Interface. 7897 * Only relevant in case of LOCAL action. 7898 * Access: RW 7899 */ 7900 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7901 7902 /* reg_ralue_ip2me_v 7903 * Valid bit for the tunnel_ptr field. 7904 * If valid = 0 then trap to CPU as IP2ME trap ID. 7905 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7906 * decapsulation then tunnel decapsulation is done. 7907 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7908 * decapsulation then trap as IP2ME trap ID. 7909 * Only relevant in case of IP2ME action. 7910 * Access: RW 7911 */ 7912 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7913 7914 /* reg_ralue_ip2me_tunnel_ptr 7915 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7916 * For Spectrum, pointer to KVD Linear. 7917 * Only relevant in case of IP2ME action. 7918 * Access: RW 7919 */ 7920 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7921 7922 static inline void mlxsw_reg_ralue_pack(char *payload, 7923 enum mlxsw_reg_ralxx_protocol protocol, 7924 enum mlxsw_reg_ralue_op op, 7925 u16 virtual_router, u8 prefix_len) 7926 { 7927 MLXSW_REG_ZERO(ralue, payload); 7928 mlxsw_reg_ralue_protocol_set(payload, protocol); 7929 mlxsw_reg_ralue_op_set(payload, op); 7930 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7931 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7932 mlxsw_reg_ralue_entry_type_set(payload, 7933 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7934 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7935 } 7936 7937 static inline void mlxsw_reg_ralue_pack4(char *payload, 7938 enum mlxsw_reg_ralxx_protocol protocol, 7939 enum mlxsw_reg_ralue_op op, 7940 u16 virtual_router, u8 prefix_len, 7941 u32 dip) 7942 { 7943 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7944 mlxsw_reg_ralue_dip4_set(payload, dip); 7945 } 7946 7947 static inline void mlxsw_reg_ralue_pack6(char *payload, 7948 enum mlxsw_reg_ralxx_protocol protocol, 7949 enum mlxsw_reg_ralue_op op, 7950 u16 virtual_router, u8 prefix_len, 7951 const void *dip) 7952 { 7953 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7954 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7955 } 7956 7957 static inline void 7958 mlxsw_reg_ralue_act_remote_pack(char *payload, 7959 enum mlxsw_reg_ralue_trap_action trap_action, 7960 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7961 { 7962 mlxsw_reg_ralue_action_type_set(payload, 7963 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7964 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7965 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7966 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7967 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7968 } 7969 7970 static inline void 7971 mlxsw_reg_ralue_act_local_pack(char *payload, 7972 enum mlxsw_reg_ralue_trap_action trap_action, 7973 u16 trap_id, u16 local_erif) 7974 { 7975 mlxsw_reg_ralue_action_type_set(payload, 7976 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7977 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7978 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7979 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7980 } 7981 7982 static inline void 7983 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7984 { 7985 mlxsw_reg_ralue_action_type_set(payload, 7986 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7987 } 7988 7989 static inline void 7990 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7991 { 7992 mlxsw_reg_ralue_action_type_set(payload, 7993 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7994 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7995 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7996 } 7997 7998 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7999 * ---------------------------------------------------------- 8000 * The RAUHT register is used to configure and query the Unicast Host table in 8001 * devices that implement the Algorithmic LPM. 8002 */ 8003 #define MLXSW_REG_RAUHT_ID 0x8014 8004 #define MLXSW_REG_RAUHT_LEN 0x74 8005 8006 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8007 8008 enum mlxsw_reg_rauht_type { 8009 MLXSW_REG_RAUHT_TYPE_IPV4, 8010 MLXSW_REG_RAUHT_TYPE_IPV6, 8011 }; 8012 8013 /* reg_rauht_type 8014 * Access: Index 8015 */ 8016 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8017 8018 enum mlxsw_reg_rauht_op { 8019 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8020 /* Read operation */ 8021 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8022 /* Clear on read operation. Used to read entry and clear 8023 * activity bit. 8024 */ 8025 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8026 /* Add. Used to write a new entry to the table. All R/W fields are 8027 * relevant for new entry. Activity bit is set for new entries. 8028 */ 8029 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8030 /* Update action. Used to update an existing route entry and 8031 * only update the following fields: 8032 * trap_action, trap_id, mac, counter_set_type, counter_index 8033 */ 8034 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8035 /* Clear activity. A bit is cleared for the entry. */ 8036 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8037 /* Delete entry */ 8038 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8039 /* Delete all host entries on a RIF. In this command, dip 8040 * field is reserved. 8041 */ 8042 }; 8043 8044 /* reg_rauht_op 8045 * Access: OP 8046 */ 8047 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8048 8049 /* reg_rauht_a 8050 * Activity. Set for new entries. Set if a packet lookup has hit on 8051 * the specific entry. 8052 * To clear the a bit, use "clear activity" op. 8053 * Enabled by activity_dis in RGCR 8054 * Access: RO 8055 */ 8056 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8057 8058 /* reg_rauht_rif 8059 * Router Interface 8060 * Access: Index 8061 */ 8062 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8063 8064 /* reg_rauht_dip* 8065 * Destination address. 8066 * Access: Index 8067 */ 8068 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8069 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8070 8071 enum mlxsw_reg_rauht_trap_action { 8072 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8073 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8074 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8075 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8076 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8077 }; 8078 8079 /* reg_rauht_trap_action 8080 * Access: RW 8081 */ 8082 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8083 8084 enum mlxsw_reg_rauht_trap_id { 8085 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8086 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8087 }; 8088 8089 /* reg_rauht_trap_id 8090 * Trap ID to be reported to CPU. 8091 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8092 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8093 * trap_id is reserved. 8094 * Access: RW 8095 */ 8096 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8097 8098 /* reg_rauht_counter_set_type 8099 * Counter set type for flow counters 8100 * Access: RW 8101 */ 8102 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8103 8104 /* reg_rauht_counter_index 8105 * Counter index for flow counters 8106 * Access: RW 8107 */ 8108 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8109 8110 /* reg_rauht_mac 8111 * MAC address. 8112 * Access: RW 8113 */ 8114 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8115 8116 static inline void mlxsw_reg_rauht_pack(char *payload, 8117 enum mlxsw_reg_rauht_op op, u16 rif, 8118 const char *mac) 8119 { 8120 MLXSW_REG_ZERO(rauht, payload); 8121 mlxsw_reg_rauht_op_set(payload, op); 8122 mlxsw_reg_rauht_rif_set(payload, rif); 8123 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8124 } 8125 8126 static inline void mlxsw_reg_rauht_pack4(char *payload, 8127 enum mlxsw_reg_rauht_op op, u16 rif, 8128 const char *mac, u32 dip) 8129 { 8130 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8131 mlxsw_reg_rauht_dip4_set(payload, dip); 8132 } 8133 8134 static inline void mlxsw_reg_rauht_pack6(char *payload, 8135 enum mlxsw_reg_rauht_op op, u16 rif, 8136 const char *mac, const char *dip) 8137 { 8138 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8139 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8140 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8141 } 8142 8143 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8144 u64 counter_index) 8145 { 8146 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8147 mlxsw_reg_rauht_counter_set_type_set(payload, 8148 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8149 } 8150 8151 /* RALEU - Router Algorithmic LPM ECMP Update Register 8152 * --------------------------------------------------- 8153 * The register enables updating the ECMP section in the action for multiple 8154 * LPM Unicast entries in a single operation. The update is executed to 8155 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8156 */ 8157 #define MLXSW_REG_RALEU_ID 0x8015 8158 #define MLXSW_REG_RALEU_LEN 0x28 8159 8160 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8161 8162 /* reg_raleu_protocol 8163 * Protocol. 8164 * Access: Index 8165 */ 8166 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8167 8168 /* reg_raleu_virtual_router 8169 * Virtual Router ID 8170 * Range is 0..cap_max_virtual_routers-1 8171 * Access: Index 8172 */ 8173 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8174 8175 /* reg_raleu_adjacency_index 8176 * Adjacency Index used for matching on the existing entries. 8177 * Access: Index 8178 */ 8179 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8180 8181 /* reg_raleu_ecmp_size 8182 * ECMP Size used for matching on the existing entries. 8183 * Access: Index 8184 */ 8185 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8186 8187 /* reg_raleu_new_adjacency_index 8188 * New Adjacency Index. 8189 * Access: WO 8190 */ 8191 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8192 8193 /* reg_raleu_new_ecmp_size 8194 * New ECMP Size. 8195 * Access: WO 8196 */ 8197 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8198 8199 static inline void mlxsw_reg_raleu_pack(char *payload, 8200 enum mlxsw_reg_ralxx_protocol protocol, 8201 u16 virtual_router, 8202 u32 adjacency_index, u16 ecmp_size, 8203 u32 new_adjacency_index, 8204 u16 new_ecmp_size) 8205 { 8206 MLXSW_REG_ZERO(raleu, payload); 8207 mlxsw_reg_raleu_protocol_set(payload, protocol); 8208 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8209 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8210 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8211 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8212 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8213 } 8214 8215 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8216 * ---------------------------------------------------------------- 8217 * The RAUHTD register allows dumping entries from the Router Unicast Host 8218 * Table. For a given session an entry is dumped no more than one time. The 8219 * first RAUHTD access after reset is a new session. A session ends when the 8220 * num_rec response is smaller than num_rec request or for IPv4 when the 8221 * num_entries is smaller than 4. The clear activity affect the current session 8222 * or the last session if a new session has not started. 8223 */ 8224 #define MLXSW_REG_RAUHTD_ID 0x8018 8225 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8226 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8227 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8228 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8229 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8230 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8231 8232 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8233 8234 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8235 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8236 8237 /* reg_rauhtd_filter_fields 8238 * if a bit is '0' then the relevant field is ignored and dump is done 8239 * regardless of the field value 8240 * Bit0 - filter by activity: entry_a 8241 * Bit3 - filter by entry rip: entry_rif 8242 * Access: Index 8243 */ 8244 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8245 8246 enum mlxsw_reg_rauhtd_op { 8247 MLXSW_REG_RAUHTD_OP_DUMP, 8248 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8249 }; 8250 8251 /* reg_rauhtd_op 8252 * Access: OP 8253 */ 8254 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8255 8256 /* reg_rauhtd_num_rec 8257 * At request: number of records requested 8258 * At response: number of records dumped 8259 * For IPv4, each record has 4 entries at request and up to 4 entries 8260 * at response 8261 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8262 * Access: Index 8263 */ 8264 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8265 8266 /* reg_rauhtd_entry_a 8267 * Dump only if activity has value of entry_a 8268 * Reserved if filter_fields bit0 is '0' 8269 * Access: Index 8270 */ 8271 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8272 8273 enum mlxsw_reg_rauhtd_type { 8274 MLXSW_REG_RAUHTD_TYPE_IPV4, 8275 MLXSW_REG_RAUHTD_TYPE_IPV6, 8276 }; 8277 8278 /* reg_rauhtd_type 8279 * Dump only if record type is: 8280 * 0 - IPv4 8281 * 1 - IPv6 8282 * Access: Index 8283 */ 8284 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8285 8286 /* reg_rauhtd_entry_rif 8287 * Dump only if RIF has value of entry_rif 8288 * Reserved if filter_fields bit3 is '0' 8289 * Access: Index 8290 */ 8291 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8292 8293 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8294 enum mlxsw_reg_rauhtd_type type) 8295 { 8296 MLXSW_REG_ZERO(rauhtd, payload); 8297 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8298 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8299 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8300 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8301 mlxsw_reg_rauhtd_type_set(payload, type); 8302 } 8303 8304 /* reg_rauhtd_ipv4_rec_num_entries 8305 * Number of valid entries in this record: 8306 * 0 - 1 valid entry 8307 * 1 - 2 valid entries 8308 * 2 - 3 valid entries 8309 * 3 - 4 valid entries 8310 * Access: RO 8311 */ 8312 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8313 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8314 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8315 8316 /* reg_rauhtd_rec_type 8317 * Record type. 8318 * 0 - IPv4 8319 * 1 - IPv6 8320 * Access: RO 8321 */ 8322 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8323 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8324 8325 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8326 8327 /* reg_rauhtd_ipv4_ent_a 8328 * Activity. Set for new entries. Set if a packet lookup has hit on the 8329 * specific entry. 8330 * Access: RO 8331 */ 8332 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8333 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8334 8335 /* reg_rauhtd_ipv4_ent_rif 8336 * Router interface. 8337 * Access: RO 8338 */ 8339 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8340 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8341 8342 /* reg_rauhtd_ipv4_ent_dip 8343 * Destination IPv4 address. 8344 * Access: RO 8345 */ 8346 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8347 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8348 8349 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8350 8351 /* reg_rauhtd_ipv6_ent_a 8352 * Activity. Set for new entries. Set if a packet lookup has hit on the 8353 * specific entry. 8354 * Access: RO 8355 */ 8356 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8357 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8358 8359 /* reg_rauhtd_ipv6_ent_rif 8360 * Router interface. 8361 * Access: RO 8362 */ 8363 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8364 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8365 8366 /* reg_rauhtd_ipv6_ent_dip 8367 * Destination IPv6 address. 8368 * Access: RO 8369 */ 8370 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8371 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8372 8373 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8374 int ent_index, u16 *p_rif, 8375 u32 *p_dip) 8376 { 8377 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8378 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8379 } 8380 8381 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8382 int rec_index, u16 *p_rif, 8383 char *p_dip) 8384 { 8385 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8386 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8387 } 8388 8389 /* RTDP - Routing Tunnel Decap Properties Register 8390 * ----------------------------------------------- 8391 * The RTDP register is used for configuring the tunnel decap properties of NVE 8392 * and IPinIP. 8393 */ 8394 #define MLXSW_REG_RTDP_ID 0x8020 8395 #define MLXSW_REG_RTDP_LEN 0x44 8396 8397 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8398 8399 enum mlxsw_reg_rtdp_type { 8400 MLXSW_REG_RTDP_TYPE_NVE, 8401 MLXSW_REG_RTDP_TYPE_IPIP, 8402 }; 8403 8404 /* reg_rtdp_type 8405 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8406 * Access: RW 8407 */ 8408 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8409 8410 /* reg_rtdp_tunnel_index 8411 * Index to the Decap entry. 8412 * For Spectrum, Index to KVD Linear. 8413 * Access: Index 8414 */ 8415 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8416 8417 /* reg_rtdp_egress_router_interface 8418 * Underlay egress router interface. 8419 * Valid range is from 0 to cap_max_router_interfaces - 1 8420 * Access: RW 8421 */ 8422 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8423 8424 /* IPinIP */ 8425 8426 /* reg_rtdp_ipip_irif 8427 * Ingress Router Interface for the overlay router 8428 * Access: RW 8429 */ 8430 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8431 8432 enum mlxsw_reg_rtdp_ipip_sip_check { 8433 /* No sip checks. */ 8434 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8435 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8436 * equal ipv4_usip. 8437 */ 8438 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8439 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8440 * equal ipv6_usip. 8441 */ 8442 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8443 }; 8444 8445 /* reg_rtdp_ipip_sip_check 8446 * SIP check to perform. If decapsulation failed due to these configurations 8447 * then trap_id is IPIP_DECAP_ERROR. 8448 * Access: RW 8449 */ 8450 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8451 8452 /* If set, allow decapsulation of IPinIP (without GRE). */ 8453 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8454 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8455 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8456 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8457 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8458 8459 /* reg_rtdp_ipip_type_check 8460 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8461 * these configurations then trap_id is IPIP_DECAP_ERROR. 8462 * Access: RW 8463 */ 8464 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8465 8466 /* reg_rtdp_ipip_gre_key_check 8467 * Whether GRE key should be checked. When check is enabled: 8468 * - A packet received as IPinIP (without GRE) will always pass. 8469 * - A packet received as IPinGREinIP without a key will not pass the check. 8470 * - A packet received as IPinGREinIP with a key will pass the check only if the 8471 * key in the packet is equal to expected_gre_key. 8472 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8473 * Access: RW 8474 */ 8475 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8476 8477 /* reg_rtdp_ipip_ipv4_usip 8478 * Underlay IPv4 address for ipv4 source address check. 8479 * Reserved when sip_check is not '1'. 8480 * Access: RW 8481 */ 8482 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8483 8484 /* reg_rtdp_ipip_ipv6_usip_ptr 8485 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8486 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8487 * is to the KVD linear. 8488 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8489 * Access: RW 8490 */ 8491 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8492 8493 /* reg_rtdp_ipip_expected_gre_key 8494 * GRE key for checking. 8495 * Reserved when gre_key_check is '0'. 8496 * Access: RW 8497 */ 8498 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8499 8500 static inline void mlxsw_reg_rtdp_pack(char *payload, 8501 enum mlxsw_reg_rtdp_type type, 8502 u32 tunnel_index) 8503 { 8504 MLXSW_REG_ZERO(rtdp, payload); 8505 mlxsw_reg_rtdp_type_set(payload, type); 8506 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8507 } 8508 8509 static inline void 8510 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8511 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8512 unsigned int type_check, bool gre_key_check, 8513 u32 expected_gre_key) 8514 { 8515 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8516 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8517 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8518 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8519 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8520 } 8521 8522 static inline void 8523 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8524 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8525 unsigned int type_check, bool gre_key_check, 8526 u32 ipv4_usip, u32 expected_gre_key) 8527 { 8528 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8529 gre_key_check, expected_gre_key); 8530 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8531 } 8532 8533 static inline void 8534 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8535 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8536 unsigned int type_check, bool gre_key_check, 8537 u32 ipv6_usip_ptr, u32 expected_gre_key) 8538 { 8539 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8540 gre_key_check, expected_gre_key); 8541 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8542 } 8543 8544 /* RIPS - Router IP version Six Register 8545 * ------------------------------------- 8546 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8547 * IPinIP 8548 */ 8549 #define MLXSW_REG_RIPS_ID 0x8021 8550 #define MLXSW_REG_RIPS_LEN 0x14 8551 8552 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8553 8554 /* reg_rips_index 8555 * Index to IPv6 address. 8556 * For Spectrum, the index is to the KVD linear. 8557 * Access: Index 8558 */ 8559 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8560 8561 /* reg_rips_ipv6 8562 * IPv6 address 8563 * Access: RW 8564 */ 8565 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8566 8567 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8568 const struct in6_addr *ipv6) 8569 { 8570 MLXSW_REG_ZERO(rips, payload); 8571 mlxsw_reg_rips_index_set(payload, index); 8572 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8573 } 8574 8575 /* RATRAD - Router Adjacency Table Activity Dump Register 8576 * ------------------------------------------------------ 8577 * The RATRAD register is used to dump and optionally clear activity bits of 8578 * router adjacency table entries. 8579 */ 8580 #define MLXSW_REG_RATRAD_ID 0x8022 8581 #define MLXSW_REG_RATRAD_LEN 0x210 8582 8583 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8584 8585 enum { 8586 /* Read activity */ 8587 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8588 /* Read and clear activity */ 8589 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8590 }; 8591 8592 /* reg_ratrad_op 8593 * Access: Operation 8594 */ 8595 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8596 8597 /* reg_ratrad_ecmp_size 8598 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8599 * ranges: 8600 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8601 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8602 * Access: Index 8603 */ 8604 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8605 8606 /* reg_ratrad_adjacency_index 8607 * Index into the adjacency table. 8608 * Access: Index 8609 */ 8610 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8611 8612 /* reg_ratrad_activity_vector 8613 * Activity bit per adjacency index. 8614 * Bits higher than ecmp_size are reserved. 8615 * Access: RO 8616 */ 8617 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8618 8619 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8620 u16 ecmp_size) 8621 { 8622 MLXSW_REG_ZERO(ratrad, payload); 8623 mlxsw_reg_ratrad_op_set(payload, 8624 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8625 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8626 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8627 } 8628 8629 /* RIGR-V2 - Router Interface Group Register Version 2 8630 * --------------------------------------------------- 8631 * The RIGR_V2 register is used to add, remove and query egress interface list 8632 * of a multicast forwarding entry. 8633 */ 8634 #define MLXSW_REG_RIGR2_ID 0x8023 8635 #define MLXSW_REG_RIGR2_LEN 0xB0 8636 8637 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8638 8639 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8640 8641 /* reg_rigr2_rigr_index 8642 * KVD Linear index. 8643 * Access: Index 8644 */ 8645 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8646 8647 /* reg_rigr2_vnext 8648 * Next RIGR Index is valid. 8649 * Access: RW 8650 */ 8651 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8652 8653 /* reg_rigr2_next_rigr_index 8654 * Next RIGR Index. The index is to the KVD linear. 8655 * Reserved when vnxet = '0'. 8656 * Access: RW 8657 */ 8658 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8659 8660 /* reg_rigr2_vrmid 8661 * RMID Index is valid. 8662 * Access: RW 8663 */ 8664 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8665 8666 /* reg_rigr2_rmid_index 8667 * RMID Index. 8668 * Range 0 .. max_mid - 1 8669 * Reserved when vrmid = '0'. 8670 * The index is to the Port Group Table (PGT) 8671 * Access: RW 8672 */ 8673 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8674 8675 /* reg_rigr2_erif_entry_v 8676 * Egress Router Interface is valid. 8677 * Note that low-entries must be set if high-entries are set. For 8678 * example: if erif_entry[2].v is set then erif_entry[1].v and 8679 * erif_entry[0].v must be set. 8680 * Index can be from 0 to cap_mc_erif_list_entries-1 8681 * Access: RW 8682 */ 8683 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8684 8685 /* reg_rigr2_erif_entry_erif 8686 * Egress Router Interface. 8687 * Valid range is from 0 to cap_max_router_interfaces - 1 8688 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8689 * Access: RW 8690 */ 8691 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8692 8693 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8694 bool vnext, u32 next_rigr_index) 8695 { 8696 MLXSW_REG_ZERO(rigr2, payload); 8697 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8698 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8699 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8700 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8701 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8702 } 8703 8704 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8705 bool v, u16 erif) 8706 { 8707 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8708 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8709 } 8710 8711 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8712 * ------------------------------------------------------ 8713 */ 8714 #define MLXSW_REG_RECR2_ID 0x8025 8715 #define MLXSW_REG_RECR2_LEN 0x38 8716 8717 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8718 8719 /* reg_recr2_pp 8720 * Per-port configuration 8721 * Access: Index 8722 */ 8723 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8724 8725 /* reg_recr2_sh 8726 * Symmetric hash 8727 * Access: RW 8728 */ 8729 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8730 8731 /* reg_recr2_seed 8732 * Seed 8733 * Access: RW 8734 */ 8735 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8736 8737 enum { 8738 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8739 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8740 /* Enable IPv4 fields if packet is TCP or UDP */ 8741 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8742 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8743 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8744 /* Enable IPv6 fields if packet is TCP or UDP */ 8745 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8746 /* Enable TCP/UDP header fields if packet is IPv4 */ 8747 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8748 /* Enable TCP/UDP header fields if packet is IPv6 */ 8749 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8750 8751 __MLXSW_REG_RECR2_HEADER_CNT, 8752 }; 8753 8754 /* reg_recr2_outer_header_enables 8755 * Bit mask where each bit enables a specific layer to be included in 8756 * the hash calculation. 8757 * Access: RW 8758 */ 8759 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8760 8761 enum { 8762 /* IPv4 Source IP */ 8763 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8764 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8765 /* IPv4 Destination IP */ 8766 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8767 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8768 /* IP Protocol */ 8769 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8770 /* IPv6 Source IP */ 8771 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8772 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8773 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8774 /* IPv6 Destination IP */ 8775 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8776 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8777 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8778 /* IPv6 Next Header */ 8779 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8780 /* IPv6 Flow Label */ 8781 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8782 /* TCP/UDP Source Port */ 8783 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8784 /* TCP/UDP Destination Port */ 8785 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8786 8787 __MLXSW_REG_RECR2_FIELD_CNT, 8788 }; 8789 8790 /* reg_recr2_outer_header_fields_enable 8791 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8792 * Access: RW 8793 */ 8794 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8795 8796 /* reg_recr2_inner_header_enables 8797 * Bit mask where each bit enables a specific inner layer to be included in the 8798 * hash calculation. Same values as reg_recr2_outer_header_enables. 8799 * Access: RW 8800 */ 8801 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8802 8803 enum { 8804 /* Inner IPv4 Source IP */ 8805 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8806 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8807 /* Inner IPv4 Destination IP */ 8808 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8809 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8810 /* Inner IP Protocol */ 8811 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8812 /* Inner IPv6 Source IP */ 8813 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8814 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8815 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8816 /* Inner IPv6 Destination IP */ 8817 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8818 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8819 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8820 /* Inner IPv6 Next Header */ 8821 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8822 /* Inner IPv6 Flow Label */ 8823 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8824 /* Inner TCP/UDP Source Port */ 8825 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8826 /* Inner TCP/UDP Destination Port */ 8827 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8828 8829 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8830 }; 8831 8832 /* reg_recr2_inner_header_fields_enable 8833 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8834 * Access: RW 8835 */ 8836 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8837 8838 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8839 { 8840 MLXSW_REG_ZERO(recr2, payload); 8841 mlxsw_reg_recr2_pp_set(payload, false); 8842 mlxsw_reg_recr2_sh_set(payload, true); 8843 mlxsw_reg_recr2_seed_set(payload, seed); 8844 } 8845 8846 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8847 * -------------------------------------------------------------- 8848 * The RMFT_V2 register is used to configure and query the multicast table. 8849 */ 8850 #define MLXSW_REG_RMFT2_ID 0x8027 8851 #define MLXSW_REG_RMFT2_LEN 0x174 8852 8853 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8854 8855 /* reg_rmft2_v 8856 * Valid 8857 * Access: RW 8858 */ 8859 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8860 8861 enum mlxsw_reg_rmft2_type { 8862 MLXSW_REG_RMFT2_TYPE_IPV4, 8863 MLXSW_REG_RMFT2_TYPE_IPV6 8864 }; 8865 8866 /* reg_rmft2_type 8867 * Access: Index 8868 */ 8869 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8870 8871 enum mlxsw_sp_reg_rmft2_op { 8872 /* For Write: 8873 * Write operation. Used to write a new entry to the table. All RW 8874 * fields are relevant for new entry. Activity bit is set for new 8875 * entries - Note write with v (Valid) 0 will delete the entry. 8876 * For Query: 8877 * Read operation 8878 */ 8879 MLXSW_REG_RMFT2_OP_READ_WRITE, 8880 }; 8881 8882 /* reg_rmft2_op 8883 * Operation. 8884 * Access: OP 8885 */ 8886 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8887 8888 /* reg_rmft2_a 8889 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8890 * entry. 8891 * Access: RO 8892 */ 8893 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8894 8895 /* reg_rmft2_offset 8896 * Offset within the multicast forwarding table to write to. 8897 * Access: Index 8898 */ 8899 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8900 8901 /* reg_rmft2_virtual_router 8902 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8903 * Access: RW 8904 */ 8905 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8906 8907 enum mlxsw_reg_rmft2_irif_mask { 8908 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8909 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8910 }; 8911 8912 /* reg_rmft2_irif_mask 8913 * Ingress RIF mask. 8914 * Access: RW 8915 */ 8916 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8917 8918 /* reg_rmft2_irif 8919 * Ingress RIF index. 8920 * Access: RW 8921 */ 8922 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8923 8924 /* reg_rmft2_dip{4,6} 8925 * Destination IPv4/6 address 8926 * Access: RW 8927 */ 8928 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8929 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8930 8931 /* reg_rmft2_dip{4,6}_mask 8932 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8933 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8934 * Access: RW 8935 */ 8936 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8937 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8938 8939 /* reg_rmft2_sip{4,6} 8940 * Source IPv4/6 address 8941 * Access: RW 8942 */ 8943 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8944 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8945 8946 /* reg_rmft2_sip{4,6}_mask 8947 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8948 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8949 * Access: RW 8950 */ 8951 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8952 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8953 8954 /* reg_rmft2_flexible_action_set 8955 * ACL action set. The only supported action types in this field and in any 8956 * action-set pointed from here are as follows: 8957 * 00h: ACTION_NULL 8958 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8959 * 03h: ACTION_TRAP 8960 * 06h: ACTION_QOS 8961 * 08h: ACTION_POLICING_MONITORING 8962 * 10h: ACTION_ROUTER_MC 8963 * Access: RW 8964 */ 8965 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8966 MLXSW_REG_FLEX_ACTION_SET_LEN); 8967 8968 static inline void 8969 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8970 u16 virtual_router, 8971 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8972 const char *flex_action_set) 8973 { 8974 MLXSW_REG_ZERO(rmft2, payload); 8975 mlxsw_reg_rmft2_v_set(payload, v); 8976 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8977 mlxsw_reg_rmft2_offset_set(payload, offset); 8978 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8979 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8980 mlxsw_reg_rmft2_irif_set(payload, irif); 8981 if (flex_action_set) 8982 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8983 flex_action_set); 8984 } 8985 8986 static inline void 8987 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8988 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8989 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8990 const char *flexible_action_set) 8991 { 8992 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8993 irif_mask, irif, flexible_action_set); 8994 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8995 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8996 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8997 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8998 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8999 } 9000 9001 static inline void 9002 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9003 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9004 struct in6_addr dip6, struct in6_addr dip6_mask, 9005 struct in6_addr sip6, struct in6_addr sip6_mask, 9006 const char *flexible_action_set) 9007 { 9008 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9009 irif_mask, irif, flexible_action_set); 9010 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9011 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9012 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9013 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9014 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9015 } 9016 9017 /* REIV - Router Egress Interface to VID Register 9018 * ---------------------------------------------- 9019 * The REIV register maps {eRIF, egress_port} -> VID. 9020 * This mapping is done at the egress, after the ACLs. 9021 * This mapping always takes effect after router, regardless of cast 9022 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9023 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9024 * Reserved when the RIF is a loopback RIF. 9025 * 9026 * Note: Reserved when legacy bridge model is used. 9027 */ 9028 #define MLXSW_REG_REIV_ID 0x8034 9029 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9030 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9031 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9032 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9033 MLXSW_REG_REIV_REC_LEN * \ 9034 MLXSW_REG_REIV_REC_MAX_COUNT) 9035 9036 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9037 9038 /* reg_reiv_port_page 9039 * Port page - elport_record[0] is 256*port_page. 9040 * Access: Index 9041 */ 9042 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9043 9044 /* reg_reiv_erif 9045 * Egress RIF. 9046 * Range is 0..cap_max_router_interfaces-1. 9047 * Access: Index 9048 */ 9049 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9050 9051 /* reg_reiv_rec_update 9052 * Update enable (when write): 9053 * 0 - Do not update the entry. 9054 * 1 - Update the entry. 9055 * Access: OP 9056 */ 9057 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9058 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9059 9060 /* reg_reiv_rec_evid 9061 * Egress VID. 9062 * Range is 0..4095. 9063 * Access: RW 9064 */ 9065 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9066 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9067 9068 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9069 { 9070 MLXSW_REG_ZERO(reiv, payload); 9071 mlxsw_reg_reiv_port_page_set(payload, port_page); 9072 mlxsw_reg_reiv_erif_set(payload, erif); 9073 } 9074 9075 /* MFCR - Management Fan Control Register 9076 * -------------------------------------- 9077 * This register controls the settings of the Fan Speed PWM mechanism. 9078 */ 9079 #define MLXSW_REG_MFCR_ID 0x9001 9080 #define MLXSW_REG_MFCR_LEN 0x08 9081 9082 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9083 9084 enum mlxsw_reg_mfcr_pwm_frequency { 9085 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9086 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9087 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9088 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9089 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9090 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9091 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9092 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9093 }; 9094 9095 /* reg_mfcr_pwm_frequency 9096 * Controls the frequency of the PWM signal. 9097 * Access: RW 9098 */ 9099 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9100 9101 #define MLXSW_MFCR_TACHOS_MAX 10 9102 9103 /* reg_mfcr_tacho_active 9104 * Indicates which of the tachometer is active (bit per tachometer). 9105 * Access: RO 9106 */ 9107 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9108 9109 #define MLXSW_MFCR_PWMS_MAX 5 9110 9111 /* reg_mfcr_pwm_active 9112 * Indicates which of the PWM control is active (bit per PWM). 9113 * Access: RO 9114 */ 9115 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9116 9117 static inline void 9118 mlxsw_reg_mfcr_pack(char *payload, 9119 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9120 { 9121 MLXSW_REG_ZERO(mfcr, payload); 9122 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9123 } 9124 9125 static inline void 9126 mlxsw_reg_mfcr_unpack(char *payload, 9127 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9128 u16 *p_tacho_active, u8 *p_pwm_active) 9129 { 9130 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9131 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9132 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9133 } 9134 9135 /* MFSC - Management Fan Speed Control Register 9136 * -------------------------------------------- 9137 * This register controls the settings of the Fan Speed PWM mechanism. 9138 */ 9139 #define MLXSW_REG_MFSC_ID 0x9002 9140 #define MLXSW_REG_MFSC_LEN 0x08 9141 9142 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9143 9144 /* reg_mfsc_pwm 9145 * Fan pwm to control / monitor. 9146 * Access: Index 9147 */ 9148 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9149 9150 /* reg_mfsc_pwm_duty_cycle 9151 * Controls the duty cycle of the PWM. Value range from 0..255 to 9152 * represent duty cycle of 0%...100%. 9153 * Access: RW 9154 */ 9155 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9156 9157 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9158 u8 pwm_duty_cycle) 9159 { 9160 MLXSW_REG_ZERO(mfsc, payload); 9161 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9162 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9163 } 9164 9165 /* MFSM - Management Fan Speed Measurement 9166 * --------------------------------------- 9167 * This register controls the settings of the Tacho measurements and 9168 * enables reading the Tachometer measurements. 9169 */ 9170 #define MLXSW_REG_MFSM_ID 0x9003 9171 #define MLXSW_REG_MFSM_LEN 0x08 9172 9173 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9174 9175 /* reg_mfsm_tacho 9176 * Fan tachometer index. 9177 * Access: Index 9178 */ 9179 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9180 9181 /* reg_mfsm_rpm 9182 * Fan speed (round per minute). 9183 * Access: RO 9184 */ 9185 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9186 9187 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9188 { 9189 MLXSW_REG_ZERO(mfsm, payload); 9190 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9191 } 9192 9193 /* MFSL - Management Fan Speed Limit Register 9194 * ------------------------------------------ 9195 * The Fan Speed Limit register is used to configure the fan speed 9196 * event / interrupt notification mechanism. Fan speed threshold are 9197 * defined for both under-speed and over-speed. 9198 */ 9199 #define MLXSW_REG_MFSL_ID 0x9004 9200 #define MLXSW_REG_MFSL_LEN 0x0C 9201 9202 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9203 9204 /* reg_mfsl_tacho 9205 * Fan tachometer index. 9206 * Access: Index 9207 */ 9208 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9209 9210 /* reg_mfsl_tach_min 9211 * Tachometer minimum value (minimum RPM). 9212 * Access: RW 9213 */ 9214 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9215 9216 /* reg_mfsl_tach_max 9217 * Tachometer maximum value (maximum RPM). 9218 * Access: RW 9219 */ 9220 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9221 9222 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9223 u16 tach_min, u16 tach_max) 9224 { 9225 MLXSW_REG_ZERO(mfsl, payload); 9226 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9227 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9228 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9229 } 9230 9231 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9232 u16 *p_tach_min, u16 *p_tach_max) 9233 { 9234 if (p_tach_min) 9235 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9236 9237 if (p_tach_max) 9238 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9239 } 9240 9241 /* FORE - Fan Out of Range Event Register 9242 * -------------------------------------- 9243 * This register reports the status of the controlled fans compared to the 9244 * range defined by the MFSL register. 9245 */ 9246 #define MLXSW_REG_FORE_ID 0x9007 9247 #define MLXSW_REG_FORE_LEN 0x0C 9248 9249 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9250 9251 /* fan_under_limit 9252 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9253 * to a single tachometer and indicates the specific tachometer reading is 9254 * below the threshold. 9255 * Access: RO 9256 */ 9257 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9258 9259 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9260 bool *fault) 9261 { 9262 u16 limit; 9263 9264 if (fault) { 9265 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9266 *fault = limit & BIT(tacho); 9267 } 9268 } 9269 9270 /* MTCAP - Management Temperature Capabilities 9271 * ------------------------------------------- 9272 * This register exposes the capabilities of the device and 9273 * system temperature sensing. 9274 */ 9275 #define MLXSW_REG_MTCAP_ID 0x9009 9276 #define MLXSW_REG_MTCAP_LEN 0x08 9277 9278 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9279 9280 /* reg_mtcap_sensor_count 9281 * Number of sensors supported by the device. 9282 * This includes the QSFP module sensors (if exists in the QSFP module). 9283 * Access: RO 9284 */ 9285 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9286 9287 /* MTMP - Management Temperature 9288 * ----------------------------- 9289 * This register controls the settings of the temperature measurements 9290 * and enables reading the temperature measurements. Note that temperature 9291 * is in 0.125 degrees Celsius. 9292 */ 9293 #define MLXSW_REG_MTMP_ID 0x900A 9294 #define MLXSW_REG_MTMP_LEN 0x20 9295 9296 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9297 9298 /* reg_mtmp_slot_index 9299 * Slot index (0: Main board). 9300 * Access: Index 9301 */ 9302 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9303 9304 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9305 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9306 /* reg_mtmp_sensor_index 9307 * Sensors index to access. 9308 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9309 * (module 0 is mapped to sensor_index 64). 9310 * Access: Index 9311 */ 9312 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9313 9314 /* Convert to milli degrees Celsius */ 9315 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9316 ((v_) >= 0) ? ((v_) * 125) : \ 9317 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9318 * 125)); }) 9319 9320 /* reg_mtmp_max_operational_temperature 9321 * The highest temperature in the nominal operational range. Reading is in 9322 * 0.125 Celsius degrees units. 9323 * In case of module this is SFF critical temperature threshold. 9324 * Access: RO 9325 */ 9326 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9327 9328 /* reg_mtmp_temperature 9329 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9330 * degrees units. 9331 * Access: RO 9332 */ 9333 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9334 9335 /* reg_mtmp_mte 9336 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9337 * Access: RW 9338 */ 9339 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9340 9341 /* reg_mtmp_mtr 9342 * Max Temperature Reset - clears the value of the max temperature register. 9343 * Access: WO 9344 */ 9345 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9346 9347 /* reg_mtmp_max_temperature 9348 * The highest measured temperature from the sensor. 9349 * When the bit mte is cleared, the field max_temperature is reserved. 9350 * Access: RO 9351 */ 9352 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9353 9354 /* reg_mtmp_tee 9355 * Temperature Event Enable. 9356 * 0 - Do not generate event 9357 * 1 - Generate event 9358 * 2 - Generate single event 9359 * Access: RW 9360 */ 9361 9362 enum mlxsw_reg_mtmp_tee { 9363 MLXSW_REG_MTMP_TEE_NO_EVENT, 9364 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9365 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9366 }; 9367 9368 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9369 9370 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9371 9372 /* reg_mtmp_temperature_threshold_hi 9373 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9374 * Access: RW 9375 */ 9376 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9377 9378 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9379 /* reg_mtmp_temperature_threshold_lo 9380 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9381 * Access: RW 9382 */ 9383 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9384 9385 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9386 9387 /* reg_mtmp_sensor_name 9388 * Sensor Name 9389 * Access: RO 9390 */ 9391 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9392 9393 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9394 u16 sensor_index, bool max_temp_enable, 9395 bool max_temp_reset) 9396 { 9397 MLXSW_REG_ZERO(mtmp, payload); 9398 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9399 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9400 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9401 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9402 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9403 MLXSW_REG_MTMP_THRESH_HI); 9404 } 9405 9406 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9407 int *p_max_temp, int *p_temp_hi, 9408 int *p_max_oper_temp, 9409 char *sensor_name) 9410 { 9411 s16 temp; 9412 9413 if (p_temp) { 9414 temp = mlxsw_reg_mtmp_temperature_get(payload); 9415 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9416 } 9417 if (p_max_temp) { 9418 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9419 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9420 } 9421 if (p_temp_hi) { 9422 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9423 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9424 } 9425 if (p_max_oper_temp) { 9426 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9427 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9428 } 9429 if (sensor_name) 9430 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9431 } 9432 9433 /* MTWE - Management Temperature Warning Event 9434 * ------------------------------------------- 9435 * This register is used for over temperature warning. 9436 */ 9437 #define MLXSW_REG_MTWE_ID 0x900B 9438 #define MLXSW_REG_MTWE_LEN 0x10 9439 9440 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9441 9442 /* reg_mtwe_sensor_warning 9443 * Bit vector indicating which of the sensor reading is above threshold. 9444 * Address 00h bit31 is sensor_warning[127]. 9445 * Address 0Ch bit0 is sensor_warning[0]. 9446 * Access: RO 9447 */ 9448 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9449 9450 /* MTBR - Management Temperature Bulk Register 9451 * ------------------------------------------- 9452 * This register is used for bulk temperature reading. 9453 */ 9454 #define MLXSW_REG_MTBR_ID 0x900F 9455 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9456 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9457 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9458 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9459 MLXSW_REG_MTBR_REC_LEN * \ 9460 MLXSW_REG_MTBR_REC_MAX_COUNT) 9461 9462 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9463 9464 /* reg_mtbr_slot_index 9465 * Slot index (0: Main board). 9466 * Access: Index 9467 */ 9468 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9469 9470 /* reg_mtbr_base_sensor_index 9471 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9472 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9473 * Access: Index 9474 */ 9475 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9476 9477 /* reg_mtbr_num_rec 9478 * Request: Number of records to read 9479 * Response: Number of records read 9480 * See above description for more details. 9481 * Range 1..255 9482 * Access: RW 9483 */ 9484 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9485 9486 /* reg_mtbr_rec_max_temp 9487 * The highest measured temperature from the sensor. 9488 * When the bit mte is cleared, the field max_temperature is reserved. 9489 * Access: RO 9490 */ 9491 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9492 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9493 9494 /* reg_mtbr_rec_temp 9495 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9496 * degrees units. 9497 * Access: RO 9498 */ 9499 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9500 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9501 9502 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9503 u16 base_sensor_index, u8 num_rec) 9504 { 9505 MLXSW_REG_ZERO(mtbr, payload); 9506 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9507 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9508 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9509 } 9510 9511 /* Error codes from temperatute reading */ 9512 enum mlxsw_reg_mtbr_temp_status { 9513 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9514 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9515 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9516 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9517 }; 9518 9519 /* Base index for reading modules temperature */ 9520 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9521 9522 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9523 u16 *p_temp, u16 *p_max_temp) 9524 { 9525 if (p_temp) 9526 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9527 if (p_max_temp) 9528 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9529 } 9530 9531 /* MCIA - Management Cable Info Access 9532 * ----------------------------------- 9533 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9534 */ 9535 9536 #define MLXSW_REG_MCIA_ID 0x9014 9537 #define MLXSW_REG_MCIA_LEN 0x40 9538 9539 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9540 9541 /* reg_mcia_l 9542 * Lock bit. Setting this bit will lock the access to the specific 9543 * cable. Used for updating a full page in a cable EPROM. Any access 9544 * other then subsequence writes will fail while the port is locked. 9545 * Access: RW 9546 */ 9547 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9548 9549 /* reg_mcia_module 9550 * Module number. 9551 * Access: Index 9552 */ 9553 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9554 9555 /* reg_mcia_slot_index 9556 * Slot index (0: Main board) 9557 * Access: Index 9558 */ 9559 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9560 9561 enum { 9562 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9563 /* No response from module's EEPROM. */ 9564 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9565 /* Module type not supported by the device. */ 9566 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9567 /* No module present indication. */ 9568 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9569 /* Error occurred while trying to access module's EEPROM using I2C. */ 9570 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9571 /* Module is disabled. */ 9572 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9573 }; 9574 9575 /* reg_mcia_status 9576 * Module status. 9577 * Access: RO 9578 */ 9579 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9580 9581 /* reg_mcia_i2c_device_address 9582 * I2C device address. 9583 * Access: RW 9584 */ 9585 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9586 9587 /* reg_mcia_page_number 9588 * Page number. 9589 * Access: RW 9590 */ 9591 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9592 9593 /* reg_mcia_device_address 9594 * Device address. 9595 * Access: RW 9596 */ 9597 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9598 9599 /* reg_mcia_bank_number 9600 * Bank number. 9601 * Access: Index 9602 */ 9603 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9604 9605 /* reg_mcia_size 9606 * Number of bytes to read/write (up to 48 bytes). 9607 * Access: RW 9608 */ 9609 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9610 9611 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9612 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9613 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9614 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9615 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9616 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9617 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9618 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9619 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9620 #define MLXSW_REG_MCIA_PAGE0_LO 0 9621 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9622 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9623 9624 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9625 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9626 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9627 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9628 }; 9629 9630 enum mlxsw_reg_mcia_eeprom_module_info_id { 9631 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9632 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9633 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9634 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9635 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9636 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9637 }; 9638 9639 enum mlxsw_reg_mcia_eeprom_module_info { 9640 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9641 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9642 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9643 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9644 }; 9645 9646 /* reg_mcia_eeprom 9647 * Bytes to read/write. 9648 * Access: RW 9649 */ 9650 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9651 9652 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9653 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9654 * on offset 384 through 511, page 3 - on offset 512 through 639. 9655 */ 9656 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9657 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9658 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9659 9660 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9661 u8 lock, u8 page_number, 9662 u16 device_addr, u8 size, 9663 u8 i2c_device_addr) 9664 { 9665 MLXSW_REG_ZERO(mcia, payload); 9666 mlxsw_reg_mcia_slot_set(payload, slot_index); 9667 mlxsw_reg_mcia_module_set(payload, module); 9668 mlxsw_reg_mcia_l_set(payload, lock); 9669 mlxsw_reg_mcia_page_number_set(payload, page_number); 9670 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9671 mlxsw_reg_mcia_size_set(payload, size); 9672 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9673 } 9674 9675 /* MPAT - Monitoring Port Analyzer Table 9676 * ------------------------------------- 9677 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9678 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9679 */ 9680 #define MLXSW_REG_MPAT_ID 0x901A 9681 #define MLXSW_REG_MPAT_LEN 0x78 9682 9683 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9684 9685 /* reg_mpat_pa_id 9686 * Port Analyzer ID. 9687 * Access: Index 9688 */ 9689 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9690 9691 /* reg_mpat_session_id 9692 * Mirror Session ID. 9693 * Used for MIRROR_SESSION<i> trap. 9694 * Access: RW 9695 */ 9696 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9697 9698 /* reg_mpat_system_port 9699 * A unique port identifier for the final destination of the packet. 9700 * Access: RW 9701 */ 9702 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9703 9704 /* reg_mpat_e 9705 * Enable. Indicating the Port Analyzer is enabled. 9706 * Access: RW 9707 */ 9708 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9709 9710 /* reg_mpat_qos 9711 * Quality Of Service Mode. 9712 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9713 * PCP, DEI, DSCP or VL) are configured. 9714 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9715 * same as in the original packet that has triggered the mirroring. For 9716 * SPAN also the pcp,dei are maintained. 9717 * Access: RW 9718 */ 9719 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9720 9721 /* reg_mpat_be 9722 * Best effort mode. Indicates mirroring traffic should not cause packet 9723 * drop or back pressure, but will discard the mirrored packets. Mirrored 9724 * packets will be forwarded on a best effort manner. 9725 * 0: Do not discard mirrored packets 9726 * 1: Discard mirrored packets if causing congestion 9727 * Access: RW 9728 */ 9729 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9730 9731 enum mlxsw_reg_mpat_span_type { 9732 /* Local SPAN Ethernet. 9733 * The original packet is not encapsulated. 9734 */ 9735 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9736 9737 /* Remote SPAN Ethernet VLAN. 9738 * The packet is forwarded to the monitoring port on the monitoring 9739 * VLAN. 9740 */ 9741 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9742 9743 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9744 * The packet is encapsulated with GRE header. 9745 */ 9746 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9747 }; 9748 9749 /* reg_mpat_span_type 9750 * SPAN type. 9751 * Access: RW 9752 */ 9753 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9754 9755 /* reg_mpat_pide 9756 * Policer enable. 9757 * Access: RW 9758 */ 9759 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9760 9761 /* reg_mpat_pid 9762 * Policer ID. 9763 * Access: RW 9764 */ 9765 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9766 9767 /* Remote SPAN - Ethernet VLAN 9768 * - - - - - - - - - - - - - - 9769 */ 9770 9771 /* reg_mpat_eth_rspan_vid 9772 * Encapsulation header VLAN ID. 9773 * Access: RW 9774 */ 9775 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9776 9777 /* Encapsulated Remote SPAN - Ethernet L2 9778 * - - - - - - - - - - - - - - - - - - - 9779 */ 9780 9781 enum mlxsw_reg_mpat_eth_rspan_version { 9782 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9783 }; 9784 9785 /* reg_mpat_eth_rspan_version 9786 * RSPAN mirror header version. 9787 * Access: RW 9788 */ 9789 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9790 9791 /* reg_mpat_eth_rspan_mac 9792 * Destination MAC address. 9793 * Access: RW 9794 */ 9795 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9796 9797 /* reg_mpat_eth_rspan_tp 9798 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9799 * Access: RW 9800 */ 9801 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9802 9803 /* Encapsulated Remote SPAN - Ethernet L3 9804 * - - - - - - - - - - - - - - - - - - - 9805 */ 9806 9807 enum mlxsw_reg_mpat_eth_rspan_protocol { 9808 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9809 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9810 }; 9811 9812 /* reg_mpat_eth_rspan_protocol 9813 * SPAN encapsulation protocol. 9814 * Access: RW 9815 */ 9816 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9817 9818 /* reg_mpat_eth_rspan_ttl 9819 * Encapsulation header Time-to-Live/HopLimit. 9820 * Access: RW 9821 */ 9822 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9823 9824 /* reg_mpat_eth_rspan_smac 9825 * Source MAC address 9826 * Access: RW 9827 */ 9828 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9829 9830 /* reg_mpat_eth_rspan_dip* 9831 * Destination IP address. The IP version is configured by protocol. 9832 * Access: RW 9833 */ 9834 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9835 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9836 9837 /* reg_mpat_eth_rspan_sip* 9838 * Source IP address. The IP version is configured by protocol. 9839 * Access: RW 9840 */ 9841 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9842 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9843 9844 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9845 u16 system_port, bool e, 9846 enum mlxsw_reg_mpat_span_type span_type) 9847 { 9848 MLXSW_REG_ZERO(mpat, payload); 9849 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9850 mlxsw_reg_mpat_system_port_set(payload, system_port); 9851 mlxsw_reg_mpat_e_set(payload, e); 9852 mlxsw_reg_mpat_qos_set(payload, 1); 9853 mlxsw_reg_mpat_be_set(payload, 1); 9854 mlxsw_reg_mpat_span_type_set(payload, span_type); 9855 } 9856 9857 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9858 { 9859 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9860 } 9861 9862 static inline void 9863 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9864 enum mlxsw_reg_mpat_eth_rspan_version version, 9865 const char *mac, 9866 bool tp) 9867 { 9868 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9869 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9870 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9871 } 9872 9873 static inline void 9874 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9875 const char *smac, 9876 u32 sip, u32 dip) 9877 { 9878 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9879 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9880 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9881 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9882 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9883 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9884 } 9885 9886 static inline void 9887 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9888 const char *smac, 9889 struct in6_addr sip, struct in6_addr dip) 9890 { 9891 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9892 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9893 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9894 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9895 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9896 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9897 } 9898 9899 /* MPAR - Monitoring Port Analyzer Register 9900 * ---------------------------------------- 9901 * MPAR register is used to query and configure the port analyzer port mirroring 9902 * properties. 9903 */ 9904 #define MLXSW_REG_MPAR_ID 0x901B 9905 #define MLXSW_REG_MPAR_LEN 0x0C 9906 9907 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9908 9909 /* reg_mpar_local_port 9910 * The local port to mirror the packets from. 9911 * Access: Index 9912 */ 9913 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 9914 9915 enum mlxsw_reg_mpar_i_e { 9916 MLXSW_REG_MPAR_TYPE_EGRESS, 9917 MLXSW_REG_MPAR_TYPE_INGRESS, 9918 }; 9919 9920 /* reg_mpar_i_e 9921 * Ingress/Egress 9922 * Access: Index 9923 */ 9924 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9925 9926 /* reg_mpar_enable 9927 * Enable mirroring 9928 * By default, port mirroring is disabled for all ports. 9929 * Access: RW 9930 */ 9931 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9932 9933 /* reg_mpar_pa_id 9934 * Port Analyzer ID. 9935 * Access: RW 9936 */ 9937 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9938 9939 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 9940 9941 /* reg_mpar_probability_rate 9942 * Sampling rate. 9943 * Valid values are: 1 to 3.5*10^9 9944 * Value of 1 means "sample all". Default is 1. 9945 * Reserved when Spectrum-1. 9946 * Access: RW 9947 */ 9948 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 9949 9950 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 9951 enum mlxsw_reg_mpar_i_e i_e, 9952 bool enable, u8 pa_id, 9953 u32 probability_rate) 9954 { 9955 MLXSW_REG_ZERO(mpar, payload); 9956 mlxsw_reg_mpar_local_port_set(payload, local_port); 9957 mlxsw_reg_mpar_enable_set(payload, enable); 9958 mlxsw_reg_mpar_i_e_set(payload, i_e); 9959 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9960 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 9961 } 9962 9963 /* MGIR - Management General Information Register 9964 * ---------------------------------------------- 9965 * MGIR register allows software to query the hardware and firmware general 9966 * information. 9967 */ 9968 #define MLXSW_REG_MGIR_ID 0x9020 9969 #define MLXSW_REG_MGIR_LEN 0x9C 9970 9971 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 9972 9973 /* reg_mgir_hw_info_device_hw_revision 9974 * Access: RO 9975 */ 9976 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 9977 9978 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 9979 9980 /* reg_mgir_fw_info_psid 9981 * PSID (ASCII string). 9982 * Access: RO 9983 */ 9984 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 9985 9986 /* reg_mgir_fw_info_extended_major 9987 * Access: RO 9988 */ 9989 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 9990 9991 /* reg_mgir_fw_info_extended_minor 9992 * Access: RO 9993 */ 9994 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 9995 9996 /* reg_mgir_fw_info_extended_sub_minor 9997 * Access: RO 9998 */ 9999 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10000 10001 static inline void mlxsw_reg_mgir_pack(char *payload) 10002 { 10003 MLXSW_REG_ZERO(mgir, payload); 10004 } 10005 10006 static inline void 10007 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10008 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10009 { 10010 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10011 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10012 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10013 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10014 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10015 } 10016 10017 /* MRSR - Management Reset and Shutdown Register 10018 * --------------------------------------------- 10019 * MRSR register is used to reset or shutdown the switch or 10020 * the entire system (when applicable). 10021 */ 10022 #define MLXSW_REG_MRSR_ID 0x9023 10023 #define MLXSW_REG_MRSR_LEN 0x08 10024 10025 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10026 10027 /* reg_mrsr_command 10028 * Reset/shutdown command 10029 * 0 - do nothing 10030 * 1 - software reset 10031 * Access: WO 10032 */ 10033 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10034 10035 static inline void mlxsw_reg_mrsr_pack(char *payload) 10036 { 10037 MLXSW_REG_ZERO(mrsr, payload); 10038 mlxsw_reg_mrsr_command_set(payload, 1); 10039 } 10040 10041 /* MLCR - Management LED Control Register 10042 * -------------------------------------- 10043 * Controls the system LEDs. 10044 */ 10045 #define MLXSW_REG_MLCR_ID 0x902B 10046 #define MLXSW_REG_MLCR_LEN 0x0C 10047 10048 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10049 10050 /* reg_mlcr_local_port 10051 * Local port number. 10052 * Access: RW 10053 */ 10054 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10055 10056 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10057 10058 /* reg_mlcr_beacon_duration 10059 * Duration of the beacon to be active, in seconds. 10060 * 0x0 - Will turn off the beacon. 10061 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10062 * Access: RW 10063 */ 10064 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10065 10066 /* reg_mlcr_beacon_remain 10067 * Remaining duration of the beacon, in seconds. 10068 * 0xFFFF indicates an infinite amount of time. 10069 * Access: RO 10070 */ 10071 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10072 10073 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10074 bool active) 10075 { 10076 MLXSW_REG_ZERO(mlcr, payload); 10077 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10078 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10079 MLXSW_REG_MLCR_DURATION_MAX : 0); 10080 } 10081 10082 /* MCION - Management Cable IO and Notifications Register 10083 * ------------------------------------------------------ 10084 * The MCION register is used to query transceiver modules' IO pins and other 10085 * notifications. 10086 */ 10087 #define MLXSW_REG_MCION_ID 0x9052 10088 #define MLXSW_REG_MCION_LEN 0x18 10089 10090 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10091 10092 /* reg_mcion_module 10093 * Module number. 10094 * Access: Index 10095 */ 10096 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10097 10098 /* reg_mcion_slot_index 10099 * Slot index. 10100 * Access: Index 10101 */ 10102 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10103 10104 enum { 10105 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10106 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10107 }; 10108 10109 /* reg_mcion_module_status_bits 10110 * Module IO status as defined by SFF. 10111 * Access: RO 10112 */ 10113 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10114 10115 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10116 { 10117 MLXSW_REG_ZERO(mcion, payload); 10118 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10119 mlxsw_reg_mcion_module_set(payload, module); 10120 } 10121 10122 /* MTPPS - Management Pulse Per Second Register 10123 * -------------------------------------------- 10124 * This register provides the device PPS capabilities, configure the PPS in and 10125 * out modules and holds the PPS in time stamp. 10126 */ 10127 #define MLXSW_REG_MTPPS_ID 0x9053 10128 #define MLXSW_REG_MTPPS_LEN 0x3C 10129 10130 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10131 10132 /* reg_mtpps_enable 10133 * Enables the PPS functionality the specific pin. 10134 * A boolean variable. 10135 * Access: RW 10136 */ 10137 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10138 10139 enum mlxsw_reg_mtpps_pin_mode { 10140 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10141 }; 10142 10143 /* reg_mtpps_pin_mode 10144 * Pin mode to be used. The mode must comply with the supported modes of the 10145 * requested pin. 10146 * Access: RW 10147 */ 10148 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10149 10150 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10151 10152 /* reg_mtpps_pin 10153 * Pin to be configured or queried out of the supported pins. 10154 * Access: Index 10155 */ 10156 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10157 10158 /* reg_mtpps_time_stamp 10159 * When pin_mode = pps_in, the latched device time when it was triggered from 10160 * the external GPIO pin. 10161 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10162 * time to generate next output signal. 10163 * Time is in units of device clock. 10164 * Access: RW 10165 */ 10166 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10167 10168 static inline void 10169 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10170 { 10171 MLXSW_REG_ZERO(mtpps, payload); 10172 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10173 mlxsw_reg_mtpps_pin_mode_set(payload, 10174 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10175 mlxsw_reg_mtpps_enable_set(payload, true); 10176 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10177 } 10178 10179 /* MTUTC - Management UTC Register 10180 * ------------------------------- 10181 * Configures the HW UTC counter. 10182 */ 10183 #define MLXSW_REG_MTUTC_ID 0x9055 10184 #define MLXSW_REG_MTUTC_LEN 0x1C 10185 10186 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10187 10188 enum mlxsw_reg_mtutc_operation { 10189 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10190 MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, 10191 MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2, 10192 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10193 }; 10194 10195 /* reg_mtutc_operation 10196 * Operation. 10197 * Access: OP 10198 */ 10199 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10200 10201 /* reg_mtutc_freq_adjustment 10202 * Frequency adjustment: Every PPS the HW frequency will be 10203 * adjusted by this value. Units of HW clock, where HW counts 10204 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. 10205 * In Spectrum-2, the field is reversed, positive values mean to decrease the 10206 * frequency. 10207 * Access: RW 10208 */ 10209 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10210 10211 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000) 10212 10213 /* reg_mtutc_utc_sec 10214 * UTC seconds. 10215 * Access: WO 10216 */ 10217 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10218 10219 /* reg_mtutc_utc_nsec 10220 * UTC nSecs. 10221 * Range 0..(10^9-1) 10222 * Updated when operation is SET_TIME_IMMEDIATE. 10223 * Reserved on Spectrum-1. 10224 * Access: WO 10225 */ 10226 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30); 10227 10228 /* reg_mtutc_time_adjustment 10229 * Time adjustment. 10230 * Units of nSec. 10231 * Range is from -32768 to +32767. 10232 * Updated when operation is ADJUST_TIME. 10233 * Reserved on Spectrum-1. 10234 * Access: WO 10235 */ 10236 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32); 10237 10238 static inline void 10239 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10240 u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj) 10241 { 10242 MLXSW_REG_ZERO(mtutc, payload); 10243 mlxsw_reg_mtutc_operation_set(payload, oper); 10244 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10245 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10246 mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec); 10247 mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj); 10248 } 10249 10250 /* MCQI - Management Component Query Information 10251 * --------------------------------------------- 10252 * This register allows querying information about firmware components. 10253 */ 10254 #define MLXSW_REG_MCQI_ID 0x9061 10255 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10256 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10257 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10258 10259 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10260 10261 /* reg_mcqi_component_index 10262 * Index of the accessed component. 10263 * Access: Index 10264 */ 10265 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10266 10267 enum mlxfw_reg_mcqi_info_type { 10268 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10269 }; 10270 10271 /* reg_mcqi_info_type 10272 * Component properties set. 10273 * Access: RW 10274 */ 10275 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10276 10277 /* reg_mcqi_offset 10278 * The requested/returned data offset from the section start, given in bytes. 10279 * Must be DWORD aligned. 10280 * Access: RW 10281 */ 10282 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10283 10284 /* reg_mcqi_data_size 10285 * The requested/returned data size, given in bytes. If data_size is not DWORD 10286 * aligned, the last bytes are zero padded. 10287 * Access: RW 10288 */ 10289 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10290 10291 /* reg_mcqi_cap_max_component_size 10292 * Maximum size for this component, given in bytes. 10293 * Access: RO 10294 */ 10295 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10296 10297 /* reg_mcqi_cap_log_mcda_word_size 10298 * Log 2 of the access word size in bytes. Read and write access must be aligned 10299 * to the word size. Write access must be done for an integer number of words. 10300 * Access: RO 10301 */ 10302 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10303 10304 /* reg_mcqi_cap_mcda_max_write_size 10305 * Maximal write size for MCDA register 10306 * Access: RO 10307 */ 10308 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10309 10310 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10311 { 10312 MLXSW_REG_ZERO(mcqi, payload); 10313 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10314 mlxsw_reg_mcqi_info_type_set(payload, 10315 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10316 mlxsw_reg_mcqi_offset_set(payload, 0); 10317 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10318 } 10319 10320 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10321 u32 *p_cap_max_component_size, 10322 u8 *p_cap_log_mcda_word_size, 10323 u16 *p_cap_mcda_max_write_size) 10324 { 10325 *p_cap_max_component_size = 10326 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10327 *p_cap_log_mcda_word_size = 10328 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10329 *p_cap_mcda_max_write_size = 10330 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10331 } 10332 10333 /* MCC - Management Component Control 10334 * ---------------------------------- 10335 * Controls the firmware component and updates the FSM. 10336 */ 10337 #define MLXSW_REG_MCC_ID 0x9062 10338 #define MLXSW_REG_MCC_LEN 0x1C 10339 10340 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10341 10342 enum mlxsw_reg_mcc_instruction { 10343 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10344 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10345 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10346 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10347 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10348 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10349 }; 10350 10351 /* reg_mcc_instruction 10352 * Command to be executed by the FSM. 10353 * Applicable for write operation only. 10354 * Access: RW 10355 */ 10356 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10357 10358 /* reg_mcc_component_index 10359 * Index of the accessed component. Applicable only for commands that 10360 * refer to components. Otherwise, this field is reserved. 10361 * Access: Index 10362 */ 10363 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10364 10365 /* reg_mcc_update_handle 10366 * Token representing the current flow executed by the FSM. 10367 * Access: WO 10368 */ 10369 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10370 10371 /* reg_mcc_error_code 10372 * Indicates the successful completion of the instruction, or the reason it 10373 * failed 10374 * Access: RO 10375 */ 10376 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10377 10378 /* reg_mcc_control_state 10379 * Current FSM state 10380 * Access: RO 10381 */ 10382 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10383 10384 /* reg_mcc_component_size 10385 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10386 * the size may shorten the update time. Value 0x0 means that size is 10387 * unspecified. 10388 * Access: WO 10389 */ 10390 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10391 10392 static inline void mlxsw_reg_mcc_pack(char *payload, 10393 enum mlxsw_reg_mcc_instruction instr, 10394 u16 component_index, u32 update_handle, 10395 u32 component_size) 10396 { 10397 MLXSW_REG_ZERO(mcc, payload); 10398 mlxsw_reg_mcc_instruction_set(payload, instr); 10399 mlxsw_reg_mcc_component_index_set(payload, component_index); 10400 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10401 mlxsw_reg_mcc_component_size_set(payload, component_size); 10402 } 10403 10404 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10405 u8 *p_error_code, u8 *p_control_state) 10406 { 10407 if (p_update_handle) 10408 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10409 if (p_error_code) 10410 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10411 if (p_control_state) 10412 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10413 } 10414 10415 /* MCDA - Management Component Data Access 10416 * --------------------------------------- 10417 * This register allows reading and writing a firmware component. 10418 */ 10419 #define MLXSW_REG_MCDA_ID 0x9063 10420 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10421 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10422 #define MLXSW_REG_MCDA_LEN \ 10423 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10424 10425 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10426 10427 /* reg_mcda_update_handle 10428 * Token representing the current flow executed by the FSM. 10429 * Access: RW 10430 */ 10431 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10432 10433 /* reg_mcda_offset 10434 * Offset of accessed address relative to component start. Accesses must be in 10435 * accordance to log_mcda_word_size in MCQI reg. 10436 * Access: RW 10437 */ 10438 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10439 10440 /* reg_mcda_size 10441 * Size of the data accessed, given in bytes. 10442 * Access: RW 10443 */ 10444 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10445 10446 /* reg_mcda_data 10447 * Data block accessed. 10448 * Access: RW 10449 */ 10450 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10451 10452 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10453 u32 offset, u16 size, u8 *data) 10454 { 10455 int i; 10456 10457 MLXSW_REG_ZERO(mcda, payload); 10458 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10459 mlxsw_reg_mcda_offset_set(payload, offset); 10460 mlxsw_reg_mcda_size_set(payload, size); 10461 10462 for (i = 0; i < size / 4; i++) 10463 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10464 } 10465 10466 /* MPSC - Monitoring Packet Sampling Configuration Register 10467 * -------------------------------------------------------- 10468 * MPSC Register is used to configure the Packet Sampling mechanism. 10469 */ 10470 #define MLXSW_REG_MPSC_ID 0x9080 10471 #define MLXSW_REG_MPSC_LEN 0x1C 10472 10473 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10474 10475 /* reg_mpsc_local_port 10476 * Local port number 10477 * Not supported for CPU port 10478 * Access: Index 10479 */ 10480 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10481 10482 /* reg_mpsc_e 10483 * Enable sampling on port local_port 10484 * Access: RW 10485 */ 10486 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10487 10488 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10489 10490 /* reg_mpsc_rate 10491 * Sampling rate = 1 out of rate packets (with randomization around 10492 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10493 * Access: RW 10494 */ 10495 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10496 10497 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10498 u32 rate) 10499 { 10500 MLXSW_REG_ZERO(mpsc, payload); 10501 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10502 mlxsw_reg_mpsc_e_set(payload, e); 10503 mlxsw_reg_mpsc_rate_set(payload, rate); 10504 } 10505 10506 /* MGPC - Monitoring General Purpose Counter Set Register 10507 * The MGPC register retrieves and sets the General Purpose Counter Set. 10508 */ 10509 #define MLXSW_REG_MGPC_ID 0x9081 10510 #define MLXSW_REG_MGPC_LEN 0x18 10511 10512 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10513 10514 /* reg_mgpc_counter_set_type 10515 * Counter set type. 10516 * Access: OP 10517 */ 10518 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10519 10520 /* reg_mgpc_counter_index 10521 * Counter index. 10522 * Access: Index 10523 */ 10524 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10525 10526 enum mlxsw_reg_mgpc_opcode { 10527 /* Nop */ 10528 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10529 /* Clear counters */ 10530 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10531 }; 10532 10533 /* reg_mgpc_opcode 10534 * Opcode. 10535 * Access: OP 10536 */ 10537 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10538 10539 /* reg_mgpc_byte_counter 10540 * Byte counter value. 10541 * Access: RW 10542 */ 10543 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10544 10545 /* reg_mgpc_packet_counter 10546 * Packet counter value. 10547 * Access: RW 10548 */ 10549 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10550 10551 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10552 enum mlxsw_reg_mgpc_opcode opcode, 10553 enum mlxsw_reg_flow_counter_set_type set_type) 10554 { 10555 MLXSW_REG_ZERO(mgpc, payload); 10556 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10557 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10558 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10559 } 10560 10561 /* MPRS - Monitoring Parsing State Register 10562 * ---------------------------------------- 10563 * The MPRS register is used for setting up the parsing for hash, 10564 * policy-engine and routing. 10565 */ 10566 #define MLXSW_REG_MPRS_ID 0x9083 10567 #define MLXSW_REG_MPRS_LEN 0x14 10568 10569 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10570 10571 /* reg_mprs_parsing_depth 10572 * Minimum parsing depth. 10573 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10574 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10575 * Access: RW 10576 */ 10577 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10578 10579 /* reg_mprs_parsing_en 10580 * Parsing enable. 10581 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10582 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10583 * Access: RW 10584 */ 10585 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10586 10587 /* reg_mprs_vxlan_udp_dport 10588 * VxLAN UDP destination port. 10589 * Used for identifying VxLAN packets and for dport field in 10590 * encapsulation. Default is 4789. 10591 * Access: RW 10592 */ 10593 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10594 10595 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10596 u16 vxlan_udp_dport) 10597 { 10598 MLXSW_REG_ZERO(mprs, payload); 10599 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10600 mlxsw_reg_mprs_parsing_en_set(payload, true); 10601 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10602 } 10603 10604 /* MOGCR - Monitoring Global Configuration Register 10605 * ------------------------------------------------ 10606 */ 10607 #define MLXSW_REG_MOGCR_ID 0x9086 10608 #define MLXSW_REG_MOGCR_LEN 0x20 10609 10610 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10611 10612 /* reg_mogcr_ptp_iftc 10613 * PTP Ingress FIFO Trap Clear 10614 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10615 * to this value. Default 0. 10616 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10617 * Access: RW 10618 */ 10619 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10620 10621 /* reg_mogcr_ptp_eftc 10622 * PTP Egress FIFO Trap Clear 10623 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10624 * to this value. Default 0. 10625 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10626 * Access: RW 10627 */ 10628 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10629 10630 /* reg_mogcr_mirroring_pid_base 10631 * Base policer id for mirroring policers. 10632 * Must have an even value (e.g. 1000, not 1001). 10633 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10634 * Access: RW 10635 */ 10636 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10637 10638 /* MPAGR - Monitoring Port Analyzer Global Register 10639 * ------------------------------------------------ 10640 * This register is used for global port analyzer configurations. 10641 * Note: This register is not supported by current FW versions for Spectrum-1. 10642 */ 10643 #define MLXSW_REG_MPAGR_ID 0x9089 10644 #define MLXSW_REG_MPAGR_LEN 0x0C 10645 10646 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10647 10648 enum mlxsw_reg_mpagr_trigger { 10649 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10650 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10651 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10652 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10653 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10654 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10655 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10656 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10657 }; 10658 10659 /* reg_mpagr_trigger 10660 * Mirror trigger. 10661 * Access: Index 10662 */ 10663 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10664 10665 /* reg_mpagr_pa_id 10666 * Port analyzer ID. 10667 * Access: RW 10668 */ 10669 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10670 10671 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10672 10673 /* reg_mpagr_probability_rate 10674 * Sampling rate. 10675 * Valid values are: 1 to 3.5*10^9 10676 * Value of 1 means "sample all". Default is 1. 10677 * Access: RW 10678 */ 10679 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10680 10681 static inline void mlxsw_reg_mpagr_pack(char *payload, 10682 enum mlxsw_reg_mpagr_trigger trigger, 10683 u8 pa_id, u32 probability_rate) 10684 { 10685 MLXSW_REG_ZERO(mpagr, payload); 10686 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10687 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10688 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10689 } 10690 10691 /* MOMTE - Monitoring Mirror Trigger Enable Register 10692 * ------------------------------------------------- 10693 * This register is used to configure the mirror enable for different mirror 10694 * reasons. 10695 */ 10696 #define MLXSW_REG_MOMTE_ID 0x908D 10697 #define MLXSW_REG_MOMTE_LEN 0x10 10698 10699 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10700 10701 /* reg_momte_local_port 10702 * Local port number. 10703 * Access: Index 10704 */ 10705 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10706 10707 enum mlxsw_reg_momte_type { 10708 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10709 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10710 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10711 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10712 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10713 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10714 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10715 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10716 }; 10717 10718 /* reg_momte_type 10719 * Type of mirroring. 10720 * Access: Index 10721 */ 10722 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10723 10724 /* reg_momte_tclass_en 10725 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10726 * 0: disable (default) 10727 * 1: enable 10728 * Access: RW 10729 */ 10730 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10731 10732 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10733 enum mlxsw_reg_momte_type type) 10734 { 10735 MLXSW_REG_ZERO(momte, payload); 10736 mlxsw_reg_momte_local_port_set(payload, local_port); 10737 mlxsw_reg_momte_type_set(payload, type); 10738 } 10739 10740 /* MTPPPC - Time Precision Packet Port Configuration 10741 * ------------------------------------------------- 10742 * This register serves for configuration of which PTP messages should be 10743 * timestamped. This is a global configuration, despite the register name. 10744 * 10745 * Reserved when Spectrum-2. 10746 */ 10747 #define MLXSW_REG_MTPPPC_ID 0x9090 10748 #define MLXSW_REG_MTPPPC_LEN 0x28 10749 10750 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10751 10752 /* reg_mtpppc_ing_timestamp_message_type 10753 * Bitwise vector of PTP message types to timestamp at ingress. 10754 * MessageType field as defined by IEEE 1588 10755 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10756 * Default all 0 10757 * Access: RW 10758 */ 10759 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10760 10761 /* reg_mtpppc_egr_timestamp_message_type 10762 * Bitwise vector of PTP message types to timestamp at egress. 10763 * MessageType field as defined by IEEE 1588 10764 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10765 * Default all 0 10766 * Access: RW 10767 */ 10768 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10769 10770 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10771 { 10772 MLXSW_REG_ZERO(mtpppc, payload); 10773 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10774 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10775 } 10776 10777 /* MTPPTR - Time Precision Packet Timestamping Reading 10778 * --------------------------------------------------- 10779 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10780 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10781 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10782 * trapped. The sequence number is used to synchronize the timestamp FIFO 10783 * entries and the trapped packets. 10784 * Reserved when Spectrum-2. 10785 */ 10786 10787 #define MLXSW_REG_MTPPTR_ID 0x9091 10788 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10789 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10790 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10791 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10792 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10793 10794 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10795 10796 /* reg_mtpptr_local_port 10797 * Not supported for CPU port. 10798 * Access: Index 10799 */ 10800 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10801 10802 enum mlxsw_reg_mtpptr_dir { 10803 MLXSW_REG_MTPPTR_DIR_INGRESS, 10804 MLXSW_REG_MTPPTR_DIR_EGRESS, 10805 }; 10806 10807 /* reg_mtpptr_dir 10808 * Direction. 10809 * Access: Index 10810 */ 10811 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10812 10813 /* reg_mtpptr_clr 10814 * Clear the records. 10815 * Access: OP 10816 */ 10817 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10818 10819 /* reg_mtpptr_num_rec 10820 * Number of valid records in the response 10821 * Range 0.. cap_ptp_timestamp_fifo 10822 * Access: RO 10823 */ 10824 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10825 10826 /* reg_mtpptr_rec_message_type 10827 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10828 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10829 * Access: RO 10830 */ 10831 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10832 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10833 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10834 10835 /* reg_mtpptr_rec_domain_number 10836 * DomainNumber field as defined by IEEE 1588 10837 * Access: RO 10838 */ 10839 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10840 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10841 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10842 10843 /* reg_mtpptr_rec_sequence_id 10844 * SequenceId field as defined by IEEE 1588 10845 * Access: RO 10846 */ 10847 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10848 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10849 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10850 10851 /* reg_mtpptr_rec_timestamp_high 10852 * Timestamp of when the PTP packet has passed through the port Units of PLL 10853 * clock time. 10854 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10855 * Access: RO 10856 */ 10857 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10858 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10859 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10860 10861 /* reg_mtpptr_rec_timestamp_low 10862 * See rec_timestamp_high. 10863 * Access: RO 10864 */ 10865 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10866 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10867 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10868 10869 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10870 unsigned int rec, 10871 u8 *p_message_type, 10872 u8 *p_domain_number, 10873 u16 *p_sequence_id, 10874 u64 *p_timestamp) 10875 { 10876 u32 timestamp_high, timestamp_low; 10877 10878 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10879 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10880 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10881 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10882 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10883 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10884 } 10885 10886 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10887 * --------------------------------------------------------- 10888 * This register is used for configuring under which trap to deliver PTP 10889 * packets depending on type of the packet. 10890 */ 10891 #define MLXSW_REG_MTPTPT_ID 0x9092 10892 #define MLXSW_REG_MTPTPT_LEN 0x08 10893 10894 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10895 10896 enum mlxsw_reg_mtptpt_trap_id { 10897 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10898 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10899 }; 10900 10901 /* reg_mtptpt_trap_id 10902 * Trap id. 10903 * Access: Index 10904 */ 10905 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10906 10907 /* reg_mtptpt_message_type 10908 * Bitwise vector of PTP message types to trap. This is a necessary but 10909 * non-sufficient condition since need to enable also per port. See MTPPPC. 10910 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10911 * Bit0: Sync, Bit1: Delay_Req) 10912 */ 10913 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10914 10915 static inline void mlxsw_reg_mtptpt_pack(char *payload, 10916 enum mlxsw_reg_mtptpt_trap_id trap_id, 10917 u16 message_type) 10918 { 10919 MLXSW_REG_ZERO(mtptpt, payload); 10920 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10921 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10922 } 10923 10924 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register 10925 * ------------------------------------------------------------------------- 10926 */ 10927 #define MLXSW_REG_MTPCPC_ID 0x9093 10928 #define MLXSW_REG_MTPCPC_LEN 0x2C 10929 10930 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN); 10931 10932 /* reg_mtpcpc_pport 10933 * Per port: 10934 * 0: config is global. When reading - the local_port is 1. 10935 * 1: config is per port. 10936 * Access: Index 10937 */ 10938 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1); 10939 10940 /* reg_mtpcpc_local_port 10941 * Local port number. 10942 * Supported to/from CPU port. 10943 * Reserved when pport = 0. 10944 * Access: Index 10945 */ 10946 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12); 10947 10948 /* reg_mtpcpc_ptp_trap_en 10949 * Enable PTP traps. 10950 * The trap_id is configured by MTPTPT. 10951 * Access: RW 10952 */ 10953 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1); 10954 10955 /* reg_mtpcpc_ing_correction_message_type 10956 * Bitwise vector of PTP message types to update correction-field at ingress. 10957 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10958 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 10959 * Default all 0 10960 * Access: RW 10961 */ 10962 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16); 10963 10964 /* reg_mtpcpc_egr_correction_message_type 10965 * Bitwise vector of PTP message types to update correction-field at egress. 10966 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10967 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 10968 * Default all 0 10969 * Access: RW 10970 */ 10971 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16); 10972 10973 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport, 10974 u16 local_port, bool ptp_trap_en, 10975 u16 ing, u16 egr) 10976 { 10977 MLXSW_REG_ZERO(mtpcpc, payload); 10978 mlxsw_reg_mtpcpc_pport_set(payload, pport); 10979 mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0); 10980 mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en); 10981 mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing); 10982 mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr); 10983 } 10984 10985 /* MFGD - Monitoring FW General Debug Register 10986 * ------------------------------------------- 10987 */ 10988 #define MLXSW_REG_MFGD_ID 0x90F0 10989 #define MLXSW_REG_MFGD_LEN 0x0C 10990 10991 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 10992 10993 /* reg_mfgd_fw_fatal_event_mode 10994 * 0 - don't check FW fatal (default) 10995 * 1 - check FW fatal - enable MFDE trap 10996 * Access: RW 10997 */ 10998 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 10999 11000 /* reg_mfgd_trigger_test 11001 * Access: WO 11002 */ 11003 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11004 11005 /* MGPIR - Management General Peripheral Information Register 11006 * ---------------------------------------------------------- 11007 * MGPIR register allows software to query the hardware and 11008 * firmware general information of peripheral entities. 11009 */ 11010 #define MLXSW_REG_MGPIR_ID 0x9100 11011 #define MLXSW_REG_MGPIR_LEN 0xA0 11012 11013 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11014 11015 enum mlxsw_reg_mgpir_device_type { 11016 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11017 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11018 }; 11019 11020 /* mgpir_slot_index 11021 * Slot index (0: Main board). 11022 * Access: Index 11023 */ 11024 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11025 11026 /* mgpir_device_type 11027 * Access: RO 11028 */ 11029 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11030 11031 /* mgpir_devices_per_flash 11032 * Number of devices of device_type per flash (can be shared by few devices). 11033 * Access: RO 11034 */ 11035 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11036 11037 /* mgpir_num_of_devices 11038 * Number of devices of device_type. 11039 * Access: RO 11040 */ 11041 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11042 11043 /* max_modules_per_slot 11044 * Maximum number of modules that can be connected per slot. 11045 * Access: RO 11046 */ 11047 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11048 11049 /* mgpir_num_of_slots 11050 * Number of slots in the system. 11051 * Access: RO 11052 */ 11053 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11054 11055 /* mgpir_num_of_modules 11056 * Number of modules. 11057 * Access: RO 11058 */ 11059 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11060 11061 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11062 { 11063 MLXSW_REG_ZERO(mgpir, payload); 11064 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11065 } 11066 11067 static inline void 11068 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11069 enum mlxsw_reg_mgpir_device_type *device_type, 11070 u8 *devices_per_flash, u8 *num_of_modules, 11071 u8 *num_of_slots) 11072 { 11073 if (num_of_devices) 11074 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11075 if (device_type) 11076 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11077 if (devices_per_flash) 11078 *devices_per_flash = 11079 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11080 if (num_of_modules) 11081 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11082 if (num_of_slots) 11083 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11084 } 11085 11086 /* MBCT - Management Binary Code Transfer Register 11087 * ----------------------------------------------- 11088 * This register allows to transfer binary codes from the host to 11089 * the management FW by transferring it by chunks of maximum 1KB. 11090 */ 11091 #define MLXSW_REG_MBCT_ID 0x9120 11092 #define MLXSW_REG_MBCT_LEN 0x420 11093 11094 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11095 11096 /* reg_mbct_slot_index 11097 * Slot index. 0 is reserved. 11098 * Access: Index 11099 */ 11100 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11101 11102 /* reg_mbct_data_size 11103 * Actual data field size in bytes for the current data transfer. 11104 * Access: WO 11105 */ 11106 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11107 11108 enum mlxsw_reg_mbct_op { 11109 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11110 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11111 MLXSW_REG_MBCT_OP_ACTIVATE, 11112 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11113 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11114 }; 11115 11116 /* reg_mbct_op 11117 * Access: WO 11118 */ 11119 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11120 11121 /* reg_mbct_last 11122 * Indicates that the current data field is the last chunk of the INI. 11123 * Access: WO 11124 */ 11125 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11126 11127 /* reg_mbct_oee 11128 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11129 * was executed and the fsm_state has changed. 11130 * Access: WO 11131 */ 11132 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11133 11134 enum mlxsw_reg_mbct_status { 11135 /* Partial data transfer completed successfully and ready for next 11136 * data transfer. 11137 */ 11138 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11139 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11140 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11141 /* Error - trying to erase INI while it being used. */ 11142 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11143 /* Last data transfer completed, applying magic pattern. */ 11144 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11145 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11146 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11147 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11148 }; 11149 11150 /* reg_mbct_status 11151 * Status. 11152 * Access: RO 11153 */ 11154 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11155 11156 enum mlxsw_reg_mbct_fsm_state { 11157 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11158 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11159 }; 11160 11161 /* reg_mbct_fsm_state 11162 * FSM state. 11163 * Access: RO 11164 */ 11165 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11166 11167 #define MLXSW_REG_MBCT_DATA_LEN 1024 11168 11169 /* reg_mbct_data 11170 * Up to 1KB of data. 11171 * Access: WO 11172 */ 11173 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11174 11175 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11176 enum mlxsw_reg_mbct_op op, bool oee) 11177 { 11178 MLXSW_REG_ZERO(mbct, payload); 11179 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11180 mlxsw_reg_mbct_op_set(payload, op); 11181 mlxsw_reg_mbct_oee_set(payload, oee); 11182 } 11183 11184 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11185 u16 data_size, bool last, 11186 const char *data) 11187 { 11188 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11189 return; 11190 mlxsw_reg_mbct_data_size_set(payload, data_size); 11191 mlxsw_reg_mbct_last_set(payload, last); 11192 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11193 } 11194 11195 static inline void 11196 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11197 enum mlxsw_reg_mbct_status *p_status, 11198 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11199 { 11200 if (p_slot_index) 11201 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11202 *p_status = mlxsw_reg_mbct_status_get(payload); 11203 if (p_fsm_state) 11204 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11205 } 11206 11207 /* MDDT - Management DownStream Device Tunneling Register 11208 * ------------------------------------------------------ 11209 * This register allows to deliver query and request messages (PRM registers, 11210 * commands) to a DownStream device. 11211 */ 11212 #define MLXSW_REG_MDDT_ID 0x9160 11213 #define MLXSW_REG_MDDT_LEN 0x110 11214 11215 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN); 11216 11217 /* reg_mddt_slot_index 11218 * Slot index. 11219 * Access: Index 11220 */ 11221 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4); 11222 11223 /* reg_mddt_device_index 11224 * Device index. 11225 * Access: Index 11226 */ 11227 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8); 11228 11229 /* reg_mddt_read_size 11230 * Read size in D-Words. 11231 * Access: OP 11232 */ 11233 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8); 11234 11235 /* reg_mddt_write_size 11236 * Write size in D-Words. 11237 * Access: OP 11238 */ 11239 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8); 11240 11241 enum mlxsw_reg_mddt_status { 11242 MLXSW_REG_MDDT_STATUS_OK, 11243 }; 11244 11245 /* reg_mddt_status 11246 * Return code of the Downstream Device to the register that was sent. 11247 * Access: RO 11248 */ 11249 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8); 11250 11251 enum mlxsw_reg_mddt_method { 11252 MLXSW_REG_MDDT_METHOD_QUERY, 11253 MLXSW_REG_MDDT_METHOD_WRITE, 11254 }; 11255 11256 /* reg_mddt_method 11257 * Access: OP 11258 */ 11259 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2); 11260 11261 /* reg_mddt_register_id 11262 * Access: Index 11263 */ 11264 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16); 11265 11266 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C 11267 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4 11268 11269 static inline char *mlxsw_reg_mddt_inner_payload(char *payload) 11270 { 11271 return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET + 11272 MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11273 } 11274 11275 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index, 11276 u8 device_index, 11277 enum mlxsw_reg_mddt_method method, 11278 const struct mlxsw_reg_info *reg, 11279 char **inner_payload) 11280 { 11281 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11282 11283 if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN)) 11284 len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET; 11285 11286 MLXSW_REG_ZERO(mddt, payload); 11287 mlxsw_reg_mddt_slot_index_set(payload, slot_index); 11288 mlxsw_reg_mddt_device_index_set(payload, device_index); 11289 mlxsw_reg_mddt_method_set(payload, method); 11290 mlxsw_reg_mddt_register_id_set(payload, reg->id); 11291 mlxsw_reg_mddt_read_size_set(payload, len / 4); 11292 mlxsw_reg_mddt_write_size_set(payload, len / 4); 11293 *inner_payload = mlxsw_reg_mddt_inner_payload(payload); 11294 } 11295 11296 /* MDDQ - Management DownStream Device Query Register 11297 * -------------------------------------------------- 11298 * This register allows to query the DownStream device properties. The desired 11299 * information is chosen upon the query_type field and is delivered by 32B 11300 * of data blocks. 11301 */ 11302 #define MLXSW_REG_MDDQ_ID 0x9161 11303 #define MLXSW_REG_MDDQ_LEN 0x30 11304 11305 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11306 11307 /* reg_mddq_sie 11308 * Slot info event enable. 11309 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11310 * active / ready will generate a DSDSC event. 11311 * Access: RW 11312 */ 11313 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11314 11315 enum mlxsw_reg_mddq_query_type { 11316 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11317 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices 11318 * on the slot, data_valid 11319 * will be '0'. 11320 */ 11321 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME, 11322 }; 11323 11324 /* reg_mddq_query_type 11325 * Access: Index 11326 */ 11327 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11328 11329 /* reg_mddq_slot_index 11330 * Slot index. 0 is reserved. 11331 * Access: Index 11332 */ 11333 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11334 11335 /* reg_mddq_response_msg_seq 11336 * Response message sequential number. For a specific request, the response 11337 * message sequential number is the following one. In addition, the last 11338 * message should be 0. 11339 * Access: RO 11340 */ 11341 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8); 11342 11343 /* reg_mddq_request_msg_seq 11344 * Request message sequential number. 11345 * The first message number should be 0. 11346 * Access: Index 11347 */ 11348 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8); 11349 11350 /* reg_mddq_data_valid 11351 * If set, the data in the data field is valid and contain the information 11352 * for the queried index. 11353 * Access: RO 11354 */ 11355 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1); 11356 11357 /* reg_mddq_slot_info_provisioned 11358 * If set, the INI file is applied and the card is provisioned. 11359 * Access: RO 11360 */ 11361 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11362 11363 /* reg_mddq_slot_info_sr_valid 11364 * If set, Shift Register is valid (after being provisioned) and data 11365 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11366 * Access: RO 11367 */ 11368 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11369 11370 enum mlxsw_reg_mddq_slot_info_ready { 11371 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11372 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11373 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11374 }; 11375 11376 /* reg_mddq_slot_info_lc_ready 11377 * If set, the LC is powered on, matching the INI version and a new FW 11378 * version can be burnt (if necessary). 11379 * Access: RO 11380 */ 11381 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11382 11383 /* reg_mddq_slot_info_active 11384 * If set, the FW has completed the MDDC.device_enable command. 11385 * Access: RO 11386 */ 11387 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11388 11389 /* reg_mddq_slot_info_hw_revision 11390 * Major user-configured version number of the current INI file. 11391 * Valid only when active or ready are '1'. 11392 * Access: RO 11393 */ 11394 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11395 11396 /* reg_mddq_slot_info_ini_file_version 11397 * User-configured version number of the current INI file. 11398 * Valid only when active or lc_ready are '1'. 11399 * Access: RO 11400 */ 11401 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11402 11403 /* reg_mddq_slot_info_card_type 11404 * Access: RO 11405 */ 11406 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11407 11408 static inline void 11409 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11410 enum mlxsw_reg_mddq_query_type query_type) 11411 { 11412 MLXSW_REG_ZERO(mddq, payload); 11413 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11414 mlxsw_reg_mddq_query_type_set(payload, query_type); 11415 } 11416 11417 static inline void 11418 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11419 { 11420 __mlxsw_reg_mddq_pack(payload, slot_index, 11421 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11422 mlxsw_reg_mddq_sie_set(payload, sie); 11423 } 11424 11425 static inline void 11426 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11427 bool *p_provisioned, bool *p_sr_valid, 11428 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11429 bool *p_active, u16 *p_hw_revision, 11430 u16 *p_ini_file_version, 11431 u8 *p_card_type) 11432 { 11433 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11434 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11435 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11436 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11437 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11438 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11439 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11440 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11441 } 11442 11443 /* reg_mddq_device_info_flash_owner 11444 * If set, the device is the flash owner. Otherwise, a shared flash 11445 * is used by this device (another device is the flash owner). 11446 * Access: RO 11447 */ 11448 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1); 11449 11450 /* reg_mddq_device_info_device_index 11451 * Device index. The first device should number 0. 11452 * Access: RO 11453 */ 11454 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8); 11455 11456 /* reg_mddq_device_info_fw_major 11457 * Major FW version number. 11458 * Access: RO 11459 */ 11460 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16); 11461 11462 /* reg_mddq_device_info_fw_minor 11463 * Minor FW version number. 11464 * Access: RO 11465 */ 11466 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16); 11467 11468 /* reg_mddq_device_info_fw_sub_minor 11469 * Sub-minor FW version number. 11470 * Access: RO 11471 */ 11472 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16); 11473 11474 static inline void 11475 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index, 11476 u8 request_msg_seq) 11477 { 11478 __mlxsw_reg_mddq_pack(payload, slot_index, 11479 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO); 11480 mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq); 11481 } 11482 11483 static inline void 11484 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq, 11485 bool *p_data_valid, bool *p_flash_owner, 11486 u8 *p_device_index, u16 *p_fw_major, 11487 u16 *p_fw_minor, u16 *p_fw_sub_minor) 11488 { 11489 *p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload); 11490 *p_data_valid = mlxsw_reg_mddq_data_valid_get(payload); 11491 *p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload); 11492 *p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload); 11493 *p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload); 11494 *p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload); 11495 *p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload); 11496 } 11497 11498 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11499 11500 /* reg_mddq_slot_ascii_name 11501 * Slot's ASCII name. 11502 * Access: RO 11503 */ 11504 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11505 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11506 11507 static inline void 11508 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11509 { 11510 __mlxsw_reg_mddq_pack(payload, slot_index, 11511 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11512 } 11513 11514 static inline void 11515 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11516 { 11517 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11518 } 11519 11520 /* MDDC - Management DownStream Device Control Register 11521 * ---------------------------------------------------- 11522 * This register allows to control downstream devices and line cards. 11523 */ 11524 #define MLXSW_REG_MDDC_ID 0x9163 11525 #define MLXSW_REG_MDDC_LEN 0x30 11526 11527 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11528 11529 /* reg_mddc_slot_index 11530 * Slot index. 0 is reserved. 11531 * Access: Index 11532 */ 11533 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11534 11535 /* reg_mddc_rst 11536 * Reset request. 11537 * Access: OP 11538 */ 11539 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11540 11541 /* reg_mddc_device_enable 11542 * When set, FW is the manager and allowed to program the downstream device. 11543 * Access: RW 11544 */ 11545 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11546 11547 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11548 bool device_enable) 11549 { 11550 MLXSW_REG_ZERO(mddc, payload); 11551 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11552 mlxsw_reg_mddc_rst_set(payload, rst); 11553 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11554 } 11555 11556 /* MFDE - Monitoring FW Debug Register 11557 * ----------------------------------- 11558 */ 11559 #define MLXSW_REG_MFDE_ID 0x9200 11560 #define MLXSW_REG_MFDE_LEN 0x30 11561 11562 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11563 11564 /* reg_mfde_irisc_id 11565 * Which irisc triggered the event 11566 * Access: RO 11567 */ 11568 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11569 11570 enum mlxsw_reg_mfde_severity { 11571 /* Unrecoverable switch behavior */ 11572 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11573 /* Unexpected state with possible systemic failure */ 11574 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11575 /* Unexpected state without systemic failure */ 11576 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11577 }; 11578 11579 /* reg_mfde_severity 11580 * The severity of the event. 11581 * Access: RO 11582 */ 11583 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11584 11585 enum mlxsw_reg_mfde_event_id { 11586 /* CRspace timeout */ 11587 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11588 /* KVD insertion machine stopped */ 11589 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11590 /* Triggered by MFGD.trigger_test */ 11591 MLXSW_REG_MFDE_EVENT_ID_TEST, 11592 /* Triggered when firmware hits an assert */ 11593 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11594 /* Fatal error interrupt from hardware */ 11595 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11596 }; 11597 11598 /* reg_mfde_event_id 11599 * Access: RO 11600 */ 11601 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11602 11603 enum mlxsw_reg_mfde_method { 11604 MLXSW_REG_MFDE_METHOD_QUERY, 11605 MLXSW_REG_MFDE_METHOD_WRITE, 11606 }; 11607 11608 /* reg_mfde_method 11609 * Access: RO 11610 */ 11611 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11612 11613 /* reg_mfde_long_process 11614 * Indicates if the command is in long_process mode. 11615 * Access: RO 11616 */ 11617 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11618 11619 enum mlxsw_reg_mfde_command_type { 11620 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11621 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11622 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11623 }; 11624 11625 /* reg_mfde_command_type 11626 * Access: RO 11627 */ 11628 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11629 11630 /* reg_mfde_reg_attr_id 11631 * EMAD - register id, MAD - attibute id 11632 * Access: RO 11633 */ 11634 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11635 11636 /* reg_mfde_crspace_to_log_address 11637 * crspace address accessed, which resulted in timeout. 11638 * Access: RO 11639 */ 11640 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11641 11642 /* reg_mfde_crspace_to_oe 11643 * 0 - New event 11644 * 1 - Old event, occurred before MFGD activation. 11645 * Access: RO 11646 */ 11647 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11648 11649 /* reg_mfde_crspace_to_log_id 11650 * Which irisc triggered the timeout. 11651 * Access: RO 11652 */ 11653 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11654 11655 /* reg_mfde_crspace_to_log_ip 11656 * IP (instruction pointer) that triggered the timeout. 11657 * Access: RO 11658 */ 11659 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11660 11661 /* reg_mfde_kvd_im_stop_oe 11662 * 0 - New event 11663 * 1 - Old event, occurred before MFGD activation. 11664 * Access: RO 11665 */ 11666 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11667 11668 /* reg_mfde_kvd_im_stop_pipes_mask 11669 * Bit per kvh pipe. 11670 * Access: RO 11671 */ 11672 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11673 11674 /* reg_mfde_fw_assert_var0-4 11675 * Variables passed to assert. 11676 * Access: RO 11677 */ 11678 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11679 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11680 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11681 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11682 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11683 11684 /* reg_mfde_fw_assert_existptr 11685 * The instruction pointer when assert was triggered. 11686 * Access: RO 11687 */ 11688 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11689 11690 /* reg_mfde_fw_assert_callra 11691 * The return address after triggering assert. 11692 * Access: RO 11693 */ 11694 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11695 11696 /* reg_mfde_fw_assert_oe 11697 * 0 - New event 11698 * 1 - Old event, occurred before MFGD activation. 11699 * Access: RO 11700 */ 11701 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11702 11703 /* reg_mfde_fw_assert_tile_v 11704 * 0: The assert was from main 11705 * 1: The assert was from a tile 11706 * Access: RO 11707 */ 11708 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11709 11710 /* reg_mfde_fw_assert_tile_index 11711 * When tile_v=1, the tile_index that caused the assert. 11712 * Access: RO 11713 */ 11714 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11715 11716 /* reg_mfde_fw_assert_ext_synd 11717 * A generated one-to-one identifier which is specific per-assert. 11718 * Access: RO 11719 */ 11720 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11721 11722 /* reg_mfde_fatal_cause_id 11723 * HW interrupt cause id. 11724 * Access: RO 11725 */ 11726 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11727 11728 /* reg_mfde_fatal_cause_tile_v 11729 * 0: The assert was from main 11730 * 1: The assert was from a tile 11731 * Access: RO 11732 */ 11733 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11734 11735 /* reg_mfde_fatal_cause_tile_index 11736 * When tile_v=1, the tile_index that caused the assert. 11737 * Access: RO 11738 */ 11739 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11740 11741 /* TNGCR - Tunneling NVE General Configuration Register 11742 * ---------------------------------------------------- 11743 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11744 */ 11745 #define MLXSW_REG_TNGCR_ID 0xA001 11746 #define MLXSW_REG_TNGCR_LEN 0x44 11747 11748 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11749 11750 enum mlxsw_reg_tngcr_type { 11751 MLXSW_REG_TNGCR_TYPE_VXLAN, 11752 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11753 MLXSW_REG_TNGCR_TYPE_GENEVE, 11754 MLXSW_REG_TNGCR_TYPE_NVGRE, 11755 }; 11756 11757 /* reg_tngcr_type 11758 * Tunnel type for encapsulation and decapsulation. The types are mutually 11759 * exclusive. 11760 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11761 * Access: RW 11762 */ 11763 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11764 11765 /* reg_tngcr_nve_valid 11766 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11767 * Access: RW 11768 */ 11769 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11770 11771 /* reg_tngcr_nve_ttl_uc 11772 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11773 * Access: RW 11774 */ 11775 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11776 11777 /* reg_tngcr_nve_ttl_mc 11778 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11779 * Access: RW 11780 */ 11781 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11782 11783 enum { 11784 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11785 MLXSW_REG_TNGCR_FL_NO_COPY, 11786 /* Copy flow label from inner packet if packet is IPv6 and 11787 * encapsulation is by IPv6. Otherwise, calculate flow label using 11788 * nve_flh. 11789 */ 11790 MLXSW_REG_TNGCR_FL_COPY, 11791 }; 11792 11793 /* reg_tngcr_nve_flc 11794 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11795 * Access: RW 11796 */ 11797 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11798 11799 enum { 11800 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11801 * uses {nve_fl_prefix, nve_fl_suffix}. 11802 */ 11803 MLXSW_REG_TNGCR_FL_NO_HASH, 11804 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11805 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11806 */ 11807 MLXSW_REG_TNGCR_FL_HASH, 11808 }; 11809 11810 /* reg_tngcr_nve_flh 11811 * NVE flow label hash. 11812 * Access: RW 11813 */ 11814 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11815 11816 /* reg_tngcr_nve_fl_prefix 11817 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11818 * Access: RW 11819 */ 11820 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11821 11822 /* reg_tngcr_nve_fl_suffix 11823 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11824 * Reserved when nve_flh=1 and for Spectrum. 11825 * Access: RW 11826 */ 11827 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11828 11829 enum { 11830 /* Source UDP port is fixed (default '0') */ 11831 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11832 /* Source UDP port is calculated based on hash */ 11833 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11834 }; 11835 11836 /* reg_tngcr_nve_udp_sport_type 11837 * NVE UDP source port type. 11838 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11839 * When the source UDP port is calculated based on hash, then the 8 LSBs 11840 * are calculated from hash the 8 MSBs are configured by 11841 * nve_udp_sport_prefix. 11842 * Access: RW 11843 */ 11844 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11845 11846 /* reg_tngcr_nve_udp_sport_prefix 11847 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11848 * Reserved when NVE type is NVGRE. 11849 * Access: RW 11850 */ 11851 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11852 11853 /* reg_tngcr_nve_group_size_mc 11854 * The amount of sequential linked lists of MC entries. The first linked 11855 * list is configured by SFD.underlay_mc_ptr. 11856 * Valid values: 1, 2, 4, 8, 16, 32, 64 11857 * The linked list are configured by TNUMT. 11858 * The hash is set by LAG hash. 11859 * Access: RW 11860 */ 11861 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11862 11863 /* reg_tngcr_nve_group_size_flood 11864 * The amount of sequential linked lists of flooding entries. The first 11865 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11866 * Valid values: 1, 2, 4, 8, 16, 32, 64 11867 * The linked list are configured by TNUMT. 11868 * The hash is set by LAG hash. 11869 * Access: RW 11870 */ 11871 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11872 11873 /* reg_tngcr_learn_enable 11874 * During decapsulation, whether to learn from NVE port. 11875 * Reserved when Spectrum-2. See TNPC. 11876 * Access: RW 11877 */ 11878 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11879 11880 /* reg_tngcr_underlay_virtual_router 11881 * Underlay virtual router. 11882 * Reserved when Spectrum-2. 11883 * Access: RW 11884 */ 11885 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11886 11887 /* reg_tngcr_underlay_rif 11888 * Underlay ingress router interface. RIF type should be loopback generic. 11889 * Reserved when Spectrum. 11890 * Access: RW 11891 */ 11892 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11893 11894 /* reg_tngcr_usipv4 11895 * Underlay source IPv4 address of the NVE. 11896 * Access: RW 11897 */ 11898 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11899 11900 /* reg_tngcr_usipv6 11901 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11902 * modified under traffic of NVE tunneling encapsulation. 11903 * Access: RW 11904 */ 11905 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11906 11907 static inline void mlxsw_reg_tngcr_pack(char *payload, 11908 enum mlxsw_reg_tngcr_type type, 11909 bool valid, u8 ttl) 11910 { 11911 MLXSW_REG_ZERO(tngcr, payload); 11912 mlxsw_reg_tngcr_type_set(payload, type); 11913 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11914 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11915 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11916 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11917 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11918 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11919 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11920 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11921 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11922 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11923 } 11924 11925 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11926 * ------------------------------------------------------- 11927 * The TNUMT register is for building the underlay MC table. It is used 11928 * for MC, flooding and BC traffic into the NVE tunnel. 11929 */ 11930 #define MLXSW_REG_TNUMT_ID 0xA003 11931 #define MLXSW_REG_TNUMT_LEN 0x20 11932 11933 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11934 11935 enum mlxsw_reg_tnumt_record_type { 11936 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11937 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11938 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11939 }; 11940 11941 /* reg_tnumt_record_type 11942 * Record type. 11943 * Access: RW 11944 */ 11945 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11946 11947 /* reg_tnumt_tunnel_port 11948 * Tunnel port. 11949 * Access: RW 11950 */ 11951 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11952 11953 /* reg_tnumt_underlay_mc_ptr 11954 * Index to the underlay multicast table. 11955 * For Spectrum the index is to the KVD linear. 11956 * Access: Index 11957 */ 11958 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11959 11960 /* reg_tnumt_vnext 11961 * The next_underlay_mc_ptr is valid. 11962 * Access: RW 11963 */ 11964 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11965 11966 /* reg_tnumt_next_underlay_mc_ptr 11967 * The next index to the underlay multicast table. 11968 * Access: RW 11969 */ 11970 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11971 11972 /* reg_tnumt_record_size 11973 * Number of IP addresses in the record. 11974 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11975 * Access: RW 11976 */ 11977 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11978 11979 /* reg_tnumt_udip 11980 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11981 * Access: RW 11982 */ 11983 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11984 11985 /* reg_tnumt_udip_ptr 11986 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11987 * i >= size. The IPv6 addresses are configured by RIPS. 11988 * Access: RW 11989 */ 11990 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11991 11992 static inline void mlxsw_reg_tnumt_pack(char *payload, 11993 enum mlxsw_reg_tnumt_record_type type, 11994 enum mlxsw_reg_tunnel_port tport, 11995 u32 underlay_mc_ptr, bool vnext, 11996 u32 next_underlay_mc_ptr, 11997 u8 record_size) 11998 { 11999 MLXSW_REG_ZERO(tnumt, payload); 12000 mlxsw_reg_tnumt_record_type_set(payload, type); 12001 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 12002 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 12003 mlxsw_reg_tnumt_vnext_set(payload, vnext); 12004 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 12005 mlxsw_reg_tnumt_record_size_set(payload, record_size); 12006 } 12007 12008 /* TNQCR - Tunneling NVE QoS Configuration Register 12009 * ------------------------------------------------ 12010 * The TNQCR register configures how QoS is set in encapsulation into the 12011 * underlay network. 12012 */ 12013 #define MLXSW_REG_TNQCR_ID 0xA010 12014 #define MLXSW_REG_TNQCR_LEN 0x0C 12015 12016 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 12017 12018 /* reg_tnqcr_enc_set_dscp 12019 * For encapsulation: How to set DSCP field: 12020 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 12021 * (outer) IP header. If there is no IP header, use TNQDR.dscp 12022 * 1 - Set the DSCP field as TNQDR.dscp 12023 * Access: RW 12024 */ 12025 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 12026 12027 static inline void mlxsw_reg_tnqcr_pack(char *payload) 12028 { 12029 MLXSW_REG_ZERO(tnqcr, payload); 12030 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 12031 } 12032 12033 /* TNQDR - Tunneling NVE QoS Default Register 12034 * ------------------------------------------ 12035 * The TNQDR register configures the default QoS settings for NVE 12036 * encapsulation. 12037 */ 12038 #define MLXSW_REG_TNQDR_ID 0xA011 12039 #define MLXSW_REG_TNQDR_LEN 0x08 12040 12041 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 12042 12043 /* reg_tnqdr_local_port 12044 * Local port number (receive port). CPU port is supported. 12045 * Access: Index 12046 */ 12047 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 12048 12049 /* reg_tnqdr_dscp 12050 * For encapsulation, the default DSCP. 12051 * Access: RW 12052 */ 12053 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 12054 12055 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 12056 { 12057 MLXSW_REG_ZERO(tnqdr, payload); 12058 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 12059 mlxsw_reg_tnqdr_dscp_set(payload, 0); 12060 } 12061 12062 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 12063 * -------------------------------------------------------- 12064 * The TNEEM register maps ECN of the IP header at the ingress to the 12065 * encapsulation to the ECN of the underlay network. 12066 */ 12067 #define MLXSW_REG_TNEEM_ID 0xA012 12068 #define MLXSW_REG_TNEEM_LEN 0x0C 12069 12070 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 12071 12072 /* reg_tneem_overlay_ecn 12073 * ECN of the IP header in the overlay network. 12074 * Access: Index 12075 */ 12076 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 12077 12078 /* reg_tneem_underlay_ecn 12079 * ECN of the IP header in the underlay network. 12080 * Access: RW 12081 */ 12082 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 12083 12084 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 12085 u8 underlay_ecn) 12086 { 12087 MLXSW_REG_ZERO(tneem, payload); 12088 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 12089 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 12090 } 12091 12092 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 12093 * -------------------------------------------------------- 12094 * The TNDEM register configures the actions that are done in the 12095 * decapsulation. 12096 */ 12097 #define MLXSW_REG_TNDEM_ID 0xA013 12098 #define MLXSW_REG_TNDEM_LEN 0x0C 12099 12100 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12101 12102 /* reg_tndem_underlay_ecn 12103 * ECN field of the IP header in the underlay network. 12104 * Access: Index 12105 */ 12106 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12107 12108 /* reg_tndem_overlay_ecn 12109 * ECN field of the IP header in the overlay network. 12110 * Access: Index 12111 */ 12112 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12113 12114 /* reg_tndem_eip_ecn 12115 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12116 * from the decapsulation. 12117 * Access: RW 12118 */ 12119 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12120 12121 /* reg_tndem_trap_en 12122 * Trap enable: 12123 * 0 - No trap due to decap ECN 12124 * 1 - Trap enable with trap_id 12125 * Access: RW 12126 */ 12127 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12128 12129 /* reg_tndem_trap_id 12130 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12131 * Reserved when trap_en is '0'. 12132 * Access: RW 12133 */ 12134 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12135 12136 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12137 u8 overlay_ecn, u8 ecn, bool trap_en, 12138 u16 trap_id) 12139 { 12140 MLXSW_REG_ZERO(tndem, payload); 12141 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12142 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12143 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12144 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12145 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12146 } 12147 12148 /* TNPC - Tunnel Port Configuration Register 12149 * ----------------------------------------- 12150 * The TNPC register is used for tunnel port configuration. 12151 * Reserved when Spectrum. 12152 */ 12153 #define MLXSW_REG_TNPC_ID 0xA020 12154 #define MLXSW_REG_TNPC_LEN 0x18 12155 12156 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12157 12158 /* reg_tnpc_tunnel_port 12159 * Tunnel port. 12160 * Access: Index 12161 */ 12162 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12163 12164 /* reg_tnpc_learn_enable_v6 12165 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12166 * Access: RW 12167 */ 12168 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12169 12170 /* reg_tnpc_learn_enable_v4 12171 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12172 * Access: RW 12173 */ 12174 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12175 12176 static inline void mlxsw_reg_tnpc_pack(char *payload, 12177 enum mlxsw_reg_tunnel_port tport, 12178 bool learn_enable) 12179 { 12180 MLXSW_REG_ZERO(tnpc, payload); 12181 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12182 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12183 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12184 } 12185 12186 /* TIGCR - Tunneling IPinIP General Configuration Register 12187 * ------------------------------------------------------- 12188 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12189 */ 12190 #define MLXSW_REG_TIGCR_ID 0xA801 12191 #define MLXSW_REG_TIGCR_LEN 0x10 12192 12193 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12194 12195 /* reg_tigcr_ipip_ttlc 12196 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12197 * header. 12198 * Access: RW 12199 */ 12200 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12201 12202 /* reg_tigcr_ipip_ttl_uc 12203 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12204 * reg_tigcr_ipip_ttlc is unset. 12205 * Access: RW 12206 */ 12207 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12208 12209 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12210 { 12211 MLXSW_REG_ZERO(tigcr, payload); 12212 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12213 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12214 } 12215 12216 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12217 * ----------------------------------------------------------- 12218 * The TIEEM register maps ECN of the IP header at the ingress to the 12219 * encapsulation to the ECN of the underlay network. 12220 */ 12221 #define MLXSW_REG_TIEEM_ID 0xA812 12222 #define MLXSW_REG_TIEEM_LEN 0x0C 12223 12224 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12225 12226 /* reg_tieem_overlay_ecn 12227 * ECN of the IP header in the overlay network. 12228 * Access: Index 12229 */ 12230 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12231 12232 /* reg_tineem_underlay_ecn 12233 * ECN of the IP header in the underlay network. 12234 * Access: RW 12235 */ 12236 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12237 12238 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12239 u8 underlay_ecn) 12240 { 12241 MLXSW_REG_ZERO(tieem, payload); 12242 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12243 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12244 } 12245 12246 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12247 * ----------------------------------------------------------- 12248 * The TIDEM register configures the actions that are done in the 12249 * decapsulation. 12250 */ 12251 #define MLXSW_REG_TIDEM_ID 0xA813 12252 #define MLXSW_REG_TIDEM_LEN 0x0C 12253 12254 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12255 12256 /* reg_tidem_underlay_ecn 12257 * ECN field of the IP header in the underlay network. 12258 * Access: Index 12259 */ 12260 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12261 12262 /* reg_tidem_overlay_ecn 12263 * ECN field of the IP header in the overlay network. 12264 * Access: Index 12265 */ 12266 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12267 12268 /* reg_tidem_eip_ecn 12269 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12270 * from the decapsulation. 12271 * Access: RW 12272 */ 12273 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12274 12275 /* reg_tidem_trap_en 12276 * Trap enable: 12277 * 0 - No trap due to decap ECN 12278 * 1 - Trap enable with trap_id 12279 * Access: RW 12280 */ 12281 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12282 12283 /* reg_tidem_trap_id 12284 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12285 * Reserved when trap_en is '0'. 12286 * Access: RW 12287 */ 12288 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12289 12290 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12291 u8 overlay_ecn, u8 eip_ecn, 12292 bool trap_en, u16 trap_id) 12293 { 12294 MLXSW_REG_ZERO(tidem, payload); 12295 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12296 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12297 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12298 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12299 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12300 } 12301 12302 /* SBPR - Shared Buffer Pools Register 12303 * ----------------------------------- 12304 * The SBPR configures and retrieves the shared buffer pools and configuration. 12305 */ 12306 #define MLXSW_REG_SBPR_ID 0xB001 12307 #define MLXSW_REG_SBPR_LEN 0x14 12308 12309 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12310 12311 /* reg_sbpr_desc 12312 * When set, configures descriptor buffer. 12313 * Access: Index 12314 */ 12315 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12316 12317 /* shared direstion enum for SBPR, SBCM, SBPM */ 12318 enum mlxsw_reg_sbxx_dir { 12319 MLXSW_REG_SBXX_DIR_INGRESS, 12320 MLXSW_REG_SBXX_DIR_EGRESS, 12321 }; 12322 12323 /* reg_sbpr_dir 12324 * Direction. 12325 * Access: Index 12326 */ 12327 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12328 12329 /* reg_sbpr_pool 12330 * Pool index. 12331 * Access: Index 12332 */ 12333 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12334 12335 /* reg_sbpr_infi_size 12336 * Size is infinite. 12337 * Access: RW 12338 */ 12339 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12340 12341 /* reg_sbpr_size 12342 * Pool size in buffer cells. 12343 * Reserved when infi_size = 1. 12344 * Access: RW 12345 */ 12346 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12347 12348 enum mlxsw_reg_sbpr_mode { 12349 MLXSW_REG_SBPR_MODE_STATIC, 12350 MLXSW_REG_SBPR_MODE_DYNAMIC, 12351 }; 12352 12353 /* reg_sbpr_mode 12354 * Pool quota calculation mode. 12355 * Access: RW 12356 */ 12357 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12358 12359 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12360 enum mlxsw_reg_sbxx_dir dir, 12361 enum mlxsw_reg_sbpr_mode mode, u32 size, 12362 bool infi_size) 12363 { 12364 MLXSW_REG_ZERO(sbpr, payload); 12365 mlxsw_reg_sbpr_pool_set(payload, pool); 12366 mlxsw_reg_sbpr_dir_set(payload, dir); 12367 mlxsw_reg_sbpr_mode_set(payload, mode); 12368 mlxsw_reg_sbpr_size_set(payload, size); 12369 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12370 } 12371 12372 /* SBCM - Shared Buffer Class Management Register 12373 * ---------------------------------------------- 12374 * The SBCM register configures and retrieves the shared buffer allocation 12375 * and configuration according to Port-PG, including the binding to pool 12376 * and definition of the associated quota. 12377 */ 12378 #define MLXSW_REG_SBCM_ID 0xB002 12379 #define MLXSW_REG_SBCM_LEN 0x28 12380 12381 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12382 12383 /* reg_sbcm_local_port 12384 * Local port number. 12385 * For Ingress: excludes CPU port and Router port 12386 * For Egress: excludes IP Router 12387 * Access: Index 12388 */ 12389 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12390 12391 /* reg_sbcm_pg_buff 12392 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12393 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12394 * For traffic class: range is 0..cap_max_tclass - 1 12395 * Note that when traffic class is in MC aware mode then the traffic 12396 * classes which are MC aware cannot be configured. 12397 * Access: Index 12398 */ 12399 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12400 12401 /* reg_sbcm_dir 12402 * Direction. 12403 * Access: Index 12404 */ 12405 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12406 12407 /* reg_sbcm_min_buff 12408 * Minimum buffer size for the limiter, in cells. 12409 * Access: RW 12410 */ 12411 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12412 12413 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12414 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12415 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12416 12417 /* reg_sbcm_infi_max 12418 * Max buffer is infinite. 12419 * Access: RW 12420 */ 12421 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12422 12423 /* reg_sbcm_max_buff 12424 * When the pool associated to the port-pg/tclass is configured to 12425 * static, Maximum buffer size for the limiter configured in cells. 12426 * When the pool associated to the port-pg/tclass is configured to 12427 * dynamic, the max_buff holds the "alpha" parameter, supporting 12428 * the following values: 12429 * 0: 0 12430 * i: (1/128)*2^(i-1), for i=1..14 12431 * 0xFF: Infinity 12432 * Reserved when infi_max = 1. 12433 * Access: RW 12434 */ 12435 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12436 12437 /* reg_sbcm_pool 12438 * Association of the port-priority to a pool. 12439 * Access: RW 12440 */ 12441 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12442 12443 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12444 enum mlxsw_reg_sbxx_dir dir, 12445 u32 min_buff, u32 max_buff, 12446 bool infi_max, u8 pool) 12447 { 12448 MLXSW_REG_ZERO(sbcm, payload); 12449 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12450 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12451 mlxsw_reg_sbcm_dir_set(payload, dir); 12452 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12453 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12454 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12455 mlxsw_reg_sbcm_pool_set(payload, pool); 12456 } 12457 12458 /* SBPM - Shared Buffer Port Management Register 12459 * --------------------------------------------- 12460 * The SBPM register configures and retrieves the shared buffer allocation 12461 * and configuration according to Port-Pool, including the definition 12462 * of the associated quota. 12463 */ 12464 #define MLXSW_REG_SBPM_ID 0xB003 12465 #define MLXSW_REG_SBPM_LEN 0x28 12466 12467 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12468 12469 /* reg_sbpm_local_port 12470 * Local port number. 12471 * For Ingress: excludes CPU port and Router port 12472 * For Egress: excludes IP Router 12473 * Access: Index 12474 */ 12475 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12476 12477 /* reg_sbpm_pool 12478 * The pool associated to quota counting on the local_port. 12479 * Access: Index 12480 */ 12481 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12482 12483 /* reg_sbpm_dir 12484 * Direction. 12485 * Access: Index 12486 */ 12487 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12488 12489 /* reg_sbpm_buff_occupancy 12490 * Current buffer occupancy in cells. 12491 * Access: RO 12492 */ 12493 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12494 12495 /* reg_sbpm_clr 12496 * Clear Max Buffer Occupancy 12497 * When this bit is set, max_buff_occupancy field is cleared (and a 12498 * new max value is tracked from the time the clear was performed). 12499 * Access: OP 12500 */ 12501 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12502 12503 /* reg_sbpm_max_buff_occupancy 12504 * Maximum value of buffer occupancy in cells monitored. Cleared by 12505 * writing to the clr field. 12506 * Access: RO 12507 */ 12508 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12509 12510 /* reg_sbpm_min_buff 12511 * Minimum buffer size for the limiter, in cells. 12512 * Access: RW 12513 */ 12514 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12515 12516 /* reg_sbpm_max_buff 12517 * When the pool associated to the port-pg/tclass is configured to 12518 * static, Maximum buffer size for the limiter configured in cells. 12519 * When the pool associated to the port-pg/tclass is configured to 12520 * dynamic, the max_buff holds the "alpha" parameter, supporting 12521 * the following values: 12522 * 0: 0 12523 * i: (1/128)*2^(i-1), for i=1..14 12524 * 0xFF: Infinity 12525 * Access: RW 12526 */ 12527 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12528 12529 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12530 enum mlxsw_reg_sbxx_dir dir, bool clr, 12531 u32 min_buff, u32 max_buff) 12532 { 12533 MLXSW_REG_ZERO(sbpm, payload); 12534 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12535 mlxsw_reg_sbpm_pool_set(payload, pool); 12536 mlxsw_reg_sbpm_dir_set(payload, dir); 12537 mlxsw_reg_sbpm_clr_set(payload, clr); 12538 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12539 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12540 } 12541 12542 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12543 u32 *p_max_buff_occupancy) 12544 { 12545 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12546 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12547 } 12548 12549 /* SBMM - Shared Buffer Multicast Management Register 12550 * -------------------------------------------------- 12551 * The SBMM register configures and retrieves the shared buffer allocation 12552 * and configuration for MC packets according to Switch-Priority, including 12553 * the binding to pool and definition of the associated quota. 12554 */ 12555 #define MLXSW_REG_SBMM_ID 0xB004 12556 #define MLXSW_REG_SBMM_LEN 0x28 12557 12558 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12559 12560 /* reg_sbmm_prio 12561 * Switch Priority. 12562 * Access: Index 12563 */ 12564 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12565 12566 /* reg_sbmm_min_buff 12567 * Minimum buffer size for the limiter, in cells. 12568 * Access: RW 12569 */ 12570 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12571 12572 /* reg_sbmm_max_buff 12573 * When the pool associated to the port-pg/tclass is configured to 12574 * static, Maximum buffer size for the limiter configured in cells. 12575 * When the pool associated to the port-pg/tclass is configured to 12576 * dynamic, the max_buff holds the "alpha" parameter, supporting 12577 * the following values: 12578 * 0: 0 12579 * i: (1/128)*2^(i-1), for i=1..14 12580 * 0xFF: Infinity 12581 * Access: RW 12582 */ 12583 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12584 12585 /* reg_sbmm_pool 12586 * Association of the port-priority to a pool. 12587 * Access: RW 12588 */ 12589 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12590 12591 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12592 u32 max_buff, u8 pool) 12593 { 12594 MLXSW_REG_ZERO(sbmm, payload); 12595 mlxsw_reg_sbmm_prio_set(payload, prio); 12596 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12597 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12598 mlxsw_reg_sbmm_pool_set(payload, pool); 12599 } 12600 12601 /* SBSR - Shared Buffer Status Register 12602 * ------------------------------------ 12603 * The SBSR register retrieves the shared buffer occupancy according to 12604 * Port-Pool. Note that this register enables reading a large amount of data. 12605 * It is the user's responsibility to limit the amount of data to ensure the 12606 * response can match the maximum transfer unit. In case the response exceeds 12607 * the maximum transport unit, it will be truncated with no special notice. 12608 */ 12609 #define MLXSW_REG_SBSR_ID 0xB005 12610 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12611 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12612 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12613 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12614 MLXSW_REG_SBSR_REC_LEN * \ 12615 MLXSW_REG_SBSR_REC_MAX_COUNT) 12616 12617 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12618 12619 /* reg_sbsr_clr 12620 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12621 * field is cleared (and a new max value is tracked from the time the clear 12622 * was performed). 12623 * Access: OP 12624 */ 12625 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12626 12627 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12628 12629 /* reg_sbsr_port_page 12630 * Determines the range of the ports specified in the 'ingress_port_mask' 12631 * and 'egress_port_mask' bit masks. 12632 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12633 * Access: Index 12634 */ 12635 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12636 12637 /* reg_sbsr_ingress_port_mask 12638 * Bit vector for all ingress network ports. 12639 * Indicates which of the ports (for which the relevant bit is set) 12640 * are affected by the set operation. Configuration of any other port 12641 * does not change. 12642 * Access: Index 12643 */ 12644 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12645 12646 /* reg_sbsr_pg_buff_mask 12647 * Bit vector for all switch priority groups. 12648 * Indicates which of the priorities (for which the relevant bit is set) 12649 * are affected by the set operation. Configuration of any other priority 12650 * does not change. 12651 * Range is 0..cap_max_pg_buffers - 1 12652 * Access: Index 12653 */ 12654 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12655 12656 /* reg_sbsr_egress_port_mask 12657 * Bit vector for all egress network ports. 12658 * Indicates which of the ports (for which the relevant bit is set) 12659 * are affected by the set operation. Configuration of any other port 12660 * does not change. 12661 * Access: Index 12662 */ 12663 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12664 12665 /* reg_sbsr_tclass_mask 12666 * Bit vector for all traffic classes. 12667 * Indicates which of the traffic classes (for which the relevant bit is 12668 * set) are affected by the set operation. Configuration of any other 12669 * traffic class does not change. 12670 * Range is 0..cap_max_tclass - 1 12671 * Access: Index 12672 */ 12673 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12674 12675 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12676 { 12677 MLXSW_REG_ZERO(sbsr, payload); 12678 mlxsw_reg_sbsr_clr_set(payload, clr); 12679 } 12680 12681 /* reg_sbsr_rec_buff_occupancy 12682 * Current buffer occupancy in cells. 12683 * Access: RO 12684 */ 12685 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12686 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12687 12688 /* reg_sbsr_rec_max_buff_occupancy 12689 * Maximum value of buffer occupancy in cells monitored. Cleared by 12690 * writing to the clr field. 12691 * Access: RO 12692 */ 12693 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12694 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12695 12696 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12697 u32 *p_buff_occupancy, 12698 u32 *p_max_buff_occupancy) 12699 { 12700 *p_buff_occupancy = 12701 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12702 *p_max_buff_occupancy = 12703 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12704 } 12705 12706 /* SBIB - Shared Buffer Internal Buffer Register 12707 * --------------------------------------------- 12708 * The SBIB register configures per port buffers for internal use. The internal 12709 * buffers consume memory on the port buffers (note that the port buffers are 12710 * used also by PBMC). 12711 * 12712 * For Spectrum this is used for egress mirroring. 12713 */ 12714 #define MLXSW_REG_SBIB_ID 0xB006 12715 #define MLXSW_REG_SBIB_LEN 0x10 12716 12717 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12718 12719 /* reg_sbib_local_port 12720 * Local port number 12721 * Not supported for CPU port and router port 12722 * Access: Index 12723 */ 12724 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12725 12726 /* reg_sbib_buff_size 12727 * Units represented in cells 12728 * Allowed range is 0 to (cap_max_headroom_size - 1) 12729 * Default is 0 12730 * Access: RW 12731 */ 12732 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12733 12734 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12735 u32 buff_size) 12736 { 12737 MLXSW_REG_ZERO(sbib, payload); 12738 mlxsw_reg_sbib_local_port_set(payload, local_port); 12739 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12740 } 12741 12742 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12743 MLXSW_REG(sgcr), 12744 MLXSW_REG(spad), 12745 MLXSW_REG(sspr), 12746 MLXSW_REG(sfdat), 12747 MLXSW_REG(sfd), 12748 MLXSW_REG(sfn), 12749 MLXSW_REG(spms), 12750 MLXSW_REG(spvid), 12751 MLXSW_REG(spvm), 12752 MLXSW_REG(spaft), 12753 MLXSW_REG(sfgc), 12754 MLXSW_REG(sfdf), 12755 MLXSW_REG(sldr), 12756 MLXSW_REG(slcr), 12757 MLXSW_REG(slcor), 12758 MLXSW_REG(spmlr), 12759 MLXSW_REG(svfa), 12760 MLXSW_REG(spvtr), 12761 MLXSW_REG(svpe), 12762 MLXSW_REG(sfmr), 12763 MLXSW_REG(spvmlr), 12764 MLXSW_REG(spvc), 12765 MLXSW_REG(spevet), 12766 MLXSW_REG(smpe), 12767 MLXSW_REG(smid2), 12768 MLXSW_REG(cwtp), 12769 MLXSW_REG(cwtpm), 12770 MLXSW_REG(pgcr), 12771 MLXSW_REG(ppbt), 12772 MLXSW_REG(pacl), 12773 MLXSW_REG(pagt), 12774 MLXSW_REG(ptar), 12775 MLXSW_REG(ppbs), 12776 MLXSW_REG(prcr), 12777 MLXSW_REG(pefa), 12778 MLXSW_REG(pemrbt), 12779 MLXSW_REG(ptce2), 12780 MLXSW_REG(perpt), 12781 MLXSW_REG(peabfe), 12782 MLXSW_REG(perar), 12783 MLXSW_REG(ptce3), 12784 MLXSW_REG(percr), 12785 MLXSW_REG(pererp), 12786 MLXSW_REG(iedr), 12787 MLXSW_REG(qpts), 12788 MLXSW_REG(qpcr), 12789 MLXSW_REG(qtct), 12790 MLXSW_REG(qeec), 12791 MLXSW_REG(qrwe), 12792 MLXSW_REG(qpdsm), 12793 MLXSW_REG(qpdp), 12794 MLXSW_REG(qpdpm), 12795 MLXSW_REG(qtctm), 12796 MLXSW_REG(qpsc), 12797 MLXSW_REG(pmlp), 12798 MLXSW_REG(pmtu), 12799 MLXSW_REG(ptys), 12800 MLXSW_REG(ppad), 12801 MLXSW_REG(paos), 12802 MLXSW_REG(pfcc), 12803 MLXSW_REG(ppcnt), 12804 MLXSW_REG(pptb), 12805 MLXSW_REG(pbmc), 12806 MLXSW_REG(pspa), 12807 MLXSW_REG(pmaos), 12808 MLXSW_REG(pplr), 12809 MLXSW_REG(pmtdb), 12810 MLXSW_REG(pmecr), 12811 MLXSW_REG(pmpe), 12812 MLXSW_REG(pddr), 12813 MLXSW_REG(pmmp), 12814 MLXSW_REG(pllp), 12815 MLXSW_REG(pmtm), 12816 MLXSW_REG(htgt), 12817 MLXSW_REG(hpkt), 12818 MLXSW_REG(rgcr), 12819 MLXSW_REG(ritr), 12820 MLXSW_REG(rtar), 12821 MLXSW_REG(ratr), 12822 MLXSW_REG(rtdp), 12823 MLXSW_REG(rips), 12824 MLXSW_REG(ratrad), 12825 MLXSW_REG(rdpm), 12826 MLXSW_REG(ricnt), 12827 MLXSW_REG(rrcr), 12828 MLXSW_REG(ralta), 12829 MLXSW_REG(ralst), 12830 MLXSW_REG(raltb), 12831 MLXSW_REG(ralue), 12832 MLXSW_REG(rauht), 12833 MLXSW_REG(raleu), 12834 MLXSW_REG(rauhtd), 12835 MLXSW_REG(rigr2), 12836 MLXSW_REG(recr2), 12837 MLXSW_REG(rmft2), 12838 MLXSW_REG(reiv), 12839 MLXSW_REG(mfcr), 12840 MLXSW_REG(mfsc), 12841 MLXSW_REG(mfsm), 12842 MLXSW_REG(mfsl), 12843 MLXSW_REG(fore), 12844 MLXSW_REG(mtcap), 12845 MLXSW_REG(mtmp), 12846 MLXSW_REG(mtwe), 12847 MLXSW_REG(mtbr), 12848 MLXSW_REG(mcia), 12849 MLXSW_REG(mpat), 12850 MLXSW_REG(mpar), 12851 MLXSW_REG(mgir), 12852 MLXSW_REG(mrsr), 12853 MLXSW_REG(mlcr), 12854 MLXSW_REG(mcion), 12855 MLXSW_REG(mtpps), 12856 MLXSW_REG(mtutc), 12857 MLXSW_REG(mpsc), 12858 MLXSW_REG(mcqi), 12859 MLXSW_REG(mcc), 12860 MLXSW_REG(mcda), 12861 MLXSW_REG(mgpc), 12862 MLXSW_REG(mprs), 12863 MLXSW_REG(mogcr), 12864 MLXSW_REG(mpagr), 12865 MLXSW_REG(momte), 12866 MLXSW_REG(mtpppc), 12867 MLXSW_REG(mtpptr), 12868 MLXSW_REG(mtptpt), 12869 MLXSW_REG(mtpcpc), 12870 MLXSW_REG(mfgd), 12871 MLXSW_REG(mgpir), 12872 MLXSW_REG(mbct), 12873 MLXSW_REG(mddt), 12874 MLXSW_REG(mddq), 12875 MLXSW_REG(mddc), 12876 MLXSW_REG(mfde), 12877 MLXSW_REG(tngcr), 12878 MLXSW_REG(tnumt), 12879 MLXSW_REG(tnqcr), 12880 MLXSW_REG(tnqdr), 12881 MLXSW_REG(tneem), 12882 MLXSW_REG(tndem), 12883 MLXSW_REG(tnpc), 12884 MLXSW_REG(tigcr), 12885 MLXSW_REG(tieem), 12886 MLXSW_REG(tidem), 12887 MLXSW_REG(sbpr), 12888 MLXSW_REG(sbcm), 12889 MLXSW_REG(sbpm), 12890 MLXSW_REG(sbmm), 12891 MLXSW_REG(sbsr), 12892 MLXSW_REG(sbib), 12893 }; 12894 12895 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12896 { 12897 const struct mlxsw_reg_info *reg_info; 12898 int i; 12899 12900 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12901 reg_info = mlxsw_reg_infos[i]; 12902 if (reg_info->id == reg_id) 12903 return reg_info->name; 12904 } 12905 return "*UNKNOWN*"; 12906 } 12907 12908 /* PUDE - Port Up / Down Event 12909 * --------------------------- 12910 * Reports the operational state change of a port. 12911 */ 12912 #define MLXSW_REG_PUDE_LEN 0x10 12913 12914 /* reg_pude_swid 12915 * Switch partition ID with which to associate the port. 12916 * Access: Index 12917 */ 12918 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12919 12920 /* reg_pude_local_port 12921 * Local port number. 12922 * Access: Index 12923 */ 12924 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12925 12926 /* reg_pude_admin_status 12927 * Port administrative state (the desired state). 12928 * 1 - Up. 12929 * 2 - Down. 12930 * 3 - Up once. This means that in case of link failure, the port won't go 12931 * into polling mode, but will wait to be re-enabled by software. 12932 * 4 - Disabled by system. Can only be set by hardware. 12933 * Access: RO 12934 */ 12935 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12936 12937 /* reg_pude_oper_status 12938 * Port operatioanl state. 12939 * 1 - Up. 12940 * 2 - Down. 12941 * 3 - Down by port failure. This means that the device will not let the 12942 * port up again until explicitly specified by software. 12943 * Access: RO 12944 */ 12945 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12946 12947 #endif 12948