1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com> 8 * Copyright (c) 2017-2018 Petr Machata <petrm@mellanox.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the names of the copyright holders nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MLXSW_REG_H 40 #define _MLXSW_REG_H 41 42 #include <linux/kernel.h> 43 #include <linux/string.h> 44 #include <linux/bitops.h> 45 #include <linux/if_vlan.h> 46 47 #include "item.h" 48 #include "port.h" 49 50 struct mlxsw_reg_info { 51 u16 id; 52 u16 len; /* In u8 */ 53 const char *name; 54 }; 55 56 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 57 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 58 .id = _id, \ 59 .len = _len, \ 60 .name = #_name, \ 61 } 62 63 #define MLXSW_REG(type) (&mlxsw_reg_##type) 64 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 65 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 66 67 /* SGCR - Switch General Configuration Register 68 * -------------------------------------------- 69 * This register is used for configuration of the switch capabilities. 70 */ 71 #define MLXSW_REG_SGCR_ID 0x2000 72 #define MLXSW_REG_SGCR_LEN 0x10 73 74 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 75 76 /* reg_sgcr_llb 77 * Link Local Broadcast (Default=0) 78 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 79 * packets and ignore the IGMP snooping entries. 80 * Access: RW 81 */ 82 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 83 84 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 85 { 86 MLXSW_REG_ZERO(sgcr, payload); 87 mlxsw_reg_sgcr_llb_set(payload, !!llb); 88 } 89 90 /* SPAD - Switch Physical Address Register 91 * --------------------------------------- 92 * The SPAD register configures the switch physical MAC address. 93 */ 94 #define MLXSW_REG_SPAD_ID 0x2002 95 #define MLXSW_REG_SPAD_LEN 0x10 96 97 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 98 99 /* reg_spad_base_mac 100 * Base MAC address for the switch partitions. 101 * Per switch partition MAC address is equal to: 102 * base_mac + swid 103 * Access: RW 104 */ 105 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 106 107 /* SMID - Switch Multicast ID 108 * -------------------------- 109 * The MID record maps from a MID (Multicast ID), which is a unique identifier 110 * of the multicast group within the stacking domain, into a list of local 111 * ports into which the packet is replicated. 112 */ 113 #define MLXSW_REG_SMID_ID 0x2007 114 #define MLXSW_REG_SMID_LEN 0x240 115 116 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 117 118 /* reg_smid_swid 119 * Switch partition ID. 120 * Access: Index 121 */ 122 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 123 124 /* reg_smid_mid 125 * Multicast identifier - global identifier that represents the multicast group 126 * across all devices. 127 * Access: Index 128 */ 129 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 130 131 /* reg_smid_port 132 * Local port memebership (1 bit per port). 133 * Access: RW 134 */ 135 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 136 137 /* reg_smid_port_mask 138 * Local port mask (1 bit per port). 139 * Access: W 140 */ 141 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 142 143 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 144 u8 port, bool set) 145 { 146 MLXSW_REG_ZERO(smid, payload); 147 mlxsw_reg_smid_swid_set(payload, 0); 148 mlxsw_reg_smid_mid_set(payload, mid); 149 mlxsw_reg_smid_port_set(payload, port, set); 150 mlxsw_reg_smid_port_mask_set(payload, port, 1); 151 } 152 153 /* SSPR - Switch System Port Record Register 154 * ----------------------------------------- 155 * Configures the system port to local port mapping. 156 */ 157 #define MLXSW_REG_SSPR_ID 0x2008 158 #define MLXSW_REG_SSPR_LEN 0x8 159 160 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 161 162 /* reg_sspr_m 163 * Master - if set, then the record describes the master system port. 164 * This is needed in case a local port is mapped into several system ports 165 * (for multipathing). That number will be reported as the source system 166 * port when packets are forwarded to the CPU. Only one master port is allowed 167 * per local port. 168 * 169 * Note: Must be set for Spectrum. 170 * Access: RW 171 */ 172 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 173 174 /* reg_sspr_local_port 175 * Local port number. 176 * 177 * Access: RW 178 */ 179 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 180 181 /* reg_sspr_sub_port 182 * Virtual port within the physical port. 183 * Should be set to 0 when virtual ports are not enabled on the port. 184 * 185 * Access: RW 186 */ 187 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 188 189 /* reg_sspr_system_port 190 * Unique identifier within the stacking domain that represents all the ports 191 * that are available in the system (external ports). 192 * 193 * Currently, only single-ASIC configurations are supported, so we default to 194 * 1:1 mapping between system ports and local ports. 195 * Access: Index 196 */ 197 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 198 199 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 200 { 201 MLXSW_REG_ZERO(sspr, payload); 202 mlxsw_reg_sspr_m_set(payload, 1); 203 mlxsw_reg_sspr_local_port_set(payload, local_port); 204 mlxsw_reg_sspr_sub_port_set(payload, 0); 205 mlxsw_reg_sspr_system_port_set(payload, local_port); 206 } 207 208 /* SFDAT - Switch Filtering Database Aging Time 209 * -------------------------------------------- 210 * Controls the Switch aging time. Aging time is able to be set per Switch 211 * Partition. 212 */ 213 #define MLXSW_REG_SFDAT_ID 0x2009 214 #define MLXSW_REG_SFDAT_LEN 0x8 215 216 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 217 218 /* reg_sfdat_swid 219 * Switch partition ID. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 223 224 /* reg_sfdat_age_time 225 * Aging time in seconds 226 * Min - 10 seconds 227 * Max - 1,000,000 seconds 228 * Default is 300 seconds. 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 232 233 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 234 { 235 MLXSW_REG_ZERO(sfdat, payload); 236 mlxsw_reg_sfdat_swid_set(payload, 0); 237 mlxsw_reg_sfdat_age_time_set(payload, age_time); 238 } 239 240 /* SFD - Switch Filtering Database 241 * ------------------------------- 242 * The following register defines the access to the filtering database. 243 * The register supports querying, adding, removing and modifying the database. 244 * The access is optimized for bulk updates in which case more than one 245 * FDB record is present in the same command. 246 */ 247 #define MLXSW_REG_SFD_ID 0x200A 248 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 249 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 250 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 251 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 252 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 253 254 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 255 256 /* reg_sfd_swid 257 * Switch partition ID for queries. Reserved on Write. 258 * Access: Index 259 */ 260 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 261 262 enum mlxsw_reg_sfd_op { 263 /* Dump entire FDB a (process according to record_locator) */ 264 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 265 /* Query records by {MAC, VID/FID} value */ 266 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 267 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 268 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 269 /* Test. Response indicates if each of the records could be 270 * added to the FDB. 271 */ 272 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 273 /* Add/modify. Aged-out records cannot be added. This command removes 274 * the learning notification of the {MAC, VID/FID}. Response includes 275 * the entries that were added to the FDB. 276 */ 277 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 278 /* Remove record by {MAC, VID/FID}. This command also removes 279 * the learning notification and aged-out notifications 280 * of the {MAC, VID/FID}. The response provides current (pre-removal) 281 * entries as non-aged-out. 282 */ 283 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 284 /* Remove learned notification by {MAC, VID/FID}. The response provides 285 * the removed learning notification. 286 */ 287 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 288 }; 289 290 /* reg_sfd_op 291 * Operation. 292 * Access: OP 293 */ 294 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 295 296 /* reg_sfd_record_locator 297 * Used for querying the FDB. Use record_locator=0 to initiate the 298 * query. When a record is returned, a new record_locator is 299 * returned to be used in the subsequent query. 300 * Reserved for database update. 301 * Access: Index 302 */ 303 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 304 305 /* reg_sfd_num_rec 306 * Request: Number of records to read/add/modify/remove 307 * Response: Number of records read/added/replaced/removed 308 * See above description for more details. 309 * Ranges 0..64 310 * Access: RW 311 */ 312 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 313 314 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 315 u32 record_locator) 316 { 317 MLXSW_REG_ZERO(sfd, payload); 318 mlxsw_reg_sfd_op_set(payload, op); 319 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 320 } 321 322 /* reg_sfd_rec_swid 323 * Switch partition ID. 324 * Access: Index 325 */ 326 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 327 MLXSW_REG_SFD_REC_LEN, 0x00, false); 328 329 enum mlxsw_reg_sfd_rec_type { 330 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 331 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 332 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 333 }; 334 335 /* reg_sfd_rec_type 336 * FDB record type. 337 * Access: RW 338 */ 339 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 340 MLXSW_REG_SFD_REC_LEN, 0x00, false); 341 342 enum mlxsw_reg_sfd_rec_policy { 343 /* Replacement disabled, aging disabled. */ 344 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 345 /* (mlag remote): Replacement enabled, aging disabled, 346 * learning notification enabled on this port. 347 */ 348 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 349 /* (ingress device): Replacement enabled, aging enabled. */ 350 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 351 }; 352 353 /* reg_sfd_rec_policy 354 * Policy. 355 * Access: RW 356 */ 357 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 358 MLXSW_REG_SFD_REC_LEN, 0x00, false); 359 360 /* reg_sfd_rec_a 361 * Activity. Set for new static entries. Set for static entries if a frame SMAC 362 * lookup hits on the entry. 363 * To clear the a bit, use "query and clear activity" op. 364 * Access: RO 365 */ 366 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 367 MLXSW_REG_SFD_REC_LEN, 0x00, false); 368 369 /* reg_sfd_rec_mac 370 * MAC address. 371 * Access: Index 372 */ 373 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 374 MLXSW_REG_SFD_REC_LEN, 0x02); 375 376 enum mlxsw_reg_sfd_rec_action { 377 /* forward */ 378 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 379 /* forward and trap, trap_id is FDB_TRAP */ 380 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 381 /* trap and do not forward, trap_id is FDB_TRAP */ 382 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 383 /* forward to IP router */ 384 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 385 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 386 }; 387 388 /* reg_sfd_rec_action 389 * Action to apply on the packet. 390 * Note: Dynamic entries can only be configured with NOP action. 391 * Access: RW 392 */ 393 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 394 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 395 396 /* reg_sfd_uc_sub_port 397 * VEPA channel on local port. 398 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 399 * VEPA is not enabled. 400 * Access: RW 401 */ 402 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 403 MLXSW_REG_SFD_REC_LEN, 0x08, false); 404 405 /* reg_sfd_uc_fid_vid 406 * Filtering ID or VLAN ID 407 * For SwitchX and SwitchX-2: 408 * - Dynamic entries (policy 2,3) use FID 409 * - Static entries (policy 0) use VID 410 * - When independent learning is configured, VID=FID 411 * For Spectrum: use FID for both Dynamic and Static entries. 412 * VID should not be used. 413 * Access: Index 414 */ 415 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 416 MLXSW_REG_SFD_REC_LEN, 0x08, false); 417 418 /* reg_sfd_uc_system_port 419 * Unique port identifier for the final destination of the packet. 420 * Access: RW 421 */ 422 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 423 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 424 425 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 426 enum mlxsw_reg_sfd_rec_type rec_type, 427 const char *mac, 428 enum mlxsw_reg_sfd_rec_action action) 429 { 430 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 431 432 if (rec_index >= num_rec) 433 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 434 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 435 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 436 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 437 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 438 } 439 440 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 441 enum mlxsw_reg_sfd_rec_policy policy, 442 const char *mac, u16 fid_vid, 443 enum mlxsw_reg_sfd_rec_action action, 444 u8 local_port) 445 { 446 mlxsw_reg_sfd_rec_pack(payload, rec_index, 447 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 448 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 449 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 450 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 451 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 452 } 453 454 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 455 char *mac, u16 *p_fid_vid, 456 u8 *p_local_port) 457 { 458 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 459 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 460 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 461 } 462 463 /* reg_sfd_uc_lag_sub_port 464 * LAG sub port. 465 * Must be 0 if multichannel VEPA is not enabled. 466 * Access: RW 467 */ 468 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 469 MLXSW_REG_SFD_REC_LEN, 0x08, false); 470 471 /* reg_sfd_uc_lag_fid_vid 472 * Filtering ID or VLAN ID 473 * For SwitchX and SwitchX-2: 474 * - Dynamic entries (policy 2,3) use FID 475 * - Static entries (policy 0) use VID 476 * - When independent learning is configured, VID=FID 477 * For Spectrum: use FID for both Dynamic and Static entries. 478 * VID should not be used. 479 * Access: Index 480 */ 481 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 482 MLXSW_REG_SFD_REC_LEN, 0x08, false); 483 484 /* reg_sfd_uc_lag_lag_vid 485 * Indicates VID in case of vFIDs. Reserved for FIDs. 486 * Access: RW 487 */ 488 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 489 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 490 491 /* reg_sfd_uc_lag_lag_id 492 * LAG Identifier - pointer into the LAG descriptor table. 493 * Access: RW 494 */ 495 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 496 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 497 498 static inline void 499 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 500 enum mlxsw_reg_sfd_rec_policy policy, 501 const char *mac, u16 fid_vid, 502 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 503 u16 lag_id) 504 { 505 mlxsw_reg_sfd_rec_pack(payload, rec_index, 506 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 507 mac, action); 508 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 509 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 510 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 511 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 512 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 513 } 514 515 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 516 char *mac, u16 *p_vid, 517 u16 *p_lag_id) 518 { 519 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 520 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 521 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 522 } 523 524 /* reg_sfd_mc_pgi 525 * 526 * Multicast port group index - index into the port group table. 527 * Value 0x1FFF indicates the pgi should point to the MID entry. 528 * For Spectrum this value must be set to 0x1FFF 529 * Access: RW 530 */ 531 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 532 MLXSW_REG_SFD_REC_LEN, 0x08, false); 533 534 /* reg_sfd_mc_fid_vid 535 * 536 * Filtering ID or VLAN ID 537 * Access: Index 538 */ 539 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 540 MLXSW_REG_SFD_REC_LEN, 0x08, false); 541 542 /* reg_sfd_mc_mid 543 * 544 * Multicast identifier - global identifier that represents the multicast 545 * group across all devices. 546 * Access: RW 547 */ 548 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 549 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 550 551 static inline void 552 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 553 const char *mac, u16 fid_vid, 554 enum mlxsw_reg_sfd_rec_action action, u16 mid) 555 { 556 mlxsw_reg_sfd_rec_pack(payload, rec_index, 557 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 558 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 559 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 560 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 561 } 562 563 /* SFN - Switch FDB Notification Register 564 * ------------------------------------------- 565 * The switch provides notifications on newly learned FDB entries and 566 * aged out entries. The notifications can be polled by software. 567 */ 568 #define MLXSW_REG_SFN_ID 0x200B 569 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 570 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 571 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 572 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 573 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 574 575 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 576 577 /* reg_sfn_swid 578 * Switch partition ID. 579 * Access: Index 580 */ 581 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 582 583 /* reg_sfn_end 584 * Forces the current session to end. 585 * Access: OP 586 */ 587 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 588 589 /* reg_sfn_num_rec 590 * Request: Number of learned notifications and aged-out notification 591 * records requested. 592 * Response: Number of notification records returned (must be smaller 593 * than or equal to the value requested) 594 * Ranges 0..64 595 * Access: OP 596 */ 597 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 598 599 static inline void mlxsw_reg_sfn_pack(char *payload) 600 { 601 MLXSW_REG_ZERO(sfn, payload); 602 mlxsw_reg_sfn_swid_set(payload, 0); 603 mlxsw_reg_sfn_end_set(payload, 1); 604 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 605 } 606 607 /* reg_sfn_rec_swid 608 * Switch partition ID. 609 * Access: RO 610 */ 611 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 612 MLXSW_REG_SFN_REC_LEN, 0x00, false); 613 614 enum mlxsw_reg_sfn_rec_type { 615 /* MAC addresses learned on a regular port. */ 616 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 617 /* MAC addresses learned on a LAG port. */ 618 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 619 /* Aged-out MAC address on a regular port. */ 620 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 621 /* Aged-out MAC address on a LAG port. */ 622 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 623 }; 624 625 /* reg_sfn_rec_type 626 * Notification record type. 627 * Access: RO 628 */ 629 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 630 MLXSW_REG_SFN_REC_LEN, 0x00, false); 631 632 /* reg_sfn_rec_mac 633 * MAC address. 634 * Access: RO 635 */ 636 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 637 MLXSW_REG_SFN_REC_LEN, 0x02); 638 639 /* reg_sfn_mac_sub_port 640 * VEPA channel on the local port. 641 * 0 if multichannel VEPA is not enabled. 642 * Access: RO 643 */ 644 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 645 MLXSW_REG_SFN_REC_LEN, 0x08, false); 646 647 /* reg_sfn_mac_fid 648 * Filtering identifier. 649 * Access: RO 650 */ 651 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 652 MLXSW_REG_SFN_REC_LEN, 0x08, false); 653 654 /* reg_sfn_mac_system_port 655 * Unique port identifier for the final destination of the packet. 656 * Access: RO 657 */ 658 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 659 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 660 661 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 662 char *mac, u16 *p_vid, 663 u8 *p_local_port) 664 { 665 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 666 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 667 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 668 } 669 670 /* reg_sfn_mac_lag_lag_id 671 * LAG ID (pointer into the LAG descriptor table). 672 * Access: RO 673 */ 674 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 675 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 676 677 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 678 char *mac, u16 *p_vid, 679 u16 *p_lag_id) 680 { 681 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 682 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 683 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 684 } 685 686 /* SPMS - Switch Port MSTP/RSTP State Register 687 * ------------------------------------------- 688 * Configures the spanning tree state of a physical port. 689 */ 690 #define MLXSW_REG_SPMS_ID 0x200D 691 #define MLXSW_REG_SPMS_LEN 0x404 692 693 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 694 695 /* reg_spms_local_port 696 * Local port number. 697 * Access: Index 698 */ 699 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 700 701 enum mlxsw_reg_spms_state { 702 MLXSW_REG_SPMS_STATE_NO_CHANGE, 703 MLXSW_REG_SPMS_STATE_DISCARDING, 704 MLXSW_REG_SPMS_STATE_LEARNING, 705 MLXSW_REG_SPMS_STATE_FORWARDING, 706 }; 707 708 /* reg_spms_state 709 * Spanning tree state of each VLAN ID (VID) of the local port. 710 * 0 - Do not change spanning tree state (used only when writing). 711 * 1 - Discarding. No learning or forwarding to/from this port (default). 712 * 2 - Learning. Port is learning, but not forwarding. 713 * 3 - Forwarding. Port is learning and forwarding. 714 * Access: RW 715 */ 716 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 717 718 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 719 { 720 MLXSW_REG_ZERO(spms, payload); 721 mlxsw_reg_spms_local_port_set(payload, local_port); 722 } 723 724 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 725 enum mlxsw_reg_spms_state state) 726 { 727 mlxsw_reg_spms_state_set(payload, vid, state); 728 } 729 730 /* SPVID - Switch Port VID 731 * ----------------------- 732 * The switch port VID configures the default VID for a port. 733 */ 734 #define MLXSW_REG_SPVID_ID 0x200E 735 #define MLXSW_REG_SPVID_LEN 0x08 736 737 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 738 739 /* reg_spvid_local_port 740 * Local port number. 741 * Access: Index 742 */ 743 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 744 745 /* reg_spvid_sub_port 746 * Virtual port within the physical port. 747 * Should be set to 0 when virtual ports are not enabled on the port. 748 * Access: Index 749 */ 750 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 751 752 /* reg_spvid_pvid 753 * Port default VID 754 * Access: RW 755 */ 756 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 757 758 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 759 { 760 MLXSW_REG_ZERO(spvid, payload); 761 mlxsw_reg_spvid_local_port_set(payload, local_port); 762 mlxsw_reg_spvid_pvid_set(payload, pvid); 763 } 764 765 /* SPVM - Switch Port VLAN Membership 766 * ---------------------------------- 767 * The Switch Port VLAN Membership register configures the VLAN membership 768 * of a port in a VLAN denoted by VID. VLAN membership is managed per 769 * virtual port. The register can be used to add and remove VID(s) from a port. 770 */ 771 #define MLXSW_REG_SPVM_ID 0x200F 772 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 773 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 774 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 775 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 776 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 777 778 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 779 780 /* reg_spvm_pt 781 * Priority tagged. If this bit is set, packets forwarded to the port with 782 * untagged VLAN membership (u bit is set) will be tagged with priority tag 783 * (VID=0) 784 * Access: RW 785 */ 786 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 787 788 /* reg_spvm_pte 789 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 790 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 791 * Access: WO 792 */ 793 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 794 795 /* reg_spvm_local_port 796 * Local port number. 797 * Access: Index 798 */ 799 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 800 801 /* reg_spvm_sub_port 802 * Virtual port within the physical port. 803 * Should be set to 0 when virtual ports are not enabled on the port. 804 * Access: Index 805 */ 806 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 807 808 /* reg_spvm_num_rec 809 * Number of records to update. Each record contains: i, e, u, vid. 810 * Access: OP 811 */ 812 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 813 814 /* reg_spvm_rec_i 815 * Ingress membership in VLAN ID. 816 * Access: Index 817 */ 818 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 819 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 820 MLXSW_REG_SPVM_REC_LEN, 0, false); 821 822 /* reg_spvm_rec_e 823 * Egress membership in VLAN ID. 824 * Access: Index 825 */ 826 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 827 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 828 MLXSW_REG_SPVM_REC_LEN, 0, false); 829 830 /* reg_spvm_rec_u 831 * Untagged - port is an untagged member - egress transmission uses untagged 832 * frames on VID<n> 833 * Access: Index 834 */ 835 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 836 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 837 MLXSW_REG_SPVM_REC_LEN, 0, false); 838 839 /* reg_spvm_rec_vid 840 * Egress membership in VLAN ID. 841 * Access: Index 842 */ 843 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 844 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 845 MLXSW_REG_SPVM_REC_LEN, 0, false); 846 847 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 848 u16 vid_begin, u16 vid_end, 849 bool is_member, bool untagged) 850 { 851 int size = vid_end - vid_begin + 1; 852 int i; 853 854 MLXSW_REG_ZERO(spvm, payload); 855 mlxsw_reg_spvm_local_port_set(payload, local_port); 856 mlxsw_reg_spvm_num_rec_set(payload, size); 857 858 for (i = 0; i < size; i++) { 859 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 860 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 861 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 862 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 863 } 864 } 865 866 /* SPAFT - Switch Port Acceptable Frame Types 867 * ------------------------------------------ 868 * The Switch Port Acceptable Frame Types register configures the frame 869 * admittance of the port. 870 */ 871 #define MLXSW_REG_SPAFT_ID 0x2010 872 #define MLXSW_REG_SPAFT_LEN 0x08 873 874 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 875 876 /* reg_spaft_local_port 877 * Local port number. 878 * Access: Index 879 * 880 * Note: CPU port is not supported (all tag types are allowed). 881 */ 882 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 883 884 /* reg_spaft_sub_port 885 * Virtual port within the physical port. 886 * Should be set to 0 when virtual ports are not enabled on the port. 887 * Access: RW 888 */ 889 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 890 891 /* reg_spaft_allow_untagged 892 * When set, untagged frames on the ingress are allowed (default). 893 * Access: RW 894 */ 895 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 896 897 /* reg_spaft_allow_prio_tagged 898 * When set, priority tagged frames on the ingress are allowed (default). 899 * Access: RW 900 */ 901 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 902 903 /* reg_spaft_allow_tagged 904 * When set, tagged frames on the ingress are allowed (default). 905 * Access: RW 906 */ 907 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 908 909 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 910 bool allow_untagged) 911 { 912 MLXSW_REG_ZERO(spaft, payload); 913 mlxsw_reg_spaft_local_port_set(payload, local_port); 914 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 915 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 916 mlxsw_reg_spaft_allow_tagged_set(payload, true); 917 } 918 919 /* SFGC - Switch Flooding Group Configuration 920 * ------------------------------------------ 921 * The following register controls the association of flooding tables and MIDs 922 * to packet types used for flooding. 923 */ 924 #define MLXSW_REG_SFGC_ID 0x2011 925 #define MLXSW_REG_SFGC_LEN 0x10 926 927 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 928 929 enum mlxsw_reg_sfgc_type { 930 MLXSW_REG_SFGC_TYPE_BROADCAST, 931 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 932 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 933 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 934 MLXSW_REG_SFGC_TYPE_RESERVED, 935 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 936 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 937 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 938 MLXSW_REG_SFGC_TYPE_MAX, 939 }; 940 941 /* reg_sfgc_type 942 * The traffic type to reach the flooding table. 943 * Access: Index 944 */ 945 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 946 947 enum mlxsw_reg_sfgc_bridge_type { 948 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 949 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 950 }; 951 952 /* reg_sfgc_bridge_type 953 * Access: Index 954 * 955 * Note: SwitchX-2 only supports 802.1Q mode. 956 */ 957 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 958 959 enum mlxsw_flood_table_type { 960 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 961 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 962 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 963 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 964 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 965 }; 966 967 /* reg_sfgc_table_type 968 * See mlxsw_flood_table_type 969 * Access: RW 970 * 971 * Note: FID offset and FID types are not supported in SwitchX-2. 972 */ 973 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 974 975 /* reg_sfgc_flood_table 976 * Flooding table index to associate with the specific type on the specific 977 * switch partition. 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 981 982 /* reg_sfgc_mid 983 * The multicast ID for the swid. Not supported for Spectrum 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 987 988 /* reg_sfgc_counter_set_type 989 * Counter Set Type for flow counters. 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 993 994 /* reg_sfgc_counter_index 995 * Counter Index for flow counters. 996 * Access: RW 997 */ 998 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 999 1000 static inline void 1001 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1002 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1003 enum mlxsw_flood_table_type table_type, 1004 unsigned int flood_table) 1005 { 1006 MLXSW_REG_ZERO(sfgc, payload); 1007 mlxsw_reg_sfgc_type_set(payload, type); 1008 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1009 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1010 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1011 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1012 } 1013 1014 /* SFTR - Switch Flooding Table Register 1015 * ------------------------------------- 1016 * The switch flooding table is used for flooding packet replication. The table 1017 * defines a bit mask of ports for packet replication. 1018 */ 1019 #define MLXSW_REG_SFTR_ID 0x2012 1020 #define MLXSW_REG_SFTR_LEN 0x420 1021 1022 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1023 1024 /* reg_sftr_swid 1025 * Switch partition ID with which to associate the port. 1026 * Access: Index 1027 */ 1028 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1029 1030 /* reg_sftr_flood_table 1031 * Flooding table index to associate with the specific type on the specific 1032 * switch partition. 1033 * Access: Index 1034 */ 1035 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1036 1037 /* reg_sftr_index 1038 * Index. Used as an index into the Flooding Table in case the table is 1039 * configured to use VID / FID or FID Offset. 1040 * Access: Index 1041 */ 1042 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1043 1044 /* reg_sftr_table_type 1045 * See mlxsw_flood_table_type 1046 * Access: RW 1047 */ 1048 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1049 1050 /* reg_sftr_range 1051 * Range of entries to update 1052 * Access: Index 1053 */ 1054 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1055 1056 /* reg_sftr_port 1057 * Local port membership (1 bit per port). 1058 * Access: RW 1059 */ 1060 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1061 1062 /* reg_sftr_cpu_port_mask 1063 * CPU port mask (1 bit per port). 1064 * Access: W 1065 */ 1066 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1067 1068 static inline void mlxsw_reg_sftr_pack(char *payload, 1069 unsigned int flood_table, 1070 unsigned int index, 1071 enum mlxsw_flood_table_type table_type, 1072 unsigned int range, u8 port, bool set) 1073 { 1074 MLXSW_REG_ZERO(sftr, payload); 1075 mlxsw_reg_sftr_swid_set(payload, 0); 1076 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1077 mlxsw_reg_sftr_index_set(payload, index); 1078 mlxsw_reg_sftr_table_type_set(payload, table_type); 1079 mlxsw_reg_sftr_range_set(payload, range); 1080 mlxsw_reg_sftr_port_set(payload, port, set); 1081 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1082 } 1083 1084 /* SFDF - Switch Filtering DB Flush 1085 * -------------------------------- 1086 * The switch filtering DB flush register is used to flush the FDB. 1087 * Note that FDB notifications are flushed as well. 1088 */ 1089 #define MLXSW_REG_SFDF_ID 0x2013 1090 #define MLXSW_REG_SFDF_LEN 0x14 1091 1092 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1093 1094 /* reg_sfdf_swid 1095 * Switch partition ID. 1096 * Access: Index 1097 */ 1098 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1099 1100 enum mlxsw_reg_sfdf_flush_type { 1101 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1102 MLXSW_REG_SFDF_FLUSH_PER_FID, 1103 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1104 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1105 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1106 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1107 }; 1108 1109 /* reg_sfdf_flush_type 1110 * Flush type. 1111 * 0 - All SWID dynamic entries are flushed. 1112 * 1 - All FID dynamic entries are flushed. 1113 * 2 - All dynamic entries pointing to port are flushed. 1114 * 3 - All FID dynamic entries pointing to port are flushed. 1115 * 4 - All dynamic entries pointing to LAG are flushed. 1116 * 5 - All FID dynamic entries pointing to LAG are flushed. 1117 * Access: RW 1118 */ 1119 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1120 1121 /* reg_sfdf_flush_static 1122 * Static. 1123 * 0 - Flush only dynamic entries. 1124 * 1 - Flush both dynamic and static entries. 1125 * Access: RW 1126 */ 1127 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1128 1129 static inline void mlxsw_reg_sfdf_pack(char *payload, 1130 enum mlxsw_reg_sfdf_flush_type type) 1131 { 1132 MLXSW_REG_ZERO(sfdf, payload); 1133 mlxsw_reg_sfdf_flush_type_set(payload, type); 1134 mlxsw_reg_sfdf_flush_static_set(payload, true); 1135 } 1136 1137 /* reg_sfdf_fid 1138 * FID to flush. 1139 * Access: RW 1140 */ 1141 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1142 1143 /* reg_sfdf_system_port 1144 * Port to flush. 1145 * Access: RW 1146 */ 1147 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1148 1149 /* reg_sfdf_port_fid_system_port 1150 * Port to flush, pointed to by FID. 1151 * Access: RW 1152 */ 1153 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1154 1155 /* reg_sfdf_lag_id 1156 * LAG ID to flush. 1157 * Access: RW 1158 */ 1159 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1160 1161 /* reg_sfdf_lag_fid_lag_id 1162 * LAG ID to flush, pointed to by FID. 1163 * Access: RW 1164 */ 1165 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1166 1167 /* SLDR - Switch LAG Descriptor Register 1168 * ----------------------------------------- 1169 * The switch LAG descriptor register is populated by LAG descriptors. 1170 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1171 * max_lag-1. 1172 */ 1173 #define MLXSW_REG_SLDR_ID 0x2014 1174 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1175 1176 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1177 1178 enum mlxsw_reg_sldr_op { 1179 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1180 MLXSW_REG_SLDR_OP_LAG_CREATE, 1181 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1182 /* Ports that appear in the list have the Distributor enabled */ 1183 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1184 /* Removes ports from the disributor list */ 1185 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1186 }; 1187 1188 /* reg_sldr_op 1189 * Operation. 1190 * Access: RW 1191 */ 1192 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1193 1194 /* reg_sldr_lag_id 1195 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1196 * Access: Index 1197 */ 1198 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1199 1200 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1201 { 1202 MLXSW_REG_ZERO(sldr, payload); 1203 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1204 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1205 } 1206 1207 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1208 { 1209 MLXSW_REG_ZERO(sldr, payload); 1210 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1211 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1212 } 1213 1214 /* reg_sldr_num_ports 1215 * The number of member ports of the LAG. 1216 * Reserved for Create / Destroy operations 1217 * For Add / Remove operations - indicates the number of ports in the list. 1218 * Access: RW 1219 */ 1220 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1221 1222 /* reg_sldr_system_port 1223 * System port. 1224 * Access: RW 1225 */ 1226 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1227 1228 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1229 u8 local_port) 1230 { 1231 MLXSW_REG_ZERO(sldr, payload); 1232 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1233 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1234 mlxsw_reg_sldr_num_ports_set(payload, 1); 1235 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1236 } 1237 1238 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1239 u8 local_port) 1240 { 1241 MLXSW_REG_ZERO(sldr, payload); 1242 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1243 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1244 mlxsw_reg_sldr_num_ports_set(payload, 1); 1245 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1246 } 1247 1248 /* SLCR - Switch LAG Configuration 2 Register 1249 * ------------------------------------------- 1250 * The Switch LAG Configuration register is used for configuring the 1251 * LAG properties of the switch. 1252 */ 1253 #define MLXSW_REG_SLCR_ID 0x2015 1254 #define MLXSW_REG_SLCR_LEN 0x10 1255 1256 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1257 1258 enum mlxsw_reg_slcr_pp { 1259 /* Global Configuration (for all ports) */ 1260 MLXSW_REG_SLCR_PP_GLOBAL, 1261 /* Per port configuration, based on local_port field */ 1262 MLXSW_REG_SLCR_PP_PER_PORT, 1263 }; 1264 1265 /* reg_slcr_pp 1266 * Per Port Configuration 1267 * Note: Reading at Global mode results in reading port 1 configuration. 1268 * Access: Index 1269 */ 1270 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1271 1272 /* reg_slcr_local_port 1273 * Local port number 1274 * Supported from CPU port 1275 * Not supported from router port 1276 * Reserved when pp = Global Configuration 1277 * Access: Index 1278 */ 1279 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1280 1281 enum mlxsw_reg_slcr_type { 1282 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1283 MLXSW_REG_SLCR_TYPE_XOR, 1284 MLXSW_REG_SLCR_TYPE_RANDOM, 1285 }; 1286 1287 /* reg_slcr_type 1288 * Hash type 1289 * Access: RW 1290 */ 1291 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1292 1293 /* Ingress port */ 1294 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1295 /* SMAC - for IPv4 and IPv6 packets */ 1296 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1297 /* SMAC - for non-IP packets */ 1298 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1299 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1300 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1301 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1302 /* DMAC - for IPv4 and IPv6 packets */ 1303 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1304 /* DMAC - for non-IP packets */ 1305 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1306 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1307 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1308 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1309 /* Ethertype - for IPv4 and IPv6 packets */ 1310 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1311 /* Ethertype - for non-IP packets */ 1312 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1313 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1314 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1315 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1316 /* VLAN ID - for IPv4 and IPv6 packets */ 1317 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1318 /* VLAN ID - for non-IP packets */ 1319 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1320 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1321 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1322 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1323 /* Source IP address (can be IPv4 or IPv6) */ 1324 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1325 /* Destination IP address (can be IPv4 or IPv6) */ 1326 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1327 /* TCP/UDP source port */ 1328 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1329 /* TCP/UDP destination port*/ 1330 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1331 /* IPv4 Protocol/IPv6 Next Header */ 1332 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1333 /* IPv6 Flow label */ 1334 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1335 /* SID - FCoE source ID */ 1336 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1337 /* DID - FCoE destination ID */ 1338 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1339 /* OXID - FCoE originator exchange ID */ 1340 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1341 /* Destination QP number - for RoCE packets */ 1342 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1343 1344 /* reg_slcr_lag_hash 1345 * LAG hashing configuration. This is a bitmask, in which each set 1346 * bit includes the corresponding item in the LAG hash calculation. 1347 * The default lag_hash contains SMAC, DMAC, VLANID and 1348 * Ethertype (for all packet types). 1349 * Access: RW 1350 */ 1351 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1352 1353 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1354 { 1355 MLXSW_REG_ZERO(slcr, payload); 1356 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1357 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1358 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1359 } 1360 1361 /* SLCOR - Switch LAG Collector Register 1362 * ------------------------------------- 1363 * The Switch LAG Collector register controls the Local Port membership 1364 * in a LAG and enablement of the collector. 1365 */ 1366 #define MLXSW_REG_SLCOR_ID 0x2016 1367 #define MLXSW_REG_SLCOR_LEN 0x10 1368 1369 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1370 1371 enum mlxsw_reg_slcor_col { 1372 /* Port is added with collector disabled */ 1373 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1374 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1375 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1376 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1377 }; 1378 1379 /* reg_slcor_col 1380 * Collector configuration 1381 * Access: RW 1382 */ 1383 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1384 1385 /* reg_slcor_local_port 1386 * Local port number 1387 * Not supported for CPU port 1388 * Access: Index 1389 */ 1390 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1391 1392 /* reg_slcor_lag_id 1393 * LAG Identifier. Index into the LAG descriptor table. 1394 * Access: Index 1395 */ 1396 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1397 1398 /* reg_slcor_port_index 1399 * Port index in the LAG list. Only valid on Add Port to LAG col. 1400 * Valid range is from 0 to cap_max_lag_members-1 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1404 1405 static inline void mlxsw_reg_slcor_pack(char *payload, 1406 u8 local_port, u16 lag_id, 1407 enum mlxsw_reg_slcor_col col) 1408 { 1409 MLXSW_REG_ZERO(slcor, payload); 1410 mlxsw_reg_slcor_col_set(payload, col); 1411 mlxsw_reg_slcor_local_port_set(payload, local_port); 1412 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1413 } 1414 1415 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1416 u8 local_port, u16 lag_id, 1417 u8 port_index) 1418 { 1419 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1420 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1421 mlxsw_reg_slcor_port_index_set(payload, port_index); 1422 } 1423 1424 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1425 u8 local_port, u16 lag_id) 1426 { 1427 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1428 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1429 } 1430 1431 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1432 u8 local_port, u16 lag_id) 1433 { 1434 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1435 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1436 } 1437 1438 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1439 u8 local_port, u16 lag_id) 1440 { 1441 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1442 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1443 } 1444 1445 /* SPMLR - Switch Port MAC Learning Register 1446 * ----------------------------------------- 1447 * Controls the Switch MAC learning policy per port. 1448 */ 1449 #define MLXSW_REG_SPMLR_ID 0x2018 1450 #define MLXSW_REG_SPMLR_LEN 0x8 1451 1452 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1453 1454 /* reg_spmlr_local_port 1455 * Local port number. 1456 * Access: Index 1457 */ 1458 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1459 1460 /* reg_spmlr_sub_port 1461 * Virtual port within the physical port. 1462 * Should be set to 0 when virtual ports are not enabled on the port. 1463 * Access: Index 1464 */ 1465 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1466 1467 enum mlxsw_reg_spmlr_learn_mode { 1468 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1469 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1470 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1471 }; 1472 1473 /* reg_spmlr_learn_mode 1474 * Learning mode on the port. 1475 * 0 - Learning disabled. 1476 * 2 - Learning enabled. 1477 * 3 - Security mode. 1478 * 1479 * In security mode the switch does not learn MACs on the port, but uses the 1480 * SMAC to see if it exists on another ingress port. If so, the packet is 1481 * classified as a bad packet and is discarded unless the software registers 1482 * to receive port security error packets usign HPKT. 1483 */ 1484 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1485 1486 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1487 enum mlxsw_reg_spmlr_learn_mode mode) 1488 { 1489 MLXSW_REG_ZERO(spmlr, payload); 1490 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1491 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1492 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1493 } 1494 1495 /* SVFA - Switch VID to FID Allocation Register 1496 * -------------------------------------------- 1497 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1498 * virtualized ports. 1499 */ 1500 #define MLXSW_REG_SVFA_ID 0x201C 1501 #define MLXSW_REG_SVFA_LEN 0x10 1502 1503 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1504 1505 /* reg_svfa_swid 1506 * Switch partition ID. 1507 * Access: Index 1508 */ 1509 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1510 1511 /* reg_svfa_local_port 1512 * Local port number. 1513 * Access: Index 1514 * 1515 * Note: Reserved for 802.1Q FIDs. 1516 */ 1517 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1518 1519 enum mlxsw_reg_svfa_mt { 1520 MLXSW_REG_SVFA_MT_VID_TO_FID, 1521 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1522 }; 1523 1524 /* reg_svfa_mapping_table 1525 * Mapping table: 1526 * 0 - VID to FID 1527 * 1 - {Port, VID} to FID 1528 * Access: Index 1529 * 1530 * Note: Reserved for SwitchX-2. 1531 */ 1532 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1533 1534 /* reg_svfa_v 1535 * Valid. 1536 * Valid if set. 1537 * Access: RW 1538 * 1539 * Note: Reserved for SwitchX-2. 1540 */ 1541 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1542 1543 /* reg_svfa_fid 1544 * Filtering ID. 1545 * Access: RW 1546 */ 1547 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1548 1549 /* reg_svfa_vid 1550 * VLAN ID. 1551 * Access: Index 1552 */ 1553 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1554 1555 /* reg_svfa_counter_set_type 1556 * Counter set type for flow counters. 1557 * Access: RW 1558 * 1559 * Note: Reserved for SwitchX-2. 1560 */ 1561 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1562 1563 /* reg_svfa_counter_index 1564 * Counter index for flow counters. 1565 * Access: RW 1566 * 1567 * Note: Reserved for SwitchX-2. 1568 */ 1569 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1570 1571 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1572 enum mlxsw_reg_svfa_mt mt, bool valid, 1573 u16 fid, u16 vid) 1574 { 1575 MLXSW_REG_ZERO(svfa, payload); 1576 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1577 mlxsw_reg_svfa_swid_set(payload, 0); 1578 mlxsw_reg_svfa_local_port_set(payload, local_port); 1579 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1580 mlxsw_reg_svfa_v_set(payload, valid); 1581 mlxsw_reg_svfa_fid_set(payload, fid); 1582 mlxsw_reg_svfa_vid_set(payload, vid); 1583 } 1584 1585 /* SVPE - Switch Virtual-Port Enabling Register 1586 * -------------------------------------------- 1587 * Enables port virtualization. 1588 */ 1589 #define MLXSW_REG_SVPE_ID 0x201E 1590 #define MLXSW_REG_SVPE_LEN 0x4 1591 1592 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1593 1594 /* reg_svpe_local_port 1595 * Local port number 1596 * Access: Index 1597 * 1598 * Note: CPU port is not supported (uses VLAN mode only). 1599 */ 1600 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1601 1602 /* reg_svpe_vp_en 1603 * Virtual port enable. 1604 * 0 - Disable, VLAN mode (VID to FID). 1605 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1606 * Access: RW 1607 */ 1608 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1609 1610 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1611 bool enable) 1612 { 1613 MLXSW_REG_ZERO(svpe, payload); 1614 mlxsw_reg_svpe_local_port_set(payload, local_port); 1615 mlxsw_reg_svpe_vp_en_set(payload, enable); 1616 } 1617 1618 /* SFMR - Switch FID Management Register 1619 * ------------------------------------- 1620 * Creates and configures FIDs. 1621 */ 1622 #define MLXSW_REG_SFMR_ID 0x201F 1623 #define MLXSW_REG_SFMR_LEN 0x18 1624 1625 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1626 1627 enum mlxsw_reg_sfmr_op { 1628 MLXSW_REG_SFMR_OP_CREATE_FID, 1629 MLXSW_REG_SFMR_OP_DESTROY_FID, 1630 }; 1631 1632 /* reg_sfmr_op 1633 * Operation. 1634 * 0 - Create or edit FID. 1635 * 1 - Destroy FID. 1636 * Access: WO 1637 */ 1638 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1639 1640 /* reg_sfmr_fid 1641 * Filtering ID. 1642 * Access: Index 1643 */ 1644 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1645 1646 /* reg_sfmr_fid_offset 1647 * FID offset. 1648 * Used to point into the flooding table selected by SFGC register if 1649 * the table is of type FID-Offset. Otherwise, this field is reserved. 1650 * Access: RW 1651 */ 1652 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1653 1654 /* reg_sfmr_vtfp 1655 * Valid Tunnel Flood Pointer. 1656 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1657 * Access: RW 1658 * 1659 * Note: Reserved for 802.1Q FIDs. 1660 */ 1661 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1662 1663 /* reg_sfmr_nve_tunnel_flood_ptr 1664 * Underlay Flooding and BC Pointer. 1665 * Used as a pointer to the first entry of the group based link lists of 1666 * flooding or BC entries (for NVE tunnels). 1667 * Access: RW 1668 */ 1669 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1670 1671 /* reg_sfmr_vv 1672 * VNI Valid. 1673 * If not set, then vni is reserved. 1674 * Access: RW 1675 * 1676 * Note: Reserved for 802.1Q FIDs. 1677 */ 1678 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1679 1680 /* reg_sfmr_vni 1681 * Virtual Network Identifier. 1682 * Access: RW 1683 * 1684 * Note: A given VNI can only be assigned to one FID. 1685 */ 1686 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1687 1688 static inline void mlxsw_reg_sfmr_pack(char *payload, 1689 enum mlxsw_reg_sfmr_op op, u16 fid, 1690 u16 fid_offset) 1691 { 1692 MLXSW_REG_ZERO(sfmr, payload); 1693 mlxsw_reg_sfmr_op_set(payload, op); 1694 mlxsw_reg_sfmr_fid_set(payload, fid); 1695 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1696 mlxsw_reg_sfmr_vtfp_set(payload, false); 1697 mlxsw_reg_sfmr_vv_set(payload, false); 1698 } 1699 1700 /* SPVMLR - Switch Port VLAN MAC Learning Register 1701 * ----------------------------------------------- 1702 * Controls the switch MAC learning policy per {Port, VID}. 1703 */ 1704 #define MLXSW_REG_SPVMLR_ID 0x2020 1705 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1706 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1707 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1708 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1709 MLXSW_REG_SPVMLR_REC_LEN * \ 1710 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1711 1712 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1713 1714 /* reg_spvmlr_local_port 1715 * Local ingress port. 1716 * Access: Index 1717 * 1718 * Note: CPU port is not supported. 1719 */ 1720 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1721 1722 /* reg_spvmlr_num_rec 1723 * Number of records to update. 1724 * Access: OP 1725 */ 1726 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1727 1728 /* reg_spvmlr_rec_learn_enable 1729 * 0 - Disable learning for {Port, VID}. 1730 * 1 - Enable learning for {Port, VID}. 1731 * Access: RW 1732 */ 1733 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1734 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1735 1736 /* reg_spvmlr_rec_vid 1737 * VLAN ID to be added/removed from port or for querying. 1738 * Access: Index 1739 */ 1740 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1741 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1742 1743 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1744 u16 vid_begin, u16 vid_end, 1745 bool learn_enable) 1746 { 1747 int num_rec = vid_end - vid_begin + 1; 1748 int i; 1749 1750 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1751 1752 MLXSW_REG_ZERO(spvmlr, payload); 1753 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1754 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1755 1756 for (i = 0; i < num_rec; i++) { 1757 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1758 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1759 } 1760 } 1761 1762 /* CWTP - Congetion WRED ECN TClass Profile 1763 * ---------------------------------------- 1764 * Configures the profiles for queues of egress port and traffic class 1765 */ 1766 #define MLXSW_REG_CWTP_ID 0x2802 1767 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1768 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1769 #define MLXSW_REG_CWTP_LEN 0x40 1770 1771 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1772 1773 /* reg_cwtp_local_port 1774 * Local port number 1775 * Not supported for CPU port 1776 * Access: Index 1777 */ 1778 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1779 1780 /* reg_cwtp_traffic_class 1781 * Traffic Class to configure 1782 * Access: Index 1783 */ 1784 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1785 1786 /* reg_cwtp_profile_min 1787 * Minimum Average Queue Size of the profile in cells. 1788 * Access: RW 1789 */ 1790 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1791 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1792 1793 /* reg_cwtp_profile_percent 1794 * Percentage of WRED and ECN marking for maximum Average Queue size 1795 * Range is 0 to 100, units of integer percentage 1796 * Access: RW 1797 */ 1798 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1799 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1800 1801 /* reg_cwtp_profile_max 1802 * Maximum Average Queue size of the profile in cells 1803 * Access: RW 1804 */ 1805 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1806 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1807 1808 #define MLXSW_REG_CWTP_MIN_VALUE 64 1809 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1810 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1811 1812 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1813 u8 traffic_class) 1814 { 1815 int i; 1816 1817 MLXSW_REG_ZERO(cwtp, payload); 1818 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1819 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1820 1821 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1822 mlxsw_reg_cwtp_profile_min_set(payload, i, 1823 MLXSW_REG_CWTP_MIN_VALUE); 1824 mlxsw_reg_cwtp_profile_max_set(payload, i, 1825 MLXSW_REG_CWTP_MIN_VALUE); 1826 } 1827 } 1828 1829 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1830 1831 static inline void 1832 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1833 u32 probability) 1834 { 1835 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1836 1837 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1838 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1839 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1840 } 1841 1842 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1843 * --------------------------------------------------- 1844 * The CWTPM register maps each egress port and traffic class to profile num. 1845 */ 1846 #define MLXSW_REG_CWTPM_ID 0x2803 1847 #define MLXSW_REG_CWTPM_LEN 0x44 1848 1849 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1850 1851 /* reg_cwtpm_local_port 1852 * Local port number 1853 * Not supported for CPU port 1854 * Access: Index 1855 */ 1856 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1857 1858 /* reg_cwtpm_traffic_class 1859 * Traffic Class to configure 1860 * Access: Index 1861 */ 1862 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1863 1864 /* reg_cwtpm_ew 1865 * Control enablement of WRED for traffic class: 1866 * 0 - Disable 1867 * 1 - Enable 1868 * Access: RW 1869 */ 1870 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1871 1872 /* reg_cwtpm_ee 1873 * Control enablement of ECN for traffic class: 1874 * 0 - Disable 1875 * 1 - Enable 1876 * Access: RW 1877 */ 1878 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1879 1880 /* reg_cwtpm_tcp_g 1881 * TCP Green Profile. 1882 * Index of the profile within {port, traffic class} to use. 1883 * 0 for disabling both WRED and ECN for this type of traffic. 1884 * Access: RW 1885 */ 1886 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1887 1888 /* reg_cwtpm_tcp_y 1889 * TCP Yellow Profile. 1890 * Index of the profile within {port, traffic class} to use. 1891 * 0 for disabling both WRED and ECN for this type of traffic. 1892 * Access: RW 1893 */ 1894 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1895 1896 /* reg_cwtpm_tcp_r 1897 * TCP Red Profile. 1898 * Index of the profile within {port, traffic class} to use. 1899 * 0 for disabling both WRED and ECN for this type of traffic. 1900 * Access: RW 1901 */ 1902 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 1903 1904 /* reg_cwtpm_ntcp_g 1905 * Non-TCP Green Profile. 1906 * Index of the profile within {port, traffic class} to use. 1907 * 0 for disabling both WRED and ECN for this type of traffic. 1908 * Access: RW 1909 */ 1910 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 1911 1912 /* reg_cwtpm_ntcp_y 1913 * Non-TCP Yellow Profile. 1914 * Index of the profile within {port, traffic class} to use. 1915 * 0 for disabling both WRED and ECN for this type of traffic. 1916 * Access: RW 1917 */ 1918 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 1919 1920 /* reg_cwtpm_ntcp_r 1921 * Non-TCP Red Profile. 1922 * Index of the profile within {port, traffic class} to use. 1923 * 0 for disabling both WRED and ECN for this type of traffic. 1924 * Access: RW 1925 */ 1926 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 1927 1928 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 1929 1930 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 1931 u8 traffic_class, u8 profile, 1932 bool wred, bool ecn) 1933 { 1934 MLXSW_REG_ZERO(cwtpm, payload); 1935 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 1936 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 1937 mlxsw_reg_cwtpm_ew_set(payload, wred); 1938 mlxsw_reg_cwtpm_ee_set(payload, ecn); 1939 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 1940 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 1941 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 1942 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 1943 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 1944 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 1945 } 1946 1947 /* PGCR - Policy-Engine General Configuration Register 1948 * --------------------------------------------------- 1949 * This register configures general Policy-Engine settings. 1950 */ 1951 #define MLXSW_REG_PGCR_ID 0x3001 1952 #define MLXSW_REG_PGCR_LEN 0x20 1953 1954 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 1955 1956 /* reg_pgcr_default_action_pointer_base 1957 * Default action pointer base. Each region has a default action pointer 1958 * which is equal to default_action_pointer_base + region_id. 1959 * Access: RW 1960 */ 1961 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 1962 1963 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 1964 { 1965 MLXSW_REG_ZERO(pgcr, payload); 1966 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 1967 } 1968 1969 /* PPBT - Policy-Engine Port Binding Table 1970 * --------------------------------------- 1971 * This register is used for configuration of the Port Binding Table. 1972 */ 1973 #define MLXSW_REG_PPBT_ID 0x3002 1974 #define MLXSW_REG_PPBT_LEN 0x14 1975 1976 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 1977 1978 enum mlxsw_reg_pxbt_e { 1979 MLXSW_REG_PXBT_E_IACL, 1980 MLXSW_REG_PXBT_E_EACL, 1981 }; 1982 1983 /* reg_ppbt_e 1984 * Access: Index 1985 */ 1986 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 1987 1988 enum mlxsw_reg_pxbt_op { 1989 MLXSW_REG_PXBT_OP_BIND, 1990 MLXSW_REG_PXBT_OP_UNBIND, 1991 }; 1992 1993 /* reg_ppbt_op 1994 * Access: RW 1995 */ 1996 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 1997 1998 /* reg_ppbt_local_port 1999 * Local port. Not including CPU port. 2000 * Access: Index 2001 */ 2002 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2003 2004 /* reg_ppbt_g 2005 * group - When set, the binding is of an ACL group. When cleared, 2006 * the binding is of an ACL. 2007 * Must be set to 1 for Spectrum. 2008 * Access: RW 2009 */ 2010 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2011 2012 /* reg_ppbt_acl_info 2013 * ACL/ACL group identifier. If the g bit is set, this field should hold 2014 * the acl_group_id, else it should hold the acl_id. 2015 * Access: RW 2016 */ 2017 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2018 2019 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2020 enum mlxsw_reg_pxbt_op op, 2021 u8 local_port, u16 acl_info) 2022 { 2023 MLXSW_REG_ZERO(ppbt, payload); 2024 mlxsw_reg_ppbt_e_set(payload, e); 2025 mlxsw_reg_ppbt_op_set(payload, op); 2026 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2027 mlxsw_reg_ppbt_g_set(payload, true); 2028 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2029 } 2030 2031 /* PACL - Policy-Engine ACL Register 2032 * --------------------------------- 2033 * This register is used for configuration of the ACL. 2034 */ 2035 #define MLXSW_REG_PACL_ID 0x3004 2036 #define MLXSW_REG_PACL_LEN 0x70 2037 2038 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2039 2040 /* reg_pacl_v 2041 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2042 * while the ACL is bounded to either a port, VLAN or ACL rule. 2043 * Access: RW 2044 */ 2045 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2046 2047 /* reg_pacl_acl_id 2048 * An identifier representing the ACL (managed by software) 2049 * Range 0 .. cap_max_acl_regions - 1 2050 * Access: Index 2051 */ 2052 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2053 2054 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2055 2056 /* reg_pacl_tcam_region_info 2057 * Opaque object that represents a TCAM region. 2058 * Obtained through PTAR register. 2059 * Access: RW 2060 */ 2061 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2062 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2063 2064 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2065 bool valid, const char *tcam_region_info) 2066 { 2067 MLXSW_REG_ZERO(pacl, payload); 2068 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2069 mlxsw_reg_pacl_v_set(payload, valid); 2070 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2071 } 2072 2073 /* PAGT - Policy-Engine ACL Group Table 2074 * ------------------------------------ 2075 * This register is used for configuration of the ACL Group Table. 2076 */ 2077 #define MLXSW_REG_PAGT_ID 0x3005 2078 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2079 #define MLXSW_REG_PAGT_ACL_LEN 4 2080 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2081 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2082 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2083 2084 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2085 2086 /* reg_pagt_size 2087 * Number of ACLs in the group. 2088 * Size 0 invalidates a group. 2089 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2090 * Total number of ACLs in all groups must be lower or equal 2091 * to cap_max_acl_tot_groups 2092 * Note: a group which is binded must not be invalidated 2093 * Access: Index 2094 */ 2095 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2096 2097 /* reg_pagt_acl_group_id 2098 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2099 * the ACL Group identifier (managed by software). 2100 * Access: Index 2101 */ 2102 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2103 2104 /* reg_pagt_acl_id 2105 * ACL identifier 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2109 2110 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2111 { 2112 MLXSW_REG_ZERO(pagt, payload); 2113 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2114 } 2115 2116 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2117 u16 acl_id) 2118 { 2119 u8 size = mlxsw_reg_pagt_size_get(payload); 2120 2121 if (index >= size) 2122 mlxsw_reg_pagt_size_set(payload, index + 1); 2123 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2124 } 2125 2126 /* PTAR - Policy-Engine TCAM Allocation Register 2127 * --------------------------------------------- 2128 * This register is used for allocation of regions in the TCAM. 2129 * Note: Query method is not supported on this register. 2130 */ 2131 #define MLXSW_REG_PTAR_ID 0x3006 2132 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2133 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2134 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2135 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2136 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2137 2138 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2139 2140 enum mlxsw_reg_ptar_op { 2141 /* allocate a TCAM region */ 2142 MLXSW_REG_PTAR_OP_ALLOC, 2143 /* resize a TCAM region */ 2144 MLXSW_REG_PTAR_OP_RESIZE, 2145 /* deallocate TCAM region */ 2146 MLXSW_REG_PTAR_OP_FREE, 2147 /* test allocation */ 2148 MLXSW_REG_PTAR_OP_TEST, 2149 }; 2150 2151 /* reg_ptar_op 2152 * Access: OP 2153 */ 2154 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2155 2156 /* reg_ptar_action_set_type 2157 * Type of action set to be used on this region. 2158 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2159 * Access: WO 2160 */ 2161 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2162 2163 enum mlxsw_reg_ptar_key_type { 2164 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2165 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2166 }; 2167 2168 /* reg_ptar_key_type 2169 * TCAM key type for the region. 2170 * Access: WO 2171 */ 2172 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2173 2174 /* reg_ptar_region_size 2175 * TCAM region size. When allocating/resizing this is the requested size, 2176 * the response is the actual size. Note that actual size may be 2177 * larger than requested. 2178 * Allowed range 1 .. cap_max_rules-1 2179 * Reserved during op deallocate. 2180 * Access: WO 2181 */ 2182 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2183 2184 /* reg_ptar_region_id 2185 * Region identifier 2186 * Range 0 .. cap_max_regions-1 2187 * Access: Index 2188 */ 2189 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2190 2191 /* reg_ptar_tcam_region_info 2192 * Opaque object that represents the TCAM region. 2193 * Returned when allocating a region. 2194 * Provided by software for ACL generation and region deallocation and resize. 2195 * Access: RW 2196 */ 2197 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2198 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2199 2200 /* reg_ptar_flexible_key_id 2201 * Identifier of the Flexible Key. 2202 * Only valid if key_type == "FLEX_KEY" 2203 * The key size will be rounded up to one of the following values: 2204 * 9B, 18B, 36B, 54B. 2205 * This field is reserved for in resize operation. 2206 * Access: WO 2207 */ 2208 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2209 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2210 2211 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2212 enum mlxsw_reg_ptar_key_type key_type, 2213 u16 region_size, u16 region_id, 2214 const char *tcam_region_info) 2215 { 2216 MLXSW_REG_ZERO(ptar, payload); 2217 mlxsw_reg_ptar_op_set(payload, op); 2218 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2219 mlxsw_reg_ptar_key_type_set(payload, key_type); 2220 mlxsw_reg_ptar_region_size_set(payload, region_size); 2221 mlxsw_reg_ptar_region_id_set(payload, region_id); 2222 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2223 } 2224 2225 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2226 u16 key_id) 2227 { 2228 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2229 } 2230 2231 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2232 { 2233 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2234 } 2235 2236 /* PPBS - Policy-Engine Policy Based Switching Register 2237 * ---------------------------------------------------- 2238 * This register retrieves and sets Policy Based Switching Table entries. 2239 */ 2240 #define MLXSW_REG_PPBS_ID 0x300C 2241 #define MLXSW_REG_PPBS_LEN 0x14 2242 2243 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2244 2245 /* reg_ppbs_pbs_ptr 2246 * Index into the PBS table. 2247 * For Spectrum, the index points to the KVD Linear. 2248 * Access: Index 2249 */ 2250 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2251 2252 /* reg_ppbs_system_port 2253 * Unique port identifier for the final destination of the packet. 2254 * Access: RW 2255 */ 2256 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2257 2258 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2259 u16 system_port) 2260 { 2261 MLXSW_REG_ZERO(ppbs, payload); 2262 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2263 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2264 } 2265 2266 /* PRCR - Policy-Engine Rules Copy Register 2267 * ---------------------------------------- 2268 * This register is used for accessing rules within a TCAM region. 2269 */ 2270 #define MLXSW_REG_PRCR_ID 0x300D 2271 #define MLXSW_REG_PRCR_LEN 0x40 2272 2273 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2274 2275 enum mlxsw_reg_prcr_op { 2276 /* Move rules. Moves the rules from "tcam_region_info" starting 2277 * at offset "offset" to "dest_tcam_region_info" 2278 * at offset "dest_offset." 2279 */ 2280 MLXSW_REG_PRCR_OP_MOVE, 2281 /* Copy rules. Copies the rules from "tcam_region_info" starting 2282 * at offset "offset" to "dest_tcam_region_info" 2283 * at offset "dest_offset." 2284 */ 2285 MLXSW_REG_PRCR_OP_COPY, 2286 }; 2287 2288 /* reg_prcr_op 2289 * Access: OP 2290 */ 2291 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2292 2293 /* reg_prcr_offset 2294 * Offset within the source region to copy/move from. 2295 * Access: Index 2296 */ 2297 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2298 2299 /* reg_prcr_size 2300 * The number of rules to copy/move. 2301 * Access: WO 2302 */ 2303 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2304 2305 /* reg_prcr_tcam_region_info 2306 * Opaque object that represents the source TCAM region. 2307 * Access: Index 2308 */ 2309 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2310 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2311 2312 /* reg_prcr_dest_offset 2313 * Offset within the source region to copy/move to. 2314 * Access: Index 2315 */ 2316 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2317 2318 /* reg_prcr_dest_tcam_region_info 2319 * Opaque object that represents the destination TCAM region. 2320 * Access: Index 2321 */ 2322 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2323 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2324 2325 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2326 const char *src_tcam_region_info, 2327 u16 src_offset, 2328 const char *dest_tcam_region_info, 2329 u16 dest_offset, u16 size) 2330 { 2331 MLXSW_REG_ZERO(prcr, payload); 2332 mlxsw_reg_prcr_op_set(payload, op); 2333 mlxsw_reg_prcr_offset_set(payload, src_offset); 2334 mlxsw_reg_prcr_size_set(payload, size); 2335 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2336 src_tcam_region_info); 2337 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2338 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2339 dest_tcam_region_info); 2340 } 2341 2342 /* PEFA - Policy-Engine Extended Flexible Action Register 2343 * ------------------------------------------------------ 2344 * This register is used for accessing an extended flexible action entry 2345 * in the central KVD Linear Database. 2346 */ 2347 #define MLXSW_REG_PEFA_ID 0x300F 2348 #define MLXSW_REG_PEFA_LEN 0xB0 2349 2350 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2351 2352 /* reg_pefa_index 2353 * Index in the KVD Linear Centralized Database. 2354 * Access: Index 2355 */ 2356 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2357 2358 /* reg_pefa_a 2359 * Index in the KVD Linear Centralized Database. 2360 * Activity 2361 * For a new entry: set if ca=0, clear if ca=1 2362 * Set if a packet lookup has hit on the specific entry 2363 * Access: RO 2364 */ 2365 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2366 2367 /* reg_pefa_ca 2368 * Clear activity 2369 * When write: activity is according to this field 2370 * When read: after reading the activity is cleared according to ca 2371 * Access: OP 2372 */ 2373 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2374 2375 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2376 2377 /* reg_pefa_flex_action_set 2378 * Action-set to perform when rule is matched. 2379 * Must be zero padded if action set is shorter. 2380 * Access: RW 2381 */ 2382 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2383 2384 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2385 const char *flex_action_set) 2386 { 2387 MLXSW_REG_ZERO(pefa, payload); 2388 mlxsw_reg_pefa_index_set(payload, index); 2389 mlxsw_reg_pefa_ca_set(payload, ca); 2390 if (flex_action_set) 2391 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2392 flex_action_set); 2393 } 2394 2395 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2396 { 2397 *p_a = mlxsw_reg_pefa_a_get(payload); 2398 } 2399 2400 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2401 * ----------------------------------------------------- 2402 * This register is used for accessing rules within a TCAM region. 2403 * It is a new version of PTCE in order to support wider key, 2404 * mask and action within a TCAM region. This register is not supported 2405 * by SwitchX and SwitchX-2. 2406 */ 2407 #define MLXSW_REG_PTCE2_ID 0x3017 2408 #define MLXSW_REG_PTCE2_LEN 0x1D8 2409 2410 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2411 2412 /* reg_ptce2_v 2413 * Valid. 2414 * Access: RW 2415 */ 2416 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2417 2418 /* reg_ptce2_a 2419 * Activity. Set if a packet lookup has hit on the specific entry. 2420 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2421 * Access: RO 2422 */ 2423 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2424 2425 enum mlxsw_reg_ptce2_op { 2426 /* Read operation. */ 2427 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2428 /* clear on read operation. Used to read entry 2429 * and clear Activity bit. 2430 */ 2431 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2432 /* Write operation. Used to write a new entry to the table. 2433 * All R/W fields are relevant for new entry. Activity bit is set 2434 * for new entries - Note write with v = 0 will delete the entry. 2435 */ 2436 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2437 /* Update action. Only action set will be updated. */ 2438 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2439 /* Clear activity. A bit is cleared for the entry. */ 2440 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2441 }; 2442 2443 /* reg_ptce2_op 2444 * Access: OP 2445 */ 2446 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2447 2448 /* reg_ptce2_offset 2449 * Access: Index 2450 */ 2451 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2452 2453 /* reg_ptce2_priority 2454 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2455 * Note: priority does not have to be unique per rule. 2456 * Within a region, higher priority should have lower offset (no limitation 2457 * between regions in a multi-region). 2458 * Access: RW 2459 */ 2460 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2461 2462 /* reg_ptce2_tcam_region_info 2463 * Opaque object that represents the TCAM region. 2464 * Access: Index 2465 */ 2466 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2467 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2468 2469 #define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96 2470 2471 /* reg_ptce2_flex_key_blocks 2472 * ACL Key. 2473 * Access: RW 2474 */ 2475 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2476 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2477 2478 /* reg_ptce2_mask 2479 * mask- in the same size as key. A bit that is set directs the TCAM 2480 * to compare the corresponding bit in key. A bit that is clear directs 2481 * the TCAM to ignore the corresponding bit in key. 2482 * Access: RW 2483 */ 2484 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2485 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2486 2487 /* reg_ptce2_flex_action_set 2488 * ACL action set. 2489 * Access: RW 2490 */ 2491 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2492 MLXSW_REG_FLEX_ACTION_SET_LEN); 2493 2494 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2495 enum mlxsw_reg_ptce2_op op, 2496 const char *tcam_region_info, 2497 u16 offset, u32 priority) 2498 { 2499 MLXSW_REG_ZERO(ptce2, payload); 2500 mlxsw_reg_ptce2_v_set(payload, valid); 2501 mlxsw_reg_ptce2_op_set(payload, op); 2502 mlxsw_reg_ptce2_offset_set(payload, offset); 2503 mlxsw_reg_ptce2_priority_set(payload, priority); 2504 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2505 } 2506 2507 /* PERAR - Policy-Engine Region Association Register 2508 * ------------------------------------------------- 2509 * This register associates a hw region for region_id's. Changing on the fly 2510 * is supported by the device. 2511 */ 2512 #define MLXSW_REG_PERAR_ID 0x3026 2513 #define MLXSW_REG_PERAR_LEN 0x08 2514 2515 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2516 2517 /* reg_perar_region_id 2518 * Region identifier 2519 * Range 0 .. cap_max_regions-1 2520 * Access: Index 2521 */ 2522 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2523 2524 static inline unsigned int 2525 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2526 { 2527 return DIV_ROUND_UP(block_num, 4); 2528 } 2529 2530 /* reg_perar_hw_region 2531 * HW Region 2532 * Range 0 .. cap_max_regions-1 2533 * Default: hw_region = region_id 2534 * For a 8 key block region, 2 consecutive regions are used 2535 * For a 12 key block region, 3 consecutive regions are used 2536 * Access: RW 2537 */ 2538 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2539 2540 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2541 u16 hw_region) 2542 { 2543 MLXSW_REG_ZERO(perar, payload); 2544 mlxsw_reg_perar_region_id_set(payload, region_id); 2545 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2546 } 2547 2548 /* PERCR - Policy-Engine Region Configuration Register 2549 * --------------------------------------------------- 2550 * This register configures the region parameters. The region_id must be 2551 * allocated. 2552 */ 2553 #define MLXSW_REG_PERCR_ID 0x302A 2554 #define MLXSW_REG_PERCR_LEN 0x80 2555 2556 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2557 2558 /* reg_percr_region_id 2559 * Region identifier. 2560 * Range 0..cap_max_regions-1 2561 * Access: Index 2562 */ 2563 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2564 2565 /* reg_percr_atcam_ignore_prune 2566 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2567 * Access: RW 2568 */ 2569 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2570 2571 /* reg_percr_ctcam_ignore_prune 2572 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2573 * Access: RW 2574 */ 2575 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2576 2577 /* reg_percr_bf_bypass 2578 * Bloom filter bypass. 2579 * 0 - Bloom filter is used (default) 2580 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2581 * region_id or eRP. See PERPT.bf_bypass 2582 * Access: RW 2583 */ 2584 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 2585 2586 /* reg_percr_master_mask 2587 * Master mask. Logical OR mask of all masks of all rules of a region 2588 * (both A-TCAM and C-TCAM). When there are no eRPs 2589 * (erpt_pointer_valid = 0), then this provides the mask. 2590 * Access: RW 2591 */ 2592 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 2593 2594 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 2595 { 2596 MLXSW_REG_ZERO(percr, payload); 2597 mlxsw_reg_percr_region_id_set(payload, region_id); 2598 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 2599 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 2600 mlxsw_reg_percr_bf_bypass_set(payload, true); 2601 memset(payload + 0x20, 0xff, 96); 2602 } 2603 2604 /* PERERP - Policy-Engine Region eRP Register 2605 * ------------------------------------------ 2606 * This register configures the region eRP. The region_id must be 2607 * allocated. 2608 */ 2609 #define MLXSW_REG_PERERP_ID 0x302B 2610 #define MLXSW_REG_PERERP_LEN 0x1C 2611 2612 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 2613 2614 /* reg_pererp_region_id 2615 * Region identifier. 2616 * Range 0..cap_max_regions-1 2617 * Access: Index 2618 */ 2619 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 2620 2621 /* reg_pererp_ctcam_le 2622 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 2623 * Access: RW 2624 */ 2625 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 2626 2627 /* reg_pererp_erpt_pointer_valid 2628 * erpt_pointer is valid. 2629 * Access: RW 2630 */ 2631 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 2632 2633 /* reg_pererp_erpt_bank_pointer 2634 * Pointer to eRP table bank. May be modified at any time. 2635 * Range 0..cap_max_erp_table_banks-1 2636 * Reserved when erpt_pointer_valid = 0 2637 */ 2638 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 2639 2640 /* reg_pererp_erpt_pointer 2641 * Pointer to eRP table within the eRP bank. Can be changed for an 2642 * existing region. 2643 * Range 0..cap_max_erp_table_size-1 2644 * Reserved when erpt_pointer_valid = 0 2645 * Access: RW 2646 */ 2647 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 2648 2649 /* reg_pererp_erpt_vector 2650 * Vector of allowed eRP indexes starting from erpt_pointer within the 2651 * erpt_bank_pointer. Next entries will be in next bank. 2652 * Note that eRP index is used and not eRP ID. 2653 * Reserved when erpt_pointer_valid = 0 2654 * Access: RW 2655 */ 2656 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 2657 2658 /* reg_pererp_master_rp_id 2659 * Master RP ID. When there are no eRPs, then this provides the eRP ID 2660 * for the lookup. Can be changed for an existing region. 2661 * Reserved when erpt_pointer_valid = 1 2662 * Access: RW 2663 */ 2664 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 2665 2666 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id) 2667 { 2668 MLXSW_REG_ZERO(pererp, payload); 2669 mlxsw_reg_pererp_region_id_set(payload, region_id); 2670 mlxsw_reg_pererp_ctcam_le_set(payload, true); 2671 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, true); 2672 } 2673 2674 /* IEDR - Infrastructure Entry Delete Register 2675 * ---------------------------------------------------- 2676 * This register is used for deleting entries from the entry tables. 2677 * It is legitimate to attempt to delete a nonexisting entry (the device will 2678 * respond as a good flow). 2679 */ 2680 #define MLXSW_REG_IEDR_ID 0x3804 2681 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 2682 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 2683 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 2684 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 2685 MLXSW_REG_IEDR_REC_LEN * \ 2686 MLXSW_REG_IEDR_REC_MAX_COUNT) 2687 2688 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 2689 2690 /* reg_iedr_num_rec 2691 * Number of records. 2692 * Access: OP 2693 */ 2694 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 2695 2696 /* reg_iedr_rec_type 2697 * Resource type. 2698 * Access: OP 2699 */ 2700 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 2701 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 2702 2703 /* reg_iedr_rec_size 2704 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 2705 * Access: OP 2706 */ 2707 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 2708 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 2709 2710 /* reg_iedr_rec_index_start 2711 * Resource index start. 2712 * Access: OP 2713 */ 2714 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 2715 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 2716 2717 static inline void mlxsw_reg_iedr_pack(char *payload) 2718 { 2719 MLXSW_REG_ZERO(iedr, payload); 2720 } 2721 2722 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 2723 u8 rec_type, u16 rec_size, 2724 u32 rec_index_start) 2725 { 2726 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 2727 2728 if (rec_index >= num_rec) 2729 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 2730 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 2731 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 2732 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 2733 } 2734 2735 /* QPCR - QoS Policer Configuration Register 2736 * ----------------------------------------- 2737 * The QPCR register is used to create policers - that limit 2738 * the rate of bytes or packets via some trap group. 2739 */ 2740 #define MLXSW_REG_QPCR_ID 0x4004 2741 #define MLXSW_REG_QPCR_LEN 0x28 2742 2743 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 2744 2745 enum mlxsw_reg_qpcr_g { 2746 MLXSW_REG_QPCR_G_GLOBAL = 2, 2747 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 2748 }; 2749 2750 /* reg_qpcr_g 2751 * The policer type. 2752 * Access: Index 2753 */ 2754 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 2755 2756 /* reg_qpcr_pid 2757 * Policer ID. 2758 * Access: Index 2759 */ 2760 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 2761 2762 /* reg_qpcr_color_aware 2763 * Is the policer aware of colors. 2764 * Must be 0 (unaware) for cpu port. 2765 * Access: RW for unbounded policer. RO for bounded policer. 2766 */ 2767 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 2768 2769 /* reg_qpcr_bytes 2770 * Is policer limit is for bytes per sec or packets per sec. 2771 * 0 - packets 2772 * 1 - bytes 2773 * Access: RW for unbounded policer. RO for bounded policer. 2774 */ 2775 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 2776 2777 enum mlxsw_reg_qpcr_ir_units { 2778 MLXSW_REG_QPCR_IR_UNITS_M, 2779 MLXSW_REG_QPCR_IR_UNITS_K, 2780 }; 2781 2782 /* reg_qpcr_ir_units 2783 * Policer's units for cir and eir fields (for bytes limits only) 2784 * 1 - 10^3 2785 * 0 - 10^6 2786 * Access: OP 2787 */ 2788 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 2789 2790 enum mlxsw_reg_qpcr_rate_type { 2791 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 2792 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 2793 }; 2794 2795 /* reg_qpcr_rate_type 2796 * Policer can have one limit (single rate) or 2 limits with specific operation 2797 * for packets that exceed the lower rate but not the upper one. 2798 * (For cpu port must be single rate) 2799 * Access: RW for unbounded policer. RO for bounded policer. 2800 */ 2801 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 2802 2803 /* reg_qpc_cbs 2804 * Policer's committed burst size. 2805 * The policer is working with time slices of 50 nano sec. By default every 2806 * slice is granted the proportionate share of the committed rate. If we want to 2807 * allow a slice to exceed that share (while still keeping the rate per sec) we 2808 * can allow burst. The burst size is between the default proportionate share 2809 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 2810 * committed rate will result in exceeding the rate). The burst size must be a 2811 * log of 2 and will be determined by 2^cbs. 2812 * Access: RW 2813 */ 2814 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 2815 2816 /* reg_qpcr_cir 2817 * Policer's committed rate. 2818 * The rate used for sungle rate, the lower rate for double rate. 2819 * For bytes limits, the rate will be this value * the unit from ir_units. 2820 * (Resolution error is up to 1%). 2821 * Access: RW 2822 */ 2823 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 2824 2825 /* reg_qpcr_eir 2826 * Policer's exceed rate. 2827 * The higher rate for double rate, reserved for single rate. 2828 * Lower rate for double rate policer. 2829 * For bytes limits, the rate will be this value * the unit from ir_units. 2830 * (Resolution error is up to 1%). 2831 * Access: RW 2832 */ 2833 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 2834 2835 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 2836 2837 /* reg_qpcr_exceed_action. 2838 * What to do with packets between the 2 limits for double rate. 2839 * Access: RW for unbounded policer. RO for bounded policer. 2840 */ 2841 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 2842 2843 enum mlxsw_reg_qpcr_action { 2844 /* Discard */ 2845 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 2846 /* Forward and set color to red. 2847 * If the packet is intended to cpu port, it will be dropped. 2848 */ 2849 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 2850 }; 2851 2852 /* reg_qpcr_violate_action 2853 * What to do with packets that cross the cir limit (for single rate) or the eir 2854 * limit (for double rate). 2855 * Access: RW for unbounded policer. RO for bounded policer. 2856 */ 2857 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 2858 2859 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 2860 enum mlxsw_reg_qpcr_ir_units ir_units, 2861 bool bytes, u32 cir, u16 cbs) 2862 { 2863 MLXSW_REG_ZERO(qpcr, payload); 2864 mlxsw_reg_qpcr_pid_set(payload, pid); 2865 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 2866 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 2867 mlxsw_reg_qpcr_violate_action_set(payload, 2868 MLXSW_REG_QPCR_ACTION_DISCARD); 2869 mlxsw_reg_qpcr_cir_set(payload, cir); 2870 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 2871 mlxsw_reg_qpcr_bytes_set(payload, bytes); 2872 mlxsw_reg_qpcr_cbs_set(payload, cbs); 2873 } 2874 2875 /* QTCT - QoS Switch Traffic Class Table 2876 * ------------------------------------- 2877 * Configures the mapping between the packet switch priority and the 2878 * traffic class on the transmit port. 2879 */ 2880 #define MLXSW_REG_QTCT_ID 0x400A 2881 #define MLXSW_REG_QTCT_LEN 0x08 2882 2883 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 2884 2885 /* reg_qtct_local_port 2886 * Local port number. 2887 * Access: Index 2888 * 2889 * Note: CPU port is not supported. 2890 */ 2891 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 2892 2893 /* reg_qtct_sub_port 2894 * Virtual port within the physical port. 2895 * Should be set to 0 when virtual ports are not enabled on the port. 2896 * Access: Index 2897 */ 2898 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 2899 2900 /* reg_qtct_switch_prio 2901 * Switch priority. 2902 * Access: Index 2903 */ 2904 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 2905 2906 /* reg_qtct_tclass 2907 * Traffic class. 2908 * Default values: 2909 * switch_prio 0 : tclass 1 2910 * switch_prio 1 : tclass 0 2911 * switch_prio i : tclass i, for i > 1 2912 * Access: RW 2913 */ 2914 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 2915 2916 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 2917 u8 switch_prio, u8 tclass) 2918 { 2919 MLXSW_REG_ZERO(qtct, payload); 2920 mlxsw_reg_qtct_local_port_set(payload, local_port); 2921 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 2922 mlxsw_reg_qtct_tclass_set(payload, tclass); 2923 } 2924 2925 /* QEEC - QoS ETS Element Configuration Register 2926 * --------------------------------------------- 2927 * Configures the ETS elements. 2928 */ 2929 #define MLXSW_REG_QEEC_ID 0x400D 2930 #define MLXSW_REG_QEEC_LEN 0x1C 2931 2932 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 2933 2934 /* reg_qeec_local_port 2935 * Local port number. 2936 * Access: Index 2937 * 2938 * Note: CPU port is supported. 2939 */ 2940 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 2941 2942 enum mlxsw_reg_qeec_hr { 2943 MLXSW_REG_QEEC_HIERARCY_PORT, 2944 MLXSW_REG_QEEC_HIERARCY_GROUP, 2945 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2946 MLXSW_REG_QEEC_HIERARCY_TC, 2947 }; 2948 2949 /* reg_qeec_element_hierarchy 2950 * 0 - Port 2951 * 1 - Group 2952 * 2 - Subgroup 2953 * 3 - Traffic Class 2954 * Access: Index 2955 */ 2956 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 2957 2958 /* reg_qeec_element_index 2959 * The index of the element in the hierarchy. 2960 * Access: Index 2961 */ 2962 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 2963 2964 /* reg_qeec_next_element_index 2965 * The index of the next (lower) element in the hierarchy. 2966 * Access: RW 2967 * 2968 * Note: Reserved for element_hierarchy 0. 2969 */ 2970 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 2971 2972 enum { 2973 MLXSW_REG_QEEC_BYTES_MODE, 2974 MLXSW_REG_QEEC_PACKETS_MODE, 2975 }; 2976 2977 /* reg_qeec_pb 2978 * Packets or bytes mode. 2979 * 0 - Bytes mode 2980 * 1 - Packets mode 2981 * Access: RW 2982 * 2983 * Note: Used for max shaper configuration. For Spectrum, packets mode 2984 * is supported only for traffic classes of CPU port. 2985 */ 2986 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 2987 2988 /* reg_qeec_mase 2989 * Max shaper configuration enable. Enables configuration of the max 2990 * shaper on this ETS element. 2991 * 0 - Disable 2992 * 1 - Enable 2993 * Access: RW 2994 */ 2995 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 2996 2997 /* A large max rate will disable the max shaper. */ 2998 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 2999 3000 /* reg_qeec_max_shaper_rate 3001 * Max shaper information rate. 3002 * For CPU port, can only be configured for port hierarchy. 3003 * When in bytes mode, value is specified in units of 1000bps. 3004 * Access: RW 3005 */ 3006 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3007 3008 /* reg_qeec_de 3009 * DWRR configuration enable. Enables configuration of the dwrr and 3010 * dwrr_weight. 3011 * 0 - Disable 3012 * 1 - Enable 3013 * Access: RW 3014 */ 3015 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3016 3017 /* reg_qeec_dwrr 3018 * Transmission selection algorithm to use on the link going down from 3019 * the ETS element. 3020 * 0 - Strict priority 3021 * 1 - DWRR 3022 * Access: RW 3023 */ 3024 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3025 3026 /* reg_qeec_dwrr_weight 3027 * DWRR weight on the link going down from the ETS element. The 3028 * percentage of bandwidth guaranteed to an ETS element within 3029 * its hierarchy. The sum of all weights across all ETS elements 3030 * within one hierarchy should be equal to 100. Reserved when 3031 * transmission selection algorithm is strict priority. 3032 * Access: RW 3033 */ 3034 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3035 3036 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3037 enum mlxsw_reg_qeec_hr hr, u8 index, 3038 u8 next_index) 3039 { 3040 MLXSW_REG_ZERO(qeec, payload); 3041 mlxsw_reg_qeec_local_port_set(payload, local_port); 3042 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3043 mlxsw_reg_qeec_element_index_set(payload, index); 3044 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3045 } 3046 3047 /* PMLP - Ports Module to Local Port Register 3048 * ------------------------------------------ 3049 * Configures the assignment of modules to local ports. 3050 */ 3051 #define MLXSW_REG_PMLP_ID 0x5002 3052 #define MLXSW_REG_PMLP_LEN 0x40 3053 3054 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3055 3056 /* reg_pmlp_rxtx 3057 * 0 - Tx value is used for both Tx and Rx. 3058 * 1 - Rx value is taken from a separte field. 3059 * Access: RW 3060 */ 3061 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3062 3063 /* reg_pmlp_local_port 3064 * Local port number. 3065 * Access: Index 3066 */ 3067 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3068 3069 /* reg_pmlp_width 3070 * 0 - Unmap local port. 3071 * 1 - Lane 0 is used. 3072 * 2 - Lanes 0 and 1 are used. 3073 * 4 - Lanes 0, 1, 2 and 3 are used. 3074 * Access: RW 3075 */ 3076 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3077 3078 /* reg_pmlp_module 3079 * Module number. 3080 * Access: RW 3081 */ 3082 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3083 3084 /* reg_pmlp_tx_lane 3085 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3086 * Access: RW 3087 */ 3088 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3089 3090 /* reg_pmlp_rx_lane 3091 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3092 * equal to Tx lane. 3093 * Access: RW 3094 */ 3095 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3096 3097 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3098 { 3099 MLXSW_REG_ZERO(pmlp, payload); 3100 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3101 } 3102 3103 /* PMTU - Port MTU Register 3104 * ------------------------ 3105 * Configures and reports the port MTU. 3106 */ 3107 #define MLXSW_REG_PMTU_ID 0x5003 3108 #define MLXSW_REG_PMTU_LEN 0x10 3109 3110 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3111 3112 /* reg_pmtu_local_port 3113 * Local port number. 3114 * Access: Index 3115 */ 3116 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3117 3118 /* reg_pmtu_max_mtu 3119 * Maximum MTU. 3120 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3121 * reported, otherwise the minimum between the max_mtu of the different 3122 * types is reported. 3123 * Access: RO 3124 */ 3125 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3126 3127 /* reg_pmtu_admin_mtu 3128 * MTU value to set port to. Must be smaller or equal to max_mtu. 3129 * Note: If port type is Infiniband, then port must be disabled, when its 3130 * MTU is set. 3131 * Access: RW 3132 */ 3133 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3134 3135 /* reg_pmtu_oper_mtu 3136 * The actual MTU configured on the port. Packets exceeding this size 3137 * will be dropped. 3138 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3139 * oper_mtu might be smaller than admin_mtu. 3140 * Access: RO 3141 */ 3142 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3143 3144 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3145 u16 new_mtu) 3146 { 3147 MLXSW_REG_ZERO(pmtu, payload); 3148 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3149 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3150 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3151 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3152 } 3153 3154 /* PTYS - Port Type and Speed Register 3155 * ----------------------------------- 3156 * Configures and reports the port speed type. 3157 * 3158 * Note: When set while the link is up, the changes will not take effect 3159 * until the port transitions from down to up state. 3160 */ 3161 #define MLXSW_REG_PTYS_ID 0x5004 3162 #define MLXSW_REG_PTYS_LEN 0x40 3163 3164 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3165 3166 /* an_disable_admin 3167 * Auto negotiation disable administrative configuration 3168 * 0 - Device doesn't support AN disable. 3169 * 1 - Device supports AN disable. 3170 * Access: RW 3171 */ 3172 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3173 3174 /* reg_ptys_local_port 3175 * Local port number. 3176 * Access: Index 3177 */ 3178 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3179 3180 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3181 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3182 3183 /* reg_ptys_proto_mask 3184 * Protocol mask. Indicates which protocol is used. 3185 * 0 - Infiniband. 3186 * 1 - Fibre Channel. 3187 * 2 - Ethernet. 3188 * Access: Index 3189 */ 3190 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3191 3192 enum { 3193 MLXSW_REG_PTYS_AN_STATUS_NA, 3194 MLXSW_REG_PTYS_AN_STATUS_OK, 3195 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3196 }; 3197 3198 /* reg_ptys_an_status 3199 * Autonegotiation status. 3200 * Access: RO 3201 */ 3202 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3203 3204 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3205 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3206 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3207 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3208 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3209 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3210 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 3211 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 3212 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 3213 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 3214 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 3215 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 3216 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 3217 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 3218 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 3219 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 3220 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 3221 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 3222 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 3223 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 3224 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 3225 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 3226 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 3227 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 3228 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 3229 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 3230 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 3231 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 3232 3233 /* reg_ptys_eth_proto_cap 3234 * Ethernet port supported speeds and protocols. 3235 * Access: RO 3236 */ 3237 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 3238 3239 /* reg_ptys_ib_link_width_cap 3240 * IB port supported widths. 3241 * Access: RO 3242 */ 3243 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 3244 3245 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 3246 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 3247 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 3248 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 3249 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 3250 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 3251 3252 /* reg_ptys_ib_proto_cap 3253 * IB port supported speeds and protocols. 3254 * Access: RO 3255 */ 3256 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 3257 3258 /* reg_ptys_eth_proto_admin 3259 * Speed and protocol to set port to. 3260 * Access: RW 3261 */ 3262 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 3263 3264 /* reg_ptys_ib_link_width_admin 3265 * IB width to set port to. 3266 * Access: RW 3267 */ 3268 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 3269 3270 /* reg_ptys_ib_proto_admin 3271 * IB speeds and protocols to set port to. 3272 * Access: RW 3273 */ 3274 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 3275 3276 /* reg_ptys_eth_proto_oper 3277 * The current speed and protocol configured for the port. 3278 * Access: RO 3279 */ 3280 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 3281 3282 /* reg_ptys_ib_link_width_oper 3283 * The current IB width to set port to. 3284 * Access: RO 3285 */ 3286 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 3287 3288 /* reg_ptys_ib_proto_oper 3289 * The current IB speed and protocol. 3290 * Access: RO 3291 */ 3292 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 3293 3294 /* reg_ptys_eth_proto_lp_advertise 3295 * The protocols that were advertised by the link partner during 3296 * autonegotiation. 3297 * Access: RO 3298 */ 3299 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3300 3301 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3302 u32 proto_admin, bool autoneg) 3303 { 3304 MLXSW_REG_ZERO(ptys, payload); 3305 mlxsw_reg_ptys_local_port_set(payload, local_port); 3306 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 3307 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 3308 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 3309 } 3310 3311 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 3312 u32 *p_eth_proto_cap, 3313 u32 *p_eth_proto_adm, 3314 u32 *p_eth_proto_oper) 3315 { 3316 if (p_eth_proto_cap) 3317 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 3318 if (p_eth_proto_adm) 3319 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 3320 if (p_eth_proto_oper) 3321 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 3322 } 3323 3324 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 3325 u16 proto_admin, u16 link_width) 3326 { 3327 MLXSW_REG_ZERO(ptys, payload); 3328 mlxsw_reg_ptys_local_port_set(payload, local_port); 3329 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 3330 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 3331 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 3332 } 3333 3334 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 3335 u16 *p_ib_link_width_cap, 3336 u16 *p_ib_proto_oper, 3337 u16 *p_ib_link_width_oper) 3338 { 3339 if (p_ib_proto_cap) 3340 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 3341 if (p_ib_link_width_cap) 3342 *p_ib_link_width_cap = 3343 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 3344 if (p_ib_proto_oper) 3345 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 3346 if (p_ib_link_width_oper) 3347 *p_ib_link_width_oper = 3348 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 3349 } 3350 3351 /* PPAD - Port Physical Address Register 3352 * ------------------------------------- 3353 * The PPAD register configures the per port physical MAC address. 3354 */ 3355 #define MLXSW_REG_PPAD_ID 0x5005 3356 #define MLXSW_REG_PPAD_LEN 0x10 3357 3358 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 3359 3360 /* reg_ppad_single_base_mac 3361 * 0: base_mac, local port should be 0 and mac[7:0] is 3362 * reserved. HW will set incremental 3363 * 1: single_mac - mac of the local_port 3364 * Access: RW 3365 */ 3366 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 3367 3368 /* reg_ppad_local_port 3369 * port number, if single_base_mac = 0 then local_port is reserved 3370 * Access: RW 3371 */ 3372 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 3373 3374 /* reg_ppad_mac 3375 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 3376 * If single_base_mac = 1 - the per port MAC address 3377 * Access: RW 3378 */ 3379 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 3380 3381 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 3382 u8 local_port) 3383 { 3384 MLXSW_REG_ZERO(ppad, payload); 3385 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 3386 mlxsw_reg_ppad_local_port_set(payload, local_port); 3387 } 3388 3389 /* PAOS - Ports Administrative and Operational Status Register 3390 * ----------------------------------------------------------- 3391 * Configures and retrieves per port administrative and operational status. 3392 */ 3393 #define MLXSW_REG_PAOS_ID 0x5006 3394 #define MLXSW_REG_PAOS_LEN 0x10 3395 3396 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 3397 3398 /* reg_paos_swid 3399 * Switch partition ID with which to associate the port. 3400 * Note: while external ports uses unique local port numbers (and thus swid is 3401 * redundant), router ports use the same local port number where swid is the 3402 * only indication for the relevant port. 3403 * Access: Index 3404 */ 3405 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 3406 3407 /* reg_paos_local_port 3408 * Local port number. 3409 * Access: Index 3410 */ 3411 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 3412 3413 /* reg_paos_admin_status 3414 * Port administrative state (the desired state of the port): 3415 * 1 - Up. 3416 * 2 - Down. 3417 * 3 - Up once. This means that in case of link failure, the port won't go 3418 * into polling mode, but will wait to be re-enabled by software. 3419 * 4 - Disabled by system. Can only be set by hardware. 3420 * Access: RW 3421 */ 3422 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 3423 3424 /* reg_paos_oper_status 3425 * Port operational state (the current state): 3426 * 1 - Up. 3427 * 2 - Down. 3428 * 3 - Down by port failure. This means that the device will not let the 3429 * port up again until explicitly specified by software. 3430 * Access: RO 3431 */ 3432 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 3433 3434 /* reg_paos_ase 3435 * Admin state update enabled. 3436 * Access: WO 3437 */ 3438 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 3439 3440 /* reg_paos_ee 3441 * Event update enable. If this bit is set, event generation will be 3442 * updated based on the e field. 3443 * Access: WO 3444 */ 3445 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 3446 3447 /* reg_paos_e 3448 * Event generation on operational state change: 3449 * 0 - Do not generate event. 3450 * 1 - Generate Event. 3451 * 2 - Generate Single Event. 3452 * Access: RW 3453 */ 3454 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 3455 3456 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 3457 enum mlxsw_port_admin_status status) 3458 { 3459 MLXSW_REG_ZERO(paos, payload); 3460 mlxsw_reg_paos_swid_set(payload, 0); 3461 mlxsw_reg_paos_local_port_set(payload, local_port); 3462 mlxsw_reg_paos_admin_status_set(payload, status); 3463 mlxsw_reg_paos_oper_status_set(payload, 0); 3464 mlxsw_reg_paos_ase_set(payload, 1); 3465 mlxsw_reg_paos_ee_set(payload, 1); 3466 mlxsw_reg_paos_e_set(payload, 1); 3467 } 3468 3469 /* PFCC - Ports Flow Control Configuration Register 3470 * ------------------------------------------------ 3471 * Configures and retrieves the per port flow control configuration. 3472 */ 3473 #define MLXSW_REG_PFCC_ID 0x5007 3474 #define MLXSW_REG_PFCC_LEN 0x20 3475 3476 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 3477 3478 /* reg_pfcc_local_port 3479 * Local port number. 3480 * Access: Index 3481 */ 3482 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 3483 3484 /* reg_pfcc_pnat 3485 * Port number access type. Determines the way local_port is interpreted: 3486 * 0 - Local port number. 3487 * 1 - IB / label port number. 3488 * Access: Index 3489 */ 3490 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 3491 3492 /* reg_pfcc_shl_cap 3493 * Send to higher layers capabilities: 3494 * 0 - No capability of sending Pause and PFC frames to higher layers. 3495 * 1 - Device has capability of sending Pause and PFC frames to higher 3496 * layers. 3497 * Access: RO 3498 */ 3499 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 3500 3501 /* reg_pfcc_shl_opr 3502 * Send to higher layers operation: 3503 * 0 - Pause and PFC frames are handled by the port (default). 3504 * 1 - Pause and PFC frames are handled by the port and also sent to 3505 * higher layers. Only valid if shl_cap = 1. 3506 * Access: RW 3507 */ 3508 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 3509 3510 /* reg_pfcc_ppan 3511 * Pause policy auto negotiation. 3512 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 3513 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 3514 * based on the auto-negotiation resolution. 3515 * Access: RW 3516 * 3517 * Note: The auto-negotiation advertisement is set according to pptx and 3518 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 3519 */ 3520 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 3521 3522 /* reg_pfcc_prio_mask_tx 3523 * Bit per priority indicating if Tx flow control policy should be 3524 * updated based on bit pfctx. 3525 * Access: WO 3526 */ 3527 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 3528 3529 /* reg_pfcc_prio_mask_rx 3530 * Bit per priority indicating if Rx flow control policy should be 3531 * updated based on bit pfcrx. 3532 * Access: WO 3533 */ 3534 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 3535 3536 /* reg_pfcc_pptx 3537 * Admin Pause policy on Tx. 3538 * 0 - Never generate Pause frames (default). 3539 * 1 - Generate Pause frames according to Rx buffer threshold. 3540 * Access: RW 3541 */ 3542 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 3543 3544 /* reg_pfcc_aptx 3545 * Active (operational) Pause policy on Tx. 3546 * 0 - Never generate Pause frames. 3547 * 1 - Generate Pause frames according to Rx buffer threshold. 3548 * Access: RO 3549 */ 3550 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 3551 3552 /* reg_pfcc_pfctx 3553 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 3554 * 0 - Never generate priority Pause frames on the specified priority 3555 * (default). 3556 * 1 - Generate priority Pause frames according to Rx buffer threshold on 3557 * the specified priority. 3558 * Access: RW 3559 * 3560 * Note: pfctx and pptx must be mutually exclusive. 3561 */ 3562 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 3563 3564 /* reg_pfcc_pprx 3565 * Admin Pause policy on Rx. 3566 * 0 - Ignore received Pause frames (default). 3567 * 1 - Respect received Pause frames. 3568 * Access: RW 3569 */ 3570 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 3571 3572 /* reg_pfcc_aprx 3573 * Active (operational) Pause policy on Rx. 3574 * 0 - Ignore received Pause frames. 3575 * 1 - Respect received Pause frames. 3576 * Access: RO 3577 */ 3578 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 3579 3580 /* reg_pfcc_pfcrx 3581 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 3582 * 0 - Ignore incoming priority Pause frames on the specified priority 3583 * (default). 3584 * 1 - Respect incoming priority Pause frames on the specified priority. 3585 * Access: RW 3586 */ 3587 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 3588 3589 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 3590 3591 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 3592 { 3593 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3594 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3595 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 3596 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 3597 } 3598 3599 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 3600 { 3601 MLXSW_REG_ZERO(pfcc, payload); 3602 mlxsw_reg_pfcc_local_port_set(payload, local_port); 3603 } 3604 3605 /* PPCNT - Ports Performance Counters Register 3606 * ------------------------------------------- 3607 * The PPCNT register retrieves per port performance counters. 3608 */ 3609 #define MLXSW_REG_PPCNT_ID 0x5008 3610 #define MLXSW_REG_PPCNT_LEN 0x100 3611 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 3612 3613 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 3614 3615 /* reg_ppcnt_swid 3616 * For HCA: must be always 0. 3617 * Switch partition ID to associate port with. 3618 * Switch partitions are numbered from 0 to 7 inclusively. 3619 * Switch partition 254 indicates stacking ports. 3620 * Switch partition 255 indicates all switch partitions. 3621 * Only valid on Set() operation with local_port=255. 3622 * Access: Index 3623 */ 3624 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 3625 3626 /* reg_ppcnt_local_port 3627 * Local port number. 3628 * 255 indicates all ports on the device, and is only allowed 3629 * for Set() operation. 3630 * Access: Index 3631 */ 3632 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 3633 3634 /* reg_ppcnt_pnat 3635 * Port number access type: 3636 * 0 - Local port number 3637 * 1 - IB port number 3638 * Access: Index 3639 */ 3640 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 3641 3642 enum mlxsw_reg_ppcnt_grp { 3643 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 3644 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 3645 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 3646 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 3647 MLXSW_REG_PPCNT_TC_CNT = 0x11, 3648 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 3649 }; 3650 3651 /* reg_ppcnt_grp 3652 * Performance counter group. 3653 * Group 63 indicates all groups. Only valid on Set() operation with 3654 * clr bit set. 3655 * 0x0: IEEE 802.3 Counters 3656 * 0x1: RFC 2863 Counters 3657 * 0x2: RFC 2819 Counters 3658 * 0x3: RFC 3635 Counters 3659 * 0x5: Ethernet Extended Counters 3660 * 0x8: Link Level Retransmission Counters 3661 * 0x10: Per Priority Counters 3662 * 0x11: Per Traffic Class Counters 3663 * 0x12: Physical Layer Counters 3664 * 0x13: Per Traffic Class Congestion Counters 3665 * Access: Index 3666 */ 3667 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 3668 3669 /* reg_ppcnt_clr 3670 * Clear counters. Setting the clr bit will reset the counter value 3671 * for all counters in the counter group. This bit can be set 3672 * for both Set() and Get() operation. 3673 * Access: OP 3674 */ 3675 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 3676 3677 /* reg_ppcnt_prio_tc 3678 * Priority for counter set that support per priority, valid values: 0-7. 3679 * Traffic class for counter set that support per traffic class, 3680 * valid values: 0- cap_max_tclass-1 . 3681 * For HCA: cap_max_tclass is always 8. 3682 * Otherwise must be 0. 3683 * Access: Index 3684 */ 3685 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 3686 3687 /* Ethernet IEEE 802.3 Counter Group */ 3688 3689 /* reg_ppcnt_a_frames_transmitted_ok 3690 * Access: RO 3691 */ 3692 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 3693 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3694 3695 /* reg_ppcnt_a_frames_received_ok 3696 * Access: RO 3697 */ 3698 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 3699 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3700 3701 /* reg_ppcnt_a_frame_check_sequence_errors 3702 * Access: RO 3703 */ 3704 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 3705 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 3706 3707 /* reg_ppcnt_a_alignment_errors 3708 * Access: RO 3709 */ 3710 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 3711 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 3712 3713 /* reg_ppcnt_a_octets_transmitted_ok 3714 * Access: RO 3715 */ 3716 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 3717 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3718 3719 /* reg_ppcnt_a_octets_received_ok 3720 * Access: RO 3721 */ 3722 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 3723 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3724 3725 /* reg_ppcnt_a_multicast_frames_xmitted_ok 3726 * Access: RO 3727 */ 3728 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 3729 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 3730 3731 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 3732 * Access: RO 3733 */ 3734 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 3735 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 3736 3737 /* reg_ppcnt_a_multicast_frames_received_ok 3738 * Access: RO 3739 */ 3740 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 3741 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 3742 3743 /* reg_ppcnt_a_broadcast_frames_received_ok 3744 * Access: RO 3745 */ 3746 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 3747 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3748 3749 /* reg_ppcnt_a_in_range_length_errors 3750 * Access: RO 3751 */ 3752 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 3753 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3754 3755 /* reg_ppcnt_a_out_of_range_length_field 3756 * Access: RO 3757 */ 3758 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 3759 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3760 3761 /* reg_ppcnt_a_frame_too_long_errors 3762 * Access: RO 3763 */ 3764 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 3765 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3766 3767 /* reg_ppcnt_a_symbol_error_during_carrier 3768 * Access: RO 3769 */ 3770 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 3771 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3772 3773 /* reg_ppcnt_a_mac_control_frames_transmitted 3774 * Access: RO 3775 */ 3776 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 3777 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3778 3779 /* reg_ppcnt_a_mac_control_frames_received 3780 * Access: RO 3781 */ 3782 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 3783 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 3784 3785 /* reg_ppcnt_a_unsupported_opcodes_received 3786 * Access: RO 3787 */ 3788 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 3789 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 3790 3791 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 3792 * Access: RO 3793 */ 3794 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 3795 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 3796 3797 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 3798 * Access: RO 3799 */ 3800 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 3801 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 3802 3803 /* Ethernet RFC 2819 Counter Group */ 3804 3805 /* reg_ppcnt_ether_stats_pkts64octets 3806 * Access: RO 3807 */ 3808 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 3809 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3810 3811 /* reg_ppcnt_ether_stats_pkts65to127octets 3812 * Access: RO 3813 */ 3814 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 3815 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3816 3817 /* reg_ppcnt_ether_stats_pkts128to255octets 3818 * Access: RO 3819 */ 3820 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 3821 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3822 3823 /* reg_ppcnt_ether_stats_pkts256to511octets 3824 * Access: RO 3825 */ 3826 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 3827 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3828 3829 /* reg_ppcnt_ether_stats_pkts512to1023octets 3830 * Access: RO 3831 */ 3832 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 3833 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 3834 3835 /* reg_ppcnt_ether_stats_pkts1024to1518octets 3836 * Access: RO 3837 */ 3838 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 3839 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 3840 3841 /* reg_ppcnt_ether_stats_pkts1519to2047octets 3842 * Access: RO 3843 */ 3844 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 3845 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 3846 3847 /* reg_ppcnt_ether_stats_pkts2048to4095octets 3848 * Access: RO 3849 */ 3850 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 3851 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 3852 3853 /* reg_ppcnt_ether_stats_pkts4096to8191octets 3854 * Access: RO 3855 */ 3856 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 3857 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 3858 3859 /* reg_ppcnt_ether_stats_pkts8192to10239octets 3860 * Access: RO 3861 */ 3862 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 3863 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 3864 3865 /* Ethernet Extended Counter Group Counters */ 3866 3867 /* reg_ppcnt_ecn_marked 3868 * Access: RO 3869 */ 3870 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 3871 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3872 3873 /* Ethernet Per Priority Group Counters */ 3874 3875 /* reg_ppcnt_rx_octets 3876 * Access: RO 3877 */ 3878 MLXSW_ITEM64(reg, ppcnt, rx_octets, 3879 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3880 3881 /* reg_ppcnt_rx_frames 3882 * Access: RO 3883 */ 3884 MLXSW_ITEM64(reg, ppcnt, rx_frames, 3885 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3886 3887 /* reg_ppcnt_tx_octets 3888 * Access: RO 3889 */ 3890 MLXSW_ITEM64(reg, ppcnt, tx_octets, 3891 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3892 3893 /* reg_ppcnt_tx_frames 3894 * Access: RO 3895 */ 3896 MLXSW_ITEM64(reg, ppcnt, tx_frames, 3897 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3898 3899 /* reg_ppcnt_rx_pause 3900 * Access: RO 3901 */ 3902 MLXSW_ITEM64(reg, ppcnt, rx_pause, 3903 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3904 3905 /* reg_ppcnt_rx_pause_duration 3906 * Access: RO 3907 */ 3908 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 3909 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3910 3911 /* reg_ppcnt_tx_pause 3912 * Access: RO 3913 */ 3914 MLXSW_ITEM64(reg, ppcnt, tx_pause, 3915 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3916 3917 /* reg_ppcnt_tx_pause_duration 3918 * Access: RO 3919 */ 3920 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 3921 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3922 3923 /* reg_ppcnt_rx_pause_transition 3924 * Access: RO 3925 */ 3926 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 3927 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3928 3929 /* Ethernet Per Traffic Group Counters */ 3930 3931 /* reg_ppcnt_tc_transmit_queue 3932 * Contains the transmit queue depth in cells of traffic class 3933 * selected by prio_tc and the port selected by local_port. 3934 * The field cannot be cleared. 3935 * Access: RO 3936 */ 3937 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 3938 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3939 3940 /* reg_ppcnt_tc_no_buffer_discard_uc 3941 * The number of unicast packets dropped due to lack of shared 3942 * buffer resources. 3943 * Access: RO 3944 */ 3945 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 3946 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3947 3948 /* Ethernet Per Traffic Class Congestion Group Counters */ 3949 3950 /* reg_ppcnt_wred_discard 3951 * Access: RO 3952 */ 3953 MLXSW_ITEM64(reg, ppcnt, wred_discard, 3954 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3955 3956 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 3957 enum mlxsw_reg_ppcnt_grp grp, 3958 u8 prio_tc) 3959 { 3960 MLXSW_REG_ZERO(ppcnt, payload); 3961 mlxsw_reg_ppcnt_swid_set(payload, 0); 3962 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 3963 mlxsw_reg_ppcnt_pnat_set(payload, 0); 3964 mlxsw_reg_ppcnt_grp_set(payload, grp); 3965 mlxsw_reg_ppcnt_clr_set(payload, 0); 3966 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 3967 } 3968 3969 /* PLIB - Port Local to InfiniBand Port 3970 * ------------------------------------ 3971 * The PLIB register performs mapping from Local Port into InfiniBand Port. 3972 */ 3973 #define MLXSW_REG_PLIB_ID 0x500A 3974 #define MLXSW_REG_PLIB_LEN 0x10 3975 3976 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 3977 3978 /* reg_plib_local_port 3979 * Local port number. 3980 * Access: Index 3981 */ 3982 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 3983 3984 /* reg_plib_ib_port 3985 * InfiniBand port remapping for local_port. 3986 * Access: RW 3987 */ 3988 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 3989 3990 /* PPTB - Port Prio To Buffer Register 3991 * ----------------------------------- 3992 * Configures the switch priority to buffer table. 3993 */ 3994 #define MLXSW_REG_PPTB_ID 0x500B 3995 #define MLXSW_REG_PPTB_LEN 0x10 3996 3997 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 3998 3999 enum { 4000 MLXSW_REG_PPTB_MM_UM, 4001 MLXSW_REG_PPTB_MM_UNICAST, 4002 MLXSW_REG_PPTB_MM_MULTICAST, 4003 }; 4004 4005 /* reg_pptb_mm 4006 * Mapping mode. 4007 * 0 - Map both unicast and multicast packets to the same buffer. 4008 * 1 - Map only unicast packets. 4009 * 2 - Map only multicast packets. 4010 * Access: Index 4011 * 4012 * Note: SwitchX-2 only supports the first option. 4013 */ 4014 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4015 4016 /* reg_pptb_local_port 4017 * Local port number. 4018 * Access: Index 4019 */ 4020 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 4021 4022 /* reg_pptb_um 4023 * Enables the update of the untagged_buf field. 4024 * Access: RW 4025 */ 4026 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 4027 4028 /* reg_pptb_pm 4029 * Enables the update of the prio_to_buff field. 4030 * Bit <i> is a flag for updating the mapping for switch priority <i>. 4031 * Access: RW 4032 */ 4033 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 4034 4035 /* reg_pptb_prio_to_buff 4036 * Mapping of switch priority <i> to one of the allocated receive port 4037 * buffers. 4038 * Access: RW 4039 */ 4040 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 4041 4042 /* reg_pptb_pm_msb 4043 * Enables the update of the prio_to_buff field. 4044 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 4045 * Access: RW 4046 */ 4047 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 4048 4049 /* reg_pptb_untagged_buff 4050 * Mapping of untagged frames to one of the allocated receive port buffers. 4051 * Access: RW 4052 * 4053 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 4054 * Spectrum, as it maps untagged packets based on the default switch priority. 4055 */ 4056 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 4057 4058 /* reg_pptb_prio_to_buff_msb 4059 * Mapping of switch priority <i+8> to one of the allocated receive port 4060 * buffers. 4061 * Access: RW 4062 */ 4063 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 4064 4065 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 4066 4067 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 4068 { 4069 MLXSW_REG_ZERO(pptb, payload); 4070 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 4071 mlxsw_reg_pptb_local_port_set(payload, local_port); 4072 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4073 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4074 } 4075 4076 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 4077 u8 buff) 4078 { 4079 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 4080 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 4081 } 4082 4083 /* PBMC - Port Buffer Management Control Register 4084 * ---------------------------------------------- 4085 * The PBMC register configures and retrieves the port packet buffer 4086 * allocation for different Prios, and the Pause threshold management. 4087 */ 4088 #define MLXSW_REG_PBMC_ID 0x500C 4089 #define MLXSW_REG_PBMC_LEN 0x6C 4090 4091 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 4092 4093 /* reg_pbmc_local_port 4094 * Local port number. 4095 * Access: Index 4096 */ 4097 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 4098 4099 /* reg_pbmc_xoff_timer_value 4100 * When device generates a pause frame, it uses this value as the pause 4101 * timer (time for the peer port to pause in quota-512 bit time). 4102 * Access: RW 4103 */ 4104 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 4105 4106 /* reg_pbmc_xoff_refresh 4107 * The time before a new pause frame should be sent to refresh the pause RW 4108 * state. Using the same units as xoff_timer_value above (in quota-512 bit 4109 * time). 4110 * Access: RW 4111 */ 4112 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 4113 4114 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 4115 4116 /* reg_pbmc_buf_lossy 4117 * The field indicates if the buffer is lossy. 4118 * 0 - Lossless 4119 * 1 - Lossy 4120 * Access: RW 4121 */ 4122 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 4123 4124 /* reg_pbmc_buf_epsb 4125 * Eligible for Port Shared buffer. 4126 * If epsb is set, packets assigned to buffer are allowed to insert the port 4127 * shared buffer. 4128 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 4129 * Access: RW 4130 */ 4131 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 4132 4133 /* reg_pbmc_buf_size 4134 * The part of the packet buffer array is allocated for the specific buffer. 4135 * Units are represented in cells. 4136 * Access: RW 4137 */ 4138 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 4139 4140 /* reg_pbmc_buf_xoff_threshold 4141 * Once the amount of data in the buffer goes above this value, device 4142 * starts sending PFC frames for all priorities associated with the 4143 * buffer. Units are represented in cells. Reserved in case of lossy 4144 * buffer. 4145 * Access: RW 4146 * 4147 * Note: In Spectrum, reserved for buffer[9]. 4148 */ 4149 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 4150 0x08, 0x04, false); 4151 4152 /* reg_pbmc_buf_xon_threshold 4153 * When the amount of data in the buffer goes below this value, device 4154 * stops sending PFC frames for the priorities associated with the 4155 * buffer. Units are represented in cells. Reserved in case of lossy 4156 * buffer. 4157 * Access: RW 4158 * 4159 * Note: In Spectrum, reserved for buffer[9]. 4160 */ 4161 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 4162 0x08, 0x04, false); 4163 4164 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 4165 u16 xoff_timer_value, u16 xoff_refresh) 4166 { 4167 MLXSW_REG_ZERO(pbmc, payload); 4168 mlxsw_reg_pbmc_local_port_set(payload, local_port); 4169 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 4170 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 4171 } 4172 4173 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 4174 int buf_index, 4175 u16 size) 4176 { 4177 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 4178 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4179 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4180 } 4181 4182 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 4183 int buf_index, u16 size, 4184 u16 threshold) 4185 { 4186 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 4187 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4188 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4189 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 4190 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 4191 } 4192 4193 /* PSPA - Port Switch Partition Allocation 4194 * --------------------------------------- 4195 * Controls the association of a port with a switch partition and enables 4196 * configuring ports as stacking ports. 4197 */ 4198 #define MLXSW_REG_PSPA_ID 0x500D 4199 #define MLXSW_REG_PSPA_LEN 0x8 4200 4201 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 4202 4203 /* reg_pspa_swid 4204 * Switch partition ID. 4205 * Access: RW 4206 */ 4207 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 4208 4209 /* reg_pspa_local_port 4210 * Local port number. 4211 * Access: Index 4212 */ 4213 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 4214 4215 /* reg_pspa_sub_port 4216 * Virtual port within the local port. Set to 0 when virtual ports are 4217 * disabled on the local port. 4218 * Access: Index 4219 */ 4220 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 4221 4222 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 4223 { 4224 MLXSW_REG_ZERO(pspa, payload); 4225 mlxsw_reg_pspa_swid_set(payload, swid); 4226 mlxsw_reg_pspa_local_port_set(payload, local_port); 4227 mlxsw_reg_pspa_sub_port_set(payload, 0); 4228 } 4229 4230 /* HTGT - Host Trap Group Table 4231 * ---------------------------- 4232 * Configures the properties for forwarding to CPU. 4233 */ 4234 #define MLXSW_REG_HTGT_ID 0x7002 4235 #define MLXSW_REG_HTGT_LEN 0x20 4236 4237 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 4238 4239 /* reg_htgt_swid 4240 * Switch partition ID. 4241 * Access: Index 4242 */ 4243 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 4244 4245 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 4246 4247 /* reg_htgt_type 4248 * CPU path type. 4249 * Access: RW 4250 */ 4251 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 4252 4253 enum mlxsw_reg_htgt_trap_group { 4254 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 4255 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 4256 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 4257 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 4258 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 4259 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 4260 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 4261 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 4262 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 4263 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 4264 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 4265 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 4266 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 4267 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 4268 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 4269 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 4270 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 4271 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 4272 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 4273 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 4274 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 4275 }; 4276 4277 /* reg_htgt_trap_group 4278 * Trap group number. User defined number specifying which trap groups 4279 * should be forwarded to the CPU. The mapping between trap IDs and trap 4280 * groups is configured using HPKT register. 4281 * Access: Index 4282 */ 4283 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 4284 4285 enum { 4286 MLXSW_REG_HTGT_POLICER_DISABLE, 4287 MLXSW_REG_HTGT_POLICER_ENABLE, 4288 }; 4289 4290 /* reg_htgt_pide 4291 * Enable policer ID specified using 'pid' field. 4292 * Access: RW 4293 */ 4294 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 4295 4296 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 4297 4298 /* reg_htgt_pid 4299 * Policer ID for the trap group. 4300 * Access: RW 4301 */ 4302 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 4303 4304 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 4305 4306 /* reg_htgt_mirror_action 4307 * Mirror action to use. 4308 * 0 - Trap to CPU. 4309 * 1 - Trap to CPU and mirror to a mirroring agent. 4310 * 2 - Mirror to a mirroring agent and do not trap to CPU. 4311 * Access: RW 4312 * 4313 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 4314 */ 4315 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 4316 4317 /* reg_htgt_mirroring_agent 4318 * Mirroring agent. 4319 * Access: RW 4320 */ 4321 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 4322 4323 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 4324 4325 /* reg_htgt_priority 4326 * Trap group priority. 4327 * In case a packet matches multiple classification rules, the packet will 4328 * only be trapped once, based on the trap ID associated with the group (via 4329 * register HPKT) with the highest priority. 4330 * Supported values are 0-7, with 7 represnting the highest priority. 4331 * Access: RW 4332 * 4333 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 4334 * by the 'trap_group' field. 4335 */ 4336 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 4337 4338 #define MLXSW_REG_HTGT_DEFAULT_TC 7 4339 4340 /* reg_htgt_local_path_cpu_tclass 4341 * CPU ingress traffic class for the trap group. 4342 * Access: RW 4343 */ 4344 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 4345 4346 enum mlxsw_reg_htgt_local_path_rdq { 4347 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 4348 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 4349 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 4350 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 4351 }; 4352 /* reg_htgt_local_path_rdq 4353 * Receive descriptor queue (RDQ) to use for the trap group. 4354 * Access: RW 4355 */ 4356 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 4357 4358 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 4359 u8 priority, u8 tc) 4360 { 4361 MLXSW_REG_ZERO(htgt, payload); 4362 4363 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 4364 mlxsw_reg_htgt_pide_set(payload, 4365 MLXSW_REG_HTGT_POLICER_DISABLE); 4366 } else { 4367 mlxsw_reg_htgt_pide_set(payload, 4368 MLXSW_REG_HTGT_POLICER_ENABLE); 4369 mlxsw_reg_htgt_pid_set(payload, policer_id); 4370 } 4371 4372 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 4373 mlxsw_reg_htgt_trap_group_set(payload, group); 4374 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 4375 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 4376 mlxsw_reg_htgt_priority_set(payload, priority); 4377 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 4378 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 4379 } 4380 4381 /* HPKT - Host Packet Trap 4382 * ----------------------- 4383 * Configures trap IDs inside trap groups. 4384 */ 4385 #define MLXSW_REG_HPKT_ID 0x7003 4386 #define MLXSW_REG_HPKT_LEN 0x10 4387 4388 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 4389 4390 enum { 4391 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 4392 MLXSW_REG_HPKT_ACK_REQUIRED, 4393 }; 4394 4395 /* reg_hpkt_ack 4396 * Require acknowledgements from the host for events. 4397 * If set, then the device will wait for the event it sent to be acknowledged 4398 * by the host. This option is only relevant for event trap IDs. 4399 * Access: RW 4400 * 4401 * Note: Currently not supported by firmware. 4402 */ 4403 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 4404 4405 enum mlxsw_reg_hpkt_action { 4406 MLXSW_REG_HPKT_ACTION_FORWARD, 4407 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 4408 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 4409 MLXSW_REG_HPKT_ACTION_DISCARD, 4410 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 4411 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 4412 }; 4413 4414 /* reg_hpkt_action 4415 * Action to perform on packet when trapped. 4416 * 0 - No action. Forward to CPU based on switching rules. 4417 * 1 - Trap to CPU (CPU receives sole copy). 4418 * 2 - Mirror to CPU (CPU receives a replica of the packet). 4419 * 3 - Discard. 4420 * 4 - Soft discard (allow other traps to act on the packet). 4421 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 4422 * Access: RW 4423 * 4424 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 4425 * addressed to the CPU. 4426 */ 4427 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 4428 4429 /* reg_hpkt_trap_group 4430 * Trap group to associate the trap with. 4431 * Access: RW 4432 */ 4433 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 4434 4435 /* reg_hpkt_trap_id 4436 * Trap ID. 4437 * Access: Index 4438 * 4439 * Note: A trap ID can only be associated with a single trap group. The device 4440 * will associate the trap ID with the last trap group configured. 4441 */ 4442 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 4443 4444 enum { 4445 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 4446 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 4447 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 4448 }; 4449 4450 /* reg_hpkt_ctrl 4451 * Configure dedicated buffer resources for control packets. 4452 * Ignored by SwitchX-2. 4453 * 0 - Keep factory defaults. 4454 * 1 - Do not use control buffer for this trap ID. 4455 * 2 - Use control buffer for this trap ID. 4456 * Access: RW 4457 */ 4458 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 4459 4460 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 4461 enum mlxsw_reg_htgt_trap_group trap_group, 4462 bool is_ctrl) 4463 { 4464 MLXSW_REG_ZERO(hpkt, payload); 4465 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 4466 mlxsw_reg_hpkt_action_set(payload, action); 4467 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 4468 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 4469 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 4470 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 4471 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 4472 } 4473 4474 /* RGCR - Router General Configuration Register 4475 * -------------------------------------------- 4476 * The register is used for setting up the router configuration. 4477 */ 4478 #define MLXSW_REG_RGCR_ID 0x8001 4479 #define MLXSW_REG_RGCR_LEN 0x28 4480 4481 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 4482 4483 /* reg_rgcr_ipv4_en 4484 * IPv4 router enable. 4485 * Access: RW 4486 */ 4487 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 4488 4489 /* reg_rgcr_ipv6_en 4490 * IPv6 router enable. 4491 * Access: RW 4492 */ 4493 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 4494 4495 /* reg_rgcr_max_router_interfaces 4496 * Defines the maximum number of active router interfaces for all virtual 4497 * routers. 4498 * Access: RW 4499 */ 4500 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 4501 4502 /* reg_rgcr_usp 4503 * Update switch priority and packet color. 4504 * 0 - Preserve the value of Switch Priority and packet color. 4505 * 1 - Recalculate the value of Switch Priority and packet color. 4506 * Access: RW 4507 * 4508 * Note: Not supported by SwitchX and SwitchX-2. 4509 */ 4510 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 4511 4512 /* reg_rgcr_pcp_rw 4513 * Indicates how to handle the pcp_rewrite_en value: 4514 * 0 - Preserve the value of pcp_rewrite_en. 4515 * 2 - Disable PCP rewrite. 4516 * 3 - Enable PCP rewrite. 4517 * Access: RW 4518 * 4519 * Note: Not supported by SwitchX and SwitchX-2. 4520 */ 4521 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 4522 4523 /* reg_rgcr_activity_dis 4524 * Activity disable: 4525 * 0 - Activity will be set when an entry is hit (default). 4526 * 1 - Activity will not be set when an entry is hit. 4527 * 4528 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 4529 * (RALUE). 4530 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 4531 * Entry (RAUHT). 4532 * Bits 2:7 are reserved. 4533 * Access: RW 4534 * 4535 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 4536 */ 4537 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 4538 4539 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 4540 bool ipv6_en) 4541 { 4542 MLXSW_REG_ZERO(rgcr, payload); 4543 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 4544 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 4545 } 4546 4547 /* RITR - Router Interface Table Register 4548 * -------------------------------------- 4549 * The register is used to configure the router interface table. 4550 */ 4551 #define MLXSW_REG_RITR_ID 0x8002 4552 #define MLXSW_REG_RITR_LEN 0x40 4553 4554 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 4555 4556 /* reg_ritr_enable 4557 * Enables routing on the router interface. 4558 * Access: RW 4559 */ 4560 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 4561 4562 /* reg_ritr_ipv4 4563 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 4564 * interface. 4565 * Access: RW 4566 */ 4567 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 4568 4569 /* reg_ritr_ipv6 4570 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 4571 * interface. 4572 * Access: RW 4573 */ 4574 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 4575 4576 /* reg_ritr_ipv4_mc 4577 * IPv4 multicast routing enable. 4578 * Access: RW 4579 */ 4580 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 4581 4582 /* reg_ritr_ipv6_mc 4583 * IPv6 multicast routing enable. 4584 * Access: RW 4585 */ 4586 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 4587 4588 enum mlxsw_reg_ritr_if_type { 4589 /* VLAN interface. */ 4590 MLXSW_REG_RITR_VLAN_IF, 4591 /* FID interface. */ 4592 MLXSW_REG_RITR_FID_IF, 4593 /* Sub-port interface. */ 4594 MLXSW_REG_RITR_SP_IF, 4595 /* Loopback Interface. */ 4596 MLXSW_REG_RITR_LOOPBACK_IF, 4597 }; 4598 4599 /* reg_ritr_type 4600 * Router interface type as per enum mlxsw_reg_ritr_if_type. 4601 * Access: RW 4602 */ 4603 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 4604 4605 enum { 4606 MLXSW_REG_RITR_RIF_CREATE, 4607 MLXSW_REG_RITR_RIF_DEL, 4608 }; 4609 4610 /* reg_ritr_op 4611 * Opcode: 4612 * 0 - Create or edit RIF. 4613 * 1 - Delete RIF. 4614 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 4615 * is not supported. An interface must be deleted and re-created in order 4616 * to update properties. 4617 * Access: WO 4618 */ 4619 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 4620 4621 /* reg_ritr_rif 4622 * Router interface index. A pointer to the Router Interface Table. 4623 * Access: Index 4624 */ 4625 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 4626 4627 /* reg_ritr_ipv4_fe 4628 * IPv4 Forwarding Enable. 4629 * Enables routing of IPv4 traffic on the router interface. When disabled, 4630 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4631 * Not supported in SwitchX-2. 4632 * Access: RW 4633 */ 4634 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 4635 4636 /* reg_ritr_ipv6_fe 4637 * IPv6 Forwarding Enable. 4638 * Enables routing of IPv6 traffic on the router interface. When disabled, 4639 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4640 * Not supported in SwitchX-2. 4641 * Access: RW 4642 */ 4643 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 4644 4645 /* reg_ritr_ipv4_mc_fe 4646 * IPv4 Multicast Forwarding Enable. 4647 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4648 * will be enabled. 4649 * Access: RW 4650 */ 4651 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 4652 4653 /* reg_ritr_ipv6_mc_fe 4654 * IPv6 Multicast Forwarding Enable. 4655 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4656 * will be enabled. 4657 * Access: RW 4658 */ 4659 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 4660 4661 /* reg_ritr_lb_en 4662 * Loop-back filter enable for unicast packets. 4663 * If the flag is set then loop-back filter for unicast packets is 4664 * implemented on the RIF. Multicast packets are always subject to 4665 * loop-back filtering. 4666 * Access: RW 4667 */ 4668 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 4669 4670 /* reg_ritr_virtual_router 4671 * Virtual router ID associated with the router interface. 4672 * Access: RW 4673 */ 4674 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 4675 4676 /* reg_ritr_mtu 4677 * Router interface MTU. 4678 * Access: RW 4679 */ 4680 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 4681 4682 /* reg_ritr_if_swid 4683 * Switch partition ID. 4684 * Access: RW 4685 */ 4686 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 4687 4688 /* reg_ritr_if_mac 4689 * Router interface MAC address. 4690 * In Spectrum, all MAC addresses must have the same 38 MSBits. 4691 * Access: RW 4692 */ 4693 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 4694 4695 /* reg_ritr_if_vrrp_id_ipv6 4696 * VRRP ID for IPv6 4697 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 4698 * Access: RW 4699 */ 4700 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 4701 4702 /* reg_ritr_if_vrrp_id_ipv4 4703 * VRRP ID for IPv4 4704 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 4705 * Access: RW 4706 */ 4707 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 4708 4709 /* VLAN Interface */ 4710 4711 /* reg_ritr_vlan_if_vid 4712 * VLAN ID. 4713 * Access: RW 4714 */ 4715 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 4716 4717 /* FID Interface */ 4718 4719 /* reg_ritr_fid_if_fid 4720 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 4721 * the vFID range are supported. 4722 * Access: RW 4723 */ 4724 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 4725 4726 static inline void mlxsw_reg_ritr_fid_set(char *payload, 4727 enum mlxsw_reg_ritr_if_type rif_type, 4728 u16 fid) 4729 { 4730 if (rif_type == MLXSW_REG_RITR_FID_IF) 4731 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 4732 else 4733 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 4734 } 4735 4736 /* Sub-port Interface */ 4737 4738 /* reg_ritr_sp_if_lag 4739 * LAG indication. When this bit is set the system_port field holds the 4740 * LAG identifier. 4741 * Access: RW 4742 */ 4743 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 4744 4745 /* reg_ritr_sp_system_port 4746 * Port unique indentifier. When lag bit is set, this field holds the 4747 * lag_id in bits 0:9. 4748 * Access: RW 4749 */ 4750 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 4751 4752 /* reg_ritr_sp_if_vid 4753 * VLAN ID. 4754 * Access: RW 4755 */ 4756 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 4757 4758 /* Loopback Interface */ 4759 4760 enum mlxsw_reg_ritr_loopback_protocol { 4761 /* IPinIP IPv4 underlay Unicast */ 4762 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 4763 /* IPinIP IPv6 underlay Unicast */ 4764 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 4765 }; 4766 4767 /* reg_ritr_loopback_protocol 4768 * Access: RW 4769 */ 4770 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 4771 4772 enum mlxsw_reg_ritr_loopback_ipip_type { 4773 /* Tunnel is IPinIP. */ 4774 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 4775 /* Tunnel is GRE, no key. */ 4776 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 4777 /* Tunnel is GRE, with a key. */ 4778 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 4779 }; 4780 4781 /* reg_ritr_loopback_ipip_type 4782 * Encapsulation type. 4783 * Access: RW 4784 */ 4785 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 4786 4787 enum mlxsw_reg_ritr_loopback_ipip_options { 4788 /* The key is defined by gre_key. */ 4789 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 4790 }; 4791 4792 /* reg_ritr_loopback_ipip_options 4793 * Access: RW 4794 */ 4795 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 4796 4797 /* reg_ritr_loopback_ipip_uvr 4798 * Underlay Virtual Router ID. 4799 * Range is 0..cap_max_virtual_routers-1. 4800 * Reserved for Spectrum-2. 4801 * Access: RW 4802 */ 4803 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 4804 4805 /* reg_ritr_loopback_ipip_usip* 4806 * Encapsulation Underlay source IP. 4807 * Access: RW 4808 */ 4809 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 4810 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 4811 4812 /* reg_ritr_loopback_ipip_gre_key 4813 * GRE Key. 4814 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 4815 * Access: RW 4816 */ 4817 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 4818 4819 /* Shared between ingress/egress */ 4820 enum mlxsw_reg_ritr_counter_set_type { 4821 /* No Count. */ 4822 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 4823 /* Basic. Used for router interfaces, counting the following: 4824 * - Error and Discard counters. 4825 * - Unicast, Multicast and Broadcast counters. Sharing the 4826 * same set of counters for the different type of traffic 4827 * (IPv4, IPv6 and mpls). 4828 */ 4829 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 4830 }; 4831 4832 /* reg_ritr_ingress_counter_index 4833 * Counter Index for flow counter. 4834 * Access: RW 4835 */ 4836 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 4837 4838 /* reg_ritr_ingress_counter_set_type 4839 * Igress Counter Set Type for router interface counter. 4840 * Access: RW 4841 */ 4842 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 4843 4844 /* reg_ritr_egress_counter_index 4845 * Counter Index for flow counter. 4846 * Access: RW 4847 */ 4848 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 4849 4850 /* reg_ritr_egress_counter_set_type 4851 * Egress Counter Set Type for router interface counter. 4852 * Access: RW 4853 */ 4854 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 4855 4856 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 4857 bool enable, bool egress) 4858 { 4859 enum mlxsw_reg_ritr_counter_set_type set_type; 4860 4861 if (enable) 4862 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 4863 else 4864 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 4865 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 4866 4867 if (egress) 4868 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 4869 else 4870 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 4871 } 4872 4873 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 4874 { 4875 MLXSW_REG_ZERO(ritr, payload); 4876 mlxsw_reg_ritr_rif_set(payload, rif); 4877 } 4878 4879 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 4880 u16 system_port, u16 vid) 4881 { 4882 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 4883 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 4884 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 4885 } 4886 4887 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 4888 enum mlxsw_reg_ritr_if_type type, 4889 u16 rif, u16 vr_id, u16 mtu) 4890 { 4891 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 4892 4893 MLXSW_REG_ZERO(ritr, payload); 4894 mlxsw_reg_ritr_enable_set(payload, enable); 4895 mlxsw_reg_ritr_ipv4_set(payload, 1); 4896 mlxsw_reg_ritr_ipv6_set(payload, 1); 4897 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 4898 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 4899 mlxsw_reg_ritr_type_set(payload, type); 4900 mlxsw_reg_ritr_op_set(payload, op); 4901 mlxsw_reg_ritr_rif_set(payload, rif); 4902 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 4903 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 4904 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 4905 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 4906 mlxsw_reg_ritr_lb_en_set(payload, 1); 4907 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 4908 mlxsw_reg_ritr_mtu_set(payload, mtu); 4909 } 4910 4911 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 4912 { 4913 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 4914 } 4915 4916 static inline void 4917 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 4918 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4919 enum mlxsw_reg_ritr_loopback_ipip_options options, 4920 u16 uvr_id, u32 gre_key) 4921 { 4922 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 4923 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 4924 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 4925 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 4926 } 4927 4928 static inline void 4929 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 4930 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4931 enum mlxsw_reg_ritr_loopback_ipip_options options, 4932 u16 uvr_id, u32 usip, u32 gre_key) 4933 { 4934 mlxsw_reg_ritr_loopback_protocol_set(payload, 4935 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 4936 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 4937 uvr_id, gre_key); 4938 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 4939 } 4940 4941 /* RTAR - Router TCAM Allocation Register 4942 * -------------------------------------- 4943 * This register is used for allocation of regions in the TCAM table. 4944 */ 4945 #define MLXSW_REG_RTAR_ID 0x8004 4946 #define MLXSW_REG_RTAR_LEN 0x20 4947 4948 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 4949 4950 enum mlxsw_reg_rtar_op { 4951 MLXSW_REG_RTAR_OP_ALLOCATE, 4952 MLXSW_REG_RTAR_OP_RESIZE, 4953 MLXSW_REG_RTAR_OP_DEALLOCATE, 4954 }; 4955 4956 /* reg_rtar_op 4957 * Access: WO 4958 */ 4959 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 4960 4961 enum mlxsw_reg_rtar_key_type { 4962 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 4963 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 4964 }; 4965 4966 /* reg_rtar_key_type 4967 * TCAM key type for the region. 4968 * Access: WO 4969 */ 4970 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 4971 4972 /* reg_rtar_region_size 4973 * TCAM region size. When allocating/resizing this is the requested 4974 * size, the response is the actual size. 4975 * Note: Actual size may be larger than requested. 4976 * Reserved for op = Deallocate 4977 * Access: WO 4978 */ 4979 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 4980 4981 static inline void mlxsw_reg_rtar_pack(char *payload, 4982 enum mlxsw_reg_rtar_op op, 4983 enum mlxsw_reg_rtar_key_type key_type, 4984 u16 region_size) 4985 { 4986 MLXSW_REG_ZERO(rtar, payload); 4987 mlxsw_reg_rtar_op_set(payload, op); 4988 mlxsw_reg_rtar_key_type_set(payload, key_type); 4989 mlxsw_reg_rtar_region_size_set(payload, region_size); 4990 } 4991 4992 /* RATR - Router Adjacency Table Register 4993 * -------------------------------------- 4994 * The RATR register is used to configure the Router Adjacency (next-hop) 4995 * Table. 4996 */ 4997 #define MLXSW_REG_RATR_ID 0x8008 4998 #define MLXSW_REG_RATR_LEN 0x2C 4999 5000 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5001 5002 enum mlxsw_reg_ratr_op { 5003 /* Read */ 5004 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5005 /* Read and clear activity */ 5006 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 5007 /* Write Adjacency entry */ 5008 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 5009 /* Write Adjacency entry only if the activity is cleared. 5010 * The write may not succeed if the activity is set. There is not 5011 * direct feedback if the write has succeeded or not, however 5012 * the get will reveal the actual entry (SW can compare the get 5013 * response to the set command). 5014 */ 5015 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 5016 }; 5017 5018 /* reg_ratr_op 5019 * Note that Write operation may also be used for updating 5020 * counter_set_type and counter_index. In this case all other 5021 * fields must not be updated. 5022 * Access: OP 5023 */ 5024 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 5025 5026 /* reg_ratr_v 5027 * Valid bit. Indicates if the adjacency entry is valid. 5028 * Note: the device may need some time before reusing an invalidated 5029 * entry. During this time the entry can not be reused. It is 5030 * recommended to use another entry before reusing an invalidated 5031 * entry (e.g. software can put it at the end of the list for 5032 * reusing). Trying to access an invalidated entry not yet cleared 5033 * by the device results with failure indicating "Try Again" status. 5034 * When valid is '0' then egress_router_interface,trap_action, 5035 * adjacency_parameters and counters are reserved 5036 * Access: RW 5037 */ 5038 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 5039 5040 /* reg_ratr_a 5041 * Activity. Set for new entries. Set if a packet lookup has hit on 5042 * the specific entry. To clear the a bit, use "clear activity". 5043 * Access: RO 5044 */ 5045 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 5046 5047 enum mlxsw_reg_ratr_type { 5048 /* Ethernet */ 5049 MLXSW_REG_RATR_TYPE_ETHERNET, 5050 /* IPoIB Unicast without GRH. 5051 * Reserved for Spectrum. 5052 */ 5053 MLXSW_REG_RATR_TYPE_IPOIB_UC, 5054 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 5055 * adjacency). 5056 * Reserved for Spectrum. 5057 */ 5058 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 5059 /* IPoIB Multicast. 5060 * Reserved for Spectrum. 5061 */ 5062 MLXSW_REG_RATR_TYPE_IPOIB_MC, 5063 /* MPLS. 5064 * Reserved for SwitchX/-2. 5065 */ 5066 MLXSW_REG_RATR_TYPE_MPLS, 5067 /* IPinIP Encap. 5068 * Reserved for SwitchX/-2. 5069 */ 5070 MLXSW_REG_RATR_TYPE_IPIP, 5071 }; 5072 5073 /* reg_ratr_type 5074 * Adjacency entry type. 5075 * Access: RW 5076 */ 5077 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 5078 5079 /* reg_ratr_adjacency_index_low 5080 * Bits 15:0 of index into the adjacency table. 5081 * For SwitchX and SwitchX-2, the adjacency table is linear and 5082 * used for adjacency entries only. 5083 * For Spectrum, the index is to the KVD linear. 5084 * Access: Index 5085 */ 5086 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 5087 5088 /* reg_ratr_egress_router_interface 5089 * Range is 0 .. cap_max_router_interfaces - 1 5090 * Access: RW 5091 */ 5092 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 5093 5094 enum mlxsw_reg_ratr_trap_action { 5095 MLXSW_REG_RATR_TRAP_ACTION_NOP, 5096 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 5097 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 5098 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 5099 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 5100 }; 5101 5102 /* reg_ratr_trap_action 5103 * see mlxsw_reg_ratr_trap_action 5104 * Access: RW 5105 */ 5106 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 5107 5108 /* reg_ratr_adjacency_index_high 5109 * Bits 23:16 of the adjacency_index. 5110 * Access: Index 5111 */ 5112 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 5113 5114 enum mlxsw_reg_ratr_trap_id { 5115 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 5116 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 5117 }; 5118 5119 /* reg_ratr_trap_id 5120 * Trap ID to be reported to CPU. 5121 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5122 * For trap_action of NOP, MIRROR and DISCARD_ERROR 5123 * Access: RW 5124 */ 5125 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 5126 5127 /* reg_ratr_eth_destination_mac 5128 * MAC address of the destination next-hop. 5129 * Access: RW 5130 */ 5131 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 5132 5133 enum mlxsw_reg_ratr_ipip_type { 5134 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 5135 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 5136 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 5137 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 5138 }; 5139 5140 /* reg_ratr_ipip_type 5141 * Underlay destination ip type. 5142 * Note: the type field must match the protocol of the router interface. 5143 * Access: RW 5144 */ 5145 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 5146 5147 /* reg_ratr_ipip_ipv4_udip 5148 * Underlay ipv4 dip. 5149 * Reserved when ipip_type is IPv6. 5150 * Access: RW 5151 */ 5152 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 5153 5154 /* reg_ratr_ipip_ipv6_ptr 5155 * Pointer to IPv6 underlay destination ip address. 5156 * For Spectrum: Pointer to KVD linear space. 5157 * Access: RW 5158 */ 5159 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 5160 5161 enum mlxsw_reg_flow_counter_set_type { 5162 /* No count */ 5163 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 5164 /* Count packets and bytes */ 5165 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 5166 /* Count only packets */ 5167 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 5168 }; 5169 5170 /* reg_ratr_counter_set_type 5171 * Counter set type for flow counters 5172 * Access: RW 5173 */ 5174 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 5175 5176 /* reg_ratr_counter_index 5177 * Counter index for flow counters 5178 * Access: RW 5179 */ 5180 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 5181 5182 static inline void 5183 mlxsw_reg_ratr_pack(char *payload, 5184 enum mlxsw_reg_ratr_op op, bool valid, 5185 enum mlxsw_reg_ratr_type type, 5186 u32 adjacency_index, u16 egress_rif) 5187 { 5188 MLXSW_REG_ZERO(ratr, payload); 5189 mlxsw_reg_ratr_op_set(payload, op); 5190 mlxsw_reg_ratr_v_set(payload, valid); 5191 mlxsw_reg_ratr_type_set(payload, type); 5192 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 5193 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 5194 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 5195 } 5196 5197 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 5198 const char *dest_mac) 5199 { 5200 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 5201 } 5202 5203 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 5204 { 5205 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 5206 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 5207 } 5208 5209 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 5210 bool counter_enable) 5211 { 5212 enum mlxsw_reg_flow_counter_set_type set_type; 5213 5214 if (counter_enable) 5215 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 5216 else 5217 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 5218 5219 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 5220 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 5221 } 5222 5223 /* RDPM - Router DSCP to Priority Mapping 5224 * -------------------------------------- 5225 * Controls the mapping from DSCP field to switch priority on routed packets 5226 */ 5227 #define MLXSW_REG_RDPM_ID 0x8009 5228 #define MLXSW_REG_RDPM_BASE_LEN 0x00 5229 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 5230 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 5231 #define MLXSW_REG_RDPM_LEN 0x40 5232 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 5233 MLXSW_REG_RDPM_LEN - \ 5234 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 5235 5236 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 5237 5238 /* reg_dscp_entry_e 5239 * Enable update of the specific entry 5240 * Access: Index 5241 */ 5242 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 5243 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 5244 5245 /* reg_dscp_entry_prio 5246 * Switch Priority 5247 * Access: RW 5248 */ 5249 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 5250 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 5251 5252 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 5253 u8 prio) 5254 { 5255 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 5256 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 5257 } 5258 5259 /* RICNT - Router Interface Counter Register 5260 * ----------------------------------------- 5261 * The RICNT register retrieves per port performance counters 5262 */ 5263 #define MLXSW_REG_RICNT_ID 0x800B 5264 #define MLXSW_REG_RICNT_LEN 0x100 5265 5266 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 5267 5268 /* reg_ricnt_counter_index 5269 * Counter index 5270 * Access: RW 5271 */ 5272 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 5273 5274 enum mlxsw_reg_ricnt_counter_set_type { 5275 /* No Count. */ 5276 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 5277 /* Basic. Used for router interfaces, counting the following: 5278 * - Error and Discard counters. 5279 * - Unicast, Multicast and Broadcast counters. Sharing the 5280 * same set of counters for the different type of traffic 5281 * (IPv4, IPv6 and mpls). 5282 */ 5283 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 5284 }; 5285 5286 /* reg_ricnt_counter_set_type 5287 * Counter Set Type for router interface counter 5288 * Access: RW 5289 */ 5290 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 5291 5292 enum mlxsw_reg_ricnt_opcode { 5293 /* Nop. Supported only for read access*/ 5294 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 5295 /* Clear. Setting the clr bit will reset the counter value for 5296 * all counters of the specified Router Interface. 5297 */ 5298 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 5299 }; 5300 5301 /* reg_ricnt_opcode 5302 * Opcode 5303 * Access: RW 5304 */ 5305 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 5306 5307 /* reg_ricnt_good_unicast_packets 5308 * good unicast packets. 5309 * Access: RW 5310 */ 5311 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 5312 5313 /* reg_ricnt_good_multicast_packets 5314 * good multicast packets. 5315 * Access: RW 5316 */ 5317 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 5318 5319 /* reg_ricnt_good_broadcast_packets 5320 * good broadcast packets 5321 * Access: RW 5322 */ 5323 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 5324 5325 /* reg_ricnt_good_unicast_bytes 5326 * A count of L3 data and padding octets not including L2 headers 5327 * for good unicast frames. 5328 * Access: RW 5329 */ 5330 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 5331 5332 /* reg_ricnt_good_multicast_bytes 5333 * A count of L3 data and padding octets not including L2 headers 5334 * for good multicast frames. 5335 * Access: RW 5336 */ 5337 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 5338 5339 /* reg_ritr_good_broadcast_bytes 5340 * A count of L3 data and padding octets not including L2 headers 5341 * for good broadcast frames. 5342 * Access: RW 5343 */ 5344 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 5345 5346 /* reg_ricnt_error_packets 5347 * A count of errored frames that do not pass the router checks. 5348 * Access: RW 5349 */ 5350 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 5351 5352 /* reg_ricnt_discrad_packets 5353 * A count of non-errored frames that do not pass the router checks. 5354 * Access: RW 5355 */ 5356 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 5357 5358 /* reg_ricnt_error_bytes 5359 * A count of L3 data and padding octets not including L2 headers 5360 * for errored frames. 5361 * Access: RW 5362 */ 5363 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 5364 5365 /* reg_ricnt_discard_bytes 5366 * A count of L3 data and padding octets not including L2 headers 5367 * for non-errored frames that do not pass the router checks. 5368 * Access: RW 5369 */ 5370 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 5371 5372 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 5373 enum mlxsw_reg_ricnt_opcode op) 5374 { 5375 MLXSW_REG_ZERO(ricnt, payload); 5376 mlxsw_reg_ricnt_op_set(payload, op); 5377 mlxsw_reg_ricnt_counter_index_set(payload, index); 5378 mlxsw_reg_ricnt_counter_set_type_set(payload, 5379 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 5380 } 5381 5382 /* RRCR - Router Rules Copy Register Layout 5383 * ---------------------------------------- 5384 * This register is used for moving and copying route entry rules. 5385 */ 5386 #define MLXSW_REG_RRCR_ID 0x800F 5387 #define MLXSW_REG_RRCR_LEN 0x24 5388 5389 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 5390 5391 enum mlxsw_reg_rrcr_op { 5392 /* Move rules */ 5393 MLXSW_REG_RRCR_OP_MOVE, 5394 /* Copy rules */ 5395 MLXSW_REG_RRCR_OP_COPY, 5396 }; 5397 5398 /* reg_rrcr_op 5399 * Access: WO 5400 */ 5401 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 5402 5403 /* reg_rrcr_offset 5404 * Offset within the region from which to copy/move. 5405 * Access: Index 5406 */ 5407 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 5408 5409 /* reg_rrcr_size 5410 * The number of rules to copy/move. 5411 * Access: WO 5412 */ 5413 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 5414 5415 /* reg_rrcr_table_id 5416 * Identifier of the table on which to perform the operation. Encoding is the 5417 * same as in RTAR.key_type 5418 * Access: Index 5419 */ 5420 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 5421 5422 /* reg_rrcr_dest_offset 5423 * Offset within the region to which to copy/move 5424 * Access: Index 5425 */ 5426 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 5427 5428 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 5429 u16 offset, u16 size, 5430 enum mlxsw_reg_rtar_key_type table_id, 5431 u16 dest_offset) 5432 { 5433 MLXSW_REG_ZERO(rrcr, payload); 5434 mlxsw_reg_rrcr_op_set(payload, op); 5435 mlxsw_reg_rrcr_offset_set(payload, offset); 5436 mlxsw_reg_rrcr_size_set(payload, size); 5437 mlxsw_reg_rrcr_table_id_set(payload, table_id); 5438 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 5439 } 5440 5441 /* RALTA - Router Algorithmic LPM Tree Allocation Register 5442 * ------------------------------------------------------- 5443 * RALTA is used to allocate the LPM trees of the SHSPM method. 5444 */ 5445 #define MLXSW_REG_RALTA_ID 0x8010 5446 #define MLXSW_REG_RALTA_LEN 0x04 5447 5448 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 5449 5450 /* reg_ralta_op 5451 * opcode (valid for Write, must be 0 on Read) 5452 * 0 - allocate a tree 5453 * 1 - deallocate a tree 5454 * Access: OP 5455 */ 5456 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 5457 5458 enum mlxsw_reg_ralxx_protocol { 5459 MLXSW_REG_RALXX_PROTOCOL_IPV4, 5460 MLXSW_REG_RALXX_PROTOCOL_IPV6, 5461 }; 5462 5463 /* reg_ralta_protocol 5464 * Protocol. 5465 * Deallocation opcode: Reserved. 5466 * Access: RW 5467 */ 5468 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 5469 5470 /* reg_ralta_tree_id 5471 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 5472 * the tree identifier (managed by software). 5473 * Note that tree_id 0 is allocated for a default-route tree. 5474 * Access: Index 5475 */ 5476 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 5477 5478 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 5479 enum mlxsw_reg_ralxx_protocol protocol, 5480 u8 tree_id) 5481 { 5482 MLXSW_REG_ZERO(ralta, payload); 5483 mlxsw_reg_ralta_op_set(payload, !alloc); 5484 mlxsw_reg_ralta_protocol_set(payload, protocol); 5485 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 5486 } 5487 5488 /* RALST - Router Algorithmic LPM Structure Tree Register 5489 * ------------------------------------------------------ 5490 * RALST is used to set and query the structure of an LPM tree. 5491 * The structure of the tree must be sorted as a sorted binary tree, while 5492 * each node is a bin that is tagged as the length of the prefixes the lookup 5493 * will refer to. Therefore, bin X refers to a set of entries with prefixes 5494 * of X bits to match with the destination address. The bin 0 indicates 5495 * the default action, when there is no match of any prefix. 5496 */ 5497 #define MLXSW_REG_RALST_ID 0x8011 5498 #define MLXSW_REG_RALST_LEN 0x104 5499 5500 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 5501 5502 /* reg_ralst_root_bin 5503 * The bin number of the root bin. 5504 * 0<root_bin=<(length of IP address) 5505 * For a default-route tree configure 0xff 5506 * Access: RW 5507 */ 5508 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 5509 5510 /* reg_ralst_tree_id 5511 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5512 * Access: Index 5513 */ 5514 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 5515 5516 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 5517 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 5518 #define MLXSW_REG_RALST_BIN_COUNT 128 5519 5520 /* reg_ralst_left_child_bin 5521 * Holding the children of the bin according to the stored tree's structure. 5522 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5523 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5524 * Access: RW 5525 */ 5526 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 5527 5528 /* reg_ralst_right_child_bin 5529 * Holding the children of the bin according to the stored tree's structure. 5530 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5531 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5532 * Access: RW 5533 */ 5534 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 5535 false); 5536 5537 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 5538 { 5539 MLXSW_REG_ZERO(ralst, payload); 5540 5541 /* Initialize all bins to have no left or right child */ 5542 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 5543 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 5544 5545 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 5546 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 5547 } 5548 5549 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 5550 u8 left_child_bin, 5551 u8 right_child_bin) 5552 { 5553 int bin_index = bin_number - 1; 5554 5555 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 5556 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 5557 right_child_bin); 5558 } 5559 5560 /* RALTB - Router Algorithmic LPM Tree Binding Register 5561 * ---------------------------------------------------- 5562 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 5563 */ 5564 #define MLXSW_REG_RALTB_ID 0x8012 5565 #define MLXSW_REG_RALTB_LEN 0x04 5566 5567 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 5568 5569 /* reg_raltb_virtual_router 5570 * Virtual Router ID 5571 * Range is 0..cap_max_virtual_routers-1 5572 * Access: Index 5573 */ 5574 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 5575 5576 /* reg_raltb_protocol 5577 * Protocol. 5578 * Access: Index 5579 */ 5580 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 5581 5582 /* reg_raltb_tree_id 5583 * Tree to be used for the {virtual_router, protocol} 5584 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5585 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 5586 * Access: RW 5587 */ 5588 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 5589 5590 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 5591 enum mlxsw_reg_ralxx_protocol protocol, 5592 u8 tree_id) 5593 { 5594 MLXSW_REG_ZERO(raltb, payload); 5595 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 5596 mlxsw_reg_raltb_protocol_set(payload, protocol); 5597 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 5598 } 5599 5600 /* RALUE - Router Algorithmic LPM Unicast Entry Register 5601 * ----------------------------------------------------- 5602 * RALUE is used to configure and query LPM entries that serve 5603 * the Unicast protocols. 5604 */ 5605 #define MLXSW_REG_RALUE_ID 0x8013 5606 #define MLXSW_REG_RALUE_LEN 0x38 5607 5608 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 5609 5610 /* reg_ralue_protocol 5611 * Protocol. 5612 * Access: Index 5613 */ 5614 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 5615 5616 enum mlxsw_reg_ralue_op { 5617 /* Read operation. If entry doesn't exist, the operation fails. */ 5618 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 5619 /* Clear on read operation. Used to read entry and 5620 * clear Activity bit. 5621 */ 5622 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 5623 /* Write operation. Used to write a new entry to the table. All RW 5624 * fields are written for new entry. Activity bit is set 5625 * for new entries. 5626 */ 5627 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 5628 /* Update operation. Used to update an existing route entry and 5629 * only update the RW fields that are detailed in the field 5630 * op_u_mask. If entry doesn't exist, the operation fails. 5631 */ 5632 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 5633 /* Clear activity. The Activity bit (the field a) is cleared 5634 * for the entry. 5635 */ 5636 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 5637 /* Delete operation. Used to delete an existing entry. If entry 5638 * doesn't exist, the operation fails. 5639 */ 5640 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 5641 }; 5642 5643 /* reg_ralue_op 5644 * Operation. 5645 * Access: OP 5646 */ 5647 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 5648 5649 /* reg_ralue_a 5650 * Activity. Set for new entries. Set if a packet lookup has hit on the 5651 * specific entry, only if the entry is a route. To clear the a bit, use 5652 * "clear activity" op. 5653 * Enabled by activity_dis in RGCR 5654 * Access: RO 5655 */ 5656 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 5657 5658 /* reg_ralue_virtual_router 5659 * Virtual Router ID 5660 * Range is 0..cap_max_virtual_routers-1 5661 * Access: Index 5662 */ 5663 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 5664 5665 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 5666 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 5667 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 5668 5669 /* reg_ralue_op_u_mask 5670 * opcode update mask. 5671 * On read operation, this field is reserved. 5672 * This field is valid for update opcode, otherwise - reserved. 5673 * This field is a bitmask of the fields that should be updated. 5674 * Access: WO 5675 */ 5676 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 5677 5678 /* reg_ralue_prefix_len 5679 * Number of bits in the prefix of the LPM route. 5680 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 5681 * two entries in the physical HW table. 5682 * Access: Index 5683 */ 5684 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 5685 5686 /* reg_ralue_dip* 5687 * The prefix of the route or of the marker that the object of the LPM 5688 * is compared with. The most significant bits of the dip are the prefix. 5689 * The least significant bits must be '0' if the prefix_len is smaller 5690 * than 128 for IPv6 or smaller than 32 for IPv4. 5691 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 5692 * Access: Index 5693 */ 5694 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 5695 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 5696 5697 enum mlxsw_reg_ralue_entry_type { 5698 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 5699 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 5700 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 5701 }; 5702 5703 /* reg_ralue_entry_type 5704 * Entry type. 5705 * Note - for Marker entries, the action_type and action fields are reserved. 5706 * Access: RW 5707 */ 5708 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 5709 5710 /* reg_ralue_bmp_len 5711 * The best match prefix length in the case that there is no match for 5712 * longer prefixes. 5713 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 5714 * Note for any update operation with entry_type modification this 5715 * field must be set. 5716 * Access: RW 5717 */ 5718 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 5719 5720 enum mlxsw_reg_ralue_action_type { 5721 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 5722 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 5723 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 5724 }; 5725 5726 /* reg_ralue_action_type 5727 * Action Type 5728 * Indicates how the IP address is connected. 5729 * It can be connected to a local subnet through local_erif or can be 5730 * on a remote subnet connected through a next-hop router, 5731 * or transmitted to the CPU. 5732 * Reserved when entry_type = MARKER_ENTRY 5733 * Access: RW 5734 */ 5735 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 5736 5737 enum mlxsw_reg_ralue_trap_action { 5738 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 5739 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 5740 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 5741 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 5742 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 5743 }; 5744 5745 /* reg_ralue_trap_action 5746 * Trap action. 5747 * For IP2ME action, only NOP and MIRROR are possible. 5748 * Access: RW 5749 */ 5750 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 5751 5752 /* reg_ralue_trap_id 5753 * Trap ID to be reported to CPU. 5754 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 5755 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 5756 * Access: RW 5757 */ 5758 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 5759 5760 /* reg_ralue_adjacency_index 5761 * Points to the first entry of the group-based ECMP. 5762 * Only relevant in case of REMOTE action. 5763 * Access: RW 5764 */ 5765 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 5766 5767 /* reg_ralue_ecmp_size 5768 * Amount of sequential entries starting 5769 * from the adjacency_index (the number of ECMPs). 5770 * The valid range is 1-64, 512, 1024, 2048 and 4096. 5771 * Reserved when trap_action is TRAP or DISCARD_ERROR. 5772 * Only relevant in case of REMOTE action. 5773 * Access: RW 5774 */ 5775 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 5776 5777 /* reg_ralue_local_erif 5778 * Egress Router Interface. 5779 * Only relevant in case of LOCAL action. 5780 * Access: RW 5781 */ 5782 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 5783 5784 /* reg_ralue_ip2me_v 5785 * Valid bit for the tunnel_ptr field. 5786 * If valid = 0 then trap to CPU as IP2ME trap ID. 5787 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 5788 * decapsulation then tunnel decapsulation is done. 5789 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 5790 * decapsulation then trap as IP2ME trap ID. 5791 * Only relevant in case of IP2ME action. 5792 * Access: RW 5793 */ 5794 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 5795 5796 /* reg_ralue_ip2me_tunnel_ptr 5797 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 5798 * For Spectrum, pointer to KVD Linear. 5799 * Only relevant in case of IP2ME action. 5800 * Access: RW 5801 */ 5802 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 5803 5804 static inline void mlxsw_reg_ralue_pack(char *payload, 5805 enum mlxsw_reg_ralxx_protocol protocol, 5806 enum mlxsw_reg_ralue_op op, 5807 u16 virtual_router, u8 prefix_len) 5808 { 5809 MLXSW_REG_ZERO(ralue, payload); 5810 mlxsw_reg_ralue_protocol_set(payload, protocol); 5811 mlxsw_reg_ralue_op_set(payload, op); 5812 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 5813 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 5814 mlxsw_reg_ralue_entry_type_set(payload, 5815 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 5816 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 5817 } 5818 5819 static inline void mlxsw_reg_ralue_pack4(char *payload, 5820 enum mlxsw_reg_ralxx_protocol protocol, 5821 enum mlxsw_reg_ralue_op op, 5822 u16 virtual_router, u8 prefix_len, 5823 u32 dip) 5824 { 5825 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5826 mlxsw_reg_ralue_dip4_set(payload, dip); 5827 } 5828 5829 static inline void mlxsw_reg_ralue_pack6(char *payload, 5830 enum mlxsw_reg_ralxx_protocol protocol, 5831 enum mlxsw_reg_ralue_op op, 5832 u16 virtual_router, u8 prefix_len, 5833 const void *dip) 5834 { 5835 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5836 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 5837 } 5838 5839 static inline void 5840 mlxsw_reg_ralue_act_remote_pack(char *payload, 5841 enum mlxsw_reg_ralue_trap_action trap_action, 5842 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 5843 { 5844 mlxsw_reg_ralue_action_type_set(payload, 5845 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 5846 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5847 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5848 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 5849 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 5850 } 5851 5852 static inline void 5853 mlxsw_reg_ralue_act_local_pack(char *payload, 5854 enum mlxsw_reg_ralue_trap_action trap_action, 5855 u16 trap_id, u16 local_erif) 5856 { 5857 mlxsw_reg_ralue_action_type_set(payload, 5858 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 5859 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5860 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5861 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 5862 } 5863 5864 static inline void 5865 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 5866 { 5867 mlxsw_reg_ralue_action_type_set(payload, 5868 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5869 } 5870 5871 static inline void 5872 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 5873 { 5874 mlxsw_reg_ralue_action_type_set(payload, 5875 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5876 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 5877 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 5878 } 5879 5880 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 5881 * ---------------------------------------------------------- 5882 * The RAUHT register is used to configure and query the Unicast Host table in 5883 * devices that implement the Algorithmic LPM. 5884 */ 5885 #define MLXSW_REG_RAUHT_ID 0x8014 5886 #define MLXSW_REG_RAUHT_LEN 0x74 5887 5888 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 5889 5890 enum mlxsw_reg_rauht_type { 5891 MLXSW_REG_RAUHT_TYPE_IPV4, 5892 MLXSW_REG_RAUHT_TYPE_IPV6, 5893 }; 5894 5895 /* reg_rauht_type 5896 * Access: Index 5897 */ 5898 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 5899 5900 enum mlxsw_reg_rauht_op { 5901 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 5902 /* Read operation */ 5903 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 5904 /* Clear on read operation. Used to read entry and clear 5905 * activity bit. 5906 */ 5907 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 5908 /* Add. Used to write a new entry to the table. All R/W fields are 5909 * relevant for new entry. Activity bit is set for new entries. 5910 */ 5911 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 5912 /* Update action. Used to update an existing route entry and 5913 * only update the following fields: 5914 * trap_action, trap_id, mac, counter_set_type, counter_index 5915 */ 5916 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 5917 /* Clear activity. A bit is cleared for the entry. */ 5918 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 5919 /* Delete entry */ 5920 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 5921 /* Delete all host entries on a RIF. In this command, dip 5922 * field is reserved. 5923 */ 5924 }; 5925 5926 /* reg_rauht_op 5927 * Access: OP 5928 */ 5929 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 5930 5931 /* reg_rauht_a 5932 * Activity. Set for new entries. Set if a packet lookup has hit on 5933 * the specific entry. 5934 * To clear the a bit, use "clear activity" op. 5935 * Enabled by activity_dis in RGCR 5936 * Access: RO 5937 */ 5938 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 5939 5940 /* reg_rauht_rif 5941 * Router Interface 5942 * Access: Index 5943 */ 5944 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 5945 5946 /* reg_rauht_dip* 5947 * Destination address. 5948 * Access: Index 5949 */ 5950 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 5951 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 5952 5953 enum mlxsw_reg_rauht_trap_action { 5954 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 5955 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 5956 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 5957 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 5958 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 5959 }; 5960 5961 /* reg_rauht_trap_action 5962 * Access: RW 5963 */ 5964 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 5965 5966 enum mlxsw_reg_rauht_trap_id { 5967 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 5968 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 5969 }; 5970 5971 /* reg_rauht_trap_id 5972 * Trap ID to be reported to CPU. 5973 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5974 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 5975 * trap_id is reserved. 5976 * Access: RW 5977 */ 5978 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 5979 5980 /* reg_rauht_counter_set_type 5981 * Counter set type for flow counters 5982 * Access: RW 5983 */ 5984 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 5985 5986 /* reg_rauht_counter_index 5987 * Counter index for flow counters 5988 * Access: RW 5989 */ 5990 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 5991 5992 /* reg_rauht_mac 5993 * MAC address. 5994 * Access: RW 5995 */ 5996 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 5997 5998 static inline void mlxsw_reg_rauht_pack(char *payload, 5999 enum mlxsw_reg_rauht_op op, u16 rif, 6000 const char *mac) 6001 { 6002 MLXSW_REG_ZERO(rauht, payload); 6003 mlxsw_reg_rauht_op_set(payload, op); 6004 mlxsw_reg_rauht_rif_set(payload, rif); 6005 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 6006 } 6007 6008 static inline void mlxsw_reg_rauht_pack4(char *payload, 6009 enum mlxsw_reg_rauht_op op, u16 rif, 6010 const char *mac, u32 dip) 6011 { 6012 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6013 mlxsw_reg_rauht_dip4_set(payload, dip); 6014 } 6015 6016 static inline void mlxsw_reg_rauht_pack6(char *payload, 6017 enum mlxsw_reg_rauht_op op, u16 rif, 6018 const char *mac, const char *dip) 6019 { 6020 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6021 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 6022 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 6023 } 6024 6025 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 6026 u64 counter_index) 6027 { 6028 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 6029 mlxsw_reg_rauht_counter_set_type_set(payload, 6030 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 6031 } 6032 6033 /* RALEU - Router Algorithmic LPM ECMP Update Register 6034 * --------------------------------------------------- 6035 * The register enables updating the ECMP section in the action for multiple 6036 * LPM Unicast entries in a single operation. The update is executed to 6037 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 6038 */ 6039 #define MLXSW_REG_RALEU_ID 0x8015 6040 #define MLXSW_REG_RALEU_LEN 0x28 6041 6042 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 6043 6044 /* reg_raleu_protocol 6045 * Protocol. 6046 * Access: Index 6047 */ 6048 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 6049 6050 /* reg_raleu_virtual_router 6051 * Virtual Router ID 6052 * Range is 0..cap_max_virtual_routers-1 6053 * Access: Index 6054 */ 6055 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 6056 6057 /* reg_raleu_adjacency_index 6058 * Adjacency Index used for matching on the existing entries. 6059 * Access: Index 6060 */ 6061 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 6062 6063 /* reg_raleu_ecmp_size 6064 * ECMP Size used for matching on the existing entries. 6065 * Access: Index 6066 */ 6067 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 6068 6069 /* reg_raleu_new_adjacency_index 6070 * New Adjacency Index. 6071 * Access: WO 6072 */ 6073 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 6074 6075 /* reg_raleu_new_ecmp_size 6076 * New ECMP Size. 6077 * Access: WO 6078 */ 6079 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 6080 6081 static inline void mlxsw_reg_raleu_pack(char *payload, 6082 enum mlxsw_reg_ralxx_protocol protocol, 6083 u16 virtual_router, 6084 u32 adjacency_index, u16 ecmp_size, 6085 u32 new_adjacency_index, 6086 u16 new_ecmp_size) 6087 { 6088 MLXSW_REG_ZERO(raleu, payload); 6089 mlxsw_reg_raleu_protocol_set(payload, protocol); 6090 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 6091 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 6092 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 6093 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 6094 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 6095 } 6096 6097 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 6098 * ---------------------------------------------------------------- 6099 * The RAUHTD register allows dumping entries from the Router Unicast Host 6100 * Table. For a given session an entry is dumped no more than one time. The 6101 * first RAUHTD access after reset is a new session. A session ends when the 6102 * num_rec response is smaller than num_rec request or for IPv4 when the 6103 * num_entries is smaller than 4. The clear activity affect the current session 6104 * or the last session if a new session has not started. 6105 */ 6106 #define MLXSW_REG_RAUHTD_ID 0x8018 6107 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 6108 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 6109 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 6110 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 6111 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 6112 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 6113 6114 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 6115 6116 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 6117 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 6118 6119 /* reg_rauhtd_filter_fields 6120 * if a bit is '0' then the relevant field is ignored and dump is done 6121 * regardless of the field value 6122 * Bit0 - filter by activity: entry_a 6123 * Bit3 - filter by entry rip: entry_rif 6124 * Access: Index 6125 */ 6126 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 6127 6128 enum mlxsw_reg_rauhtd_op { 6129 MLXSW_REG_RAUHTD_OP_DUMP, 6130 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 6131 }; 6132 6133 /* reg_rauhtd_op 6134 * Access: OP 6135 */ 6136 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 6137 6138 /* reg_rauhtd_num_rec 6139 * At request: number of records requested 6140 * At response: number of records dumped 6141 * For IPv4, each record has 4 entries at request and up to 4 entries 6142 * at response 6143 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 6144 * Access: Index 6145 */ 6146 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 6147 6148 /* reg_rauhtd_entry_a 6149 * Dump only if activity has value of entry_a 6150 * Reserved if filter_fields bit0 is '0' 6151 * Access: Index 6152 */ 6153 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 6154 6155 enum mlxsw_reg_rauhtd_type { 6156 MLXSW_REG_RAUHTD_TYPE_IPV4, 6157 MLXSW_REG_RAUHTD_TYPE_IPV6, 6158 }; 6159 6160 /* reg_rauhtd_type 6161 * Dump only if record type is: 6162 * 0 - IPv4 6163 * 1 - IPv6 6164 * Access: Index 6165 */ 6166 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 6167 6168 /* reg_rauhtd_entry_rif 6169 * Dump only if RIF has value of entry_rif 6170 * Reserved if filter_fields bit3 is '0' 6171 * Access: Index 6172 */ 6173 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 6174 6175 static inline void mlxsw_reg_rauhtd_pack(char *payload, 6176 enum mlxsw_reg_rauhtd_type type) 6177 { 6178 MLXSW_REG_ZERO(rauhtd, payload); 6179 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 6180 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 6181 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 6182 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 6183 mlxsw_reg_rauhtd_type_set(payload, type); 6184 } 6185 6186 /* reg_rauhtd_ipv4_rec_num_entries 6187 * Number of valid entries in this record: 6188 * 0 - 1 valid entry 6189 * 1 - 2 valid entries 6190 * 2 - 3 valid entries 6191 * 3 - 4 valid entries 6192 * Access: RO 6193 */ 6194 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 6195 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 6196 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 6197 6198 /* reg_rauhtd_rec_type 6199 * Record type. 6200 * 0 - IPv4 6201 * 1 - IPv6 6202 * Access: RO 6203 */ 6204 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 6205 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 6206 6207 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 6208 6209 /* reg_rauhtd_ipv4_ent_a 6210 * Activity. Set for new entries. Set if a packet lookup has hit on the 6211 * specific entry. 6212 * Access: RO 6213 */ 6214 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 6215 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 6216 6217 /* reg_rauhtd_ipv4_ent_rif 6218 * Router interface. 6219 * Access: RO 6220 */ 6221 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6222 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 6223 6224 /* reg_rauhtd_ipv4_ent_dip 6225 * Destination IPv4 address. 6226 * Access: RO 6227 */ 6228 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6229 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 6230 6231 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 6232 6233 /* reg_rauhtd_ipv6_ent_a 6234 * Activity. Set for new entries. Set if a packet lookup has hit on the 6235 * specific entry. 6236 * Access: RO 6237 */ 6238 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 6239 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 6240 6241 /* reg_rauhtd_ipv6_ent_rif 6242 * Router interface. 6243 * Access: RO 6244 */ 6245 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6246 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 6247 6248 /* reg_rauhtd_ipv6_ent_dip 6249 * Destination IPv6 address. 6250 * Access: RO 6251 */ 6252 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 6253 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 6254 6255 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 6256 int ent_index, u16 *p_rif, 6257 u32 *p_dip) 6258 { 6259 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 6260 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 6261 } 6262 6263 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 6264 int rec_index, u16 *p_rif, 6265 char *p_dip) 6266 { 6267 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 6268 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 6269 } 6270 6271 /* RTDP - Routing Tunnel Decap Properties Register 6272 * ----------------------------------------------- 6273 * The RTDP register is used for configuring the tunnel decap properties of NVE 6274 * and IPinIP. 6275 */ 6276 #define MLXSW_REG_RTDP_ID 0x8020 6277 #define MLXSW_REG_RTDP_LEN 0x44 6278 6279 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 6280 6281 enum mlxsw_reg_rtdp_type { 6282 MLXSW_REG_RTDP_TYPE_NVE, 6283 MLXSW_REG_RTDP_TYPE_IPIP, 6284 }; 6285 6286 /* reg_rtdp_type 6287 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 6288 * Access: RW 6289 */ 6290 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 6291 6292 /* reg_rtdp_tunnel_index 6293 * Index to the Decap entry. 6294 * For Spectrum, Index to KVD Linear. 6295 * Access: Index 6296 */ 6297 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 6298 6299 /* IPinIP */ 6300 6301 /* reg_rtdp_ipip_irif 6302 * Ingress Router Interface for the overlay router 6303 * Access: RW 6304 */ 6305 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 6306 6307 enum mlxsw_reg_rtdp_ipip_sip_check { 6308 /* No sip checks. */ 6309 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 6310 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 6311 * equal ipv4_usip. 6312 */ 6313 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 6314 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 6315 * equal ipv6_usip. 6316 */ 6317 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 6318 }; 6319 6320 /* reg_rtdp_ipip_sip_check 6321 * SIP check to perform. If decapsulation failed due to these configurations 6322 * then trap_id is IPIP_DECAP_ERROR. 6323 * Access: RW 6324 */ 6325 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 6326 6327 /* If set, allow decapsulation of IPinIP (without GRE). */ 6328 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 6329 /* If set, allow decapsulation of IPinGREinIP without a key. */ 6330 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 6331 /* If set, allow decapsulation of IPinGREinIP with a key. */ 6332 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 6333 6334 /* reg_rtdp_ipip_type_check 6335 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 6336 * these configurations then trap_id is IPIP_DECAP_ERROR. 6337 * Access: RW 6338 */ 6339 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 6340 6341 /* reg_rtdp_ipip_gre_key_check 6342 * Whether GRE key should be checked. When check is enabled: 6343 * - A packet received as IPinIP (without GRE) will always pass. 6344 * - A packet received as IPinGREinIP without a key will not pass the check. 6345 * - A packet received as IPinGREinIP with a key will pass the check only if the 6346 * key in the packet is equal to expected_gre_key. 6347 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 6348 * Access: RW 6349 */ 6350 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 6351 6352 /* reg_rtdp_ipip_ipv4_usip 6353 * Underlay IPv4 address for ipv4 source address check. 6354 * Reserved when sip_check is not '1'. 6355 * Access: RW 6356 */ 6357 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 6358 6359 /* reg_rtdp_ipip_ipv6_usip_ptr 6360 * This field is valid when sip_check is "sipv6 check explicitly". This is a 6361 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 6362 * is to the KVD linear. 6363 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 6364 * Access: RW 6365 */ 6366 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 6367 6368 /* reg_rtdp_ipip_expected_gre_key 6369 * GRE key for checking. 6370 * Reserved when gre_key_check is '0'. 6371 * Access: RW 6372 */ 6373 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 6374 6375 static inline void mlxsw_reg_rtdp_pack(char *payload, 6376 enum mlxsw_reg_rtdp_type type, 6377 u32 tunnel_index) 6378 { 6379 MLXSW_REG_ZERO(rtdp, payload); 6380 mlxsw_reg_rtdp_type_set(payload, type); 6381 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 6382 } 6383 6384 static inline void 6385 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 6386 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 6387 unsigned int type_check, bool gre_key_check, 6388 u32 ipv4_usip, u32 expected_gre_key) 6389 { 6390 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 6391 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 6392 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 6393 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 6394 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 6395 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 6396 } 6397 6398 /* RIGR-V2 - Router Interface Group Register Version 2 6399 * --------------------------------------------------- 6400 * The RIGR_V2 register is used to add, remove and query egress interface list 6401 * of a multicast forwarding entry. 6402 */ 6403 #define MLXSW_REG_RIGR2_ID 0x8023 6404 #define MLXSW_REG_RIGR2_LEN 0xB0 6405 6406 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 6407 6408 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 6409 6410 /* reg_rigr2_rigr_index 6411 * KVD Linear index. 6412 * Access: Index 6413 */ 6414 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 6415 6416 /* reg_rigr2_vnext 6417 * Next RIGR Index is valid. 6418 * Access: RW 6419 */ 6420 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 6421 6422 /* reg_rigr2_next_rigr_index 6423 * Next RIGR Index. The index is to the KVD linear. 6424 * Reserved when vnxet = '0'. 6425 * Access: RW 6426 */ 6427 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 6428 6429 /* reg_rigr2_vrmid 6430 * RMID Index is valid. 6431 * Access: RW 6432 */ 6433 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 6434 6435 /* reg_rigr2_rmid_index 6436 * RMID Index. 6437 * Range 0 .. max_mid - 1 6438 * Reserved when vrmid = '0'. 6439 * The index is to the Port Group Table (PGT) 6440 * Access: RW 6441 */ 6442 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 6443 6444 /* reg_rigr2_erif_entry_v 6445 * Egress Router Interface is valid. 6446 * Note that low-entries must be set if high-entries are set. For 6447 * example: if erif_entry[2].v is set then erif_entry[1].v and 6448 * erif_entry[0].v must be set. 6449 * Index can be from 0 to cap_mc_erif_list_entries-1 6450 * Access: RW 6451 */ 6452 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 6453 6454 /* reg_rigr2_erif_entry_erif 6455 * Egress Router Interface. 6456 * Valid range is from 0 to cap_max_router_interfaces - 1 6457 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 6458 * Access: RW 6459 */ 6460 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 6461 6462 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 6463 bool vnext, u32 next_rigr_index) 6464 { 6465 MLXSW_REG_ZERO(rigr2, payload); 6466 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 6467 mlxsw_reg_rigr2_vnext_set(payload, vnext); 6468 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 6469 mlxsw_reg_rigr2_vrmid_set(payload, 0); 6470 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 6471 } 6472 6473 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 6474 bool v, u16 erif) 6475 { 6476 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 6477 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 6478 } 6479 6480 /* RECR-V2 - Router ECMP Configuration Version 2 Register 6481 * ------------------------------------------------------ 6482 */ 6483 #define MLXSW_REG_RECR2_ID 0x8025 6484 #define MLXSW_REG_RECR2_LEN 0x38 6485 6486 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 6487 6488 /* reg_recr2_pp 6489 * Per-port configuration 6490 * Access: Index 6491 */ 6492 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 6493 6494 /* reg_recr2_sh 6495 * Symmetric hash 6496 * Access: RW 6497 */ 6498 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 6499 6500 /* reg_recr2_seed 6501 * Seed 6502 * Access: RW 6503 */ 6504 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 6505 6506 enum { 6507 /* Enable IPv4 fields if packet is not TCP and not UDP */ 6508 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 6509 /* Enable IPv4 fields if packet is TCP or UDP */ 6510 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 6511 /* Enable IPv6 fields if packet is not TCP and not UDP */ 6512 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 6513 /* Enable IPv6 fields if packet is TCP or UDP */ 6514 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 6515 /* Enable TCP/UDP header fields if packet is IPv4 */ 6516 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 6517 /* Enable TCP/UDP header fields if packet is IPv6 */ 6518 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 6519 }; 6520 6521 /* reg_recr2_outer_header_enables 6522 * Bit mask where each bit enables a specific layer to be included in 6523 * the hash calculation. 6524 * Access: RW 6525 */ 6526 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 6527 6528 enum { 6529 /* IPv4 Source IP */ 6530 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 6531 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 6532 /* IPv4 Destination IP */ 6533 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 6534 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 6535 /* IP Protocol */ 6536 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 6537 /* IPv6 Source IP */ 6538 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 6539 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 6540 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 6541 /* IPv6 Destination IP */ 6542 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 6543 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 6544 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 6545 /* IPv6 Next Header */ 6546 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 6547 /* IPv6 Flow Label */ 6548 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 6549 /* TCP/UDP Source Port */ 6550 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 6551 /* TCP/UDP Destination Port */ 6552 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 6553 }; 6554 6555 /* reg_recr2_outer_header_fields_enable 6556 * Packet fields to enable for ECMP hash subject to outer_header_enable. 6557 * Access: RW 6558 */ 6559 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 6560 6561 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 6562 { 6563 int i; 6564 6565 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 6566 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6567 true); 6568 } 6569 6570 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 6571 { 6572 int i; 6573 6574 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 6575 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6576 true); 6577 } 6578 6579 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 6580 { 6581 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 6582 6583 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6584 6585 i = MLXSW_REG_RECR2_IPV6_SIP8; 6586 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 6587 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6588 true); 6589 } 6590 6591 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 6592 { 6593 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 6594 6595 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6596 6597 i = MLXSW_REG_RECR2_IPV6_DIP8; 6598 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 6599 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6600 true); 6601 } 6602 6603 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 6604 { 6605 MLXSW_REG_ZERO(recr2, payload); 6606 mlxsw_reg_recr2_pp_set(payload, false); 6607 mlxsw_reg_recr2_sh_set(payload, true); 6608 mlxsw_reg_recr2_seed_set(payload, seed); 6609 } 6610 6611 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 6612 * -------------------------------------------------------------- 6613 * The RMFT_V2 register is used to configure and query the multicast table. 6614 */ 6615 #define MLXSW_REG_RMFT2_ID 0x8027 6616 #define MLXSW_REG_RMFT2_LEN 0x174 6617 6618 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 6619 6620 /* reg_rmft2_v 6621 * Valid 6622 * Access: RW 6623 */ 6624 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 6625 6626 enum mlxsw_reg_rmft2_type { 6627 MLXSW_REG_RMFT2_TYPE_IPV4, 6628 MLXSW_REG_RMFT2_TYPE_IPV6 6629 }; 6630 6631 /* reg_rmft2_type 6632 * Access: Index 6633 */ 6634 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 6635 6636 enum mlxsw_sp_reg_rmft2_op { 6637 /* For Write: 6638 * Write operation. Used to write a new entry to the table. All RW 6639 * fields are relevant for new entry. Activity bit is set for new 6640 * entries - Note write with v (Valid) 0 will delete the entry. 6641 * For Query: 6642 * Read operation 6643 */ 6644 MLXSW_REG_RMFT2_OP_READ_WRITE, 6645 }; 6646 6647 /* reg_rmft2_op 6648 * Operation. 6649 * Access: OP 6650 */ 6651 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 6652 6653 /* reg_rmft2_a 6654 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 6655 * entry. 6656 * Access: RO 6657 */ 6658 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 6659 6660 /* reg_rmft2_offset 6661 * Offset within the multicast forwarding table to write to. 6662 * Access: Index 6663 */ 6664 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 6665 6666 /* reg_rmft2_virtual_router 6667 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 6668 * Access: RW 6669 */ 6670 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 6671 6672 enum mlxsw_reg_rmft2_irif_mask { 6673 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 6674 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 6675 }; 6676 6677 /* reg_rmft2_irif_mask 6678 * Ingress RIF mask. 6679 * Access: RW 6680 */ 6681 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 6682 6683 /* reg_rmft2_irif 6684 * Ingress RIF index. 6685 * Access: RW 6686 */ 6687 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 6688 6689 /* reg_rmft2_dip{4,6} 6690 * Destination IPv4/6 address 6691 * Access: RW 6692 */ 6693 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 6694 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 6695 6696 /* reg_rmft2_dip{4,6}_mask 6697 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6698 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6699 * Access: RW 6700 */ 6701 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 6702 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 6703 6704 /* reg_rmft2_sip{4,6} 6705 * Source IPv4/6 address 6706 * Access: RW 6707 */ 6708 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 6709 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 6710 6711 /* reg_rmft2_sip{4,6}_mask 6712 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6713 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6714 * Access: RW 6715 */ 6716 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 6717 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 6718 6719 /* reg_rmft2_flexible_action_set 6720 * ACL action set. The only supported action types in this field and in any 6721 * action-set pointed from here are as follows: 6722 * 00h: ACTION_NULL 6723 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 6724 * 03h: ACTION_TRAP 6725 * 06h: ACTION_QOS 6726 * 08h: ACTION_POLICING_MONITORING 6727 * 10h: ACTION_ROUTER_MC 6728 * Access: RW 6729 */ 6730 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 6731 MLXSW_REG_FLEX_ACTION_SET_LEN); 6732 6733 static inline void 6734 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 6735 u16 virtual_router, 6736 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6737 const char *flex_action_set) 6738 { 6739 MLXSW_REG_ZERO(rmft2, payload); 6740 mlxsw_reg_rmft2_v_set(payload, v); 6741 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 6742 mlxsw_reg_rmft2_offset_set(payload, offset); 6743 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 6744 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 6745 mlxsw_reg_rmft2_irif_set(payload, irif); 6746 if (flex_action_set) 6747 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 6748 flex_action_set); 6749 } 6750 6751 static inline void 6752 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 6753 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6754 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 6755 const char *flexible_action_set) 6756 { 6757 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 6758 irif_mask, irif, flexible_action_set); 6759 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 6760 mlxsw_reg_rmft2_dip4_set(payload, dip4); 6761 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 6762 mlxsw_reg_rmft2_sip4_set(payload, sip4); 6763 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 6764 } 6765 6766 static inline void 6767 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 6768 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6769 struct in6_addr dip6, struct in6_addr dip6_mask, 6770 struct in6_addr sip6, struct in6_addr sip6_mask, 6771 const char *flexible_action_set) 6772 { 6773 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 6774 irif_mask, irif, flexible_action_set); 6775 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 6776 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 6777 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 6778 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 6779 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 6780 } 6781 6782 /* MFCR - Management Fan Control Register 6783 * -------------------------------------- 6784 * This register controls the settings of the Fan Speed PWM mechanism. 6785 */ 6786 #define MLXSW_REG_MFCR_ID 0x9001 6787 #define MLXSW_REG_MFCR_LEN 0x08 6788 6789 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 6790 6791 enum mlxsw_reg_mfcr_pwm_frequency { 6792 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 6793 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 6794 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 6795 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 6796 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 6797 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 6798 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 6799 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 6800 }; 6801 6802 /* reg_mfcr_pwm_frequency 6803 * Controls the frequency of the PWM signal. 6804 * Access: RW 6805 */ 6806 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 6807 6808 #define MLXSW_MFCR_TACHOS_MAX 10 6809 6810 /* reg_mfcr_tacho_active 6811 * Indicates which of the tachometer is active (bit per tachometer). 6812 * Access: RO 6813 */ 6814 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 6815 6816 #define MLXSW_MFCR_PWMS_MAX 5 6817 6818 /* reg_mfcr_pwm_active 6819 * Indicates which of the PWM control is active (bit per PWM). 6820 * Access: RO 6821 */ 6822 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 6823 6824 static inline void 6825 mlxsw_reg_mfcr_pack(char *payload, 6826 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 6827 { 6828 MLXSW_REG_ZERO(mfcr, payload); 6829 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 6830 } 6831 6832 static inline void 6833 mlxsw_reg_mfcr_unpack(char *payload, 6834 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 6835 u16 *p_tacho_active, u8 *p_pwm_active) 6836 { 6837 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 6838 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 6839 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 6840 } 6841 6842 /* MFSC - Management Fan Speed Control Register 6843 * -------------------------------------------- 6844 * This register controls the settings of the Fan Speed PWM mechanism. 6845 */ 6846 #define MLXSW_REG_MFSC_ID 0x9002 6847 #define MLXSW_REG_MFSC_LEN 0x08 6848 6849 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 6850 6851 /* reg_mfsc_pwm 6852 * Fan pwm to control / monitor. 6853 * Access: Index 6854 */ 6855 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 6856 6857 /* reg_mfsc_pwm_duty_cycle 6858 * Controls the duty cycle of the PWM. Value range from 0..255 to 6859 * represent duty cycle of 0%...100%. 6860 * Access: RW 6861 */ 6862 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 6863 6864 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 6865 u8 pwm_duty_cycle) 6866 { 6867 MLXSW_REG_ZERO(mfsc, payload); 6868 mlxsw_reg_mfsc_pwm_set(payload, pwm); 6869 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 6870 } 6871 6872 /* MFSM - Management Fan Speed Measurement 6873 * --------------------------------------- 6874 * This register controls the settings of the Tacho measurements and 6875 * enables reading the Tachometer measurements. 6876 */ 6877 #define MLXSW_REG_MFSM_ID 0x9003 6878 #define MLXSW_REG_MFSM_LEN 0x08 6879 6880 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 6881 6882 /* reg_mfsm_tacho 6883 * Fan tachometer index. 6884 * Access: Index 6885 */ 6886 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 6887 6888 /* reg_mfsm_rpm 6889 * Fan speed (round per minute). 6890 * Access: RO 6891 */ 6892 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 6893 6894 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 6895 { 6896 MLXSW_REG_ZERO(mfsm, payload); 6897 mlxsw_reg_mfsm_tacho_set(payload, tacho); 6898 } 6899 6900 /* MFSL - Management Fan Speed Limit Register 6901 * ------------------------------------------ 6902 * The Fan Speed Limit register is used to configure the fan speed 6903 * event / interrupt notification mechanism. Fan speed threshold are 6904 * defined for both under-speed and over-speed. 6905 */ 6906 #define MLXSW_REG_MFSL_ID 0x9004 6907 #define MLXSW_REG_MFSL_LEN 0x0C 6908 6909 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 6910 6911 /* reg_mfsl_tacho 6912 * Fan tachometer index. 6913 * Access: Index 6914 */ 6915 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 6916 6917 /* reg_mfsl_tach_min 6918 * Tachometer minimum value (minimum RPM). 6919 * Access: RW 6920 */ 6921 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 6922 6923 /* reg_mfsl_tach_max 6924 * Tachometer maximum value (maximum RPM). 6925 * Access: RW 6926 */ 6927 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 6928 6929 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 6930 u16 tach_min, u16 tach_max) 6931 { 6932 MLXSW_REG_ZERO(mfsl, payload); 6933 mlxsw_reg_mfsl_tacho_set(payload, tacho); 6934 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 6935 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 6936 } 6937 6938 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 6939 u16 *p_tach_min, u16 *p_tach_max) 6940 { 6941 if (p_tach_min) 6942 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 6943 6944 if (p_tach_max) 6945 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 6946 } 6947 6948 /* MTCAP - Management Temperature Capabilities 6949 * ------------------------------------------- 6950 * This register exposes the capabilities of the device and 6951 * system temperature sensing. 6952 */ 6953 #define MLXSW_REG_MTCAP_ID 0x9009 6954 #define MLXSW_REG_MTCAP_LEN 0x08 6955 6956 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 6957 6958 /* reg_mtcap_sensor_count 6959 * Number of sensors supported by the device. 6960 * This includes the QSFP module sensors (if exists in the QSFP module). 6961 * Access: RO 6962 */ 6963 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 6964 6965 /* MTMP - Management Temperature 6966 * ----------------------------- 6967 * This register controls the settings of the temperature measurements 6968 * and enables reading the temperature measurements. Note that temperature 6969 * is in 0.125 degrees Celsius. 6970 */ 6971 #define MLXSW_REG_MTMP_ID 0x900A 6972 #define MLXSW_REG_MTMP_LEN 0x20 6973 6974 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 6975 6976 /* reg_mtmp_sensor_index 6977 * Sensors index to access. 6978 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 6979 * (module 0 is mapped to sensor_index 64). 6980 * Access: Index 6981 */ 6982 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 6983 6984 /* Convert to milli degrees Celsius */ 6985 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 6986 6987 /* reg_mtmp_temperature 6988 * Temperature reading from the sensor. Reading is in 0.125 Celsius 6989 * degrees units. 6990 * Access: RO 6991 */ 6992 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 6993 6994 /* reg_mtmp_mte 6995 * Max Temperature Enable - enables measuring the max temperature on a sensor. 6996 * Access: RW 6997 */ 6998 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 6999 7000 /* reg_mtmp_mtr 7001 * Max Temperature Reset - clears the value of the max temperature register. 7002 * Access: WO 7003 */ 7004 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 7005 7006 /* reg_mtmp_max_temperature 7007 * The highest measured temperature from the sensor. 7008 * When the bit mte is cleared, the field max_temperature is reserved. 7009 * Access: RO 7010 */ 7011 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 7012 7013 /* reg_mtmp_tee 7014 * Temperature Event Enable. 7015 * 0 - Do not generate event 7016 * 1 - Generate event 7017 * 2 - Generate single event 7018 * Access: RW 7019 */ 7020 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 7021 7022 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 7023 7024 /* reg_mtmp_temperature_threshold_hi 7025 * High threshold for Temperature Warning Event. In 0.125 Celsius. 7026 * Access: RW 7027 */ 7028 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 7029 7030 /* reg_mtmp_temperature_threshold_lo 7031 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 7032 * Access: RW 7033 */ 7034 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 7035 7036 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 7037 7038 /* reg_mtmp_sensor_name 7039 * Sensor Name 7040 * Access: RO 7041 */ 7042 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 7043 7044 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 7045 bool max_temp_enable, 7046 bool max_temp_reset) 7047 { 7048 MLXSW_REG_ZERO(mtmp, payload); 7049 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 7050 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 7051 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 7052 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 7053 MLXSW_REG_MTMP_THRESH_HI); 7054 } 7055 7056 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 7057 unsigned int *p_max_temp, 7058 char *sensor_name) 7059 { 7060 u16 temp; 7061 7062 if (p_temp) { 7063 temp = mlxsw_reg_mtmp_temperature_get(payload); 7064 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7065 } 7066 if (p_max_temp) { 7067 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 7068 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7069 } 7070 if (sensor_name) 7071 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 7072 } 7073 7074 /* MCIA - Management Cable Info Access 7075 * ----------------------------------- 7076 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 7077 */ 7078 7079 #define MLXSW_REG_MCIA_ID 0x9014 7080 #define MLXSW_REG_MCIA_LEN 0x40 7081 7082 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 7083 7084 /* reg_mcia_l 7085 * Lock bit. Setting this bit will lock the access to the specific 7086 * cable. Used for updating a full page in a cable EPROM. Any access 7087 * other then subsequence writes will fail while the port is locked. 7088 * Access: RW 7089 */ 7090 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 7091 7092 /* reg_mcia_module 7093 * Module number. 7094 * Access: Index 7095 */ 7096 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 7097 7098 /* reg_mcia_status 7099 * Module status. 7100 * Access: RO 7101 */ 7102 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 7103 7104 /* reg_mcia_i2c_device_address 7105 * I2C device address. 7106 * Access: RW 7107 */ 7108 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 7109 7110 /* reg_mcia_page_number 7111 * Page number. 7112 * Access: RW 7113 */ 7114 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 7115 7116 /* reg_mcia_device_address 7117 * Device address. 7118 * Access: RW 7119 */ 7120 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 7121 7122 /* reg_mcia_size 7123 * Number of bytes to read/write (up to 48 bytes). 7124 * Access: RW 7125 */ 7126 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 7127 7128 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 7129 7130 /* reg_mcia_eeprom 7131 * Bytes to read/write. 7132 * Access: RW 7133 */ 7134 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 7135 7136 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 7137 u8 page_number, u16 device_addr, 7138 u8 size, u8 i2c_device_addr) 7139 { 7140 MLXSW_REG_ZERO(mcia, payload); 7141 mlxsw_reg_mcia_module_set(payload, module); 7142 mlxsw_reg_mcia_l_set(payload, lock); 7143 mlxsw_reg_mcia_page_number_set(payload, page_number); 7144 mlxsw_reg_mcia_device_address_set(payload, device_addr); 7145 mlxsw_reg_mcia_size_set(payload, size); 7146 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 7147 } 7148 7149 /* MPAT - Monitoring Port Analyzer Table 7150 * ------------------------------------- 7151 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 7152 * For an enabled analyzer, all fields except e (enable) cannot be modified. 7153 */ 7154 #define MLXSW_REG_MPAT_ID 0x901A 7155 #define MLXSW_REG_MPAT_LEN 0x78 7156 7157 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 7158 7159 /* reg_mpat_pa_id 7160 * Port Analyzer ID. 7161 * Access: Index 7162 */ 7163 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 7164 7165 /* reg_mpat_system_port 7166 * A unique port identifier for the final destination of the packet. 7167 * Access: RW 7168 */ 7169 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 7170 7171 /* reg_mpat_e 7172 * Enable. Indicating the Port Analyzer is enabled. 7173 * Access: RW 7174 */ 7175 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 7176 7177 /* reg_mpat_qos 7178 * Quality Of Service Mode. 7179 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 7180 * PCP, DEI, DSCP or VL) are configured. 7181 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 7182 * same as in the original packet that has triggered the mirroring. For 7183 * SPAN also the pcp,dei are maintained. 7184 * Access: RW 7185 */ 7186 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 7187 7188 /* reg_mpat_be 7189 * Best effort mode. Indicates mirroring traffic should not cause packet 7190 * drop or back pressure, but will discard the mirrored packets. Mirrored 7191 * packets will be forwarded on a best effort manner. 7192 * 0: Do not discard mirrored packets 7193 * 1: Discard mirrored packets if causing congestion 7194 * Access: RW 7195 */ 7196 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 7197 7198 enum mlxsw_reg_mpat_span_type { 7199 /* Local SPAN Ethernet. 7200 * The original packet is not encapsulated. 7201 */ 7202 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 7203 7204 /* Remote SPAN Ethernet VLAN. 7205 * The packet is forwarded to the monitoring port on the monitoring 7206 * VLAN. 7207 */ 7208 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 7209 7210 /* Encapsulated Remote SPAN Ethernet L3 GRE. 7211 * The packet is encapsulated with GRE header. 7212 */ 7213 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 7214 }; 7215 7216 /* reg_mpat_span_type 7217 * SPAN type. 7218 * Access: RW 7219 */ 7220 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 7221 7222 /* Remote SPAN - Ethernet VLAN 7223 * - - - - - - - - - - - - - - 7224 */ 7225 7226 /* reg_mpat_eth_rspan_vid 7227 * Encapsulation header VLAN ID. 7228 * Access: RW 7229 */ 7230 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 7231 7232 /* Encapsulated Remote SPAN - Ethernet L2 7233 * - - - - - - - - - - - - - - - - - - - 7234 */ 7235 7236 enum mlxsw_reg_mpat_eth_rspan_version { 7237 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 7238 }; 7239 7240 /* reg_mpat_eth_rspan_version 7241 * RSPAN mirror header version. 7242 * Access: RW 7243 */ 7244 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 7245 7246 /* reg_mpat_eth_rspan_mac 7247 * Destination MAC address. 7248 * Access: RW 7249 */ 7250 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 7251 7252 /* reg_mpat_eth_rspan_tp 7253 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 7254 * Access: RW 7255 */ 7256 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 7257 7258 /* Encapsulated Remote SPAN - Ethernet L3 7259 * - - - - - - - - - - - - - - - - - - - 7260 */ 7261 7262 enum mlxsw_reg_mpat_eth_rspan_protocol { 7263 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 7264 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 7265 }; 7266 7267 /* reg_mpat_eth_rspan_protocol 7268 * SPAN encapsulation protocol. 7269 * Access: RW 7270 */ 7271 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 7272 7273 /* reg_mpat_eth_rspan_ttl 7274 * Encapsulation header Time-to-Live/HopLimit. 7275 * Access: RW 7276 */ 7277 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 7278 7279 /* reg_mpat_eth_rspan_smac 7280 * Source MAC address 7281 * Access: RW 7282 */ 7283 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 7284 7285 /* reg_mpat_eth_rspan_dip* 7286 * Destination IP address. The IP version is configured by protocol. 7287 * Access: RW 7288 */ 7289 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 7290 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 7291 7292 /* reg_mpat_eth_rspan_sip* 7293 * Source IP address. The IP version is configured by protocol. 7294 * Access: RW 7295 */ 7296 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 7297 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 7298 7299 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 7300 u16 system_port, bool e, 7301 enum mlxsw_reg_mpat_span_type span_type) 7302 { 7303 MLXSW_REG_ZERO(mpat, payload); 7304 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 7305 mlxsw_reg_mpat_system_port_set(payload, system_port); 7306 mlxsw_reg_mpat_e_set(payload, e); 7307 mlxsw_reg_mpat_qos_set(payload, 1); 7308 mlxsw_reg_mpat_be_set(payload, 1); 7309 mlxsw_reg_mpat_span_type_set(payload, span_type); 7310 } 7311 7312 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 7313 { 7314 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 7315 } 7316 7317 static inline void 7318 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 7319 enum mlxsw_reg_mpat_eth_rspan_version version, 7320 const char *mac, 7321 bool tp) 7322 { 7323 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 7324 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 7325 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 7326 } 7327 7328 static inline void 7329 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 7330 const char *smac, 7331 u32 sip, u32 dip) 7332 { 7333 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 7334 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 7335 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 7336 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 7337 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 7338 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 7339 } 7340 7341 static inline void 7342 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 7343 const char *smac, 7344 struct in6_addr sip, struct in6_addr dip) 7345 { 7346 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 7347 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 7348 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 7349 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 7350 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 7351 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 7352 } 7353 7354 /* MPAR - Monitoring Port Analyzer Register 7355 * ---------------------------------------- 7356 * MPAR register is used to query and configure the port analyzer port mirroring 7357 * properties. 7358 */ 7359 #define MLXSW_REG_MPAR_ID 0x901B 7360 #define MLXSW_REG_MPAR_LEN 0x08 7361 7362 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 7363 7364 /* reg_mpar_local_port 7365 * The local port to mirror the packets from. 7366 * Access: Index 7367 */ 7368 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 7369 7370 enum mlxsw_reg_mpar_i_e { 7371 MLXSW_REG_MPAR_TYPE_EGRESS, 7372 MLXSW_REG_MPAR_TYPE_INGRESS, 7373 }; 7374 7375 /* reg_mpar_i_e 7376 * Ingress/Egress 7377 * Access: Index 7378 */ 7379 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 7380 7381 /* reg_mpar_enable 7382 * Enable mirroring 7383 * By default, port mirroring is disabled for all ports. 7384 * Access: RW 7385 */ 7386 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 7387 7388 /* reg_mpar_pa_id 7389 * Port Analyzer ID. 7390 * Access: RW 7391 */ 7392 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 7393 7394 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 7395 enum mlxsw_reg_mpar_i_e i_e, 7396 bool enable, u8 pa_id) 7397 { 7398 MLXSW_REG_ZERO(mpar, payload); 7399 mlxsw_reg_mpar_local_port_set(payload, local_port); 7400 mlxsw_reg_mpar_enable_set(payload, enable); 7401 mlxsw_reg_mpar_i_e_set(payload, i_e); 7402 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 7403 } 7404 7405 /* MRSR - Management Reset and Shutdown Register 7406 * --------------------------------------------- 7407 * MRSR register is used to reset or shutdown the switch or 7408 * the entire system (when applicable). 7409 */ 7410 #define MLXSW_REG_MRSR_ID 0x9023 7411 #define MLXSW_REG_MRSR_LEN 0x08 7412 7413 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 7414 7415 /* reg_mrsr_command 7416 * Reset/shutdown command 7417 * 0 - do nothing 7418 * 1 - software reset 7419 * Access: WO 7420 */ 7421 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 7422 7423 static inline void mlxsw_reg_mrsr_pack(char *payload) 7424 { 7425 MLXSW_REG_ZERO(mrsr, payload); 7426 mlxsw_reg_mrsr_command_set(payload, 1); 7427 } 7428 7429 /* MLCR - Management LED Control Register 7430 * -------------------------------------- 7431 * Controls the system LEDs. 7432 */ 7433 #define MLXSW_REG_MLCR_ID 0x902B 7434 #define MLXSW_REG_MLCR_LEN 0x0C 7435 7436 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 7437 7438 /* reg_mlcr_local_port 7439 * Local port number. 7440 * Access: RW 7441 */ 7442 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 7443 7444 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 7445 7446 /* reg_mlcr_beacon_duration 7447 * Duration of the beacon to be active, in seconds. 7448 * 0x0 - Will turn off the beacon. 7449 * 0xFFFF - Will turn on the beacon until explicitly turned off. 7450 * Access: RW 7451 */ 7452 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 7453 7454 /* reg_mlcr_beacon_remain 7455 * Remaining duration of the beacon, in seconds. 7456 * 0xFFFF indicates an infinite amount of time. 7457 * Access: RO 7458 */ 7459 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 7460 7461 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 7462 bool active) 7463 { 7464 MLXSW_REG_ZERO(mlcr, payload); 7465 mlxsw_reg_mlcr_local_port_set(payload, local_port); 7466 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 7467 MLXSW_REG_MLCR_DURATION_MAX : 0); 7468 } 7469 7470 /* MCQI - Management Component Query Information 7471 * --------------------------------------------- 7472 * This register allows querying information about firmware components. 7473 */ 7474 #define MLXSW_REG_MCQI_ID 0x9061 7475 #define MLXSW_REG_MCQI_BASE_LEN 0x18 7476 #define MLXSW_REG_MCQI_CAP_LEN 0x14 7477 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 7478 7479 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 7480 7481 /* reg_mcqi_component_index 7482 * Index of the accessed component. 7483 * Access: Index 7484 */ 7485 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 7486 7487 enum mlxfw_reg_mcqi_info_type { 7488 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 7489 }; 7490 7491 /* reg_mcqi_info_type 7492 * Component properties set. 7493 * Access: RW 7494 */ 7495 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 7496 7497 /* reg_mcqi_offset 7498 * The requested/returned data offset from the section start, given in bytes. 7499 * Must be DWORD aligned. 7500 * Access: RW 7501 */ 7502 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 7503 7504 /* reg_mcqi_data_size 7505 * The requested/returned data size, given in bytes. If data_size is not DWORD 7506 * aligned, the last bytes are zero padded. 7507 * Access: RW 7508 */ 7509 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 7510 7511 /* reg_mcqi_cap_max_component_size 7512 * Maximum size for this component, given in bytes. 7513 * Access: RO 7514 */ 7515 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 7516 7517 /* reg_mcqi_cap_log_mcda_word_size 7518 * Log 2 of the access word size in bytes. Read and write access must be aligned 7519 * to the word size. Write access must be done for an integer number of words. 7520 * Access: RO 7521 */ 7522 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 7523 7524 /* reg_mcqi_cap_mcda_max_write_size 7525 * Maximal write size for MCDA register 7526 * Access: RO 7527 */ 7528 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 7529 7530 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 7531 { 7532 MLXSW_REG_ZERO(mcqi, payload); 7533 mlxsw_reg_mcqi_component_index_set(payload, component_index); 7534 mlxsw_reg_mcqi_info_type_set(payload, 7535 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 7536 mlxsw_reg_mcqi_offset_set(payload, 0); 7537 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 7538 } 7539 7540 static inline void mlxsw_reg_mcqi_unpack(char *payload, 7541 u32 *p_cap_max_component_size, 7542 u8 *p_cap_log_mcda_word_size, 7543 u16 *p_cap_mcda_max_write_size) 7544 { 7545 *p_cap_max_component_size = 7546 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 7547 *p_cap_log_mcda_word_size = 7548 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 7549 *p_cap_mcda_max_write_size = 7550 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 7551 } 7552 7553 /* MCC - Management Component Control 7554 * ---------------------------------- 7555 * Controls the firmware component and updates the FSM. 7556 */ 7557 #define MLXSW_REG_MCC_ID 0x9062 7558 #define MLXSW_REG_MCC_LEN 0x1C 7559 7560 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 7561 7562 enum mlxsw_reg_mcc_instruction { 7563 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 7564 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 7565 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 7566 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 7567 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 7568 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 7569 }; 7570 7571 /* reg_mcc_instruction 7572 * Command to be executed by the FSM. 7573 * Applicable for write operation only. 7574 * Access: RW 7575 */ 7576 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 7577 7578 /* reg_mcc_component_index 7579 * Index of the accessed component. Applicable only for commands that 7580 * refer to components. Otherwise, this field is reserved. 7581 * Access: Index 7582 */ 7583 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 7584 7585 /* reg_mcc_update_handle 7586 * Token representing the current flow executed by the FSM. 7587 * Access: WO 7588 */ 7589 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 7590 7591 /* reg_mcc_error_code 7592 * Indicates the successful completion of the instruction, or the reason it 7593 * failed 7594 * Access: RO 7595 */ 7596 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 7597 7598 /* reg_mcc_control_state 7599 * Current FSM state 7600 * Access: RO 7601 */ 7602 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 7603 7604 /* reg_mcc_component_size 7605 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 7606 * the size may shorten the update time. Value 0x0 means that size is 7607 * unspecified. 7608 * Access: WO 7609 */ 7610 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 7611 7612 static inline void mlxsw_reg_mcc_pack(char *payload, 7613 enum mlxsw_reg_mcc_instruction instr, 7614 u16 component_index, u32 update_handle, 7615 u32 component_size) 7616 { 7617 MLXSW_REG_ZERO(mcc, payload); 7618 mlxsw_reg_mcc_instruction_set(payload, instr); 7619 mlxsw_reg_mcc_component_index_set(payload, component_index); 7620 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 7621 mlxsw_reg_mcc_component_size_set(payload, component_size); 7622 } 7623 7624 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 7625 u8 *p_error_code, u8 *p_control_state) 7626 { 7627 if (p_update_handle) 7628 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 7629 if (p_error_code) 7630 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 7631 if (p_control_state) 7632 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 7633 } 7634 7635 /* MCDA - Management Component Data Access 7636 * --------------------------------------- 7637 * This register allows reading and writing a firmware component. 7638 */ 7639 #define MLXSW_REG_MCDA_ID 0x9063 7640 #define MLXSW_REG_MCDA_BASE_LEN 0x10 7641 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 7642 #define MLXSW_REG_MCDA_LEN \ 7643 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 7644 7645 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 7646 7647 /* reg_mcda_update_handle 7648 * Token representing the current flow executed by the FSM. 7649 * Access: RW 7650 */ 7651 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 7652 7653 /* reg_mcda_offset 7654 * Offset of accessed address relative to component start. Accesses must be in 7655 * accordance to log_mcda_word_size in MCQI reg. 7656 * Access: RW 7657 */ 7658 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 7659 7660 /* reg_mcda_size 7661 * Size of the data accessed, given in bytes. 7662 * Access: RW 7663 */ 7664 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 7665 7666 /* reg_mcda_data 7667 * Data block accessed. 7668 * Access: RW 7669 */ 7670 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 7671 7672 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 7673 u32 offset, u16 size, u8 *data) 7674 { 7675 int i; 7676 7677 MLXSW_REG_ZERO(mcda, payload); 7678 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 7679 mlxsw_reg_mcda_offset_set(payload, offset); 7680 mlxsw_reg_mcda_size_set(payload, size); 7681 7682 for (i = 0; i < size / 4; i++) 7683 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 7684 } 7685 7686 /* MPSC - Monitoring Packet Sampling Configuration Register 7687 * -------------------------------------------------------- 7688 * MPSC Register is used to configure the Packet Sampling mechanism. 7689 */ 7690 #define MLXSW_REG_MPSC_ID 0x9080 7691 #define MLXSW_REG_MPSC_LEN 0x1C 7692 7693 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 7694 7695 /* reg_mpsc_local_port 7696 * Local port number 7697 * Not supported for CPU port 7698 * Access: Index 7699 */ 7700 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 7701 7702 /* reg_mpsc_e 7703 * Enable sampling on port local_port 7704 * Access: RW 7705 */ 7706 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 7707 7708 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 7709 7710 /* reg_mpsc_rate 7711 * Sampling rate = 1 out of rate packets (with randomization around 7712 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 7713 * Access: RW 7714 */ 7715 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 7716 7717 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 7718 u32 rate) 7719 { 7720 MLXSW_REG_ZERO(mpsc, payload); 7721 mlxsw_reg_mpsc_local_port_set(payload, local_port); 7722 mlxsw_reg_mpsc_e_set(payload, e); 7723 mlxsw_reg_mpsc_rate_set(payload, rate); 7724 } 7725 7726 /* MGPC - Monitoring General Purpose Counter Set Register 7727 * The MGPC register retrieves and sets the General Purpose Counter Set. 7728 */ 7729 #define MLXSW_REG_MGPC_ID 0x9081 7730 #define MLXSW_REG_MGPC_LEN 0x18 7731 7732 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 7733 7734 /* reg_mgpc_counter_set_type 7735 * Counter set type. 7736 * Access: OP 7737 */ 7738 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 7739 7740 /* reg_mgpc_counter_index 7741 * Counter index. 7742 * Access: Index 7743 */ 7744 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 7745 7746 enum mlxsw_reg_mgpc_opcode { 7747 /* Nop */ 7748 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 7749 /* Clear counters */ 7750 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 7751 }; 7752 7753 /* reg_mgpc_opcode 7754 * Opcode. 7755 * Access: OP 7756 */ 7757 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 7758 7759 /* reg_mgpc_byte_counter 7760 * Byte counter value. 7761 * Access: RW 7762 */ 7763 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 7764 7765 /* reg_mgpc_packet_counter 7766 * Packet counter value. 7767 * Access: RW 7768 */ 7769 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 7770 7771 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 7772 enum mlxsw_reg_mgpc_opcode opcode, 7773 enum mlxsw_reg_flow_counter_set_type set_type) 7774 { 7775 MLXSW_REG_ZERO(mgpc, payload); 7776 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 7777 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 7778 mlxsw_reg_mgpc_opcode_set(payload, opcode); 7779 } 7780 7781 /* TIGCR - Tunneling IPinIP General Configuration Register 7782 * ------------------------------------------------------- 7783 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 7784 */ 7785 #define MLXSW_REG_TIGCR_ID 0xA801 7786 #define MLXSW_REG_TIGCR_LEN 0x10 7787 7788 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 7789 7790 /* reg_tigcr_ipip_ttlc 7791 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 7792 * header. 7793 * Access: RW 7794 */ 7795 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 7796 7797 /* reg_tigcr_ipip_ttl_uc 7798 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 7799 * reg_tigcr_ipip_ttlc is unset. 7800 * Access: RW 7801 */ 7802 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 7803 7804 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 7805 { 7806 MLXSW_REG_ZERO(tigcr, payload); 7807 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 7808 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 7809 } 7810 7811 /* SBPR - Shared Buffer Pools Register 7812 * ----------------------------------- 7813 * The SBPR configures and retrieves the shared buffer pools and configuration. 7814 */ 7815 #define MLXSW_REG_SBPR_ID 0xB001 7816 #define MLXSW_REG_SBPR_LEN 0x14 7817 7818 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 7819 7820 /* shared direstion enum for SBPR, SBCM, SBPM */ 7821 enum mlxsw_reg_sbxx_dir { 7822 MLXSW_REG_SBXX_DIR_INGRESS, 7823 MLXSW_REG_SBXX_DIR_EGRESS, 7824 }; 7825 7826 /* reg_sbpr_dir 7827 * Direction. 7828 * Access: Index 7829 */ 7830 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 7831 7832 /* reg_sbpr_pool 7833 * Pool index. 7834 * Access: Index 7835 */ 7836 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 7837 7838 /* reg_sbpr_size 7839 * Pool size in buffer cells. 7840 * Access: RW 7841 */ 7842 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 7843 7844 enum mlxsw_reg_sbpr_mode { 7845 MLXSW_REG_SBPR_MODE_STATIC, 7846 MLXSW_REG_SBPR_MODE_DYNAMIC, 7847 }; 7848 7849 /* reg_sbpr_mode 7850 * Pool quota calculation mode. 7851 * Access: RW 7852 */ 7853 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 7854 7855 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 7856 enum mlxsw_reg_sbxx_dir dir, 7857 enum mlxsw_reg_sbpr_mode mode, u32 size) 7858 { 7859 MLXSW_REG_ZERO(sbpr, payload); 7860 mlxsw_reg_sbpr_pool_set(payload, pool); 7861 mlxsw_reg_sbpr_dir_set(payload, dir); 7862 mlxsw_reg_sbpr_mode_set(payload, mode); 7863 mlxsw_reg_sbpr_size_set(payload, size); 7864 } 7865 7866 /* SBCM - Shared Buffer Class Management Register 7867 * ---------------------------------------------- 7868 * The SBCM register configures and retrieves the shared buffer allocation 7869 * and configuration according to Port-PG, including the binding to pool 7870 * and definition of the associated quota. 7871 */ 7872 #define MLXSW_REG_SBCM_ID 0xB002 7873 #define MLXSW_REG_SBCM_LEN 0x28 7874 7875 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 7876 7877 /* reg_sbcm_local_port 7878 * Local port number. 7879 * For Ingress: excludes CPU port and Router port 7880 * For Egress: excludes IP Router 7881 * Access: Index 7882 */ 7883 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 7884 7885 /* reg_sbcm_pg_buff 7886 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 7887 * For PG buffer: range is 0..cap_max_pg_buffers - 1 7888 * For traffic class: range is 0..cap_max_tclass - 1 7889 * Note that when traffic class is in MC aware mode then the traffic 7890 * classes which are MC aware cannot be configured. 7891 * Access: Index 7892 */ 7893 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 7894 7895 /* reg_sbcm_dir 7896 * Direction. 7897 * Access: Index 7898 */ 7899 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 7900 7901 /* reg_sbcm_min_buff 7902 * Minimum buffer size for the limiter, in cells. 7903 * Access: RW 7904 */ 7905 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 7906 7907 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 7908 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 7909 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 7910 7911 /* reg_sbcm_max_buff 7912 * When the pool associated to the port-pg/tclass is configured to 7913 * static, Maximum buffer size for the limiter configured in cells. 7914 * When the pool associated to the port-pg/tclass is configured to 7915 * dynamic, the max_buff holds the "alpha" parameter, supporting 7916 * the following values: 7917 * 0: 0 7918 * i: (1/128)*2^(i-1), for i=1..14 7919 * 0xFF: Infinity 7920 * Access: RW 7921 */ 7922 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 7923 7924 /* reg_sbcm_pool 7925 * Association of the port-priority to a pool. 7926 * Access: RW 7927 */ 7928 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 7929 7930 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 7931 enum mlxsw_reg_sbxx_dir dir, 7932 u32 min_buff, u32 max_buff, u8 pool) 7933 { 7934 MLXSW_REG_ZERO(sbcm, payload); 7935 mlxsw_reg_sbcm_local_port_set(payload, local_port); 7936 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 7937 mlxsw_reg_sbcm_dir_set(payload, dir); 7938 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 7939 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 7940 mlxsw_reg_sbcm_pool_set(payload, pool); 7941 } 7942 7943 /* SBPM - Shared Buffer Port Management Register 7944 * --------------------------------------------- 7945 * The SBPM register configures and retrieves the shared buffer allocation 7946 * and configuration according to Port-Pool, including the definition 7947 * of the associated quota. 7948 */ 7949 #define MLXSW_REG_SBPM_ID 0xB003 7950 #define MLXSW_REG_SBPM_LEN 0x28 7951 7952 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 7953 7954 /* reg_sbpm_local_port 7955 * Local port number. 7956 * For Ingress: excludes CPU port and Router port 7957 * For Egress: excludes IP Router 7958 * Access: Index 7959 */ 7960 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 7961 7962 /* reg_sbpm_pool 7963 * The pool associated to quota counting on the local_port. 7964 * Access: Index 7965 */ 7966 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 7967 7968 /* reg_sbpm_dir 7969 * Direction. 7970 * Access: Index 7971 */ 7972 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 7973 7974 /* reg_sbpm_buff_occupancy 7975 * Current buffer occupancy in cells. 7976 * Access: RO 7977 */ 7978 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 7979 7980 /* reg_sbpm_clr 7981 * Clear Max Buffer Occupancy 7982 * When this bit is set, max_buff_occupancy field is cleared (and a 7983 * new max value is tracked from the time the clear was performed). 7984 * Access: OP 7985 */ 7986 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 7987 7988 /* reg_sbpm_max_buff_occupancy 7989 * Maximum value of buffer occupancy in cells monitored. Cleared by 7990 * writing to the clr field. 7991 * Access: RO 7992 */ 7993 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 7994 7995 /* reg_sbpm_min_buff 7996 * Minimum buffer size for the limiter, in cells. 7997 * Access: RW 7998 */ 7999 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 8000 8001 /* reg_sbpm_max_buff 8002 * When the pool associated to the port-pg/tclass is configured to 8003 * static, Maximum buffer size for the limiter configured in cells. 8004 * When the pool associated to the port-pg/tclass is configured to 8005 * dynamic, the max_buff holds the "alpha" parameter, supporting 8006 * the following values: 8007 * 0: 0 8008 * i: (1/128)*2^(i-1), for i=1..14 8009 * 0xFF: Infinity 8010 * Access: RW 8011 */ 8012 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 8013 8014 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 8015 enum mlxsw_reg_sbxx_dir dir, bool clr, 8016 u32 min_buff, u32 max_buff) 8017 { 8018 MLXSW_REG_ZERO(sbpm, payload); 8019 mlxsw_reg_sbpm_local_port_set(payload, local_port); 8020 mlxsw_reg_sbpm_pool_set(payload, pool); 8021 mlxsw_reg_sbpm_dir_set(payload, dir); 8022 mlxsw_reg_sbpm_clr_set(payload, clr); 8023 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 8024 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 8025 } 8026 8027 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 8028 u32 *p_max_buff_occupancy) 8029 { 8030 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 8031 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 8032 } 8033 8034 /* SBMM - Shared Buffer Multicast Management Register 8035 * -------------------------------------------------- 8036 * The SBMM register configures and retrieves the shared buffer allocation 8037 * and configuration for MC packets according to Switch-Priority, including 8038 * the binding to pool and definition of the associated quota. 8039 */ 8040 #define MLXSW_REG_SBMM_ID 0xB004 8041 #define MLXSW_REG_SBMM_LEN 0x28 8042 8043 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 8044 8045 /* reg_sbmm_prio 8046 * Switch Priority. 8047 * Access: Index 8048 */ 8049 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 8050 8051 /* reg_sbmm_min_buff 8052 * Minimum buffer size for the limiter, in cells. 8053 * Access: RW 8054 */ 8055 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 8056 8057 /* reg_sbmm_max_buff 8058 * When the pool associated to the port-pg/tclass is configured to 8059 * static, Maximum buffer size for the limiter configured in cells. 8060 * When the pool associated to the port-pg/tclass is configured to 8061 * dynamic, the max_buff holds the "alpha" parameter, supporting 8062 * the following values: 8063 * 0: 0 8064 * i: (1/128)*2^(i-1), for i=1..14 8065 * 0xFF: Infinity 8066 * Access: RW 8067 */ 8068 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 8069 8070 /* reg_sbmm_pool 8071 * Association of the port-priority to a pool. 8072 * Access: RW 8073 */ 8074 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 8075 8076 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 8077 u32 max_buff, u8 pool) 8078 { 8079 MLXSW_REG_ZERO(sbmm, payload); 8080 mlxsw_reg_sbmm_prio_set(payload, prio); 8081 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 8082 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 8083 mlxsw_reg_sbmm_pool_set(payload, pool); 8084 } 8085 8086 /* SBSR - Shared Buffer Status Register 8087 * ------------------------------------ 8088 * The SBSR register retrieves the shared buffer occupancy according to 8089 * Port-Pool. Note that this register enables reading a large amount of data. 8090 * It is the user's responsibility to limit the amount of data to ensure the 8091 * response can match the maximum transfer unit. In case the response exceeds 8092 * the maximum transport unit, it will be truncated with no special notice. 8093 */ 8094 #define MLXSW_REG_SBSR_ID 0xB005 8095 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 8096 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 8097 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 8098 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 8099 MLXSW_REG_SBSR_REC_LEN * \ 8100 MLXSW_REG_SBSR_REC_MAX_COUNT) 8101 8102 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 8103 8104 /* reg_sbsr_clr 8105 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 8106 * field is cleared (and a new max value is tracked from the time the clear 8107 * was performed). 8108 * Access: OP 8109 */ 8110 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 8111 8112 /* reg_sbsr_ingress_port_mask 8113 * Bit vector for all ingress network ports. 8114 * Indicates which of the ports (for which the relevant bit is set) 8115 * are affected by the set operation. Configuration of any other port 8116 * does not change. 8117 * Access: Index 8118 */ 8119 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 8120 8121 /* reg_sbsr_pg_buff_mask 8122 * Bit vector for all switch priority groups. 8123 * Indicates which of the priorities (for which the relevant bit is set) 8124 * are affected by the set operation. Configuration of any other priority 8125 * does not change. 8126 * Range is 0..cap_max_pg_buffers - 1 8127 * Access: Index 8128 */ 8129 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 8130 8131 /* reg_sbsr_egress_port_mask 8132 * Bit vector for all egress network ports. 8133 * Indicates which of the ports (for which the relevant bit is set) 8134 * are affected by the set operation. Configuration of any other port 8135 * does not change. 8136 * Access: Index 8137 */ 8138 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 8139 8140 /* reg_sbsr_tclass_mask 8141 * Bit vector for all traffic classes. 8142 * Indicates which of the traffic classes (for which the relevant bit is 8143 * set) are affected by the set operation. Configuration of any other 8144 * traffic class does not change. 8145 * Range is 0..cap_max_tclass - 1 8146 * Access: Index 8147 */ 8148 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 8149 8150 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 8151 { 8152 MLXSW_REG_ZERO(sbsr, payload); 8153 mlxsw_reg_sbsr_clr_set(payload, clr); 8154 } 8155 8156 /* reg_sbsr_rec_buff_occupancy 8157 * Current buffer occupancy in cells. 8158 * Access: RO 8159 */ 8160 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 8161 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 8162 8163 /* reg_sbsr_rec_max_buff_occupancy 8164 * Maximum value of buffer occupancy in cells monitored. Cleared by 8165 * writing to the clr field. 8166 * Access: RO 8167 */ 8168 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 8169 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 8170 8171 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 8172 u32 *p_buff_occupancy, 8173 u32 *p_max_buff_occupancy) 8174 { 8175 *p_buff_occupancy = 8176 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 8177 *p_max_buff_occupancy = 8178 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 8179 } 8180 8181 /* SBIB - Shared Buffer Internal Buffer Register 8182 * --------------------------------------------- 8183 * The SBIB register configures per port buffers for internal use. The internal 8184 * buffers consume memory on the port buffers (note that the port buffers are 8185 * used also by PBMC). 8186 * 8187 * For Spectrum this is used for egress mirroring. 8188 */ 8189 #define MLXSW_REG_SBIB_ID 0xB006 8190 #define MLXSW_REG_SBIB_LEN 0x10 8191 8192 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 8193 8194 /* reg_sbib_local_port 8195 * Local port number 8196 * Not supported for CPU port and router port 8197 * Access: Index 8198 */ 8199 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 8200 8201 /* reg_sbib_buff_size 8202 * Units represented in cells 8203 * Allowed range is 0 to (cap_max_headroom_size - 1) 8204 * Default is 0 8205 * Access: RW 8206 */ 8207 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 8208 8209 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 8210 u32 buff_size) 8211 { 8212 MLXSW_REG_ZERO(sbib, payload); 8213 mlxsw_reg_sbib_local_port_set(payload, local_port); 8214 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 8215 } 8216 8217 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 8218 MLXSW_REG(sgcr), 8219 MLXSW_REG(spad), 8220 MLXSW_REG(smid), 8221 MLXSW_REG(sspr), 8222 MLXSW_REG(sfdat), 8223 MLXSW_REG(sfd), 8224 MLXSW_REG(sfn), 8225 MLXSW_REG(spms), 8226 MLXSW_REG(spvid), 8227 MLXSW_REG(spvm), 8228 MLXSW_REG(spaft), 8229 MLXSW_REG(sfgc), 8230 MLXSW_REG(sftr), 8231 MLXSW_REG(sfdf), 8232 MLXSW_REG(sldr), 8233 MLXSW_REG(slcr), 8234 MLXSW_REG(slcor), 8235 MLXSW_REG(spmlr), 8236 MLXSW_REG(svfa), 8237 MLXSW_REG(svpe), 8238 MLXSW_REG(sfmr), 8239 MLXSW_REG(spvmlr), 8240 MLXSW_REG(cwtp), 8241 MLXSW_REG(cwtpm), 8242 MLXSW_REG(pgcr), 8243 MLXSW_REG(ppbt), 8244 MLXSW_REG(pacl), 8245 MLXSW_REG(pagt), 8246 MLXSW_REG(ptar), 8247 MLXSW_REG(ppbs), 8248 MLXSW_REG(prcr), 8249 MLXSW_REG(pefa), 8250 MLXSW_REG(ptce2), 8251 MLXSW_REG(perar), 8252 MLXSW_REG(percr), 8253 MLXSW_REG(pererp), 8254 MLXSW_REG(iedr), 8255 MLXSW_REG(qpcr), 8256 MLXSW_REG(qtct), 8257 MLXSW_REG(qeec), 8258 MLXSW_REG(pmlp), 8259 MLXSW_REG(pmtu), 8260 MLXSW_REG(ptys), 8261 MLXSW_REG(ppad), 8262 MLXSW_REG(paos), 8263 MLXSW_REG(pfcc), 8264 MLXSW_REG(ppcnt), 8265 MLXSW_REG(plib), 8266 MLXSW_REG(pptb), 8267 MLXSW_REG(pbmc), 8268 MLXSW_REG(pspa), 8269 MLXSW_REG(htgt), 8270 MLXSW_REG(hpkt), 8271 MLXSW_REG(rgcr), 8272 MLXSW_REG(ritr), 8273 MLXSW_REG(rtar), 8274 MLXSW_REG(ratr), 8275 MLXSW_REG(rtdp), 8276 MLXSW_REG(rdpm), 8277 MLXSW_REG(ricnt), 8278 MLXSW_REG(rrcr), 8279 MLXSW_REG(ralta), 8280 MLXSW_REG(ralst), 8281 MLXSW_REG(raltb), 8282 MLXSW_REG(ralue), 8283 MLXSW_REG(rauht), 8284 MLXSW_REG(raleu), 8285 MLXSW_REG(rauhtd), 8286 MLXSW_REG(rigr2), 8287 MLXSW_REG(recr2), 8288 MLXSW_REG(rmft2), 8289 MLXSW_REG(mfcr), 8290 MLXSW_REG(mfsc), 8291 MLXSW_REG(mfsm), 8292 MLXSW_REG(mfsl), 8293 MLXSW_REG(mtcap), 8294 MLXSW_REG(mtmp), 8295 MLXSW_REG(mcia), 8296 MLXSW_REG(mpat), 8297 MLXSW_REG(mpar), 8298 MLXSW_REG(mrsr), 8299 MLXSW_REG(mlcr), 8300 MLXSW_REG(mpsc), 8301 MLXSW_REG(mcqi), 8302 MLXSW_REG(mcc), 8303 MLXSW_REG(mcda), 8304 MLXSW_REG(mgpc), 8305 MLXSW_REG(tigcr), 8306 MLXSW_REG(sbpr), 8307 MLXSW_REG(sbcm), 8308 MLXSW_REG(sbpm), 8309 MLXSW_REG(sbmm), 8310 MLXSW_REG(sbsr), 8311 MLXSW_REG(sbib), 8312 }; 8313 8314 static inline const char *mlxsw_reg_id_str(u16 reg_id) 8315 { 8316 const struct mlxsw_reg_info *reg_info; 8317 int i; 8318 8319 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 8320 reg_info = mlxsw_reg_infos[i]; 8321 if (reg_info->id == reg_id) 8322 return reg_info->name; 8323 } 8324 return "*UNKNOWN*"; 8325 } 8326 8327 /* PUDE - Port Up / Down Event 8328 * --------------------------- 8329 * Reports the operational state change of a port. 8330 */ 8331 #define MLXSW_REG_PUDE_LEN 0x10 8332 8333 /* reg_pude_swid 8334 * Switch partition ID with which to associate the port. 8335 * Access: Index 8336 */ 8337 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 8338 8339 /* reg_pude_local_port 8340 * Local port number. 8341 * Access: Index 8342 */ 8343 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 8344 8345 /* reg_pude_admin_status 8346 * Port administrative state (the desired state). 8347 * 1 - Up. 8348 * 2 - Down. 8349 * 3 - Up once. This means that in case of link failure, the port won't go 8350 * into polling mode, but will wait to be re-enabled by software. 8351 * 4 - Disabled by system. Can only be set by hardware. 8352 * Access: RO 8353 */ 8354 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 8355 8356 /* reg_pude_oper_status 8357 * Port operatioanl state. 8358 * 1 - Up. 8359 * 2 - Down. 8360 * 3 - Down by port failure. This means that the device will not let the 8361 * port up again until explicitly specified by software. 8362 * Access: RO 8363 */ 8364 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 8365 8366 #endif 8367