1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com> 8 * Copyright (c) 2017-2018 Petr Machata <petrm@mellanox.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the names of the copyright holders nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MLXSW_REG_H 40 #define _MLXSW_REG_H 41 42 #include <linux/string.h> 43 #include <linux/bitops.h> 44 #include <linux/if_vlan.h> 45 46 #include "item.h" 47 #include "port.h" 48 49 struct mlxsw_reg_info { 50 u16 id; 51 u16 len; /* In u8 */ 52 const char *name; 53 }; 54 55 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 56 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 57 .id = _id, \ 58 .len = _len, \ 59 .name = #_name, \ 60 } 61 62 #define MLXSW_REG(type) (&mlxsw_reg_##type) 63 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 64 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 65 66 /* SGCR - Switch General Configuration Register 67 * -------------------------------------------- 68 * This register is used for configuration of the switch capabilities. 69 */ 70 #define MLXSW_REG_SGCR_ID 0x2000 71 #define MLXSW_REG_SGCR_LEN 0x10 72 73 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 74 75 /* reg_sgcr_llb 76 * Link Local Broadcast (Default=0) 77 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 78 * packets and ignore the IGMP snooping entries. 79 * Access: RW 80 */ 81 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 82 83 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 84 { 85 MLXSW_REG_ZERO(sgcr, payload); 86 mlxsw_reg_sgcr_llb_set(payload, !!llb); 87 } 88 89 /* SPAD - Switch Physical Address Register 90 * --------------------------------------- 91 * The SPAD register configures the switch physical MAC address. 92 */ 93 #define MLXSW_REG_SPAD_ID 0x2002 94 #define MLXSW_REG_SPAD_LEN 0x10 95 96 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 97 98 /* reg_spad_base_mac 99 * Base MAC address for the switch partitions. 100 * Per switch partition MAC address is equal to: 101 * base_mac + swid 102 * Access: RW 103 */ 104 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 105 106 /* SMID - Switch Multicast ID 107 * -------------------------- 108 * The MID record maps from a MID (Multicast ID), which is a unique identifier 109 * of the multicast group within the stacking domain, into a list of local 110 * ports into which the packet is replicated. 111 */ 112 #define MLXSW_REG_SMID_ID 0x2007 113 #define MLXSW_REG_SMID_LEN 0x240 114 115 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 116 117 /* reg_smid_swid 118 * Switch partition ID. 119 * Access: Index 120 */ 121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 122 123 /* reg_smid_mid 124 * Multicast identifier - global identifier that represents the multicast group 125 * across all devices. 126 * Access: Index 127 */ 128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 129 130 /* reg_smid_port 131 * Local port memebership (1 bit per port). 132 * Access: RW 133 */ 134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 135 136 /* reg_smid_port_mask 137 * Local port mask (1 bit per port). 138 * Access: W 139 */ 140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 141 142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 143 u8 port, bool set) 144 { 145 MLXSW_REG_ZERO(smid, payload); 146 mlxsw_reg_smid_swid_set(payload, 0); 147 mlxsw_reg_smid_mid_set(payload, mid); 148 mlxsw_reg_smid_port_set(payload, port, set); 149 mlxsw_reg_smid_port_mask_set(payload, port, 1); 150 } 151 152 /* SSPR - Switch System Port Record Register 153 * ----------------------------------------- 154 * Configures the system port to local port mapping. 155 */ 156 #define MLXSW_REG_SSPR_ID 0x2008 157 #define MLXSW_REG_SSPR_LEN 0x8 158 159 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 160 161 /* reg_sspr_m 162 * Master - if set, then the record describes the master system port. 163 * This is needed in case a local port is mapped into several system ports 164 * (for multipathing). That number will be reported as the source system 165 * port when packets are forwarded to the CPU. Only one master port is allowed 166 * per local port. 167 * 168 * Note: Must be set for Spectrum. 169 * Access: RW 170 */ 171 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 172 173 /* reg_sspr_local_port 174 * Local port number. 175 * 176 * Access: RW 177 */ 178 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 179 180 /* reg_sspr_sub_port 181 * Virtual port within the physical port. 182 * Should be set to 0 when virtual ports are not enabled on the port. 183 * 184 * Access: RW 185 */ 186 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 187 188 /* reg_sspr_system_port 189 * Unique identifier within the stacking domain that represents all the ports 190 * that are available in the system (external ports). 191 * 192 * Currently, only single-ASIC configurations are supported, so we default to 193 * 1:1 mapping between system ports and local ports. 194 * Access: Index 195 */ 196 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 197 198 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 199 { 200 MLXSW_REG_ZERO(sspr, payload); 201 mlxsw_reg_sspr_m_set(payload, 1); 202 mlxsw_reg_sspr_local_port_set(payload, local_port); 203 mlxsw_reg_sspr_sub_port_set(payload, 0); 204 mlxsw_reg_sspr_system_port_set(payload, local_port); 205 } 206 207 /* SFDAT - Switch Filtering Database Aging Time 208 * -------------------------------------------- 209 * Controls the Switch aging time. Aging time is able to be set per Switch 210 * Partition. 211 */ 212 #define MLXSW_REG_SFDAT_ID 0x2009 213 #define MLXSW_REG_SFDAT_LEN 0x8 214 215 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 216 217 /* reg_sfdat_swid 218 * Switch partition ID. 219 * Access: Index 220 */ 221 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 222 223 /* reg_sfdat_age_time 224 * Aging time in seconds 225 * Min - 10 seconds 226 * Max - 1,000,000 seconds 227 * Default is 300 seconds. 228 * Access: RW 229 */ 230 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 231 232 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 233 { 234 MLXSW_REG_ZERO(sfdat, payload); 235 mlxsw_reg_sfdat_swid_set(payload, 0); 236 mlxsw_reg_sfdat_age_time_set(payload, age_time); 237 } 238 239 /* SFD - Switch Filtering Database 240 * ------------------------------- 241 * The following register defines the access to the filtering database. 242 * The register supports querying, adding, removing and modifying the database. 243 * The access is optimized for bulk updates in which case more than one 244 * FDB record is present in the same command. 245 */ 246 #define MLXSW_REG_SFD_ID 0x200A 247 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 248 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 249 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 250 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 251 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 252 253 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 254 255 /* reg_sfd_swid 256 * Switch partition ID for queries. Reserved on Write. 257 * Access: Index 258 */ 259 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 260 261 enum mlxsw_reg_sfd_op { 262 /* Dump entire FDB a (process according to record_locator) */ 263 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 264 /* Query records by {MAC, VID/FID} value */ 265 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 266 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 267 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 268 /* Test. Response indicates if each of the records could be 269 * added to the FDB. 270 */ 271 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 272 /* Add/modify. Aged-out records cannot be added. This command removes 273 * the learning notification of the {MAC, VID/FID}. Response includes 274 * the entries that were added to the FDB. 275 */ 276 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 277 /* Remove record by {MAC, VID/FID}. This command also removes 278 * the learning notification and aged-out notifications 279 * of the {MAC, VID/FID}. The response provides current (pre-removal) 280 * entries as non-aged-out. 281 */ 282 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 283 /* Remove learned notification by {MAC, VID/FID}. The response provides 284 * the removed learning notification. 285 */ 286 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 287 }; 288 289 /* reg_sfd_op 290 * Operation. 291 * Access: OP 292 */ 293 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 294 295 /* reg_sfd_record_locator 296 * Used for querying the FDB. Use record_locator=0 to initiate the 297 * query. When a record is returned, a new record_locator is 298 * returned to be used in the subsequent query. 299 * Reserved for database update. 300 * Access: Index 301 */ 302 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 303 304 /* reg_sfd_num_rec 305 * Request: Number of records to read/add/modify/remove 306 * Response: Number of records read/added/replaced/removed 307 * See above description for more details. 308 * Ranges 0..64 309 * Access: RW 310 */ 311 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 312 313 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 314 u32 record_locator) 315 { 316 MLXSW_REG_ZERO(sfd, payload); 317 mlxsw_reg_sfd_op_set(payload, op); 318 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 319 } 320 321 /* reg_sfd_rec_swid 322 * Switch partition ID. 323 * Access: Index 324 */ 325 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 326 MLXSW_REG_SFD_REC_LEN, 0x00, false); 327 328 enum mlxsw_reg_sfd_rec_type { 329 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 330 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 331 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 332 }; 333 334 /* reg_sfd_rec_type 335 * FDB record type. 336 * Access: RW 337 */ 338 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 339 MLXSW_REG_SFD_REC_LEN, 0x00, false); 340 341 enum mlxsw_reg_sfd_rec_policy { 342 /* Replacement disabled, aging disabled. */ 343 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 344 /* (mlag remote): Replacement enabled, aging disabled, 345 * learning notification enabled on this port. 346 */ 347 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 348 /* (ingress device): Replacement enabled, aging enabled. */ 349 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 350 }; 351 352 /* reg_sfd_rec_policy 353 * Policy. 354 * Access: RW 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 357 MLXSW_REG_SFD_REC_LEN, 0x00, false); 358 359 /* reg_sfd_rec_a 360 * Activity. Set for new static entries. Set for static entries if a frame SMAC 361 * lookup hits on the entry. 362 * To clear the a bit, use "query and clear activity" op. 363 * Access: RO 364 */ 365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 366 MLXSW_REG_SFD_REC_LEN, 0x00, false); 367 368 /* reg_sfd_rec_mac 369 * MAC address. 370 * Access: Index 371 */ 372 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 373 MLXSW_REG_SFD_REC_LEN, 0x02); 374 375 enum mlxsw_reg_sfd_rec_action { 376 /* forward */ 377 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 378 /* forward and trap, trap_id is FDB_TRAP */ 379 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 380 /* trap and do not forward, trap_id is FDB_TRAP */ 381 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 382 /* forward to IP router */ 383 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 384 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 385 }; 386 387 /* reg_sfd_rec_action 388 * Action to apply on the packet. 389 * Note: Dynamic entries can only be configured with NOP action. 390 * Access: RW 391 */ 392 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 393 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 394 395 /* reg_sfd_uc_sub_port 396 * VEPA channel on local port. 397 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 398 * VEPA is not enabled. 399 * Access: RW 400 */ 401 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 402 MLXSW_REG_SFD_REC_LEN, 0x08, false); 403 404 /* reg_sfd_uc_fid_vid 405 * Filtering ID or VLAN ID 406 * For SwitchX and SwitchX-2: 407 * - Dynamic entries (policy 2,3) use FID 408 * - Static entries (policy 0) use VID 409 * - When independent learning is configured, VID=FID 410 * For Spectrum: use FID for both Dynamic and Static entries. 411 * VID should not be used. 412 * Access: Index 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_system_port 418 * Unique port identifier for the final destination of the packet. 419 * Access: RW 420 */ 421 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 422 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 423 424 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 425 enum mlxsw_reg_sfd_rec_type rec_type, 426 const char *mac, 427 enum mlxsw_reg_sfd_rec_action action) 428 { 429 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 430 431 if (rec_index >= num_rec) 432 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 433 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 434 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 435 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 436 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 437 } 438 439 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 440 enum mlxsw_reg_sfd_rec_policy policy, 441 const char *mac, u16 fid_vid, 442 enum mlxsw_reg_sfd_rec_action action, 443 u8 local_port) 444 { 445 mlxsw_reg_sfd_rec_pack(payload, rec_index, 446 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 448 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 449 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 450 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 451 } 452 453 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 454 char *mac, u16 *p_fid_vid, 455 u8 *p_local_port) 456 { 457 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 458 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 459 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 460 } 461 462 /* reg_sfd_uc_lag_sub_port 463 * LAG sub port. 464 * Must be 0 if multichannel VEPA is not enabled. 465 * Access: RW 466 */ 467 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 468 MLXSW_REG_SFD_REC_LEN, 0x08, false); 469 470 /* reg_sfd_uc_lag_fid_vid 471 * Filtering ID or VLAN ID 472 * For SwitchX and SwitchX-2: 473 * - Dynamic entries (policy 2,3) use FID 474 * - Static entries (policy 0) use VID 475 * - When independent learning is configured, VID=FID 476 * For Spectrum: use FID for both Dynamic and Static entries. 477 * VID should not be used. 478 * Access: Index 479 */ 480 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 481 MLXSW_REG_SFD_REC_LEN, 0x08, false); 482 483 /* reg_sfd_uc_lag_lag_vid 484 * Indicates VID in case of vFIDs. Reserved for FIDs. 485 * Access: RW 486 */ 487 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 488 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 489 490 /* reg_sfd_uc_lag_lag_id 491 * LAG Identifier - pointer into the LAG descriptor table. 492 * Access: RW 493 */ 494 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 495 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 496 497 static inline void 498 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 499 enum mlxsw_reg_sfd_rec_policy policy, 500 const char *mac, u16 fid_vid, 501 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 502 u16 lag_id) 503 { 504 mlxsw_reg_sfd_rec_pack(payload, rec_index, 505 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 506 mac, action); 507 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 508 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 509 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 510 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 511 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 512 } 513 514 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 515 char *mac, u16 *p_vid, 516 u16 *p_lag_id) 517 { 518 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 519 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 520 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 521 } 522 523 /* reg_sfd_mc_pgi 524 * 525 * Multicast port group index - index into the port group table. 526 * Value 0x1FFF indicates the pgi should point to the MID entry. 527 * For Spectrum this value must be set to 0x1FFF 528 * Access: RW 529 */ 530 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 531 MLXSW_REG_SFD_REC_LEN, 0x08, false); 532 533 /* reg_sfd_mc_fid_vid 534 * 535 * Filtering ID or VLAN ID 536 * Access: Index 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 539 MLXSW_REG_SFD_REC_LEN, 0x08, false); 540 541 /* reg_sfd_mc_mid 542 * 543 * Multicast identifier - global identifier that represents the multicast 544 * group across all devices. 545 * Access: RW 546 */ 547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 548 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 549 550 static inline void 551 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 552 const char *mac, u16 fid_vid, 553 enum mlxsw_reg_sfd_rec_action action, u16 mid) 554 { 555 mlxsw_reg_sfd_rec_pack(payload, rec_index, 556 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 557 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 558 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 559 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 560 } 561 562 /* SFN - Switch FDB Notification Register 563 * ------------------------------------------- 564 * The switch provides notifications on newly learned FDB entries and 565 * aged out entries. The notifications can be polled by software. 566 */ 567 #define MLXSW_REG_SFN_ID 0x200B 568 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 569 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 570 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 571 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 572 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 573 574 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 575 576 /* reg_sfn_swid 577 * Switch partition ID. 578 * Access: Index 579 */ 580 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 581 582 /* reg_sfn_end 583 * Forces the current session to end. 584 * Access: OP 585 */ 586 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 587 588 /* reg_sfn_num_rec 589 * Request: Number of learned notifications and aged-out notification 590 * records requested. 591 * Response: Number of notification records returned (must be smaller 592 * than or equal to the value requested) 593 * Ranges 0..64 594 * Access: OP 595 */ 596 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 597 598 static inline void mlxsw_reg_sfn_pack(char *payload) 599 { 600 MLXSW_REG_ZERO(sfn, payload); 601 mlxsw_reg_sfn_swid_set(payload, 0); 602 mlxsw_reg_sfn_end_set(payload, 1); 603 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 604 } 605 606 /* reg_sfn_rec_swid 607 * Switch partition ID. 608 * Access: RO 609 */ 610 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 611 MLXSW_REG_SFN_REC_LEN, 0x00, false); 612 613 enum mlxsw_reg_sfn_rec_type { 614 /* MAC addresses learned on a regular port. */ 615 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 616 /* MAC addresses learned on a LAG port. */ 617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 618 /* Aged-out MAC address on a regular port. */ 619 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 620 /* Aged-out MAC address on a LAG port. */ 621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 622 }; 623 624 /* reg_sfn_rec_type 625 * Notification record type. 626 * Access: RO 627 */ 628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 629 MLXSW_REG_SFN_REC_LEN, 0x00, false); 630 631 /* reg_sfn_rec_mac 632 * MAC address. 633 * Access: RO 634 */ 635 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 636 MLXSW_REG_SFN_REC_LEN, 0x02); 637 638 /* reg_sfn_mac_sub_port 639 * VEPA channel on the local port. 640 * 0 if multichannel VEPA is not enabled. 641 * Access: RO 642 */ 643 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 644 MLXSW_REG_SFN_REC_LEN, 0x08, false); 645 646 /* reg_sfn_mac_fid 647 * Filtering identifier. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 651 MLXSW_REG_SFN_REC_LEN, 0x08, false); 652 653 /* reg_sfn_mac_system_port 654 * Unique port identifier for the final destination of the packet. 655 * Access: RO 656 */ 657 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 658 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 659 660 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 661 char *mac, u16 *p_vid, 662 u8 *p_local_port) 663 { 664 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 665 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 666 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 667 } 668 669 /* reg_sfn_mac_lag_lag_id 670 * LAG ID (pointer into the LAG descriptor table). 671 * Access: RO 672 */ 673 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 674 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 675 676 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 677 char *mac, u16 *p_vid, 678 u16 *p_lag_id) 679 { 680 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 681 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 682 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 683 } 684 685 /* SPMS - Switch Port MSTP/RSTP State Register 686 * ------------------------------------------- 687 * Configures the spanning tree state of a physical port. 688 */ 689 #define MLXSW_REG_SPMS_ID 0x200D 690 #define MLXSW_REG_SPMS_LEN 0x404 691 692 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 693 694 /* reg_spms_local_port 695 * Local port number. 696 * Access: Index 697 */ 698 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 699 700 enum mlxsw_reg_spms_state { 701 MLXSW_REG_SPMS_STATE_NO_CHANGE, 702 MLXSW_REG_SPMS_STATE_DISCARDING, 703 MLXSW_REG_SPMS_STATE_LEARNING, 704 MLXSW_REG_SPMS_STATE_FORWARDING, 705 }; 706 707 /* reg_spms_state 708 * Spanning tree state of each VLAN ID (VID) of the local port. 709 * 0 - Do not change spanning tree state (used only when writing). 710 * 1 - Discarding. No learning or forwarding to/from this port (default). 711 * 2 - Learning. Port is learning, but not forwarding. 712 * 3 - Forwarding. Port is learning and forwarding. 713 * Access: RW 714 */ 715 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 716 717 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 718 { 719 MLXSW_REG_ZERO(spms, payload); 720 mlxsw_reg_spms_local_port_set(payload, local_port); 721 } 722 723 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 724 enum mlxsw_reg_spms_state state) 725 { 726 mlxsw_reg_spms_state_set(payload, vid, state); 727 } 728 729 /* SPVID - Switch Port VID 730 * ----------------------- 731 * The switch port VID configures the default VID for a port. 732 */ 733 #define MLXSW_REG_SPVID_ID 0x200E 734 #define MLXSW_REG_SPVID_LEN 0x08 735 736 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 737 738 /* reg_spvid_local_port 739 * Local port number. 740 * Access: Index 741 */ 742 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 743 744 /* reg_spvid_sub_port 745 * Virtual port within the physical port. 746 * Should be set to 0 when virtual ports are not enabled on the port. 747 * Access: Index 748 */ 749 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 750 751 /* reg_spvid_pvid 752 * Port default VID 753 * Access: RW 754 */ 755 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 756 757 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 758 { 759 MLXSW_REG_ZERO(spvid, payload); 760 mlxsw_reg_spvid_local_port_set(payload, local_port); 761 mlxsw_reg_spvid_pvid_set(payload, pvid); 762 } 763 764 /* SPVM - Switch Port VLAN Membership 765 * ---------------------------------- 766 * The Switch Port VLAN Membership register configures the VLAN membership 767 * of a port in a VLAN denoted by VID. VLAN membership is managed per 768 * virtual port. The register can be used to add and remove VID(s) from a port. 769 */ 770 #define MLXSW_REG_SPVM_ID 0x200F 771 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 772 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 773 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 774 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 775 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 776 777 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 778 779 /* reg_spvm_pt 780 * Priority tagged. If this bit is set, packets forwarded to the port with 781 * untagged VLAN membership (u bit is set) will be tagged with priority tag 782 * (VID=0) 783 * Access: RW 784 */ 785 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 786 787 /* reg_spvm_pte 788 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 789 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 790 * Access: WO 791 */ 792 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 793 794 /* reg_spvm_local_port 795 * Local port number. 796 * Access: Index 797 */ 798 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 799 800 /* reg_spvm_sub_port 801 * Virtual port within the physical port. 802 * Should be set to 0 when virtual ports are not enabled on the port. 803 * Access: Index 804 */ 805 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 806 807 /* reg_spvm_num_rec 808 * Number of records to update. Each record contains: i, e, u, vid. 809 * Access: OP 810 */ 811 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 812 813 /* reg_spvm_rec_i 814 * Ingress membership in VLAN ID. 815 * Access: Index 816 */ 817 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 818 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 819 MLXSW_REG_SPVM_REC_LEN, 0, false); 820 821 /* reg_spvm_rec_e 822 * Egress membership in VLAN ID. 823 * Access: Index 824 */ 825 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 826 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 827 MLXSW_REG_SPVM_REC_LEN, 0, false); 828 829 /* reg_spvm_rec_u 830 * Untagged - port is an untagged member - egress transmission uses untagged 831 * frames on VID<n> 832 * Access: Index 833 */ 834 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 835 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 836 MLXSW_REG_SPVM_REC_LEN, 0, false); 837 838 /* reg_spvm_rec_vid 839 * Egress membership in VLAN ID. 840 * Access: Index 841 */ 842 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 843 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 844 MLXSW_REG_SPVM_REC_LEN, 0, false); 845 846 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 847 u16 vid_begin, u16 vid_end, 848 bool is_member, bool untagged) 849 { 850 int size = vid_end - vid_begin + 1; 851 int i; 852 853 MLXSW_REG_ZERO(spvm, payload); 854 mlxsw_reg_spvm_local_port_set(payload, local_port); 855 mlxsw_reg_spvm_num_rec_set(payload, size); 856 857 for (i = 0; i < size; i++) { 858 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 859 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 860 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 861 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 862 } 863 } 864 865 /* SPAFT - Switch Port Acceptable Frame Types 866 * ------------------------------------------ 867 * The Switch Port Acceptable Frame Types register configures the frame 868 * admittance of the port. 869 */ 870 #define MLXSW_REG_SPAFT_ID 0x2010 871 #define MLXSW_REG_SPAFT_LEN 0x08 872 873 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 874 875 /* reg_spaft_local_port 876 * Local port number. 877 * Access: Index 878 * 879 * Note: CPU port is not supported (all tag types are allowed). 880 */ 881 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 882 883 /* reg_spaft_sub_port 884 * Virtual port within the physical port. 885 * Should be set to 0 when virtual ports are not enabled on the port. 886 * Access: RW 887 */ 888 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 889 890 /* reg_spaft_allow_untagged 891 * When set, untagged frames on the ingress are allowed (default). 892 * Access: RW 893 */ 894 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 895 896 /* reg_spaft_allow_prio_tagged 897 * When set, priority tagged frames on the ingress are allowed (default). 898 * Access: RW 899 */ 900 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 901 902 /* reg_spaft_allow_tagged 903 * When set, tagged frames on the ingress are allowed (default). 904 * Access: RW 905 */ 906 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 907 908 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 909 bool allow_untagged) 910 { 911 MLXSW_REG_ZERO(spaft, payload); 912 mlxsw_reg_spaft_local_port_set(payload, local_port); 913 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 914 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 915 mlxsw_reg_spaft_allow_tagged_set(payload, true); 916 } 917 918 /* SFGC - Switch Flooding Group Configuration 919 * ------------------------------------------ 920 * The following register controls the association of flooding tables and MIDs 921 * to packet types used for flooding. 922 */ 923 #define MLXSW_REG_SFGC_ID 0x2011 924 #define MLXSW_REG_SFGC_LEN 0x10 925 926 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 927 928 enum mlxsw_reg_sfgc_type { 929 MLXSW_REG_SFGC_TYPE_BROADCAST, 930 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 931 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 932 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 933 MLXSW_REG_SFGC_TYPE_RESERVED, 934 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 935 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 936 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 937 MLXSW_REG_SFGC_TYPE_MAX, 938 }; 939 940 /* reg_sfgc_type 941 * The traffic type to reach the flooding table. 942 * Access: Index 943 */ 944 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 945 946 enum mlxsw_reg_sfgc_bridge_type { 947 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 948 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 949 }; 950 951 /* reg_sfgc_bridge_type 952 * Access: Index 953 * 954 * Note: SwitchX-2 only supports 802.1Q mode. 955 */ 956 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 957 958 enum mlxsw_flood_table_type { 959 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 960 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 961 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 962 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 963 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 964 }; 965 966 /* reg_sfgc_table_type 967 * See mlxsw_flood_table_type 968 * Access: RW 969 * 970 * Note: FID offset and FID types are not supported in SwitchX-2. 971 */ 972 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 973 974 /* reg_sfgc_flood_table 975 * Flooding table index to associate with the specific type on the specific 976 * switch partition. 977 * Access: RW 978 */ 979 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 980 981 /* reg_sfgc_mid 982 * The multicast ID for the swid. Not supported for Spectrum 983 * Access: RW 984 */ 985 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 986 987 /* reg_sfgc_counter_set_type 988 * Counter Set Type for flow counters. 989 * Access: RW 990 */ 991 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 992 993 /* reg_sfgc_counter_index 994 * Counter Index for flow counters. 995 * Access: RW 996 */ 997 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 998 999 static inline void 1000 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1001 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1002 enum mlxsw_flood_table_type table_type, 1003 unsigned int flood_table) 1004 { 1005 MLXSW_REG_ZERO(sfgc, payload); 1006 mlxsw_reg_sfgc_type_set(payload, type); 1007 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1008 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1009 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1010 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1011 } 1012 1013 /* SFTR - Switch Flooding Table Register 1014 * ------------------------------------- 1015 * The switch flooding table is used for flooding packet replication. The table 1016 * defines a bit mask of ports for packet replication. 1017 */ 1018 #define MLXSW_REG_SFTR_ID 0x2012 1019 #define MLXSW_REG_SFTR_LEN 0x420 1020 1021 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1022 1023 /* reg_sftr_swid 1024 * Switch partition ID with which to associate the port. 1025 * Access: Index 1026 */ 1027 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1028 1029 /* reg_sftr_flood_table 1030 * Flooding table index to associate with the specific type on the specific 1031 * switch partition. 1032 * Access: Index 1033 */ 1034 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1035 1036 /* reg_sftr_index 1037 * Index. Used as an index into the Flooding Table in case the table is 1038 * configured to use VID / FID or FID Offset. 1039 * Access: Index 1040 */ 1041 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1042 1043 /* reg_sftr_table_type 1044 * See mlxsw_flood_table_type 1045 * Access: RW 1046 */ 1047 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1048 1049 /* reg_sftr_range 1050 * Range of entries to update 1051 * Access: Index 1052 */ 1053 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1054 1055 /* reg_sftr_port 1056 * Local port membership (1 bit per port). 1057 * Access: RW 1058 */ 1059 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1060 1061 /* reg_sftr_cpu_port_mask 1062 * CPU port mask (1 bit per port). 1063 * Access: W 1064 */ 1065 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1066 1067 static inline void mlxsw_reg_sftr_pack(char *payload, 1068 unsigned int flood_table, 1069 unsigned int index, 1070 enum mlxsw_flood_table_type table_type, 1071 unsigned int range, u8 port, bool set) 1072 { 1073 MLXSW_REG_ZERO(sftr, payload); 1074 mlxsw_reg_sftr_swid_set(payload, 0); 1075 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1076 mlxsw_reg_sftr_index_set(payload, index); 1077 mlxsw_reg_sftr_table_type_set(payload, table_type); 1078 mlxsw_reg_sftr_range_set(payload, range); 1079 mlxsw_reg_sftr_port_set(payload, port, set); 1080 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1081 } 1082 1083 /* SFDF - Switch Filtering DB Flush 1084 * -------------------------------- 1085 * The switch filtering DB flush register is used to flush the FDB. 1086 * Note that FDB notifications are flushed as well. 1087 */ 1088 #define MLXSW_REG_SFDF_ID 0x2013 1089 #define MLXSW_REG_SFDF_LEN 0x14 1090 1091 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1092 1093 /* reg_sfdf_swid 1094 * Switch partition ID. 1095 * Access: Index 1096 */ 1097 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1098 1099 enum mlxsw_reg_sfdf_flush_type { 1100 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1101 MLXSW_REG_SFDF_FLUSH_PER_FID, 1102 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1103 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1104 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1105 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1106 }; 1107 1108 /* reg_sfdf_flush_type 1109 * Flush type. 1110 * 0 - All SWID dynamic entries are flushed. 1111 * 1 - All FID dynamic entries are flushed. 1112 * 2 - All dynamic entries pointing to port are flushed. 1113 * 3 - All FID dynamic entries pointing to port are flushed. 1114 * 4 - All dynamic entries pointing to LAG are flushed. 1115 * 5 - All FID dynamic entries pointing to LAG are flushed. 1116 * Access: RW 1117 */ 1118 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1119 1120 /* reg_sfdf_flush_static 1121 * Static. 1122 * 0 - Flush only dynamic entries. 1123 * 1 - Flush both dynamic and static entries. 1124 * Access: RW 1125 */ 1126 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1127 1128 static inline void mlxsw_reg_sfdf_pack(char *payload, 1129 enum mlxsw_reg_sfdf_flush_type type) 1130 { 1131 MLXSW_REG_ZERO(sfdf, payload); 1132 mlxsw_reg_sfdf_flush_type_set(payload, type); 1133 mlxsw_reg_sfdf_flush_static_set(payload, true); 1134 } 1135 1136 /* reg_sfdf_fid 1137 * FID to flush. 1138 * Access: RW 1139 */ 1140 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1141 1142 /* reg_sfdf_system_port 1143 * Port to flush. 1144 * Access: RW 1145 */ 1146 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1147 1148 /* reg_sfdf_port_fid_system_port 1149 * Port to flush, pointed to by FID. 1150 * Access: RW 1151 */ 1152 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1153 1154 /* reg_sfdf_lag_id 1155 * LAG ID to flush. 1156 * Access: RW 1157 */ 1158 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1159 1160 /* reg_sfdf_lag_fid_lag_id 1161 * LAG ID to flush, pointed to by FID. 1162 * Access: RW 1163 */ 1164 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1165 1166 /* SLDR - Switch LAG Descriptor Register 1167 * ----------------------------------------- 1168 * The switch LAG descriptor register is populated by LAG descriptors. 1169 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1170 * max_lag-1. 1171 */ 1172 #define MLXSW_REG_SLDR_ID 0x2014 1173 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1174 1175 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1176 1177 enum mlxsw_reg_sldr_op { 1178 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1179 MLXSW_REG_SLDR_OP_LAG_CREATE, 1180 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1181 /* Ports that appear in the list have the Distributor enabled */ 1182 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1183 /* Removes ports from the disributor list */ 1184 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1185 }; 1186 1187 /* reg_sldr_op 1188 * Operation. 1189 * Access: RW 1190 */ 1191 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1192 1193 /* reg_sldr_lag_id 1194 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1195 * Access: Index 1196 */ 1197 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1198 1199 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1200 { 1201 MLXSW_REG_ZERO(sldr, payload); 1202 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1203 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1204 } 1205 1206 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1207 { 1208 MLXSW_REG_ZERO(sldr, payload); 1209 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1210 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1211 } 1212 1213 /* reg_sldr_num_ports 1214 * The number of member ports of the LAG. 1215 * Reserved for Create / Destroy operations 1216 * For Add / Remove operations - indicates the number of ports in the list. 1217 * Access: RW 1218 */ 1219 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1220 1221 /* reg_sldr_system_port 1222 * System port. 1223 * Access: RW 1224 */ 1225 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1226 1227 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1228 u8 local_port) 1229 { 1230 MLXSW_REG_ZERO(sldr, payload); 1231 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1232 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1233 mlxsw_reg_sldr_num_ports_set(payload, 1); 1234 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1235 } 1236 1237 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1238 u8 local_port) 1239 { 1240 MLXSW_REG_ZERO(sldr, payload); 1241 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1242 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1243 mlxsw_reg_sldr_num_ports_set(payload, 1); 1244 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1245 } 1246 1247 /* SLCR - Switch LAG Configuration 2 Register 1248 * ------------------------------------------- 1249 * The Switch LAG Configuration register is used for configuring the 1250 * LAG properties of the switch. 1251 */ 1252 #define MLXSW_REG_SLCR_ID 0x2015 1253 #define MLXSW_REG_SLCR_LEN 0x10 1254 1255 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1256 1257 enum mlxsw_reg_slcr_pp { 1258 /* Global Configuration (for all ports) */ 1259 MLXSW_REG_SLCR_PP_GLOBAL, 1260 /* Per port configuration, based on local_port field */ 1261 MLXSW_REG_SLCR_PP_PER_PORT, 1262 }; 1263 1264 /* reg_slcr_pp 1265 * Per Port Configuration 1266 * Note: Reading at Global mode results in reading port 1 configuration. 1267 * Access: Index 1268 */ 1269 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1270 1271 /* reg_slcr_local_port 1272 * Local port number 1273 * Supported from CPU port 1274 * Not supported from router port 1275 * Reserved when pp = Global Configuration 1276 * Access: Index 1277 */ 1278 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1279 1280 enum mlxsw_reg_slcr_type { 1281 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1282 MLXSW_REG_SLCR_TYPE_XOR, 1283 MLXSW_REG_SLCR_TYPE_RANDOM, 1284 }; 1285 1286 /* reg_slcr_type 1287 * Hash type 1288 * Access: RW 1289 */ 1290 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1291 1292 /* Ingress port */ 1293 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1294 /* SMAC - for IPv4 and IPv6 packets */ 1295 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1296 /* SMAC - for non-IP packets */ 1297 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1298 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1299 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1300 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1301 /* DMAC - for IPv4 and IPv6 packets */ 1302 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1303 /* DMAC - for non-IP packets */ 1304 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1305 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1306 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1307 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1308 /* Ethertype - for IPv4 and IPv6 packets */ 1309 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1310 /* Ethertype - for non-IP packets */ 1311 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1312 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1313 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1314 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1315 /* VLAN ID - for IPv4 and IPv6 packets */ 1316 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1317 /* VLAN ID - for non-IP packets */ 1318 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1319 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1320 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1321 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1322 /* Source IP address (can be IPv4 or IPv6) */ 1323 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1324 /* Destination IP address (can be IPv4 or IPv6) */ 1325 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1326 /* TCP/UDP source port */ 1327 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1328 /* TCP/UDP destination port*/ 1329 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1330 /* IPv4 Protocol/IPv6 Next Header */ 1331 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1332 /* IPv6 Flow label */ 1333 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1334 /* SID - FCoE source ID */ 1335 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1336 /* DID - FCoE destination ID */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1338 /* OXID - FCoE originator exchange ID */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1340 /* Destination QP number - for RoCE packets */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1342 1343 /* reg_slcr_lag_hash 1344 * LAG hashing configuration. This is a bitmask, in which each set 1345 * bit includes the corresponding item in the LAG hash calculation. 1346 * The default lag_hash contains SMAC, DMAC, VLANID and 1347 * Ethertype (for all packet types). 1348 * Access: RW 1349 */ 1350 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1351 1352 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1353 { 1354 MLXSW_REG_ZERO(slcr, payload); 1355 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1356 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1357 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1358 } 1359 1360 /* SLCOR - Switch LAG Collector Register 1361 * ------------------------------------- 1362 * The Switch LAG Collector register controls the Local Port membership 1363 * in a LAG and enablement of the collector. 1364 */ 1365 #define MLXSW_REG_SLCOR_ID 0x2016 1366 #define MLXSW_REG_SLCOR_LEN 0x10 1367 1368 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1369 1370 enum mlxsw_reg_slcor_col { 1371 /* Port is added with collector disabled */ 1372 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1373 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1374 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1375 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1376 }; 1377 1378 /* reg_slcor_col 1379 * Collector configuration 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1383 1384 /* reg_slcor_local_port 1385 * Local port number 1386 * Not supported for CPU port 1387 * Access: Index 1388 */ 1389 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1390 1391 /* reg_slcor_lag_id 1392 * LAG Identifier. Index into the LAG descriptor table. 1393 * Access: Index 1394 */ 1395 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1396 1397 /* reg_slcor_port_index 1398 * Port index in the LAG list. Only valid on Add Port to LAG col. 1399 * Valid range is from 0 to cap_max_lag_members-1 1400 * Access: RW 1401 */ 1402 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1403 1404 static inline void mlxsw_reg_slcor_pack(char *payload, 1405 u8 local_port, u16 lag_id, 1406 enum mlxsw_reg_slcor_col col) 1407 { 1408 MLXSW_REG_ZERO(slcor, payload); 1409 mlxsw_reg_slcor_col_set(payload, col); 1410 mlxsw_reg_slcor_local_port_set(payload, local_port); 1411 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1412 } 1413 1414 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1415 u8 local_port, u16 lag_id, 1416 u8 port_index) 1417 { 1418 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1419 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1420 mlxsw_reg_slcor_port_index_set(payload, port_index); 1421 } 1422 1423 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1424 u8 local_port, u16 lag_id) 1425 { 1426 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1427 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1428 } 1429 1430 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1431 u8 local_port, u16 lag_id) 1432 { 1433 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1435 } 1436 1437 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1438 u8 local_port, u16 lag_id) 1439 { 1440 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1441 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1442 } 1443 1444 /* SPMLR - Switch Port MAC Learning Register 1445 * ----------------------------------------- 1446 * Controls the Switch MAC learning policy per port. 1447 */ 1448 #define MLXSW_REG_SPMLR_ID 0x2018 1449 #define MLXSW_REG_SPMLR_LEN 0x8 1450 1451 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1452 1453 /* reg_spmlr_local_port 1454 * Local port number. 1455 * Access: Index 1456 */ 1457 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1458 1459 /* reg_spmlr_sub_port 1460 * Virtual port within the physical port. 1461 * Should be set to 0 when virtual ports are not enabled on the port. 1462 * Access: Index 1463 */ 1464 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1465 1466 enum mlxsw_reg_spmlr_learn_mode { 1467 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1468 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1469 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1470 }; 1471 1472 /* reg_spmlr_learn_mode 1473 * Learning mode on the port. 1474 * 0 - Learning disabled. 1475 * 2 - Learning enabled. 1476 * 3 - Security mode. 1477 * 1478 * In security mode the switch does not learn MACs on the port, but uses the 1479 * SMAC to see if it exists on another ingress port. If so, the packet is 1480 * classified as a bad packet and is discarded unless the software registers 1481 * to receive port security error packets usign HPKT. 1482 */ 1483 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1484 1485 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1486 enum mlxsw_reg_spmlr_learn_mode mode) 1487 { 1488 MLXSW_REG_ZERO(spmlr, payload); 1489 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1490 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1491 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1492 } 1493 1494 /* SVFA - Switch VID to FID Allocation Register 1495 * -------------------------------------------- 1496 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1497 * virtualized ports. 1498 */ 1499 #define MLXSW_REG_SVFA_ID 0x201C 1500 #define MLXSW_REG_SVFA_LEN 0x10 1501 1502 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1503 1504 /* reg_svfa_swid 1505 * Switch partition ID. 1506 * Access: Index 1507 */ 1508 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1509 1510 /* reg_svfa_local_port 1511 * Local port number. 1512 * Access: Index 1513 * 1514 * Note: Reserved for 802.1Q FIDs. 1515 */ 1516 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1517 1518 enum mlxsw_reg_svfa_mt { 1519 MLXSW_REG_SVFA_MT_VID_TO_FID, 1520 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1521 }; 1522 1523 /* reg_svfa_mapping_table 1524 * Mapping table: 1525 * 0 - VID to FID 1526 * 1 - {Port, VID} to FID 1527 * Access: Index 1528 * 1529 * Note: Reserved for SwitchX-2. 1530 */ 1531 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1532 1533 /* reg_svfa_v 1534 * Valid. 1535 * Valid if set. 1536 * Access: RW 1537 * 1538 * Note: Reserved for SwitchX-2. 1539 */ 1540 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1541 1542 /* reg_svfa_fid 1543 * Filtering ID. 1544 * Access: RW 1545 */ 1546 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1547 1548 /* reg_svfa_vid 1549 * VLAN ID. 1550 * Access: Index 1551 */ 1552 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1553 1554 /* reg_svfa_counter_set_type 1555 * Counter set type for flow counters. 1556 * Access: RW 1557 * 1558 * Note: Reserved for SwitchX-2. 1559 */ 1560 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1561 1562 /* reg_svfa_counter_index 1563 * Counter index for flow counters. 1564 * Access: RW 1565 * 1566 * Note: Reserved for SwitchX-2. 1567 */ 1568 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1569 1570 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1571 enum mlxsw_reg_svfa_mt mt, bool valid, 1572 u16 fid, u16 vid) 1573 { 1574 MLXSW_REG_ZERO(svfa, payload); 1575 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1576 mlxsw_reg_svfa_swid_set(payload, 0); 1577 mlxsw_reg_svfa_local_port_set(payload, local_port); 1578 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1579 mlxsw_reg_svfa_v_set(payload, valid); 1580 mlxsw_reg_svfa_fid_set(payload, fid); 1581 mlxsw_reg_svfa_vid_set(payload, vid); 1582 } 1583 1584 /* SVPE - Switch Virtual-Port Enabling Register 1585 * -------------------------------------------- 1586 * Enables port virtualization. 1587 */ 1588 #define MLXSW_REG_SVPE_ID 0x201E 1589 #define MLXSW_REG_SVPE_LEN 0x4 1590 1591 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1592 1593 /* reg_svpe_local_port 1594 * Local port number 1595 * Access: Index 1596 * 1597 * Note: CPU port is not supported (uses VLAN mode only). 1598 */ 1599 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1600 1601 /* reg_svpe_vp_en 1602 * Virtual port enable. 1603 * 0 - Disable, VLAN mode (VID to FID). 1604 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1608 1609 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1610 bool enable) 1611 { 1612 MLXSW_REG_ZERO(svpe, payload); 1613 mlxsw_reg_svpe_local_port_set(payload, local_port); 1614 mlxsw_reg_svpe_vp_en_set(payload, enable); 1615 } 1616 1617 /* SFMR - Switch FID Management Register 1618 * ------------------------------------- 1619 * Creates and configures FIDs. 1620 */ 1621 #define MLXSW_REG_SFMR_ID 0x201F 1622 #define MLXSW_REG_SFMR_LEN 0x18 1623 1624 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1625 1626 enum mlxsw_reg_sfmr_op { 1627 MLXSW_REG_SFMR_OP_CREATE_FID, 1628 MLXSW_REG_SFMR_OP_DESTROY_FID, 1629 }; 1630 1631 /* reg_sfmr_op 1632 * Operation. 1633 * 0 - Create or edit FID. 1634 * 1 - Destroy FID. 1635 * Access: WO 1636 */ 1637 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1638 1639 /* reg_sfmr_fid 1640 * Filtering ID. 1641 * Access: Index 1642 */ 1643 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1644 1645 /* reg_sfmr_fid_offset 1646 * FID offset. 1647 * Used to point into the flooding table selected by SFGC register if 1648 * the table is of type FID-Offset. Otherwise, this field is reserved. 1649 * Access: RW 1650 */ 1651 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1652 1653 /* reg_sfmr_vtfp 1654 * Valid Tunnel Flood Pointer. 1655 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1656 * Access: RW 1657 * 1658 * Note: Reserved for 802.1Q FIDs. 1659 */ 1660 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1661 1662 /* reg_sfmr_nve_tunnel_flood_ptr 1663 * Underlay Flooding and BC Pointer. 1664 * Used as a pointer to the first entry of the group based link lists of 1665 * flooding or BC entries (for NVE tunnels). 1666 * Access: RW 1667 */ 1668 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1669 1670 /* reg_sfmr_vv 1671 * VNI Valid. 1672 * If not set, then vni is reserved. 1673 * Access: RW 1674 * 1675 * Note: Reserved for 802.1Q FIDs. 1676 */ 1677 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1678 1679 /* reg_sfmr_vni 1680 * Virtual Network Identifier. 1681 * Access: RW 1682 * 1683 * Note: A given VNI can only be assigned to one FID. 1684 */ 1685 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1686 1687 static inline void mlxsw_reg_sfmr_pack(char *payload, 1688 enum mlxsw_reg_sfmr_op op, u16 fid, 1689 u16 fid_offset) 1690 { 1691 MLXSW_REG_ZERO(sfmr, payload); 1692 mlxsw_reg_sfmr_op_set(payload, op); 1693 mlxsw_reg_sfmr_fid_set(payload, fid); 1694 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1695 mlxsw_reg_sfmr_vtfp_set(payload, false); 1696 mlxsw_reg_sfmr_vv_set(payload, false); 1697 } 1698 1699 /* SPVMLR - Switch Port VLAN MAC Learning Register 1700 * ----------------------------------------------- 1701 * Controls the switch MAC learning policy per {Port, VID}. 1702 */ 1703 #define MLXSW_REG_SPVMLR_ID 0x2020 1704 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1705 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1706 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1707 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1708 MLXSW_REG_SPVMLR_REC_LEN * \ 1709 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1710 1711 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1712 1713 /* reg_spvmlr_local_port 1714 * Local ingress port. 1715 * Access: Index 1716 * 1717 * Note: CPU port is not supported. 1718 */ 1719 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1720 1721 /* reg_spvmlr_num_rec 1722 * Number of records to update. 1723 * Access: OP 1724 */ 1725 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1726 1727 /* reg_spvmlr_rec_learn_enable 1728 * 0 - Disable learning for {Port, VID}. 1729 * 1 - Enable learning for {Port, VID}. 1730 * Access: RW 1731 */ 1732 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1733 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1734 1735 /* reg_spvmlr_rec_vid 1736 * VLAN ID to be added/removed from port or for querying. 1737 * Access: Index 1738 */ 1739 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1740 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1741 1742 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1743 u16 vid_begin, u16 vid_end, 1744 bool learn_enable) 1745 { 1746 int num_rec = vid_end - vid_begin + 1; 1747 int i; 1748 1749 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1750 1751 MLXSW_REG_ZERO(spvmlr, payload); 1752 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1753 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1754 1755 for (i = 0; i < num_rec; i++) { 1756 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1757 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1758 } 1759 } 1760 1761 /* CWTP - Congetion WRED ECN TClass Profile 1762 * ---------------------------------------- 1763 * Configures the profiles for queues of egress port and traffic class 1764 */ 1765 #define MLXSW_REG_CWTP_ID 0x2802 1766 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1767 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1768 #define MLXSW_REG_CWTP_LEN 0x40 1769 1770 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1771 1772 /* reg_cwtp_local_port 1773 * Local port number 1774 * Not supported for CPU port 1775 * Access: Index 1776 */ 1777 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1778 1779 /* reg_cwtp_traffic_class 1780 * Traffic Class to configure 1781 * Access: Index 1782 */ 1783 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1784 1785 /* reg_cwtp_profile_min 1786 * Minimum Average Queue Size of the profile in cells. 1787 * Access: RW 1788 */ 1789 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1790 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1791 1792 /* reg_cwtp_profile_percent 1793 * Percentage of WRED and ECN marking for maximum Average Queue size 1794 * Range is 0 to 100, units of integer percentage 1795 * Access: RW 1796 */ 1797 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1798 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1799 1800 /* reg_cwtp_profile_max 1801 * Maximum Average Queue size of the profile in cells 1802 * Access: RW 1803 */ 1804 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1805 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1806 1807 #define MLXSW_REG_CWTP_MIN_VALUE 64 1808 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1809 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1810 1811 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1812 u8 traffic_class) 1813 { 1814 int i; 1815 1816 MLXSW_REG_ZERO(cwtp, payload); 1817 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1818 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1819 1820 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1821 mlxsw_reg_cwtp_profile_min_set(payload, i, 1822 MLXSW_REG_CWTP_MIN_VALUE); 1823 mlxsw_reg_cwtp_profile_max_set(payload, i, 1824 MLXSW_REG_CWTP_MIN_VALUE); 1825 } 1826 } 1827 1828 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1829 1830 static inline void 1831 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1832 u32 probability) 1833 { 1834 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1835 1836 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1837 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1838 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1839 } 1840 1841 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1842 * --------------------------------------------------- 1843 * The CWTPM register maps each egress port and traffic class to profile num. 1844 */ 1845 #define MLXSW_REG_CWTPM_ID 0x2803 1846 #define MLXSW_REG_CWTPM_LEN 0x44 1847 1848 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1849 1850 /* reg_cwtpm_local_port 1851 * Local port number 1852 * Not supported for CPU port 1853 * Access: Index 1854 */ 1855 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1856 1857 /* reg_cwtpm_traffic_class 1858 * Traffic Class to configure 1859 * Access: Index 1860 */ 1861 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1862 1863 /* reg_cwtpm_ew 1864 * Control enablement of WRED for traffic class: 1865 * 0 - Disable 1866 * 1 - Enable 1867 * Access: RW 1868 */ 1869 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1870 1871 /* reg_cwtpm_ee 1872 * Control enablement of ECN for traffic class: 1873 * 0 - Disable 1874 * 1 - Enable 1875 * Access: RW 1876 */ 1877 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1878 1879 /* reg_cwtpm_tcp_g 1880 * TCP Green Profile. 1881 * Index of the profile within {port, traffic class} to use. 1882 * 0 for disabling both WRED and ECN for this type of traffic. 1883 * Access: RW 1884 */ 1885 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1886 1887 /* reg_cwtpm_tcp_y 1888 * TCP Yellow Profile. 1889 * Index of the profile within {port, traffic class} to use. 1890 * 0 for disabling both WRED and ECN for this type of traffic. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1894 1895 /* reg_cwtpm_tcp_r 1896 * TCP Red Profile. 1897 * Index of the profile within {port, traffic class} to use. 1898 * 0 for disabling both WRED and ECN for this type of traffic. 1899 * Access: RW 1900 */ 1901 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 1902 1903 /* reg_cwtpm_ntcp_g 1904 * Non-TCP Green Profile. 1905 * Index of the profile within {port, traffic class} to use. 1906 * 0 for disabling both WRED and ECN for this type of traffic. 1907 * Access: RW 1908 */ 1909 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 1910 1911 /* reg_cwtpm_ntcp_y 1912 * Non-TCP Yellow Profile. 1913 * Index of the profile within {port, traffic class} to use. 1914 * 0 for disabling both WRED and ECN for this type of traffic. 1915 * Access: RW 1916 */ 1917 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 1918 1919 /* reg_cwtpm_ntcp_r 1920 * Non-TCP Red Profile. 1921 * Index of the profile within {port, traffic class} to use. 1922 * 0 for disabling both WRED and ECN for this type of traffic. 1923 * Access: RW 1924 */ 1925 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 1926 1927 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 1928 1929 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 1930 u8 traffic_class, u8 profile, 1931 bool wred, bool ecn) 1932 { 1933 MLXSW_REG_ZERO(cwtpm, payload); 1934 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 1935 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 1936 mlxsw_reg_cwtpm_ew_set(payload, wred); 1937 mlxsw_reg_cwtpm_ee_set(payload, ecn); 1938 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 1939 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 1940 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 1941 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 1942 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 1943 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 1944 } 1945 1946 /* PPBT - Policy-Engine Port Binding Table 1947 * --------------------------------------- 1948 * This register is used for configuration of the Port Binding Table. 1949 */ 1950 #define MLXSW_REG_PPBT_ID 0x3002 1951 #define MLXSW_REG_PPBT_LEN 0x14 1952 1953 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 1954 1955 enum mlxsw_reg_pxbt_e { 1956 MLXSW_REG_PXBT_E_IACL, 1957 MLXSW_REG_PXBT_E_EACL, 1958 }; 1959 1960 /* reg_ppbt_e 1961 * Access: Index 1962 */ 1963 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 1964 1965 enum mlxsw_reg_pxbt_op { 1966 MLXSW_REG_PXBT_OP_BIND, 1967 MLXSW_REG_PXBT_OP_UNBIND, 1968 }; 1969 1970 /* reg_ppbt_op 1971 * Access: RW 1972 */ 1973 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 1974 1975 /* reg_ppbt_local_port 1976 * Local port. Not including CPU port. 1977 * Access: Index 1978 */ 1979 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 1980 1981 /* reg_ppbt_g 1982 * group - When set, the binding is of an ACL group. When cleared, 1983 * the binding is of an ACL. 1984 * Must be set to 1 for Spectrum. 1985 * Access: RW 1986 */ 1987 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 1988 1989 /* reg_ppbt_acl_info 1990 * ACL/ACL group identifier. If the g bit is set, this field should hold 1991 * the acl_group_id, else it should hold the acl_id. 1992 * Access: RW 1993 */ 1994 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 1995 1996 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 1997 enum mlxsw_reg_pxbt_op op, 1998 u8 local_port, u16 acl_info) 1999 { 2000 MLXSW_REG_ZERO(ppbt, payload); 2001 mlxsw_reg_ppbt_e_set(payload, e); 2002 mlxsw_reg_ppbt_op_set(payload, op); 2003 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2004 mlxsw_reg_ppbt_g_set(payload, true); 2005 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2006 } 2007 2008 /* PACL - Policy-Engine ACL Register 2009 * --------------------------------- 2010 * This register is used for configuration of the ACL. 2011 */ 2012 #define MLXSW_REG_PACL_ID 0x3004 2013 #define MLXSW_REG_PACL_LEN 0x70 2014 2015 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2016 2017 /* reg_pacl_v 2018 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2019 * while the ACL is bounded to either a port, VLAN or ACL rule. 2020 * Access: RW 2021 */ 2022 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2023 2024 /* reg_pacl_acl_id 2025 * An identifier representing the ACL (managed by software) 2026 * Range 0 .. cap_max_acl_regions - 1 2027 * Access: Index 2028 */ 2029 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2030 2031 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2032 2033 /* reg_pacl_tcam_region_info 2034 * Opaque object that represents a TCAM region. 2035 * Obtained through PTAR register. 2036 * Access: RW 2037 */ 2038 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2039 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2040 2041 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2042 bool valid, const char *tcam_region_info) 2043 { 2044 MLXSW_REG_ZERO(pacl, payload); 2045 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2046 mlxsw_reg_pacl_v_set(payload, valid); 2047 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2048 } 2049 2050 /* PAGT - Policy-Engine ACL Group Table 2051 * ------------------------------------ 2052 * This register is used for configuration of the ACL Group Table. 2053 */ 2054 #define MLXSW_REG_PAGT_ID 0x3005 2055 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2056 #define MLXSW_REG_PAGT_ACL_LEN 4 2057 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2058 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2059 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2060 2061 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2062 2063 /* reg_pagt_size 2064 * Number of ACLs in the group. 2065 * Size 0 invalidates a group. 2066 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2067 * Total number of ACLs in all groups must be lower or equal 2068 * to cap_max_acl_tot_groups 2069 * Note: a group which is binded must not be invalidated 2070 * Access: Index 2071 */ 2072 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2073 2074 /* reg_pagt_acl_group_id 2075 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2076 * the ACL Group identifier (managed by software). 2077 * Access: Index 2078 */ 2079 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2080 2081 /* reg_pagt_acl_id 2082 * ACL identifier 2083 * Access: RW 2084 */ 2085 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2086 2087 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2088 { 2089 MLXSW_REG_ZERO(pagt, payload); 2090 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2091 } 2092 2093 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2094 u16 acl_id) 2095 { 2096 u8 size = mlxsw_reg_pagt_size_get(payload); 2097 2098 if (index >= size) 2099 mlxsw_reg_pagt_size_set(payload, index + 1); 2100 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2101 } 2102 2103 /* PTAR - Policy-Engine TCAM Allocation Register 2104 * --------------------------------------------- 2105 * This register is used for allocation of regions in the TCAM. 2106 * Note: Query method is not supported on this register. 2107 */ 2108 #define MLXSW_REG_PTAR_ID 0x3006 2109 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2110 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2111 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2112 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2113 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2114 2115 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2116 2117 enum mlxsw_reg_ptar_op { 2118 /* allocate a TCAM region */ 2119 MLXSW_REG_PTAR_OP_ALLOC, 2120 /* resize a TCAM region */ 2121 MLXSW_REG_PTAR_OP_RESIZE, 2122 /* deallocate TCAM region */ 2123 MLXSW_REG_PTAR_OP_FREE, 2124 /* test allocation */ 2125 MLXSW_REG_PTAR_OP_TEST, 2126 }; 2127 2128 /* reg_ptar_op 2129 * Access: OP 2130 */ 2131 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2132 2133 /* reg_ptar_action_set_type 2134 * Type of action set to be used on this region. 2135 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2136 * Access: WO 2137 */ 2138 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2139 2140 enum mlxsw_reg_ptar_key_type { 2141 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2142 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2143 }; 2144 2145 /* reg_ptar_key_type 2146 * TCAM key type for the region. 2147 * Access: WO 2148 */ 2149 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2150 2151 /* reg_ptar_region_size 2152 * TCAM region size. When allocating/resizing this is the requested size, 2153 * the response is the actual size. Note that actual size may be 2154 * larger than requested. 2155 * Allowed range 1 .. cap_max_rules-1 2156 * Reserved during op deallocate. 2157 * Access: WO 2158 */ 2159 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2160 2161 /* reg_ptar_region_id 2162 * Region identifier 2163 * Range 0 .. cap_max_regions-1 2164 * Access: Index 2165 */ 2166 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2167 2168 /* reg_ptar_tcam_region_info 2169 * Opaque object that represents the TCAM region. 2170 * Returned when allocating a region. 2171 * Provided by software for ACL generation and region deallocation and resize. 2172 * Access: RW 2173 */ 2174 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2175 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2176 2177 /* reg_ptar_flexible_key_id 2178 * Identifier of the Flexible Key. 2179 * Only valid if key_type == "FLEX_KEY" 2180 * The key size will be rounded up to one of the following values: 2181 * 9B, 18B, 36B, 54B. 2182 * This field is reserved for in resize operation. 2183 * Access: WO 2184 */ 2185 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2186 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2187 2188 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2189 enum mlxsw_reg_ptar_key_type key_type, 2190 u16 region_size, u16 region_id, 2191 const char *tcam_region_info) 2192 { 2193 MLXSW_REG_ZERO(ptar, payload); 2194 mlxsw_reg_ptar_op_set(payload, op); 2195 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2196 mlxsw_reg_ptar_key_type_set(payload, key_type); 2197 mlxsw_reg_ptar_region_size_set(payload, region_size); 2198 mlxsw_reg_ptar_region_id_set(payload, region_id); 2199 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2200 } 2201 2202 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2203 u16 key_id) 2204 { 2205 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2206 } 2207 2208 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2209 { 2210 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2211 } 2212 2213 /* PPBS - Policy-Engine Policy Based Switching Register 2214 * ---------------------------------------------------- 2215 * This register retrieves and sets Policy Based Switching Table entries. 2216 */ 2217 #define MLXSW_REG_PPBS_ID 0x300C 2218 #define MLXSW_REG_PPBS_LEN 0x14 2219 2220 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2221 2222 /* reg_ppbs_pbs_ptr 2223 * Index into the PBS table. 2224 * For Spectrum, the index points to the KVD Linear. 2225 * Access: Index 2226 */ 2227 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2228 2229 /* reg_ppbs_system_port 2230 * Unique port identifier for the final destination of the packet. 2231 * Access: RW 2232 */ 2233 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2234 2235 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2236 u16 system_port) 2237 { 2238 MLXSW_REG_ZERO(ppbs, payload); 2239 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2240 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2241 } 2242 2243 /* PRCR - Policy-Engine Rules Copy Register 2244 * ---------------------------------------- 2245 * This register is used for accessing rules within a TCAM region. 2246 */ 2247 #define MLXSW_REG_PRCR_ID 0x300D 2248 #define MLXSW_REG_PRCR_LEN 0x40 2249 2250 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2251 2252 enum mlxsw_reg_prcr_op { 2253 /* Move rules. Moves the rules from "tcam_region_info" starting 2254 * at offset "offset" to "dest_tcam_region_info" 2255 * at offset "dest_offset." 2256 */ 2257 MLXSW_REG_PRCR_OP_MOVE, 2258 /* Copy rules. Copies the rules from "tcam_region_info" starting 2259 * at offset "offset" to "dest_tcam_region_info" 2260 * at offset "dest_offset." 2261 */ 2262 MLXSW_REG_PRCR_OP_COPY, 2263 }; 2264 2265 /* reg_prcr_op 2266 * Access: OP 2267 */ 2268 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2269 2270 /* reg_prcr_offset 2271 * Offset within the source region to copy/move from. 2272 * Access: Index 2273 */ 2274 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2275 2276 /* reg_prcr_size 2277 * The number of rules to copy/move. 2278 * Access: WO 2279 */ 2280 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2281 2282 /* reg_prcr_tcam_region_info 2283 * Opaque object that represents the source TCAM region. 2284 * Access: Index 2285 */ 2286 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2287 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2288 2289 /* reg_prcr_dest_offset 2290 * Offset within the source region to copy/move to. 2291 * Access: Index 2292 */ 2293 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2294 2295 /* reg_prcr_dest_tcam_region_info 2296 * Opaque object that represents the destination TCAM region. 2297 * Access: Index 2298 */ 2299 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2300 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2301 2302 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2303 const char *src_tcam_region_info, 2304 u16 src_offset, 2305 const char *dest_tcam_region_info, 2306 u16 dest_offset, u16 size) 2307 { 2308 MLXSW_REG_ZERO(prcr, payload); 2309 mlxsw_reg_prcr_op_set(payload, op); 2310 mlxsw_reg_prcr_offset_set(payload, src_offset); 2311 mlxsw_reg_prcr_size_set(payload, size); 2312 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2313 src_tcam_region_info); 2314 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2315 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2316 dest_tcam_region_info); 2317 } 2318 2319 /* PEFA - Policy-Engine Extended Flexible Action Register 2320 * ------------------------------------------------------ 2321 * This register is used for accessing an extended flexible action entry 2322 * in the central KVD Linear Database. 2323 */ 2324 #define MLXSW_REG_PEFA_ID 0x300F 2325 #define MLXSW_REG_PEFA_LEN 0xB0 2326 2327 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2328 2329 /* reg_pefa_index 2330 * Index in the KVD Linear Centralized Database. 2331 * Access: Index 2332 */ 2333 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2334 2335 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2336 2337 /* reg_pefa_flex_action_set 2338 * Action-set to perform when rule is matched. 2339 * Must be zero padded if action set is shorter. 2340 * Access: RW 2341 */ 2342 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2343 2344 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, 2345 const char *flex_action_set) 2346 { 2347 MLXSW_REG_ZERO(pefa, payload); 2348 mlxsw_reg_pefa_index_set(payload, index); 2349 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, flex_action_set); 2350 } 2351 2352 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2353 * ----------------------------------------------------- 2354 * This register is used for accessing rules within a TCAM region. 2355 * It is a new version of PTCE in order to support wider key, 2356 * mask and action within a TCAM region. This register is not supported 2357 * by SwitchX and SwitchX-2. 2358 */ 2359 #define MLXSW_REG_PTCE2_ID 0x3017 2360 #define MLXSW_REG_PTCE2_LEN 0x1D8 2361 2362 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2363 2364 /* reg_ptce2_v 2365 * Valid. 2366 * Access: RW 2367 */ 2368 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2369 2370 /* reg_ptce2_a 2371 * Activity. Set if a packet lookup has hit on the specific entry. 2372 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2373 * Access: RO 2374 */ 2375 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2376 2377 enum mlxsw_reg_ptce2_op { 2378 /* Read operation. */ 2379 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2380 /* clear on read operation. Used to read entry 2381 * and clear Activity bit. 2382 */ 2383 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2384 /* Write operation. Used to write a new entry to the table. 2385 * All R/W fields are relevant for new entry. Activity bit is set 2386 * for new entries - Note write with v = 0 will delete the entry. 2387 */ 2388 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2389 /* Update action. Only action set will be updated. */ 2390 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2391 /* Clear activity. A bit is cleared for the entry. */ 2392 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2393 }; 2394 2395 /* reg_ptce2_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2399 2400 /* reg_ptce2_offset 2401 * Access: Index 2402 */ 2403 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2404 2405 /* reg_ptce2_priority 2406 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2407 * Note: priority does not have to be unique per rule. 2408 * Within a region, higher priority should have lower offset (no limitation 2409 * between regions in a multi-region). 2410 * Access: RW 2411 */ 2412 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2413 2414 /* reg_ptce2_tcam_region_info 2415 * Opaque object that represents the TCAM region. 2416 * Access: Index 2417 */ 2418 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2419 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2420 2421 #define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96 2422 2423 /* reg_ptce2_flex_key_blocks 2424 * ACL Key. 2425 * Access: RW 2426 */ 2427 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2428 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2429 2430 /* reg_ptce2_mask 2431 * mask- in the same size as key. A bit that is set directs the TCAM 2432 * to compare the corresponding bit in key. A bit that is clear directs 2433 * the TCAM to ignore the corresponding bit in key. 2434 * Access: RW 2435 */ 2436 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2437 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2438 2439 /* reg_ptce2_flex_action_set 2440 * ACL action set. 2441 * Access: RW 2442 */ 2443 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2444 MLXSW_REG_FLEX_ACTION_SET_LEN); 2445 2446 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2447 enum mlxsw_reg_ptce2_op op, 2448 const char *tcam_region_info, 2449 u16 offset, u32 priority) 2450 { 2451 MLXSW_REG_ZERO(ptce2, payload); 2452 mlxsw_reg_ptce2_v_set(payload, valid); 2453 mlxsw_reg_ptce2_op_set(payload, op); 2454 mlxsw_reg_ptce2_offset_set(payload, offset); 2455 mlxsw_reg_ptce2_priority_set(payload, priority); 2456 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2457 } 2458 2459 /* QPCR - QoS Policer Configuration Register 2460 * ----------------------------------------- 2461 * The QPCR register is used to create policers - that limit 2462 * the rate of bytes or packets via some trap group. 2463 */ 2464 #define MLXSW_REG_QPCR_ID 0x4004 2465 #define MLXSW_REG_QPCR_LEN 0x28 2466 2467 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 2468 2469 enum mlxsw_reg_qpcr_g { 2470 MLXSW_REG_QPCR_G_GLOBAL = 2, 2471 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 2472 }; 2473 2474 /* reg_qpcr_g 2475 * The policer type. 2476 * Access: Index 2477 */ 2478 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 2479 2480 /* reg_qpcr_pid 2481 * Policer ID. 2482 * Access: Index 2483 */ 2484 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 2485 2486 /* reg_qpcr_color_aware 2487 * Is the policer aware of colors. 2488 * Must be 0 (unaware) for cpu port. 2489 * Access: RW for unbounded policer. RO for bounded policer. 2490 */ 2491 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 2492 2493 /* reg_qpcr_bytes 2494 * Is policer limit is for bytes per sec or packets per sec. 2495 * 0 - packets 2496 * 1 - bytes 2497 * Access: RW for unbounded policer. RO for bounded policer. 2498 */ 2499 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 2500 2501 enum mlxsw_reg_qpcr_ir_units { 2502 MLXSW_REG_QPCR_IR_UNITS_M, 2503 MLXSW_REG_QPCR_IR_UNITS_K, 2504 }; 2505 2506 /* reg_qpcr_ir_units 2507 * Policer's units for cir and eir fields (for bytes limits only) 2508 * 1 - 10^3 2509 * 0 - 10^6 2510 * Access: OP 2511 */ 2512 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 2513 2514 enum mlxsw_reg_qpcr_rate_type { 2515 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 2516 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 2517 }; 2518 2519 /* reg_qpcr_rate_type 2520 * Policer can have one limit (single rate) or 2 limits with specific operation 2521 * for packets that exceed the lower rate but not the upper one. 2522 * (For cpu port must be single rate) 2523 * Access: RW for unbounded policer. RO for bounded policer. 2524 */ 2525 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 2526 2527 /* reg_qpc_cbs 2528 * Policer's committed burst size. 2529 * The policer is working with time slices of 50 nano sec. By default every 2530 * slice is granted the proportionate share of the committed rate. If we want to 2531 * allow a slice to exceed that share (while still keeping the rate per sec) we 2532 * can allow burst. The burst size is between the default proportionate share 2533 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 2534 * committed rate will result in exceeding the rate). The burst size must be a 2535 * log of 2 and will be determined by 2^cbs. 2536 * Access: RW 2537 */ 2538 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 2539 2540 /* reg_qpcr_cir 2541 * Policer's committed rate. 2542 * The rate used for sungle rate, the lower rate for double rate. 2543 * For bytes limits, the rate will be this value * the unit from ir_units. 2544 * (Resolution error is up to 1%). 2545 * Access: RW 2546 */ 2547 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 2548 2549 /* reg_qpcr_eir 2550 * Policer's exceed rate. 2551 * The higher rate for double rate, reserved for single rate. 2552 * Lower rate for double rate policer. 2553 * For bytes limits, the rate will be this value * the unit from ir_units. 2554 * (Resolution error is up to 1%). 2555 * Access: RW 2556 */ 2557 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 2558 2559 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 2560 2561 /* reg_qpcr_exceed_action. 2562 * What to do with packets between the 2 limits for double rate. 2563 * Access: RW for unbounded policer. RO for bounded policer. 2564 */ 2565 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 2566 2567 enum mlxsw_reg_qpcr_action { 2568 /* Discard */ 2569 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 2570 /* Forward and set color to red. 2571 * If the packet is intended to cpu port, it will be dropped. 2572 */ 2573 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 2574 }; 2575 2576 /* reg_qpcr_violate_action 2577 * What to do with packets that cross the cir limit (for single rate) or the eir 2578 * limit (for double rate). 2579 * Access: RW for unbounded policer. RO for bounded policer. 2580 */ 2581 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 2582 2583 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 2584 enum mlxsw_reg_qpcr_ir_units ir_units, 2585 bool bytes, u32 cir, u16 cbs) 2586 { 2587 MLXSW_REG_ZERO(qpcr, payload); 2588 mlxsw_reg_qpcr_pid_set(payload, pid); 2589 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 2590 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 2591 mlxsw_reg_qpcr_violate_action_set(payload, 2592 MLXSW_REG_QPCR_ACTION_DISCARD); 2593 mlxsw_reg_qpcr_cir_set(payload, cir); 2594 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 2595 mlxsw_reg_qpcr_bytes_set(payload, bytes); 2596 mlxsw_reg_qpcr_cbs_set(payload, cbs); 2597 } 2598 2599 /* QTCT - QoS Switch Traffic Class Table 2600 * ------------------------------------- 2601 * Configures the mapping between the packet switch priority and the 2602 * traffic class on the transmit port. 2603 */ 2604 #define MLXSW_REG_QTCT_ID 0x400A 2605 #define MLXSW_REG_QTCT_LEN 0x08 2606 2607 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 2608 2609 /* reg_qtct_local_port 2610 * Local port number. 2611 * Access: Index 2612 * 2613 * Note: CPU port is not supported. 2614 */ 2615 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 2616 2617 /* reg_qtct_sub_port 2618 * Virtual port within the physical port. 2619 * Should be set to 0 when virtual ports are not enabled on the port. 2620 * Access: Index 2621 */ 2622 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 2623 2624 /* reg_qtct_switch_prio 2625 * Switch priority. 2626 * Access: Index 2627 */ 2628 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 2629 2630 /* reg_qtct_tclass 2631 * Traffic class. 2632 * Default values: 2633 * switch_prio 0 : tclass 1 2634 * switch_prio 1 : tclass 0 2635 * switch_prio i : tclass i, for i > 1 2636 * Access: RW 2637 */ 2638 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 2639 2640 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 2641 u8 switch_prio, u8 tclass) 2642 { 2643 MLXSW_REG_ZERO(qtct, payload); 2644 mlxsw_reg_qtct_local_port_set(payload, local_port); 2645 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 2646 mlxsw_reg_qtct_tclass_set(payload, tclass); 2647 } 2648 2649 /* QEEC - QoS ETS Element Configuration Register 2650 * --------------------------------------------- 2651 * Configures the ETS elements. 2652 */ 2653 #define MLXSW_REG_QEEC_ID 0x400D 2654 #define MLXSW_REG_QEEC_LEN 0x1C 2655 2656 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 2657 2658 /* reg_qeec_local_port 2659 * Local port number. 2660 * Access: Index 2661 * 2662 * Note: CPU port is supported. 2663 */ 2664 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 2665 2666 enum mlxsw_reg_qeec_hr { 2667 MLXSW_REG_QEEC_HIERARCY_PORT, 2668 MLXSW_REG_QEEC_HIERARCY_GROUP, 2669 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2670 MLXSW_REG_QEEC_HIERARCY_TC, 2671 }; 2672 2673 /* reg_qeec_element_hierarchy 2674 * 0 - Port 2675 * 1 - Group 2676 * 2 - Subgroup 2677 * 3 - Traffic Class 2678 * Access: Index 2679 */ 2680 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 2681 2682 /* reg_qeec_element_index 2683 * The index of the element in the hierarchy. 2684 * Access: Index 2685 */ 2686 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 2687 2688 /* reg_qeec_next_element_index 2689 * The index of the next (lower) element in the hierarchy. 2690 * Access: RW 2691 * 2692 * Note: Reserved for element_hierarchy 0. 2693 */ 2694 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 2695 2696 enum { 2697 MLXSW_REG_QEEC_BYTES_MODE, 2698 MLXSW_REG_QEEC_PACKETS_MODE, 2699 }; 2700 2701 /* reg_qeec_pb 2702 * Packets or bytes mode. 2703 * 0 - Bytes mode 2704 * 1 - Packets mode 2705 * Access: RW 2706 * 2707 * Note: Used for max shaper configuration. For Spectrum, packets mode 2708 * is supported only for traffic classes of CPU port. 2709 */ 2710 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 2711 2712 /* reg_qeec_mase 2713 * Max shaper configuration enable. Enables configuration of the max 2714 * shaper on this ETS element. 2715 * 0 - Disable 2716 * 1 - Enable 2717 * Access: RW 2718 */ 2719 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 2720 2721 /* A large max rate will disable the max shaper. */ 2722 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 2723 2724 /* reg_qeec_max_shaper_rate 2725 * Max shaper information rate. 2726 * For CPU port, can only be configured for port hierarchy. 2727 * When in bytes mode, value is specified in units of 1000bps. 2728 * Access: RW 2729 */ 2730 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 2731 2732 /* reg_qeec_de 2733 * DWRR configuration enable. Enables configuration of the dwrr and 2734 * dwrr_weight. 2735 * 0 - Disable 2736 * 1 - Enable 2737 * Access: RW 2738 */ 2739 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 2740 2741 /* reg_qeec_dwrr 2742 * Transmission selection algorithm to use on the link going down from 2743 * the ETS element. 2744 * 0 - Strict priority 2745 * 1 - DWRR 2746 * Access: RW 2747 */ 2748 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 2749 2750 /* reg_qeec_dwrr_weight 2751 * DWRR weight on the link going down from the ETS element. The 2752 * percentage of bandwidth guaranteed to an ETS element within 2753 * its hierarchy. The sum of all weights across all ETS elements 2754 * within one hierarchy should be equal to 100. Reserved when 2755 * transmission selection algorithm is strict priority. 2756 * Access: RW 2757 */ 2758 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 2759 2760 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 2761 enum mlxsw_reg_qeec_hr hr, u8 index, 2762 u8 next_index) 2763 { 2764 MLXSW_REG_ZERO(qeec, payload); 2765 mlxsw_reg_qeec_local_port_set(payload, local_port); 2766 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 2767 mlxsw_reg_qeec_element_index_set(payload, index); 2768 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 2769 } 2770 2771 /* PMLP - Ports Module to Local Port Register 2772 * ------------------------------------------ 2773 * Configures the assignment of modules to local ports. 2774 */ 2775 #define MLXSW_REG_PMLP_ID 0x5002 2776 #define MLXSW_REG_PMLP_LEN 0x40 2777 2778 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 2779 2780 /* reg_pmlp_rxtx 2781 * 0 - Tx value is used for both Tx and Rx. 2782 * 1 - Rx value is taken from a separte field. 2783 * Access: RW 2784 */ 2785 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 2786 2787 /* reg_pmlp_local_port 2788 * Local port number. 2789 * Access: Index 2790 */ 2791 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 2792 2793 /* reg_pmlp_width 2794 * 0 - Unmap local port. 2795 * 1 - Lane 0 is used. 2796 * 2 - Lanes 0 and 1 are used. 2797 * 4 - Lanes 0, 1, 2 and 3 are used. 2798 * Access: RW 2799 */ 2800 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 2801 2802 /* reg_pmlp_module 2803 * Module number. 2804 * Access: RW 2805 */ 2806 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 2807 2808 /* reg_pmlp_tx_lane 2809 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 2810 * Access: RW 2811 */ 2812 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 2813 2814 /* reg_pmlp_rx_lane 2815 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 2816 * equal to Tx lane. 2817 * Access: RW 2818 */ 2819 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 2820 2821 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 2822 { 2823 MLXSW_REG_ZERO(pmlp, payload); 2824 mlxsw_reg_pmlp_local_port_set(payload, local_port); 2825 } 2826 2827 /* PMTU - Port MTU Register 2828 * ------------------------ 2829 * Configures and reports the port MTU. 2830 */ 2831 #define MLXSW_REG_PMTU_ID 0x5003 2832 #define MLXSW_REG_PMTU_LEN 0x10 2833 2834 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 2835 2836 /* reg_pmtu_local_port 2837 * Local port number. 2838 * Access: Index 2839 */ 2840 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 2841 2842 /* reg_pmtu_max_mtu 2843 * Maximum MTU. 2844 * When port type (e.g. Ethernet) is configured, the relevant MTU is 2845 * reported, otherwise the minimum between the max_mtu of the different 2846 * types is reported. 2847 * Access: RO 2848 */ 2849 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 2850 2851 /* reg_pmtu_admin_mtu 2852 * MTU value to set port to. Must be smaller or equal to max_mtu. 2853 * Note: If port type is Infiniband, then port must be disabled, when its 2854 * MTU is set. 2855 * Access: RW 2856 */ 2857 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 2858 2859 /* reg_pmtu_oper_mtu 2860 * The actual MTU configured on the port. Packets exceeding this size 2861 * will be dropped. 2862 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 2863 * oper_mtu might be smaller than admin_mtu. 2864 * Access: RO 2865 */ 2866 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 2867 2868 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 2869 u16 new_mtu) 2870 { 2871 MLXSW_REG_ZERO(pmtu, payload); 2872 mlxsw_reg_pmtu_local_port_set(payload, local_port); 2873 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 2874 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 2875 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 2876 } 2877 2878 /* PTYS - Port Type and Speed Register 2879 * ----------------------------------- 2880 * Configures and reports the port speed type. 2881 * 2882 * Note: When set while the link is up, the changes will not take effect 2883 * until the port transitions from down to up state. 2884 */ 2885 #define MLXSW_REG_PTYS_ID 0x5004 2886 #define MLXSW_REG_PTYS_LEN 0x40 2887 2888 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 2889 2890 /* an_disable_admin 2891 * Auto negotiation disable administrative configuration 2892 * 0 - Device doesn't support AN disable. 2893 * 1 - Device supports AN disable. 2894 * Access: RW 2895 */ 2896 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 2897 2898 /* reg_ptys_local_port 2899 * Local port number. 2900 * Access: Index 2901 */ 2902 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 2903 2904 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 2905 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 2906 2907 /* reg_ptys_proto_mask 2908 * Protocol mask. Indicates which protocol is used. 2909 * 0 - Infiniband. 2910 * 1 - Fibre Channel. 2911 * 2 - Ethernet. 2912 * Access: Index 2913 */ 2914 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 2915 2916 enum { 2917 MLXSW_REG_PTYS_AN_STATUS_NA, 2918 MLXSW_REG_PTYS_AN_STATUS_OK, 2919 MLXSW_REG_PTYS_AN_STATUS_FAIL, 2920 }; 2921 2922 /* reg_ptys_an_status 2923 * Autonegotiation status. 2924 * Access: RO 2925 */ 2926 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 2927 2928 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 2929 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 2930 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 2931 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 2932 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 2933 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 2934 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 2935 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 2936 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 2937 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 2938 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 2939 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 2940 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 2941 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 2942 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 2943 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 2944 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 2945 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 2946 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 2947 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 2948 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 2949 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 2950 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 2951 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 2952 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 2953 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 2954 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 2955 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 2956 2957 /* reg_ptys_eth_proto_cap 2958 * Ethernet port supported speeds and protocols. 2959 * Access: RO 2960 */ 2961 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 2962 2963 /* reg_ptys_ib_link_width_cap 2964 * IB port supported widths. 2965 * Access: RO 2966 */ 2967 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 2968 2969 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 2970 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 2971 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 2972 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 2973 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 2974 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 2975 2976 /* reg_ptys_ib_proto_cap 2977 * IB port supported speeds and protocols. 2978 * Access: RO 2979 */ 2980 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 2981 2982 /* reg_ptys_eth_proto_admin 2983 * Speed and protocol to set port to. 2984 * Access: RW 2985 */ 2986 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 2987 2988 /* reg_ptys_ib_link_width_admin 2989 * IB width to set port to. 2990 * Access: RW 2991 */ 2992 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 2993 2994 /* reg_ptys_ib_proto_admin 2995 * IB speeds and protocols to set port to. 2996 * Access: RW 2997 */ 2998 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 2999 3000 /* reg_ptys_eth_proto_oper 3001 * The current speed and protocol configured for the port. 3002 * Access: RO 3003 */ 3004 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 3005 3006 /* reg_ptys_ib_link_width_oper 3007 * The current IB width to set port to. 3008 * Access: RO 3009 */ 3010 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 3011 3012 /* reg_ptys_ib_proto_oper 3013 * The current IB speed and protocol. 3014 * Access: RO 3015 */ 3016 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 3017 3018 /* reg_ptys_eth_proto_lp_advertise 3019 * The protocols that were advertised by the link partner during 3020 * autonegotiation. 3021 * Access: RO 3022 */ 3023 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3024 3025 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3026 u32 proto_admin, bool autoneg) 3027 { 3028 MLXSW_REG_ZERO(ptys, payload); 3029 mlxsw_reg_ptys_local_port_set(payload, local_port); 3030 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 3031 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 3032 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 3033 } 3034 3035 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 3036 u32 *p_eth_proto_cap, 3037 u32 *p_eth_proto_adm, 3038 u32 *p_eth_proto_oper) 3039 { 3040 if (p_eth_proto_cap) 3041 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 3042 if (p_eth_proto_adm) 3043 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 3044 if (p_eth_proto_oper) 3045 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 3046 } 3047 3048 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 3049 u16 proto_admin, u16 link_width) 3050 { 3051 MLXSW_REG_ZERO(ptys, payload); 3052 mlxsw_reg_ptys_local_port_set(payload, local_port); 3053 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 3054 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 3055 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 3056 } 3057 3058 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 3059 u16 *p_ib_link_width_cap, 3060 u16 *p_ib_proto_oper, 3061 u16 *p_ib_link_width_oper) 3062 { 3063 if (p_ib_proto_cap) 3064 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 3065 if (p_ib_link_width_cap) 3066 *p_ib_link_width_cap = 3067 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 3068 if (p_ib_proto_oper) 3069 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 3070 if (p_ib_link_width_oper) 3071 *p_ib_link_width_oper = 3072 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 3073 } 3074 3075 /* PPAD - Port Physical Address Register 3076 * ------------------------------------- 3077 * The PPAD register configures the per port physical MAC address. 3078 */ 3079 #define MLXSW_REG_PPAD_ID 0x5005 3080 #define MLXSW_REG_PPAD_LEN 0x10 3081 3082 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 3083 3084 /* reg_ppad_single_base_mac 3085 * 0: base_mac, local port should be 0 and mac[7:0] is 3086 * reserved. HW will set incremental 3087 * 1: single_mac - mac of the local_port 3088 * Access: RW 3089 */ 3090 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 3091 3092 /* reg_ppad_local_port 3093 * port number, if single_base_mac = 0 then local_port is reserved 3094 * Access: RW 3095 */ 3096 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 3097 3098 /* reg_ppad_mac 3099 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 3100 * If single_base_mac = 1 - the per port MAC address 3101 * Access: RW 3102 */ 3103 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 3104 3105 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 3106 u8 local_port) 3107 { 3108 MLXSW_REG_ZERO(ppad, payload); 3109 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 3110 mlxsw_reg_ppad_local_port_set(payload, local_port); 3111 } 3112 3113 /* PAOS - Ports Administrative and Operational Status Register 3114 * ----------------------------------------------------------- 3115 * Configures and retrieves per port administrative and operational status. 3116 */ 3117 #define MLXSW_REG_PAOS_ID 0x5006 3118 #define MLXSW_REG_PAOS_LEN 0x10 3119 3120 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 3121 3122 /* reg_paos_swid 3123 * Switch partition ID with which to associate the port. 3124 * Note: while external ports uses unique local port numbers (and thus swid is 3125 * redundant), router ports use the same local port number where swid is the 3126 * only indication for the relevant port. 3127 * Access: Index 3128 */ 3129 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 3130 3131 /* reg_paos_local_port 3132 * Local port number. 3133 * Access: Index 3134 */ 3135 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 3136 3137 /* reg_paos_admin_status 3138 * Port administrative state (the desired state of the port): 3139 * 1 - Up. 3140 * 2 - Down. 3141 * 3 - Up once. This means that in case of link failure, the port won't go 3142 * into polling mode, but will wait to be re-enabled by software. 3143 * 4 - Disabled by system. Can only be set by hardware. 3144 * Access: RW 3145 */ 3146 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 3147 3148 /* reg_paos_oper_status 3149 * Port operational state (the current state): 3150 * 1 - Up. 3151 * 2 - Down. 3152 * 3 - Down by port failure. This means that the device will not let the 3153 * port up again until explicitly specified by software. 3154 * Access: RO 3155 */ 3156 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 3157 3158 /* reg_paos_ase 3159 * Admin state update enabled. 3160 * Access: WO 3161 */ 3162 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 3163 3164 /* reg_paos_ee 3165 * Event update enable. If this bit is set, event generation will be 3166 * updated based on the e field. 3167 * Access: WO 3168 */ 3169 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 3170 3171 /* reg_paos_e 3172 * Event generation on operational state change: 3173 * 0 - Do not generate event. 3174 * 1 - Generate Event. 3175 * 2 - Generate Single Event. 3176 * Access: RW 3177 */ 3178 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 3179 3180 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 3181 enum mlxsw_port_admin_status status) 3182 { 3183 MLXSW_REG_ZERO(paos, payload); 3184 mlxsw_reg_paos_swid_set(payload, 0); 3185 mlxsw_reg_paos_local_port_set(payload, local_port); 3186 mlxsw_reg_paos_admin_status_set(payload, status); 3187 mlxsw_reg_paos_oper_status_set(payload, 0); 3188 mlxsw_reg_paos_ase_set(payload, 1); 3189 mlxsw_reg_paos_ee_set(payload, 1); 3190 mlxsw_reg_paos_e_set(payload, 1); 3191 } 3192 3193 /* PFCC - Ports Flow Control Configuration Register 3194 * ------------------------------------------------ 3195 * Configures and retrieves the per port flow control configuration. 3196 */ 3197 #define MLXSW_REG_PFCC_ID 0x5007 3198 #define MLXSW_REG_PFCC_LEN 0x20 3199 3200 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 3201 3202 /* reg_pfcc_local_port 3203 * Local port number. 3204 * Access: Index 3205 */ 3206 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 3207 3208 /* reg_pfcc_pnat 3209 * Port number access type. Determines the way local_port is interpreted: 3210 * 0 - Local port number. 3211 * 1 - IB / label port number. 3212 * Access: Index 3213 */ 3214 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 3215 3216 /* reg_pfcc_shl_cap 3217 * Send to higher layers capabilities: 3218 * 0 - No capability of sending Pause and PFC frames to higher layers. 3219 * 1 - Device has capability of sending Pause and PFC frames to higher 3220 * layers. 3221 * Access: RO 3222 */ 3223 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 3224 3225 /* reg_pfcc_shl_opr 3226 * Send to higher layers operation: 3227 * 0 - Pause and PFC frames are handled by the port (default). 3228 * 1 - Pause and PFC frames are handled by the port and also sent to 3229 * higher layers. Only valid if shl_cap = 1. 3230 * Access: RW 3231 */ 3232 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 3233 3234 /* reg_pfcc_ppan 3235 * Pause policy auto negotiation. 3236 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 3237 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 3238 * based on the auto-negotiation resolution. 3239 * Access: RW 3240 * 3241 * Note: The auto-negotiation advertisement is set according to pptx and 3242 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 3243 */ 3244 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 3245 3246 /* reg_pfcc_prio_mask_tx 3247 * Bit per priority indicating if Tx flow control policy should be 3248 * updated based on bit pfctx. 3249 * Access: WO 3250 */ 3251 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 3252 3253 /* reg_pfcc_prio_mask_rx 3254 * Bit per priority indicating if Rx flow control policy should be 3255 * updated based on bit pfcrx. 3256 * Access: WO 3257 */ 3258 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 3259 3260 /* reg_pfcc_pptx 3261 * Admin Pause policy on Tx. 3262 * 0 - Never generate Pause frames (default). 3263 * 1 - Generate Pause frames according to Rx buffer threshold. 3264 * Access: RW 3265 */ 3266 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 3267 3268 /* reg_pfcc_aptx 3269 * Active (operational) Pause policy on Tx. 3270 * 0 - Never generate Pause frames. 3271 * 1 - Generate Pause frames according to Rx buffer threshold. 3272 * Access: RO 3273 */ 3274 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 3275 3276 /* reg_pfcc_pfctx 3277 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 3278 * 0 - Never generate priority Pause frames on the specified priority 3279 * (default). 3280 * 1 - Generate priority Pause frames according to Rx buffer threshold on 3281 * the specified priority. 3282 * Access: RW 3283 * 3284 * Note: pfctx and pptx must be mutually exclusive. 3285 */ 3286 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 3287 3288 /* reg_pfcc_pprx 3289 * Admin Pause policy on Rx. 3290 * 0 - Ignore received Pause frames (default). 3291 * 1 - Respect received Pause frames. 3292 * Access: RW 3293 */ 3294 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 3295 3296 /* reg_pfcc_aprx 3297 * Active (operational) Pause policy on Rx. 3298 * 0 - Ignore received Pause frames. 3299 * 1 - Respect received Pause frames. 3300 * Access: RO 3301 */ 3302 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 3303 3304 /* reg_pfcc_pfcrx 3305 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 3306 * 0 - Ignore incoming priority Pause frames on the specified priority 3307 * (default). 3308 * 1 - Respect incoming priority Pause frames on the specified priority. 3309 * Access: RW 3310 */ 3311 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 3312 3313 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 3314 3315 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 3316 { 3317 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3318 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3319 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 3320 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 3321 } 3322 3323 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 3324 { 3325 MLXSW_REG_ZERO(pfcc, payload); 3326 mlxsw_reg_pfcc_local_port_set(payload, local_port); 3327 } 3328 3329 /* PPCNT - Ports Performance Counters Register 3330 * ------------------------------------------- 3331 * The PPCNT register retrieves per port performance counters. 3332 */ 3333 #define MLXSW_REG_PPCNT_ID 0x5008 3334 #define MLXSW_REG_PPCNT_LEN 0x100 3335 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 3336 3337 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 3338 3339 /* reg_ppcnt_swid 3340 * For HCA: must be always 0. 3341 * Switch partition ID to associate port with. 3342 * Switch partitions are numbered from 0 to 7 inclusively. 3343 * Switch partition 254 indicates stacking ports. 3344 * Switch partition 255 indicates all switch partitions. 3345 * Only valid on Set() operation with local_port=255. 3346 * Access: Index 3347 */ 3348 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 3349 3350 /* reg_ppcnt_local_port 3351 * Local port number. 3352 * 255 indicates all ports on the device, and is only allowed 3353 * for Set() operation. 3354 * Access: Index 3355 */ 3356 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 3357 3358 /* reg_ppcnt_pnat 3359 * Port number access type: 3360 * 0 - Local port number 3361 * 1 - IB port number 3362 * Access: Index 3363 */ 3364 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 3365 3366 enum mlxsw_reg_ppcnt_grp { 3367 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 3368 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 3369 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 3370 MLXSW_REG_PPCNT_TC_CNT = 0x11, 3371 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 3372 }; 3373 3374 /* reg_ppcnt_grp 3375 * Performance counter group. 3376 * Group 63 indicates all groups. Only valid on Set() operation with 3377 * clr bit set. 3378 * 0x0: IEEE 802.3 Counters 3379 * 0x1: RFC 2863 Counters 3380 * 0x2: RFC 2819 Counters 3381 * 0x3: RFC 3635 Counters 3382 * 0x5: Ethernet Extended Counters 3383 * 0x8: Link Level Retransmission Counters 3384 * 0x10: Per Priority Counters 3385 * 0x11: Per Traffic Class Counters 3386 * 0x12: Physical Layer Counters 3387 * 0x13: Per Traffic Class Congestion Counters 3388 * Access: Index 3389 */ 3390 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 3391 3392 /* reg_ppcnt_clr 3393 * Clear counters. Setting the clr bit will reset the counter value 3394 * for all counters in the counter group. This bit can be set 3395 * for both Set() and Get() operation. 3396 * Access: OP 3397 */ 3398 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 3399 3400 /* reg_ppcnt_prio_tc 3401 * Priority for counter set that support per priority, valid values: 0-7. 3402 * Traffic class for counter set that support per traffic class, 3403 * valid values: 0- cap_max_tclass-1 . 3404 * For HCA: cap_max_tclass is always 8. 3405 * Otherwise must be 0. 3406 * Access: Index 3407 */ 3408 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 3409 3410 /* Ethernet IEEE 802.3 Counter Group */ 3411 3412 /* reg_ppcnt_a_frames_transmitted_ok 3413 * Access: RO 3414 */ 3415 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 3416 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3417 3418 /* reg_ppcnt_a_frames_received_ok 3419 * Access: RO 3420 */ 3421 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 3422 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3423 3424 /* reg_ppcnt_a_frame_check_sequence_errors 3425 * Access: RO 3426 */ 3427 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 3428 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 3429 3430 /* reg_ppcnt_a_alignment_errors 3431 * Access: RO 3432 */ 3433 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 3434 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 3435 3436 /* reg_ppcnt_a_octets_transmitted_ok 3437 * Access: RO 3438 */ 3439 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 3440 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3441 3442 /* reg_ppcnt_a_octets_received_ok 3443 * Access: RO 3444 */ 3445 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 3446 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3447 3448 /* reg_ppcnt_a_multicast_frames_xmitted_ok 3449 * Access: RO 3450 */ 3451 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 3452 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 3453 3454 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 3455 * Access: RO 3456 */ 3457 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 3458 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 3459 3460 /* reg_ppcnt_a_multicast_frames_received_ok 3461 * Access: RO 3462 */ 3463 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 3464 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 3465 3466 /* reg_ppcnt_a_broadcast_frames_received_ok 3467 * Access: RO 3468 */ 3469 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 3470 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3471 3472 /* reg_ppcnt_a_in_range_length_errors 3473 * Access: RO 3474 */ 3475 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 3476 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3477 3478 /* reg_ppcnt_a_out_of_range_length_field 3479 * Access: RO 3480 */ 3481 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 3482 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3483 3484 /* reg_ppcnt_a_frame_too_long_errors 3485 * Access: RO 3486 */ 3487 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 3488 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3489 3490 /* reg_ppcnt_a_symbol_error_during_carrier 3491 * Access: RO 3492 */ 3493 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 3494 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3495 3496 /* reg_ppcnt_a_mac_control_frames_transmitted 3497 * Access: RO 3498 */ 3499 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 3500 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3501 3502 /* reg_ppcnt_a_mac_control_frames_received 3503 * Access: RO 3504 */ 3505 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 3506 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 3507 3508 /* reg_ppcnt_a_unsupported_opcodes_received 3509 * Access: RO 3510 */ 3511 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 3512 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 3513 3514 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 3515 * Access: RO 3516 */ 3517 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 3518 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 3519 3520 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 3521 * Access: RO 3522 */ 3523 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 3524 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 3525 3526 /* Ethernet Extended Counter Group Counters */ 3527 3528 /* reg_ppcnt_ecn_marked 3529 * Access: RO 3530 */ 3531 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 3532 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3533 3534 /* Ethernet Per Priority Group Counters */ 3535 3536 /* reg_ppcnt_rx_octets 3537 * Access: RO 3538 */ 3539 MLXSW_ITEM64(reg, ppcnt, rx_octets, 3540 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3541 3542 /* reg_ppcnt_rx_frames 3543 * Access: RO 3544 */ 3545 MLXSW_ITEM64(reg, ppcnt, rx_frames, 3546 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3547 3548 /* reg_ppcnt_tx_octets 3549 * Access: RO 3550 */ 3551 MLXSW_ITEM64(reg, ppcnt, tx_octets, 3552 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3553 3554 /* reg_ppcnt_tx_frames 3555 * Access: RO 3556 */ 3557 MLXSW_ITEM64(reg, ppcnt, tx_frames, 3558 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3559 3560 /* reg_ppcnt_rx_pause 3561 * Access: RO 3562 */ 3563 MLXSW_ITEM64(reg, ppcnt, rx_pause, 3564 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3565 3566 /* reg_ppcnt_rx_pause_duration 3567 * Access: RO 3568 */ 3569 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 3570 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3571 3572 /* reg_ppcnt_tx_pause 3573 * Access: RO 3574 */ 3575 MLXSW_ITEM64(reg, ppcnt, tx_pause, 3576 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3577 3578 /* reg_ppcnt_tx_pause_duration 3579 * Access: RO 3580 */ 3581 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 3582 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3583 3584 /* reg_ppcnt_rx_pause_transition 3585 * Access: RO 3586 */ 3587 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 3588 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3589 3590 /* Ethernet Per Traffic Group Counters */ 3591 3592 /* reg_ppcnt_tc_transmit_queue 3593 * Contains the transmit queue depth in cells of traffic class 3594 * selected by prio_tc and the port selected by local_port. 3595 * The field cannot be cleared. 3596 * Access: RO 3597 */ 3598 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 3599 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3600 3601 /* reg_ppcnt_tc_no_buffer_discard_uc 3602 * The number of unicast packets dropped due to lack of shared 3603 * buffer resources. 3604 * Access: RO 3605 */ 3606 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 3607 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3608 3609 /* Ethernet Per Traffic Class Congestion Group Counters */ 3610 3611 /* reg_ppcnt_wred_discard 3612 * Access: RO 3613 */ 3614 MLXSW_ITEM64(reg, ppcnt, wred_discard, 3615 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3616 3617 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 3618 enum mlxsw_reg_ppcnt_grp grp, 3619 u8 prio_tc) 3620 { 3621 MLXSW_REG_ZERO(ppcnt, payload); 3622 mlxsw_reg_ppcnt_swid_set(payload, 0); 3623 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 3624 mlxsw_reg_ppcnt_pnat_set(payload, 0); 3625 mlxsw_reg_ppcnt_grp_set(payload, grp); 3626 mlxsw_reg_ppcnt_clr_set(payload, 0); 3627 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 3628 } 3629 3630 /* PLIB - Port Local to InfiniBand Port 3631 * ------------------------------------ 3632 * The PLIB register performs mapping from Local Port into InfiniBand Port. 3633 */ 3634 #define MLXSW_REG_PLIB_ID 0x500A 3635 #define MLXSW_REG_PLIB_LEN 0x10 3636 3637 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 3638 3639 /* reg_plib_local_port 3640 * Local port number. 3641 * Access: Index 3642 */ 3643 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 3644 3645 /* reg_plib_ib_port 3646 * InfiniBand port remapping for local_port. 3647 * Access: RW 3648 */ 3649 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 3650 3651 /* PPTB - Port Prio To Buffer Register 3652 * ----------------------------------- 3653 * Configures the switch priority to buffer table. 3654 */ 3655 #define MLXSW_REG_PPTB_ID 0x500B 3656 #define MLXSW_REG_PPTB_LEN 0x10 3657 3658 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 3659 3660 enum { 3661 MLXSW_REG_PPTB_MM_UM, 3662 MLXSW_REG_PPTB_MM_UNICAST, 3663 MLXSW_REG_PPTB_MM_MULTICAST, 3664 }; 3665 3666 /* reg_pptb_mm 3667 * Mapping mode. 3668 * 0 - Map both unicast and multicast packets to the same buffer. 3669 * 1 - Map only unicast packets. 3670 * 2 - Map only multicast packets. 3671 * Access: Index 3672 * 3673 * Note: SwitchX-2 only supports the first option. 3674 */ 3675 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 3676 3677 /* reg_pptb_local_port 3678 * Local port number. 3679 * Access: Index 3680 */ 3681 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 3682 3683 /* reg_pptb_um 3684 * Enables the update of the untagged_buf field. 3685 * Access: RW 3686 */ 3687 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 3688 3689 /* reg_pptb_pm 3690 * Enables the update of the prio_to_buff field. 3691 * Bit <i> is a flag for updating the mapping for switch priority <i>. 3692 * Access: RW 3693 */ 3694 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 3695 3696 /* reg_pptb_prio_to_buff 3697 * Mapping of switch priority <i> to one of the allocated receive port 3698 * buffers. 3699 * Access: RW 3700 */ 3701 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 3702 3703 /* reg_pptb_pm_msb 3704 * Enables the update of the prio_to_buff field. 3705 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 3706 * Access: RW 3707 */ 3708 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 3709 3710 /* reg_pptb_untagged_buff 3711 * Mapping of untagged frames to one of the allocated receive port buffers. 3712 * Access: RW 3713 * 3714 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 3715 * Spectrum, as it maps untagged packets based on the default switch priority. 3716 */ 3717 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 3718 3719 /* reg_pptb_prio_to_buff_msb 3720 * Mapping of switch priority <i+8> to one of the allocated receive port 3721 * buffers. 3722 * Access: RW 3723 */ 3724 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 3725 3726 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 3727 3728 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 3729 { 3730 MLXSW_REG_ZERO(pptb, payload); 3731 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 3732 mlxsw_reg_pptb_local_port_set(payload, local_port); 3733 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3734 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3735 } 3736 3737 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 3738 u8 buff) 3739 { 3740 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 3741 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 3742 } 3743 3744 /* PBMC - Port Buffer Management Control Register 3745 * ---------------------------------------------- 3746 * The PBMC register configures and retrieves the port packet buffer 3747 * allocation for different Prios, and the Pause threshold management. 3748 */ 3749 #define MLXSW_REG_PBMC_ID 0x500C 3750 #define MLXSW_REG_PBMC_LEN 0x6C 3751 3752 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 3753 3754 /* reg_pbmc_local_port 3755 * Local port number. 3756 * Access: Index 3757 */ 3758 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 3759 3760 /* reg_pbmc_xoff_timer_value 3761 * When device generates a pause frame, it uses this value as the pause 3762 * timer (time for the peer port to pause in quota-512 bit time). 3763 * Access: RW 3764 */ 3765 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 3766 3767 /* reg_pbmc_xoff_refresh 3768 * The time before a new pause frame should be sent to refresh the pause RW 3769 * state. Using the same units as xoff_timer_value above (in quota-512 bit 3770 * time). 3771 * Access: RW 3772 */ 3773 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 3774 3775 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 3776 3777 /* reg_pbmc_buf_lossy 3778 * The field indicates if the buffer is lossy. 3779 * 0 - Lossless 3780 * 1 - Lossy 3781 * Access: RW 3782 */ 3783 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 3784 3785 /* reg_pbmc_buf_epsb 3786 * Eligible for Port Shared buffer. 3787 * If epsb is set, packets assigned to buffer are allowed to insert the port 3788 * shared buffer. 3789 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 3790 * Access: RW 3791 */ 3792 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 3793 3794 /* reg_pbmc_buf_size 3795 * The part of the packet buffer array is allocated for the specific buffer. 3796 * Units are represented in cells. 3797 * Access: RW 3798 */ 3799 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 3800 3801 /* reg_pbmc_buf_xoff_threshold 3802 * Once the amount of data in the buffer goes above this value, device 3803 * starts sending PFC frames for all priorities associated with the 3804 * buffer. Units are represented in cells. Reserved in case of lossy 3805 * buffer. 3806 * Access: RW 3807 * 3808 * Note: In Spectrum, reserved for buffer[9]. 3809 */ 3810 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 3811 0x08, 0x04, false); 3812 3813 /* reg_pbmc_buf_xon_threshold 3814 * When the amount of data in the buffer goes below this value, device 3815 * stops sending PFC frames for the priorities associated with the 3816 * buffer. Units are represented in cells. Reserved in case of lossy 3817 * buffer. 3818 * Access: RW 3819 * 3820 * Note: In Spectrum, reserved for buffer[9]. 3821 */ 3822 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 3823 0x08, 0x04, false); 3824 3825 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 3826 u16 xoff_timer_value, u16 xoff_refresh) 3827 { 3828 MLXSW_REG_ZERO(pbmc, payload); 3829 mlxsw_reg_pbmc_local_port_set(payload, local_port); 3830 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 3831 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 3832 } 3833 3834 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 3835 int buf_index, 3836 u16 size) 3837 { 3838 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 3839 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3840 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3841 } 3842 3843 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 3844 int buf_index, u16 size, 3845 u16 threshold) 3846 { 3847 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 3848 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3849 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3850 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 3851 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 3852 } 3853 3854 /* PSPA - Port Switch Partition Allocation 3855 * --------------------------------------- 3856 * Controls the association of a port with a switch partition and enables 3857 * configuring ports as stacking ports. 3858 */ 3859 #define MLXSW_REG_PSPA_ID 0x500D 3860 #define MLXSW_REG_PSPA_LEN 0x8 3861 3862 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 3863 3864 /* reg_pspa_swid 3865 * Switch partition ID. 3866 * Access: RW 3867 */ 3868 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 3869 3870 /* reg_pspa_local_port 3871 * Local port number. 3872 * Access: Index 3873 */ 3874 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 3875 3876 /* reg_pspa_sub_port 3877 * Virtual port within the local port. Set to 0 when virtual ports are 3878 * disabled on the local port. 3879 * Access: Index 3880 */ 3881 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 3882 3883 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 3884 { 3885 MLXSW_REG_ZERO(pspa, payload); 3886 mlxsw_reg_pspa_swid_set(payload, swid); 3887 mlxsw_reg_pspa_local_port_set(payload, local_port); 3888 mlxsw_reg_pspa_sub_port_set(payload, 0); 3889 } 3890 3891 /* HTGT - Host Trap Group Table 3892 * ---------------------------- 3893 * Configures the properties for forwarding to CPU. 3894 */ 3895 #define MLXSW_REG_HTGT_ID 0x7002 3896 #define MLXSW_REG_HTGT_LEN 0x20 3897 3898 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 3899 3900 /* reg_htgt_swid 3901 * Switch partition ID. 3902 * Access: Index 3903 */ 3904 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 3905 3906 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 3907 3908 /* reg_htgt_type 3909 * CPU path type. 3910 * Access: RW 3911 */ 3912 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 3913 3914 enum mlxsw_reg_htgt_trap_group { 3915 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3916 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 3917 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 3918 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 3919 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 3920 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 3921 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 3922 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 3923 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 3924 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 3925 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 3926 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 3927 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 3928 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 3929 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 3930 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 3931 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 3932 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 3933 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 3934 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 3935 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 3936 }; 3937 3938 /* reg_htgt_trap_group 3939 * Trap group number. User defined number specifying which trap groups 3940 * should be forwarded to the CPU. The mapping between trap IDs and trap 3941 * groups is configured using HPKT register. 3942 * Access: Index 3943 */ 3944 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 3945 3946 enum { 3947 MLXSW_REG_HTGT_POLICER_DISABLE, 3948 MLXSW_REG_HTGT_POLICER_ENABLE, 3949 }; 3950 3951 /* reg_htgt_pide 3952 * Enable policer ID specified using 'pid' field. 3953 * Access: RW 3954 */ 3955 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 3956 3957 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 3958 3959 /* reg_htgt_pid 3960 * Policer ID for the trap group. 3961 * Access: RW 3962 */ 3963 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 3964 3965 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 3966 3967 /* reg_htgt_mirror_action 3968 * Mirror action to use. 3969 * 0 - Trap to CPU. 3970 * 1 - Trap to CPU and mirror to a mirroring agent. 3971 * 2 - Mirror to a mirroring agent and do not trap to CPU. 3972 * Access: RW 3973 * 3974 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 3975 */ 3976 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 3977 3978 /* reg_htgt_mirroring_agent 3979 * Mirroring agent. 3980 * Access: RW 3981 */ 3982 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 3983 3984 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 3985 3986 /* reg_htgt_priority 3987 * Trap group priority. 3988 * In case a packet matches multiple classification rules, the packet will 3989 * only be trapped once, based on the trap ID associated with the group (via 3990 * register HPKT) with the highest priority. 3991 * Supported values are 0-7, with 7 represnting the highest priority. 3992 * Access: RW 3993 * 3994 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 3995 * by the 'trap_group' field. 3996 */ 3997 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 3998 3999 #define MLXSW_REG_HTGT_DEFAULT_TC 7 4000 4001 /* reg_htgt_local_path_cpu_tclass 4002 * CPU ingress traffic class for the trap group. 4003 * Access: RW 4004 */ 4005 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 4006 4007 enum mlxsw_reg_htgt_local_path_rdq { 4008 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 4009 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 4010 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 4011 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 4012 }; 4013 /* reg_htgt_local_path_rdq 4014 * Receive descriptor queue (RDQ) to use for the trap group. 4015 * Access: RW 4016 */ 4017 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 4018 4019 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 4020 u8 priority, u8 tc) 4021 { 4022 MLXSW_REG_ZERO(htgt, payload); 4023 4024 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 4025 mlxsw_reg_htgt_pide_set(payload, 4026 MLXSW_REG_HTGT_POLICER_DISABLE); 4027 } else { 4028 mlxsw_reg_htgt_pide_set(payload, 4029 MLXSW_REG_HTGT_POLICER_ENABLE); 4030 mlxsw_reg_htgt_pid_set(payload, policer_id); 4031 } 4032 4033 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 4034 mlxsw_reg_htgt_trap_group_set(payload, group); 4035 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 4036 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 4037 mlxsw_reg_htgt_priority_set(payload, priority); 4038 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 4039 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 4040 } 4041 4042 /* HPKT - Host Packet Trap 4043 * ----------------------- 4044 * Configures trap IDs inside trap groups. 4045 */ 4046 #define MLXSW_REG_HPKT_ID 0x7003 4047 #define MLXSW_REG_HPKT_LEN 0x10 4048 4049 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 4050 4051 enum { 4052 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 4053 MLXSW_REG_HPKT_ACK_REQUIRED, 4054 }; 4055 4056 /* reg_hpkt_ack 4057 * Require acknowledgements from the host for events. 4058 * If set, then the device will wait for the event it sent to be acknowledged 4059 * by the host. This option is only relevant for event trap IDs. 4060 * Access: RW 4061 * 4062 * Note: Currently not supported by firmware. 4063 */ 4064 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 4065 4066 enum mlxsw_reg_hpkt_action { 4067 MLXSW_REG_HPKT_ACTION_FORWARD, 4068 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 4069 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 4070 MLXSW_REG_HPKT_ACTION_DISCARD, 4071 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 4072 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 4073 }; 4074 4075 /* reg_hpkt_action 4076 * Action to perform on packet when trapped. 4077 * 0 - No action. Forward to CPU based on switching rules. 4078 * 1 - Trap to CPU (CPU receives sole copy). 4079 * 2 - Mirror to CPU (CPU receives a replica of the packet). 4080 * 3 - Discard. 4081 * 4 - Soft discard (allow other traps to act on the packet). 4082 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 4083 * Access: RW 4084 * 4085 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 4086 * addressed to the CPU. 4087 */ 4088 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 4089 4090 /* reg_hpkt_trap_group 4091 * Trap group to associate the trap with. 4092 * Access: RW 4093 */ 4094 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 4095 4096 /* reg_hpkt_trap_id 4097 * Trap ID. 4098 * Access: Index 4099 * 4100 * Note: A trap ID can only be associated with a single trap group. The device 4101 * will associate the trap ID with the last trap group configured. 4102 */ 4103 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 4104 4105 enum { 4106 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 4107 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 4108 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 4109 }; 4110 4111 /* reg_hpkt_ctrl 4112 * Configure dedicated buffer resources for control packets. 4113 * Ignored by SwitchX-2. 4114 * 0 - Keep factory defaults. 4115 * 1 - Do not use control buffer for this trap ID. 4116 * 2 - Use control buffer for this trap ID. 4117 * Access: RW 4118 */ 4119 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 4120 4121 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 4122 enum mlxsw_reg_htgt_trap_group trap_group, 4123 bool is_ctrl) 4124 { 4125 MLXSW_REG_ZERO(hpkt, payload); 4126 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 4127 mlxsw_reg_hpkt_action_set(payload, action); 4128 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 4129 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 4130 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 4131 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 4132 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 4133 } 4134 4135 /* RGCR - Router General Configuration Register 4136 * -------------------------------------------- 4137 * The register is used for setting up the router configuration. 4138 */ 4139 #define MLXSW_REG_RGCR_ID 0x8001 4140 #define MLXSW_REG_RGCR_LEN 0x28 4141 4142 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 4143 4144 /* reg_rgcr_ipv4_en 4145 * IPv4 router enable. 4146 * Access: RW 4147 */ 4148 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 4149 4150 /* reg_rgcr_ipv6_en 4151 * IPv6 router enable. 4152 * Access: RW 4153 */ 4154 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 4155 4156 /* reg_rgcr_max_router_interfaces 4157 * Defines the maximum number of active router interfaces for all virtual 4158 * routers. 4159 * Access: RW 4160 */ 4161 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 4162 4163 /* reg_rgcr_usp 4164 * Update switch priority and packet color. 4165 * 0 - Preserve the value of Switch Priority and packet color. 4166 * 1 - Recalculate the value of Switch Priority and packet color. 4167 * Access: RW 4168 * 4169 * Note: Not supported by SwitchX and SwitchX-2. 4170 */ 4171 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 4172 4173 /* reg_rgcr_pcp_rw 4174 * Indicates how to handle the pcp_rewrite_en value: 4175 * 0 - Preserve the value of pcp_rewrite_en. 4176 * 2 - Disable PCP rewrite. 4177 * 3 - Enable PCP rewrite. 4178 * Access: RW 4179 * 4180 * Note: Not supported by SwitchX and SwitchX-2. 4181 */ 4182 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 4183 4184 /* reg_rgcr_activity_dis 4185 * Activity disable: 4186 * 0 - Activity will be set when an entry is hit (default). 4187 * 1 - Activity will not be set when an entry is hit. 4188 * 4189 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 4190 * (RALUE). 4191 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 4192 * Entry (RAUHT). 4193 * Bits 2:7 are reserved. 4194 * Access: RW 4195 * 4196 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 4197 */ 4198 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 4199 4200 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 4201 bool ipv6_en) 4202 { 4203 MLXSW_REG_ZERO(rgcr, payload); 4204 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 4205 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 4206 } 4207 4208 /* RITR - Router Interface Table Register 4209 * -------------------------------------- 4210 * The register is used to configure the router interface table. 4211 */ 4212 #define MLXSW_REG_RITR_ID 0x8002 4213 #define MLXSW_REG_RITR_LEN 0x40 4214 4215 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 4216 4217 /* reg_ritr_enable 4218 * Enables routing on the router interface. 4219 * Access: RW 4220 */ 4221 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 4222 4223 /* reg_ritr_ipv4 4224 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 4225 * interface. 4226 * Access: RW 4227 */ 4228 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 4229 4230 /* reg_ritr_ipv6 4231 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 4232 * interface. 4233 * Access: RW 4234 */ 4235 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 4236 4237 /* reg_ritr_ipv4_mc 4238 * IPv4 multicast routing enable. 4239 * Access: RW 4240 */ 4241 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 4242 4243 /* reg_ritr_ipv6_mc 4244 * IPv6 multicast routing enable. 4245 * Access: RW 4246 */ 4247 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 4248 4249 enum mlxsw_reg_ritr_if_type { 4250 /* VLAN interface. */ 4251 MLXSW_REG_RITR_VLAN_IF, 4252 /* FID interface. */ 4253 MLXSW_REG_RITR_FID_IF, 4254 /* Sub-port interface. */ 4255 MLXSW_REG_RITR_SP_IF, 4256 /* Loopback Interface. */ 4257 MLXSW_REG_RITR_LOOPBACK_IF, 4258 }; 4259 4260 /* reg_ritr_type 4261 * Router interface type as per enum mlxsw_reg_ritr_if_type. 4262 * Access: RW 4263 */ 4264 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 4265 4266 enum { 4267 MLXSW_REG_RITR_RIF_CREATE, 4268 MLXSW_REG_RITR_RIF_DEL, 4269 }; 4270 4271 /* reg_ritr_op 4272 * Opcode: 4273 * 0 - Create or edit RIF. 4274 * 1 - Delete RIF. 4275 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 4276 * is not supported. An interface must be deleted and re-created in order 4277 * to update properties. 4278 * Access: WO 4279 */ 4280 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 4281 4282 /* reg_ritr_rif 4283 * Router interface index. A pointer to the Router Interface Table. 4284 * Access: Index 4285 */ 4286 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 4287 4288 /* reg_ritr_ipv4_fe 4289 * IPv4 Forwarding Enable. 4290 * Enables routing of IPv4 traffic on the router interface. When disabled, 4291 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4292 * Not supported in SwitchX-2. 4293 * Access: RW 4294 */ 4295 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 4296 4297 /* reg_ritr_ipv6_fe 4298 * IPv6 Forwarding Enable. 4299 * Enables routing of IPv6 traffic on the router interface. When disabled, 4300 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4301 * Not supported in SwitchX-2. 4302 * Access: RW 4303 */ 4304 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 4305 4306 /* reg_ritr_ipv4_mc_fe 4307 * IPv4 Multicast Forwarding Enable. 4308 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4309 * will be enabled. 4310 * Access: RW 4311 */ 4312 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 4313 4314 /* reg_ritr_ipv6_mc_fe 4315 * IPv6 Multicast Forwarding Enable. 4316 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4317 * will be enabled. 4318 * Access: RW 4319 */ 4320 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 4321 4322 /* reg_ritr_lb_en 4323 * Loop-back filter enable for unicast packets. 4324 * If the flag is set then loop-back filter for unicast packets is 4325 * implemented on the RIF. Multicast packets are always subject to 4326 * loop-back filtering. 4327 * Access: RW 4328 */ 4329 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 4330 4331 /* reg_ritr_virtual_router 4332 * Virtual router ID associated with the router interface. 4333 * Access: RW 4334 */ 4335 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 4336 4337 /* reg_ritr_mtu 4338 * Router interface MTU. 4339 * Access: RW 4340 */ 4341 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 4342 4343 /* reg_ritr_if_swid 4344 * Switch partition ID. 4345 * Access: RW 4346 */ 4347 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 4348 4349 /* reg_ritr_if_mac 4350 * Router interface MAC address. 4351 * In Spectrum, all MAC addresses must have the same 38 MSBits. 4352 * Access: RW 4353 */ 4354 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 4355 4356 /* reg_ritr_if_vrrp_id_ipv6 4357 * VRRP ID for IPv6 4358 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 4359 * Access: RW 4360 */ 4361 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 4362 4363 /* reg_ritr_if_vrrp_id_ipv4 4364 * VRRP ID for IPv4 4365 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 4366 * Access: RW 4367 */ 4368 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 4369 4370 /* VLAN Interface */ 4371 4372 /* reg_ritr_vlan_if_vid 4373 * VLAN ID. 4374 * Access: RW 4375 */ 4376 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 4377 4378 /* FID Interface */ 4379 4380 /* reg_ritr_fid_if_fid 4381 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 4382 * the vFID range are supported. 4383 * Access: RW 4384 */ 4385 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 4386 4387 static inline void mlxsw_reg_ritr_fid_set(char *payload, 4388 enum mlxsw_reg_ritr_if_type rif_type, 4389 u16 fid) 4390 { 4391 if (rif_type == MLXSW_REG_RITR_FID_IF) 4392 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 4393 else 4394 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 4395 } 4396 4397 /* Sub-port Interface */ 4398 4399 /* reg_ritr_sp_if_lag 4400 * LAG indication. When this bit is set the system_port field holds the 4401 * LAG identifier. 4402 * Access: RW 4403 */ 4404 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 4405 4406 /* reg_ritr_sp_system_port 4407 * Port unique indentifier. When lag bit is set, this field holds the 4408 * lag_id in bits 0:9. 4409 * Access: RW 4410 */ 4411 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 4412 4413 /* reg_ritr_sp_if_vid 4414 * VLAN ID. 4415 * Access: RW 4416 */ 4417 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 4418 4419 /* Loopback Interface */ 4420 4421 enum mlxsw_reg_ritr_loopback_protocol { 4422 /* IPinIP IPv4 underlay Unicast */ 4423 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 4424 /* IPinIP IPv6 underlay Unicast */ 4425 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 4426 }; 4427 4428 /* reg_ritr_loopback_protocol 4429 * Access: RW 4430 */ 4431 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 4432 4433 enum mlxsw_reg_ritr_loopback_ipip_type { 4434 /* Tunnel is IPinIP. */ 4435 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 4436 /* Tunnel is GRE, no key. */ 4437 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 4438 /* Tunnel is GRE, with a key. */ 4439 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 4440 }; 4441 4442 /* reg_ritr_loopback_ipip_type 4443 * Encapsulation type. 4444 * Access: RW 4445 */ 4446 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 4447 4448 enum mlxsw_reg_ritr_loopback_ipip_options { 4449 /* The key is defined by gre_key. */ 4450 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 4451 }; 4452 4453 /* reg_ritr_loopback_ipip_options 4454 * Access: RW 4455 */ 4456 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 4457 4458 /* reg_ritr_loopback_ipip_uvr 4459 * Underlay Virtual Router ID. 4460 * Range is 0..cap_max_virtual_routers-1. 4461 * Reserved for Spectrum-2. 4462 * Access: RW 4463 */ 4464 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 4465 4466 /* reg_ritr_loopback_ipip_usip* 4467 * Encapsulation Underlay source IP. 4468 * Access: RW 4469 */ 4470 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 4471 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 4472 4473 /* reg_ritr_loopback_ipip_gre_key 4474 * GRE Key. 4475 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 4476 * Access: RW 4477 */ 4478 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 4479 4480 /* Shared between ingress/egress */ 4481 enum mlxsw_reg_ritr_counter_set_type { 4482 /* No Count. */ 4483 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 4484 /* Basic. Used for router interfaces, counting the following: 4485 * - Error and Discard counters. 4486 * - Unicast, Multicast and Broadcast counters. Sharing the 4487 * same set of counters for the different type of traffic 4488 * (IPv4, IPv6 and mpls). 4489 */ 4490 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 4491 }; 4492 4493 /* reg_ritr_ingress_counter_index 4494 * Counter Index for flow counter. 4495 * Access: RW 4496 */ 4497 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 4498 4499 /* reg_ritr_ingress_counter_set_type 4500 * Igress Counter Set Type for router interface counter. 4501 * Access: RW 4502 */ 4503 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 4504 4505 /* reg_ritr_egress_counter_index 4506 * Counter Index for flow counter. 4507 * Access: RW 4508 */ 4509 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 4510 4511 /* reg_ritr_egress_counter_set_type 4512 * Egress Counter Set Type for router interface counter. 4513 * Access: RW 4514 */ 4515 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 4516 4517 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 4518 bool enable, bool egress) 4519 { 4520 enum mlxsw_reg_ritr_counter_set_type set_type; 4521 4522 if (enable) 4523 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 4524 else 4525 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 4526 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 4527 4528 if (egress) 4529 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 4530 else 4531 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 4532 } 4533 4534 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 4535 { 4536 MLXSW_REG_ZERO(ritr, payload); 4537 mlxsw_reg_ritr_rif_set(payload, rif); 4538 } 4539 4540 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 4541 u16 system_port, u16 vid) 4542 { 4543 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 4544 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 4545 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 4546 } 4547 4548 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 4549 enum mlxsw_reg_ritr_if_type type, 4550 u16 rif, u16 vr_id, u16 mtu) 4551 { 4552 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 4553 4554 MLXSW_REG_ZERO(ritr, payload); 4555 mlxsw_reg_ritr_enable_set(payload, enable); 4556 mlxsw_reg_ritr_ipv4_set(payload, 1); 4557 mlxsw_reg_ritr_ipv6_set(payload, 1); 4558 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 4559 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 4560 mlxsw_reg_ritr_type_set(payload, type); 4561 mlxsw_reg_ritr_op_set(payload, op); 4562 mlxsw_reg_ritr_rif_set(payload, rif); 4563 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 4564 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 4565 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 4566 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 4567 mlxsw_reg_ritr_lb_en_set(payload, 1); 4568 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 4569 mlxsw_reg_ritr_mtu_set(payload, mtu); 4570 } 4571 4572 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 4573 { 4574 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 4575 } 4576 4577 static inline void 4578 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 4579 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4580 enum mlxsw_reg_ritr_loopback_ipip_options options, 4581 u16 uvr_id, u32 gre_key) 4582 { 4583 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 4584 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 4585 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 4586 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 4587 } 4588 4589 static inline void 4590 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 4591 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4592 enum mlxsw_reg_ritr_loopback_ipip_options options, 4593 u16 uvr_id, u32 usip, u32 gre_key) 4594 { 4595 mlxsw_reg_ritr_loopback_protocol_set(payload, 4596 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 4597 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 4598 uvr_id, gre_key); 4599 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 4600 } 4601 4602 /* RTAR - Router TCAM Allocation Register 4603 * -------------------------------------- 4604 * This register is used for allocation of regions in the TCAM table. 4605 */ 4606 #define MLXSW_REG_RTAR_ID 0x8004 4607 #define MLXSW_REG_RTAR_LEN 0x20 4608 4609 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 4610 4611 enum mlxsw_reg_rtar_op { 4612 MLXSW_REG_RTAR_OP_ALLOCATE, 4613 MLXSW_REG_RTAR_OP_RESIZE, 4614 MLXSW_REG_RTAR_OP_DEALLOCATE, 4615 }; 4616 4617 /* reg_rtar_op 4618 * Access: WO 4619 */ 4620 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 4621 4622 enum mlxsw_reg_rtar_key_type { 4623 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 4624 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 4625 }; 4626 4627 /* reg_rtar_key_type 4628 * TCAM key type for the region. 4629 * Access: WO 4630 */ 4631 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 4632 4633 /* reg_rtar_region_size 4634 * TCAM region size. When allocating/resizing this is the requested 4635 * size, the response is the actual size. 4636 * Note: Actual size may be larger than requested. 4637 * Reserved for op = Deallocate 4638 * Access: WO 4639 */ 4640 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 4641 4642 static inline void mlxsw_reg_rtar_pack(char *payload, 4643 enum mlxsw_reg_rtar_op op, 4644 enum mlxsw_reg_rtar_key_type key_type, 4645 u16 region_size) 4646 { 4647 MLXSW_REG_ZERO(rtar, payload); 4648 mlxsw_reg_rtar_op_set(payload, op); 4649 mlxsw_reg_rtar_key_type_set(payload, key_type); 4650 mlxsw_reg_rtar_region_size_set(payload, region_size); 4651 } 4652 4653 /* RATR - Router Adjacency Table Register 4654 * -------------------------------------- 4655 * The RATR register is used to configure the Router Adjacency (next-hop) 4656 * Table. 4657 */ 4658 #define MLXSW_REG_RATR_ID 0x8008 4659 #define MLXSW_REG_RATR_LEN 0x2C 4660 4661 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 4662 4663 enum mlxsw_reg_ratr_op { 4664 /* Read */ 4665 MLXSW_REG_RATR_OP_QUERY_READ = 0, 4666 /* Read and clear activity */ 4667 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 4668 /* Write Adjacency entry */ 4669 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 4670 /* Write Adjacency entry only if the activity is cleared. 4671 * The write may not succeed if the activity is set. There is not 4672 * direct feedback if the write has succeeded or not, however 4673 * the get will reveal the actual entry (SW can compare the get 4674 * response to the set command). 4675 */ 4676 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 4677 }; 4678 4679 /* reg_ratr_op 4680 * Note that Write operation may also be used for updating 4681 * counter_set_type and counter_index. In this case all other 4682 * fields must not be updated. 4683 * Access: OP 4684 */ 4685 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 4686 4687 /* reg_ratr_v 4688 * Valid bit. Indicates if the adjacency entry is valid. 4689 * Note: the device may need some time before reusing an invalidated 4690 * entry. During this time the entry can not be reused. It is 4691 * recommended to use another entry before reusing an invalidated 4692 * entry (e.g. software can put it at the end of the list for 4693 * reusing). Trying to access an invalidated entry not yet cleared 4694 * by the device results with failure indicating "Try Again" status. 4695 * When valid is '0' then egress_router_interface,trap_action, 4696 * adjacency_parameters and counters are reserved 4697 * Access: RW 4698 */ 4699 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 4700 4701 /* reg_ratr_a 4702 * Activity. Set for new entries. Set if a packet lookup has hit on 4703 * the specific entry. To clear the a bit, use "clear activity". 4704 * Access: RO 4705 */ 4706 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 4707 4708 enum mlxsw_reg_ratr_type { 4709 /* Ethernet */ 4710 MLXSW_REG_RATR_TYPE_ETHERNET, 4711 /* IPoIB Unicast without GRH. 4712 * Reserved for Spectrum. 4713 */ 4714 MLXSW_REG_RATR_TYPE_IPOIB_UC, 4715 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 4716 * adjacency). 4717 * Reserved for Spectrum. 4718 */ 4719 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 4720 /* IPoIB Multicast. 4721 * Reserved for Spectrum. 4722 */ 4723 MLXSW_REG_RATR_TYPE_IPOIB_MC, 4724 /* MPLS. 4725 * Reserved for SwitchX/-2. 4726 */ 4727 MLXSW_REG_RATR_TYPE_MPLS, 4728 /* IPinIP Encap. 4729 * Reserved for SwitchX/-2. 4730 */ 4731 MLXSW_REG_RATR_TYPE_IPIP, 4732 }; 4733 4734 /* reg_ratr_type 4735 * Adjacency entry type. 4736 * Access: RW 4737 */ 4738 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 4739 4740 /* reg_ratr_adjacency_index_low 4741 * Bits 15:0 of index into the adjacency table. 4742 * For SwitchX and SwitchX-2, the adjacency table is linear and 4743 * used for adjacency entries only. 4744 * For Spectrum, the index is to the KVD linear. 4745 * Access: Index 4746 */ 4747 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 4748 4749 /* reg_ratr_egress_router_interface 4750 * Range is 0 .. cap_max_router_interfaces - 1 4751 * Access: RW 4752 */ 4753 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 4754 4755 enum mlxsw_reg_ratr_trap_action { 4756 MLXSW_REG_RATR_TRAP_ACTION_NOP, 4757 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 4758 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 4759 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 4760 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 4761 }; 4762 4763 /* reg_ratr_trap_action 4764 * see mlxsw_reg_ratr_trap_action 4765 * Access: RW 4766 */ 4767 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 4768 4769 /* reg_ratr_adjacency_index_high 4770 * Bits 23:16 of the adjacency_index. 4771 * Access: Index 4772 */ 4773 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 4774 4775 enum mlxsw_reg_ratr_trap_id { 4776 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 4777 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 4778 }; 4779 4780 /* reg_ratr_trap_id 4781 * Trap ID to be reported to CPU. 4782 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 4783 * For trap_action of NOP, MIRROR and DISCARD_ERROR 4784 * Access: RW 4785 */ 4786 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 4787 4788 /* reg_ratr_eth_destination_mac 4789 * MAC address of the destination next-hop. 4790 * Access: RW 4791 */ 4792 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 4793 4794 enum mlxsw_reg_ratr_ipip_type { 4795 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 4796 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 4797 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 4798 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 4799 }; 4800 4801 /* reg_ratr_ipip_type 4802 * Underlay destination ip type. 4803 * Note: the type field must match the protocol of the router interface. 4804 * Access: RW 4805 */ 4806 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 4807 4808 /* reg_ratr_ipip_ipv4_udip 4809 * Underlay ipv4 dip. 4810 * Reserved when ipip_type is IPv6. 4811 * Access: RW 4812 */ 4813 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 4814 4815 /* reg_ratr_ipip_ipv6_ptr 4816 * Pointer to IPv6 underlay destination ip address. 4817 * For Spectrum: Pointer to KVD linear space. 4818 * Access: RW 4819 */ 4820 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 4821 4822 enum mlxsw_reg_flow_counter_set_type { 4823 /* No count */ 4824 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4825 /* Count packets and bytes */ 4826 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 4827 /* Count only packets */ 4828 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 4829 }; 4830 4831 /* reg_ratr_counter_set_type 4832 * Counter set type for flow counters 4833 * Access: RW 4834 */ 4835 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 4836 4837 /* reg_ratr_counter_index 4838 * Counter index for flow counters 4839 * Access: RW 4840 */ 4841 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 4842 4843 static inline void 4844 mlxsw_reg_ratr_pack(char *payload, 4845 enum mlxsw_reg_ratr_op op, bool valid, 4846 enum mlxsw_reg_ratr_type type, 4847 u32 adjacency_index, u16 egress_rif) 4848 { 4849 MLXSW_REG_ZERO(ratr, payload); 4850 mlxsw_reg_ratr_op_set(payload, op); 4851 mlxsw_reg_ratr_v_set(payload, valid); 4852 mlxsw_reg_ratr_type_set(payload, type); 4853 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 4854 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 4855 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 4856 } 4857 4858 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 4859 const char *dest_mac) 4860 { 4861 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 4862 } 4863 4864 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 4865 { 4866 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 4867 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 4868 } 4869 4870 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 4871 bool counter_enable) 4872 { 4873 enum mlxsw_reg_flow_counter_set_type set_type; 4874 4875 if (counter_enable) 4876 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 4877 else 4878 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 4879 4880 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 4881 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 4882 } 4883 4884 /* RDPM - Router DSCP to Priority Mapping 4885 * -------------------------------------- 4886 * Controls the mapping from DSCP field to switch priority on routed packets 4887 */ 4888 #define MLXSW_REG_RDPM_ID 0x8009 4889 #define MLXSW_REG_RDPM_BASE_LEN 0x00 4890 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 4891 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4892 #define MLXSW_REG_RDPM_LEN 0x40 4893 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 4894 MLXSW_REG_RDPM_LEN - \ 4895 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 4896 4897 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 4898 4899 /* reg_dscp_entry_e 4900 * Enable update of the specific entry 4901 * Access: Index 4902 */ 4903 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 4904 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4905 4906 /* reg_dscp_entry_prio 4907 * Switch Priority 4908 * Access: RW 4909 */ 4910 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 4911 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4912 4913 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 4914 u8 prio) 4915 { 4916 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 4917 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 4918 } 4919 4920 /* RICNT - Router Interface Counter Register 4921 * ----------------------------------------- 4922 * The RICNT register retrieves per port performance counters 4923 */ 4924 #define MLXSW_REG_RICNT_ID 0x800B 4925 #define MLXSW_REG_RICNT_LEN 0x100 4926 4927 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 4928 4929 /* reg_ricnt_counter_index 4930 * Counter index 4931 * Access: RW 4932 */ 4933 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 4934 4935 enum mlxsw_reg_ricnt_counter_set_type { 4936 /* No Count. */ 4937 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4938 /* Basic. Used for router interfaces, counting the following: 4939 * - Error and Discard counters. 4940 * - Unicast, Multicast and Broadcast counters. Sharing the 4941 * same set of counters for the different type of traffic 4942 * (IPv4, IPv6 and mpls). 4943 */ 4944 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 4945 }; 4946 4947 /* reg_ricnt_counter_set_type 4948 * Counter Set Type for router interface counter 4949 * Access: RW 4950 */ 4951 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 4952 4953 enum mlxsw_reg_ricnt_opcode { 4954 /* Nop. Supported only for read access*/ 4955 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 4956 /* Clear. Setting the clr bit will reset the counter value for 4957 * all counters of the specified Router Interface. 4958 */ 4959 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 4960 }; 4961 4962 /* reg_ricnt_opcode 4963 * Opcode 4964 * Access: RW 4965 */ 4966 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 4967 4968 /* reg_ricnt_good_unicast_packets 4969 * good unicast packets. 4970 * Access: RW 4971 */ 4972 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 4973 4974 /* reg_ricnt_good_multicast_packets 4975 * good multicast packets. 4976 * Access: RW 4977 */ 4978 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 4979 4980 /* reg_ricnt_good_broadcast_packets 4981 * good broadcast packets 4982 * Access: RW 4983 */ 4984 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 4985 4986 /* reg_ricnt_good_unicast_bytes 4987 * A count of L3 data and padding octets not including L2 headers 4988 * for good unicast frames. 4989 * Access: RW 4990 */ 4991 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 4992 4993 /* reg_ricnt_good_multicast_bytes 4994 * A count of L3 data and padding octets not including L2 headers 4995 * for good multicast frames. 4996 * Access: RW 4997 */ 4998 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 4999 5000 /* reg_ritr_good_broadcast_bytes 5001 * A count of L3 data and padding octets not including L2 headers 5002 * for good broadcast frames. 5003 * Access: RW 5004 */ 5005 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 5006 5007 /* reg_ricnt_error_packets 5008 * A count of errored frames that do not pass the router checks. 5009 * Access: RW 5010 */ 5011 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 5012 5013 /* reg_ricnt_discrad_packets 5014 * A count of non-errored frames that do not pass the router checks. 5015 * Access: RW 5016 */ 5017 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 5018 5019 /* reg_ricnt_error_bytes 5020 * A count of L3 data and padding octets not including L2 headers 5021 * for errored frames. 5022 * Access: RW 5023 */ 5024 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 5025 5026 /* reg_ricnt_discard_bytes 5027 * A count of L3 data and padding octets not including L2 headers 5028 * for non-errored frames that do not pass the router checks. 5029 * Access: RW 5030 */ 5031 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 5032 5033 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 5034 enum mlxsw_reg_ricnt_opcode op) 5035 { 5036 MLXSW_REG_ZERO(ricnt, payload); 5037 mlxsw_reg_ricnt_op_set(payload, op); 5038 mlxsw_reg_ricnt_counter_index_set(payload, index); 5039 mlxsw_reg_ricnt_counter_set_type_set(payload, 5040 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 5041 } 5042 5043 /* RRCR - Router Rules Copy Register Layout 5044 * ---------------------------------------- 5045 * This register is used for moving and copying route entry rules. 5046 */ 5047 #define MLXSW_REG_RRCR_ID 0x800F 5048 #define MLXSW_REG_RRCR_LEN 0x24 5049 5050 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 5051 5052 enum mlxsw_reg_rrcr_op { 5053 /* Move rules */ 5054 MLXSW_REG_RRCR_OP_MOVE, 5055 /* Copy rules */ 5056 MLXSW_REG_RRCR_OP_COPY, 5057 }; 5058 5059 /* reg_rrcr_op 5060 * Access: WO 5061 */ 5062 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 5063 5064 /* reg_rrcr_offset 5065 * Offset within the region from which to copy/move. 5066 * Access: Index 5067 */ 5068 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 5069 5070 /* reg_rrcr_size 5071 * The number of rules to copy/move. 5072 * Access: WO 5073 */ 5074 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 5075 5076 /* reg_rrcr_table_id 5077 * Identifier of the table on which to perform the operation. Encoding is the 5078 * same as in RTAR.key_type 5079 * Access: Index 5080 */ 5081 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 5082 5083 /* reg_rrcr_dest_offset 5084 * Offset within the region to which to copy/move 5085 * Access: Index 5086 */ 5087 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 5088 5089 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 5090 u16 offset, u16 size, 5091 enum mlxsw_reg_rtar_key_type table_id, 5092 u16 dest_offset) 5093 { 5094 MLXSW_REG_ZERO(rrcr, payload); 5095 mlxsw_reg_rrcr_op_set(payload, op); 5096 mlxsw_reg_rrcr_offset_set(payload, offset); 5097 mlxsw_reg_rrcr_size_set(payload, size); 5098 mlxsw_reg_rrcr_table_id_set(payload, table_id); 5099 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 5100 } 5101 5102 /* RALTA - Router Algorithmic LPM Tree Allocation Register 5103 * ------------------------------------------------------- 5104 * RALTA is used to allocate the LPM trees of the SHSPM method. 5105 */ 5106 #define MLXSW_REG_RALTA_ID 0x8010 5107 #define MLXSW_REG_RALTA_LEN 0x04 5108 5109 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 5110 5111 /* reg_ralta_op 5112 * opcode (valid for Write, must be 0 on Read) 5113 * 0 - allocate a tree 5114 * 1 - deallocate a tree 5115 * Access: OP 5116 */ 5117 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 5118 5119 enum mlxsw_reg_ralxx_protocol { 5120 MLXSW_REG_RALXX_PROTOCOL_IPV4, 5121 MLXSW_REG_RALXX_PROTOCOL_IPV6, 5122 }; 5123 5124 /* reg_ralta_protocol 5125 * Protocol. 5126 * Deallocation opcode: Reserved. 5127 * Access: RW 5128 */ 5129 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 5130 5131 /* reg_ralta_tree_id 5132 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 5133 * the tree identifier (managed by software). 5134 * Note that tree_id 0 is allocated for a default-route tree. 5135 * Access: Index 5136 */ 5137 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 5138 5139 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 5140 enum mlxsw_reg_ralxx_protocol protocol, 5141 u8 tree_id) 5142 { 5143 MLXSW_REG_ZERO(ralta, payload); 5144 mlxsw_reg_ralta_op_set(payload, !alloc); 5145 mlxsw_reg_ralta_protocol_set(payload, protocol); 5146 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 5147 } 5148 5149 /* RALST - Router Algorithmic LPM Structure Tree Register 5150 * ------------------------------------------------------ 5151 * RALST is used to set and query the structure of an LPM tree. 5152 * The structure of the tree must be sorted as a sorted binary tree, while 5153 * each node is a bin that is tagged as the length of the prefixes the lookup 5154 * will refer to. Therefore, bin X refers to a set of entries with prefixes 5155 * of X bits to match with the destination address. The bin 0 indicates 5156 * the default action, when there is no match of any prefix. 5157 */ 5158 #define MLXSW_REG_RALST_ID 0x8011 5159 #define MLXSW_REG_RALST_LEN 0x104 5160 5161 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 5162 5163 /* reg_ralst_root_bin 5164 * The bin number of the root bin. 5165 * 0<root_bin=<(length of IP address) 5166 * For a default-route tree configure 0xff 5167 * Access: RW 5168 */ 5169 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 5170 5171 /* reg_ralst_tree_id 5172 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5173 * Access: Index 5174 */ 5175 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 5176 5177 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 5178 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 5179 #define MLXSW_REG_RALST_BIN_COUNT 128 5180 5181 /* reg_ralst_left_child_bin 5182 * Holding the children of the bin according to the stored tree's structure. 5183 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5184 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5185 * Access: RW 5186 */ 5187 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 5188 5189 /* reg_ralst_right_child_bin 5190 * Holding the children of the bin according to the stored tree's structure. 5191 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5192 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5193 * Access: RW 5194 */ 5195 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 5196 false); 5197 5198 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 5199 { 5200 MLXSW_REG_ZERO(ralst, payload); 5201 5202 /* Initialize all bins to have no left or right child */ 5203 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 5204 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 5205 5206 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 5207 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 5208 } 5209 5210 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 5211 u8 left_child_bin, 5212 u8 right_child_bin) 5213 { 5214 int bin_index = bin_number - 1; 5215 5216 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 5217 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 5218 right_child_bin); 5219 } 5220 5221 /* RALTB - Router Algorithmic LPM Tree Binding Register 5222 * ---------------------------------------------------- 5223 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 5224 */ 5225 #define MLXSW_REG_RALTB_ID 0x8012 5226 #define MLXSW_REG_RALTB_LEN 0x04 5227 5228 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 5229 5230 /* reg_raltb_virtual_router 5231 * Virtual Router ID 5232 * Range is 0..cap_max_virtual_routers-1 5233 * Access: Index 5234 */ 5235 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 5236 5237 /* reg_raltb_protocol 5238 * Protocol. 5239 * Access: Index 5240 */ 5241 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 5242 5243 /* reg_raltb_tree_id 5244 * Tree to be used for the {virtual_router, protocol} 5245 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5246 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 5247 * Access: RW 5248 */ 5249 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 5250 5251 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 5252 enum mlxsw_reg_ralxx_protocol protocol, 5253 u8 tree_id) 5254 { 5255 MLXSW_REG_ZERO(raltb, payload); 5256 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 5257 mlxsw_reg_raltb_protocol_set(payload, protocol); 5258 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 5259 } 5260 5261 /* RALUE - Router Algorithmic LPM Unicast Entry Register 5262 * ----------------------------------------------------- 5263 * RALUE is used to configure and query LPM entries that serve 5264 * the Unicast protocols. 5265 */ 5266 #define MLXSW_REG_RALUE_ID 0x8013 5267 #define MLXSW_REG_RALUE_LEN 0x38 5268 5269 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 5270 5271 /* reg_ralue_protocol 5272 * Protocol. 5273 * Access: Index 5274 */ 5275 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 5276 5277 enum mlxsw_reg_ralue_op { 5278 /* Read operation. If entry doesn't exist, the operation fails. */ 5279 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 5280 /* Clear on read operation. Used to read entry and 5281 * clear Activity bit. 5282 */ 5283 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 5284 /* Write operation. Used to write a new entry to the table. All RW 5285 * fields are written for new entry. Activity bit is set 5286 * for new entries. 5287 */ 5288 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 5289 /* Update operation. Used to update an existing route entry and 5290 * only update the RW fields that are detailed in the field 5291 * op_u_mask. If entry doesn't exist, the operation fails. 5292 */ 5293 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 5294 /* Clear activity. The Activity bit (the field a) is cleared 5295 * for the entry. 5296 */ 5297 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 5298 /* Delete operation. Used to delete an existing entry. If entry 5299 * doesn't exist, the operation fails. 5300 */ 5301 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 5302 }; 5303 5304 /* reg_ralue_op 5305 * Operation. 5306 * Access: OP 5307 */ 5308 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 5309 5310 /* reg_ralue_a 5311 * Activity. Set for new entries. Set if a packet lookup has hit on the 5312 * specific entry, only if the entry is a route. To clear the a bit, use 5313 * "clear activity" op. 5314 * Enabled by activity_dis in RGCR 5315 * Access: RO 5316 */ 5317 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 5318 5319 /* reg_ralue_virtual_router 5320 * Virtual Router ID 5321 * Range is 0..cap_max_virtual_routers-1 5322 * Access: Index 5323 */ 5324 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 5325 5326 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 5327 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 5328 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 5329 5330 /* reg_ralue_op_u_mask 5331 * opcode update mask. 5332 * On read operation, this field is reserved. 5333 * This field is valid for update opcode, otherwise - reserved. 5334 * This field is a bitmask of the fields that should be updated. 5335 * Access: WO 5336 */ 5337 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 5338 5339 /* reg_ralue_prefix_len 5340 * Number of bits in the prefix of the LPM route. 5341 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 5342 * two entries in the physical HW table. 5343 * Access: Index 5344 */ 5345 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 5346 5347 /* reg_ralue_dip* 5348 * The prefix of the route or of the marker that the object of the LPM 5349 * is compared with. The most significant bits of the dip are the prefix. 5350 * The least significant bits must be '0' if the prefix_len is smaller 5351 * than 128 for IPv6 or smaller than 32 for IPv4. 5352 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 5353 * Access: Index 5354 */ 5355 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 5356 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 5357 5358 enum mlxsw_reg_ralue_entry_type { 5359 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 5360 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 5361 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 5362 }; 5363 5364 /* reg_ralue_entry_type 5365 * Entry type. 5366 * Note - for Marker entries, the action_type and action fields are reserved. 5367 * Access: RW 5368 */ 5369 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 5370 5371 /* reg_ralue_bmp_len 5372 * The best match prefix length in the case that there is no match for 5373 * longer prefixes. 5374 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 5375 * Note for any update operation with entry_type modification this 5376 * field must be set. 5377 * Access: RW 5378 */ 5379 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 5380 5381 enum mlxsw_reg_ralue_action_type { 5382 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 5383 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 5384 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 5385 }; 5386 5387 /* reg_ralue_action_type 5388 * Action Type 5389 * Indicates how the IP address is connected. 5390 * It can be connected to a local subnet through local_erif or can be 5391 * on a remote subnet connected through a next-hop router, 5392 * or transmitted to the CPU. 5393 * Reserved when entry_type = MARKER_ENTRY 5394 * Access: RW 5395 */ 5396 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 5397 5398 enum mlxsw_reg_ralue_trap_action { 5399 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 5400 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 5401 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 5402 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 5403 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 5404 }; 5405 5406 /* reg_ralue_trap_action 5407 * Trap action. 5408 * For IP2ME action, only NOP and MIRROR are possible. 5409 * Access: RW 5410 */ 5411 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 5412 5413 /* reg_ralue_trap_id 5414 * Trap ID to be reported to CPU. 5415 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 5416 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 5417 * Access: RW 5418 */ 5419 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 5420 5421 /* reg_ralue_adjacency_index 5422 * Points to the first entry of the group-based ECMP. 5423 * Only relevant in case of REMOTE action. 5424 * Access: RW 5425 */ 5426 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 5427 5428 /* reg_ralue_ecmp_size 5429 * Amount of sequential entries starting 5430 * from the adjacency_index (the number of ECMPs). 5431 * The valid range is 1-64, 512, 1024, 2048 and 4096. 5432 * Reserved when trap_action is TRAP or DISCARD_ERROR. 5433 * Only relevant in case of REMOTE action. 5434 * Access: RW 5435 */ 5436 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 5437 5438 /* reg_ralue_local_erif 5439 * Egress Router Interface. 5440 * Only relevant in case of LOCAL action. 5441 * Access: RW 5442 */ 5443 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 5444 5445 /* reg_ralue_ip2me_v 5446 * Valid bit for the tunnel_ptr field. 5447 * If valid = 0 then trap to CPU as IP2ME trap ID. 5448 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 5449 * decapsulation then tunnel decapsulation is done. 5450 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 5451 * decapsulation then trap as IP2ME trap ID. 5452 * Only relevant in case of IP2ME action. 5453 * Access: RW 5454 */ 5455 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 5456 5457 /* reg_ralue_ip2me_tunnel_ptr 5458 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 5459 * For Spectrum, pointer to KVD Linear. 5460 * Only relevant in case of IP2ME action. 5461 * Access: RW 5462 */ 5463 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 5464 5465 static inline void mlxsw_reg_ralue_pack(char *payload, 5466 enum mlxsw_reg_ralxx_protocol protocol, 5467 enum mlxsw_reg_ralue_op op, 5468 u16 virtual_router, u8 prefix_len) 5469 { 5470 MLXSW_REG_ZERO(ralue, payload); 5471 mlxsw_reg_ralue_protocol_set(payload, protocol); 5472 mlxsw_reg_ralue_op_set(payload, op); 5473 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 5474 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 5475 mlxsw_reg_ralue_entry_type_set(payload, 5476 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 5477 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 5478 } 5479 5480 static inline void mlxsw_reg_ralue_pack4(char *payload, 5481 enum mlxsw_reg_ralxx_protocol protocol, 5482 enum mlxsw_reg_ralue_op op, 5483 u16 virtual_router, u8 prefix_len, 5484 u32 dip) 5485 { 5486 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5487 mlxsw_reg_ralue_dip4_set(payload, dip); 5488 } 5489 5490 static inline void mlxsw_reg_ralue_pack6(char *payload, 5491 enum mlxsw_reg_ralxx_protocol protocol, 5492 enum mlxsw_reg_ralue_op op, 5493 u16 virtual_router, u8 prefix_len, 5494 const void *dip) 5495 { 5496 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5497 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 5498 } 5499 5500 static inline void 5501 mlxsw_reg_ralue_act_remote_pack(char *payload, 5502 enum mlxsw_reg_ralue_trap_action trap_action, 5503 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 5504 { 5505 mlxsw_reg_ralue_action_type_set(payload, 5506 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 5507 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5508 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5509 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 5510 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 5511 } 5512 5513 static inline void 5514 mlxsw_reg_ralue_act_local_pack(char *payload, 5515 enum mlxsw_reg_ralue_trap_action trap_action, 5516 u16 trap_id, u16 local_erif) 5517 { 5518 mlxsw_reg_ralue_action_type_set(payload, 5519 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 5520 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5521 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5522 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 5523 } 5524 5525 static inline void 5526 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 5527 { 5528 mlxsw_reg_ralue_action_type_set(payload, 5529 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5530 } 5531 5532 static inline void 5533 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 5534 { 5535 mlxsw_reg_ralue_action_type_set(payload, 5536 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5537 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 5538 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 5539 } 5540 5541 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 5542 * ---------------------------------------------------------- 5543 * The RAUHT register is used to configure and query the Unicast Host table in 5544 * devices that implement the Algorithmic LPM. 5545 */ 5546 #define MLXSW_REG_RAUHT_ID 0x8014 5547 #define MLXSW_REG_RAUHT_LEN 0x74 5548 5549 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 5550 5551 enum mlxsw_reg_rauht_type { 5552 MLXSW_REG_RAUHT_TYPE_IPV4, 5553 MLXSW_REG_RAUHT_TYPE_IPV6, 5554 }; 5555 5556 /* reg_rauht_type 5557 * Access: Index 5558 */ 5559 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 5560 5561 enum mlxsw_reg_rauht_op { 5562 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 5563 /* Read operation */ 5564 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 5565 /* Clear on read operation. Used to read entry and clear 5566 * activity bit. 5567 */ 5568 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 5569 /* Add. Used to write a new entry to the table. All R/W fields are 5570 * relevant for new entry. Activity bit is set for new entries. 5571 */ 5572 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 5573 /* Update action. Used to update an existing route entry and 5574 * only update the following fields: 5575 * trap_action, trap_id, mac, counter_set_type, counter_index 5576 */ 5577 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 5578 /* Clear activity. A bit is cleared for the entry. */ 5579 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 5580 /* Delete entry */ 5581 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 5582 /* Delete all host entries on a RIF. In this command, dip 5583 * field is reserved. 5584 */ 5585 }; 5586 5587 /* reg_rauht_op 5588 * Access: OP 5589 */ 5590 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 5591 5592 /* reg_rauht_a 5593 * Activity. Set for new entries. Set if a packet lookup has hit on 5594 * the specific entry. 5595 * To clear the a bit, use "clear activity" op. 5596 * Enabled by activity_dis in RGCR 5597 * Access: RO 5598 */ 5599 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 5600 5601 /* reg_rauht_rif 5602 * Router Interface 5603 * Access: Index 5604 */ 5605 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 5606 5607 /* reg_rauht_dip* 5608 * Destination address. 5609 * Access: Index 5610 */ 5611 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 5612 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 5613 5614 enum mlxsw_reg_rauht_trap_action { 5615 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 5616 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 5617 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 5618 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 5619 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 5620 }; 5621 5622 /* reg_rauht_trap_action 5623 * Access: RW 5624 */ 5625 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 5626 5627 enum mlxsw_reg_rauht_trap_id { 5628 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 5629 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 5630 }; 5631 5632 /* reg_rauht_trap_id 5633 * Trap ID to be reported to CPU. 5634 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5635 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 5636 * trap_id is reserved. 5637 * Access: RW 5638 */ 5639 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 5640 5641 /* reg_rauht_counter_set_type 5642 * Counter set type for flow counters 5643 * Access: RW 5644 */ 5645 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 5646 5647 /* reg_rauht_counter_index 5648 * Counter index for flow counters 5649 * Access: RW 5650 */ 5651 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 5652 5653 /* reg_rauht_mac 5654 * MAC address. 5655 * Access: RW 5656 */ 5657 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 5658 5659 static inline void mlxsw_reg_rauht_pack(char *payload, 5660 enum mlxsw_reg_rauht_op op, u16 rif, 5661 const char *mac) 5662 { 5663 MLXSW_REG_ZERO(rauht, payload); 5664 mlxsw_reg_rauht_op_set(payload, op); 5665 mlxsw_reg_rauht_rif_set(payload, rif); 5666 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 5667 } 5668 5669 static inline void mlxsw_reg_rauht_pack4(char *payload, 5670 enum mlxsw_reg_rauht_op op, u16 rif, 5671 const char *mac, u32 dip) 5672 { 5673 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5674 mlxsw_reg_rauht_dip4_set(payload, dip); 5675 } 5676 5677 static inline void mlxsw_reg_rauht_pack6(char *payload, 5678 enum mlxsw_reg_rauht_op op, u16 rif, 5679 const char *mac, const char *dip) 5680 { 5681 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5682 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 5683 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 5684 } 5685 5686 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 5687 u64 counter_index) 5688 { 5689 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 5690 mlxsw_reg_rauht_counter_set_type_set(payload, 5691 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 5692 } 5693 5694 /* RALEU - Router Algorithmic LPM ECMP Update Register 5695 * --------------------------------------------------- 5696 * The register enables updating the ECMP section in the action for multiple 5697 * LPM Unicast entries in a single operation. The update is executed to 5698 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 5699 */ 5700 #define MLXSW_REG_RALEU_ID 0x8015 5701 #define MLXSW_REG_RALEU_LEN 0x28 5702 5703 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 5704 5705 /* reg_raleu_protocol 5706 * Protocol. 5707 * Access: Index 5708 */ 5709 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 5710 5711 /* reg_raleu_virtual_router 5712 * Virtual Router ID 5713 * Range is 0..cap_max_virtual_routers-1 5714 * Access: Index 5715 */ 5716 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 5717 5718 /* reg_raleu_adjacency_index 5719 * Adjacency Index used for matching on the existing entries. 5720 * Access: Index 5721 */ 5722 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 5723 5724 /* reg_raleu_ecmp_size 5725 * ECMP Size used for matching on the existing entries. 5726 * Access: Index 5727 */ 5728 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 5729 5730 /* reg_raleu_new_adjacency_index 5731 * New Adjacency Index. 5732 * Access: WO 5733 */ 5734 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 5735 5736 /* reg_raleu_new_ecmp_size 5737 * New ECMP Size. 5738 * Access: WO 5739 */ 5740 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 5741 5742 static inline void mlxsw_reg_raleu_pack(char *payload, 5743 enum mlxsw_reg_ralxx_protocol protocol, 5744 u16 virtual_router, 5745 u32 adjacency_index, u16 ecmp_size, 5746 u32 new_adjacency_index, 5747 u16 new_ecmp_size) 5748 { 5749 MLXSW_REG_ZERO(raleu, payload); 5750 mlxsw_reg_raleu_protocol_set(payload, protocol); 5751 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 5752 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 5753 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 5754 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 5755 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 5756 } 5757 5758 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 5759 * ---------------------------------------------------------------- 5760 * The RAUHTD register allows dumping entries from the Router Unicast Host 5761 * Table. For a given session an entry is dumped no more than one time. The 5762 * first RAUHTD access after reset is a new session. A session ends when the 5763 * num_rec response is smaller than num_rec request or for IPv4 when the 5764 * num_entries is smaller than 4. The clear activity affect the current session 5765 * or the last session if a new session has not started. 5766 */ 5767 #define MLXSW_REG_RAUHTD_ID 0x8018 5768 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 5769 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 5770 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 5771 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 5772 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 5773 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 5774 5775 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 5776 5777 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 5778 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 5779 5780 /* reg_rauhtd_filter_fields 5781 * if a bit is '0' then the relevant field is ignored and dump is done 5782 * regardless of the field value 5783 * Bit0 - filter by activity: entry_a 5784 * Bit3 - filter by entry rip: entry_rif 5785 * Access: Index 5786 */ 5787 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 5788 5789 enum mlxsw_reg_rauhtd_op { 5790 MLXSW_REG_RAUHTD_OP_DUMP, 5791 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 5792 }; 5793 5794 /* reg_rauhtd_op 5795 * Access: OP 5796 */ 5797 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 5798 5799 /* reg_rauhtd_num_rec 5800 * At request: number of records requested 5801 * At response: number of records dumped 5802 * For IPv4, each record has 4 entries at request and up to 4 entries 5803 * at response 5804 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 5805 * Access: Index 5806 */ 5807 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 5808 5809 /* reg_rauhtd_entry_a 5810 * Dump only if activity has value of entry_a 5811 * Reserved if filter_fields bit0 is '0' 5812 * Access: Index 5813 */ 5814 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 5815 5816 enum mlxsw_reg_rauhtd_type { 5817 MLXSW_REG_RAUHTD_TYPE_IPV4, 5818 MLXSW_REG_RAUHTD_TYPE_IPV6, 5819 }; 5820 5821 /* reg_rauhtd_type 5822 * Dump only if record type is: 5823 * 0 - IPv4 5824 * 1 - IPv6 5825 * Access: Index 5826 */ 5827 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 5828 5829 /* reg_rauhtd_entry_rif 5830 * Dump only if RIF has value of entry_rif 5831 * Reserved if filter_fields bit3 is '0' 5832 * Access: Index 5833 */ 5834 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 5835 5836 static inline void mlxsw_reg_rauhtd_pack(char *payload, 5837 enum mlxsw_reg_rauhtd_type type) 5838 { 5839 MLXSW_REG_ZERO(rauhtd, payload); 5840 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 5841 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 5842 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 5843 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 5844 mlxsw_reg_rauhtd_type_set(payload, type); 5845 } 5846 5847 /* reg_rauhtd_ipv4_rec_num_entries 5848 * Number of valid entries in this record: 5849 * 0 - 1 valid entry 5850 * 1 - 2 valid entries 5851 * 2 - 3 valid entries 5852 * 3 - 4 valid entries 5853 * Access: RO 5854 */ 5855 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 5856 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 5857 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5858 5859 /* reg_rauhtd_rec_type 5860 * Record type. 5861 * 0 - IPv4 5862 * 1 - IPv6 5863 * Access: RO 5864 */ 5865 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 5866 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5867 5868 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 5869 5870 /* reg_rauhtd_ipv4_ent_a 5871 * Activity. Set for new entries. Set if a packet lookup has hit on the 5872 * specific entry. 5873 * Access: RO 5874 */ 5875 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5876 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5877 5878 /* reg_rauhtd_ipv4_ent_rif 5879 * Router interface. 5880 * Access: RO 5881 */ 5882 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5883 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5884 5885 /* reg_rauhtd_ipv4_ent_dip 5886 * Destination IPv4 address. 5887 * Access: RO 5888 */ 5889 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5890 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 5891 5892 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 5893 5894 /* reg_rauhtd_ipv6_ent_a 5895 * Activity. Set for new entries. Set if a packet lookup has hit on the 5896 * specific entry. 5897 * Access: RO 5898 */ 5899 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5900 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5901 5902 /* reg_rauhtd_ipv6_ent_rif 5903 * Router interface. 5904 * Access: RO 5905 */ 5906 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5907 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5908 5909 /* reg_rauhtd_ipv6_ent_dip 5910 * Destination IPv6 address. 5911 * Access: RO 5912 */ 5913 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 5914 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 5915 5916 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 5917 int ent_index, u16 *p_rif, 5918 u32 *p_dip) 5919 { 5920 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 5921 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 5922 } 5923 5924 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 5925 int rec_index, u16 *p_rif, 5926 char *p_dip) 5927 { 5928 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 5929 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 5930 } 5931 5932 /* RTDP - Routing Tunnel Decap Properties Register 5933 * ----------------------------------------------- 5934 * The RTDP register is used for configuring the tunnel decap properties of NVE 5935 * and IPinIP. 5936 */ 5937 #define MLXSW_REG_RTDP_ID 0x8020 5938 #define MLXSW_REG_RTDP_LEN 0x44 5939 5940 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 5941 5942 enum mlxsw_reg_rtdp_type { 5943 MLXSW_REG_RTDP_TYPE_NVE, 5944 MLXSW_REG_RTDP_TYPE_IPIP, 5945 }; 5946 5947 /* reg_rtdp_type 5948 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 5949 * Access: RW 5950 */ 5951 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 5952 5953 /* reg_rtdp_tunnel_index 5954 * Index to the Decap entry. 5955 * For Spectrum, Index to KVD Linear. 5956 * Access: Index 5957 */ 5958 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 5959 5960 /* IPinIP */ 5961 5962 /* reg_rtdp_ipip_irif 5963 * Ingress Router Interface for the overlay router 5964 * Access: RW 5965 */ 5966 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 5967 5968 enum mlxsw_reg_rtdp_ipip_sip_check { 5969 /* No sip checks. */ 5970 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 5971 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 5972 * equal ipv4_usip. 5973 */ 5974 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 5975 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 5976 * equal ipv6_usip. 5977 */ 5978 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 5979 }; 5980 5981 /* reg_rtdp_ipip_sip_check 5982 * SIP check to perform. If decapsulation failed due to these configurations 5983 * then trap_id is IPIP_DECAP_ERROR. 5984 * Access: RW 5985 */ 5986 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 5987 5988 /* If set, allow decapsulation of IPinIP (without GRE). */ 5989 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 5990 /* If set, allow decapsulation of IPinGREinIP without a key. */ 5991 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 5992 /* If set, allow decapsulation of IPinGREinIP with a key. */ 5993 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 5994 5995 /* reg_rtdp_ipip_type_check 5996 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 5997 * these configurations then trap_id is IPIP_DECAP_ERROR. 5998 * Access: RW 5999 */ 6000 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 6001 6002 /* reg_rtdp_ipip_gre_key_check 6003 * Whether GRE key should be checked. When check is enabled: 6004 * - A packet received as IPinIP (without GRE) will always pass. 6005 * - A packet received as IPinGREinIP without a key will not pass the check. 6006 * - A packet received as IPinGREinIP with a key will pass the check only if the 6007 * key in the packet is equal to expected_gre_key. 6008 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 6009 * Access: RW 6010 */ 6011 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 6012 6013 /* reg_rtdp_ipip_ipv4_usip 6014 * Underlay IPv4 address for ipv4 source address check. 6015 * Reserved when sip_check is not '1'. 6016 * Access: RW 6017 */ 6018 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 6019 6020 /* reg_rtdp_ipip_ipv6_usip_ptr 6021 * This field is valid when sip_check is "sipv6 check explicitly". This is a 6022 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 6023 * is to the KVD linear. 6024 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 6025 * Access: RW 6026 */ 6027 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 6028 6029 /* reg_rtdp_ipip_expected_gre_key 6030 * GRE key for checking. 6031 * Reserved when gre_key_check is '0'. 6032 * Access: RW 6033 */ 6034 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 6035 6036 static inline void mlxsw_reg_rtdp_pack(char *payload, 6037 enum mlxsw_reg_rtdp_type type, 6038 u32 tunnel_index) 6039 { 6040 MLXSW_REG_ZERO(rtdp, payload); 6041 mlxsw_reg_rtdp_type_set(payload, type); 6042 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 6043 } 6044 6045 static inline void 6046 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 6047 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 6048 unsigned int type_check, bool gre_key_check, 6049 u32 ipv4_usip, u32 expected_gre_key) 6050 { 6051 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 6052 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 6053 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 6054 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 6055 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 6056 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 6057 } 6058 6059 /* RIGR-V2 - Router Interface Group Register Version 2 6060 * --------------------------------------------------- 6061 * The RIGR_V2 register is used to add, remove and query egress interface list 6062 * of a multicast forwarding entry. 6063 */ 6064 #define MLXSW_REG_RIGR2_ID 0x8023 6065 #define MLXSW_REG_RIGR2_LEN 0xB0 6066 6067 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 6068 6069 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 6070 6071 /* reg_rigr2_rigr_index 6072 * KVD Linear index. 6073 * Access: Index 6074 */ 6075 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 6076 6077 /* reg_rigr2_vnext 6078 * Next RIGR Index is valid. 6079 * Access: RW 6080 */ 6081 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 6082 6083 /* reg_rigr2_next_rigr_index 6084 * Next RIGR Index. The index is to the KVD linear. 6085 * Reserved when vnxet = '0'. 6086 * Access: RW 6087 */ 6088 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 6089 6090 /* reg_rigr2_vrmid 6091 * RMID Index is valid. 6092 * Access: RW 6093 */ 6094 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 6095 6096 /* reg_rigr2_rmid_index 6097 * RMID Index. 6098 * Range 0 .. max_mid - 1 6099 * Reserved when vrmid = '0'. 6100 * The index is to the Port Group Table (PGT) 6101 * Access: RW 6102 */ 6103 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 6104 6105 /* reg_rigr2_erif_entry_v 6106 * Egress Router Interface is valid. 6107 * Note that low-entries must be set if high-entries are set. For 6108 * example: if erif_entry[2].v is set then erif_entry[1].v and 6109 * erif_entry[0].v must be set. 6110 * Index can be from 0 to cap_mc_erif_list_entries-1 6111 * Access: RW 6112 */ 6113 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 6114 6115 /* reg_rigr2_erif_entry_erif 6116 * Egress Router Interface. 6117 * Valid range is from 0 to cap_max_router_interfaces - 1 6118 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 6119 * Access: RW 6120 */ 6121 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 6122 6123 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 6124 bool vnext, u32 next_rigr_index) 6125 { 6126 MLXSW_REG_ZERO(rigr2, payload); 6127 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 6128 mlxsw_reg_rigr2_vnext_set(payload, vnext); 6129 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 6130 mlxsw_reg_rigr2_vrmid_set(payload, 0); 6131 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 6132 } 6133 6134 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 6135 bool v, u16 erif) 6136 { 6137 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 6138 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 6139 } 6140 6141 /* RECR-V2 - Router ECMP Configuration Version 2 Register 6142 * ------------------------------------------------------ 6143 */ 6144 #define MLXSW_REG_RECR2_ID 0x8025 6145 #define MLXSW_REG_RECR2_LEN 0x38 6146 6147 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 6148 6149 /* reg_recr2_pp 6150 * Per-port configuration 6151 * Access: Index 6152 */ 6153 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 6154 6155 /* reg_recr2_sh 6156 * Symmetric hash 6157 * Access: RW 6158 */ 6159 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 6160 6161 /* reg_recr2_seed 6162 * Seed 6163 * Access: RW 6164 */ 6165 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 6166 6167 enum { 6168 /* Enable IPv4 fields if packet is not TCP and not UDP */ 6169 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 6170 /* Enable IPv4 fields if packet is TCP or UDP */ 6171 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 6172 /* Enable IPv6 fields if packet is not TCP and not UDP */ 6173 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 6174 /* Enable IPv6 fields if packet is TCP or UDP */ 6175 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 6176 /* Enable TCP/UDP header fields if packet is IPv4 */ 6177 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 6178 /* Enable TCP/UDP header fields if packet is IPv6 */ 6179 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 6180 }; 6181 6182 /* reg_recr2_outer_header_enables 6183 * Bit mask where each bit enables a specific layer to be included in 6184 * the hash calculation. 6185 * Access: RW 6186 */ 6187 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 6188 6189 enum { 6190 /* IPv4 Source IP */ 6191 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 6192 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 6193 /* IPv4 Destination IP */ 6194 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 6195 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 6196 /* IP Protocol */ 6197 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 6198 /* IPv6 Source IP */ 6199 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 6200 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 6201 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 6202 /* IPv6 Destination IP */ 6203 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 6204 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 6205 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 6206 /* IPv6 Next Header */ 6207 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 6208 /* IPv6 Flow Label */ 6209 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 6210 /* TCP/UDP Source Port */ 6211 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 6212 /* TCP/UDP Destination Port */ 6213 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 6214 }; 6215 6216 /* reg_recr2_outer_header_fields_enable 6217 * Packet fields to enable for ECMP hash subject to outer_header_enable. 6218 * Access: RW 6219 */ 6220 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 6221 6222 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 6223 { 6224 int i; 6225 6226 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 6227 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6228 true); 6229 } 6230 6231 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 6232 { 6233 int i; 6234 6235 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 6236 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6237 true); 6238 } 6239 6240 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 6241 { 6242 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 6243 6244 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6245 6246 i = MLXSW_REG_RECR2_IPV6_SIP8; 6247 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 6248 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6249 true); 6250 } 6251 6252 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 6253 { 6254 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 6255 6256 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6257 6258 i = MLXSW_REG_RECR2_IPV6_DIP8; 6259 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 6260 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6261 true); 6262 } 6263 6264 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 6265 { 6266 MLXSW_REG_ZERO(recr2, payload); 6267 mlxsw_reg_recr2_pp_set(payload, false); 6268 mlxsw_reg_recr2_sh_set(payload, true); 6269 mlxsw_reg_recr2_seed_set(payload, seed); 6270 } 6271 6272 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 6273 * -------------------------------------------------------------- 6274 * The RMFT_V2 register is used to configure and query the multicast table. 6275 */ 6276 #define MLXSW_REG_RMFT2_ID 0x8027 6277 #define MLXSW_REG_RMFT2_LEN 0x174 6278 6279 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 6280 6281 /* reg_rmft2_v 6282 * Valid 6283 * Access: RW 6284 */ 6285 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 6286 6287 enum mlxsw_reg_rmft2_type { 6288 MLXSW_REG_RMFT2_TYPE_IPV4, 6289 MLXSW_REG_RMFT2_TYPE_IPV6 6290 }; 6291 6292 /* reg_rmft2_type 6293 * Access: Index 6294 */ 6295 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 6296 6297 enum mlxsw_sp_reg_rmft2_op { 6298 /* For Write: 6299 * Write operation. Used to write a new entry to the table. All RW 6300 * fields are relevant for new entry. Activity bit is set for new 6301 * entries - Note write with v (Valid) 0 will delete the entry. 6302 * For Query: 6303 * Read operation 6304 */ 6305 MLXSW_REG_RMFT2_OP_READ_WRITE, 6306 }; 6307 6308 /* reg_rmft2_op 6309 * Operation. 6310 * Access: OP 6311 */ 6312 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 6313 6314 /* reg_rmft2_a 6315 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 6316 * entry. 6317 * Access: RO 6318 */ 6319 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 6320 6321 /* reg_rmft2_offset 6322 * Offset within the multicast forwarding table to write to. 6323 * Access: Index 6324 */ 6325 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 6326 6327 /* reg_rmft2_virtual_router 6328 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 6329 * Access: RW 6330 */ 6331 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 6332 6333 enum mlxsw_reg_rmft2_irif_mask { 6334 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 6335 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 6336 }; 6337 6338 /* reg_rmft2_irif_mask 6339 * Ingress RIF mask. 6340 * Access: RW 6341 */ 6342 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 6343 6344 /* reg_rmft2_irif 6345 * Ingress RIF index. 6346 * Access: RW 6347 */ 6348 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 6349 6350 /* reg_rmft2_dip{4,6} 6351 * Destination IPv4/6 address 6352 * Access: RW 6353 */ 6354 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 6355 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 6356 6357 /* reg_rmft2_dip{4,6}_mask 6358 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6359 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6360 * Access: RW 6361 */ 6362 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 6363 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 6364 6365 /* reg_rmft2_sip{4,6} 6366 * Source IPv4/6 address 6367 * Access: RW 6368 */ 6369 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 6370 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 6371 6372 /* reg_rmft2_sip{4,6}_mask 6373 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6374 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6375 * Access: RW 6376 */ 6377 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 6378 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 6379 6380 /* reg_rmft2_flexible_action_set 6381 * ACL action set. The only supported action types in this field and in any 6382 * action-set pointed from here are as follows: 6383 * 00h: ACTION_NULL 6384 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 6385 * 03h: ACTION_TRAP 6386 * 06h: ACTION_QOS 6387 * 08h: ACTION_POLICING_MONITORING 6388 * 10h: ACTION_ROUTER_MC 6389 * Access: RW 6390 */ 6391 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 6392 MLXSW_REG_FLEX_ACTION_SET_LEN); 6393 6394 static inline void 6395 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 6396 u16 virtual_router, 6397 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6398 const char *flex_action_set) 6399 { 6400 MLXSW_REG_ZERO(rmft2, payload); 6401 mlxsw_reg_rmft2_v_set(payload, v); 6402 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 6403 mlxsw_reg_rmft2_offset_set(payload, offset); 6404 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 6405 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 6406 mlxsw_reg_rmft2_irif_set(payload, irif); 6407 if (flex_action_set) 6408 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 6409 flex_action_set); 6410 } 6411 6412 static inline void 6413 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 6414 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6415 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 6416 const char *flexible_action_set) 6417 { 6418 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 6419 irif_mask, irif, flexible_action_set); 6420 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 6421 mlxsw_reg_rmft2_dip4_set(payload, dip4); 6422 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 6423 mlxsw_reg_rmft2_sip4_set(payload, sip4); 6424 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 6425 } 6426 6427 static inline void 6428 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 6429 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6430 struct in6_addr dip6, struct in6_addr dip6_mask, 6431 struct in6_addr sip6, struct in6_addr sip6_mask, 6432 const char *flexible_action_set) 6433 { 6434 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 6435 irif_mask, irif, flexible_action_set); 6436 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 6437 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 6438 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 6439 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 6440 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 6441 } 6442 6443 /* MFCR - Management Fan Control Register 6444 * -------------------------------------- 6445 * This register controls the settings of the Fan Speed PWM mechanism. 6446 */ 6447 #define MLXSW_REG_MFCR_ID 0x9001 6448 #define MLXSW_REG_MFCR_LEN 0x08 6449 6450 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 6451 6452 enum mlxsw_reg_mfcr_pwm_frequency { 6453 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 6454 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 6455 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 6456 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 6457 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 6458 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 6459 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 6460 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 6461 }; 6462 6463 /* reg_mfcr_pwm_frequency 6464 * Controls the frequency of the PWM signal. 6465 * Access: RW 6466 */ 6467 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 6468 6469 #define MLXSW_MFCR_TACHOS_MAX 10 6470 6471 /* reg_mfcr_tacho_active 6472 * Indicates which of the tachometer is active (bit per tachometer). 6473 * Access: RO 6474 */ 6475 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 6476 6477 #define MLXSW_MFCR_PWMS_MAX 5 6478 6479 /* reg_mfcr_pwm_active 6480 * Indicates which of the PWM control is active (bit per PWM). 6481 * Access: RO 6482 */ 6483 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 6484 6485 static inline void 6486 mlxsw_reg_mfcr_pack(char *payload, 6487 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 6488 { 6489 MLXSW_REG_ZERO(mfcr, payload); 6490 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 6491 } 6492 6493 static inline void 6494 mlxsw_reg_mfcr_unpack(char *payload, 6495 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 6496 u16 *p_tacho_active, u8 *p_pwm_active) 6497 { 6498 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 6499 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 6500 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 6501 } 6502 6503 /* MFSC - Management Fan Speed Control Register 6504 * -------------------------------------------- 6505 * This register controls the settings of the Fan Speed PWM mechanism. 6506 */ 6507 #define MLXSW_REG_MFSC_ID 0x9002 6508 #define MLXSW_REG_MFSC_LEN 0x08 6509 6510 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 6511 6512 /* reg_mfsc_pwm 6513 * Fan pwm to control / monitor. 6514 * Access: Index 6515 */ 6516 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 6517 6518 /* reg_mfsc_pwm_duty_cycle 6519 * Controls the duty cycle of the PWM. Value range from 0..255 to 6520 * represent duty cycle of 0%...100%. 6521 * Access: RW 6522 */ 6523 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 6524 6525 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 6526 u8 pwm_duty_cycle) 6527 { 6528 MLXSW_REG_ZERO(mfsc, payload); 6529 mlxsw_reg_mfsc_pwm_set(payload, pwm); 6530 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 6531 } 6532 6533 /* MFSM - Management Fan Speed Measurement 6534 * --------------------------------------- 6535 * This register controls the settings of the Tacho measurements and 6536 * enables reading the Tachometer measurements. 6537 */ 6538 #define MLXSW_REG_MFSM_ID 0x9003 6539 #define MLXSW_REG_MFSM_LEN 0x08 6540 6541 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 6542 6543 /* reg_mfsm_tacho 6544 * Fan tachometer index. 6545 * Access: Index 6546 */ 6547 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 6548 6549 /* reg_mfsm_rpm 6550 * Fan speed (round per minute). 6551 * Access: RO 6552 */ 6553 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 6554 6555 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 6556 { 6557 MLXSW_REG_ZERO(mfsm, payload); 6558 mlxsw_reg_mfsm_tacho_set(payload, tacho); 6559 } 6560 6561 /* MFSL - Management Fan Speed Limit Register 6562 * ------------------------------------------ 6563 * The Fan Speed Limit register is used to configure the fan speed 6564 * event / interrupt notification mechanism. Fan speed threshold are 6565 * defined for both under-speed and over-speed. 6566 */ 6567 #define MLXSW_REG_MFSL_ID 0x9004 6568 #define MLXSW_REG_MFSL_LEN 0x0C 6569 6570 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 6571 6572 /* reg_mfsl_tacho 6573 * Fan tachometer index. 6574 * Access: Index 6575 */ 6576 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 6577 6578 /* reg_mfsl_tach_min 6579 * Tachometer minimum value (minimum RPM). 6580 * Access: RW 6581 */ 6582 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 6583 6584 /* reg_mfsl_tach_max 6585 * Tachometer maximum value (maximum RPM). 6586 * Access: RW 6587 */ 6588 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 6589 6590 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 6591 u16 tach_min, u16 tach_max) 6592 { 6593 MLXSW_REG_ZERO(mfsl, payload); 6594 mlxsw_reg_mfsl_tacho_set(payload, tacho); 6595 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 6596 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 6597 } 6598 6599 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 6600 u16 *p_tach_min, u16 *p_tach_max) 6601 { 6602 if (p_tach_min) 6603 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 6604 6605 if (p_tach_max) 6606 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 6607 } 6608 6609 /* MTCAP - Management Temperature Capabilities 6610 * ------------------------------------------- 6611 * This register exposes the capabilities of the device and 6612 * system temperature sensing. 6613 */ 6614 #define MLXSW_REG_MTCAP_ID 0x9009 6615 #define MLXSW_REG_MTCAP_LEN 0x08 6616 6617 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 6618 6619 /* reg_mtcap_sensor_count 6620 * Number of sensors supported by the device. 6621 * This includes the QSFP module sensors (if exists in the QSFP module). 6622 * Access: RO 6623 */ 6624 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 6625 6626 /* MTMP - Management Temperature 6627 * ----------------------------- 6628 * This register controls the settings of the temperature measurements 6629 * and enables reading the temperature measurements. Note that temperature 6630 * is in 0.125 degrees Celsius. 6631 */ 6632 #define MLXSW_REG_MTMP_ID 0x900A 6633 #define MLXSW_REG_MTMP_LEN 0x20 6634 6635 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 6636 6637 /* reg_mtmp_sensor_index 6638 * Sensors index to access. 6639 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 6640 * (module 0 is mapped to sensor_index 64). 6641 * Access: Index 6642 */ 6643 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 6644 6645 /* Convert to milli degrees Celsius */ 6646 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 6647 6648 /* reg_mtmp_temperature 6649 * Temperature reading from the sensor. Reading is in 0.125 Celsius 6650 * degrees units. 6651 * Access: RO 6652 */ 6653 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 6654 6655 /* reg_mtmp_mte 6656 * Max Temperature Enable - enables measuring the max temperature on a sensor. 6657 * Access: RW 6658 */ 6659 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 6660 6661 /* reg_mtmp_mtr 6662 * Max Temperature Reset - clears the value of the max temperature register. 6663 * Access: WO 6664 */ 6665 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 6666 6667 /* reg_mtmp_max_temperature 6668 * The highest measured temperature from the sensor. 6669 * When the bit mte is cleared, the field max_temperature is reserved. 6670 * Access: RO 6671 */ 6672 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 6673 6674 /* reg_mtmp_tee 6675 * Temperature Event Enable. 6676 * 0 - Do not generate event 6677 * 1 - Generate event 6678 * 2 - Generate single event 6679 * Access: RW 6680 */ 6681 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 6682 6683 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 6684 6685 /* reg_mtmp_temperature_threshold_hi 6686 * High threshold for Temperature Warning Event. In 0.125 Celsius. 6687 * Access: RW 6688 */ 6689 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 6690 6691 /* reg_mtmp_temperature_threshold_lo 6692 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 6693 * Access: RW 6694 */ 6695 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 6696 6697 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 6698 6699 /* reg_mtmp_sensor_name 6700 * Sensor Name 6701 * Access: RO 6702 */ 6703 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 6704 6705 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 6706 bool max_temp_enable, 6707 bool max_temp_reset) 6708 { 6709 MLXSW_REG_ZERO(mtmp, payload); 6710 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 6711 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 6712 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 6713 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 6714 MLXSW_REG_MTMP_THRESH_HI); 6715 } 6716 6717 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 6718 unsigned int *p_max_temp, 6719 char *sensor_name) 6720 { 6721 u16 temp; 6722 6723 if (p_temp) { 6724 temp = mlxsw_reg_mtmp_temperature_get(payload); 6725 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6726 } 6727 if (p_max_temp) { 6728 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 6729 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6730 } 6731 if (sensor_name) 6732 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 6733 } 6734 6735 /* MCIA - Management Cable Info Access 6736 * ----------------------------------- 6737 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 6738 */ 6739 6740 #define MLXSW_REG_MCIA_ID 0x9014 6741 #define MLXSW_REG_MCIA_LEN 0x40 6742 6743 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 6744 6745 /* reg_mcia_l 6746 * Lock bit. Setting this bit will lock the access to the specific 6747 * cable. Used for updating a full page in a cable EPROM. Any access 6748 * other then subsequence writes will fail while the port is locked. 6749 * Access: RW 6750 */ 6751 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 6752 6753 /* reg_mcia_module 6754 * Module number. 6755 * Access: Index 6756 */ 6757 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 6758 6759 /* reg_mcia_status 6760 * Module status. 6761 * Access: RO 6762 */ 6763 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 6764 6765 /* reg_mcia_i2c_device_address 6766 * I2C device address. 6767 * Access: RW 6768 */ 6769 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 6770 6771 /* reg_mcia_page_number 6772 * Page number. 6773 * Access: RW 6774 */ 6775 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 6776 6777 /* reg_mcia_device_address 6778 * Device address. 6779 * Access: RW 6780 */ 6781 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 6782 6783 /* reg_mcia_size 6784 * Number of bytes to read/write (up to 48 bytes). 6785 * Access: RW 6786 */ 6787 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 6788 6789 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 6790 6791 /* reg_mcia_eeprom 6792 * Bytes to read/write. 6793 * Access: RW 6794 */ 6795 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 6796 6797 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 6798 u8 page_number, u16 device_addr, 6799 u8 size, u8 i2c_device_addr) 6800 { 6801 MLXSW_REG_ZERO(mcia, payload); 6802 mlxsw_reg_mcia_module_set(payload, module); 6803 mlxsw_reg_mcia_l_set(payload, lock); 6804 mlxsw_reg_mcia_page_number_set(payload, page_number); 6805 mlxsw_reg_mcia_device_address_set(payload, device_addr); 6806 mlxsw_reg_mcia_size_set(payload, size); 6807 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 6808 } 6809 6810 /* MPAT - Monitoring Port Analyzer Table 6811 * ------------------------------------- 6812 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 6813 * For an enabled analyzer, all fields except e (enable) cannot be modified. 6814 */ 6815 #define MLXSW_REG_MPAT_ID 0x901A 6816 #define MLXSW_REG_MPAT_LEN 0x78 6817 6818 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 6819 6820 /* reg_mpat_pa_id 6821 * Port Analyzer ID. 6822 * Access: Index 6823 */ 6824 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 6825 6826 /* reg_mpat_system_port 6827 * A unique port identifier for the final destination of the packet. 6828 * Access: RW 6829 */ 6830 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 6831 6832 /* reg_mpat_e 6833 * Enable. Indicating the Port Analyzer is enabled. 6834 * Access: RW 6835 */ 6836 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 6837 6838 /* reg_mpat_qos 6839 * Quality Of Service Mode. 6840 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 6841 * PCP, DEI, DSCP or VL) are configured. 6842 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 6843 * same as in the original packet that has triggered the mirroring. For 6844 * SPAN also the pcp,dei are maintained. 6845 * Access: RW 6846 */ 6847 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 6848 6849 /* reg_mpat_be 6850 * Best effort mode. Indicates mirroring traffic should not cause packet 6851 * drop or back pressure, but will discard the mirrored packets. Mirrored 6852 * packets will be forwarded on a best effort manner. 6853 * 0: Do not discard mirrored packets 6854 * 1: Discard mirrored packets if causing congestion 6855 * Access: RW 6856 */ 6857 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 6858 6859 enum mlxsw_reg_mpat_span_type { 6860 /* Local SPAN Ethernet. 6861 * The original packet is not encapsulated. 6862 */ 6863 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 6864 6865 /* Remote SPAN Ethernet VLAN. 6866 * The packet is forwarded to the monitoring port on the monitoring 6867 * VLAN. 6868 */ 6869 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 6870 6871 /* Encapsulated Remote SPAN Ethernet L3 GRE. 6872 * The packet is encapsulated with GRE header. 6873 */ 6874 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 6875 }; 6876 6877 /* reg_mpat_span_type 6878 * SPAN type. 6879 * Access: RW 6880 */ 6881 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 6882 6883 /* Remote SPAN - Ethernet VLAN 6884 * - - - - - - - - - - - - - - 6885 */ 6886 6887 /* reg_mpat_eth_rspan_vid 6888 * Encapsulation header VLAN ID. 6889 * Access: RW 6890 */ 6891 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 6892 6893 /* Encapsulated Remote SPAN - Ethernet L2 6894 * - - - - - - - - - - - - - - - - - - - 6895 */ 6896 6897 enum mlxsw_reg_mpat_eth_rspan_version { 6898 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 6899 }; 6900 6901 /* reg_mpat_eth_rspan_version 6902 * RSPAN mirror header version. 6903 * Access: RW 6904 */ 6905 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 6906 6907 /* reg_mpat_eth_rspan_mac 6908 * Destination MAC address. 6909 * Access: RW 6910 */ 6911 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 6912 6913 /* reg_mpat_eth_rspan_tp 6914 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 6915 * Access: RW 6916 */ 6917 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 6918 6919 /* Encapsulated Remote SPAN - Ethernet L3 6920 * - - - - - - - - - - - - - - - - - - - 6921 */ 6922 6923 enum mlxsw_reg_mpat_eth_rspan_protocol { 6924 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 6925 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 6926 }; 6927 6928 /* reg_mpat_eth_rspan_protocol 6929 * SPAN encapsulation protocol. 6930 * Access: RW 6931 */ 6932 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 6933 6934 /* reg_mpat_eth_rspan_ttl 6935 * Encapsulation header Time-to-Live/HopLimit. 6936 * Access: RW 6937 */ 6938 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 6939 6940 /* reg_mpat_eth_rspan_smac 6941 * Source MAC address 6942 * Access: RW 6943 */ 6944 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 6945 6946 /* reg_mpat_eth_rspan_dip* 6947 * Destination IP address. The IP version is configured by protocol. 6948 * Access: RW 6949 */ 6950 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 6951 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 6952 6953 /* reg_mpat_eth_rspan_sip* 6954 * Source IP address. The IP version is configured by protocol. 6955 * Access: RW 6956 */ 6957 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 6958 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 6959 6960 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 6961 u16 system_port, bool e, 6962 enum mlxsw_reg_mpat_span_type span_type) 6963 { 6964 MLXSW_REG_ZERO(mpat, payload); 6965 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 6966 mlxsw_reg_mpat_system_port_set(payload, system_port); 6967 mlxsw_reg_mpat_e_set(payload, e); 6968 mlxsw_reg_mpat_qos_set(payload, 1); 6969 mlxsw_reg_mpat_be_set(payload, 1); 6970 mlxsw_reg_mpat_span_type_set(payload, span_type); 6971 } 6972 6973 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 6974 { 6975 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 6976 } 6977 6978 static inline void 6979 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 6980 enum mlxsw_reg_mpat_eth_rspan_version version, 6981 const char *mac, 6982 bool tp) 6983 { 6984 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 6985 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 6986 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 6987 } 6988 6989 static inline void 6990 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 6991 const char *smac, 6992 u32 sip, u32 dip) 6993 { 6994 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 6995 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 6996 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 6997 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 6998 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 6999 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 7000 } 7001 7002 static inline void 7003 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 7004 const char *smac, 7005 struct in6_addr sip, struct in6_addr dip) 7006 { 7007 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 7008 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 7009 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 7010 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 7011 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 7012 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 7013 } 7014 7015 /* MPAR - Monitoring Port Analyzer Register 7016 * ---------------------------------------- 7017 * MPAR register is used to query and configure the port analyzer port mirroring 7018 * properties. 7019 */ 7020 #define MLXSW_REG_MPAR_ID 0x901B 7021 #define MLXSW_REG_MPAR_LEN 0x08 7022 7023 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 7024 7025 /* reg_mpar_local_port 7026 * The local port to mirror the packets from. 7027 * Access: Index 7028 */ 7029 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 7030 7031 enum mlxsw_reg_mpar_i_e { 7032 MLXSW_REG_MPAR_TYPE_EGRESS, 7033 MLXSW_REG_MPAR_TYPE_INGRESS, 7034 }; 7035 7036 /* reg_mpar_i_e 7037 * Ingress/Egress 7038 * Access: Index 7039 */ 7040 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 7041 7042 /* reg_mpar_enable 7043 * Enable mirroring 7044 * By default, port mirroring is disabled for all ports. 7045 * Access: RW 7046 */ 7047 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 7048 7049 /* reg_mpar_pa_id 7050 * Port Analyzer ID. 7051 * Access: RW 7052 */ 7053 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 7054 7055 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 7056 enum mlxsw_reg_mpar_i_e i_e, 7057 bool enable, u8 pa_id) 7058 { 7059 MLXSW_REG_ZERO(mpar, payload); 7060 mlxsw_reg_mpar_local_port_set(payload, local_port); 7061 mlxsw_reg_mpar_enable_set(payload, enable); 7062 mlxsw_reg_mpar_i_e_set(payload, i_e); 7063 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 7064 } 7065 7066 /* MRSR - Management Reset and Shutdown Register 7067 * --------------------------------------------- 7068 * MRSR register is used to reset or shutdown the switch or 7069 * the entire system (when applicable). 7070 */ 7071 #define MLXSW_REG_MRSR_ID 0x9023 7072 #define MLXSW_REG_MRSR_LEN 0x08 7073 7074 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 7075 7076 /* reg_mrsr_command 7077 * Reset/shutdown command 7078 * 0 - do nothing 7079 * 1 - software reset 7080 * Access: WO 7081 */ 7082 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 7083 7084 static inline void mlxsw_reg_mrsr_pack(char *payload) 7085 { 7086 MLXSW_REG_ZERO(mrsr, payload); 7087 mlxsw_reg_mrsr_command_set(payload, 1); 7088 } 7089 7090 /* MLCR - Management LED Control Register 7091 * -------------------------------------- 7092 * Controls the system LEDs. 7093 */ 7094 #define MLXSW_REG_MLCR_ID 0x902B 7095 #define MLXSW_REG_MLCR_LEN 0x0C 7096 7097 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 7098 7099 /* reg_mlcr_local_port 7100 * Local port number. 7101 * Access: RW 7102 */ 7103 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 7104 7105 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 7106 7107 /* reg_mlcr_beacon_duration 7108 * Duration of the beacon to be active, in seconds. 7109 * 0x0 - Will turn off the beacon. 7110 * 0xFFFF - Will turn on the beacon until explicitly turned off. 7111 * Access: RW 7112 */ 7113 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 7114 7115 /* reg_mlcr_beacon_remain 7116 * Remaining duration of the beacon, in seconds. 7117 * 0xFFFF indicates an infinite amount of time. 7118 * Access: RO 7119 */ 7120 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 7121 7122 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 7123 bool active) 7124 { 7125 MLXSW_REG_ZERO(mlcr, payload); 7126 mlxsw_reg_mlcr_local_port_set(payload, local_port); 7127 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 7128 MLXSW_REG_MLCR_DURATION_MAX : 0); 7129 } 7130 7131 /* MCQI - Management Component Query Information 7132 * --------------------------------------------- 7133 * This register allows querying information about firmware components. 7134 */ 7135 #define MLXSW_REG_MCQI_ID 0x9061 7136 #define MLXSW_REG_MCQI_BASE_LEN 0x18 7137 #define MLXSW_REG_MCQI_CAP_LEN 0x14 7138 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 7139 7140 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 7141 7142 /* reg_mcqi_component_index 7143 * Index of the accessed component. 7144 * Access: Index 7145 */ 7146 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 7147 7148 enum mlxfw_reg_mcqi_info_type { 7149 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 7150 }; 7151 7152 /* reg_mcqi_info_type 7153 * Component properties set. 7154 * Access: RW 7155 */ 7156 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 7157 7158 /* reg_mcqi_offset 7159 * The requested/returned data offset from the section start, given in bytes. 7160 * Must be DWORD aligned. 7161 * Access: RW 7162 */ 7163 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 7164 7165 /* reg_mcqi_data_size 7166 * The requested/returned data size, given in bytes. If data_size is not DWORD 7167 * aligned, the last bytes are zero padded. 7168 * Access: RW 7169 */ 7170 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 7171 7172 /* reg_mcqi_cap_max_component_size 7173 * Maximum size for this component, given in bytes. 7174 * Access: RO 7175 */ 7176 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 7177 7178 /* reg_mcqi_cap_log_mcda_word_size 7179 * Log 2 of the access word size in bytes. Read and write access must be aligned 7180 * to the word size. Write access must be done for an integer number of words. 7181 * Access: RO 7182 */ 7183 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 7184 7185 /* reg_mcqi_cap_mcda_max_write_size 7186 * Maximal write size for MCDA register 7187 * Access: RO 7188 */ 7189 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 7190 7191 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 7192 { 7193 MLXSW_REG_ZERO(mcqi, payload); 7194 mlxsw_reg_mcqi_component_index_set(payload, component_index); 7195 mlxsw_reg_mcqi_info_type_set(payload, 7196 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 7197 mlxsw_reg_mcqi_offset_set(payload, 0); 7198 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 7199 } 7200 7201 static inline void mlxsw_reg_mcqi_unpack(char *payload, 7202 u32 *p_cap_max_component_size, 7203 u8 *p_cap_log_mcda_word_size, 7204 u16 *p_cap_mcda_max_write_size) 7205 { 7206 *p_cap_max_component_size = 7207 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 7208 *p_cap_log_mcda_word_size = 7209 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 7210 *p_cap_mcda_max_write_size = 7211 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 7212 } 7213 7214 /* MCC - Management Component Control 7215 * ---------------------------------- 7216 * Controls the firmware component and updates the FSM. 7217 */ 7218 #define MLXSW_REG_MCC_ID 0x9062 7219 #define MLXSW_REG_MCC_LEN 0x1C 7220 7221 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 7222 7223 enum mlxsw_reg_mcc_instruction { 7224 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 7225 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 7226 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 7227 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 7228 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 7229 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 7230 }; 7231 7232 /* reg_mcc_instruction 7233 * Command to be executed by the FSM. 7234 * Applicable for write operation only. 7235 * Access: RW 7236 */ 7237 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 7238 7239 /* reg_mcc_component_index 7240 * Index of the accessed component. Applicable only for commands that 7241 * refer to components. Otherwise, this field is reserved. 7242 * Access: Index 7243 */ 7244 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 7245 7246 /* reg_mcc_update_handle 7247 * Token representing the current flow executed by the FSM. 7248 * Access: WO 7249 */ 7250 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 7251 7252 /* reg_mcc_error_code 7253 * Indicates the successful completion of the instruction, or the reason it 7254 * failed 7255 * Access: RO 7256 */ 7257 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 7258 7259 /* reg_mcc_control_state 7260 * Current FSM state 7261 * Access: RO 7262 */ 7263 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 7264 7265 /* reg_mcc_component_size 7266 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 7267 * the size may shorten the update time. Value 0x0 means that size is 7268 * unspecified. 7269 * Access: WO 7270 */ 7271 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 7272 7273 static inline void mlxsw_reg_mcc_pack(char *payload, 7274 enum mlxsw_reg_mcc_instruction instr, 7275 u16 component_index, u32 update_handle, 7276 u32 component_size) 7277 { 7278 MLXSW_REG_ZERO(mcc, payload); 7279 mlxsw_reg_mcc_instruction_set(payload, instr); 7280 mlxsw_reg_mcc_component_index_set(payload, component_index); 7281 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 7282 mlxsw_reg_mcc_component_size_set(payload, component_size); 7283 } 7284 7285 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 7286 u8 *p_error_code, u8 *p_control_state) 7287 { 7288 if (p_update_handle) 7289 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 7290 if (p_error_code) 7291 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 7292 if (p_control_state) 7293 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 7294 } 7295 7296 /* MCDA - Management Component Data Access 7297 * --------------------------------------- 7298 * This register allows reading and writing a firmware component. 7299 */ 7300 #define MLXSW_REG_MCDA_ID 0x9063 7301 #define MLXSW_REG_MCDA_BASE_LEN 0x10 7302 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 7303 #define MLXSW_REG_MCDA_LEN \ 7304 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 7305 7306 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 7307 7308 /* reg_mcda_update_handle 7309 * Token representing the current flow executed by the FSM. 7310 * Access: RW 7311 */ 7312 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 7313 7314 /* reg_mcda_offset 7315 * Offset of accessed address relative to component start. Accesses must be in 7316 * accordance to log_mcda_word_size in MCQI reg. 7317 * Access: RW 7318 */ 7319 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 7320 7321 /* reg_mcda_size 7322 * Size of the data accessed, given in bytes. 7323 * Access: RW 7324 */ 7325 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 7326 7327 /* reg_mcda_data 7328 * Data block accessed. 7329 * Access: RW 7330 */ 7331 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 7332 7333 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 7334 u32 offset, u16 size, u8 *data) 7335 { 7336 int i; 7337 7338 MLXSW_REG_ZERO(mcda, payload); 7339 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 7340 mlxsw_reg_mcda_offset_set(payload, offset); 7341 mlxsw_reg_mcda_size_set(payload, size); 7342 7343 for (i = 0; i < size / 4; i++) 7344 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 7345 } 7346 7347 /* MPSC - Monitoring Packet Sampling Configuration Register 7348 * -------------------------------------------------------- 7349 * MPSC Register is used to configure the Packet Sampling mechanism. 7350 */ 7351 #define MLXSW_REG_MPSC_ID 0x9080 7352 #define MLXSW_REG_MPSC_LEN 0x1C 7353 7354 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 7355 7356 /* reg_mpsc_local_port 7357 * Local port number 7358 * Not supported for CPU port 7359 * Access: Index 7360 */ 7361 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 7362 7363 /* reg_mpsc_e 7364 * Enable sampling on port local_port 7365 * Access: RW 7366 */ 7367 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 7368 7369 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 7370 7371 /* reg_mpsc_rate 7372 * Sampling rate = 1 out of rate packets (with randomization around 7373 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 7374 * Access: RW 7375 */ 7376 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 7377 7378 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 7379 u32 rate) 7380 { 7381 MLXSW_REG_ZERO(mpsc, payload); 7382 mlxsw_reg_mpsc_local_port_set(payload, local_port); 7383 mlxsw_reg_mpsc_e_set(payload, e); 7384 mlxsw_reg_mpsc_rate_set(payload, rate); 7385 } 7386 7387 /* MGPC - Monitoring General Purpose Counter Set Register 7388 * The MGPC register retrieves and sets the General Purpose Counter Set. 7389 */ 7390 #define MLXSW_REG_MGPC_ID 0x9081 7391 #define MLXSW_REG_MGPC_LEN 0x18 7392 7393 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 7394 7395 /* reg_mgpc_counter_set_type 7396 * Counter set type. 7397 * Access: OP 7398 */ 7399 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 7400 7401 /* reg_mgpc_counter_index 7402 * Counter index. 7403 * Access: Index 7404 */ 7405 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 7406 7407 enum mlxsw_reg_mgpc_opcode { 7408 /* Nop */ 7409 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 7410 /* Clear counters */ 7411 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 7412 }; 7413 7414 /* reg_mgpc_opcode 7415 * Opcode. 7416 * Access: OP 7417 */ 7418 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 7419 7420 /* reg_mgpc_byte_counter 7421 * Byte counter value. 7422 * Access: RW 7423 */ 7424 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 7425 7426 /* reg_mgpc_packet_counter 7427 * Packet counter value. 7428 * Access: RW 7429 */ 7430 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 7431 7432 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 7433 enum mlxsw_reg_mgpc_opcode opcode, 7434 enum mlxsw_reg_flow_counter_set_type set_type) 7435 { 7436 MLXSW_REG_ZERO(mgpc, payload); 7437 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 7438 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 7439 mlxsw_reg_mgpc_opcode_set(payload, opcode); 7440 } 7441 7442 /* TIGCR - Tunneling IPinIP General Configuration Register 7443 * ------------------------------------------------------- 7444 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 7445 */ 7446 #define MLXSW_REG_TIGCR_ID 0xA801 7447 #define MLXSW_REG_TIGCR_LEN 0x10 7448 7449 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 7450 7451 /* reg_tigcr_ipip_ttlc 7452 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 7453 * header. 7454 * Access: RW 7455 */ 7456 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 7457 7458 /* reg_tigcr_ipip_ttl_uc 7459 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 7460 * reg_tigcr_ipip_ttlc is unset. 7461 * Access: RW 7462 */ 7463 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 7464 7465 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 7466 { 7467 MLXSW_REG_ZERO(tigcr, payload); 7468 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 7469 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 7470 } 7471 7472 /* SBPR - Shared Buffer Pools Register 7473 * ----------------------------------- 7474 * The SBPR configures and retrieves the shared buffer pools and configuration. 7475 */ 7476 #define MLXSW_REG_SBPR_ID 0xB001 7477 #define MLXSW_REG_SBPR_LEN 0x14 7478 7479 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 7480 7481 /* shared direstion enum for SBPR, SBCM, SBPM */ 7482 enum mlxsw_reg_sbxx_dir { 7483 MLXSW_REG_SBXX_DIR_INGRESS, 7484 MLXSW_REG_SBXX_DIR_EGRESS, 7485 }; 7486 7487 /* reg_sbpr_dir 7488 * Direction. 7489 * Access: Index 7490 */ 7491 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 7492 7493 /* reg_sbpr_pool 7494 * Pool index. 7495 * Access: Index 7496 */ 7497 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 7498 7499 /* reg_sbpr_size 7500 * Pool size in buffer cells. 7501 * Access: RW 7502 */ 7503 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 7504 7505 enum mlxsw_reg_sbpr_mode { 7506 MLXSW_REG_SBPR_MODE_STATIC, 7507 MLXSW_REG_SBPR_MODE_DYNAMIC, 7508 }; 7509 7510 /* reg_sbpr_mode 7511 * Pool quota calculation mode. 7512 * Access: RW 7513 */ 7514 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 7515 7516 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 7517 enum mlxsw_reg_sbxx_dir dir, 7518 enum mlxsw_reg_sbpr_mode mode, u32 size) 7519 { 7520 MLXSW_REG_ZERO(sbpr, payload); 7521 mlxsw_reg_sbpr_pool_set(payload, pool); 7522 mlxsw_reg_sbpr_dir_set(payload, dir); 7523 mlxsw_reg_sbpr_mode_set(payload, mode); 7524 mlxsw_reg_sbpr_size_set(payload, size); 7525 } 7526 7527 /* SBCM - Shared Buffer Class Management Register 7528 * ---------------------------------------------- 7529 * The SBCM register configures and retrieves the shared buffer allocation 7530 * and configuration according to Port-PG, including the binding to pool 7531 * and definition of the associated quota. 7532 */ 7533 #define MLXSW_REG_SBCM_ID 0xB002 7534 #define MLXSW_REG_SBCM_LEN 0x28 7535 7536 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 7537 7538 /* reg_sbcm_local_port 7539 * Local port number. 7540 * For Ingress: excludes CPU port and Router port 7541 * For Egress: excludes IP Router 7542 * Access: Index 7543 */ 7544 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 7545 7546 /* reg_sbcm_pg_buff 7547 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 7548 * For PG buffer: range is 0..cap_max_pg_buffers - 1 7549 * For traffic class: range is 0..cap_max_tclass - 1 7550 * Note that when traffic class is in MC aware mode then the traffic 7551 * classes which are MC aware cannot be configured. 7552 * Access: Index 7553 */ 7554 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 7555 7556 /* reg_sbcm_dir 7557 * Direction. 7558 * Access: Index 7559 */ 7560 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 7561 7562 /* reg_sbcm_min_buff 7563 * Minimum buffer size for the limiter, in cells. 7564 * Access: RW 7565 */ 7566 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 7567 7568 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 7569 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 7570 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 7571 7572 /* reg_sbcm_max_buff 7573 * When the pool associated to the port-pg/tclass is configured to 7574 * static, Maximum buffer size for the limiter configured in cells. 7575 * When the pool associated to the port-pg/tclass is configured to 7576 * dynamic, the max_buff holds the "alpha" parameter, supporting 7577 * the following values: 7578 * 0: 0 7579 * i: (1/128)*2^(i-1), for i=1..14 7580 * 0xFF: Infinity 7581 * Access: RW 7582 */ 7583 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 7584 7585 /* reg_sbcm_pool 7586 * Association of the port-priority to a pool. 7587 * Access: RW 7588 */ 7589 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 7590 7591 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 7592 enum mlxsw_reg_sbxx_dir dir, 7593 u32 min_buff, u32 max_buff, u8 pool) 7594 { 7595 MLXSW_REG_ZERO(sbcm, payload); 7596 mlxsw_reg_sbcm_local_port_set(payload, local_port); 7597 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 7598 mlxsw_reg_sbcm_dir_set(payload, dir); 7599 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 7600 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 7601 mlxsw_reg_sbcm_pool_set(payload, pool); 7602 } 7603 7604 /* SBPM - Shared Buffer Port Management Register 7605 * --------------------------------------------- 7606 * The SBPM register configures and retrieves the shared buffer allocation 7607 * and configuration according to Port-Pool, including the definition 7608 * of the associated quota. 7609 */ 7610 #define MLXSW_REG_SBPM_ID 0xB003 7611 #define MLXSW_REG_SBPM_LEN 0x28 7612 7613 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 7614 7615 /* reg_sbpm_local_port 7616 * Local port number. 7617 * For Ingress: excludes CPU port and Router port 7618 * For Egress: excludes IP Router 7619 * Access: Index 7620 */ 7621 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 7622 7623 /* reg_sbpm_pool 7624 * The pool associated to quota counting on the local_port. 7625 * Access: Index 7626 */ 7627 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 7628 7629 /* reg_sbpm_dir 7630 * Direction. 7631 * Access: Index 7632 */ 7633 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 7634 7635 /* reg_sbpm_buff_occupancy 7636 * Current buffer occupancy in cells. 7637 * Access: RO 7638 */ 7639 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 7640 7641 /* reg_sbpm_clr 7642 * Clear Max Buffer Occupancy 7643 * When this bit is set, max_buff_occupancy field is cleared (and a 7644 * new max value is tracked from the time the clear was performed). 7645 * Access: OP 7646 */ 7647 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 7648 7649 /* reg_sbpm_max_buff_occupancy 7650 * Maximum value of buffer occupancy in cells monitored. Cleared by 7651 * writing to the clr field. 7652 * Access: RO 7653 */ 7654 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 7655 7656 /* reg_sbpm_min_buff 7657 * Minimum buffer size for the limiter, in cells. 7658 * Access: RW 7659 */ 7660 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 7661 7662 /* reg_sbpm_max_buff 7663 * When the pool associated to the port-pg/tclass is configured to 7664 * static, Maximum buffer size for the limiter configured in cells. 7665 * When the pool associated to the port-pg/tclass is configured to 7666 * dynamic, the max_buff holds the "alpha" parameter, supporting 7667 * the following values: 7668 * 0: 0 7669 * i: (1/128)*2^(i-1), for i=1..14 7670 * 0xFF: Infinity 7671 * Access: RW 7672 */ 7673 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 7674 7675 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 7676 enum mlxsw_reg_sbxx_dir dir, bool clr, 7677 u32 min_buff, u32 max_buff) 7678 { 7679 MLXSW_REG_ZERO(sbpm, payload); 7680 mlxsw_reg_sbpm_local_port_set(payload, local_port); 7681 mlxsw_reg_sbpm_pool_set(payload, pool); 7682 mlxsw_reg_sbpm_dir_set(payload, dir); 7683 mlxsw_reg_sbpm_clr_set(payload, clr); 7684 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 7685 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 7686 } 7687 7688 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 7689 u32 *p_max_buff_occupancy) 7690 { 7691 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 7692 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 7693 } 7694 7695 /* SBMM - Shared Buffer Multicast Management Register 7696 * -------------------------------------------------- 7697 * The SBMM register configures and retrieves the shared buffer allocation 7698 * and configuration for MC packets according to Switch-Priority, including 7699 * the binding to pool and definition of the associated quota. 7700 */ 7701 #define MLXSW_REG_SBMM_ID 0xB004 7702 #define MLXSW_REG_SBMM_LEN 0x28 7703 7704 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 7705 7706 /* reg_sbmm_prio 7707 * Switch Priority. 7708 * Access: Index 7709 */ 7710 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 7711 7712 /* reg_sbmm_min_buff 7713 * Minimum buffer size for the limiter, in cells. 7714 * Access: RW 7715 */ 7716 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 7717 7718 /* reg_sbmm_max_buff 7719 * When the pool associated to the port-pg/tclass is configured to 7720 * static, Maximum buffer size for the limiter configured in cells. 7721 * When the pool associated to the port-pg/tclass is configured to 7722 * dynamic, the max_buff holds the "alpha" parameter, supporting 7723 * the following values: 7724 * 0: 0 7725 * i: (1/128)*2^(i-1), for i=1..14 7726 * 0xFF: Infinity 7727 * Access: RW 7728 */ 7729 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 7730 7731 /* reg_sbmm_pool 7732 * Association of the port-priority to a pool. 7733 * Access: RW 7734 */ 7735 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 7736 7737 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 7738 u32 max_buff, u8 pool) 7739 { 7740 MLXSW_REG_ZERO(sbmm, payload); 7741 mlxsw_reg_sbmm_prio_set(payload, prio); 7742 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 7743 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 7744 mlxsw_reg_sbmm_pool_set(payload, pool); 7745 } 7746 7747 /* SBSR - Shared Buffer Status Register 7748 * ------------------------------------ 7749 * The SBSR register retrieves the shared buffer occupancy according to 7750 * Port-Pool. Note that this register enables reading a large amount of data. 7751 * It is the user's responsibility to limit the amount of data to ensure the 7752 * response can match the maximum transfer unit. In case the response exceeds 7753 * the maximum transport unit, it will be truncated with no special notice. 7754 */ 7755 #define MLXSW_REG_SBSR_ID 0xB005 7756 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 7757 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 7758 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 7759 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 7760 MLXSW_REG_SBSR_REC_LEN * \ 7761 MLXSW_REG_SBSR_REC_MAX_COUNT) 7762 7763 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 7764 7765 /* reg_sbsr_clr 7766 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 7767 * field is cleared (and a new max value is tracked from the time the clear 7768 * was performed). 7769 * Access: OP 7770 */ 7771 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 7772 7773 /* reg_sbsr_ingress_port_mask 7774 * Bit vector for all ingress network ports. 7775 * Indicates which of the ports (for which the relevant bit is set) 7776 * are affected by the set operation. Configuration of any other port 7777 * does not change. 7778 * Access: Index 7779 */ 7780 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 7781 7782 /* reg_sbsr_pg_buff_mask 7783 * Bit vector for all switch priority groups. 7784 * Indicates which of the priorities (for which the relevant bit is set) 7785 * are affected by the set operation. Configuration of any other priority 7786 * does not change. 7787 * Range is 0..cap_max_pg_buffers - 1 7788 * Access: Index 7789 */ 7790 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 7791 7792 /* reg_sbsr_egress_port_mask 7793 * Bit vector for all egress network ports. 7794 * Indicates which of the ports (for which the relevant bit is set) 7795 * are affected by the set operation. Configuration of any other port 7796 * does not change. 7797 * Access: Index 7798 */ 7799 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 7800 7801 /* reg_sbsr_tclass_mask 7802 * Bit vector for all traffic classes. 7803 * Indicates which of the traffic classes (for which the relevant bit is 7804 * set) are affected by the set operation. Configuration of any other 7805 * traffic class does not change. 7806 * Range is 0..cap_max_tclass - 1 7807 * Access: Index 7808 */ 7809 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 7810 7811 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 7812 { 7813 MLXSW_REG_ZERO(sbsr, payload); 7814 mlxsw_reg_sbsr_clr_set(payload, clr); 7815 } 7816 7817 /* reg_sbsr_rec_buff_occupancy 7818 * Current buffer occupancy in cells. 7819 * Access: RO 7820 */ 7821 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7822 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 7823 7824 /* reg_sbsr_rec_max_buff_occupancy 7825 * Maximum value of buffer occupancy in cells monitored. Cleared by 7826 * writing to the clr field. 7827 * Access: RO 7828 */ 7829 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7830 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 7831 7832 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 7833 u32 *p_buff_occupancy, 7834 u32 *p_max_buff_occupancy) 7835 { 7836 *p_buff_occupancy = 7837 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 7838 *p_max_buff_occupancy = 7839 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 7840 } 7841 7842 /* SBIB - Shared Buffer Internal Buffer Register 7843 * --------------------------------------------- 7844 * The SBIB register configures per port buffers for internal use. The internal 7845 * buffers consume memory on the port buffers (note that the port buffers are 7846 * used also by PBMC). 7847 * 7848 * For Spectrum this is used for egress mirroring. 7849 */ 7850 #define MLXSW_REG_SBIB_ID 0xB006 7851 #define MLXSW_REG_SBIB_LEN 0x10 7852 7853 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 7854 7855 /* reg_sbib_local_port 7856 * Local port number 7857 * Not supported for CPU port and router port 7858 * Access: Index 7859 */ 7860 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 7861 7862 /* reg_sbib_buff_size 7863 * Units represented in cells 7864 * Allowed range is 0 to (cap_max_headroom_size - 1) 7865 * Default is 0 7866 * Access: RW 7867 */ 7868 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 7869 7870 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 7871 u32 buff_size) 7872 { 7873 MLXSW_REG_ZERO(sbib, payload); 7874 mlxsw_reg_sbib_local_port_set(payload, local_port); 7875 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 7876 } 7877 7878 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 7879 MLXSW_REG(sgcr), 7880 MLXSW_REG(spad), 7881 MLXSW_REG(smid), 7882 MLXSW_REG(sspr), 7883 MLXSW_REG(sfdat), 7884 MLXSW_REG(sfd), 7885 MLXSW_REG(sfn), 7886 MLXSW_REG(spms), 7887 MLXSW_REG(spvid), 7888 MLXSW_REG(spvm), 7889 MLXSW_REG(spaft), 7890 MLXSW_REG(sfgc), 7891 MLXSW_REG(sftr), 7892 MLXSW_REG(sfdf), 7893 MLXSW_REG(sldr), 7894 MLXSW_REG(slcr), 7895 MLXSW_REG(slcor), 7896 MLXSW_REG(spmlr), 7897 MLXSW_REG(svfa), 7898 MLXSW_REG(svpe), 7899 MLXSW_REG(sfmr), 7900 MLXSW_REG(spvmlr), 7901 MLXSW_REG(cwtp), 7902 MLXSW_REG(cwtpm), 7903 MLXSW_REG(ppbt), 7904 MLXSW_REG(pacl), 7905 MLXSW_REG(pagt), 7906 MLXSW_REG(ptar), 7907 MLXSW_REG(ppbs), 7908 MLXSW_REG(prcr), 7909 MLXSW_REG(pefa), 7910 MLXSW_REG(ptce2), 7911 MLXSW_REG(qpcr), 7912 MLXSW_REG(qtct), 7913 MLXSW_REG(qeec), 7914 MLXSW_REG(pmlp), 7915 MLXSW_REG(pmtu), 7916 MLXSW_REG(ptys), 7917 MLXSW_REG(ppad), 7918 MLXSW_REG(paos), 7919 MLXSW_REG(pfcc), 7920 MLXSW_REG(ppcnt), 7921 MLXSW_REG(plib), 7922 MLXSW_REG(pptb), 7923 MLXSW_REG(pbmc), 7924 MLXSW_REG(pspa), 7925 MLXSW_REG(htgt), 7926 MLXSW_REG(hpkt), 7927 MLXSW_REG(rgcr), 7928 MLXSW_REG(ritr), 7929 MLXSW_REG(rtar), 7930 MLXSW_REG(ratr), 7931 MLXSW_REG(rtdp), 7932 MLXSW_REG(rdpm), 7933 MLXSW_REG(ricnt), 7934 MLXSW_REG(rrcr), 7935 MLXSW_REG(ralta), 7936 MLXSW_REG(ralst), 7937 MLXSW_REG(raltb), 7938 MLXSW_REG(ralue), 7939 MLXSW_REG(rauht), 7940 MLXSW_REG(raleu), 7941 MLXSW_REG(rauhtd), 7942 MLXSW_REG(rigr2), 7943 MLXSW_REG(recr2), 7944 MLXSW_REG(rmft2), 7945 MLXSW_REG(mfcr), 7946 MLXSW_REG(mfsc), 7947 MLXSW_REG(mfsm), 7948 MLXSW_REG(mfsl), 7949 MLXSW_REG(mtcap), 7950 MLXSW_REG(mtmp), 7951 MLXSW_REG(mcia), 7952 MLXSW_REG(mpat), 7953 MLXSW_REG(mpar), 7954 MLXSW_REG(mrsr), 7955 MLXSW_REG(mlcr), 7956 MLXSW_REG(mpsc), 7957 MLXSW_REG(mcqi), 7958 MLXSW_REG(mcc), 7959 MLXSW_REG(mcda), 7960 MLXSW_REG(mgpc), 7961 MLXSW_REG(tigcr), 7962 MLXSW_REG(sbpr), 7963 MLXSW_REG(sbcm), 7964 MLXSW_REG(sbpm), 7965 MLXSW_REG(sbmm), 7966 MLXSW_REG(sbsr), 7967 MLXSW_REG(sbib), 7968 }; 7969 7970 static inline const char *mlxsw_reg_id_str(u16 reg_id) 7971 { 7972 const struct mlxsw_reg_info *reg_info; 7973 int i; 7974 7975 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 7976 reg_info = mlxsw_reg_infos[i]; 7977 if (reg_info->id == reg_id) 7978 return reg_info->name; 7979 } 7980 return "*UNKNOWN*"; 7981 } 7982 7983 /* PUDE - Port Up / Down Event 7984 * --------------------------- 7985 * Reports the operational state change of a port. 7986 */ 7987 #define MLXSW_REG_PUDE_LEN 0x10 7988 7989 /* reg_pude_swid 7990 * Switch partition ID with which to associate the port. 7991 * Access: Index 7992 */ 7993 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 7994 7995 /* reg_pude_local_port 7996 * Local port number. 7997 * Access: Index 7998 */ 7999 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 8000 8001 /* reg_pude_admin_status 8002 * Port administrative state (the desired state). 8003 * 1 - Up. 8004 * 2 - Down. 8005 * 3 - Up once. This means that in case of link failure, the port won't go 8006 * into polling mode, but will wait to be re-enabled by software. 8007 * 4 - Disabled by system. Can only be set by hardware. 8008 * Access: RO 8009 */ 8010 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 8011 8012 /* reg_pude_oper_status 8013 * Port operatioanl state. 8014 * 1 - Up. 8015 * 2 - Down. 8016 * 3 - Down by port failure. This means that the device will not let the 8017 * port up again until explicitly specified by software. 8018 * Access: RO 8019 */ 8020 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 8021 8022 #endif 8023