1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the names of the copyright holders nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") version 2 as published by the Free 22 * Software Foundation. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _MLXSW_REG_H 38 #define _MLXSW_REG_H 39 40 #include <linux/string.h> 41 #include <linux/bitops.h> 42 #include <linux/if_vlan.h> 43 44 #include "item.h" 45 #include "port.h" 46 47 struct mlxsw_reg_info { 48 u16 id; 49 u16 len; /* In u8 */ 50 }; 51 52 #define MLXSW_REG(type) (&mlxsw_reg_##type) 53 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 54 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 55 56 /* SGCR - Switch General Configuration Register 57 * -------------------------------------------- 58 * This register is used for configuration of the switch capabilities. 59 */ 60 #define MLXSW_REG_SGCR_ID 0x2000 61 #define MLXSW_REG_SGCR_LEN 0x10 62 63 static const struct mlxsw_reg_info mlxsw_reg_sgcr = { 64 .id = MLXSW_REG_SGCR_ID, 65 .len = MLXSW_REG_SGCR_LEN, 66 }; 67 68 /* reg_sgcr_llb 69 * Link Local Broadcast (Default=0) 70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 71 * packets and ignore the IGMP snooping entries. 72 * Access: RW 73 */ 74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 75 76 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 77 { 78 MLXSW_REG_ZERO(sgcr, payload); 79 mlxsw_reg_sgcr_llb_set(payload, !!llb); 80 } 81 82 /* SPAD - Switch Physical Address Register 83 * --------------------------------------- 84 * The SPAD register configures the switch physical MAC address. 85 */ 86 #define MLXSW_REG_SPAD_ID 0x2002 87 #define MLXSW_REG_SPAD_LEN 0x10 88 89 static const struct mlxsw_reg_info mlxsw_reg_spad = { 90 .id = MLXSW_REG_SPAD_ID, 91 .len = MLXSW_REG_SPAD_LEN, 92 }; 93 94 /* reg_spad_base_mac 95 * Base MAC address for the switch partitions. 96 * Per switch partition MAC address is equal to: 97 * base_mac + swid 98 * Access: RW 99 */ 100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 101 102 /* SMID - Switch Multicast ID 103 * -------------------------- 104 * The MID record maps from a MID (Multicast ID), which is a unique identifier 105 * of the multicast group within the stacking domain, into a list of local 106 * ports into which the packet is replicated. 107 */ 108 #define MLXSW_REG_SMID_ID 0x2007 109 #define MLXSW_REG_SMID_LEN 0x240 110 111 static const struct mlxsw_reg_info mlxsw_reg_smid = { 112 .id = MLXSW_REG_SMID_ID, 113 .len = MLXSW_REG_SMID_LEN, 114 }; 115 116 /* reg_smid_swid 117 * Switch partition ID. 118 * Access: Index 119 */ 120 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 121 122 /* reg_smid_mid 123 * Multicast identifier - global identifier that represents the multicast group 124 * across all devices. 125 * Access: Index 126 */ 127 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 128 129 /* reg_smid_port 130 * Local port memebership (1 bit per port). 131 * Access: RW 132 */ 133 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 134 135 /* reg_smid_port_mask 136 * Local port mask (1 bit per port). 137 * Access: W 138 */ 139 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 140 141 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 142 u8 port, bool set) 143 { 144 MLXSW_REG_ZERO(smid, payload); 145 mlxsw_reg_smid_swid_set(payload, 0); 146 mlxsw_reg_smid_mid_set(payload, mid); 147 mlxsw_reg_smid_port_set(payload, port, set); 148 mlxsw_reg_smid_port_mask_set(payload, port, 1); 149 } 150 151 /* SSPR - Switch System Port Record Register 152 * ----------------------------------------- 153 * Configures the system port to local port mapping. 154 */ 155 #define MLXSW_REG_SSPR_ID 0x2008 156 #define MLXSW_REG_SSPR_LEN 0x8 157 158 static const struct mlxsw_reg_info mlxsw_reg_sspr = { 159 .id = MLXSW_REG_SSPR_ID, 160 .len = MLXSW_REG_SSPR_LEN, 161 }; 162 163 /* reg_sspr_m 164 * Master - if set, then the record describes the master system port. 165 * This is needed in case a local port is mapped into several system ports 166 * (for multipathing). That number will be reported as the source system 167 * port when packets are forwarded to the CPU. Only one master port is allowed 168 * per local port. 169 * 170 * Note: Must be set for Spectrum. 171 * Access: RW 172 */ 173 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 174 175 /* reg_sspr_local_port 176 * Local port number. 177 * 178 * Access: RW 179 */ 180 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 181 182 /* reg_sspr_sub_port 183 * Virtual port within the physical port. 184 * Should be set to 0 when virtual ports are not enabled on the port. 185 * 186 * Access: RW 187 */ 188 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 189 190 /* reg_sspr_system_port 191 * Unique identifier within the stacking domain that represents all the ports 192 * that are available in the system (external ports). 193 * 194 * Currently, only single-ASIC configurations are supported, so we default to 195 * 1:1 mapping between system ports and local ports. 196 * Access: Index 197 */ 198 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 199 200 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 201 { 202 MLXSW_REG_ZERO(sspr, payload); 203 mlxsw_reg_sspr_m_set(payload, 1); 204 mlxsw_reg_sspr_local_port_set(payload, local_port); 205 mlxsw_reg_sspr_sub_port_set(payload, 0); 206 mlxsw_reg_sspr_system_port_set(payload, local_port); 207 } 208 209 /* SFDAT - Switch Filtering Database Aging Time 210 * -------------------------------------------- 211 * Controls the Switch aging time. Aging time is able to be set per Switch 212 * Partition. 213 */ 214 #define MLXSW_REG_SFDAT_ID 0x2009 215 #define MLXSW_REG_SFDAT_LEN 0x8 216 217 static const struct mlxsw_reg_info mlxsw_reg_sfdat = { 218 .id = MLXSW_REG_SFDAT_ID, 219 .len = MLXSW_REG_SFDAT_LEN, 220 }; 221 222 /* reg_sfdat_swid 223 * Switch partition ID. 224 * Access: Index 225 */ 226 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 227 228 /* reg_sfdat_age_time 229 * Aging time in seconds 230 * Min - 10 seconds 231 * Max - 1,000,000 seconds 232 * Default is 300 seconds. 233 * Access: RW 234 */ 235 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 236 237 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 238 { 239 MLXSW_REG_ZERO(sfdat, payload); 240 mlxsw_reg_sfdat_swid_set(payload, 0); 241 mlxsw_reg_sfdat_age_time_set(payload, age_time); 242 } 243 244 /* SFD - Switch Filtering Database 245 * ------------------------------- 246 * The following register defines the access to the filtering database. 247 * The register supports querying, adding, removing and modifying the database. 248 * The access is optimized for bulk updates in which case more than one 249 * FDB record is present in the same command. 250 */ 251 #define MLXSW_REG_SFD_ID 0x200A 252 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 253 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 254 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 255 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 256 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 257 258 static const struct mlxsw_reg_info mlxsw_reg_sfd = { 259 .id = MLXSW_REG_SFD_ID, 260 .len = MLXSW_REG_SFD_LEN, 261 }; 262 263 /* reg_sfd_swid 264 * Switch partition ID for queries. Reserved on Write. 265 * Access: Index 266 */ 267 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 268 269 enum mlxsw_reg_sfd_op { 270 /* Dump entire FDB a (process according to record_locator) */ 271 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 272 /* Query records by {MAC, VID/FID} value */ 273 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 274 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 275 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 276 /* Test. Response indicates if each of the records could be 277 * added to the FDB. 278 */ 279 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 280 /* Add/modify. Aged-out records cannot be added. This command removes 281 * the learning notification of the {MAC, VID/FID}. Response includes 282 * the entries that were added to the FDB. 283 */ 284 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 285 /* Remove record by {MAC, VID/FID}. This command also removes 286 * the learning notification and aged-out notifications 287 * of the {MAC, VID/FID}. The response provides current (pre-removal) 288 * entries as non-aged-out. 289 */ 290 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 291 /* Remove learned notification by {MAC, VID/FID}. The response provides 292 * the removed learning notification. 293 */ 294 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 295 }; 296 297 /* reg_sfd_op 298 * Operation. 299 * Access: OP 300 */ 301 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 302 303 /* reg_sfd_record_locator 304 * Used for querying the FDB. Use record_locator=0 to initiate the 305 * query. When a record is returned, a new record_locator is 306 * returned to be used in the subsequent query. 307 * Reserved for database update. 308 * Access: Index 309 */ 310 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 311 312 /* reg_sfd_num_rec 313 * Request: Number of records to read/add/modify/remove 314 * Response: Number of records read/added/replaced/removed 315 * See above description for more details. 316 * Ranges 0..64 317 * Access: RW 318 */ 319 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 320 321 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 322 u32 record_locator) 323 { 324 MLXSW_REG_ZERO(sfd, payload); 325 mlxsw_reg_sfd_op_set(payload, op); 326 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 327 } 328 329 /* reg_sfd_rec_swid 330 * Switch partition ID. 331 * Access: Index 332 */ 333 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 334 MLXSW_REG_SFD_REC_LEN, 0x00, false); 335 336 enum mlxsw_reg_sfd_rec_type { 337 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 338 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 339 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 340 }; 341 342 /* reg_sfd_rec_type 343 * FDB record type. 344 * Access: RW 345 */ 346 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 347 MLXSW_REG_SFD_REC_LEN, 0x00, false); 348 349 enum mlxsw_reg_sfd_rec_policy { 350 /* Replacement disabled, aging disabled. */ 351 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 352 /* (mlag remote): Replacement enabled, aging disabled, 353 * learning notification enabled on this port. 354 */ 355 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 356 /* (ingress device): Replacement enabled, aging enabled. */ 357 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 358 }; 359 360 /* reg_sfd_rec_policy 361 * Policy. 362 * Access: RW 363 */ 364 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 365 MLXSW_REG_SFD_REC_LEN, 0x00, false); 366 367 /* reg_sfd_rec_a 368 * Activity. Set for new static entries. Set for static entries if a frame SMAC 369 * lookup hits on the entry. 370 * To clear the a bit, use "query and clear activity" op. 371 * Access: RO 372 */ 373 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 374 MLXSW_REG_SFD_REC_LEN, 0x00, false); 375 376 /* reg_sfd_rec_mac 377 * MAC address. 378 * Access: Index 379 */ 380 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 381 MLXSW_REG_SFD_REC_LEN, 0x02); 382 383 enum mlxsw_reg_sfd_rec_action { 384 /* forward */ 385 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 386 /* forward and trap, trap_id is FDB_TRAP */ 387 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 388 /* trap and do not forward, trap_id is FDB_TRAP */ 389 MLXSW_REG_SFD_REC_ACTION_TRAP = 3, 390 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 391 }; 392 393 /* reg_sfd_rec_action 394 * Action to apply on the packet. 395 * Note: Dynamic entries can only be configured with NOP action. 396 * Access: RW 397 */ 398 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 399 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 400 401 /* reg_sfd_uc_sub_port 402 * VEPA channel on local port. 403 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 404 * VEPA is not enabled. 405 * Access: RW 406 */ 407 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 408 MLXSW_REG_SFD_REC_LEN, 0x08, false); 409 410 /* reg_sfd_uc_fid_vid 411 * Filtering ID or VLAN ID 412 * For SwitchX and SwitchX-2: 413 * - Dynamic entries (policy 2,3) use FID 414 * - Static entries (policy 0) use VID 415 * - When independent learning is configured, VID=FID 416 * For Spectrum: use FID for both Dynamic and Static entries. 417 * VID should not be used. 418 * Access: Index 419 */ 420 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 421 MLXSW_REG_SFD_REC_LEN, 0x08, false); 422 423 /* reg_sfd_uc_system_port 424 * Unique port identifier for the final destination of the packet. 425 * Access: RW 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 428 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 429 430 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 431 enum mlxsw_reg_sfd_rec_type rec_type, 432 const char *mac, 433 enum mlxsw_reg_sfd_rec_action action) 434 { 435 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 436 437 if (rec_index >= num_rec) 438 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 439 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 440 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 441 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 442 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 443 } 444 445 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 446 enum mlxsw_reg_sfd_rec_policy policy, 447 const char *mac, u16 fid_vid, 448 enum mlxsw_reg_sfd_rec_action action, 449 u8 local_port) 450 { 451 mlxsw_reg_sfd_rec_pack(payload, rec_index, 452 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 453 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 454 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 455 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 456 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 457 } 458 459 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 460 char *mac, u16 *p_fid_vid, 461 u8 *p_local_port) 462 { 463 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 464 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 465 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 466 } 467 468 /* reg_sfd_uc_lag_sub_port 469 * LAG sub port. 470 * Must be 0 if multichannel VEPA is not enabled. 471 * Access: RW 472 */ 473 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 474 MLXSW_REG_SFD_REC_LEN, 0x08, false); 475 476 /* reg_sfd_uc_lag_fid_vid 477 * Filtering ID or VLAN ID 478 * For SwitchX and SwitchX-2: 479 * - Dynamic entries (policy 2,3) use FID 480 * - Static entries (policy 0) use VID 481 * - When independent learning is configured, VID=FID 482 * For Spectrum: use FID for both Dynamic and Static entries. 483 * VID should not be used. 484 * Access: Index 485 */ 486 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 487 MLXSW_REG_SFD_REC_LEN, 0x08, false); 488 489 /* reg_sfd_uc_lag_lag_vid 490 * Indicates VID in case of vFIDs. Reserved for FIDs. 491 * Access: RW 492 */ 493 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 494 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 495 496 /* reg_sfd_uc_lag_lag_id 497 * LAG Identifier - pointer into the LAG descriptor table. 498 * Access: RW 499 */ 500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 501 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 502 503 static inline void 504 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 505 enum mlxsw_reg_sfd_rec_policy policy, 506 const char *mac, u16 fid_vid, 507 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 508 u16 lag_id) 509 { 510 mlxsw_reg_sfd_rec_pack(payload, rec_index, 511 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 512 mac, action); 513 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 514 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 515 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 516 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 517 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 518 } 519 520 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 521 char *mac, u16 *p_vid, 522 u16 *p_lag_id) 523 { 524 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 525 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 526 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 527 } 528 529 /* reg_sfd_mc_pgi 530 * 531 * Multicast port group index - index into the port group table. 532 * Value 0x1FFF indicates the pgi should point to the MID entry. 533 * For Spectrum this value must be set to 0x1FFF 534 * Access: RW 535 */ 536 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 537 MLXSW_REG_SFD_REC_LEN, 0x08, false); 538 539 /* reg_sfd_mc_fid_vid 540 * 541 * Filtering ID or VLAN ID 542 * Access: Index 543 */ 544 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 545 MLXSW_REG_SFD_REC_LEN, 0x08, false); 546 547 /* reg_sfd_mc_mid 548 * 549 * Multicast identifier - global identifier that represents the multicast 550 * group across all devices. 551 * Access: RW 552 */ 553 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 554 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 555 556 static inline void 557 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 558 const char *mac, u16 fid_vid, 559 enum mlxsw_reg_sfd_rec_action action, u16 mid) 560 { 561 mlxsw_reg_sfd_rec_pack(payload, rec_index, 562 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 563 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 564 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 565 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 566 } 567 568 /* SFN - Switch FDB Notification Register 569 * ------------------------------------------- 570 * The switch provides notifications on newly learned FDB entries and 571 * aged out entries. The notifications can be polled by software. 572 */ 573 #define MLXSW_REG_SFN_ID 0x200B 574 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 575 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 576 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 577 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 578 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 579 580 static const struct mlxsw_reg_info mlxsw_reg_sfn = { 581 .id = MLXSW_REG_SFN_ID, 582 .len = MLXSW_REG_SFN_LEN, 583 }; 584 585 /* reg_sfn_swid 586 * Switch partition ID. 587 * Access: Index 588 */ 589 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 590 591 /* reg_sfn_num_rec 592 * Request: Number of learned notifications and aged-out notification 593 * records requested. 594 * Response: Number of notification records returned (must be smaller 595 * than or equal to the value requested) 596 * Ranges 0..64 597 * Access: OP 598 */ 599 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 600 601 static inline void mlxsw_reg_sfn_pack(char *payload) 602 { 603 MLXSW_REG_ZERO(sfn, payload); 604 mlxsw_reg_sfn_swid_set(payload, 0); 605 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 606 } 607 608 /* reg_sfn_rec_swid 609 * Switch partition ID. 610 * Access: RO 611 */ 612 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 613 MLXSW_REG_SFN_REC_LEN, 0x00, false); 614 615 enum mlxsw_reg_sfn_rec_type { 616 /* MAC addresses learned on a regular port. */ 617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 618 /* MAC addresses learned on a LAG port. */ 619 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 620 /* Aged-out MAC address on a regular port. */ 621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 622 /* Aged-out MAC address on a LAG port. */ 623 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 624 }; 625 626 /* reg_sfn_rec_type 627 * Notification record type. 628 * Access: RO 629 */ 630 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 631 MLXSW_REG_SFN_REC_LEN, 0x00, false); 632 633 /* reg_sfn_rec_mac 634 * MAC address. 635 * Access: RO 636 */ 637 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 638 MLXSW_REG_SFN_REC_LEN, 0x02); 639 640 /* reg_sfn_mac_sub_port 641 * VEPA channel on the local port. 642 * 0 if multichannel VEPA is not enabled. 643 * Access: RO 644 */ 645 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 646 MLXSW_REG_SFN_REC_LEN, 0x08, false); 647 648 /* reg_sfn_mac_fid 649 * Filtering identifier. 650 * Access: RO 651 */ 652 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 653 MLXSW_REG_SFN_REC_LEN, 0x08, false); 654 655 /* reg_sfn_mac_system_port 656 * Unique port identifier for the final destination of the packet. 657 * Access: RO 658 */ 659 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 660 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 661 662 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 663 char *mac, u16 *p_vid, 664 u8 *p_local_port) 665 { 666 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 667 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 668 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 669 } 670 671 /* reg_sfn_mac_lag_lag_id 672 * LAG ID (pointer into the LAG descriptor table). 673 * Access: RO 674 */ 675 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 676 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 677 678 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 679 char *mac, u16 *p_vid, 680 u16 *p_lag_id) 681 { 682 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 683 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 684 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 685 } 686 687 /* SPMS - Switch Port MSTP/RSTP State Register 688 * ------------------------------------------- 689 * Configures the spanning tree state of a physical port. 690 */ 691 #define MLXSW_REG_SPMS_ID 0x200D 692 #define MLXSW_REG_SPMS_LEN 0x404 693 694 static const struct mlxsw_reg_info mlxsw_reg_spms = { 695 .id = MLXSW_REG_SPMS_ID, 696 .len = MLXSW_REG_SPMS_LEN, 697 }; 698 699 /* reg_spms_local_port 700 * Local port number. 701 * Access: Index 702 */ 703 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 704 705 enum mlxsw_reg_spms_state { 706 MLXSW_REG_SPMS_STATE_NO_CHANGE, 707 MLXSW_REG_SPMS_STATE_DISCARDING, 708 MLXSW_REG_SPMS_STATE_LEARNING, 709 MLXSW_REG_SPMS_STATE_FORWARDING, 710 }; 711 712 /* reg_spms_state 713 * Spanning tree state of each VLAN ID (VID) of the local port. 714 * 0 - Do not change spanning tree state (used only when writing). 715 * 1 - Discarding. No learning or forwarding to/from this port (default). 716 * 2 - Learning. Port is learning, but not forwarding. 717 * 3 - Forwarding. Port is learning and forwarding. 718 * Access: RW 719 */ 720 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 721 722 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 723 { 724 MLXSW_REG_ZERO(spms, payload); 725 mlxsw_reg_spms_local_port_set(payload, local_port); 726 } 727 728 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 729 enum mlxsw_reg_spms_state state) 730 { 731 mlxsw_reg_spms_state_set(payload, vid, state); 732 } 733 734 /* SPVID - Switch Port VID 735 * ----------------------- 736 * The switch port VID configures the default VID for a port. 737 */ 738 #define MLXSW_REG_SPVID_ID 0x200E 739 #define MLXSW_REG_SPVID_LEN 0x08 740 741 static const struct mlxsw_reg_info mlxsw_reg_spvid = { 742 .id = MLXSW_REG_SPVID_ID, 743 .len = MLXSW_REG_SPVID_LEN, 744 }; 745 746 /* reg_spvid_local_port 747 * Local port number. 748 * Access: Index 749 */ 750 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 751 752 /* reg_spvid_sub_port 753 * Virtual port within the physical port. 754 * Should be set to 0 when virtual ports are not enabled on the port. 755 * Access: Index 756 */ 757 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 758 759 /* reg_spvid_pvid 760 * Port default VID 761 * Access: RW 762 */ 763 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 764 765 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 766 { 767 MLXSW_REG_ZERO(spvid, payload); 768 mlxsw_reg_spvid_local_port_set(payload, local_port); 769 mlxsw_reg_spvid_pvid_set(payload, pvid); 770 } 771 772 /* SPVM - Switch Port VLAN Membership 773 * ---------------------------------- 774 * The Switch Port VLAN Membership register configures the VLAN membership 775 * of a port in a VLAN denoted by VID. VLAN membership is managed per 776 * virtual port. The register can be used to add and remove VID(s) from a port. 777 */ 778 #define MLXSW_REG_SPVM_ID 0x200F 779 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 780 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 781 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256 782 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 783 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 784 785 static const struct mlxsw_reg_info mlxsw_reg_spvm = { 786 .id = MLXSW_REG_SPVM_ID, 787 .len = MLXSW_REG_SPVM_LEN, 788 }; 789 790 /* reg_spvm_pt 791 * Priority tagged. If this bit is set, packets forwarded to the port with 792 * untagged VLAN membership (u bit is set) will be tagged with priority tag 793 * (VID=0) 794 * Access: RW 795 */ 796 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 797 798 /* reg_spvm_pte 799 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 800 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 801 * Access: WO 802 */ 803 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 804 805 /* reg_spvm_local_port 806 * Local port number. 807 * Access: Index 808 */ 809 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 810 811 /* reg_spvm_sub_port 812 * Virtual port within the physical port. 813 * Should be set to 0 when virtual ports are not enabled on the port. 814 * Access: Index 815 */ 816 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 817 818 /* reg_spvm_num_rec 819 * Number of records to update. Each record contains: i, e, u, vid. 820 * Access: OP 821 */ 822 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 823 824 /* reg_spvm_rec_i 825 * Ingress membership in VLAN ID. 826 * Access: Index 827 */ 828 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 829 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 830 MLXSW_REG_SPVM_REC_LEN, 0, false); 831 832 /* reg_spvm_rec_e 833 * Egress membership in VLAN ID. 834 * Access: Index 835 */ 836 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 837 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 838 MLXSW_REG_SPVM_REC_LEN, 0, false); 839 840 /* reg_spvm_rec_u 841 * Untagged - port is an untagged member - egress transmission uses untagged 842 * frames on VID<n> 843 * Access: Index 844 */ 845 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 846 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 847 MLXSW_REG_SPVM_REC_LEN, 0, false); 848 849 /* reg_spvm_rec_vid 850 * Egress membership in VLAN ID. 851 * Access: Index 852 */ 853 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 854 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 855 MLXSW_REG_SPVM_REC_LEN, 0, false); 856 857 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 858 u16 vid_begin, u16 vid_end, 859 bool is_member, bool untagged) 860 { 861 int size = vid_end - vid_begin + 1; 862 int i; 863 864 MLXSW_REG_ZERO(spvm, payload); 865 mlxsw_reg_spvm_local_port_set(payload, local_port); 866 mlxsw_reg_spvm_num_rec_set(payload, size); 867 868 for (i = 0; i < size; i++) { 869 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 870 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 871 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 872 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 873 } 874 } 875 876 /* SFGC - Switch Flooding Group Configuration 877 * ------------------------------------------ 878 * The following register controls the association of flooding tables and MIDs 879 * to packet types used for flooding. 880 */ 881 #define MLXSW_REG_SFGC_ID 0x2011 882 #define MLXSW_REG_SFGC_LEN 0x10 883 884 static const struct mlxsw_reg_info mlxsw_reg_sfgc = { 885 .id = MLXSW_REG_SFGC_ID, 886 .len = MLXSW_REG_SFGC_LEN, 887 }; 888 889 enum mlxsw_reg_sfgc_type { 890 MLXSW_REG_SFGC_TYPE_BROADCAST, 891 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 892 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 893 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 894 MLXSW_REG_SFGC_TYPE_RESERVED, 895 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 896 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 897 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 898 MLXSW_REG_SFGC_TYPE_MAX, 899 }; 900 901 /* reg_sfgc_type 902 * The traffic type to reach the flooding table. 903 * Access: Index 904 */ 905 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 906 907 enum mlxsw_reg_sfgc_bridge_type { 908 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 909 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 910 }; 911 912 /* reg_sfgc_bridge_type 913 * Access: Index 914 * 915 * Note: SwitchX-2 only supports 802.1Q mode. 916 */ 917 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 918 919 enum mlxsw_flood_table_type { 920 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 921 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 922 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 923 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3, 924 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 925 }; 926 927 /* reg_sfgc_table_type 928 * See mlxsw_flood_table_type 929 * Access: RW 930 * 931 * Note: FID offset and FID types are not supported in SwitchX-2. 932 */ 933 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 934 935 /* reg_sfgc_flood_table 936 * Flooding table index to associate with the specific type on the specific 937 * switch partition. 938 * Access: RW 939 */ 940 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 941 942 /* reg_sfgc_mid 943 * The multicast ID for the swid. Not supported for Spectrum 944 * Access: RW 945 */ 946 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 947 948 /* reg_sfgc_counter_set_type 949 * Counter Set Type for flow counters. 950 * Access: RW 951 */ 952 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 953 954 /* reg_sfgc_counter_index 955 * Counter Index for flow counters. 956 * Access: RW 957 */ 958 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 959 960 static inline void 961 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 962 enum mlxsw_reg_sfgc_bridge_type bridge_type, 963 enum mlxsw_flood_table_type table_type, 964 unsigned int flood_table) 965 { 966 MLXSW_REG_ZERO(sfgc, payload); 967 mlxsw_reg_sfgc_type_set(payload, type); 968 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 969 mlxsw_reg_sfgc_table_type_set(payload, table_type); 970 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 971 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 972 } 973 974 /* SFTR - Switch Flooding Table Register 975 * ------------------------------------- 976 * The switch flooding table is used for flooding packet replication. The table 977 * defines a bit mask of ports for packet replication. 978 */ 979 #define MLXSW_REG_SFTR_ID 0x2012 980 #define MLXSW_REG_SFTR_LEN 0x420 981 982 static const struct mlxsw_reg_info mlxsw_reg_sftr = { 983 .id = MLXSW_REG_SFTR_ID, 984 .len = MLXSW_REG_SFTR_LEN, 985 }; 986 987 /* reg_sftr_swid 988 * Switch partition ID with which to associate the port. 989 * Access: Index 990 */ 991 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 992 993 /* reg_sftr_flood_table 994 * Flooding table index to associate with the specific type on the specific 995 * switch partition. 996 * Access: Index 997 */ 998 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 999 1000 /* reg_sftr_index 1001 * Index. Used as an index into the Flooding Table in case the table is 1002 * configured to use VID / FID or FID Offset. 1003 * Access: Index 1004 */ 1005 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1006 1007 /* reg_sftr_table_type 1008 * See mlxsw_flood_table_type 1009 * Access: RW 1010 */ 1011 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1012 1013 /* reg_sftr_range 1014 * Range of entries to update 1015 * Access: Index 1016 */ 1017 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1018 1019 /* reg_sftr_port 1020 * Local port membership (1 bit per port). 1021 * Access: RW 1022 */ 1023 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1024 1025 /* reg_sftr_cpu_port_mask 1026 * CPU port mask (1 bit per port). 1027 * Access: W 1028 */ 1029 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1030 1031 static inline void mlxsw_reg_sftr_pack(char *payload, 1032 unsigned int flood_table, 1033 unsigned int index, 1034 enum mlxsw_flood_table_type table_type, 1035 unsigned int range, u8 port, bool set) 1036 { 1037 MLXSW_REG_ZERO(sftr, payload); 1038 mlxsw_reg_sftr_swid_set(payload, 0); 1039 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1040 mlxsw_reg_sftr_index_set(payload, index); 1041 mlxsw_reg_sftr_table_type_set(payload, table_type); 1042 mlxsw_reg_sftr_range_set(payload, range); 1043 mlxsw_reg_sftr_port_set(payload, port, set); 1044 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1045 } 1046 1047 /* SLDR - Switch LAG Descriptor Register 1048 * ----------------------------------------- 1049 * The switch LAG descriptor register is populated by LAG descriptors. 1050 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1051 * max_lag-1. 1052 */ 1053 #define MLXSW_REG_SLDR_ID 0x2014 1054 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1055 1056 static const struct mlxsw_reg_info mlxsw_reg_sldr = { 1057 .id = MLXSW_REG_SLDR_ID, 1058 .len = MLXSW_REG_SLDR_LEN, 1059 }; 1060 1061 enum mlxsw_reg_sldr_op { 1062 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1063 MLXSW_REG_SLDR_OP_LAG_CREATE, 1064 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1065 /* Ports that appear in the list have the Distributor enabled */ 1066 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1067 /* Removes ports from the disributor list */ 1068 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1069 }; 1070 1071 /* reg_sldr_op 1072 * Operation. 1073 * Access: RW 1074 */ 1075 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1076 1077 /* reg_sldr_lag_id 1078 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1079 * Access: Index 1080 */ 1081 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1082 1083 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1084 { 1085 MLXSW_REG_ZERO(sldr, payload); 1086 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1087 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1088 } 1089 1090 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1091 { 1092 MLXSW_REG_ZERO(sldr, payload); 1093 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1094 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1095 } 1096 1097 /* reg_sldr_num_ports 1098 * The number of member ports of the LAG. 1099 * Reserved for Create / Destroy operations 1100 * For Add / Remove operations - indicates the number of ports in the list. 1101 * Access: RW 1102 */ 1103 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1104 1105 /* reg_sldr_system_port 1106 * System port. 1107 * Access: RW 1108 */ 1109 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1110 1111 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1112 u8 local_port) 1113 { 1114 MLXSW_REG_ZERO(sldr, payload); 1115 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1116 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1117 mlxsw_reg_sldr_num_ports_set(payload, 1); 1118 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1119 } 1120 1121 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1122 u8 local_port) 1123 { 1124 MLXSW_REG_ZERO(sldr, payload); 1125 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1126 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1127 mlxsw_reg_sldr_num_ports_set(payload, 1); 1128 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1129 } 1130 1131 /* SLCR - Switch LAG Configuration 2 Register 1132 * ------------------------------------------- 1133 * The Switch LAG Configuration register is used for configuring the 1134 * LAG properties of the switch. 1135 */ 1136 #define MLXSW_REG_SLCR_ID 0x2015 1137 #define MLXSW_REG_SLCR_LEN 0x10 1138 1139 static const struct mlxsw_reg_info mlxsw_reg_slcr = { 1140 .id = MLXSW_REG_SLCR_ID, 1141 .len = MLXSW_REG_SLCR_LEN, 1142 }; 1143 1144 enum mlxsw_reg_slcr_pp { 1145 /* Global Configuration (for all ports) */ 1146 MLXSW_REG_SLCR_PP_GLOBAL, 1147 /* Per port configuration, based on local_port field */ 1148 MLXSW_REG_SLCR_PP_PER_PORT, 1149 }; 1150 1151 /* reg_slcr_pp 1152 * Per Port Configuration 1153 * Note: Reading at Global mode results in reading port 1 configuration. 1154 * Access: Index 1155 */ 1156 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1157 1158 /* reg_slcr_local_port 1159 * Local port number 1160 * Supported from CPU port 1161 * Not supported from router port 1162 * Reserved when pp = Global Configuration 1163 * Access: Index 1164 */ 1165 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1166 1167 enum mlxsw_reg_slcr_type { 1168 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1169 MLXSW_REG_SLCR_TYPE_XOR, 1170 MLXSW_REG_SLCR_TYPE_RANDOM, 1171 }; 1172 1173 /* reg_slcr_type 1174 * Hash type 1175 * Access: RW 1176 */ 1177 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1178 1179 /* Ingress port */ 1180 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1181 /* SMAC - for IPv4 and IPv6 packets */ 1182 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1183 /* SMAC - for non-IP packets */ 1184 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1185 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1186 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1187 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1188 /* DMAC - for IPv4 and IPv6 packets */ 1189 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1190 /* DMAC - for non-IP packets */ 1191 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1192 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1193 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1194 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1195 /* Ethertype - for IPv4 and IPv6 packets */ 1196 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1197 /* Ethertype - for non-IP packets */ 1198 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1199 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1200 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1201 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1202 /* VLAN ID - for IPv4 and IPv6 packets */ 1203 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1204 /* VLAN ID - for non-IP packets */ 1205 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1206 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1207 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1208 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1209 /* Source IP address (can be IPv4 or IPv6) */ 1210 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1211 /* Destination IP address (can be IPv4 or IPv6) */ 1212 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1213 /* TCP/UDP source port */ 1214 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1215 /* TCP/UDP destination port*/ 1216 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1217 /* IPv4 Protocol/IPv6 Next Header */ 1218 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1219 /* IPv6 Flow label */ 1220 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1221 /* SID - FCoE source ID */ 1222 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1223 /* DID - FCoE destination ID */ 1224 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1225 /* OXID - FCoE originator exchange ID */ 1226 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1227 /* Destination QP number - for RoCE packets */ 1228 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1229 1230 /* reg_slcr_lag_hash 1231 * LAG hashing configuration. This is a bitmask, in which each set 1232 * bit includes the corresponding item in the LAG hash calculation. 1233 * The default lag_hash contains SMAC, DMAC, VLANID and 1234 * Ethertype (for all packet types). 1235 * Access: RW 1236 */ 1237 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1238 1239 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1240 { 1241 MLXSW_REG_ZERO(slcr, payload); 1242 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1243 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR); 1244 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1245 } 1246 1247 /* SLCOR - Switch LAG Collector Register 1248 * ------------------------------------- 1249 * The Switch LAG Collector register controls the Local Port membership 1250 * in a LAG and enablement of the collector. 1251 */ 1252 #define MLXSW_REG_SLCOR_ID 0x2016 1253 #define MLXSW_REG_SLCOR_LEN 0x10 1254 1255 static const struct mlxsw_reg_info mlxsw_reg_slcor = { 1256 .id = MLXSW_REG_SLCOR_ID, 1257 .len = MLXSW_REG_SLCOR_LEN, 1258 }; 1259 1260 enum mlxsw_reg_slcor_col { 1261 /* Port is added with collector disabled */ 1262 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1263 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1264 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1265 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1266 }; 1267 1268 /* reg_slcor_col 1269 * Collector configuration 1270 * Access: RW 1271 */ 1272 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1273 1274 /* reg_slcor_local_port 1275 * Local port number 1276 * Not supported for CPU port 1277 * Access: Index 1278 */ 1279 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1280 1281 /* reg_slcor_lag_id 1282 * LAG Identifier. Index into the LAG descriptor table. 1283 * Access: Index 1284 */ 1285 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1286 1287 /* reg_slcor_port_index 1288 * Port index in the LAG list. Only valid on Add Port to LAG col. 1289 * Valid range is from 0 to cap_max_lag_members-1 1290 * Access: RW 1291 */ 1292 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1293 1294 static inline void mlxsw_reg_slcor_pack(char *payload, 1295 u8 local_port, u16 lag_id, 1296 enum mlxsw_reg_slcor_col col) 1297 { 1298 MLXSW_REG_ZERO(slcor, payload); 1299 mlxsw_reg_slcor_col_set(payload, col); 1300 mlxsw_reg_slcor_local_port_set(payload, local_port); 1301 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1302 } 1303 1304 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1305 u8 local_port, u16 lag_id, 1306 u8 port_index) 1307 { 1308 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1309 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1310 mlxsw_reg_slcor_port_index_set(payload, port_index); 1311 } 1312 1313 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1314 u8 local_port, u16 lag_id) 1315 { 1316 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1317 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1318 } 1319 1320 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1321 u8 local_port, u16 lag_id) 1322 { 1323 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1324 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1325 } 1326 1327 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1328 u8 local_port, u16 lag_id) 1329 { 1330 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1331 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1332 } 1333 1334 /* SPMLR - Switch Port MAC Learning Register 1335 * ----------------------------------------- 1336 * Controls the Switch MAC learning policy per port. 1337 */ 1338 #define MLXSW_REG_SPMLR_ID 0x2018 1339 #define MLXSW_REG_SPMLR_LEN 0x8 1340 1341 static const struct mlxsw_reg_info mlxsw_reg_spmlr = { 1342 .id = MLXSW_REG_SPMLR_ID, 1343 .len = MLXSW_REG_SPMLR_LEN, 1344 }; 1345 1346 /* reg_spmlr_local_port 1347 * Local port number. 1348 * Access: Index 1349 */ 1350 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1351 1352 /* reg_spmlr_sub_port 1353 * Virtual port within the physical port. 1354 * Should be set to 0 when virtual ports are not enabled on the port. 1355 * Access: Index 1356 */ 1357 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1358 1359 enum mlxsw_reg_spmlr_learn_mode { 1360 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1361 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1362 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1363 }; 1364 1365 /* reg_spmlr_learn_mode 1366 * Learning mode on the port. 1367 * 0 - Learning disabled. 1368 * 2 - Learning enabled. 1369 * 3 - Security mode. 1370 * 1371 * In security mode the switch does not learn MACs on the port, but uses the 1372 * SMAC to see if it exists on another ingress port. If so, the packet is 1373 * classified as a bad packet and is discarded unless the software registers 1374 * to receive port security error packets usign HPKT. 1375 */ 1376 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1377 1378 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1379 enum mlxsw_reg_spmlr_learn_mode mode) 1380 { 1381 MLXSW_REG_ZERO(spmlr, payload); 1382 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1383 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1384 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1385 } 1386 1387 /* SVFA - Switch VID to FID Allocation Register 1388 * -------------------------------------------- 1389 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1390 * virtualized ports. 1391 */ 1392 #define MLXSW_REG_SVFA_ID 0x201C 1393 #define MLXSW_REG_SVFA_LEN 0x10 1394 1395 static const struct mlxsw_reg_info mlxsw_reg_svfa = { 1396 .id = MLXSW_REG_SVFA_ID, 1397 .len = MLXSW_REG_SVFA_LEN, 1398 }; 1399 1400 /* reg_svfa_swid 1401 * Switch partition ID. 1402 * Access: Index 1403 */ 1404 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1405 1406 /* reg_svfa_local_port 1407 * Local port number. 1408 * Access: Index 1409 * 1410 * Note: Reserved for 802.1Q FIDs. 1411 */ 1412 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1413 1414 enum mlxsw_reg_svfa_mt { 1415 MLXSW_REG_SVFA_MT_VID_TO_FID, 1416 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1417 }; 1418 1419 /* reg_svfa_mapping_table 1420 * Mapping table: 1421 * 0 - VID to FID 1422 * 1 - {Port, VID} to FID 1423 * Access: Index 1424 * 1425 * Note: Reserved for SwitchX-2. 1426 */ 1427 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1428 1429 /* reg_svfa_v 1430 * Valid. 1431 * Valid if set. 1432 * Access: RW 1433 * 1434 * Note: Reserved for SwitchX-2. 1435 */ 1436 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1437 1438 /* reg_svfa_fid 1439 * Filtering ID. 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1443 1444 /* reg_svfa_vid 1445 * VLAN ID. 1446 * Access: Index 1447 */ 1448 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1449 1450 /* reg_svfa_counter_set_type 1451 * Counter set type for flow counters. 1452 * Access: RW 1453 * 1454 * Note: Reserved for SwitchX-2. 1455 */ 1456 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1457 1458 /* reg_svfa_counter_index 1459 * Counter index for flow counters. 1460 * Access: RW 1461 * 1462 * Note: Reserved for SwitchX-2. 1463 */ 1464 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1465 1466 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1467 enum mlxsw_reg_svfa_mt mt, bool valid, 1468 u16 fid, u16 vid) 1469 { 1470 MLXSW_REG_ZERO(svfa, payload); 1471 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1472 mlxsw_reg_svfa_swid_set(payload, 0); 1473 mlxsw_reg_svfa_local_port_set(payload, local_port); 1474 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1475 mlxsw_reg_svfa_v_set(payload, valid); 1476 mlxsw_reg_svfa_fid_set(payload, fid); 1477 mlxsw_reg_svfa_vid_set(payload, vid); 1478 } 1479 1480 /* SVPE - Switch Virtual-Port Enabling Register 1481 * -------------------------------------------- 1482 * Enables port virtualization. 1483 */ 1484 #define MLXSW_REG_SVPE_ID 0x201E 1485 #define MLXSW_REG_SVPE_LEN 0x4 1486 1487 static const struct mlxsw_reg_info mlxsw_reg_svpe = { 1488 .id = MLXSW_REG_SVPE_ID, 1489 .len = MLXSW_REG_SVPE_LEN, 1490 }; 1491 1492 /* reg_svpe_local_port 1493 * Local port number 1494 * Access: Index 1495 * 1496 * Note: CPU port is not supported (uses VLAN mode only). 1497 */ 1498 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1499 1500 /* reg_svpe_vp_en 1501 * Virtual port enable. 1502 * 0 - Disable, VLAN mode (VID to FID). 1503 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1504 * Access: RW 1505 */ 1506 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1507 1508 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1509 bool enable) 1510 { 1511 MLXSW_REG_ZERO(svpe, payload); 1512 mlxsw_reg_svpe_local_port_set(payload, local_port); 1513 mlxsw_reg_svpe_vp_en_set(payload, enable); 1514 } 1515 1516 /* SFMR - Switch FID Management Register 1517 * ------------------------------------- 1518 * Creates and configures FIDs. 1519 */ 1520 #define MLXSW_REG_SFMR_ID 0x201F 1521 #define MLXSW_REG_SFMR_LEN 0x18 1522 1523 static const struct mlxsw_reg_info mlxsw_reg_sfmr = { 1524 .id = MLXSW_REG_SFMR_ID, 1525 .len = MLXSW_REG_SFMR_LEN, 1526 }; 1527 1528 enum mlxsw_reg_sfmr_op { 1529 MLXSW_REG_SFMR_OP_CREATE_FID, 1530 MLXSW_REG_SFMR_OP_DESTROY_FID, 1531 }; 1532 1533 /* reg_sfmr_op 1534 * Operation. 1535 * 0 - Create or edit FID. 1536 * 1 - Destroy FID. 1537 * Access: WO 1538 */ 1539 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1540 1541 /* reg_sfmr_fid 1542 * Filtering ID. 1543 * Access: Index 1544 */ 1545 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1546 1547 /* reg_sfmr_fid_offset 1548 * FID offset. 1549 * Used to point into the flooding table selected by SFGC register if 1550 * the table is of type FID-Offset. Otherwise, this field is reserved. 1551 * Access: RW 1552 */ 1553 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1554 1555 /* reg_sfmr_vtfp 1556 * Valid Tunnel Flood Pointer. 1557 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1558 * Access: RW 1559 * 1560 * Note: Reserved for 802.1Q FIDs. 1561 */ 1562 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1563 1564 /* reg_sfmr_nve_tunnel_flood_ptr 1565 * Underlay Flooding and BC Pointer. 1566 * Used as a pointer to the first entry of the group based link lists of 1567 * flooding or BC entries (for NVE tunnels). 1568 * Access: RW 1569 */ 1570 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1571 1572 /* reg_sfmr_vv 1573 * VNI Valid. 1574 * If not set, then vni is reserved. 1575 * Access: RW 1576 * 1577 * Note: Reserved for 802.1Q FIDs. 1578 */ 1579 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1580 1581 /* reg_sfmr_vni 1582 * Virtual Network Identifier. 1583 * Access: RW 1584 * 1585 * Note: A given VNI can only be assigned to one FID. 1586 */ 1587 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1588 1589 static inline void mlxsw_reg_sfmr_pack(char *payload, 1590 enum mlxsw_reg_sfmr_op op, u16 fid, 1591 u16 fid_offset) 1592 { 1593 MLXSW_REG_ZERO(sfmr, payload); 1594 mlxsw_reg_sfmr_op_set(payload, op); 1595 mlxsw_reg_sfmr_fid_set(payload, fid); 1596 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1597 mlxsw_reg_sfmr_vtfp_set(payload, false); 1598 mlxsw_reg_sfmr_vv_set(payload, false); 1599 } 1600 1601 /* SPVMLR - Switch Port VLAN MAC Learning Register 1602 * ----------------------------------------------- 1603 * Controls the switch MAC learning policy per {Port, VID}. 1604 */ 1605 #define MLXSW_REG_SPVMLR_ID 0x2020 1606 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1607 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1608 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256 1609 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1610 MLXSW_REG_SPVMLR_REC_LEN * \ 1611 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1612 1613 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = { 1614 .id = MLXSW_REG_SPVMLR_ID, 1615 .len = MLXSW_REG_SPVMLR_LEN, 1616 }; 1617 1618 /* reg_spvmlr_local_port 1619 * Local ingress port. 1620 * Access: Index 1621 * 1622 * Note: CPU port is not supported. 1623 */ 1624 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1625 1626 /* reg_spvmlr_num_rec 1627 * Number of records to update. 1628 * Access: OP 1629 */ 1630 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1631 1632 /* reg_spvmlr_rec_learn_enable 1633 * 0 - Disable learning for {Port, VID}. 1634 * 1 - Enable learning for {Port, VID}. 1635 * Access: RW 1636 */ 1637 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1638 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1639 1640 /* reg_spvmlr_rec_vid 1641 * VLAN ID to be added/removed from port or for querying. 1642 * Access: Index 1643 */ 1644 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1645 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1646 1647 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1648 u16 vid_begin, u16 vid_end, 1649 bool learn_enable) 1650 { 1651 int num_rec = vid_end - vid_begin + 1; 1652 int i; 1653 1654 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1655 1656 MLXSW_REG_ZERO(spvmlr, payload); 1657 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1658 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1659 1660 for (i = 0; i < num_rec; i++) { 1661 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1662 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1663 } 1664 } 1665 1666 /* PMLP - Ports Module to Local Port Register 1667 * ------------------------------------------ 1668 * Configures the assignment of modules to local ports. 1669 */ 1670 #define MLXSW_REG_PMLP_ID 0x5002 1671 #define MLXSW_REG_PMLP_LEN 0x40 1672 1673 static const struct mlxsw_reg_info mlxsw_reg_pmlp = { 1674 .id = MLXSW_REG_PMLP_ID, 1675 .len = MLXSW_REG_PMLP_LEN, 1676 }; 1677 1678 /* reg_pmlp_rxtx 1679 * 0 - Tx value is used for both Tx and Rx. 1680 * 1 - Rx value is taken from a separte field. 1681 * Access: RW 1682 */ 1683 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 1684 1685 /* reg_pmlp_local_port 1686 * Local port number. 1687 * Access: Index 1688 */ 1689 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 1690 1691 /* reg_pmlp_width 1692 * 0 - Unmap local port. 1693 * 1 - Lane 0 is used. 1694 * 2 - Lanes 0 and 1 are used. 1695 * 4 - Lanes 0, 1, 2 and 3 are used. 1696 * Access: RW 1697 */ 1698 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 1699 1700 /* reg_pmlp_module 1701 * Module number. 1702 * Access: RW 1703 */ 1704 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false); 1705 1706 /* reg_pmlp_tx_lane 1707 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 1708 * Access: RW 1709 */ 1710 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false); 1711 1712 /* reg_pmlp_rx_lane 1713 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 1714 * equal to Tx lane. 1715 * Access: RW 1716 */ 1717 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false); 1718 1719 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 1720 { 1721 MLXSW_REG_ZERO(pmlp, payload); 1722 mlxsw_reg_pmlp_local_port_set(payload, local_port); 1723 } 1724 1725 /* PMTU - Port MTU Register 1726 * ------------------------ 1727 * Configures and reports the port MTU. 1728 */ 1729 #define MLXSW_REG_PMTU_ID 0x5003 1730 #define MLXSW_REG_PMTU_LEN 0x10 1731 1732 static const struct mlxsw_reg_info mlxsw_reg_pmtu = { 1733 .id = MLXSW_REG_PMTU_ID, 1734 .len = MLXSW_REG_PMTU_LEN, 1735 }; 1736 1737 /* reg_pmtu_local_port 1738 * Local port number. 1739 * Access: Index 1740 */ 1741 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 1742 1743 /* reg_pmtu_max_mtu 1744 * Maximum MTU. 1745 * When port type (e.g. Ethernet) is configured, the relevant MTU is 1746 * reported, otherwise the minimum between the max_mtu of the different 1747 * types is reported. 1748 * Access: RO 1749 */ 1750 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 1751 1752 /* reg_pmtu_admin_mtu 1753 * MTU value to set port to. Must be smaller or equal to max_mtu. 1754 * Note: If port type is Infiniband, then port must be disabled, when its 1755 * MTU is set. 1756 * Access: RW 1757 */ 1758 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 1759 1760 /* reg_pmtu_oper_mtu 1761 * The actual MTU configured on the port. Packets exceeding this size 1762 * will be dropped. 1763 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 1764 * oper_mtu might be smaller than admin_mtu. 1765 * Access: RO 1766 */ 1767 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 1768 1769 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 1770 u16 new_mtu) 1771 { 1772 MLXSW_REG_ZERO(pmtu, payload); 1773 mlxsw_reg_pmtu_local_port_set(payload, local_port); 1774 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 1775 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 1776 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 1777 } 1778 1779 /* PTYS - Port Type and Speed Register 1780 * ----------------------------------- 1781 * Configures and reports the port speed type. 1782 * 1783 * Note: When set while the link is up, the changes will not take effect 1784 * until the port transitions from down to up state. 1785 */ 1786 #define MLXSW_REG_PTYS_ID 0x5004 1787 #define MLXSW_REG_PTYS_LEN 0x40 1788 1789 static const struct mlxsw_reg_info mlxsw_reg_ptys = { 1790 .id = MLXSW_REG_PTYS_ID, 1791 .len = MLXSW_REG_PTYS_LEN, 1792 }; 1793 1794 /* reg_ptys_local_port 1795 * Local port number. 1796 * Access: Index 1797 */ 1798 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 1799 1800 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 1801 1802 /* reg_ptys_proto_mask 1803 * Protocol mask. Indicates which protocol is used. 1804 * 0 - Infiniband. 1805 * 1 - Fibre Channel. 1806 * 2 - Ethernet. 1807 * Access: Index 1808 */ 1809 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 1810 1811 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 1812 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 1813 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 1814 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 1815 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 1816 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 1817 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 1818 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 1819 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 1820 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 1821 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 1822 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 1823 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 1824 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 1825 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 1826 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 1827 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 1828 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 1829 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 1830 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 1831 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 1832 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 1833 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 1834 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 1835 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 1836 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 1837 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 1838 1839 /* reg_ptys_eth_proto_cap 1840 * Ethernet port supported speeds and protocols. 1841 * Access: RO 1842 */ 1843 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 1844 1845 /* reg_ptys_eth_proto_admin 1846 * Speed and protocol to set port to. 1847 * Access: RW 1848 */ 1849 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 1850 1851 /* reg_ptys_eth_proto_oper 1852 * The current speed and protocol configured for the port. 1853 * Access: RO 1854 */ 1855 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 1856 1857 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port, 1858 u32 proto_admin) 1859 { 1860 MLXSW_REG_ZERO(ptys, payload); 1861 mlxsw_reg_ptys_local_port_set(payload, local_port); 1862 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 1863 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 1864 } 1865 1866 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap, 1867 u32 *p_eth_proto_adm, 1868 u32 *p_eth_proto_oper) 1869 { 1870 if (p_eth_proto_cap) 1871 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 1872 if (p_eth_proto_adm) 1873 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 1874 if (p_eth_proto_oper) 1875 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 1876 } 1877 1878 /* PPAD - Port Physical Address Register 1879 * ------------------------------------- 1880 * The PPAD register configures the per port physical MAC address. 1881 */ 1882 #define MLXSW_REG_PPAD_ID 0x5005 1883 #define MLXSW_REG_PPAD_LEN 0x10 1884 1885 static const struct mlxsw_reg_info mlxsw_reg_ppad = { 1886 .id = MLXSW_REG_PPAD_ID, 1887 .len = MLXSW_REG_PPAD_LEN, 1888 }; 1889 1890 /* reg_ppad_single_base_mac 1891 * 0: base_mac, local port should be 0 and mac[7:0] is 1892 * reserved. HW will set incremental 1893 * 1: single_mac - mac of the local_port 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 1897 1898 /* reg_ppad_local_port 1899 * port number, if single_base_mac = 0 then local_port is reserved 1900 * Access: RW 1901 */ 1902 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 1903 1904 /* reg_ppad_mac 1905 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 1906 * If single_base_mac = 1 - the per port MAC address 1907 * Access: RW 1908 */ 1909 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 1910 1911 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 1912 u8 local_port) 1913 { 1914 MLXSW_REG_ZERO(ppad, payload); 1915 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 1916 mlxsw_reg_ppad_local_port_set(payload, local_port); 1917 } 1918 1919 /* PAOS - Ports Administrative and Operational Status Register 1920 * ----------------------------------------------------------- 1921 * Configures and retrieves per port administrative and operational status. 1922 */ 1923 #define MLXSW_REG_PAOS_ID 0x5006 1924 #define MLXSW_REG_PAOS_LEN 0x10 1925 1926 static const struct mlxsw_reg_info mlxsw_reg_paos = { 1927 .id = MLXSW_REG_PAOS_ID, 1928 .len = MLXSW_REG_PAOS_LEN, 1929 }; 1930 1931 /* reg_paos_swid 1932 * Switch partition ID with which to associate the port. 1933 * Note: while external ports uses unique local port numbers (and thus swid is 1934 * redundant), router ports use the same local port number where swid is the 1935 * only indication for the relevant port. 1936 * Access: Index 1937 */ 1938 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 1939 1940 /* reg_paos_local_port 1941 * Local port number. 1942 * Access: Index 1943 */ 1944 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 1945 1946 /* reg_paos_admin_status 1947 * Port administrative state (the desired state of the port): 1948 * 1 - Up. 1949 * 2 - Down. 1950 * 3 - Up once. This means that in case of link failure, the port won't go 1951 * into polling mode, but will wait to be re-enabled by software. 1952 * 4 - Disabled by system. Can only be set by hardware. 1953 * Access: RW 1954 */ 1955 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 1956 1957 /* reg_paos_oper_status 1958 * Port operational state (the current state): 1959 * 1 - Up. 1960 * 2 - Down. 1961 * 3 - Down by port failure. This means that the device will not let the 1962 * port up again until explicitly specified by software. 1963 * Access: RO 1964 */ 1965 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 1966 1967 /* reg_paos_ase 1968 * Admin state update enabled. 1969 * Access: WO 1970 */ 1971 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 1972 1973 /* reg_paos_ee 1974 * Event update enable. If this bit is set, event generation will be 1975 * updated based on the e field. 1976 * Access: WO 1977 */ 1978 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 1979 1980 /* reg_paos_e 1981 * Event generation on operational state change: 1982 * 0 - Do not generate event. 1983 * 1 - Generate Event. 1984 * 2 - Generate Single Event. 1985 * Access: RW 1986 */ 1987 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 1988 1989 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 1990 enum mlxsw_port_admin_status status) 1991 { 1992 MLXSW_REG_ZERO(paos, payload); 1993 mlxsw_reg_paos_swid_set(payload, 0); 1994 mlxsw_reg_paos_local_port_set(payload, local_port); 1995 mlxsw_reg_paos_admin_status_set(payload, status); 1996 mlxsw_reg_paos_oper_status_set(payload, 0); 1997 mlxsw_reg_paos_ase_set(payload, 1); 1998 mlxsw_reg_paos_ee_set(payload, 1); 1999 mlxsw_reg_paos_e_set(payload, 1); 2000 } 2001 2002 /* PPCNT - Ports Performance Counters Register 2003 * ------------------------------------------- 2004 * The PPCNT register retrieves per port performance counters. 2005 */ 2006 #define MLXSW_REG_PPCNT_ID 0x5008 2007 #define MLXSW_REG_PPCNT_LEN 0x100 2008 2009 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = { 2010 .id = MLXSW_REG_PPCNT_ID, 2011 .len = MLXSW_REG_PPCNT_LEN, 2012 }; 2013 2014 /* reg_ppcnt_swid 2015 * For HCA: must be always 0. 2016 * Switch partition ID to associate port with. 2017 * Switch partitions are numbered from 0 to 7 inclusively. 2018 * Switch partition 254 indicates stacking ports. 2019 * Switch partition 255 indicates all switch partitions. 2020 * Only valid on Set() operation with local_port=255. 2021 * Access: Index 2022 */ 2023 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 2024 2025 /* reg_ppcnt_local_port 2026 * Local port number. 2027 * 255 indicates all ports on the device, and is only allowed 2028 * for Set() operation. 2029 * Access: Index 2030 */ 2031 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 2032 2033 /* reg_ppcnt_pnat 2034 * Port number access type: 2035 * 0 - Local port number 2036 * 1 - IB port number 2037 * Access: Index 2038 */ 2039 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 2040 2041 /* reg_ppcnt_grp 2042 * Performance counter group. 2043 * Group 63 indicates all groups. Only valid on Set() operation with 2044 * clr bit set. 2045 * 0x0: IEEE 802.3 Counters 2046 * 0x1: RFC 2863 Counters 2047 * 0x2: RFC 2819 Counters 2048 * 0x3: RFC 3635 Counters 2049 * 0x5: Ethernet Extended Counters 2050 * 0x8: Link Level Retransmission Counters 2051 * 0x10: Per Priority Counters 2052 * 0x11: Per Traffic Class Counters 2053 * 0x12: Physical Layer Counters 2054 * Access: Index 2055 */ 2056 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 2057 2058 /* reg_ppcnt_clr 2059 * Clear counters. Setting the clr bit will reset the counter value 2060 * for all counters in the counter group. This bit can be set 2061 * for both Set() and Get() operation. 2062 * Access: OP 2063 */ 2064 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 2065 2066 /* reg_ppcnt_prio_tc 2067 * Priority for counter set that support per priority, valid values: 0-7. 2068 * Traffic class for counter set that support per traffic class, 2069 * valid values: 0- cap_max_tclass-1 . 2070 * For HCA: cap_max_tclass is always 8. 2071 * Otherwise must be 0. 2072 * Access: Index 2073 */ 2074 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 2075 2076 /* reg_ppcnt_a_frames_transmitted_ok 2077 * Access: RO 2078 */ 2079 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 2080 0x08 + 0x00, 0, 64); 2081 2082 /* reg_ppcnt_a_frames_received_ok 2083 * Access: RO 2084 */ 2085 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 2086 0x08 + 0x08, 0, 64); 2087 2088 /* reg_ppcnt_a_frame_check_sequence_errors 2089 * Access: RO 2090 */ 2091 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 2092 0x08 + 0x10, 0, 64); 2093 2094 /* reg_ppcnt_a_alignment_errors 2095 * Access: RO 2096 */ 2097 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 2098 0x08 + 0x18, 0, 64); 2099 2100 /* reg_ppcnt_a_octets_transmitted_ok 2101 * Access: RO 2102 */ 2103 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 2104 0x08 + 0x20, 0, 64); 2105 2106 /* reg_ppcnt_a_octets_received_ok 2107 * Access: RO 2108 */ 2109 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 2110 0x08 + 0x28, 0, 64); 2111 2112 /* reg_ppcnt_a_multicast_frames_xmitted_ok 2113 * Access: RO 2114 */ 2115 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 2116 0x08 + 0x30, 0, 64); 2117 2118 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 2119 * Access: RO 2120 */ 2121 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 2122 0x08 + 0x38, 0, 64); 2123 2124 /* reg_ppcnt_a_multicast_frames_received_ok 2125 * Access: RO 2126 */ 2127 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 2128 0x08 + 0x40, 0, 64); 2129 2130 /* reg_ppcnt_a_broadcast_frames_received_ok 2131 * Access: RO 2132 */ 2133 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 2134 0x08 + 0x48, 0, 64); 2135 2136 /* reg_ppcnt_a_in_range_length_errors 2137 * Access: RO 2138 */ 2139 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 2140 0x08 + 0x50, 0, 64); 2141 2142 /* reg_ppcnt_a_out_of_range_length_field 2143 * Access: RO 2144 */ 2145 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 2146 0x08 + 0x58, 0, 64); 2147 2148 /* reg_ppcnt_a_frame_too_long_errors 2149 * Access: RO 2150 */ 2151 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 2152 0x08 + 0x60, 0, 64); 2153 2154 /* reg_ppcnt_a_symbol_error_during_carrier 2155 * Access: RO 2156 */ 2157 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 2158 0x08 + 0x68, 0, 64); 2159 2160 /* reg_ppcnt_a_mac_control_frames_transmitted 2161 * Access: RO 2162 */ 2163 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 2164 0x08 + 0x70, 0, 64); 2165 2166 /* reg_ppcnt_a_mac_control_frames_received 2167 * Access: RO 2168 */ 2169 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 2170 0x08 + 0x78, 0, 64); 2171 2172 /* reg_ppcnt_a_unsupported_opcodes_received 2173 * Access: RO 2174 */ 2175 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 2176 0x08 + 0x80, 0, 64); 2177 2178 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 2179 * Access: RO 2180 */ 2181 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 2182 0x08 + 0x88, 0, 64); 2183 2184 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 2185 * Access: RO 2186 */ 2187 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 2188 0x08 + 0x90, 0, 64); 2189 2190 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port) 2191 { 2192 MLXSW_REG_ZERO(ppcnt, payload); 2193 mlxsw_reg_ppcnt_swid_set(payload, 0); 2194 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 2195 mlxsw_reg_ppcnt_pnat_set(payload, 0); 2196 mlxsw_reg_ppcnt_grp_set(payload, 0); 2197 mlxsw_reg_ppcnt_clr_set(payload, 0); 2198 mlxsw_reg_ppcnt_prio_tc_set(payload, 0); 2199 } 2200 2201 /* PBMC - Port Buffer Management Control Register 2202 * ---------------------------------------------- 2203 * The PBMC register configures and retrieves the port packet buffer 2204 * allocation for different Prios, and the Pause threshold management. 2205 */ 2206 #define MLXSW_REG_PBMC_ID 0x500C 2207 #define MLXSW_REG_PBMC_LEN 0x68 2208 2209 static const struct mlxsw_reg_info mlxsw_reg_pbmc = { 2210 .id = MLXSW_REG_PBMC_ID, 2211 .len = MLXSW_REG_PBMC_LEN, 2212 }; 2213 2214 /* reg_pbmc_local_port 2215 * Local port number. 2216 * Access: Index 2217 */ 2218 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 2219 2220 /* reg_pbmc_xoff_timer_value 2221 * When device generates a pause frame, it uses this value as the pause 2222 * timer (time for the peer port to pause in quota-512 bit time). 2223 * Access: RW 2224 */ 2225 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 2226 2227 /* reg_pbmc_xoff_refresh 2228 * The time before a new pause frame should be sent to refresh the pause RW 2229 * state. Using the same units as xoff_timer_value above (in quota-512 bit 2230 * time). 2231 * Access: RW 2232 */ 2233 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 2234 2235 /* reg_pbmc_buf_lossy 2236 * The field indicates if the buffer is lossy. 2237 * 0 - Lossless 2238 * 1 - Lossy 2239 * Access: RW 2240 */ 2241 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 2242 2243 /* reg_pbmc_buf_epsb 2244 * Eligible for Port Shared buffer. 2245 * If epsb is set, packets assigned to buffer are allowed to insert the port 2246 * shared buffer. 2247 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 2248 * Access: RW 2249 */ 2250 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 2251 2252 /* reg_pbmc_buf_size 2253 * The part of the packet buffer array is allocated for the specific buffer. 2254 * Units are represented in cells. 2255 * Access: RW 2256 */ 2257 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 2258 2259 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 2260 u16 xoff_timer_value, u16 xoff_refresh) 2261 { 2262 MLXSW_REG_ZERO(pbmc, payload); 2263 mlxsw_reg_pbmc_local_port_set(payload, local_port); 2264 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 2265 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 2266 } 2267 2268 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 2269 int buf_index, 2270 u16 size) 2271 { 2272 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 2273 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 2274 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 2275 } 2276 2277 /* PSPA - Port Switch Partition Allocation 2278 * --------------------------------------- 2279 * Controls the association of a port with a switch partition and enables 2280 * configuring ports as stacking ports. 2281 */ 2282 #define MLXSW_REG_PSPA_ID 0x500D 2283 #define MLXSW_REG_PSPA_LEN 0x8 2284 2285 static const struct mlxsw_reg_info mlxsw_reg_pspa = { 2286 .id = MLXSW_REG_PSPA_ID, 2287 .len = MLXSW_REG_PSPA_LEN, 2288 }; 2289 2290 /* reg_pspa_swid 2291 * Switch partition ID. 2292 * Access: RW 2293 */ 2294 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 2295 2296 /* reg_pspa_local_port 2297 * Local port number. 2298 * Access: Index 2299 */ 2300 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 2301 2302 /* reg_pspa_sub_port 2303 * Virtual port within the local port. Set to 0 when virtual ports are 2304 * disabled on the local port. 2305 * Access: Index 2306 */ 2307 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 2308 2309 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 2310 { 2311 MLXSW_REG_ZERO(pspa, payload); 2312 mlxsw_reg_pspa_swid_set(payload, swid); 2313 mlxsw_reg_pspa_local_port_set(payload, local_port); 2314 mlxsw_reg_pspa_sub_port_set(payload, 0); 2315 } 2316 2317 /* HTGT - Host Trap Group Table 2318 * ---------------------------- 2319 * Configures the properties for forwarding to CPU. 2320 */ 2321 #define MLXSW_REG_HTGT_ID 0x7002 2322 #define MLXSW_REG_HTGT_LEN 0x100 2323 2324 static const struct mlxsw_reg_info mlxsw_reg_htgt = { 2325 .id = MLXSW_REG_HTGT_ID, 2326 .len = MLXSW_REG_HTGT_LEN, 2327 }; 2328 2329 /* reg_htgt_swid 2330 * Switch partition ID. 2331 * Access: Index 2332 */ 2333 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 2334 2335 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 2336 2337 /* reg_htgt_type 2338 * CPU path type. 2339 * Access: RW 2340 */ 2341 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 2342 2343 enum mlxsw_reg_htgt_trap_group { 2344 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 2345 MLXSW_REG_HTGT_TRAP_GROUP_RX, 2346 MLXSW_REG_HTGT_TRAP_GROUP_CTRL, 2347 }; 2348 2349 /* reg_htgt_trap_group 2350 * Trap group number. User defined number specifying which trap groups 2351 * should be forwarded to the CPU. The mapping between trap IDs and trap 2352 * groups is configured using HPKT register. 2353 * Access: Index 2354 */ 2355 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 2356 2357 enum { 2358 MLXSW_REG_HTGT_POLICER_DISABLE, 2359 MLXSW_REG_HTGT_POLICER_ENABLE, 2360 }; 2361 2362 /* reg_htgt_pide 2363 * Enable policer ID specified using 'pid' field. 2364 * Access: RW 2365 */ 2366 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 2367 2368 /* reg_htgt_pid 2369 * Policer ID for the trap group. 2370 * Access: RW 2371 */ 2372 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 2373 2374 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 2375 2376 /* reg_htgt_mirror_action 2377 * Mirror action to use. 2378 * 0 - Trap to CPU. 2379 * 1 - Trap to CPU and mirror to a mirroring agent. 2380 * 2 - Mirror to a mirroring agent and do not trap to CPU. 2381 * Access: RW 2382 * 2383 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 2384 */ 2385 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 2386 2387 /* reg_htgt_mirroring_agent 2388 * Mirroring agent. 2389 * Access: RW 2390 */ 2391 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 2392 2393 /* reg_htgt_priority 2394 * Trap group priority. 2395 * In case a packet matches multiple classification rules, the packet will 2396 * only be trapped once, based on the trap ID associated with the group (via 2397 * register HPKT) with the highest priority. 2398 * Supported values are 0-7, with 7 represnting the highest priority. 2399 * Access: RW 2400 * 2401 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 2402 * by the 'trap_group' field. 2403 */ 2404 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 2405 2406 /* reg_htgt_local_path_cpu_tclass 2407 * CPU ingress traffic class for the trap group. 2408 * Access: RW 2409 */ 2410 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 2411 2412 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15 2413 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14 2414 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13 2415 2416 /* reg_htgt_local_path_rdq 2417 * Receive descriptor queue (RDQ) to use for the trap group. 2418 * Access: RW 2419 */ 2420 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 2421 2422 static inline void mlxsw_reg_htgt_pack(char *payload, 2423 enum mlxsw_reg_htgt_trap_group group) 2424 { 2425 u8 swid, rdq; 2426 2427 MLXSW_REG_ZERO(htgt, payload); 2428 switch (group) { 2429 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD: 2430 swid = MLXSW_PORT_SWID_ALL_SWIDS; 2431 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD; 2432 break; 2433 case MLXSW_REG_HTGT_TRAP_GROUP_RX: 2434 swid = 0; 2435 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX; 2436 break; 2437 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL: 2438 swid = 0; 2439 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL; 2440 break; 2441 } 2442 mlxsw_reg_htgt_swid_set(payload, swid); 2443 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 2444 mlxsw_reg_htgt_trap_group_set(payload, group); 2445 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE); 2446 mlxsw_reg_htgt_pid_set(payload, 0); 2447 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 2448 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 2449 mlxsw_reg_htgt_priority_set(payload, 0); 2450 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7); 2451 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq); 2452 } 2453 2454 /* HPKT - Host Packet Trap 2455 * ----------------------- 2456 * Configures trap IDs inside trap groups. 2457 */ 2458 #define MLXSW_REG_HPKT_ID 0x7003 2459 #define MLXSW_REG_HPKT_LEN 0x10 2460 2461 static const struct mlxsw_reg_info mlxsw_reg_hpkt = { 2462 .id = MLXSW_REG_HPKT_ID, 2463 .len = MLXSW_REG_HPKT_LEN, 2464 }; 2465 2466 enum { 2467 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 2468 MLXSW_REG_HPKT_ACK_REQUIRED, 2469 }; 2470 2471 /* reg_hpkt_ack 2472 * Require acknowledgements from the host for events. 2473 * If set, then the device will wait for the event it sent to be acknowledged 2474 * by the host. This option is only relevant for event trap IDs. 2475 * Access: RW 2476 * 2477 * Note: Currently not supported by firmware. 2478 */ 2479 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 2480 2481 enum mlxsw_reg_hpkt_action { 2482 MLXSW_REG_HPKT_ACTION_FORWARD, 2483 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 2484 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 2485 MLXSW_REG_HPKT_ACTION_DISCARD, 2486 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 2487 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 2488 }; 2489 2490 /* reg_hpkt_action 2491 * Action to perform on packet when trapped. 2492 * 0 - No action. Forward to CPU based on switching rules. 2493 * 1 - Trap to CPU (CPU receives sole copy). 2494 * 2 - Mirror to CPU (CPU receives a replica of the packet). 2495 * 3 - Discard. 2496 * 4 - Soft discard (allow other traps to act on the packet). 2497 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 2498 * Access: RW 2499 * 2500 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 2501 * addressed to the CPU. 2502 */ 2503 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 2504 2505 /* reg_hpkt_trap_group 2506 * Trap group to associate the trap with. 2507 * Access: RW 2508 */ 2509 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 2510 2511 /* reg_hpkt_trap_id 2512 * Trap ID. 2513 * Access: Index 2514 * 2515 * Note: A trap ID can only be associated with a single trap group. The device 2516 * will associate the trap ID with the last trap group configured. 2517 */ 2518 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 2519 2520 enum { 2521 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 2522 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 2523 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 2524 }; 2525 2526 /* reg_hpkt_ctrl 2527 * Configure dedicated buffer resources for control packets. 2528 * 0 - Keep factory defaults. 2529 * 1 - Do not use control buffer for this trap ID. 2530 * 2 - Use control buffer for this trap ID. 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 2534 2535 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id) 2536 { 2537 enum mlxsw_reg_htgt_trap_group trap_group; 2538 2539 MLXSW_REG_ZERO(hpkt, payload); 2540 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 2541 mlxsw_reg_hpkt_action_set(payload, action); 2542 switch (trap_id) { 2543 case MLXSW_TRAP_ID_ETHEMAD: 2544 case MLXSW_TRAP_ID_PUDE: 2545 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD; 2546 break; 2547 default: 2548 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX; 2549 break; 2550 } 2551 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 2552 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 2553 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT); 2554 } 2555 2556 /* MFCR - Management Fan Control Register 2557 * -------------------------------------- 2558 * This register controls the settings of the Fan Speed PWM mechanism. 2559 */ 2560 #define MLXSW_REG_MFCR_ID 0x9001 2561 #define MLXSW_REG_MFCR_LEN 0x08 2562 2563 static const struct mlxsw_reg_info mlxsw_reg_mfcr = { 2564 .id = MLXSW_REG_MFCR_ID, 2565 .len = MLXSW_REG_MFCR_LEN, 2566 }; 2567 2568 enum mlxsw_reg_mfcr_pwm_frequency { 2569 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 2570 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 2571 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 2572 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 2573 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 2574 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 2575 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 2576 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 2577 }; 2578 2579 /* reg_mfcr_pwm_frequency 2580 * Controls the frequency of the PWM signal. 2581 * Access: RW 2582 */ 2583 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6); 2584 2585 #define MLXSW_MFCR_TACHOS_MAX 10 2586 2587 /* reg_mfcr_tacho_active 2588 * Indicates which of the tachometer is active (bit per tachometer). 2589 * Access: RO 2590 */ 2591 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 2592 2593 #define MLXSW_MFCR_PWMS_MAX 5 2594 2595 /* reg_mfcr_pwm_active 2596 * Indicates which of the PWM control is active (bit per PWM). 2597 * Access: RO 2598 */ 2599 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 2600 2601 static inline void 2602 mlxsw_reg_mfcr_pack(char *payload, 2603 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 2604 { 2605 MLXSW_REG_ZERO(mfcr, payload); 2606 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 2607 } 2608 2609 static inline void 2610 mlxsw_reg_mfcr_unpack(char *payload, 2611 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 2612 u16 *p_tacho_active, u8 *p_pwm_active) 2613 { 2614 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 2615 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 2616 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 2617 } 2618 2619 /* MFSC - Management Fan Speed Control Register 2620 * -------------------------------------------- 2621 * This register controls the settings of the Fan Speed PWM mechanism. 2622 */ 2623 #define MLXSW_REG_MFSC_ID 0x9002 2624 #define MLXSW_REG_MFSC_LEN 0x08 2625 2626 static const struct mlxsw_reg_info mlxsw_reg_mfsc = { 2627 .id = MLXSW_REG_MFSC_ID, 2628 .len = MLXSW_REG_MFSC_LEN, 2629 }; 2630 2631 /* reg_mfsc_pwm 2632 * Fan pwm to control / monitor. 2633 * Access: Index 2634 */ 2635 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 2636 2637 /* reg_mfsc_pwm_duty_cycle 2638 * Controls the duty cycle of the PWM. Value range from 0..255 to 2639 * represent duty cycle of 0%...100%. 2640 * Access: RW 2641 */ 2642 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 2643 2644 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 2645 u8 pwm_duty_cycle) 2646 { 2647 MLXSW_REG_ZERO(mfsc, payload); 2648 mlxsw_reg_mfsc_pwm_set(payload, pwm); 2649 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 2650 } 2651 2652 /* MFSM - Management Fan Speed Measurement 2653 * --------------------------------------- 2654 * This register controls the settings of the Tacho measurements and 2655 * enables reading the Tachometer measurements. 2656 */ 2657 #define MLXSW_REG_MFSM_ID 0x9003 2658 #define MLXSW_REG_MFSM_LEN 0x08 2659 2660 static const struct mlxsw_reg_info mlxsw_reg_mfsm = { 2661 .id = MLXSW_REG_MFSM_ID, 2662 .len = MLXSW_REG_MFSM_LEN, 2663 }; 2664 2665 /* reg_mfsm_tacho 2666 * Fan tachometer index. 2667 * Access: Index 2668 */ 2669 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 2670 2671 /* reg_mfsm_rpm 2672 * Fan speed (round per minute). 2673 * Access: RO 2674 */ 2675 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 2676 2677 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 2678 { 2679 MLXSW_REG_ZERO(mfsm, payload); 2680 mlxsw_reg_mfsm_tacho_set(payload, tacho); 2681 } 2682 2683 /* MTCAP - Management Temperature Capabilities 2684 * ------------------------------------------- 2685 * This register exposes the capabilities of the device and 2686 * system temperature sensing. 2687 */ 2688 #define MLXSW_REG_MTCAP_ID 0x9009 2689 #define MLXSW_REG_MTCAP_LEN 0x08 2690 2691 static const struct mlxsw_reg_info mlxsw_reg_mtcap = { 2692 .id = MLXSW_REG_MTCAP_ID, 2693 .len = MLXSW_REG_MTCAP_LEN, 2694 }; 2695 2696 /* reg_mtcap_sensor_count 2697 * Number of sensors supported by the device. 2698 * This includes the QSFP module sensors (if exists in the QSFP module). 2699 * Access: RO 2700 */ 2701 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 2702 2703 /* MTMP - Management Temperature 2704 * ----------------------------- 2705 * This register controls the settings of the temperature measurements 2706 * and enables reading the temperature measurements. Note that temperature 2707 * is in 0.125 degrees Celsius. 2708 */ 2709 #define MLXSW_REG_MTMP_ID 0x900A 2710 #define MLXSW_REG_MTMP_LEN 0x20 2711 2712 static const struct mlxsw_reg_info mlxsw_reg_mtmp = { 2713 .id = MLXSW_REG_MTMP_ID, 2714 .len = MLXSW_REG_MTMP_LEN, 2715 }; 2716 2717 /* reg_mtmp_sensor_index 2718 * Sensors index to access. 2719 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 2720 * (module 0 is mapped to sensor_index 64). 2721 * Access: Index 2722 */ 2723 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 2724 2725 /* Convert to milli degrees Celsius */ 2726 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 2727 2728 /* reg_mtmp_temperature 2729 * Temperature reading from the sensor. Reading is in 0.125 Celsius 2730 * degrees units. 2731 * Access: RO 2732 */ 2733 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 2734 2735 /* reg_mtmp_mte 2736 * Max Temperature Enable - enables measuring the max temperature on a sensor. 2737 * Access: RW 2738 */ 2739 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 2740 2741 /* reg_mtmp_mtr 2742 * Max Temperature Reset - clears the value of the max temperature register. 2743 * Access: WO 2744 */ 2745 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 2746 2747 /* reg_mtmp_max_temperature 2748 * The highest measured temperature from the sensor. 2749 * When the bit mte is cleared, the field max_temperature is reserved. 2750 * Access: RO 2751 */ 2752 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 2753 2754 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 2755 2756 /* reg_mtmp_sensor_name 2757 * Sensor Name 2758 * Access: RO 2759 */ 2760 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 2761 2762 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 2763 bool max_temp_enable, 2764 bool max_temp_reset) 2765 { 2766 MLXSW_REG_ZERO(mtmp, payload); 2767 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 2768 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 2769 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 2770 } 2771 2772 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 2773 unsigned int *p_max_temp, 2774 char *sensor_name) 2775 { 2776 u16 temp; 2777 2778 if (p_temp) { 2779 temp = mlxsw_reg_mtmp_temperature_get(payload); 2780 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 2781 } 2782 if (p_max_temp) { 2783 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 2784 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 2785 } 2786 if (sensor_name) 2787 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 2788 } 2789 2790 /* MLCR - Management LED Control Register 2791 * -------------------------------------- 2792 * Controls the system LEDs. 2793 */ 2794 #define MLXSW_REG_MLCR_ID 0x902B 2795 #define MLXSW_REG_MLCR_LEN 0x0C 2796 2797 static const struct mlxsw_reg_info mlxsw_reg_mlcr = { 2798 .id = MLXSW_REG_MLCR_ID, 2799 .len = MLXSW_REG_MLCR_LEN, 2800 }; 2801 2802 /* reg_mlcr_local_port 2803 * Local port number. 2804 * Access: RW 2805 */ 2806 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 2807 2808 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 2809 2810 /* reg_mlcr_beacon_duration 2811 * Duration of the beacon to be active, in seconds. 2812 * 0x0 - Will turn off the beacon. 2813 * 0xFFFF - Will turn on the beacon until explicitly turned off. 2814 * Access: RW 2815 */ 2816 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 2817 2818 /* reg_mlcr_beacon_remain 2819 * Remaining duration of the beacon, in seconds. 2820 * 0xFFFF indicates an infinite amount of time. 2821 * Access: RO 2822 */ 2823 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 2824 2825 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 2826 bool active) 2827 { 2828 MLXSW_REG_ZERO(mlcr, payload); 2829 mlxsw_reg_mlcr_local_port_set(payload, local_port); 2830 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 2831 MLXSW_REG_MLCR_DURATION_MAX : 0); 2832 } 2833 2834 /* SBPR - Shared Buffer Pools Register 2835 * ----------------------------------- 2836 * The SBPR configures and retrieves the shared buffer pools and configuration. 2837 */ 2838 #define MLXSW_REG_SBPR_ID 0xB001 2839 #define MLXSW_REG_SBPR_LEN 0x14 2840 2841 static const struct mlxsw_reg_info mlxsw_reg_sbpr = { 2842 .id = MLXSW_REG_SBPR_ID, 2843 .len = MLXSW_REG_SBPR_LEN, 2844 }; 2845 2846 enum mlxsw_reg_sbpr_dir { 2847 MLXSW_REG_SBPR_DIR_INGRESS, 2848 MLXSW_REG_SBPR_DIR_EGRESS, 2849 }; 2850 2851 /* reg_sbpr_dir 2852 * Direction. 2853 * Access: Index 2854 */ 2855 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 2856 2857 /* reg_sbpr_pool 2858 * Pool index. 2859 * Access: Index 2860 */ 2861 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 2862 2863 /* reg_sbpr_size 2864 * Pool size in buffer cells. 2865 * Access: RW 2866 */ 2867 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 2868 2869 enum mlxsw_reg_sbpr_mode { 2870 MLXSW_REG_SBPR_MODE_STATIC, 2871 MLXSW_REG_SBPR_MODE_DYNAMIC, 2872 }; 2873 2874 /* reg_sbpr_mode 2875 * Pool quota calculation mode. 2876 * Access: RW 2877 */ 2878 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 2879 2880 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 2881 enum mlxsw_reg_sbpr_dir dir, 2882 enum mlxsw_reg_sbpr_mode mode, u32 size) 2883 { 2884 MLXSW_REG_ZERO(sbpr, payload); 2885 mlxsw_reg_sbpr_pool_set(payload, pool); 2886 mlxsw_reg_sbpr_dir_set(payload, dir); 2887 mlxsw_reg_sbpr_mode_set(payload, mode); 2888 mlxsw_reg_sbpr_size_set(payload, size); 2889 } 2890 2891 /* SBCM - Shared Buffer Class Management Register 2892 * ---------------------------------------------- 2893 * The SBCM register configures and retrieves the shared buffer allocation 2894 * and configuration according to Port-PG, including the binding to pool 2895 * and definition of the associated quota. 2896 */ 2897 #define MLXSW_REG_SBCM_ID 0xB002 2898 #define MLXSW_REG_SBCM_LEN 0x28 2899 2900 static const struct mlxsw_reg_info mlxsw_reg_sbcm = { 2901 .id = MLXSW_REG_SBCM_ID, 2902 .len = MLXSW_REG_SBCM_LEN, 2903 }; 2904 2905 /* reg_sbcm_local_port 2906 * Local port number. 2907 * For Ingress: excludes CPU port and Router port 2908 * For Egress: excludes IP Router 2909 * Access: Index 2910 */ 2911 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 2912 2913 /* reg_sbcm_pg_buff 2914 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 2915 * For PG buffer: range is 0..cap_max_pg_buffers - 1 2916 * For traffic class: range is 0..cap_max_tclass - 1 2917 * Note that when traffic class is in MC aware mode then the traffic 2918 * classes which are MC aware cannot be configured. 2919 * Access: Index 2920 */ 2921 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 2922 2923 enum mlxsw_reg_sbcm_dir { 2924 MLXSW_REG_SBCM_DIR_INGRESS, 2925 MLXSW_REG_SBCM_DIR_EGRESS, 2926 }; 2927 2928 /* reg_sbcm_dir 2929 * Direction. 2930 * Access: Index 2931 */ 2932 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 2933 2934 /* reg_sbcm_min_buff 2935 * Minimum buffer size for the limiter, in cells. 2936 * Access: RW 2937 */ 2938 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 2939 2940 /* reg_sbcm_max_buff 2941 * When the pool associated to the port-pg/tclass is configured to 2942 * static, Maximum buffer size for the limiter configured in cells. 2943 * When the pool associated to the port-pg/tclass is configured to 2944 * dynamic, the max_buff holds the "alpha" parameter, supporting 2945 * the following values: 2946 * 0: 0 2947 * i: (1/128)*2^(i-1), for i=1..14 2948 * 0xFF: Infinity 2949 * Access: RW 2950 */ 2951 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 2952 2953 /* reg_sbcm_pool 2954 * Association of the port-priority to a pool. 2955 * Access: RW 2956 */ 2957 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 2958 2959 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 2960 enum mlxsw_reg_sbcm_dir dir, 2961 u32 min_buff, u32 max_buff, u8 pool) 2962 { 2963 MLXSW_REG_ZERO(sbcm, payload); 2964 mlxsw_reg_sbcm_local_port_set(payload, local_port); 2965 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 2966 mlxsw_reg_sbcm_dir_set(payload, dir); 2967 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 2968 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 2969 mlxsw_reg_sbcm_pool_set(payload, pool); 2970 } 2971 2972 /* SBPM - Shared Buffer Class Management Register 2973 * ---------------------------------------------- 2974 * The SBPM register configures and retrieves the shared buffer allocation 2975 * and configuration according to Port-Pool, including the definition 2976 * of the associated quota. 2977 */ 2978 #define MLXSW_REG_SBPM_ID 0xB003 2979 #define MLXSW_REG_SBPM_LEN 0x28 2980 2981 static const struct mlxsw_reg_info mlxsw_reg_sbpm = { 2982 .id = MLXSW_REG_SBPM_ID, 2983 .len = MLXSW_REG_SBPM_LEN, 2984 }; 2985 2986 /* reg_sbpm_local_port 2987 * Local port number. 2988 * For Ingress: excludes CPU port and Router port 2989 * For Egress: excludes IP Router 2990 * Access: Index 2991 */ 2992 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 2993 2994 /* reg_sbpm_pool 2995 * The pool associated to quota counting on the local_port. 2996 * Access: Index 2997 */ 2998 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 2999 3000 enum mlxsw_reg_sbpm_dir { 3001 MLXSW_REG_SBPM_DIR_INGRESS, 3002 MLXSW_REG_SBPM_DIR_EGRESS, 3003 }; 3004 3005 /* reg_sbpm_dir 3006 * Direction. 3007 * Access: Index 3008 */ 3009 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 3010 3011 /* reg_sbpm_min_buff 3012 * Minimum buffer size for the limiter, in cells. 3013 * Access: RW 3014 */ 3015 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 3016 3017 /* reg_sbpm_max_buff 3018 * When the pool associated to the port-pg/tclass is configured to 3019 * static, Maximum buffer size for the limiter configured in cells. 3020 * When the pool associated to the port-pg/tclass is configured to 3021 * dynamic, the max_buff holds the "alpha" parameter, supporting 3022 * the following values: 3023 * 0: 0 3024 * i: (1/128)*2^(i-1), for i=1..14 3025 * 0xFF: Infinity 3026 * Access: RW 3027 */ 3028 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 3029 3030 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 3031 enum mlxsw_reg_sbpm_dir dir, 3032 u32 min_buff, u32 max_buff) 3033 { 3034 MLXSW_REG_ZERO(sbpm, payload); 3035 mlxsw_reg_sbpm_local_port_set(payload, local_port); 3036 mlxsw_reg_sbpm_pool_set(payload, pool); 3037 mlxsw_reg_sbpm_dir_set(payload, dir); 3038 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 3039 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 3040 } 3041 3042 /* SBMM - Shared Buffer Multicast Management Register 3043 * -------------------------------------------------- 3044 * The SBMM register configures and retrieves the shared buffer allocation 3045 * and configuration for MC packets according to Switch-Priority, including 3046 * the binding to pool and definition of the associated quota. 3047 */ 3048 #define MLXSW_REG_SBMM_ID 0xB004 3049 #define MLXSW_REG_SBMM_LEN 0x28 3050 3051 static const struct mlxsw_reg_info mlxsw_reg_sbmm = { 3052 .id = MLXSW_REG_SBMM_ID, 3053 .len = MLXSW_REG_SBMM_LEN, 3054 }; 3055 3056 /* reg_sbmm_prio 3057 * Switch Priority. 3058 * Access: Index 3059 */ 3060 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 3061 3062 /* reg_sbmm_min_buff 3063 * Minimum buffer size for the limiter, in cells. 3064 * Access: RW 3065 */ 3066 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 3067 3068 /* reg_sbmm_max_buff 3069 * When the pool associated to the port-pg/tclass is configured to 3070 * static, Maximum buffer size for the limiter configured in cells. 3071 * When the pool associated to the port-pg/tclass is configured to 3072 * dynamic, the max_buff holds the "alpha" parameter, supporting 3073 * the following values: 3074 * 0: 0 3075 * i: (1/128)*2^(i-1), for i=1..14 3076 * 0xFF: Infinity 3077 * Access: RW 3078 */ 3079 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 3080 3081 /* reg_sbmm_pool 3082 * Association of the port-priority to a pool. 3083 * Access: RW 3084 */ 3085 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 3086 3087 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 3088 u32 max_buff, u8 pool) 3089 { 3090 MLXSW_REG_ZERO(sbmm, payload); 3091 mlxsw_reg_sbmm_prio_set(payload, prio); 3092 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 3093 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 3094 mlxsw_reg_sbmm_pool_set(payload, pool); 3095 } 3096 3097 static inline const char *mlxsw_reg_id_str(u16 reg_id) 3098 { 3099 switch (reg_id) { 3100 case MLXSW_REG_SGCR_ID: 3101 return "SGCR"; 3102 case MLXSW_REG_SPAD_ID: 3103 return "SPAD"; 3104 case MLXSW_REG_SMID_ID: 3105 return "SMID"; 3106 case MLXSW_REG_SSPR_ID: 3107 return "SSPR"; 3108 case MLXSW_REG_SFDAT_ID: 3109 return "SFDAT"; 3110 case MLXSW_REG_SFD_ID: 3111 return "SFD"; 3112 case MLXSW_REG_SFN_ID: 3113 return "SFN"; 3114 case MLXSW_REG_SPMS_ID: 3115 return "SPMS"; 3116 case MLXSW_REG_SPVID_ID: 3117 return "SPVID"; 3118 case MLXSW_REG_SPVM_ID: 3119 return "SPVM"; 3120 case MLXSW_REG_SFGC_ID: 3121 return "SFGC"; 3122 case MLXSW_REG_SFTR_ID: 3123 return "SFTR"; 3124 case MLXSW_REG_SLDR_ID: 3125 return "SLDR"; 3126 case MLXSW_REG_SLCR_ID: 3127 return "SLCR"; 3128 case MLXSW_REG_SLCOR_ID: 3129 return "SLCOR"; 3130 case MLXSW_REG_SPMLR_ID: 3131 return "SPMLR"; 3132 case MLXSW_REG_SVFA_ID: 3133 return "SVFA"; 3134 case MLXSW_REG_SVPE_ID: 3135 return "SVPE"; 3136 case MLXSW_REG_SFMR_ID: 3137 return "SFMR"; 3138 case MLXSW_REG_SPVMLR_ID: 3139 return "SPVMLR"; 3140 case MLXSW_REG_PMLP_ID: 3141 return "PMLP"; 3142 case MLXSW_REG_PMTU_ID: 3143 return "PMTU"; 3144 case MLXSW_REG_PTYS_ID: 3145 return "PTYS"; 3146 case MLXSW_REG_PPAD_ID: 3147 return "PPAD"; 3148 case MLXSW_REG_PAOS_ID: 3149 return "PAOS"; 3150 case MLXSW_REG_PPCNT_ID: 3151 return "PPCNT"; 3152 case MLXSW_REG_PBMC_ID: 3153 return "PBMC"; 3154 case MLXSW_REG_PSPA_ID: 3155 return "PSPA"; 3156 case MLXSW_REG_HTGT_ID: 3157 return "HTGT"; 3158 case MLXSW_REG_HPKT_ID: 3159 return "HPKT"; 3160 case MLXSW_REG_MFCR_ID: 3161 return "MFCR"; 3162 case MLXSW_REG_MFSC_ID: 3163 return "MFSC"; 3164 case MLXSW_REG_MFSM_ID: 3165 return "MFSM"; 3166 case MLXSW_REG_MTCAP_ID: 3167 return "MTCAP"; 3168 case MLXSW_REG_MTMP_ID: 3169 return "MTMP"; 3170 case MLXSW_REG_MLCR_ID: 3171 return "MLCR"; 3172 case MLXSW_REG_SBPR_ID: 3173 return "SBPR"; 3174 case MLXSW_REG_SBCM_ID: 3175 return "SBCM"; 3176 case MLXSW_REG_SBPM_ID: 3177 return "SBPM"; 3178 case MLXSW_REG_SBMM_ID: 3179 return "SBMM"; 3180 default: 3181 return "*UNKNOWN*"; 3182 } 3183 } 3184 3185 /* PUDE - Port Up / Down Event 3186 * --------------------------- 3187 * Reports the operational state change of a port. 3188 */ 3189 #define MLXSW_REG_PUDE_LEN 0x10 3190 3191 /* reg_pude_swid 3192 * Switch partition ID with which to associate the port. 3193 * Access: Index 3194 */ 3195 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 3196 3197 /* reg_pude_local_port 3198 * Local port number. 3199 * Access: Index 3200 */ 3201 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 3202 3203 /* reg_pude_admin_status 3204 * Port administrative state (the desired state). 3205 * 1 - Up. 3206 * 2 - Down. 3207 * 3 - Up once. This means that in case of link failure, the port won't go 3208 * into polling mode, but will wait to be re-enabled by software. 3209 * 4 - Disabled by system. Can only be set by hardware. 3210 * Access: RO 3211 */ 3212 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 3213 3214 /* reg_pude_oper_status 3215 * Port operatioanl state. 3216 * 1 - Up. 3217 * 2 - Down. 3218 * 3 - Down by port failure. This means that the device will not let the 3219 * port up again until explicitly specified by software. 3220 * Access: RO 3221 */ 3222 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 3223 3224 #endif 3225