1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com> 8 * Copyright (c) 2017-2018 Petr Machata <petrm@mellanox.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the names of the copyright holders nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MLXSW_REG_H 40 #define _MLXSW_REG_H 41 42 #include <linux/string.h> 43 #include <linux/bitops.h> 44 #include <linux/if_vlan.h> 45 46 #include "item.h" 47 #include "port.h" 48 49 struct mlxsw_reg_info { 50 u16 id; 51 u16 len; /* In u8 */ 52 const char *name; 53 }; 54 55 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 56 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 57 .id = _id, \ 58 .len = _len, \ 59 .name = #_name, \ 60 } 61 62 #define MLXSW_REG(type) (&mlxsw_reg_##type) 63 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 64 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 65 66 /* SGCR - Switch General Configuration Register 67 * -------------------------------------------- 68 * This register is used for configuration of the switch capabilities. 69 */ 70 #define MLXSW_REG_SGCR_ID 0x2000 71 #define MLXSW_REG_SGCR_LEN 0x10 72 73 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 74 75 /* reg_sgcr_llb 76 * Link Local Broadcast (Default=0) 77 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 78 * packets and ignore the IGMP snooping entries. 79 * Access: RW 80 */ 81 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 82 83 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 84 { 85 MLXSW_REG_ZERO(sgcr, payload); 86 mlxsw_reg_sgcr_llb_set(payload, !!llb); 87 } 88 89 /* SPAD - Switch Physical Address Register 90 * --------------------------------------- 91 * The SPAD register configures the switch physical MAC address. 92 */ 93 #define MLXSW_REG_SPAD_ID 0x2002 94 #define MLXSW_REG_SPAD_LEN 0x10 95 96 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 97 98 /* reg_spad_base_mac 99 * Base MAC address for the switch partitions. 100 * Per switch partition MAC address is equal to: 101 * base_mac + swid 102 * Access: RW 103 */ 104 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 105 106 /* SMID - Switch Multicast ID 107 * -------------------------- 108 * The MID record maps from a MID (Multicast ID), which is a unique identifier 109 * of the multicast group within the stacking domain, into a list of local 110 * ports into which the packet is replicated. 111 */ 112 #define MLXSW_REG_SMID_ID 0x2007 113 #define MLXSW_REG_SMID_LEN 0x240 114 115 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 116 117 /* reg_smid_swid 118 * Switch partition ID. 119 * Access: Index 120 */ 121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 122 123 /* reg_smid_mid 124 * Multicast identifier - global identifier that represents the multicast group 125 * across all devices. 126 * Access: Index 127 */ 128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 129 130 /* reg_smid_port 131 * Local port memebership (1 bit per port). 132 * Access: RW 133 */ 134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 135 136 /* reg_smid_port_mask 137 * Local port mask (1 bit per port). 138 * Access: W 139 */ 140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 141 142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 143 u8 port, bool set) 144 { 145 MLXSW_REG_ZERO(smid, payload); 146 mlxsw_reg_smid_swid_set(payload, 0); 147 mlxsw_reg_smid_mid_set(payload, mid); 148 mlxsw_reg_smid_port_set(payload, port, set); 149 mlxsw_reg_smid_port_mask_set(payload, port, 1); 150 } 151 152 /* SSPR - Switch System Port Record Register 153 * ----------------------------------------- 154 * Configures the system port to local port mapping. 155 */ 156 #define MLXSW_REG_SSPR_ID 0x2008 157 #define MLXSW_REG_SSPR_LEN 0x8 158 159 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 160 161 /* reg_sspr_m 162 * Master - if set, then the record describes the master system port. 163 * This is needed in case a local port is mapped into several system ports 164 * (for multipathing). That number will be reported as the source system 165 * port when packets are forwarded to the CPU. Only one master port is allowed 166 * per local port. 167 * 168 * Note: Must be set for Spectrum. 169 * Access: RW 170 */ 171 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 172 173 /* reg_sspr_local_port 174 * Local port number. 175 * 176 * Access: RW 177 */ 178 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 179 180 /* reg_sspr_sub_port 181 * Virtual port within the physical port. 182 * Should be set to 0 when virtual ports are not enabled on the port. 183 * 184 * Access: RW 185 */ 186 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 187 188 /* reg_sspr_system_port 189 * Unique identifier within the stacking domain that represents all the ports 190 * that are available in the system (external ports). 191 * 192 * Currently, only single-ASIC configurations are supported, so we default to 193 * 1:1 mapping between system ports and local ports. 194 * Access: Index 195 */ 196 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 197 198 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 199 { 200 MLXSW_REG_ZERO(sspr, payload); 201 mlxsw_reg_sspr_m_set(payload, 1); 202 mlxsw_reg_sspr_local_port_set(payload, local_port); 203 mlxsw_reg_sspr_sub_port_set(payload, 0); 204 mlxsw_reg_sspr_system_port_set(payload, local_port); 205 } 206 207 /* SFDAT - Switch Filtering Database Aging Time 208 * -------------------------------------------- 209 * Controls the Switch aging time. Aging time is able to be set per Switch 210 * Partition. 211 */ 212 #define MLXSW_REG_SFDAT_ID 0x2009 213 #define MLXSW_REG_SFDAT_LEN 0x8 214 215 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 216 217 /* reg_sfdat_swid 218 * Switch partition ID. 219 * Access: Index 220 */ 221 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 222 223 /* reg_sfdat_age_time 224 * Aging time in seconds 225 * Min - 10 seconds 226 * Max - 1,000,000 seconds 227 * Default is 300 seconds. 228 * Access: RW 229 */ 230 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 231 232 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 233 { 234 MLXSW_REG_ZERO(sfdat, payload); 235 mlxsw_reg_sfdat_swid_set(payload, 0); 236 mlxsw_reg_sfdat_age_time_set(payload, age_time); 237 } 238 239 /* SFD - Switch Filtering Database 240 * ------------------------------- 241 * The following register defines the access to the filtering database. 242 * The register supports querying, adding, removing and modifying the database. 243 * The access is optimized for bulk updates in which case more than one 244 * FDB record is present in the same command. 245 */ 246 #define MLXSW_REG_SFD_ID 0x200A 247 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 248 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 249 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 250 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 251 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 252 253 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 254 255 /* reg_sfd_swid 256 * Switch partition ID for queries. Reserved on Write. 257 * Access: Index 258 */ 259 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 260 261 enum mlxsw_reg_sfd_op { 262 /* Dump entire FDB a (process according to record_locator) */ 263 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 264 /* Query records by {MAC, VID/FID} value */ 265 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 266 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 267 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 268 /* Test. Response indicates if each of the records could be 269 * added to the FDB. 270 */ 271 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 272 /* Add/modify. Aged-out records cannot be added. This command removes 273 * the learning notification of the {MAC, VID/FID}. Response includes 274 * the entries that were added to the FDB. 275 */ 276 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 277 /* Remove record by {MAC, VID/FID}. This command also removes 278 * the learning notification and aged-out notifications 279 * of the {MAC, VID/FID}. The response provides current (pre-removal) 280 * entries as non-aged-out. 281 */ 282 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 283 /* Remove learned notification by {MAC, VID/FID}. The response provides 284 * the removed learning notification. 285 */ 286 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 287 }; 288 289 /* reg_sfd_op 290 * Operation. 291 * Access: OP 292 */ 293 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 294 295 /* reg_sfd_record_locator 296 * Used for querying the FDB. Use record_locator=0 to initiate the 297 * query. When a record is returned, a new record_locator is 298 * returned to be used in the subsequent query. 299 * Reserved for database update. 300 * Access: Index 301 */ 302 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 303 304 /* reg_sfd_num_rec 305 * Request: Number of records to read/add/modify/remove 306 * Response: Number of records read/added/replaced/removed 307 * See above description for more details. 308 * Ranges 0..64 309 * Access: RW 310 */ 311 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 312 313 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 314 u32 record_locator) 315 { 316 MLXSW_REG_ZERO(sfd, payload); 317 mlxsw_reg_sfd_op_set(payload, op); 318 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 319 } 320 321 /* reg_sfd_rec_swid 322 * Switch partition ID. 323 * Access: Index 324 */ 325 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 326 MLXSW_REG_SFD_REC_LEN, 0x00, false); 327 328 enum mlxsw_reg_sfd_rec_type { 329 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 330 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 331 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 332 }; 333 334 /* reg_sfd_rec_type 335 * FDB record type. 336 * Access: RW 337 */ 338 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 339 MLXSW_REG_SFD_REC_LEN, 0x00, false); 340 341 enum mlxsw_reg_sfd_rec_policy { 342 /* Replacement disabled, aging disabled. */ 343 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 344 /* (mlag remote): Replacement enabled, aging disabled, 345 * learning notification enabled on this port. 346 */ 347 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 348 /* (ingress device): Replacement enabled, aging enabled. */ 349 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 350 }; 351 352 /* reg_sfd_rec_policy 353 * Policy. 354 * Access: RW 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 357 MLXSW_REG_SFD_REC_LEN, 0x00, false); 358 359 /* reg_sfd_rec_a 360 * Activity. Set for new static entries. Set for static entries if a frame SMAC 361 * lookup hits on the entry. 362 * To clear the a bit, use "query and clear activity" op. 363 * Access: RO 364 */ 365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 366 MLXSW_REG_SFD_REC_LEN, 0x00, false); 367 368 /* reg_sfd_rec_mac 369 * MAC address. 370 * Access: Index 371 */ 372 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 373 MLXSW_REG_SFD_REC_LEN, 0x02); 374 375 enum mlxsw_reg_sfd_rec_action { 376 /* forward */ 377 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 378 /* forward and trap, trap_id is FDB_TRAP */ 379 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 380 /* trap and do not forward, trap_id is FDB_TRAP */ 381 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 382 /* forward to IP router */ 383 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 384 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 385 }; 386 387 /* reg_sfd_rec_action 388 * Action to apply on the packet. 389 * Note: Dynamic entries can only be configured with NOP action. 390 * Access: RW 391 */ 392 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 393 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 394 395 /* reg_sfd_uc_sub_port 396 * VEPA channel on local port. 397 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 398 * VEPA is not enabled. 399 * Access: RW 400 */ 401 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 402 MLXSW_REG_SFD_REC_LEN, 0x08, false); 403 404 /* reg_sfd_uc_fid_vid 405 * Filtering ID or VLAN ID 406 * For SwitchX and SwitchX-2: 407 * - Dynamic entries (policy 2,3) use FID 408 * - Static entries (policy 0) use VID 409 * - When independent learning is configured, VID=FID 410 * For Spectrum: use FID for both Dynamic and Static entries. 411 * VID should not be used. 412 * Access: Index 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_system_port 418 * Unique port identifier for the final destination of the packet. 419 * Access: RW 420 */ 421 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 422 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 423 424 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 425 enum mlxsw_reg_sfd_rec_type rec_type, 426 const char *mac, 427 enum mlxsw_reg_sfd_rec_action action) 428 { 429 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 430 431 if (rec_index >= num_rec) 432 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 433 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 434 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 435 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 436 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 437 } 438 439 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 440 enum mlxsw_reg_sfd_rec_policy policy, 441 const char *mac, u16 fid_vid, 442 enum mlxsw_reg_sfd_rec_action action, 443 u8 local_port) 444 { 445 mlxsw_reg_sfd_rec_pack(payload, rec_index, 446 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 448 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 449 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 450 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 451 } 452 453 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 454 char *mac, u16 *p_fid_vid, 455 u8 *p_local_port) 456 { 457 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 458 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 459 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 460 } 461 462 /* reg_sfd_uc_lag_sub_port 463 * LAG sub port. 464 * Must be 0 if multichannel VEPA is not enabled. 465 * Access: RW 466 */ 467 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 468 MLXSW_REG_SFD_REC_LEN, 0x08, false); 469 470 /* reg_sfd_uc_lag_fid_vid 471 * Filtering ID or VLAN ID 472 * For SwitchX and SwitchX-2: 473 * - Dynamic entries (policy 2,3) use FID 474 * - Static entries (policy 0) use VID 475 * - When independent learning is configured, VID=FID 476 * For Spectrum: use FID for both Dynamic and Static entries. 477 * VID should not be used. 478 * Access: Index 479 */ 480 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 481 MLXSW_REG_SFD_REC_LEN, 0x08, false); 482 483 /* reg_sfd_uc_lag_lag_vid 484 * Indicates VID in case of vFIDs. Reserved for FIDs. 485 * Access: RW 486 */ 487 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 488 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 489 490 /* reg_sfd_uc_lag_lag_id 491 * LAG Identifier - pointer into the LAG descriptor table. 492 * Access: RW 493 */ 494 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 495 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 496 497 static inline void 498 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 499 enum mlxsw_reg_sfd_rec_policy policy, 500 const char *mac, u16 fid_vid, 501 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 502 u16 lag_id) 503 { 504 mlxsw_reg_sfd_rec_pack(payload, rec_index, 505 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 506 mac, action); 507 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 508 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 509 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 510 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 511 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 512 } 513 514 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 515 char *mac, u16 *p_vid, 516 u16 *p_lag_id) 517 { 518 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 519 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 520 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 521 } 522 523 /* reg_sfd_mc_pgi 524 * 525 * Multicast port group index - index into the port group table. 526 * Value 0x1FFF indicates the pgi should point to the MID entry. 527 * For Spectrum this value must be set to 0x1FFF 528 * Access: RW 529 */ 530 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 531 MLXSW_REG_SFD_REC_LEN, 0x08, false); 532 533 /* reg_sfd_mc_fid_vid 534 * 535 * Filtering ID or VLAN ID 536 * Access: Index 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 539 MLXSW_REG_SFD_REC_LEN, 0x08, false); 540 541 /* reg_sfd_mc_mid 542 * 543 * Multicast identifier - global identifier that represents the multicast 544 * group across all devices. 545 * Access: RW 546 */ 547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 548 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 549 550 static inline void 551 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 552 const char *mac, u16 fid_vid, 553 enum mlxsw_reg_sfd_rec_action action, u16 mid) 554 { 555 mlxsw_reg_sfd_rec_pack(payload, rec_index, 556 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 557 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 558 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 559 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 560 } 561 562 /* SFN - Switch FDB Notification Register 563 * ------------------------------------------- 564 * The switch provides notifications on newly learned FDB entries and 565 * aged out entries. The notifications can be polled by software. 566 */ 567 #define MLXSW_REG_SFN_ID 0x200B 568 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 569 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 570 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 571 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 572 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 573 574 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 575 576 /* reg_sfn_swid 577 * Switch partition ID. 578 * Access: Index 579 */ 580 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 581 582 /* reg_sfn_end 583 * Forces the current session to end. 584 * Access: OP 585 */ 586 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 587 588 /* reg_sfn_num_rec 589 * Request: Number of learned notifications and aged-out notification 590 * records requested. 591 * Response: Number of notification records returned (must be smaller 592 * than or equal to the value requested) 593 * Ranges 0..64 594 * Access: OP 595 */ 596 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 597 598 static inline void mlxsw_reg_sfn_pack(char *payload) 599 { 600 MLXSW_REG_ZERO(sfn, payload); 601 mlxsw_reg_sfn_swid_set(payload, 0); 602 mlxsw_reg_sfn_end_set(payload, 1); 603 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 604 } 605 606 /* reg_sfn_rec_swid 607 * Switch partition ID. 608 * Access: RO 609 */ 610 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 611 MLXSW_REG_SFN_REC_LEN, 0x00, false); 612 613 enum mlxsw_reg_sfn_rec_type { 614 /* MAC addresses learned on a regular port. */ 615 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 616 /* MAC addresses learned on a LAG port. */ 617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 618 /* Aged-out MAC address on a regular port. */ 619 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 620 /* Aged-out MAC address on a LAG port. */ 621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 622 }; 623 624 /* reg_sfn_rec_type 625 * Notification record type. 626 * Access: RO 627 */ 628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 629 MLXSW_REG_SFN_REC_LEN, 0x00, false); 630 631 /* reg_sfn_rec_mac 632 * MAC address. 633 * Access: RO 634 */ 635 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 636 MLXSW_REG_SFN_REC_LEN, 0x02); 637 638 /* reg_sfn_mac_sub_port 639 * VEPA channel on the local port. 640 * 0 if multichannel VEPA is not enabled. 641 * Access: RO 642 */ 643 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 644 MLXSW_REG_SFN_REC_LEN, 0x08, false); 645 646 /* reg_sfn_mac_fid 647 * Filtering identifier. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 651 MLXSW_REG_SFN_REC_LEN, 0x08, false); 652 653 /* reg_sfn_mac_system_port 654 * Unique port identifier for the final destination of the packet. 655 * Access: RO 656 */ 657 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 658 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 659 660 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 661 char *mac, u16 *p_vid, 662 u8 *p_local_port) 663 { 664 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 665 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 666 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 667 } 668 669 /* reg_sfn_mac_lag_lag_id 670 * LAG ID (pointer into the LAG descriptor table). 671 * Access: RO 672 */ 673 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 674 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 675 676 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 677 char *mac, u16 *p_vid, 678 u16 *p_lag_id) 679 { 680 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 681 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 682 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 683 } 684 685 /* SPMS - Switch Port MSTP/RSTP State Register 686 * ------------------------------------------- 687 * Configures the spanning tree state of a physical port. 688 */ 689 #define MLXSW_REG_SPMS_ID 0x200D 690 #define MLXSW_REG_SPMS_LEN 0x404 691 692 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 693 694 /* reg_spms_local_port 695 * Local port number. 696 * Access: Index 697 */ 698 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 699 700 enum mlxsw_reg_spms_state { 701 MLXSW_REG_SPMS_STATE_NO_CHANGE, 702 MLXSW_REG_SPMS_STATE_DISCARDING, 703 MLXSW_REG_SPMS_STATE_LEARNING, 704 MLXSW_REG_SPMS_STATE_FORWARDING, 705 }; 706 707 /* reg_spms_state 708 * Spanning tree state of each VLAN ID (VID) of the local port. 709 * 0 - Do not change spanning tree state (used only when writing). 710 * 1 - Discarding. No learning or forwarding to/from this port (default). 711 * 2 - Learning. Port is learning, but not forwarding. 712 * 3 - Forwarding. Port is learning and forwarding. 713 * Access: RW 714 */ 715 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 716 717 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 718 { 719 MLXSW_REG_ZERO(spms, payload); 720 mlxsw_reg_spms_local_port_set(payload, local_port); 721 } 722 723 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 724 enum mlxsw_reg_spms_state state) 725 { 726 mlxsw_reg_spms_state_set(payload, vid, state); 727 } 728 729 /* SPVID - Switch Port VID 730 * ----------------------- 731 * The switch port VID configures the default VID for a port. 732 */ 733 #define MLXSW_REG_SPVID_ID 0x200E 734 #define MLXSW_REG_SPVID_LEN 0x08 735 736 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 737 738 /* reg_spvid_local_port 739 * Local port number. 740 * Access: Index 741 */ 742 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 743 744 /* reg_spvid_sub_port 745 * Virtual port within the physical port. 746 * Should be set to 0 when virtual ports are not enabled on the port. 747 * Access: Index 748 */ 749 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 750 751 /* reg_spvid_pvid 752 * Port default VID 753 * Access: RW 754 */ 755 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 756 757 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 758 { 759 MLXSW_REG_ZERO(spvid, payload); 760 mlxsw_reg_spvid_local_port_set(payload, local_port); 761 mlxsw_reg_spvid_pvid_set(payload, pvid); 762 } 763 764 /* SPVM - Switch Port VLAN Membership 765 * ---------------------------------- 766 * The Switch Port VLAN Membership register configures the VLAN membership 767 * of a port in a VLAN denoted by VID. VLAN membership is managed per 768 * virtual port. The register can be used to add and remove VID(s) from a port. 769 */ 770 #define MLXSW_REG_SPVM_ID 0x200F 771 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 772 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 773 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 774 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 775 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 776 777 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 778 779 /* reg_spvm_pt 780 * Priority tagged. If this bit is set, packets forwarded to the port with 781 * untagged VLAN membership (u bit is set) will be tagged with priority tag 782 * (VID=0) 783 * Access: RW 784 */ 785 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 786 787 /* reg_spvm_pte 788 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 789 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 790 * Access: WO 791 */ 792 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 793 794 /* reg_spvm_local_port 795 * Local port number. 796 * Access: Index 797 */ 798 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 799 800 /* reg_spvm_sub_port 801 * Virtual port within the physical port. 802 * Should be set to 0 when virtual ports are not enabled on the port. 803 * Access: Index 804 */ 805 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 806 807 /* reg_spvm_num_rec 808 * Number of records to update. Each record contains: i, e, u, vid. 809 * Access: OP 810 */ 811 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 812 813 /* reg_spvm_rec_i 814 * Ingress membership in VLAN ID. 815 * Access: Index 816 */ 817 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 818 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 819 MLXSW_REG_SPVM_REC_LEN, 0, false); 820 821 /* reg_spvm_rec_e 822 * Egress membership in VLAN ID. 823 * Access: Index 824 */ 825 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 826 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 827 MLXSW_REG_SPVM_REC_LEN, 0, false); 828 829 /* reg_spvm_rec_u 830 * Untagged - port is an untagged member - egress transmission uses untagged 831 * frames on VID<n> 832 * Access: Index 833 */ 834 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 835 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 836 MLXSW_REG_SPVM_REC_LEN, 0, false); 837 838 /* reg_spvm_rec_vid 839 * Egress membership in VLAN ID. 840 * Access: Index 841 */ 842 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 843 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 844 MLXSW_REG_SPVM_REC_LEN, 0, false); 845 846 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 847 u16 vid_begin, u16 vid_end, 848 bool is_member, bool untagged) 849 { 850 int size = vid_end - vid_begin + 1; 851 int i; 852 853 MLXSW_REG_ZERO(spvm, payload); 854 mlxsw_reg_spvm_local_port_set(payload, local_port); 855 mlxsw_reg_spvm_num_rec_set(payload, size); 856 857 for (i = 0; i < size; i++) { 858 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 859 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 860 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 861 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 862 } 863 } 864 865 /* SPAFT - Switch Port Acceptable Frame Types 866 * ------------------------------------------ 867 * The Switch Port Acceptable Frame Types register configures the frame 868 * admittance of the port. 869 */ 870 #define MLXSW_REG_SPAFT_ID 0x2010 871 #define MLXSW_REG_SPAFT_LEN 0x08 872 873 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 874 875 /* reg_spaft_local_port 876 * Local port number. 877 * Access: Index 878 * 879 * Note: CPU port is not supported (all tag types are allowed). 880 */ 881 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 882 883 /* reg_spaft_sub_port 884 * Virtual port within the physical port. 885 * Should be set to 0 when virtual ports are not enabled on the port. 886 * Access: RW 887 */ 888 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 889 890 /* reg_spaft_allow_untagged 891 * When set, untagged frames on the ingress are allowed (default). 892 * Access: RW 893 */ 894 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 895 896 /* reg_spaft_allow_prio_tagged 897 * When set, priority tagged frames on the ingress are allowed (default). 898 * Access: RW 899 */ 900 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 901 902 /* reg_spaft_allow_tagged 903 * When set, tagged frames on the ingress are allowed (default). 904 * Access: RW 905 */ 906 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 907 908 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 909 bool allow_untagged) 910 { 911 MLXSW_REG_ZERO(spaft, payload); 912 mlxsw_reg_spaft_local_port_set(payload, local_port); 913 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 914 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 915 mlxsw_reg_spaft_allow_tagged_set(payload, true); 916 } 917 918 /* SFGC - Switch Flooding Group Configuration 919 * ------------------------------------------ 920 * The following register controls the association of flooding tables and MIDs 921 * to packet types used for flooding. 922 */ 923 #define MLXSW_REG_SFGC_ID 0x2011 924 #define MLXSW_REG_SFGC_LEN 0x10 925 926 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 927 928 enum mlxsw_reg_sfgc_type { 929 MLXSW_REG_SFGC_TYPE_BROADCAST, 930 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 931 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 932 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 933 MLXSW_REG_SFGC_TYPE_RESERVED, 934 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 935 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 936 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 937 MLXSW_REG_SFGC_TYPE_MAX, 938 }; 939 940 /* reg_sfgc_type 941 * The traffic type to reach the flooding table. 942 * Access: Index 943 */ 944 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 945 946 enum mlxsw_reg_sfgc_bridge_type { 947 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 948 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 949 }; 950 951 /* reg_sfgc_bridge_type 952 * Access: Index 953 * 954 * Note: SwitchX-2 only supports 802.1Q mode. 955 */ 956 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 957 958 enum mlxsw_flood_table_type { 959 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 960 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 961 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 962 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 963 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 964 }; 965 966 /* reg_sfgc_table_type 967 * See mlxsw_flood_table_type 968 * Access: RW 969 * 970 * Note: FID offset and FID types are not supported in SwitchX-2. 971 */ 972 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 973 974 /* reg_sfgc_flood_table 975 * Flooding table index to associate with the specific type on the specific 976 * switch partition. 977 * Access: RW 978 */ 979 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 980 981 /* reg_sfgc_mid 982 * The multicast ID for the swid. Not supported for Spectrum 983 * Access: RW 984 */ 985 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 986 987 /* reg_sfgc_counter_set_type 988 * Counter Set Type for flow counters. 989 * Access: RW 990 */ 991 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 992 993 /* reg_sfgc_counter_index 994 * Counter Index for flow counters. 995 * Access: RW 996 */ 997 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 998 999 static inline void 1000 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1001 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1002 enum mlxsw_flood_table_type table_type, 1003 unsigned int flood_table) 1004 { 1005 MLXSW_REG_ZERO(sfgc, payload); 1006 mlxsw_reg_sfgc_type_set(payload, type); 1007 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1008 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1009 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1010 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1011 } 1012 1013 /* SFTR - Switch Flooding Table Register 1014 * ------------------------------------- 1015 * The switch flooding table is used for flooding packet replication. The table 1016 * defines a bit mask of ports for packet replication. 1017 */ 1018 #define MLXSW_REG_SFTR_ID 0x2012 1019 #define MLXSW_REG_SFTR_LEN 0x420 1020 1021 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1022 1023 /* reg_sftr_swid 1024 * Switch partition ID with which to associate the port. 1025 * Access: Index 1026 */ 1027 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1028 1029 /* reg_sftr_flood_table 1030 * Flooding table index to associate with the specific type on the specific 1031 * switch partition. 1032 * Access: Index 1033 */ 1034 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1035 1036 /* reg_sftr_index 1037 * Index. Used as an index into the Flooding Table in case the table is 1038 * configured to use VID / FID or FID Offset. 1039 * Access: Index 1040 */ 1041 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1042 1043 /* reg_sftr_table_type 1044 * See mlxsw_flood_table_type 1045 * Access: RW 1046 */ 1047 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1048 1049 /* reg_sftr_range 1050 * Range of entries to update 1051 * Access: Index 1052 */ 1053 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1054 1055 /* reg_sftr_port 1056 * Local port membership (1 bit per port). 1057 * Access: RW 1058 */ 1059 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1060 1061 /* reg_sftr_cpu_port_mask 1062 * CPU port mask (1 bit per port). 1063 * Access: W 1064 */ 1065 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1066 1067 static inline void mlxsw_reg_sftr_pack(char *payload, 1068 unsigned int flood_table, 1069 unsigned int index, 1070 enum mlxsw_flood_table_type table_type, 1071 unsigned int range, u8 port, bool set) 1072 { 1073 MLXSW_REG_ZERO(sftr, payload); 1074 mlxsw_reg_sftr_swid_set(payload, 0); 1075 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1076 mlxsw_reg_sftr_index_set(payload, index); 1077 mlxsw_reg_sftr_table_type_set(payload, table_type); 1078 mlxsw_reg_sftr_range_set(payload, range); 1079 mlxsw_reg_sftr_port_set(payload, port, set); 1080 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1081 } 1082 1083 /* SFDF - Switch Filtering DB Flush 1084 * -------------------------------- 1085 * The switch filtering DB flush register is used to flush the FDB. 1086 * Note that FDB notifications are flushed as well. 1087 */ 1088 #define MLXSW_REG_SFDF_ID 0x2013 1089 #define MLXSW_REG_SFDF_LEN 0x14 1090 1091 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1092 1093 /* reg_sfdf_swid 1094 * Switch partition ID. 1095 * Access: Index 1096 */ 1097 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1098 1099 enum mlxsw_reg_sfdf_flush_type { 1100 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1101 MLXSW_REG_SFDF_FLUSH_PER_FID, 1102 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1103 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1104 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1105 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1106 }; 1107 1108 /* reg_sfdf_flush_type 1109 * Flush type. 1110 * 0 - All SWID dynamic entries are flushed. 1111 * 1 - All FID dynamic entries are flushed. 1112 * 2 - All dynamic entries pointing to port are flushed. 1113 * 3 - All FID dynamic entries pointing to port are flushed. 1114 * 4 - All dynamic entries pointing to LAG are flushed. 1115 * 5 - All FID dynamic entries pointing to LAG are flushed. 1116 * Access: RW 1117 */ 1118 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1119 1120 /* reg_sfdf_flush_static 1121 * Static. 1122 * 0 - Flush only dynamic entries. 1123 * 1 - Flush both dynamic and static entries. 1124 * Access: RW 1125 */ 1126 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1127 1128 static inline void mlxsw_reg_sfdf_pack(char *payload, 1129 enum mlxsw_reg_sfdf_flush_type type) 1130 { 1131 MLXSW_REG_ZERO(sfdf, payload); 1132 mlxsw_reg_sfdf_flush_type_set(payload, type); 1133 mlxsw_reg_sfdf_flush_static_set(payload, true); 1134 } 1135 1136 /* reg_sfdf_fid 1137 * FID to flush. 1138 * Access: RW 1139 */ 1140 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1141 1142 /* reg_sfdf_system_port 1143 * Port to flush. 1144 * Access: RW 1145 */ 1146 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1147 1148 /* reg_sfdf_port_fid_system_port 1149 * Port to flush, pointed to by FID. 1150 * Access: RW 1151 */ 1152 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1153 1154 /* reg_sfdf_lag_id 1155 * LAG ID to flush. 1156 * Access: RW 1157 */ 1158 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1159 1160 /* reg_sfdf_lag_fid_lag_id 1161 * LAG ID to flush, pointed to by FID. 1162 * Access: RW 1163 */ 1164 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1165 1166 /* SLDR - Switch LAG Descriptor Register 1167 * ----------------------------------------- 1168 * The switch LAG descriptor register is populated by LAG descriptors. 1169 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1170 * max_lag-1. 1171 */ 1172 #define MLXSW_REG_SLDR_ID 0x2014 1173 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1174 1175 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1176 1177 enum mlxsw_reg_sldr_op { 1178 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1179 MLXSW_REG_SLDR_OP_LAG_CREATE, 1180 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1181 /* Ports that appear in the list have the Distributor enabled */ 1182 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1183 /* Removes ports from the disributor list */ 1184 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1185 }; 1186 1187 /* reg_sldr_op 1188 * Operation. 1189 * Access: RW 1190 */ 1191 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1192 1193 /* reg_sldr_lag_id 1194 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1195 * Access: Index 1196 */ 1197 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1198 1199 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1200 { 1201 MLXSW_REG_ZERO(sldr, payload); 1202 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1203 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1204 } 1205 1206 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1207 { 1208 MLXSW_REG_ZERO(sldr, payload); 1209 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1210 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1211 } 1212 1213 /* reg_sldr_num_ports 1214 * The number of member ports of the LAG. 1215 * Reserved for Create / Destroy operations 1216 * For Add / Remove operations - indicates the number of ports in the list. 1217 * Access: RW 1218 */ 1219 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1220 1221 /* reg_sldr_system_port 1222 * System port. 1223 * Access: RW 1224 */ 1225 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1226 1227 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1228 u8 local_port) 1229 { 1230 MLXSW_REG_ZERO(sldr, payload); 1231 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1232 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1233 mlxsw_reg_sldr_num_ports_set(payload, 1); 1234 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1235 } 1236 1237 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1238 u8 local_port) 1239 { 1240 MLXSW_REG_ZERO(sldr, payload); 1241 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1242 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1243 mlxsw_reg_sldr_num_ports_set(payload, 1); 1244 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1245 } 1246 1247 /* SLCR - Switch LAG Configuration 2 Register 1248 * ------------------------------------------- 1249 * The Switch LAG Configuration register is used for configuring the 1250 * LAG properties of the switch. 1251 */ 1252 #define MLXSW_REG_SLCR_ID 0x2015 1253 #define MLXSW_REG_SLCR_LEN 0x10 1254 1255 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1256 1257 enum mlxsw_reg_slcr_pp { 1258 /* Global Configuration (for all ports) */ 1259 MLXSW_REG_SLCR_PP_GLOBAL, 1260 /* Per port configuration, based on local_port field */ 1261 MLXSW_REG_SLCR_PP_PER_PORT, 1262 }; 1263 1264 /* reg_slcr_pp 1265 * Per Port Configuration 1266 * Note: Reading at Global mode results in reading port 1 configuration. 1267 * Access: Index 1268 */ 1269 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1270 1271 /* reg_slcr_local_port 1272 * Local port number 1273 * Supported from CPU port 1274 * Not supported from router port 1275 * Reserved when pp = Global Configuration 1276 * Access: Index 1277 */ 1278 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1279 1280 enum mlxsw_reg_slcr_type { 1281 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1282 MLXSW_REG_SLCR_TYPE_XOR, 1283 MLXSW_REG_SLCR_TYPE_RANDOM, 1284 }; 1285 1286 /* reg_slcr_type 1287 * Hash type 1288 * Access: RW 1289 */ 1290 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1291 1292 /* Ingress port */ 1293 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1294 /* SMAC - for IPv4 and IPv6 packets */ 1295 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1296 /* SMAC - for non-IP packets */ 1297 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1298 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1299 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1300 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1301 /* DMAC - for IPv4 and IPv6 packets */ 1302 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1303 /* DMAC - for non-IP packets */ 1304 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1305 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1306 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1307 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1308 /* Ethertype - for IPv4 and IPv6 packets */ 1309 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1310 /* Ethertype - for non-IP packets */ 1311 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1312 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1313 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1314 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1315 /* VLAN ID - for IPv4 and IPv6 packets */ 1316 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1317 /* VLAN ID - for non-IP packets */ 1318 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1319 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1320 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1321 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1322 /* Source IP address (can be IPv4 or IPv6) */ 1323 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1324 /* Destination IP address (can be IPv4 or IPv6) */ 1325 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1326 /* TCP/UDP source port */ 1327 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1328 /* TCP/UDP destination port*/ 1329 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1330 /* IPv4 Protocol/IPv6 Next Header */ 1331 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1332 /* IPv6 Flow label */ 1333 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1334 /* SID - FCoE source ID */ 1335 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1336 /* DID - FCoE destination ID */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1338 /* OXID - FCoE originator exchange ID */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1340 /* Destination QP number - for RoCE packets */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1342 1343 /* reg_slcr_lag_hash 1344 * LAG hashing configuration. This is a bitmask, in which each set 1345 * bit includes the corresponding item in the LAG hash calculation. 1346 * The default lag_hash contains SMAC, DMAC, VLANID and 1347 * Ethertype (for all packet types). 1348 * Access: RW 1349 */ 1350 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1351 1352 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1353 { 1354 MLXSW_REG_ZERO(slcr, payload); 1355 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1356 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1357 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1358 } 1359 1360 /* SLCOR - Switch LAG Collector Register 1361 * ------------------------------------- 1362 * The Switch LAG Collector register controls the Local Port membership 1363 * in a LAG and enablement of the collector. 1364 */ 1365 #define MLXSW_REG_SLCOR_ID 0x2016 1366 #define MLXSW_REG_SLCOR_LEN 0x10 1367 1368 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1369 1370 enum mlxsw_reg_slcor_col { 1371 /* Port is added with collector disabled */ 1372 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1373 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1374 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1375 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1376 }; 1377 1378 /* reg_slcor_col 1379 * Collector configuration 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1383 1384 /* reg_slcor_local_port 1385 * Local port number 1386 * Not supported for CPU port 1387 * Access: Index 1388 */ 1389 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1390 1391 /* reg_slcor_lag_id 1392 * LAG Identifier. Index into the LAG descriptor table. 1393 * Access: Index 1394 */ 1395 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1396 1397 /* reg_slcor_port_index 1398 * Port index in the LAG list. Only valid on Add Port to LAG col. 1399 * Valid range is from 0 to cap_max_lag_members-1 1400 * Access: RW 1401 */ 1402 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1403 1404 static inline void mlxsw_reg_slcor_pack(char *payload, 1405 u8 local_port, u16 lag_id, 1406 enum mlxsw_reg_slcor_col col) 1407 { 1408 MLXSW_REG_ZERO(slcor, payload); 1409 mlxsw_reg_slcor_col_set(payload, col); 1410 mlxsw_reg_slcor_local_port_set(payload, local_port); 1411 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1412 } 1413 1414 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1415 u8 local_port, u16 lag_id, 1416 u8 port_index) 1417 { 1418 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1419 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1420 mlxsw_reg_slcor_port_index_set(payload, port_index); 1421 } 1422 1423 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1424 u8 local_port, u16 lag_id) 1425 { 1426 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1427 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1428 } 1429 1430 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1431 u8 local_port, u16 lag_id) 1432 { 1433 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1435 } 1436 1437 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1438 u8 local_port, u16 lag_id) 1439 { 1440 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1441 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1442 } 1443 1444 /* SPMLR - Switch Port MAC Learning Register 1445 * ----------------------------------------- 1446 * Controls the Switch MAC learning policy per port. 1447 */ 1448 #define MLXSW_REG_SPMLR_ID 0x2018 1449 #define MLXSW_REG_SPMLR_LEN 0x8 1450 1451 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1452 1453 /* reg_spmlr_local_port 1454 * Local port number. 1455 * Access: Index 1456 */ 1457 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1458 1459 /* reg_spmlr_sub_port 1460 * Virtual port within the physical port. 1461 * Should be set to 0 when virtual ports are not enabled on the port. 1462 * Access: Index 1463 */ 1464 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1465 1466 enum mlxsw_reg_spmlr_learn_mode { 1467 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1468 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1469 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1470 }; 1471 1472 /* reg_spmlr_learn_mode 1473 * Learning mode on the port. 1474 * 0 - Learning disabled. 1475 * 2 - Learning enabled. 1476 * 3 - Security mode. 1477 * 1478 * In security mode the switch does not learn MACs on the port, but uses the 1479 * SMAC to see if it exists on another ingress port. If so, the packet is 1480 * classified as a bad packet and is discarded unless the software registers 1481 * to receive port security error packets usign HPKT. 1482 */ 1483 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1484 1485 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1486 enum mlxsw_reg_spmlr_learn_mode mode) 1487 { 1488 MLXSW_REG_ZERO(spmlr, payload); 1489 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1490 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1491 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1492 } 1493 1494 /* SVFA - Switch VID to FID Allocation Register 1495 * -------------------------------------------- 1496 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1497 * virtualized ports. 1498 */ 1499 #define MLXSW_REG_SVFA_ID 0x201C 1500 #define MLXSW_REG_SVFA_LEN 0x10 1501 1502 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1503 1504 /* reg_svfa_swid 1505 * Switch partition ID. 1506 * Access: Index 1507 */ 1508 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1509 1510 /* reg_svfa_local_port 1511 * Local port number. 1512 * Access: Index 1513 * 1514 * Note: Reserved for 802.1Q FIDs. 1515 */ 1516 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1517 1518 enum mlxsw_reg_svfa_mt { 1519 MLXSW_REG_SVFA_MT_VID_TO_FID, 1520 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1521 }; 1522 1523 /* reg_svfa_mapping_table 1524 * Mapping table: 1525 * 0 - VID to FID 1526 * 1 - {Port, VID} to FID 1527 * Access: Index 1528 * 1529 * Note: Reserved for SwitchX-2. 1530 */ 1531 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1532 1533 /* reg_svfa_v 1534 * Valid. 1535 * Valid if set. 1536 * Access: RW 1537 * 1538 * Note: Reserved for SwitchX-2. 1539 */ 1540 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1541 1542 /* reg_svfa_fid 1543 * Filtering ID. 1544 * Access: RW 1545 */ 1546 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1547 1548 /* reg_svfa_vid 1549 * VLAN ID. 1550 * Access: Index 1551 */ 1552 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1553 1554 /* reg_svfa_counter_set_type 1555 * Counter set type for flow counters. 1556 * Access: RW 1557 * 1558 * Note: Reserved for SwitchX-2. 1559 */ 1560 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1561 1562 /* reg_svfa_counter_index 1563 * Counter index for flow counters. 1564 * Access: RW 1565 * 1566 * Note: Reserved for SwitchX-2. 1567 */ 1568 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1569 1570 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1571 enum mlxsw_reg_svfa_mt mt, bool valid, 1572 u16 fid, u16 vid) 1573 { 1574 MLXSW_REG_ZERO(svfa, payload); 1575 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1576 mlxsw_reg_svfa_swid_set(payload, 0); 1577 mlxsw_reg_svfa_local_port_set(payload, local_port); 1578 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1579 mlxsw_reg_svfa_v_set(payload, valid); 1580 mlxsw_reg_svfa_fid_set(payload, fid); 1581 mlxsw_reg_svfa_vid_set(payload, vid); 1582 } 1583 1584 /* SVPE - Switch Virtual-Port Enabling Register 1585 * -------------------------------------------- 1586 * Enables port virtualization. 1587 */ 1588 #define MLXSW_REG_SVPE_ID 0x201E 1589 #define MLXSW_REG_SVPE_LEN 0x4 1590 1591 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1592 1593 /* reg_svpe_local_port 1594 * Local port number 1595 * Access: Index 1596 * 1597 * Note: CPU port is not supported (uses VLAN mode only). 1598 */ 1599 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1600 1601 /* reg_svpe_vp_en 1602 * Virtual port enable. 1603 * 0 - Disable, VLAN mode (VID to FID). 1604 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1608 1609 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1610 bool enable) 1611 { 1612 MLXSW_REG_ZERO(svpe, payload); 1613 mlxsw_reg_svpe_local_port_set(payload, local_port); 1614 mlxsw_reg_svpe_vp_en_set(payload, enable); 1615 } 1616 1617 /* SFMR - Switch FID Management Register 1618 * ------------------------------------- 1619 * Creates and configures FIDs. 1620 */ 1621 #define MLXSW_REG_SFMR_ID 0x201F 1622 #define MLXSW_REG_SFMR_LEN 0x18 1623 1624 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1625 1626 enum mlxsw_reg_sfmr_op { 1627 MLXSW_REG_SFMR_OP_CREATE_FID, 1628 MLXSW_REG_SFMR_OP_DESTROY_FID, 1629 }; 1630 1631 /* reg_sfmr_op 1632 * Operation. 1633 * 0 - Create or edit FID. 1634 * 1 - Destroy FID. 1635 * Access: WO 1636 */ 1637 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1638 1639 /* reg_sfmr_fid 1640 * Filtering ID. 1641 * Access: Index 1642 */ 1643 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1644 1645 /* reg_sfmr_fid_offset 1646 * FID offset. 1647 * Used to point into the flooding table selected by SFGC register if 1648 * the table is of type FID-Offset. Otherwise, this field is reserved. 1649 * Access: RW 1650 */ 1651 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1652 1653 /* reg_sfmr_vtfp 1654 * Valid Tunnel Flood Pointer. 1655 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1656 * Access: RW 1657 * 1658 * Note: Reserved for 802.1Q FIDs. 1659 */ 1660 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1661 1662 /* reg_sfmr_nve_tunnel_flood_ptr 1663 * Underlay Flooding and BC Pointer. 1664 * Used as a pointer to the first entry of the group based link lists of 1665 * flooding or BC entries (for NVE tunnels). 1666 * Access: RW 1667 */ 1668 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1669 1670 /* reg_sfmr_vv 1671 * VNI Valid. 1672 * If not set, then vni is reserved. 1673 * Access: RW 1674 * 1675 * Note: Reserved for 802.1Q FIDs. 1676 */ 1677 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1678 1679 /* reg_sfmr_vni 1680 * Virtual Network Identifier. 1681 * Access: RW 1682 * 1683 * Note: A given VNI can only be assigned to one FID. 1684 */ 1685 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1686 1687 static inline void mlxsw_reg_sfmr_pack(char *payload, 1688 enum mlxsw_reg_sfmr_op op, u16 fid, 1689 u16 fid_offset) 1690 { 1691 MLXSW_REG_ZERO(sfmr, payload); 1692 mlxsw_reg_sfmr_op_set(payload, op); 1693 mlxsw_reg_sfmr_fid_set(payload, fid); 1694 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1695 mlxsw_reg_sfmr_vtfp_set(payload, false); 1696 mlxsw_reg_sfmr_vv_set(payload, false); 1697 } 1698 1699 /* SPVMLR - Switch Port VLAN MAC Learning Register 1700 * ----------------------------------------------- 1701 * Controls the switch MAC learning policy per {Port, VID}. 1702 */ 1703 #define MLXSW_REG_SPVMLR_ID 0x2020 1704 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1705 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1706 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1707 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1708 MLXSW_REG_SPVMLR_REC_LEN * \ 1709 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1710 1711 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1712 1713 /* reg_spvmlr_local_port 1714 * Local ingress port. 1715 * Access: Index 1716 * 1717 * Note: CPU port is not supported. 1718 */ 1719 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1720 1721 /* reg_spvmlr_num_rec 1722 * Number of records to update. 1723 * Access: OP 1724 */ 1725 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1726 1727 /* reg_spvmlr_rec_learn_enable 1728 * 0 - Disable learning for {Port, VID}. 1729 * 1 - Enable learning for {Port, VID}. 1730 * Access: RW 1731 */ 1732 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1733 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1734 1735 /* reg_spvmlr_rec_vid 1736 * VLAN ID to be added/removed from port or for querying. 1737 * Access: Index 1738 */ 1739 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1740 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1741 1742 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1743 u16 vid_begin, u16 vid_end, 1744 bool learn_enable) 1745 { 1746 int num_rec = vid_end - vid_begin + 1; 1747 int i; 1748 1749 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1750 1751 MLXSW_REG_ZERO(spvmlr, payload); 1752 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1753 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1754 1755 for (i = 0; i < num_rec; i++) { 1756 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1757 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1758 } 1759 } 1760 1761 /* CWTP - Congetion WRED ECN TClass Profile 1762 * ---------------------------------------- 1763 * Configures the profiles for queues of egress port and traffic class 1764 */ 1765 #define MLXSW_REG_CWTP_ID 0x2802 1766 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1767 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1768 #define MLXSW_REG_CWTP_LEN 0x40 1769 1770 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1771 1772 /* reg_cwtp_local_port 1773 * Local port number 1774 * Not supported for CPU port 1775 * Access: Index 1776 */ 1777 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1778 1779 /* reg_cwtp_traffic_class 1780 * Traffic Class to configure 1781 * Access: Index 1782 */ 1783 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1784 1785 /* reg_cwtp_profile_min 1786 * Minimum Average Queue Size of the profile in cells. 1787 * Access: RW 1788 */ 1789 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1790 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1791 1792 /* reg_cwtp_profile_percent 1793 * Percentage of WRED and ECN marking for maximum Average Queue size 1794 * Range is 0 to 100, units of integer percentage 1795 * Access: RW 1796 */ 1797 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1798 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1799 1800 /* reg_cwtp_profile_max 1801 * Maximum Average Queue size of the profile in cells 1802 * Access: RW 1803 */ 1804 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1805 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1806 1807 #define MLXSW_REG_CWTP_MIN_VALUE 64 1808 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1809 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1810 1811 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1812 u8 traffic_class) 1813 { 1814 int i; 1815 1816 MLXSW_REG_ZERO(cwtp, payload); 1817 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1818 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1819 1820 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1821 mlxsw_reg_cwtp_profile_min_set(payload, i, 1822 MLXSW_REG_CWTP_MIN_VALUE); 1823 mlxsw_reg_cwtp_profile_max_set(payload, i, 1824 MLXSW_REG_CWTP_MIN_VALUE); 1825 } 1826 } 1827 1828 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1829 1830 static inline void 1831 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1832 u32 probability) 1833 { 1834 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1835 1836 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1837 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1838 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1839 } 1840 1841 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1842 * --------------------------------------------------- 1843 * The CWTPM register maps each egress port and traffic class to profile num. 1844 */ 1845 #define MLXSW_REG_CWTPM_ID 0x2803 1846 #define MLXSW_REG_CWTPM_LEN 0x44 1847 1848 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1849 1850 /* reg_cwtpm_local_port 1851 * Local port number 1852 * Not supported for CPU port 1853 * Access: Index 1854 */ 1855 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1856 1857 /* reg_cwtpm_traffic_class 1858 * Traffic Class to configure 1859 * Access: Index 1860 */ 1861 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1862 1863 /* reg_cwtpm_ew 1864 * Control enablement of WRED for traffic class: 1865 * 0 - Disable 1866 * 1 - Enable 1867 * Access: RW 1868 */ 1869 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1870 1871 /* reg_cwtpm_ee 1872 * Control enablement of ECN for traffic class: 1873 * 0 - Disable 1874 * 1 - Enable 1875 * Access: RW 1876 */ 1877 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1878 1879 /* reg_cwtpm_tcp_g 1880 * TCP Green Profile. 1881 * Index of the profile within {port, traffic class} to use. 1882 * 0 for disabling both WRED and ECN for this type of traffic. 1883 * Access: RW 1884 */ 1885 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1886 1887 /* reg_cwtpm_tcp_y 1888 * TCP Yellow Profile. 1889 * Index of the profile within {port, traffic class} to use. 1890 * 0 for disabling both WRED and ECN for this type of traffic. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1894 1895 /* reg_cwtpm_tcp_r 1896 * TCP Red Profile. 1897 * Index of the profile within {port, traffic class} to use. 1898 * 0 for disabling both WRED and ECN for this type of traffic. 1899 * Access: RW 1900 */ 1901 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 1902 1903 /* reg_cwtpm_ntcp_g 1904 * Non-TCP Green Profile. 1905 * Index of the profile within {port, traffic class} to use. 1906 * 0 for disabling both WRED and ECN for this type of traffic. 1907 * Access: RW 1908 */ 1909 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 1910 1911 /* reg_cwtpm_ntcp_y 1912 * Non-TCP Yellow Profile. 1913 * Index of the profile within {port, traffic class} to use. 1914 * 0 for disabling both WRED and ECN for this type of traffic. 1915 * Access: RW 1916 */ 1917 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 1918 1919 /* reg_cwtpm_ntcp_r 1920 * Non-TCP Red Profile. 1921 * Index of the profile within {port, traffic class} to use. 1922 * 0 for disabling both WRED and ECN for this type of traffic. 1923 * Access: RW 1924 */ 1925 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 1926 1927 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 1928 1929 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 1930 u8 traffic_class, u8 profile, 1931 bool wred, bool ecn) 1932 { 1933 MLXSW_REG_ZERO(cwtpm, payload); 1934 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 1935 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 1936 mlxsw_reg_cwtpm_ew_set(payload, wred); 1937 mlxsw_reg_cwtpm_ee_set(payload, ecn); 1938 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 1939 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 1940 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 1941 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 1942 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 1943 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 1944 } 1945 1946 /* PPBT - Policy-Engine Port Binding Table 1947 * --------------------------------------- 1948 * This register is used for configuration of the Port Binding Table. 1949 */ 1950 #define MLXSW_REG_PPBT_ID 0x3002 1951 #define MLXSW_REG_PPBT_LEN 0x14 1952 1953 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 1954 1955 enum mlxsw_reg_pxbt_e { 1956 MLXSW_REG_PXBT_E_IACL, 1957 MLXSW_REG_PXBT_E_EACL, 1958 }; 1959 1960 /* reg_ppbt_e 1961 * Access: Index 1962 */ 1963 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 1964 1965 enum mlxsw_reg_pxbt_op { 1966 MLXSW_REG_PXBT_OP_BIND, 1967 MLXSW_REG_PXBT_OP_UNBIND, 1968 }; 1969 1970 /* reg_ppbt_op 1971 * Access: RW 1972 */ 1973 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 1974 1975 /* reg_ppbt_local_port 1976 * Local port. Not including CPU port. 1977 * Access: Index 1978 */ 1979 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 1980 1981 /* reg_ppbt_g 1982 * group - When set, the binding is of an ACL group. When cleared, 1983 * the binding is of an ACL. 1984 * Must be set to 1 for Spectrum. 1985 * Access: RW 1986 */ 1987 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 1988 1989 /* reg_ppbt_acl_info 1990 * ACL/ACL group identifier. If the g bit is set, this field should hold 1991 * the acl_group_id, else it should hold the acl_id. 1992 * Access: RW 1993 */ 1994 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 1995 1996 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 1997 enum mlxsw_reg_pxbt_op op, 1998 u8 local_port, u16 acl_info) 1999 { 2000 MLXSW_REG_ZERO(ppbt, payload); 2001 mlxsw_reg_ppbt_e_set(payload, e); 2002 mlxsw_reg_ppbt_op_set(payload, op); 2003 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2004 mlxsw_reg_ppbt_g_set(payload, true); 2005 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2006 } 2007 2008 /* PACL - Policy-Engine ACL Register 2009 * --------------------------------- 2010 * This register is used for configuration of the ACL. 2011 */ 2012 #define MLXSW_REG_PACL_ID 0x3004 2013 #define MLXSW_REG_PACL_LEN 0x70 2014 2015 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2016 2017 /* reg_pacl_v 2018 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2019 * while the ACL is bounded to either a port, VLAN or ACL rule. 2020 * Access: RW 2021 */ 2022 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2023 2024 /* reg_pacl_acl_id 2025 * An identifier representing the ACL (managed by software) 2026 * Range 0 .. cap_max_acl_regions - 1 2027 * Access: Index 2028 */ 2029 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2030 2031 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2032 2033 /* reg_pacl_tcam_region_info 2034 * Opaque object that represents a TCAM region. 2035 * Obtained through PTAR register. 2036 * Access: RW 2037 */ 2038 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2039 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2040 2041 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2042 bool valid, const char *tcam_region_info) 2043 { 2044 MLXSW_REG_ZERO(pacl, payload); 2045 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2046 mlxsw_reg_pacl_v_set(payload, valid); 2047 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2048 } 2049 2050 /* PAGT - Policy-Engine ACL Group Table 2051 * ------------------------------------ 2052 * This register is used for configuration of the ACL Group Table. 2053 */ 2054 #define MLXSW_REG_PAGT_ID 0x3005 2055 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2056 #define MLXSW_REG_PAGT_ACL_LEN 4 2057 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2058 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2059 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2060 2061 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2062 2063 /* reg_pagt_size 2064 * Number of ACLs in the group. 2065 * Size 0 invalidates a group. 2066 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2067 * Total number of ACLs in all groups must be lower or equal 2068 * to cap_max_acl_tot_groups 2069 * Note: a group which is binded must not be invalidated 2070 * Access: Index 2071 */ 2072 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2073 2074 /* reg_pagt_acl_group_id 2075 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2076 * the ACL Group identifier (managed by software). 2077 * Access: Index 2078 */ 2079 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2080 2081 /* reg_pagt_acl_id 2082 * ACL identifier 2083 * Access: RW 2084 */ 2085 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2086 2087 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2088 { 2089 MLXSW_REG_ZERO(pagt, payload); 2090 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2091 } 2092 2093 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2094 u16 acl_id) 2095 { 2096 u8 size = mlxsw_reg_pagt_size_get(payload); 2097 2098 if (index >= size) 2099 mlxsw_reg_pagt_size_set(payload, index + 1); 2100 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2101 } 2102 2103 /* PTAR - Policy-Engine TCAM Allocation Register 2104 * --------------------------------------------- 2105 * This register is used for allocation of regions in the TCAM. 2106 * Note: Query method is not supported on this register. 2107 */ 2108 #define MLXSW_REG_PTAR_ID 0x3006 2109 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2110 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2111 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2112 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2113 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2114 2115 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2116 2117 enum mlxsw_reg_ptar_op { 2118 /* allocate a TCAM region */ 2119 MLXSW_REG_PTAR_OP_ALLOC, 2120 /* resize a TCAM region */ 2121 MLXSW_REG_PTAR_OP_RESIZE, 2122 /* deallocate TCAM region */ 2123 MLXSW_REG_PTAR_OP_FREE, 2124 /* test allocation */ 2125 MLXSW_REG_PTAR_OP_TEST, 2126 }; 2127 2128 /* reg_ptar_op 2129 * Access: OP 2130 */ 2131 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2132 2133 /* reg_ptar_action_set_type 2134 * Type of action set to be used on this region. 2135 * For Spectrum, this is always type 2 - "flexible" 2136 * Access: WO 2137 */ 2138 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2139 2140 /* reg_ptar_key_type 2141 * TCAM key type for the region. 2142 * For Spectrum, this is always type 0x50 - "FLEX_KEY" 2143 * Access: WO 2144 */ 2145 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2146 2147 /* reg_ptar_region_size 2148 * TCAM region size. When allocating/resizing this is the requested size, 2149 * the response is the actual size. Note that actual size may be 2150 * larger than requested. 2151 * Allowed range 1 .. cap_max_rules-1 2152 * Reserved during op deallocate. 2153 * Access: WO 2154 */ 2155 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2156 2157 /* reg_ptar_region_id 2158 * Region identifier 2159 * Range 0 .. cap_max_regions-1 2160 * Access: Index 2161 */ 2162 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2163 2164 /* reg_ptar_tcam_region_info 2165 * Opaque object that represents the TCAM region. 2166 * Returned when allocating a region. 2167 * Provided by software for ACL generation and region deallocation and resize. 2168 * Access: RW 2169 */ 2170 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2171 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2172 2173 /* reg_ptar_flexible_key_id 2174 * Identifier of the Flexible Key. 2175 * Only valid if key_type == "FLEX_KEY" 2176 * The key size will be rounded up to one of the following values: 2177 * 9B, 18B, 36B, 54B. 2178 * This field is reserved for in resize operation. 2179 * Access: WO 2180 */ 2181 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2182 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2183 2184 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2185 u16 region_size, u16 region_id, 2186 const char *tcam_region_info) 2187 { 2188 MLXSW_REG_ZERO(ptar, payload); 2189 mlxsw_reg_ptar_op_set(payload, op); 2190 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2191 mlxsw_reg_ptar_key_type_set(payload, 0x50); /* "FLEX_KEY" */ 2192 mlxsw_reg_ptar_region_size_set(payload, region_size); 2193 mlxsw_reg_ptar_region_id_set(payload, region_id); 2194 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2195 } 2196 2197 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2198 u16 key_id) 2199 { 2200 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2201 } 2202 2203 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2204 { 2205 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2206 } 2207 2208 /* PPBS - Policy-Engine Policy Based Switching Register 2209 * ---------------------------------------------------- 2210 * This register retrieves and sets Policy Based Switching Table entries. 2211 */ 2212 #define MLXSW_REG_PPBS_ID 0x300C 2213 #define MLXSW_REG_PPBS_LEN 0x14 2214 2215 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2216 2217 /* reg_ppbs_pbs_ptr 2218 * Index into the PBS table. 2219 * For Spectrum, the index points to the KVD Linear. 2220 * Access: Index 2221 */ 2222 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2223 2224 /* reg_ppbs_system_port 2225 * Unique port identifier for the final destination of the packet. 2226 * Access: RW 2227 */ 2228 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2229 2230 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2231 u16 system_port) 2232 { 2233 MLXSW_REG_ZERO(ppbs, payload); 2234 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2235 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2236 } 2237 2238 /* PRCR - Policy-Engine Rules Copy Register 2239 * ---------------------------------------- 2240 * This register is used for accessing rules within a TCAM region. 2241 */ 2242 #define MLXSW_REG_PRCR_ID 0x300D 2243 #define MLXSW_REG_PRCR_LEN 0x40 2244 2245 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2246 2247 enum mlxsw_reg_prcr_op { 2248 /* Move rules. Moves the rules from "tcam_region_info" starting 2249 * at offset "offset" to "dest_tcam_region_info" 2250 * at offset "dest_offset." 2251 */ 2252 MLXSW_REG_PRCR_OP_MOVE, 2253 /* Copy rules. Copies the rules from "tcam_region_info" starting 2254 * at offset "offset" to "dest_tcam_region_info" 2255 * at offset "dest_offset." 2256 */ 2257 MLXSW_REG_PRCR_OP_COPY, 2258 }; 2259 2260 /* reg_prcr_op 2261 * Access: OP 2262 */ 2263 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2264 2265 /* reg_prcr_offset 2266 * Offset within the source region to copy/move from. 2267 * Access: Index 2268 */ 2269 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2270 2271 /* reg_prcr_size 2272 * The number of rules to copy/move. 2273 * Access: WO 2274 */ 2275 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2276 2277 /* reg_prcr_tcam_region_info 2278 * Opaque object that represents the source TCAM region. 2279 * Access: Index 2280 */ 2281 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2282 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2283 2284 /* reg_prcr_dest_offset 2285 * Offset within the source region to copy/move to. 2286 * Access: Index 2287 */ 2288 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2289 2290 /* reg_prcr_dest_tcam_region_info 2291 * Opaque object that represents the destination TCAM region. 2292 * Access: Index 2293 */ 2294 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2295 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2296 2297 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2298 const char *src_tcam_region_info, 2299 u16 src_offset, 2300 const char *dest_tcam_region_info, 2301 u16 dest_offset, u16 size) 2302 { 2303 MLXSW_REG_ZERO(prcr, payload); 2304 mlxsw_reg_prcr_op_set(payload, op); 2305 mlxsw_reg_prcr_offset_set(payload, src_offset); 2306 mlxsw_reg_prcr_size_set(payload, size); 2307 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2308 src_tcam_region_info); 2309 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2310 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2311 dest_tcam_region_info); 2312 } 2313 2314 /* PEFA - Policy-Engine Extended Flexible Action Register 2315 * ------------------------------------------------------ 2316 * This register is used for accessing an extended flexible action entry 2317 * in the central KVD Linear Database. 2318 */ 2319 #define MLXSW_REG_PEFA_ID 0x300F 2320 #define MLXSW_REG_PEFA_LEN 0xB0 2321 2322 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2323 2324 /* reg_pefa_index 2325 * Index in the KVD Linear Centralized Database. 2326 * Access: Index 2327 */ 2328 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2329 2330 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2331 2332 /* reg_pefa_flex_action_set 2333 * Action-set to perform when rule is matched. 2334 * Must be zero padded if action set is shorter. 2335 * Access: RW 2336 */ 2337 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2338 2339 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, 2340 const char *flex_action_set) 2341 { 2342 MLXSW_REG_ZERO(pefa, payload); 2343 mlxsw_reg_pefa_index_set(payload, index); 2344 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, flex_action_set); 2345 } 2346 2347 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2348 * ----------------------------------------------------- 2349 * This register is used for accessing rules within a TCAM region. 2350 * It is a new version of PTCE in order to support wider key, 2351 * mask and action within a TCAM region. This register is not supported 2352 * by SwitchX and SwitchX-2. 2353 */ 2354 #define MLXSW_REG_PTCE2_ID 0x3017 2355 #define MLXSW_REG_PTCE2_LEN 0x1D8 2356 2357 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2358 2359 /* reg_ptce2_v 2360 * Valid. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2364 2365 /* reg_ptce2_a 2366 * Activity. Set if a packet lookup has hit on the specific entry. 2367 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2368 * Access: RO 2369 */ 2370 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2371 2372 enum mlxsw_reg_ptce2_op { 2373 /* Read operation. */ 2374 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2375 /* clear on read operation. Used to read entry 2376 * and clear Activity bit. 2377 */ 2378 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2379 /* Write operation. Used to write a new entry to the table. 2380 * All R/W fields are relevant for new entry. Activity bit is set 2381 * for new entries - Note write with v = 0 will delete the entry. 2382 */ 2383 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2384 /* Update action. Only action set will be updated. */ 2385 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2386 /* Clear activity. A bit is cleared for the entry. */ 2387 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2388 }; 2389 2390 /* reg_ptce2_op 2391 * Access: OP 2392 */ 2393 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2394 2395 /* reg_ptce2_offset 2396 * Access: Index 2397 */ 2398 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2399 2400 /* reg_ptce2_tcam_region_info 2401 * Opaque object that represents the TCAM region. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2405 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2406 2407 #define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96 2408 2409 /* reg_ptce2_flex_key_blocks 2410 * ACL Key. 2411 * Access: RW 2412 */ 2413 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2414 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2415 2416 /* reg_ptce2_mask 2417 * mask- in the same size as key. A bit that is set directs the TCAM 2418 * to compare the corresponding bit in key. A bit that is clear directs 2419 * the TCAM to ignore the corresponding bit in key. 2420 * Access: RW 2421 */ 2422 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2423 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2424 2425 /* reg_ptce2_flex_action_set 2426 * ACL action set. 2427 * Access: RW 2428 */ 2429 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2430 MLXSW_REG_FLEX_ACTION_SET_LEN); 2431 2432 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2433 enum mlxsw_reg_ptce2_op op, 2434 const char *tcam_region_info, 2435 u16 offset) 2436 { 2437 MLXSW_REG_ZERO(ptce2, payload); 2438 mlxsw_reg_ptce2_v_set(payload, valid); 2439 mlxsw_reg_ptce2_op_set(payload, op); 2440 mlxsw_reg_ptce2_offset_set(payload, offset); 2441 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2442 } 2443 2444 /* QPCR - QoS Policer Configuration Register 2445 * ----------------------------------------- 2446 * The QPCR register is used to create policers - that limit 2447 * the rate of bytes or packets via some trap group. 2448 */ 2449 #define MLXSW_REG_QPCR_ID 0x4004 2450 #define MLXSW_REG_QPCR_LEN 0x28 2451 2452 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 2453 2454 enum mlxsw_reg_qpcr_g { 2455 MLXSW_REG_QPCR_G_GLOBAL = 2, 2456 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 2457 }; 2458 2459 /* reg_qpcr_g 2460 * The policer type. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 2464 2465 /* reg_qpcr_pid 2466 * Policer ID. 2467 * Access: Index 2468 */ 2469 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 2470 2471 /* reg_qpcr_color_aware 2472 * Is the policer aware of colors. 2473 * Must be 0 (unaware) for cpu port. 2474 * Access: RW for unbounded policer. RO for bounded policer. 2475 */ 2476 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 2477 2478 /* reg_qpcr_bytes 2479 * Is policer limit is for bytes per sec or packets per sec. 2480 * 0 - packets 2481 * 1 - bytes 2482 * Access: RW for unbounded policer. RO for bounded policer. 2483 */ 2484 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 2485 2486 enum mlxsw_reg_qpcr_ir_units { 2487 MLXSW_REG_QPCR_IR_UNITS_M, 2488 MLXSW_REG_QPCR_IR_UNITS_K, 2489 }; 2490 2491 /* reg_qpcr_ir_units 2492 * Policer's units for cir and eir fields (for bytes limits only) 2493 * 1 - 10^3 2494 * 0 - 10^6 2495 * Access: OP 2496 */ 2497 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 2498 2499 enum mlxsw_reg_qpcr_rate_type { 2500 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 2501 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 2502 }; 2503 2504 /* reg_qpcr_rate_type 2505 * Policer can have one limit (single rate) or 2 limits with specific operation 2506 * for packets that exceed the lower rate but not the upper one. 2507 * (For cpu port must be single rate) 2508 * Access: RW for unbounded policer. RO for bounded policer. 2509 */ 2510 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 2511 2512 /* reg_qpc_cbs 2513 * Policer's committed burst size. 2514 * The policer is working with time slices of 50 nano sec. By default every 2515 * slice is granted the proportionate share of the committed rate. If we want to 2516 * allow a slice to exceed that share (while still keeping the rate per sec) we 2517 * can allow burst. The burst size is between the default proportionate share 2518 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 2519 * committed rate will result in exceeding the rate). The burst size must be a 2520 * log of 2 and will be determined by 2^cbs. 2521 * Access: RW 2522 */ 2523 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 2524 2525 /* reg_qpcr_cir 2526 * Policer's committed rate. 2527 * The rate used for sungle rate, the lower rate for double rate. 2528 * For bytes limits, the rate will be this value * the unit from ir_units. 2529 * (Resolution error is up to 1%). 2530 * Access: RW 2531 */ 2532 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 2533 2534 /* reg_qpcr_eir 2535 * Policer's exceed rate. 2536 * The higher rate for double rate, reserved for single rate. 2537 * Lower rate for double rate policer. 2538 * For bytes limits, the rate will be this value * the unit from ir_units. 2539 * (Resolution error is up to 1%). 2540 * Access: RW 2541 */ 2542 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 2543 2544 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 2545 2546 /* reg_qpcr_exceed_action. 2547 * What to do with packets between the 2 limits for double rate. 2548 * Access: RW for unbounded policer. RO for bounded policer. 2549 */ 2550 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 2551 2552 enum mlxsw_reg_qpcr_action { 2553 /* Discard */ 2554 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 2555 /* Forward and set color to red. 2556 * If the packet is intended to cpu port, it will be dropped. 2557 */ 2558 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 2559 }; 2560 2561 /* reg_qpcr_violate_action 2562 * What to do with packets that cross the cir limit (for single rate) or the eir 2563 * limit (for double rate). 2564 * Access: RW for unbounded policer. RO for bounded policer. 2565 */ 2566 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 2567 2568 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 2569 enum mlxsw_reg_qpcr_ir_units ir_units, 2570 bool bytes, u32 cir, u16 cbs) 2571 { 2572 MLXSW_REG_ZERO(qpcr, payload); 2573 mlxsw_reg_qpcr_pid_set(payload, pid); 2574 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 2575 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 2576 mlxsw_reg_qpcr_violate_action_set(payload, 2577 MLXSW_REG_QPCR_ACTION_DISCARD); 2578 mlxsw_reg_qpcr_cir_set(payload, cir); 2579 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 2580 mlxsw_reg_qpcr_bytes_set(payload, bytes); 2581 mlxsw_reg_qpcr_cbs_set(payload, cbs); 2582 } 2583 2584 /* QTCT - QoS Switch Traffic Class Table 2585 * ------------------------------------- 2586 * Configures the mapping between the packet switch priority and the 2587 * traffic class on the transmit port. 2588 */ 2589 #define MLXSW_REG_QTCT_ID 0x400A 2590 #define MLXSW_REG_QTCT_LEN 0x08 2591 2592 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 2593 2594 /* reg_qtct_local_port 2595 * Local port number. 2596 * Access: Index 2597 * 2598 * Note: CPU port is not supported. 2599 */ 2600 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 2601 2602 /* reg_qtct_sub_port 2603 * Virtual port within the physical port. 2604 * Should be set to 0 when virtual ports are not enabled on the port. 2605 * Access: Index 2606 */ 2607 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 2608 2609 /* reg_qtct_switch_prio 2610 * Switch priority. 2611 * Access: Index 2612 */ 2613 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 2614 2615 /* reg_qtct_tclass 2616 * Traffic class. 2617 * Default values: 2618 * switch_prio 0 : tclass 1 2619 * switch_prio 1 : tclass 0 2620 * switch_prio i : tclass i, for i > 1 2621 * Access: RW 2622 */ 2623 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 2624 2625 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 2626 u8 switch_prio, u8 tclass) 2627 { 2628 MLXSW_REG_ZERO(qtct, payload); 2629 mlxsw_reg_qtct_local_port_set(payload, local_port); 2630 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 2631 mlxsw_reg_qtct_tclass_set(payload, tclass); 2632 } 2633 2634 /* QEEC - QoS ETS Element Configuration Register 2635 * --------------------------------------------- 2636 * Configures the ETS elements. 2637 */ 2638 #define MLXSW_REG_QEEC_ID 0x400D 2639 #define MLXSW_REG_QEEC_LEN 0x1C 2640 2641 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 2642 2643 /* reg_qeec_local_port 2644 * Local port number. 2645 * Access: Index 2646 * 2647 * Note: CPU port is supported. 2648 */ 2649 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 2650 2651 enum mlxsw_reg_qeec_hr { 2652 MLXSW_REG_QEEC_HIERARCY_PORT, 2653 MLXSW_REG_QEEC_HIERARCY_GROUP, 2654 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2655 MLXSW_REG_QEEC_HIERARCY_TC, 2656 }; 2657 2658 /* reg_qeec_element_hierarchy 2659 * 0 - Port 2660 * 1 - Group 2661 * 2 - Subgroup 2662 * 3 - Traffic Class 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 2666 2667 /* reg_qeec_element_index 2668 * The index of the element in the hierarchy. 2669 * Access: Index 2670 */ 2671 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 2672 2673 /* reg_qeec_next_element_index 2674 * The index of the next (lower) element in the hierarchy. 2675 * Access: RW 2676 * 2677 * Note: Reserved for element_hierarchy 0. 2678 */ 2679 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 2680 2681 enum { 2682 MLXSW_REG_QEEC_BYTES_MODE, 2683 MLXSW_REG_QEEC_PACKETS_MODE, 2684 }; 2685 2686 /* reg_qeec_pb 2687 * Packets or bytes mode. 2688 * 0 - Bytes mode 2689 * 1 - Packets mode 2690 * Access: RW 2691 * 2692 * Note: Used for max shaper configuration. For Spectrum, packets mode 2693 * is supported only for traffic classes of CPU port. 2694 */ 2695 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 2696 2697 /* reg_qeec_mase 2698 * Max shaper configuration enable. Enables configuration of the max 2699 * shaper on this ETS element. 2700 * 0 - Disable 2701 * 1 - Enable 2702 * Access: RW 2703 */ 2704 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 2705 2706 /* A large max rate will disable the max shaper. */ 2707 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 2708 2709 /* reg_qeec_max_shaper_rate 2710 * Max shaper information rate. 2711 * For CPU port, can only be configured for port hierarchy. 2712 * When in bytes mode, value is specified in units of 1000bps. 2713 * Access: RW 2714 */ 2715 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 2716 2717 /* reg_qeec_de 2718 * DWRR configuration enable. Enables configuration of the dwrr and 2719 * dwrr_weight. 2720 * 0 - Disable 2721 * 1 - Enable 2722 * Access: RW 2723 */ 2724 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 2725 2726 /* reg_qeec_dwrr 2727 * Transmission selection algorithm to use on the link going down from 2728 * the ETS element. 2729 * 0 - Strict priority 2730 * 1 - DWRR 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 2734 2735 /* reg_qeec_dwrr_weight 2736 * DWRR weight on the link going down from the ETS element. The 2737 * percentage of bandwidth guaranteed to an ETS element within 2738 * its hierarchy. The sum of all weights across all ETS elements 2739 * within one hierarchy should be equal to 100. Reserved when 2740 * transmission selection algorithm is strict priority. 2741 * Access: RW 2742 */ 2743 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 2744 2745 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 2746 enum mlxsw_reg_qeec_hr hr, u8 index, 2747 u8 next_index) 2748 { 2749 MLXSW_REG_ZERO(qeec, payload); 2750 mlxsw_reg_qeec_local_port_set(payload, local_port); 2751 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 2752 mlxsw_reg_qeec_element_index_set(payload, index); 2753 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 2754 } 2755 2756 /* PMLP - Ports Module to Local Port Register 2757 * ------------------------------------------ 2758 * Configures the assignment of modules to local ports. 2759 */ 2760 #define MLXSW_REG_PMLP_ID 0x5002 2761 #define MLXSW_REG_PMLP_LEN 0x40 2762 2763 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 2764 2765 /* reg_pmlp_rxtx 2766 * 0 - Tx value is used for both Tx and Rx. 2767 * 1 - Rx value is taken from a separte field. 2768 * Access: RW 2769 */ 2770 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 2771 2772 /* reg_pmlp_local_port 2773 * Local port number. 2774 * Access: Index 2775 */ 2776 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 2777 2778 /* reg_pmlp_width 2779 * 0 - Unmap local port. 2780 * 1 - Lane 0 is used. 2781 * 2 - Lanes 0 and 1 are used. 2782 * 4 - Lanes 0, 1, 2 and 3 are used. 2783 * Access: RW 2784 */ 2785 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 2786 2787 /* reg_pmlp_module 2788 * Module number. 2789 * Access: RW 2790 */ 2791 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 2792 2793 /* reg_pmlp_tx_lane 2794 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 2795 * Access: RW 2796 */ 2797 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 2798 2799 /* reg_pmlp_rx_lane 2800 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 2801 * equal to Tx lane. 2802 * Access: RW 2803 */ 2804 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 2805 2806 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 2807 { 2808 MLXSW_REG_ZERO(pmlp, payload); 2809 mlxsw_reg_pmlp_local_port_set(payload, local_port); 2810 } 2811 2812 /* PMTU - Port MTU Register 2813 * ------------------------ 2814 * Configures and reports the port MTU. 2815 */ 2816 #define MLXSW_REG_PMTU_ID 0x5003 2817 #define MLXSW_REG_PMTU_LEN 0x10 2818 2819 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 2820 2821 /* reg_pmtu_local_port 2822 * Local port number. 2823 * Access: Index 2824 */ 2825 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 2826 2827 /* reg_pmtu_max_mtu 2828 * Maximum MTU. 2829 * When port type (e.g. Ethernet) is configured, the relevant MTU is 2830 * reported, otherwise the minimum between the max_mtu of the different 2831 * types is reported. 2832 * Access: RO 2833 */ 2834 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 2835 2836 /* reg_pmtu_admin_mtu 2837 * MTU value to set port to. Must be smaller or equal to max_mtu. 2838 * Note: If port type is Infiniband, then port must be disabled, when its 2839 * MTU is set. 2840 * Access: RW 2841 */ 2842 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 2843 2844 /* reg_pmtu_oper_mtu 2845 * The actual MTU configured on the port. Packets exceeding this size 2846 * will be dropped. 2847 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 2848 * oper_mtu might be smaller than admin_mtu. 2849 * Access: RO 2850 */ 2851 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 2852 2853 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 2854 u16 new_mtu) 2855 { 2856 MLXSW_REG_ZERO(pmtu, payload); 2857 mlxsw_reg_pmtu_local_port_set(payload, local_port); 2858 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 2859 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 2860 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 2861 } 2862 2863 /* PTYS - Port Type and Speed Register 2864 * ----------------------------------- 2865 * Configures and reports the port speed type. 2866 * 2867 * Note: When set while the link is up, the changes will not take effect 2868 * until the port transitions from down to up state. 2869 */ 2870 #define MLXSW_REG_PTYS_ID 0x5004 2871 #define MLXSW_REG_PTYS_LEN 0x40 2872 2873 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 2874 2875 /* an_disable_admin 2876 * Auto negotiation disable administrative configuration 2877 * 0 - Device doesn't support AN disable. 2878 * 1 - Device supports AN disable. 2879 * Access: RW 2880 */ 2881 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 2882 2883 /* reg_ptys_local_port 2884 * Local port number. 2885 * Access: Index 2886 */ 2887 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 2888 2889 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 2890 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 2891 2892 /* reg_ptys_proto_mask 2893 * Protocol mask. Indicates which protocol is used. 2894 * 0 - Infiniband. 2895 * 1 - Fibre Channel. 2896 * 2 - Ethernet. 2897 * Access: Index 2898 */ 2899 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 2900 2901 enum { 2902 MLXSW_REG_PTYS_AN_STATUS_NA, 2903 MLXSW_REG_PTYS_AN_STATUS_OK, 2904 MLXSW_REG_PTYS_AN_STATUS_FAIL, 2905 }; 2906 2907 /* reg_ptys_an_status 2908 * Autonegotiation status. 2909 * Access: RO 2910 */ 2911 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 2912 2913 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 2914 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 2915 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 2916 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 2917 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 2918 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 2919 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 2920 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 2921 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 2922 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 2923 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 2924 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 2925 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 2926 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 2927 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 2928 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 2929 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 2930 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 2931 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 2932 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 2933 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 2934 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 2935 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 2936 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 2937 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 2938 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 2939 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 2940 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 2941 2942 /* reg_ptys_eth_proto_cap 2943 * Ethernet port supported speeds and protocols. 2944 * Access: RO 2945 */ 2946 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 2947 2948 /* reg_ptys_ib_link_width_cap 2949 * IB port supported widths. 2950 * Access: RO 2951 */ 2952 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 2953 2954 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 2955 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 2956 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 2957 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 2958 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 2959 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 2960 2961 /* reg_ptys_ib_proto_cap 2962 * IB port supported speeds and protocols. 2963 * Access: RO 2964 */ 2965 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 2966 2967 /* reg_ptys_eth_proto_admin 2968 * Speed and protocol to set port to. 2969 * Access: RW 2970 */ 2971 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 2972 2973 /* reg_ptys_ib_link_width_admin 2974 * IB width to set port to. 2975 * Access: RW 2976 */ 2977 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 2978 2979 /* reg_ptys_ib_proto_admin 2980 * IB speeds and protocols to set port to. 2981 * Access: RW 2982 */ 2983 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 2984 2985 /* reg_ptys_eth_proto_oper 2986 * The current speed and protocol configured for the port. 2987 * Access: RO 2988 */ 2989 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 2990 2991 /* reg_ptys_ib_link_width_oper 2992 * The current IB width to set port to. 2993 * Access: RO 2994 */ 2995 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 2996 2997 /* reg_ptys_ib_proto_oper 2998 * The current IB speed and protocol. 2999 * Access: RO 3000 */ 3001 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 3002 3003 /* reg_ptys_eth_proto_lp_advertise 3004 * The protocols that were advertised by the link partner during 3005 * autonegotiation. 3006 * Access: RO 3007 */ 3008 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3009 3010 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3011 u32 proto_admin, bool autoneg) 3012 { 3013 MLXSW_REG_ZERO(ptys, payload); 3014 mlxsw_reg_ptys_local_port_set(payload, local_port); 3015 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 3016 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 3017 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 3018 } 3019 3020 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 3021 u32 *p_eth_proto_cap, 3022 u32 *p_eth_proto_adm, 3023 u32 *p_eth_proto_oper) 3024 { 3025 if (p_eth_proto_cap) 3026 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 3027 if (p_eth_proto_adm) 3028 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 3029 if (p_eth_proto_oper) 3030 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 3031 } 3032 3033 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 3034 u16 proto_admin, u16 link_width) 3035 { 3036 MLXSW_REG_ZERO(ptys, payload); 3037 mlxsw_reg_ptys_local_port_set(payload, local_port); 3038 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 3039 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 3040 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 3041 } 3042 3043 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 3044 u16 *p_ib_link_width_cap, 3045 u16 *p_ib_proto_oper, 3046 u16 *p_ib_link_width_oper) 3047 { 3048 if (p_ib_proto_cap) 3049 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 3050 if (p_ib_link_width_cap) 3051 *p_ib_link_width_cap = 3052 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 3053 if (p_ib_proto_oper) 3054 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 3055 if (p_ib_link_width_oper) 3056 *p_ib_link_width_oper = 3057 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 3058 } 3059 3060 /* PPAD - Port Physical Address Register 3061 * ------------------------------------- 3062 * The PPAD register configures the per port physical MAC address. 3063 */ 3064 #define MLXSW_REG_PPAD_ID 0x5005 3065 #define MLXSW_REG_PPAD_LEN 0x10 3066 3067 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 3068 3069 /* reg_ppad_single_base_mac 3070 * 0: base_mac, local port should be 0 and mac[7:0] is 3071 * reserved. HW will set incremental 3072 * 1: single_mac - mac of the local_port 3073 * Access: RW 3074 */ 3075 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 3076 3077 /* reg_ppad_local_port 3078 * port number, if single_base_mac = 0 then local_port is reserved 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 3082 3083 /* reg_ppad_mac 3084 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 3085 * If single_base_mac = 1 - the per port MAC address 3086 * Access: RW 3087 */ 3088 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 3089 3090 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 3091 u8 local_port) 3092 { 3093 MLXSW_REG_ZERO(ppad, payload); 3094 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 3095 mlxsw_reg_ppad_local_port_set(payload, local_port); 3096 } 3097 3098 /* PAOS - Ports Administrative and Operational Status Register 3099 * ----------------------------------------------------------- 3100 * Configures and retrieves per port administrative and operational status. 3101 */ 3102 #define MLXSW_REG_PAOS_ID 0x5006 3103 #define MLXSW_REG_PAOS_LEN 0x10 3104 3105 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 3106 3107 /* reg_paos_swid 3108 * Switch partition ID with which to associate the port. 3109 * Note: while external ports uses unique local port numbers (and thus swid is 3110 * redundant), router ports use the same local port number where swid is the 3111 * only indication for the relevant port. 3112 * Access: Index 3113 */ 3114 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 3115 3116 /* reg_paos_local_port 3117 * Local port number. 3118 * Access: Index 3119 */ 3120 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 3121 3122 /* reg_paos_admin_status 3123 * Port administrative state (the desired state of the port): 3124 * 1 - Up. 3125 * 2 - Down. 3126 * 3 - Up once. This means that in case of link failure, the port won't go 3127 * into polling mode, but will wait to be re-enabled by software. 3128 * 4 - Disabled by system. Can only be set by hardware. 3129 * Access: RW 3130 */ 3131 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 3132 3133 /* reg_paos_oper_status 3134 * Port operational state (the current state): 3135 * 1 - Up. 3136 * 2 - Down. 3137 * 3 - Down by port failure. This means that the device will not let the 3138 * port up again until explicitly specified by software. 3139 * Access: RO 3140 */ 3141 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 3142 3143 /* reg_paos_ase 3144 * Admin state update enabled. 3145 * Access: WO 3146 */ 3147 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 3148 3149 /* reg_paos_ee 3150 * Event update enable. If this bit is set, event generation will be 3151 * updated based on the e field. 3152 * Access: WO 3153 */ 3154 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 3155 3156 /* reg_paos_e 3157 * Event generation on operational state change: 3158 * 0 - Do not generate event. 3159 * 1 - Generate Event. 3160 * 2 - Generate Single Event. 3161 * Access: RW 3162 */ 3163 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 3164 3165 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 3166 enum mlxsw_port_admin_status status) 3167 { 3168 MLXSW_REG_ZERO(paos, payload); 3169 mlxsw_reg_paos_swid_set(payload, 0); 3170 mlxsw_reg_paos_local_port_set(payload, local_port); 3171 mlxsw_reg_paos_admin_status_set(payload, status); 3172 mlxsw_reg_paos_oper_status_set(payload, 0); 3173 mlxsw_reg_paos_ase_set(payload, 1); 3174 mlxsw_reg_paos_ee_set(payload, 1); 3175 mlxsw_reg_paos_e_set(payload, 1); 3176 } 3177 3178 /* PFCC - Ports Flow Control Configuration Register 3179 * ------------------------------------------------ 3180 * Configures and retrieves the per port flow control configuration. 3181 */ 3182 #define MLXSW_REG_PFCC_ID 0x5007 3183 #define MLXSW_REG_PFCC_LEN 0x20 3184 3185 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 3186 3187 /* reg_pfcc_local_port 3188 * Local port number. 3189 * Access: Index 3190 */ 3191 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 3192 3193 /* reg_pfcc_pnat 3194 * Port number access type. Determines the way local_port is interpreted: 3195 * 0 - Local port number. 3196 * 1 - IB / label port number. 3197 * Access: Index 3198 */ 3199 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 3200 3201 /* reg_pfcc_shl_cap 3202 * Send to higher layers capabilities: 3203 * 0 - No capability of sending Pause and PFC frames to higher layers. 3204 * 1 - Device has capability of sending Pause and PFC frames to higher 3205 * layers. 3206 * Access: RO 3207 */ 3208 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 3209 3210 /* reg_pfcc_shl_opr 3211 * Send to higher layers operation: 3212 * 0 - Pause and PFC frames are handled by the port (default). 3213 * 1 - Pause and PFC frames are handled by the port and also sent to 3214 * higher layers. Only valid if shl_cap = 1. 3215 * Access: RW 3216 */ 3217 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 3218 3219 /* reg_pfcc_ppan 3220 * Pause policy auto negotiation. 3221 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 3222 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 3223 * based on the auto-negotiation resolution. 3224 * Access: RW 3225 * 3226 * Note: The auto-negotiation advertisement is set according to pptx and 3227 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 3228 */ 3229 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 3230 3231 /* reg_pfcc_prio_mask_tx 3232 * Bit per priority indicating if Tx flow control policy should be 3233 * updated based on bit pfctx. 3234 * Access: WO 3235 */ 3236 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 3237 3238 /* reg_pfcc_prio_mask_rx 3239 * Bit per priority indicating if Rx flow control policy should be 3240 * updated based on bit pfcrx. 3241 * Access: WO 3242 */ 3243 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 3244 3245 /* reg_pfcc_pptx 3246 * Admin Pause policy on Tx. 3247 * 0 - Never generate Pause frames (default). 3248 * 1 - Generate Pause frames according to Rx buffer threshold. 3249 * Access: RW 3250 */ 3251 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 3252 3253 /* reg_pfcc_aptx 3254 * Active (operational) Pause policy on Tx. 3255 * 0 - Never generate Pause frames. 3256 * 1 - Generate Pause frames according to Rx buffer threshold. 3257 * Access: RO 3258 */ 3259 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 3260 3261 /* reg_pfcc_pfctx 3262 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 3263 * 0 - Never generate priority Pause frames on the specified priority 3264 * (default). 3265 * 1 - Generate priority Pause frames according to Rx buffer threshold on 3266 * the specified priority. 3267 * Access: RW 3268 * 3269 * Note: pfctx and pptx must be mutually exclusive. 3270 */ 3271 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 3272 3273 /* reg_pfcc_pprx 3274 * Admin Pause policy on Rx. 3275 * 0 - Ignore received Pause frames (default). 3276 * 1 - Respect received Pause frames. 3277 * Access: RW 3278 */ 3279 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 3280 3281 /* reg_pfcc_aprx 3282 * Active (operational) Pause policy on Rx. 3283 * 0 - Ignore received Pause frames. 3284 * 1 - Respect received Pause frames. 3285 * Access: RO 3286 */ 3287 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 3288 3289 /* reg_pfcc_pfcrx 3290 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 3291 * 0 - Ignore incoming priority Pause frames on the specified priority 3292 * (default). 3293 * 1 - Respect incoming priority Pause frames on the specified priority. 3294 * Access: RW 3295 */ 3296 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 3297 3298 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 3299 3300 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 3301 { 3302 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3303 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3304 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 3305 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 3306 } 3307 3308 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 3309 { 3310 MLXSW_REG_ZERO(pfcc, payload); 3311 mlxsw_reg_pfcc_local_port_set(payload, local_port); 3312 } 3313 3314 /* PPCNT - Ports Performance Counters Register 3315 * ------------------------------------------- 3316 * The PPCNT register retrieves per port performance counters. 3317 */ 3318 #define MLXSW_REG_PPCNT_ID 0x5008 3319 #define MLXSW_REG_PPCNT_LEN 0x100 3320 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 3321 3322 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 3323 3324 /* reg_ppcnt_swid 3325 * For HCA: must be always 0. 3326 * Switch partition ID to associate port with. 3327 * Switch partitions are numbered from 0 to 7 inclusively. 3328 * Switch partition 254 indicates stacking ports. 3329 * Switch partition 255 indicates all switch partitions. 3330 * Only valid on Set() operation with local_port=255. 3331 * Access: Index 3332 */ 3333 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 3334 3335 /* reg_ppcnt_local_port 3336 * Local port number. 3337 * 255 indicates all ports on the device, and is only allowed 3338 * for Set() operation. 3339 * Access: Index 3340 */ 3341 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 3342 3343 /* reg_ppcnt_pnat 3344 * Port number access type: 3345 * 0 - Local port number 3346 * 1 - IB port number 3347 * Access: Index 3348 */ 3349 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 3350 3351 enum mlxsw_reg_ppcnt_grp { 3352 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 3353 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 3354 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 3355 MLXSW_REG_PPCNT_TC_CNT = 0x11, 3356 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 3357 }; 3358 3359 /* reg_ppcnt_grp 3360 * Performance counter group. 3361 * Group 63 indicates all groups. Only valid on Set() operation with 3362 * clr bit set. 3363 * 0x0: IEEE 802.3 Counters 3364 * 0x1: RFC 2863 Counters 3365 * 0x2: RFC 2819 Counters 3366 * 0x3: RFC 3635 Counters 3367 * 0x5: Ethernet Extended Counters 3368 * 0x8: Link Level Retransmission Counters 3369 * 0x10: Per Priority Counters 3370 * 0x11: Per Traffic Class Counters 3371 * 0x12: Physical Layer Counters 3372 * 0x13: Per Traffic Class Congestion Counters 3373 * Access: Index 3374 */ 3375 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 3376 3377 /* reg_ppcnt_clr 3378 * Clear counters. Setting the clr bit will reset the counter value 3379 * for all counters in the counter group. This bit can be set 3380 * for both Set() and Get() operation. 3381 * Access: OP 3382 */ 3383 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 3384 3385 /* reg_ppcnt_prio_tc 3386 * Priority for counter set that support per priority, valid values: 0-7. 3387 * Traffic class for counter set that support per traffic class, 3388 * valid values: 0- cap_max_tclass-1 . 3389 * For HCA: cap_max_tclass is always 8. 3390 * Otherwise must be 0. 3391 * Access: Index 3392 */ 3393 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 3394 3395 /* Ethernet IEEE 802.3 Counter Group */ 3396 3397 /* reg_ppcnt_a_frames_transmitted_ok 3398 * Access: RO 3399 */ 3400 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 3401 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3402 3403 /* reg_ppcnt_a_frames_received_ok 3404 * Access: RO 3405 */ 3406 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 3407 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3408 3409 /* reg_ppcnt_a_frame_check_sequence_errors 3410 * Access: RO 3411 */ 3412 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 3413 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 3414 3415 /* reg_ppcnt_a_alignment_errors 3416 * Access: RO 3417 */ 3418 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 3419 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 3420 3421 /* reg_ppcnt_a_octets_transmitted_ok 3422 * Access: RO 3423 */ 3424 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 3425 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3426 3427 /* reg_ppcnt_a_octets_received_ok 3428 * Access: RO 3429 */ 3430 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 3431 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3432 3433 /* reg_ppcnt_a_multicast_frames_xmitted_ok 3434 * Access: RO 3435 */ 3436 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 3437 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 3438 3439 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 3440 * Access: RO 3441 */ 3442 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 3443 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 3444 3445 /* reg_ppcnt_a_multicast_frames_received_ok 3446 * Access: RO 3447 */ 3448 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 3449 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 3450 3451 /* reg_ppcnt_a_broadcast_frames_received_ok 3452 * Access: RO 3453 */ 3454 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 3455 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3456 3457 /* reg_ppcnt_a_in_range_length_errors 3458 * Access: RO 3459 */ 3460 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 3461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3462 3463 /* reg_ppcnt_a_out_of_range_length_field 3464 * Access: RO 3465 */ 3466 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 3467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3468 3469 /* reg_ppcnt_a_frame_too_long_errors 3470 * Access: RO 3471 */ 3472 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 3473 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3474 3475 /* reg_ppcnt_a_symbol_error_during_carrier 3476 * Access: RO 3477 */ 3478 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 3479 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3480 3481 /* reg_ppcnt_a_mac_control_frames_transmitted 3482 * Access: RO 3483 */ 3484 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 3485 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3486 3487 /* reg_ppcnt_a_mac_control_frames_received 3488 * Access: RO 3489 */ 3490 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 3491 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 3492 3493 /* reg_ppcnt_a_unsupported_opcodes_received 3494 * Access: RO 3495 */ 3496 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 3497 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 3498 3499 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 3500 * Access: RO 3501 */ 3502 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 3503 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 3504 3505 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 3506 * Access: RO 3507 */ 3508 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 3509 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 3510 3511 /* Ethernet Extended Counter Group Counters */ 3512 3513 /* reg_ppcnt_ecn_marked 3514 * Access: RO 3515 */ 3516 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 3517 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3518 3519 /* Ethernet Per Priority Group Counters */ 3520 3521 /* reg_ppcnt_rx_octets 3522 * Access: RO 3523 */ 3524 MLXSW_ITEM64(reg, ppcnt, rx_octets, 3525 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3526 3527 /* reg_ppcnt_rx_frames 3528 * Access: RO 3529 */ 3530 MLXSW_ITEM64(reg, ppcnt, rx_frames, 3531 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3532 3533 /* reg_ppcnt_tx_octets 3534 * Access: RO 3535 */ 3536 MLXSW_ITEM64(reg, ppcnt, tx_octets, 3537 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3538 3539 /* reg_ppcnt_tx_frames 3540 * Access: RO 3541 */ 3542 MLXSW_ITEM64(reg, ppcnt, tx_frames, 3543 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3544 3545 /* reg_ppcnt_rx_pause 3546 * Access: RO 3547 */ 3548 MLXSW_ITEM64(reg, ppcnt, rx_pause, 3549 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3550 3551 /* reg_ppcnt_rx_pause_duration 3552 * Access: RO 3553 */ 3554 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 3555 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3556 3557 /* reg_ppcnt_tx_pause 3558 * Access: RO 3559 */ 3560 MLXSW_ITEM64(reg, ppcnt, tx_pause, 3561 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3562 3563 /* reg_ppcnt_tx_pause_duration 3564 * Access: RO 3565 */ 3566 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 3567 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3568 3569 /* reg_ppcnt_rx_pause_transition 3570 * Access: RO 3571 */ 3572 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 3573 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3574 3575 /* Ethernet Per Traffic Group Counters */ 3576 3577 /* reg_ppcnt_tc_transmit_queue 3578 * Contains the transmit queue depth in cells of traffic class 3579 * selected by prio_tc and the port selected by local_port. 3580 * The field cannot be cleared. 3581 * Access: RO 3582 */ 3583 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 3584 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3585 3586 /* reg_ppcnt_tc_no_buffer_discard_uc 3587 * The number of unicast packets dropped due to lack of shared 3588 * buffer resources. 3589 * Access: RO 3590 */ 3591 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 3592 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3593 3594 /* Ethernet Per Traffic Class Congestion Group Counters */ 3595 3596 /* reg_ppcnt_wred_discard 3597 * Access: RO 3598 */ 3599 MLXSW_ITEM64(reg, ppcnt, wred_discard, 3600 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3601 3602 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 3603 enum mlxsw_reg_ppcnt_grp grp, 3604 u8 prio_tc) 3605 { 3606 MLXSW_REG_ZERO(ppcnt, payload); 3607 mlxsw_reg_ppcnt_swid_set(payload, 0); 3608 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 3609 mlxsw_reg_ppcnt_pnat_set(payload, 0); 3610 mlxsw_reg_ppcnt_grp_set(payload, grp); 3611 mlxsw_reg_ppcnt_clr_set(payload, 0); 3612 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 3613 } 3614 3615 /* PLIB - Port Local to InfiniBand Port 3616 * ------------------------------------ 3617 * The PLIB register performs mapping from Local Port into InfiniBand Port. 3618 */ 3619 #define MLXSW_REG_PLIB_ID 0x500A 3620 #define MLXSW_REG_PLIB_LEN 0x10 3621 3622 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 3623 3624 /* reg_plib_local_port 3625 * Local port number. 3626 * Access: Index 3627 */ 3628 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 3629 3630 /* reg_plib_ib_port 3631 * InfiniBand port remapping for local_port. 3632 * Access: RW 3633 */ 3634 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 3635 3636 /* PPTB - Port Prio To Buffer Register 3637 * ----------------------------------- 3638 * Configures the switch priority to buffer table. 3639 */ 3640 #define MLXSW_REG_PPTB_ID 0x500B 3641 #define MLXSW_REG_PPTB_LEN 0x10 3642 3643 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 3644 3645 enum { 3646 MLXSW_REG_PPTB_MM_UM, 3647 MLXSW_REG_PPTB_MM_UNICAST, 3648 MLXSW_REG_PPTB_MM_MULTICAST, 3649 }; 3650 3651 /* reg_pptb_mm 3652 * Mapping mode. 3653 * 0 - Map both unicast and multicast packets to the same buffer. 3654 * 1 - Map only unicast packets. 3655 * 2 - Map only multicast packets. 3656 * Access: Index 3657 * 3658 * Note: SwitchX-2 only supports the first option. 3659 */ 3660 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 3661 3662 /* reg_pptb_local_port 3663 * Local port number. 3664 * Access: Index 3665 */ 3666 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 3667 3668 /* reg_pptb_um 3669 * Enables the update of the untagged_buf field. 3670 * Access: RW 3671 */ 3672 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 3673 3674 /* reg_pptb_pm 3675 * Enables the update of the prio_to_buff field. 3676 * Bit <i> is a flag for updating the mapping for switch priority <i>. 3677 * Access: RW 3678 */ 3679 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 3680 3681 /* reg_pptb_prio_to_buff 3682 * Mapping of switch priority <i> to one of the allocated receive port 3683 * buffers. 3684 * Access: RW 3685 */ 3686 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 3687 3688 /* reg_pptb_pm_msb 3689 * Enables the update of the prio_to_buff field. 3690 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 3691 * Access: RW 3692 */ 3693 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 3694 3695 /* reg_pptb_untagged_buff 3696 * Mapping of untagged frames to one of the allocated receive port buffers. 3697 * Access: RW 3698 * 3699 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 3700 * Spectrum, as it maps untagged packets based on the default switch priority. 3701 */ 3702 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 3703 3704 /* reg_pptb_prio_to_buff_msb 3705 * Mapping of switch priority <i+8> to one of the allocated receive port 3706 * buffers. 3707 * Access: RW 3708 */ 3709 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 3710 3711 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 3712 3713 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 3714 { 3715 MLXSW_REG_ZERO(pptb, payload); 3716 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 3717 mlxsw_reg_pptb_local_port_set(payload, local_port); 3718 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3719 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3720 } 3721 3722 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 3723 u8 buff) 3724 { 3725 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 3726 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 3727 } 3728 3729 /* PBMC - Port Buffer Management Control Register 3730 * ---------------------------------------------- 3731 * The PBMC register configures and retrieves the port packet buffer 3732 * allocation for different Prios, and the Pause threshold management. 3733 */ 3734 #define MLXSW_REG_PBMC_ID 0x500C 3735 #define MLXSW_REG_PBMC_LEN 0x6C 3736 3737 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 3738 3739 /* reg_pbmc_local_port 3740 * Local port number. 3741 * Access: Index 3742 */ 3743 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 3744 3745 /* reg_pbmc_xoff_timer_value 3746 * When device generates a pause frame, it uses this value as the pause 3747 * timer (time for the peer port to pause in quota-512 bit time). 3748 * Access: RW 3749 */ 3750 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 3751 3752 /* reg_pbmc_xoff_refresh 3753 * The time before a new pause frame should be sent to refresh the pause RW 3754 * state. Using the same units as xoff_timer_value above (in quota-512 bit 3755 * time). 3756 * Access: RW 3757 */ 3758 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 3759 3760 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 3761 3762 /* reg_pbmc_buf_lossy 3763 * The field indicates if the buffer is lossy. 3764 * 0 - Lossless 3765 * 1 - Lossy 3766 * Access: RW 3767 */ 3768 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 3769 3770 /* reg_pbmc_buf_epsb 3771 * Eligible for Port Shared buffer. 3772 * If epsb is set, packets assigned to buffer are allowed to insert the port 3773 * shared buffer. 3774 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 3775 * Access: RW 3776 */ 3777 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 3778 3779 /* reg_pbmc_buf_size 3780 * The part of the packet buffer array is allocated for the specific buffer. 3781 * Units are represented in cells. 3782 * Access: RW 3783 */ 3784 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 3785 3786 /* reg_pbmc_buf_xoff_threshold 3787 * Once the amount of data in the buffer goes above this value, device 3788 * starts sending PFC frames for all priorities associated with the 3789 * buffer. Units are represented in cells. Reserved in case of lossy 3790 * buffer. 3791 * Access: RW 3792 * 3793 * Note: In Spectrum, reserved for buffer[9]. 3794 */ 3795 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 3796 0x08, 0x04, false); 3797 3798 /* reg_pbmc_buf_xon_threshold 3799 * When the amount of data in the buffer goes below this value, device 3800 * stops sending PFC frames for the priorities associated with the 3801 * buffer. Units are represented in cells. Reserved in case of lossy 3802 * buffer. 3803 * Access: RW 3804 * 3805 * Note: In Spectrum, reserved for buffer[9]. 3806 */ 3807 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 3808 0x08, 0x04, false); 3809 3810 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 3811 u16 xoff_timer_value, u16 xoff_refresh) 3812 { 3813 MLXSW_REG_ZERO(pbmc, payload); 3814 mlxsw_reg_pbmc_local_port_set(payload, local_port); 3815 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 3816 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 3817 } 3818 3819 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 3820 int buf_index, 3821 u16 size) 3822 { 3823 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 3824 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3825 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3826 } 3827 3828 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 3829 int buf_index, u16 size, 3830 u16 threshold) 3831 { 3832 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 3833 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3834 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3835 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 3836 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 3837 } 3838 3839 /* PSPA - Port Switch Partition Allocation 3840 * --------------------------------------- 3841 * Controls the association of a port with a switch partition and enables 3842 * configuring ports as stacking ports. 3843 */ 3844 #define MLXSW_REG_PSPA_ID 0x500D 3845 #define MLXSW_REG_PSPA_LEN 0x8 3846 3847 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 3848 3849 /* reg_pspa_swid 3850 * Switch partition ID. 3851 * Access: RW 3852 */ 3853 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 3854 3855 /* reg_pspa_local_port 3856 * Local port number. 3857 * Access: Index 3858 */ 3859 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 3860 3861 /* reg_pspa_sub_port 3862 * Virtual port within the local port. Set to 0 when virtual ports are 3863 * disabled on the local port. 3864 * Access: Index 3865 */ 3866 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 3867 3868 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 3869 { 3870 MLXSW_REG_ZERO(pspa, payload); 3871 mlxsw_reg_pspa_swid_set(payload, swid); 3872 mlxsw_reg_pspa_local_port_set(payload, local_port); 3873 mlxsw_reg_pspa_sub_port_set(payload, 0); 3874 } 3875 3876 /* HTGT - Host Trap Group Table 3877 * ---------------------------- 3878 * Configures the properties for forwarding to CPU. 3879 */ 3880 #define MLXSW_REG_HTGT_ID 0x7002 3881 #define MLXSW_REG_HTGT_LEN 0x20 3882 3883 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 3884 3885 /* reg_htgt_swid 3886 * Switch partition ID. 3887 * Access: Index 3888 */ 3889 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 3890 3891 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 3892 3893 /* reg_htgt_type 3894 * CPU path type. 3895 * Access: RW 3896 */ 3897 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 3898 3899 enum mlxsw_reg_htgt_trap_group { 3900 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3901 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 3902 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 3903 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 3904 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 3905 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 3906 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 3907 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 3908 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 3909 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 3910 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 3911 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 3912 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 3913 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 3914 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 3915 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 3916 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 3917 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 3918 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 3919 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 3920 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 3921 }; 3922 3923 /* reg_htgt_trap_group 3924 * Trap group number. User defined number specifying which trap groups 3925 * should be forwarded to the CPU. The mapping between trap IDs and trap 3926 * groups is configured using HPKT register. 3927 * Access: Index 3928 */ 3929 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 3930 3931 enum { 3932 MLXSW_REG_HTGT_POLICER_DISABLE, 3933 MLXSW_REG_HTGT_POLICER_ENABLE, 3934 }; 3935 3936 /* reg_htgt_pide 3937 * Enable policer ID specified using 'pid' field. 3938 * Access: RW 3939 */ 3940 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 3941 3942 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 3943 3944 /* reg_htgt_pid 3945 * Policer ID for the trap group. 3946 * Access: RW 3947 */ 3948 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 3949 3950 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 3951 3952 /* reg_htgt_mirror_action 3953 * Mirror action to use. 3954 * 0 - Trap to CPU. 3955 * 1 - Trap to CPU and mirror to a mirroring agent. 3956 * 2 - Mirror to a mirroring agent and do not trap to CPU. 3957 * Access: RW 3958 * 3959 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 3960 */ 3961 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 3962 3963 /* reg_htgt_mirroring_agent 3964 * Mirroring agent. 3965 * Access: RW 3966 */ 3967 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 3968 3969 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 3970 3971 /* reg_htgt_priority 3972 * Trap group priority. 3973 * In case a packet matches multiple classification rules, the packet will 3974 * only be trapped once, based on the trap ID associated with the group (via 3975 * register HPKT) with the highest priority. 3976 * Supported values are 0-7, with 7 represnting the highest priority. 3977 * Access: RW 3978 * 3979 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 3980 * by the 'trap_group' field. 3981 */ 3982 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 3983 3984 #define MLXSW_REG_HTGT_DEFAULT_TC 7 3985 3986 /* reg_htgt_local_path_cpu_tclass 3987 * CPU ingress traffic class for the trap group. 3988 * Access: RW 3989 */ 3990 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 3991 3992 enum mlxsw_reg_htgt_local_path_rdq { 3993 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 3994 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 3995 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 3996 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 3997 }; 3998 /* reg_htgt_local_path_rdq 3999 * Receive descriptor queue (RDQ) to use for the trap group. 4000 * Access: RW 4001 */ 4002 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 4003 4004 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 4005 u8 priority, u8 tc) 4006 { 4007 MLXSW_REG_ZERO(htgt, payload); 4008 4009 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 4010 mlxsw_reg_htgt_pide_set(payload, 4011 MLXSW_REG_HTGT_POLICER_DISABLE); 4012 } else { 4013 mlxsw_reg_htgt_pide_set(payload, 4014 MLXSW_REG_HTGT_POLICER_ENABLE); 4015 mlxsw_reg_htgt_pid_set(payload, policer_id); 4016 } 4017 4018 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 4019 mlxsw_reg_htgt_trap_group_set(payload, group); 4020 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 4021 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 4022 mlxsw_reg_htgt_priority_set(payload, priority); 4023 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 4024 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 4025 } 4026 4027 /* HPKT - Host Packet Trap 4028 * ----------------------- 4029 * Configures trap IDs inside trap groups. 4030 */ 4031 #define MLXSW_REG_HPKT_ID 0x7003 4032 #define MLXSW_REG_HPKT_LEN 0x10 4033 4034 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 4035 4036 enum { 4037 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 4038 MLXSW_REG_HPKT_ACK_REQUIRED, 4039 }; 4040 4041 /* reg_hpkt_ack 4042 * Require acknowledgements from the host for events. 4043 * If set, then the device will wait for the event it sent to be acknowledged 4044 * by the host. This option is only relevant for event trap IDs. 4045 * Access: RW 4046 * 4047 * Note: Currently not supported by firmware. 4048 */ 4049 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 4050 4051 enum mlxsw_reg_hpkt_action { 4052 MLXSW_REG_HPKT_ACTION_FORWARD, 4053 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 4054 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 4055 MLXSW_REG_HPKT_ACTION_DISCARD, 4056 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 4057 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 4058 }; 4059 4060 /* reg_hpkt_action 4061 * Action to perform on packet when trapped. 4062 * 0 - No action. Forward to CPU based on switching rules. 4063 * 1 - Trap to CPU (CPU receives sole copy). 4064 * 2 - Mirror to CPU (CPU receives a replica of the packet). 4065 * 3 - Discard. 4066 * 4 - Soft discard (allow other traps to act on the packet). 4067 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 4068 * Access: RW 4069 * 4070 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 4071 * addressed to the CPU. 4072 */ 4073 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 4074 4075 /* reg_hpkt_trap_group 4076 * Trap group to associate the trap with. 4077 * Access: RW 4078 */ 4079 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 4080 4081 /* reg_hpkt_trap_id 4082 * Trap ID. 4083 * Access: Index 4084 * 4085 * Note: A trap ID can only be associated with a single trap group. The device 4086 * will associate the trap ID with the last trap group configured. 4087 */ 4088 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 4089 4090 enum { 4091 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 4092 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 4093 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 4094 }; 4095 4096 /* reg_hpkt_ctrl 4097 * Configure dedicated buffer resources for control packets. 4098 * Ignored by SwitchX-2. 4099 * 0 - Keep factory defaults. 4100 * 1 - Do not use control buffer for this trap ID. 4101 * 2 - Use control buffer for this trap ID. 4102 * Access: RW 4103 */ 4104 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 4105 4106 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 4107 enum mlxsw_reg_htgt_trap_group trap_group, 4108 bool is_ctrl) 4109 { 4110 MLXSW_REG_ZERO(hpkt, payload); 4111 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 4112 mlxsw_reg_hpkt_action_set(payload, action); 4113 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 4114 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 4115 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 4116 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 4117 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 4118 } 4119 4120 /* RGCR - Router General Configuration Register 4121 * -------------------------------------------- 4122 * The register is used for setting up the router configuration. 4123 */ 4124 #define MLXSW_REG_RGCR_ID 0x8001 4125 #define MLXSW_REG_RGCR_LEN 0x28 4126 4127 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 4128 4129 /* reg_rgcr_ipv4_en 4130 * IPv4 router enable. 4131 * Access: RW 4132 */ 4133 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 4134 4135 /* reg_rgcr_ipv6_en 4136 * IPv6 router enable. 4137 * Access: RW 4138 */ 4139 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 4140 4141 /* reg_rgcr_max_router_interfaces 4142 * Defines the maximum number of active router interfaces for all virtual 4143 * routers. 4144 * Access: RW 4145 */ 4146 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 4147 4148 /* reg_rgcr_usp 4149 * Update switch priority and packet color. 4150 * 0 - Preserve the value of Switch Priority and packet color. 4151 * 1 - Recalculate the value of Switch Priority and packet color. 4152 * Access: RW 4153 * 4154 * Note: Not supported by SwitchX and SwitchX-2. 4155 */ 4156 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 4157 4158 /* reg_rgcr_pcp_rw 4159 * Indicates how to handle the pcp_rewrite_en value: 4160 * 0 - Preserve the value of pcp_rewrite_en. 4161 * 2 - Disable PCP rewrite. 4162 * 3 - Enable PCP rewrite. 4163 * Access: RW 4164 * 4165 * Note: Not supported by SwitchX and SwitchX-2. 4166 */ 4167 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 4168 4169 /* reg_rgcr_activity_dis 4170 * Activity disable: 4171 * 0 - Activity will be set when an entry is hit (default). 4172 * 1 - Activity will not be set when an entry is hit. 4173 * 4174 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 4175 * (RALUE). 4176 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 4177 * Entry (RAUHT). 4178 * Bits 2:7 are reserved. 4179 * Access: RW 4180 * 4181 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 4182 */ 4183 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 4184 4185 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 4186 bool ipv6_en) 4187 { 4188 MLXSW_REG_ZERO(rgcr, payload); 4189 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 4190 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 4191 } 4192 4193 /* RITR - Router Interface Table Register 4194 * -------------------------------------- 4195 * The register is used to configure the router interface table. 4196 */ 4197 #define MLXSW_REG_RITR_ID 0x8002 4198 #define MLXSW_REG_RITR_LEN 0x40 4199 4200 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 4201 4202 /* reg_ritr_enable 4203 * Enables routing on the router interface. 4204 * Access: RW 4205 */ 4206 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 4207 4208 /* reg_ritr_ipv4 4209 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 4210 * interface. 4211 * Access: RW 4212 */ 4213 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 4214 4215 /* reg_ritr_ipv6 4216 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 4217 * interface. 4218 * Access: RW 4219 */ 4220 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 4221 4222 /* reg_ritr_ipv4_mc 4223 * IPv4 multicast routing enable. 4224 * Access: RW 4225 */ 4226 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 4227 4228 /* reg_ritr_ipv6_mc 4229 * IPv6 multicast routing enable. 4230 * Access: RW 4231 */ 4232 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 4233 4234 enum mlxsw_reg_ritr_if_type { 4235 /* VLAN interface. */ 4236 MLXSW_REG_RITR_VLAN_IF, 4237 /* FID interface. */ 4238 MLXSW_REG_RITR_FID_IF, 4239 /* Sub-port interface. */ 4240 MLXSW_REG_RITR_SP_IF, 4241 /* Loopback Interface. */ 4242 MLXSW_REG_RITR_LOOPBACK_IF, 4243 }; 4244 4245 /* reg_ritr_type 4246 * Router interface type as per enum mlxsw_reg_ritr_if_type. 4247 * Access: RW 4248 */ 4249 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 4250 4251 enum { 4252 MLXSW_REG_RITR_RIF_CREATE, 4253 MLXSW_REG_RITR_RIF_DEL, 4254 }; 4255 4256 /* reg_ritr_op 4257 * Opcode: 4258 * 0 - Create or edit RIF. 4259 * 1 - Delete RIF. 4260 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 4261 * is not supported. An interface must be deleted and re-created in order 4262 * to update properties. 4263 * Access: WO 4264 */ 4265 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 4266 4267 /* reg_ritr_rif 4268 * Router interface index. A pointer to the Router Interface Table. 4269 * Access: Index 4270 */ 4271 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 4272 4273 /* reg_ritr_ipv4_fe 4274 * IPv4 Forwarding Enable. 4275 * Enables routing of IPv4 traffic on the router interface. When disabled, 4276 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4277 * Not supported in SwitchX-2. 4278 * Access: RW 4279 */ 4280 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 4281 4282 /* reg_ritr_ipv6_fe 4283 * IPv6 Forwarding Enable. 4284 * Enables routing of IPv6 traffic on the router interface. When disabled, 4285 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4286 * Not supported in SwitchX-2. 4287 * Access: RW 4288 */ 4289 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 4290 4291 /* reg_ritr_ipv4_mc_fe 4292 * IPv4 Multicast Forwarding Enable. 4293 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4294 * will be enabled. 4295 * Access: RW 4296 */ 4297 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 4298 4299 /* reg_ritr_ipv6_mc_fe 4300 * IPv6 Multicast Forwarding Enable. 4301 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4302 * will be enabled. 4303 * Access: RW 4304 */ 4305 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 4306 4307 /* reg_ritr_lb_en 4308 * Loop-back filter enable for unicast packets. 4309 * If the flag is set then loop-back filter for unicast packets is 4310 * implemented on the RIF. Multicast packets are always subject to 4311 * loop-back filtering. 4312 * Access: RW 4313 */ 4314 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 4315 4316 /* reg_ritr_virtual_router 4317 * Virtual router ID associated with the router interface. 4318 * Access: RW 4319 */ 4320 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 4321 4322 /* reg_ritr_mtu 4323 * Router interface MTU. 4324 * Access: RW 4325 */ 4326 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 4327 4328 /* reg_ritr_if_swid 4329 * Switch partition ID. 4330 * Access: RW 4331 */ 4332 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 4333 4334 /* reg_ritr_if_mac 4335 * Router interface MAC address. 4336 * In Spectrum, all MAC addresses must have the same 38 MSBits. 4337 * Access: RW 4338 */ 4339 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 4340 4341 /* VLAN Interface */ 4342 4343 /* reg_ritr_vlan_if_vid 4344 * VLAN ID. 4345 * Access: RW 4346 */ 4347 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 4348 4349 /* FID Interface */ 4350 4351 /* reg_ritr_fid_if_fid 4352 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 4353 * the vFID range are supported. 4354 * Access: RW 4355 */ 4356 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 4357 4358 static inline void mlxsw_reg_ritr_fid_set(char *payload, 4359 enum mlxsw_reg_ritr_if_type rif_type, 4360 u16 fid) 4361 { 4362 if (rif_type == MLXSW_REG_RITR_FID_IF) 4363 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 4364 else 4365 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 4366 } 4367 4368 /* Sub-port Interface */ 4369 4370 /* reg_ritr_sp_if_lag 4371 * LAG indication. When this bit is set the system_port field holds the 4372 * LAG identifier. 4373 * Access: RW 4374 */ 4375 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 4376 4377 /* reg_ritr_sp_system_port 4378 * Port unique indentifier. When lag bit is set, this field holds the 4379 * lag_id in bits 0:9. 4380 * Access: RW 4381 */ 4382 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 4383 4384 /* reg_ritr_sp_if_vid 4385 * VLAN ID. 4386 * Access: RW 4387 */ 4388 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 4389 4390 /* Loopback Interface */ 4391 4392 enum mlxsw_reg_ritr_loopback_protocol { 4393 /* IPinIP IPv4 underlay Unicast */ 4394 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 4395 /* IPinIP IPv6 underlay Unicast */ 4396 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 4397 }; 4398 4399 /* reg_ritr_loopback_protocol 4400 * Access: RW 4401 */ 4402 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 4403 4404 enum mlxsw_reg_ritr_loopback_ipip_type { 4405 /* Tunnel is IPinIP. */ 4406 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 4407 /* Tunnel is GRE, no key. */ 4408 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 4409 /* Tunnel is GRE, with a key. */ 4410 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 4411 }; 4412 4413 /* reg_ritr_loopback_ipip_type 4414 * Encapsulation type. 4415 * Access: RW 4416 */ 4417 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 4418 4419 enum mlxsw_reg_ritr_loopback_ipip_options { 4420 /* The key is defined by gre_key. */ 4421 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 4422 }; 4423 4424 /* reg_ritr_loopback_ipip_options 4425 * Access: RW 4426 */ 4427 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 4428 4429 /* reg_ritr_loopback_ipip_uvr 4430 * Underlay Virtual Router ID. 4431 * Range is 0..cap_max_virtual_routers-1. 4432 * Reserved for Spectrum-2. 4433 * Access: RW 4434 */ 4435 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 4436 4437 /* reg_ritr_loopback_ipip_usip* 4438 * Encapsulation Underlay source IP. 4439 * Access: RW 4440 */ 4441 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 4442 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 4443 4444 /* reg_ritr_loopback_ipip_gre_key 4445 * GRE Key. 4446 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 4447 * Access: RW 4448 */ 4449 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 4450 4451 /* Shared between ingress/egress */ 4452 enum mlxsw_reg_ritr_counter_set_type { 4453 /* No Count. */ 4454 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 4455 /* Basic. Used for router interfaces, counting the following: 4456 * - Error and Discard counters. 4457 * - Unicast, Multicast and Broadcast counters. Sharing the 4458 * same set of counters for the different type of traffic 4459 * (IPv4, IPv6 and mpls). 4460 */ 4461 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 4462 }; 4463 4464 /* reg_ritr_ingress_counter_index 4465 * Counter Index for flow counter. 4466 * Access: RW 4467 */ 4468 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 4469 4470 /* reg_ritr_ingress_counter_set_type 4471 * Igress Counter Set Type for router interface counter. 4472 * Access: RW 4473 */ 4474 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 4475 4476 /* reg_ritr_egress_counter_index 4477 * Counter Index for flow counter. 4478 * Access: RW 4479 */ 4480 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 4481 4482 /* reg_ritr_egress_counter_set_type 4483 * Egress Counter Set Type for router interface counter. 4484 * Access: RW 4485 */ 4486 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 4487 4488 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 4489 bool enable, bool egress) 4490 { 4491 enum mlxsw_reg_ritr_counter_set_type set_type; 4492 4493 if (enable) 4494 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 4495 else 4496 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 4497 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 4498 4499 if (egress) 4500 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 4501 else 4502 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 4503 } 4504 4505 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 4506 { 4507 MLXSW_REG_ZERO(ritr, payload); 4508 mlxsw_reg_ritr_rif_set(payload, rif); 4509 } 4510 4511 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 4512 u16 system_port, u16 vid) 4513 { 4514 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 4515 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 4516 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 4517 } 4518 4519 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 4520 enum mlxsw_reg_ritr_if_type type, 4521 u16 rif, u16 vr_id, u16 mtu) 4522 { 4523 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 4524 4525 MLXSW_REG_ZERO(ritr, payload); 4526 mlxsw_reg_ritr_enable_set(payload, enable); 4527 mlxsw_reg_ritr_ipv4_set(payload, 1); 4528 mlxsw_reg_ritr_ipv6_set(payload, 1); 4529 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 4530 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 4531 mlxsw_reg_ritr_type_set(payload, type); 4532 mlxsw_reg_ritr_op_set(payload, op); 4533 mlxsw_reg_ritr_rif_set(payload, rif); 4534 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 4535 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 4536 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 4537 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 4538 mlxsw_reg_ritr_lb_en_set(payload, 1); 4539 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 4540 mlxsw_reg_ritr_mtu_set(payload, mtu); 4541 } 4542 4543 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 4544 { 4545 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 4546 } 4547 4548 static inline void 4549 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 4550 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4551 enum mlxsw_reg_ritr_loopback_ipip_options options, 4552 u16 uvr_id, u32 gre_key) 4553 { 4554 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 4555 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 4556 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 4557 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 4558 } 4559 4560 static inline void 4561 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 4562 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4563 enum mlxsw_reg_ritr_loopback_ipip_options options, 4564 u16 uvr_id, u32 usip, u32 gre_key) 4565 { 4566 mlxsw_reg_ritr_loopback_protocol_set(payload, 4567 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 4568 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 4569 uvr_id, gre_key); 4570 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 4571 } 4572 4573 /* RTAR - Router TCAM Allocation Register 4574 * -------------------------------------- 4575 * This register is used for allocation of regions in the TCAM table. 4576 */ 4577 #define MLXSW_REG_RTAR_ID 0x8004 4578 #define MLXSW_REG_RTAR_LEN 0x20 4579 4580 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 4581 4582 enum mlxsw_reg_rtar_op { 4583 MLXSW_REG_RTAR_OP_ALLOCATE, 4584 MLXSW_REG_RTAR_OP_RESIZE, 4585 MLXSW_REG_RTAR_OP_DEALLOCATE, 4586 }; 4587 4588 /* reg_rtar_op 4589 * Access: WO 4590 */ 4591 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 4592 4593 enum mlxsw_reg_rtar_key_type { 4594 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 4595 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 4596 }; 4597 4598 /* reg_rtar_key_type 4599 * TCAM key type for the region. 4600 * Access: WO 4601 */ 4602 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 4603 4604 /* reg_rtar_region_size 4605 * TCAM region size. When allocating/resizing this is the requested 4606 * size, the response is the actual size. 4607 * Note: Actual size may be larger than requested. 4608 * Reserved for op = Deallocate 4609 * Access: WO 4610 */ 4611 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 4612 4613 static inline void mlxsw_reg_rtar_pack(char *payload, 4614 enum mlxsw_reg_rtar_op op, 4615 enum mlxsw_reg_rtar_key_type key_type, 4616 u16 region_size) 4617 { 4618 MLXSW_REG_ZERO(rtar, payload); 4619 mlxsw_reg_rtar_op_set(payload, op); 4620 mlxsw_reg_rtar_key_type_set(payload, key_type); 4621 mlxsw_reg_rtar_region_size_set(payload, region_size); 4622 } 4623 4624 /* RATR - Router Adjacency Table Register 4625 * -------------------------------------- 4626 * The RATR register is used to configure the Router Adjacency (next-hop) 4627 * Table. 4628 */ 4629 #define MLXSW_REG_RATR_ID 0x8008 4630 #define MLXSW_REG_RATR_LEN 0x2C 4631 4632 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 4633 4634 enum mlxsw_reg_ratr_op { 4635 /* Read */ 4636 MLXSW_REG_RATR_OP_QUERY_READ = 0, 4637 /* Read and clear activity */ 4638 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 4639 /* Write Adjacency entry */ 4640 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 4641 /* Write Adjacency entry only if the activity is cleared. 4642 * The write may not succeed if the activity is set. There is not 4643 * direct feedback if the write has succeeded or not, however 4644 * the get will reveal the actual entry (SW can compare the get 4645 * response to the set command). 4646 */ 4647 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 4648 }; 4649 4650 /* reg_ratr_op 4651 * Note that Write operation may also be used for updating 4652 * counter_set_type and counter_index. In this case all other 4653 * fields must not be updated. 4654 * Access: OP 4655 */ 4656 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 4657 4658 /* reg_ratr_v 4659 * Valid bit. Indicates if the adjacency entry is valid. 4660 * Note: the device may need some time before reusing an invalidated 4661 * entry. During this time the entry can not be reused. It is 4662 * recommended to use another entry before reusing an invalidated 4663 * entry (e.g. software can put it at the end of the list for 4664 * reusing). Trying to access an invalidated entry not yet cleared 4665 * by the device results with failure indicating "Try Again" status. 4666 * When valid is '0' then egress_router_interface,trap_action, 4667 * adjacency_parameters and counters are reserved 4668 * Access: RW 4669 */ 4670 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 4671 4672 /* reg_ratr_a 4673 * Activity. Set for new entries. Set if a packet lookup has hit on 4674 * the specific entry. To clear the a bit, use "clear activity". 4675 * Access: RO 4676 */ 4677 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 4678 4679 enum mlxsw_reg_ratr_type { 4680 /* Ethernet */ 4681 MLXSW_REG_RATR_TYPE_ETHERNET, 4682 /* IPoIB Unicast without GRH. 4683 * Reserved for Spectrum. 4684 */ 4685 MLXSW_REG_RATR_TYPE_IPOIB_UC, 4686 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 4687 * adjacency). 4688 * Reserved for Spectrum. 4689 */ 4690 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 4691 /* IPoIB Multicast. 4692 * Reserved for Spectrum. 4693 */ 4694 MLXSW_REG_RATR_TYPE_IPOIB_MC, 4695 /* MPLS. 4696 * Reserved for SwitchX/-2. 4697 */ 4698 MLXSW_REG_RATR_TYPE_MPLS, 4699 /* IPinIP Encap. 4700 * Reserved for SwitchX/-2. 4701 */ 4702 MLXSW_REG_RATR_TYPE_IPIP, 4703 }; 4704 4705 /* reg_ratr_type 4706 * Adjacency entry type. 4707 * Access: RW 4708 */ 4709 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 4710 4711 /* reg_ratr_adjacency_index_low 4712 * Bits 15:0 of index into the adjacency table. 4713 * For SwitchX and SwitchX-2, the adjacency table is linear and 4714 * used for adjacency entries only. 4715 * For Spectrum, the index is to the KVD linear. 4716 * Access: Index 4717 */ 4718 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 4719 4720 /* reg_ratr_egress_router_interface 4721 * Range is 0 .. cap_max_router_interfaces - 1 4722 * Access: RW 4723 */ 4724 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 4725 4726 enum mlxsw_reg_ratr_trap_action { 4727 MLXSW_REG_RATR_TRAP_ACTION_NOP, 4728 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 4729 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 4730 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 4731 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 4732 }; 4733 4734 /* reg_ratr_trap_action 4735 * see mlxsw_reg_ratr_trap_action 4736 * Access: RW 4737 */ 4738 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 4739 4740 /* reg_ratr_adjacency_index_high 4741 * Bits 23:16 of the adjacency_index. 4742 * Access: Index 4743 */ 4744 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 4745 4746 enum mlxsw_reg_ratr_trap_id { 4747 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 4748 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 4749 }; 4750 4751 /* reg_ratr_trap_id 4752 * Trap ID to be reported to CPU. 4753 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 4754 * For trap_action of NOP, MIRROR and DISCARD_ERROR 4755 * Access: RW 4756 */ 4757 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 4758 4759 /* reg_ratr_eth_destination_mac 4760 * MAC address of the destination next-hop. 4761 * Access: RW 4762 */ 4763 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 4764 4765 enum mlxsw_reg_ratr_ipip_type { 4766 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 4767 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 4768 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 4769 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 4770 }; 4771 4772 /* reg_ratr_ipip_type 4773 * Underlay destination ip type. 4774 * Note: the type field must match the protocol of the router interface. 4775 * Access: RW 4776 */ 4777 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 4778 4779 /* reg_ratr_ipip_ipv4_udip 4780 * Underlay ipv4 dip. 4781 * Reserved when ipip_type is IPv6. 4782 * Access: RW 4783 */ 4784 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 4785 4786 /* reg_ratr_ipip_ipv6_ptr 4787 * Pointer to IPv6 underlay destination ip address. 4788 * For Spectrum: Pointer to KVD linear space. 4789 * Access: RW 4790 */ 4791 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 4792 4793 enum mlxsw_reg_flow_counter_set_type { 4794 /* No count */ 4795 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4796 /* Count packets and bytes */ 4797 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 4798 /* Count only packets */ 4799 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 4800 }; 4801 4802 /* reg_ratr_counter_set_type 4803 * Counter set type for flow counters 4804 * Access: RW 4805 */ 4806 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 4807 4808 /* reg_ratr_counter_index 4809 * Counter index for flow counters 4810 * Access: RW 4811 */ 4812 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 4813 4814 static inline void 4815 mlxsw_reg_ratr_pack(char *payload, 4816 enum mlxsw_reg_ratr_op op, bool valid, 4817 enum mlxsw_reg_ratr_type type, 4818 u32 adjacency_index, u16 egress_rif) 4819 { 4820 MLXSW_REG_ZERO(ratr, payload); 4821 mlxsw_reg_ratr_op_set(payload, op); 4822 mlxsw_reg_ratr_v_set(payload, valid); 4823 mlxsw_reg_ratr_type_set(payload, type); 4824 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 4825 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 4826 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 4827 } 4828 4829 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 4830 const char *dest_mac) 4831 { 4832 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 4833 } 4834 4835 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 4836 { 4837 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 4838 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 4839 } 4840 4841 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 4842 bool counter_enable) 4843 { 4844 enum mlxsw_reg_flow_counter_set_type set_type; 4845 4846 if (counter_enable) 4847 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 4848 else 4849 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 4850 4851 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 4852 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 4853 } 4854 4855 /* RDPM - Router DSCP to Priority Mapping 4856 * -------------------------------------- 4857 * Controls the mapping from DSCP field to switch priority on routed packets 4858 */ 4859 #define MLXSW_REG_RDPM_ID 0x8009 4860 #define MLXSW_REG_RDPM_BASE_LEN 0x00 4861 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 4862 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4863 #define MLXSW_REG_RDPM_LEN 0x40 4864 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 4865 MLXSW_REG_RDPM_LEN - \ 4866 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 4867 4868 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 4869 4870 /* reg_dscp_entry_e 4871 * Enable update of the specific entry 4872 * Access: Index 4873 */ 4874 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 4875 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4876 4877 /* reg_dscp_entry_prio 4878 * Switch Priority 4879 * Access: RW 4880 */ 4881 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 4882 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4883 4884 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 4885 u8 prio) 4886 { 4887 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 4888 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 4889 } 4890 4891 /* RICNT - Router Interface Counter Register 4892 * ----------------------------------------- 4893 * The RICNT register retrieves per port performance counters 4894 */ 4895 #define MLXSW_REG_RICNT_ID 0x800B 4896 #define MLXSW_REG_RICNT_LEN 0x100 4897 4898 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 4899 4900 /* reg_ricnt_counter_index 4901 * Counter index 4902 * Access: RW 4903 */ 4904 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 4905 4906 enum mlxsw_reg_ricnt_counter_set_type { 4907 /* No Count. */ 4908 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4909 /* Basic. Used for router interfaces, counting the following: 4910 * - Error and Discard counters. 4911 * - Unicast, Multicast and Broadcast counters. Sharing the 4912 * same set of counters for the different type of traffic 4913 * (IPv4, IPv6 and mpls). 4914 */ 4915 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 4916 }; 4917 4918 /* reg_ricnt_counter_set_type 4919 * Counter Set Type for router interface counter 4920 * Access: RW 4921 */ 4922 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 4923 4924 enum mlxsw_reg_ricnt_opcode { 4925 /* Nop. Supported only for read access*/ 4926 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 4927 /* Clear. Setting the clr bit will reset the counter value for 4928 * all counters of the specified Router Interface. 4929 */ 4930 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 4931 }; 4932 4933 /* reg_ricnt_opcode 4934 * Opcode 4935 * Access: RW 4936 */ 4937 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 4938 4939 /* reg_ricnt_good_unicast_packets 4940 * good unicast packets. 4941 * Access: RW 4942 */ 4943 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 4944 4945 /* reg_ricnt_good_multicast_packets 4946 * good multicast packets. 4947 * Access: RW 4948 */ 4949 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 4950 4951 /* reg_ricnt_good_broadcast_packets 4952 * good broadcast packets 4953 * Access: RW 4954 */ 4955 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 4956 4957 /* reg_ricnt_good_unicast_bytes 4958 * A count of L3 data and padding octets not including L2 headers 4959 * for good unicast frames. 4960 * Access: RW 4961 */ 4962 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 4963 4964 /* reg_ricnt_good_multicast_bytes 4965 * A count of L3 data and padding octets not including L2 headers 4966 * for good multicast frames. 4967 * Access: RW 4968 */ 4969 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 4970 4971 /* reg_ritr_good_broadcast_bytes 4972 * A count of L3 data and padding octets not including L2 headers 4973 * for good broadcast frames. 4974 * Access: RW 4975 */ 4976 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 4977 4978 /* reg_ricnt_error_packets 4979 * A count of errored frames that do not pass the router checks. 4980 * Access: RW 4981 */ 4982 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 4983 4984 /* reg_ricnt_discrad_packets 4985 * A count of non-errored frames that do not pass the router checks. 4986 * Access: RW 4987 */ 4988 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 4989 4990 /* reg_ricnt_error_bytes 4991 * A count of L3 data and padding octets not including L2 headers 4992 * for errored frames. 4993 * Access: RW 4994 */ 4995 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 4996 4997 /* reg_ricnt_discard_bytes 4998 * A count of L3 data and padding octets not including L2 headers 4999 * for non-errored frames that do not pass the router checks. 5000 * Access: RW 5001 */ 5002 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 5003 5004 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 5005 enum mlxsw_reg_ricnt_opcode op) 5006 { 5007 MLXSW_REG_ZERO(ricnt, payload); 5008 mlxsw_reg_ricnt_op_set(payload, op); 5009 mlxsw_reg_ricnt_counter_index_set(payload, index); 5010 mlxsw_reg_ricnt_counter_set_type_set(payload, 5011 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 5012 } 5013 5014 /* RRCR - Router Rules Copy Register Layout 5015 * ---------------------------------------- 5016 * This register is used for moving and copying route entry rules. 5017 */ 5018 #define MLXSW_REG_RRCR_ID 0x800F 5019 #define MLXSW_REG_RRCR_LEN 0x24 5020 5021 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 5022 5023 enum mlxsw_reg_rrcr_op { 5024 /* Move rules */ 5025 MLXSW_REG_RRCR_OP_MOVE, 5026 /* Copy rules */ 5027 MLXSW_REG_RRCR_OP_COPY, 5028 }; 5029 5030 /* reg_rrcr_op 5031 * Access: WO 5032 */ 5033 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 5034 5035 /* reg_rrcr_offset 5036 * Offset within the region from which to copy/move. 5037 * Access: Index 5038 */ 5039 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 5040 5041 /* reg_rrcr_size 5042 * The number of rules to copy/move. 5043 * Access: WO 5044 */ 5045 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 5046 5047 /* reg_rrcr_table_id 5048 * Identifier of the table on which to perform the operation. Encoding is the 5049 * same as in RTAR.key_type 5050 * Access: Index 5051 */ 5052 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 5053 5054 /* reg_rrcr_dest_offset 5055 * Offset within the region to which to copy/move 5056 * Access: Index 5057 */ 5058 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 5059 5060 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 5061 u16 offset, u16 size, 5062 enum mlxsw_reg_rtar_key_type table_id, 5063 u16 dest_offset) 5064 { 5065 MLXSW_REG_ZERO(rrcr, payload); 5066 mlxsw_reg_rrcr_op_set(payload, op); 5067 mlxsw_reg_rrcr_offset_set(payload, offset); 5068 mlxsw_reg_rrcr_size_set(payload, size); 5069 mlxsw_reg_rrcr_table_id_set(payload, table_id); 5070 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 5071 } 5072 5073 /* RALTA - Router Algorithmic LPM Tree Allocation Register 5074 * ------------------------------------------------------- 5075 * RALTA is used to allocate the LPM trees of the SHSPM method. 5076 */ 5077 #define MLXSW_REG_RALTA_ID 0x8010 5078 #define MLXSW_REG_RALTA_LEN 0x04 5079 5080 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 5081 5082 /* reg_ralta_op 5083 * opcode (valid for Write, must be 0 on Read) 5084 * 0 - allocate a tree 5085 * 1 - deallocate a tree 5086 * Access: OP 5087 */ 5088 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 5089 5090 enum mlxsw_reg_ralxx_protocol { 5091 MLXSW_REG_RALXX_PROTOCOL_IPV4, 5092 MLXSW_REG_RALXX_PROTOCOL_IPV6, 5093 }; 5094 5095 /* reg_ralta_protocol 5096 * Protocol. 5097 * Deallocation opcode: Reserved. 5098 * Access: RW 5099 */ 5100 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 5101 5102 /* reg_ralta_tree_id 5103 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 5104 * the tree identifier (managed by software). 5105 * Note that tree_id 0 is allocated for a default-route tree. 5106 * Access: Index 5107 */ 5108 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 5109 5110 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 5111 enum mlxsw_reg_ralxx_protocol protocol, 5112 u8 tree_id) 5113 { 5114 MLXSW_REG_ZERO(ralta, payload); 5115 mlxsw_reg_ralta_op_set(payload, !alloc); 5116 mlxsw_reg_ralta_protocol_set(payload, protocol); 5117 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 5118 } 5119 5120 /* RALST - Router Algorithmic LPM Structure Tree Register 5121 * ------------------------------------------------------ 5122 * RALST is used to set and query the structure of an LPM tree. 5123 * The structure of the tree must be sorted as a sorted binary tree, while 5124 * each node is a bin that is tagged as the length of the prefixes the lookup 5125 * will refer to. Therefore, bin X refers to a set of entries with prefixes 5126 * of X bits to match with the destination address. The bin 0 indicates 5127 * the default action, when there is no match of any prefix. 5128 */ 5129 #define MLXSW_REG_RALST_ID 0x8011 5130 #define MLXSW_REG_RALST_LEN 0x104 5131 5132 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 5133 5134 /* reg_ralst_root_bin 5135 * The bin number of the root bin. 5136 * 0<root_bin=<(length of IP address) 5137 * For a default-route tree configure 0xff 5138 * Access: RW 5139 */ 5140 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 5141 5142 /* reg_ralst_tree_id 5143 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5144 * Access: Index 5145 */ 5146 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 5147 5148 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 5149 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 5150 #define MLXSW_REG_RALST_BIN_COUNT 128 5151 5152 /* reg_ralst_left_child_bin 5153 * Holding the children of the bin according to the stored tree's structure. 5154 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5155 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5156 * Access: RW 5157 */ 5158 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 5159 5160 /* reg_ralst_right_child_bin 5161 * Holding the children of the bin according to the stored tree's structure. 5162 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5163 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5164 * Access: RW 5165 */ 5166 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 5167 false); 5168 5169 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 5170 { 5171 MLXSW_REG_ZERO(ralst, payload); 5172 5173 /* Initialize all bins to have no left or right child */ 5174 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 5175 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 5176 5177 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 5178 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 5179 } 5180 5181 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 5182 u8 left_child_bin, 5183 u8 right_child_bin) 5184 { 5185 int bin_index = bin_number - 1; 5186 5187 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 5188 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 5189 right_child_bin); 5190 } 5191 5192 /* RALTB - Router Algorithmic LPM Tree Binding Register 5193 * ---------------------------------------------------- 5194 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 5195 */ 5196 #define MLXSW_REG_RALTB_ID 0x8012 5197 #define MLXSW_REG_RALTB_LEN 0x04 5198 5199 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 5200 5201 /* reg_raltb_virtual_router 5202 * Virtual Router ID 5203 * Range is 0..cap_max_virtual_routers-1 5204 * Access: Index 5205 */ 5206 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 5207 5208 /* reg_raltb_protocol 5209 * Protocol. 5210 * Access: Index 5211 */ 5212 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 5213 5214 /* reg_raltb_tree_id 5215 * Tree to be used for the {virtual_router, protocol} 5216 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5217 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 5218 * Access: RW 5219 */ 5220 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 5221 5222 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 5223 enum mlxsw_reg_ralxx_protocol protocol, 5224 u8 tree_id) 5225 { 5226 MLXSW_REG_ZERO(raltb, payload); 5227 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 5228 mlxsw_reg_raltb_protocol_set(payload, protocol); 5229 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 5230 } 5231 5232 /* RALUE - Router Algorithmic LPM Unicast Entry Register 5233 * ----------------------------------------------------- 5234 * RALUE is used to configure and query LPM entries that serve 5235 * the Unicast protocols. 5236 */ 5237 #define MLXSW_REG_RALUE_ID 0x8013 5238 #define MLXSW_REG_RALUE_LEN 0x38 5239 5240 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 5241 5242 /* reg_ralue_protocol 5243 * Protocol. 5244 * Access: Index 5245 */ 5246 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 5247 5248 enum mlxsw_reg_ralue_op { 5249 /* Read operation. If entry doesn't exist, the operation fails. */ 5250 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 5251 /* Clear on read operation. Used to read entry and 5252 * clear Activity bit. 5253 */ 5254 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 5255 /* Write operation. Used to write a new entry to the table. All RW 5256 * fields are written for new entry. Activity bit is set 5257 * for new entries. 5258 */ 5259 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 5260 /* Update operation. Used to update an existing route entry and 5261 * only update the RW fields that are detailed in the field 5262 * op_u_mask. If entry doesn't exist, the operation fails. 5263 */ 5264 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 5265 /* Clear activity. The Activity bit (the field a) is cleared 5266 * for the entry. 5267 */ 5268 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 5269 /* Delete operation. Used to delete an existing entry. If entry 5270 * doesn't exist, the operation fails. 5271 */ 5272 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 5273 }; 5274 5275 /* reg_ralue_op 5276 * Operation. 5277 * Access: OP 5278 */ 5279 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 5280 5281 /* reg_ralue_a 5282 * Activity. Set for new entries. Set if a packet lookup has hit on the 5283 * specific entry, only if the entry is a route. To clear the a bit, use 5284 * "clear activity" op. 5285 * Enabled by activity_dis in RGCR 5286 * Access: RO 5287 */ 5288 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 5289 5290 /* reg_ralue_virtual_router 5291 * Virtual Router ID 5292 * Range is 0..cap_max_virtual_routers-1 5293 * Access: Index 5294 */ 5295 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 5296 5297 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 5298 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 5299 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 5300 5301 /* reg_ralue_op_u_mask 5302 * opcode update mask. 5303 * On read operation, this field is reserved. 5304 * This field is valid for update opcode, otherwise - reserved. 5305 * This field is a bitmask of the fields that should be updated. 5306 * Access: WO 5307 */ 5308 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 5309 5310 /* reg_ralue_prefix_len 5311 * Number of bits in the prefix of the LPM route. 5312 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 5313 * two entries in the physical HW table. 5314 * Access: Index 5315 */ 5316 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 5317 5318 /* reg_ralue_dip* 5319 * The prefix of the route or of the marker that the object of the LPM 5320 * is compared with. The most significant bits of the dip are the prefix. 5321 * The least significant bits must be '0' if the prefix_len is smaller 5322 * than 128 for IPv6 or smaller than 32 for IPv4. 5323 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 5324 * Access: Index 5325 */ 5326 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 5327 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 5328 5329 enum mlxsw_reg_ralue_entry_type { 5330 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 5331 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 5332 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 5333 }; 5334 5335 /* reg_ralue_entry_type 5336 * Entry type. 5337 * Note - for Marker entries, the action_type and action fields are reserved. 5338 * Access: RW 5339 */ 5340 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 5341 5342 /* reg_ralue_bmp_len 5343 * The best match prefix length in the case that there is no match for 5344 * longer prefixes. 5345 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 5346 * Note for any update operation with entry_type modification this 5347 * field must be set. 5348 * Access: RW 5349 */ 5350 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 5351 5352 enum mlxsw_reg_ralue_action_type { 5353 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 5354 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 5355 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 5356 }; 5357 5358 /* reg_ralue_action_type 5359 * Action Type 5360 * Indicates how the IP address is connected. 5361 * It can be connected to a local subnet through local_erif or can be 5362 * on a remote subnet connected through a next-hop router, 5363 * or transmitted to the CPU. 5364 * Reserved when entry_type = MARKER_ENTRY 5365 * Access: RW 5366 */ 5367 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 5368 5369 enum mlxsw_reg_ralue_trap_action { 5370 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 5371 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 5372 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 5373 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 5374 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 5375 }; 5376 5377 /* reg_ralue_trap_action 5378 * Trap action. 5379 * For IP2ME action, only NOP and MIRROR are possible. 5380 * Access: RW 5381 */ 5382 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 5383 5384 /* reg_ralue_trap_id 5385 * Trap ID to be reported to CPU. 5386 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 5387 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 5388 * Access: RW 5389 */ 5390 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 5391 5392 /* reg_ralue_adjacency_index 5393 * Points to the first entry of the group-based ECMP. 5394 * Only relevant in case of REMOTE action. 5395 * Access: RW 5396 */ 5397 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 5398 5399 /* reg_ralue_ecmp_size 5400 * Amount of sequential entries starting 5401 * from the adjacency_index (the number of ECMPs). 5402 * The valid range is 1-64, 512, 1024, 2048 and 4096. 5403 * Reserved when trap_action is TRAP or DISCARD_ERROR. 5404 * Only relevant in case of REMOTE action. 5405 * Access: RW 5406 */ 5407 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 5408 5409 /* reg_ralue_local_erif 5410 * Egress Router Interface. 5411 * Only relevant in case of LOCAL action. 5412 * Access: RW 5413 */ 5414 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 5415 5416 /* reg_ralue_ip2me_v 5417 * Valid bit for the tunnel_ptr field. 5418 * If valid = 0 then trap to CPU as IP2ME trap ID. 5419 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 5420 * decapsulation then tunnel decapsulation is done. 5421 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 5422 * decapsulation then trap as IP2ME trap ID. 5423 * Only relevant in case of IP2ME action. 5424 * Access: RW 5425 */ 5426 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 5427 5428 /* reg_ralue_ip2me_tunnel_ptr 5429 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 5430 * For Spectrum, pointer to KVD Linear. 5431 * Only relevant in case of IP2ME action. 5432 * Access: RW 5433 */ 5434 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 5435 5436 static inline void mlxsw_reg_ralue_pack(char *payload, 5437 enum mlxsw_reg_ralxx_protocol protocol, 5438 enum mlxsw_reg_ralue_op op, 5439 u16 virtual_router, u8 prefix_len) 5440 { 5441 MLXSW_REG_ZERO(ralue, payload); 5442 mlxsw_reg_ralue_protocol_set(payload, protocol); 5443 mlxsw_reg_ralue_op_set(payload, op); 5444 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 5445 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 5446 mlxsw_reg_ralue_entry_type_set(payload, 5447 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 5448 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 5449 } 5450 5451 static inline void mlxsw_reg_ralue_pack4(char *payload, 5452 enum mlxsw_reg_ralxx_protocol protocol, 5453 enum mlxsw_reg_ralue_op op, 5454 u16 virtual_router, u8 prefix_len, 5455 u32 dip) 5456 { 5457 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5458 mlxsw_reg_ralue_dip4_set(payload, dip); 5459 } 5460 5461 static inline void mlxsw_reg_ralue_pack6(char *payload, 5462 enum mlxsw_reg_ralxx_protocol protocol, 5463 enum mlxsw_reg_ralue_op op, 5464 u16 virtual_router, u8 prefix_len, 5465 const void *dip) 5466 { 5467 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5468 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 5469 } 5470 5471 static inline void 5472 mlxsw_reg_ralue_act_remote_pack(char *payload, 5473 enum mlxsw_reg_ralue_trap_action trap_action, 5474 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 5475 { 5476 mlxsw_reg_ralue_action_type_set(payload, 5477 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 5478 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5479 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5480 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 5481 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 5482 } 5483 5484 static inline void 5485 mlxsw_reg_ralue_act_local_pack(char *payload, 5486 enum mlxsw_reg_ralue_trap_action trap_action, 5487 u16 trap_id, u16 local_erif) 5488 { 5489 mlxsw_reg_ralue_action_type_set(payload, 5490 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 5491 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5492 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5493 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 5494 } 5495 5496 static inline void 5497 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 5498 { 5499 mlxsw_reg_ralue_action_type_set(payload, 5500 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5501 } 5502 5503 static inline void 5504 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 5505 { 5506 mlxsw_reg_ralue_action_type_set(payload, 5507 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5508 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 5509 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 5510 } 5511 5512 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 5513 * ---------------------------------------------------------- 5514 * The RAUHT register is used to configure and query the Unicast Host table in 5515 * devices that implement the Algorithmic LPM. 5516 */ 5517 #define MLXSW_REG_RAUHT_ID 0x8014 5518 #define MLXSW_REG_RAUHT_LEN 0x74 5519 5520 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 5521 5522 enum mlxsw_reg_rauht_type { 5523 MLXSW_REG_RAUHT_TYPE_IPV4, 5524 MLXSW_REG_RAUHT_TYPE_IPV6, 5525 }; 5526 5527 /* reg_rauht_type 5528 * Access: Index 5529 */ 5530 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 5531 5532 enum mlxsw_reg_rauht_op { 5533 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 5534 /* Read operation */ 5535 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 5536 /* Clear on read operation. Used to read entry and clear 5537 * activity bit. 5538 */ 5539 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 5540 /* Add. Used to write a new entry to the table. All R/W fields are 5541 * relevant for new entry. Activity bit is set for new entries. 5542 */ 5543 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 5544 /* Update action. Used to update an existing route entry and 5545 * only update the following fields: 5546 * trap_action, trap_id, mac, counter_set_type, counter_index 5547 */ 5548 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 5549 /* Clear activity. A bit is cleared for the entry. */ 5550 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 5551 /* Delete entry */ 5552 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 5553 /* Delete all host entries on a RIF. In this command, dip 5554 * field is reserved. 5555 */ 5556 }; 5557 5558 /* reg_rauht_op 5559 * Access: OP 5560 */ 5561 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 5562 5563 /* reg_rauht_a 5564 * Activity. Set for new entries. Set if a packet lookup has hit on 5565 * the specific entry. 5566 * To clear the a bit, use "clear activity" op. 5567 * Enabled by activity_dis in RGCR 5568 * Access: RO 5569 */ 5570 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 5571 5572 /* reg_rauht_rif 5573 * Router Interface 5574 * Access: Index 5575 */ 5576 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 5577 5578 /* reg_rauht_dip* 5579 * Destination address. 5580 * Access: Index 5581 */ 5582 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 5583 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 5584 5585 enum mlxsw_reg_rauht_trap_action { 5586 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 5587 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 5588 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 5589 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 5590 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 5591 }; 5592 5593 /* reg_rauht_trap_action 5594 * Access: RW 5595 */ 5596 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 5597 5598 enum mlxsw_reg_rauht_trap_id { 5599 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 5600 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 5601 }; 5602 5603 /* reg_rauht_trap_id 5604 * Trap ID to be reported to CPU. 5605 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5606 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 5607 * trap_id is reserved. 5608 * Access: RW 5609 */ 5610 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 5611 5612 /* reg_rauht_counter_set_type 5613 * Counter set type for flow counters 5614 * Access: RW 5615 */ 5616 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 5617 5618 /* reg_rauht_counter_index 5619 * Counter index for flow counters 5620 * Access: RW 5621 */ 5622 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 5623 5624 /* reg_rauht_mac 5625 * MAC address. 5626 * Access: RW 5627 */ 5628 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 5629 5630 static inline void mlxsw_reg_rauht_pack(char *payload, 5631 enum mlxsw_reg_rauht_op op, u16 rif, 5632 const char *mac) 5633 { 5634 MLXSW_REG_ZERO(rauht, payload); 5635 mlxsw_reg_rauht_op_set(payload, op); 5636 mlxsw_reg_rauht_rif_set(payload, rif); 5637 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 5638 } 5639 5640 static inline void mlxsw_reg_rauht_pack4(char *payload, 5641 enum mlxsw_reg_rauht_op op, u16 rif, 5642 const char *mac, u32 dip) 5643 { 5644 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5645 mlxsw_reg_rauht_dip4_set(payload, dip); 5646 } 5647 5648 static inline void mlxsw_reg_rauht_pack6(char *payload, 5649 enum mlxsw_reg_rauht_op op, u16 rif, 5650 const char *mac, const char *dip) 5651 { 5652 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5653 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 5654 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 5655 } 5656 5657 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 5658 u64 counter_index) 5659 { 5660 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 5661 mlxsw_reg_rauht_counter_set_type_set(payload, 5662 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 5663 } 5664 5665 /* RALEU - Router Algorithmic LPM ECMP Update Register 5666 * --------------------------------------------------- 5667 * The register enables updating the ECMP section in the action for multiple 5668 * LPM Unicast entries in a single operation. The update is executed to 5669 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 5670 */ 5671 #define MLXSW_REG_RALEU_ID 0x8015 5672 #define MLXSW_REG_RALEU_LEN 0x28 5673 5674 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 5675 5676 /* reg_raleu_protocol 5677 * Protocol. 5678 * Access: Index 5679 */ 5680 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 5681 5682 /* reg_raleu_virtual_router 5683 * Virtual Router ID 5684 * Range is 0..cap_max_virtual_routers-1 5685 * Access: Index 5686 */ 5687 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 5688 5689 /* reg_raleu_adjacency_index 5690 * Adjacency Index used for matching on the existing entries. 5691 * Access: Index 5692 */ 5693 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 5694 5695 /* reg_raleu_ecmp_size 5696 * ECMP Size used for matching on the existing entries. 5697 * Access: Index 5698 */ 5699 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 5700 5701 /* reg_raleu_new_adjacency_index 5702 * New Adjacency Index. 5703 * Access: WO 5704 */ 5705 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 5706 5707 /* reg_raleu_new_ecmp_size 5708 * New ECMP Size. 5709 * Access: WO 5710 */ 5711 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 5712 5713 static inline void mlxsw_reg_raleu_pack(char *payload, 5714 enum mlxsw_reg_ralxx_protocol protocol, 5715 u16 virtual_router, 5716 u32 adjacency_index, u16 ecmp_size, 5717 u32 new_adjacency_index, 5718 u16 new_ecmp_size) 5719 { 5720 MLXSW_REG_ZERO(raleu, payload); 5721 mlxsw_reg_raleu_protocol_set(payload, protocol); 5722 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 5723 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 5724 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 5725 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 5726 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 5727 } 5728 5729 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 5730 * ---------------------------------------------------------------- 5731 * The RAUHTD register allows dumping entries from the Router Unicast Host 5732 * Table. For a given session an entry is dumped no more than one time. The 5733 * first RAUHTD access after reset is a new session. A session ends when the 5734 * num_rec response is smaller than num_rec request or for IPv4 when the 5735 * num_entries is smaller than 4. The clear activity affect the current session 5736 * or the last session if a new session has not started. 5737 */ 5738 #define MLXSW_REG_RAUHTD_ID 0x8018 5739 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 5740 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 5741 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 5742 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 5743 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 5744 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 5745 5746 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 5747 5748 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 5749 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 5750 5751 /* reg_rauhtd_filter_fields 5752 * if a bit is '0' then the relevant field is ignored and dump is done 5753 * regardless of the field value 5754 * Bit0 - filter by activity: entry_a 5755 * Bit3 - filter by entry rip: entry_rif 5756 * Access: Index 5757 */ 5758 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 5759 5760 enum mlxsw_reg_rauhtd_op { 5761 MLXSW_REG_RAUHTD_OP_DUMP, 5762 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 5763 }; 5764 5765 /* reg_rauhtd_op 5766 * Access: OP 5767 */ 5768 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 5769 5770 /* reg_rauhtd_num_rec 5771 * At request: number of records requested 5772 * At response: number of records dumped 5773 * For IPv4, each record has 4 entries at request and up to 4 entries 5774 * at response 5775 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 5776 * Access: Index 5777 */ 5778 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 5779 5780 /* reg_rauhtd_entry_a 5781 * Dump only if activity has value of entry_a 5782 * Reserved if filter_fields bit0 is '0' 5783 * Access: Index 5784 */ 5785 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 5786 5787 enum mlxsw_reg_rauhtd_type { 5788 MLXSW_REG_RAUHTD_TYPE_IPV4, 5789 MLXSW_REG_RAUHTD_TYPE_IPV6, 5790 }; 5791 5792 /* reg_rauhtd_type 5793 * Dump only if record type is: 5794 * 0 - IPv4 5795 * 1 - IPv6 5796 * Access: Index 5797 */ 5798 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 5799 5800 /* reg_rauhtd_entry_rif 5801 * Dump only if RIF has value of entry_rif 5802 * Reserved if filter_fields bit3 is '0' 5803 * Access: Index 5804 */ 5805 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 5806 5807 static inline void mlxsw_reg_rauhtd_pack(char *payload, 5808 enum mlxsw_reg_rauhtd_type type) 5809 { 5810 MLXSW_REG_ZERO(rauhtd, payload); 5811 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 5812 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 5813 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 5814 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 5815 mlxsw_reg_rauhtd_type_set(payload, type); 5816 } 5817 5818 /* reg_rauhtd_ipv4_rec_num_entries 5819 * Number of valid entries in this record: 5820 * 0 - 1 valid entry 5821 * 1 - 2 valid entries 5822 * 2 - 3 valid entries 5823 * 3 - 4 valid entries 5824 * Access: RO 5825 */ 5826 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 5827 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 5828 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5829 5830 /* reg_rauhtd_rec_type 5831 * Record type. 5832 * 0 - IPv4 5833 * 1 - IPv6 5834 * Access: RO 5835 */ 5836 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 5837 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5838 5839 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 5840 5841 /* reg_rauhtd_ipv4_ent_a 5842 * Activity. Set for new entries. Set if a packet lookup has hit on the 5843 * specific entry. 5844 * Access: RO 5845 */ 5846 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5847 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5848 5849 /* reg_rauhtd_ipv4_ent_rif 5850 * Router interface. 5851 * Access: RO 5852 */ 5853 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5854 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5855 5856 /* reg_rauhtd_ipv4_ent_dip 5857 * Destination IPv4 address. 5858 * Access: RO 5859 */ 5860 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5861 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 5862 5863 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 5864 5865 /* reg_rauhtd_ipv6_ent_a 5866 * Activity. Set for new entries. Set if a packet lookup has hit on the 5867 * specific entry. 5868 * Access: RO 5869 */ 5870 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5871 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5872 5873 /* reg_rauhtd_ipv6_ent_rif 5874 * Router interface. 5875 * Access: RO 5876 */ 5877 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5878 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5879 5880 /* reg_rauhtd_ipv6_ent_dip 5881 * Destination IPv6 address. 5882 * Access: RO 5883 */ 5884 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 5885 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 5886 5887 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 5888 int ent_index, u16 *p_rif, 5889 u32 *p_dip) 5890 { 5891 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 5892 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 5893 } 5894 5895 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 5896 int rec_index, u16 *p_rif, 5897 char *p_dip) 5898 { 5899 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 5900 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 5901 } 5902 5903 /* RTDP - Routing Tunnel Decap Properties Register 5904 * ----------------------------------------------- 5905 * The RTDP register is used for configuring the tunnel decap properties of NVE 5906 * and IPinIP. 5907 */ 5908 #define MLXSW_REG_RTDP_ID 0x8020 5909 #define MLXSW_REG_RTDP_LEN 0x44 5910 5911 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 5912 5913 enum mlxsw_reg_rtdp_type { 5914 MLXSW_REG_RTDP_TYPE_NVE, 5915 MLXSW_REG_RTDP_TYPE_IPIP, 5916 }; 5917 5918 /* reg_rtdp_type 5919 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 5920 * Access: RW 5921 */ 5922 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 5923 5924 /* reg_rtdp_tunnel_index 5925 * Index to the Decap entry. 5926 * For Spectrum, Index to KVD Linear. 5927 * Access: Index 5928 */ 5929 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 5930 5931 /* IPinIP */ 5932 5933 /* reg_rtdp_ipip_irif 5934 * Ingress Router Interface for the overlay router 5935 * Access: RW 5936 */ 5937 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 5938 5939 enum mlxsw_reg_rtdp_ipip_sip_check { 5940 /* No sip checks. */ 5941 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 5942 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 5943 * equal ipv4_usip. 5944 */ 5945 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 5946 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 5947 * equal ipv6_usip. 5948 */ 5949 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 5950 }; 5951 5952 /* reg_rtdp_ipip_sip_check 5953 * SIP check to perform. If decapsulation failed due to these configurations 5954 * then trap_id is IPIP_DECAP_ERROR. 5955 * Access: RW 5956 */ 5957 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 5958 5959 /* If set, allow decapsulation of IPinIP (without GRE). */ 5960 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 5961 /* If set, allow decapsulation of IPinGREinIP without a key. */ 5962 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 5963 /* If set, allow decapsulation of IPinGREinIP with a key. */ 5964 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 5965 5966 /* reg_rtdp_ipip_type_check 5967 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 5968 * these configurations then trap_id is IPIP_DECAP_ERROR. 5969 * Access: RW 5970 */ 5971 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 5972 5973 /* reg_rtdp_ipip_gre_key_check 5974 * Whether GRE key should be checked. When check is enabled: 5975 * - A packet received as IPinIP (without GRE) will always pass. 5976 * - A packet received as IPinGREinIP without a key will not pass the check. 5977 * - A packet received as IPinGREinIP with a key will pass the check only if the 5978 * key in the packet is equal to expected_gre_key. 5979 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 5980 * Access: RW 5981 */ 5982 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 5983 5984 /* reg_rtdp_ipip_ipv4_usip 5985 * Underlay IPv4 address for ipv4 source address check. 5986 * Reserved when sip_check is not '1'. 5987 * Access: RW 5988 */ 5989 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 5990 5991 /* reg_rtdp_ipip_ipv6_usip_ptr 5992 * This field is valid when sip_check is "sipv6 check explicitly". This is a 5993 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 5994 * is to the KVD linear. 5995 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 5996 * Access: RW 5997 */ 5998 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 5999 6000 /* reg_rtdp_ipip_expected_gre_key 6001 * GRE key for checking. 6002 * Reserved when gre_key_check is '0'. 6003 * Access: RW 6004 */ 6005 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 6006 6007 static inline void mlxsw_reg_rtdp_pack(char *payload, 6008 enum mlxsw_reg_rtdp_type type, 6009 u32 tunnel_index) 6010 { 6011 MLXSW_REG_ZERO(rtdp, payload); 6012 mlxsw_reg_rtdp_type_set(payload, type); 6013 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 6014 } 6015 6016 static inline void 6017 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 6018 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 6019 unsigned int type_check, bool gre_key_check, 6020 u32 ipv4_usip, u32 expected_gre_key) 6021 { 6022 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 6023 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 6024 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 6025 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 6026 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 6027 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 6028 } 6029 6030 /* RIGR-V2 - Router Interface Group Register Version 2 6031 * --------------------------------------------------- 6032 * The RIGR_V2 register is used to add, remove and query egress interface list 6033 * of a multicast forwarding entry. 6034 */ 6035 #define MLXSW_REG_RIGR2_ID 0x8023 6036 #define MLXSW_REG_RIGR2_LEN 0xB0 6037 6038 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 6039 6040 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 6041 6042 /* reg_rigr2_rigr_index 6043 * KVD Linear index. 6044 * Access: Index 6045 */ 6046 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 6047 6048 /* reg_rigr2_vnext 6049 * Next RIGR Index is valid. 6050 * Access: RW 6051 */ 6052 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 6053 6054 /* reg_rigr2_next_rigr_index 6055 * Next RIGR Index. The index is to the KVD linear. 6056 * Reserved when vnxet = '0'. 6057 * Access: RW 6058 */ 6059 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 6060 6061 /* reg_rigr2_vrmid 6062 * RMID Index is valid. 6063 * Access: RW 6064 */ 6065 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 6066 6067 /* reg_rigr2_rmid_index 6068 * RMID Index. 6069 * Range 0 .. max_mid - 1 6070 * Reserved when vrmid = '0'. 6071 * The index is to the Port Group Table (PGT) 6072 * Access: RW 6073 */ 6074 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 6075 6076 /* reg_rigr2_erif_entry_v 6077 * Egress Router Interface is valid. 6078 * Note that low-entries must be set if high-entries are set. For 6079 * example: if erif_entry[2].v is set then erif_entry[1].v and 6080 * erif_entry[0].v must be set. 6081 * Index can be from 0 to cap_mc_erif_list_entries-1 6082 * Access: RW 6083 */ 6084 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 6085 6086 /* reg_rigr2_erif_entry_erif 6087 * Egress Router Interface. 6088 * Valid range is from 0 to cap_max_router_interfaces - 1 6089 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 6090 * Access: RW 6091 */ 6092 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 6093 6094 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 6095 bool vnext, u32 next_rigr_index) 6096 { 6097 MLXSW_REG_ZERO(rigr2, payload); 6098 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 6099 mlxsw_reg_rigr2_vnext_set(payload, vnext); 6100 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 6101 mlxsw_reg_rigr2_vrmid_set(payload, 0); 6102 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 6103 } 6104 6105 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 6106 bool v, u16 erif) 6107 { 6108 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 6109 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 6110 } 6111 6112 /* RECR-V2 - Router ECMP Configuration Version 2 Register 6113 * ------------------------------------------------------ 6114 */ 6115 #define MLXSW_REG_RECR2_ID 0x8025 6116 #define MLXSW_REG_RECR2_LEN 0x38 6117 6118 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 6119 6120 /* reg_recr2_pp 6121 * Per-port configuration 6122 * Access: Index 6123 */ 6124 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 6125 6126 /* reg_recr2_sh 6127 * Symmetric hash 6128 * Access: RW 6129 */ 6130 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 6131 6132 /* reg_recr2_seed 6133 * Seed 6134 * Access: RW 6135 */ 6136 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 6137 6138 enum { 6139 /* Enable IPv4 fields if packet is not TCP and not UDP */ 6140 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 6141 /* Enable IPv4 fields if packet is TCP or UDP */ 6142 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 6143 /* Enable IPv6 fields if packet is not TCP and not UDP */ 6144 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 6145 /* Enable IPv6 fields if packet is TCP or UDP */ 6146 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 6147 /* Enable TCP/UDP header fields if packet is IPv4 */ 6148 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 6149 /* Enable TCP/UDP header fields if packet is IPv6 */ 6150 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 6151 }; 6152 6153 /* reg_recr2_outer_header_enables 6154 * Bit mask where each bit enables a specific layer to be included in 6155 * the hash calculation. 6156 * Access: RW 6157 */ 6158 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 6159 6160 enum { 6161 /* IPv4 Source IP */ 6162 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 6163 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 6164 /* IPv4 Destination IP */ 6165 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 6166 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 6167 /* IP Protocol */ 6168 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 6169 /* IPv6 Source IP */ 6170 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 6171 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 6172 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 6173 /* IPv6 Destination IP */ 6174 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 6175 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 6176 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 6177 /* IPv6 Next Header */ 6178 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 6179 /* IPv6 Flow Label */ 6180 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 6181 /* TCP/UDP Source Port */ 6182 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 6183 /* TCP/UDP Destination Port */ 6184 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 6185 }; 6186 6187 /* reg_recr2_outer_header_fields_enable 6188 * Packet fields to enable for ECMP hash subject to outer_header_enable. 6189 * Access: RW 6190 */ 6191 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 6192 6193 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 6194 { 6195 int i; 6196 6197 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 6198 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6199 true); 6200 } 6201 6202 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 6203 { 6204 int i; 6205 6206 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 6207 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6208 true); 6209 } 6210 6211 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 6212 { 6213 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 6214 6215 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6216 6217 i = MLXSW_REG_RECR2_IPV6_SIP8; 6218 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 6219 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6220 true); 6221 } 6222 6223 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 6224 { 6225 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 6226 6227 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6228 6229 i = MLXSW_REG_RECR2_IPV6_DIP8; 6230 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 6231 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6232 true); 6233 } 6234 6235 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 6236 { 6237 MLXSW_REG_ZERO(recr2, payload); 6238 mlxsw_reg_recr2_pp_set(payload, false); 6239 mlxsw_reg_recr2_sh_set(payload, true); 6240 mlxsw_reg_recr2_seed_set(payload, seed); 6241 } 6242 6243 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 6244 * -------------------------------------------------------------- 6245 * The RMFT_V2 register is used to configure and query the multicast table. 6246 */ 6247 #define MLXSW_REG_RMFT2_ID 0x8027 6248 #define MLXSW_REG_RMFT2_LEN 0x174 6249 6250 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 6251 6252 /* reg_rmft2_v 6253 * Valid 6254 * Access: RW 6255 */ 6256 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 6257 6258 enum mlxsw_reg_rmft2_type { 6259 MLXSW_REG_RMFT2_TYPE_IPV4, 6260 MLXSW_REG_RMFT2_TYPE_IPV6 6261 }; 6262 6263 /* reg_rmft2_type 6264 * Access: Index 6265 */ 6266 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 6267 6268 enum mlxsw_sp_reg_rmft2_op { 6269 /* For Write: 6270 * Write operation. Used to write a new entry to the table. All RW 6271 * fields are relevant for new entry. Activity bit is set for new 6272 * entries - Note write with v (Valid) 0 will delete the entry. 6273 * For Query: 6274 * Read operation 6275 */ 6276 MLXSW_REG_RMFT2_OP_READ_WRITE, 6277 }; 6278 6279 /* reg_rmft2_op 6280 * Operation. 6281 * Access: OP 6282 */ 6283 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 6284 6285 /* reg_rmft2_a 6286 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 6287 * entry. 6288 * Access: RO 6289 */ 6290 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 6291 6292 /* reg_rmft2_offset 6293 * Offset within the multicast forwarding table to write to. 6294 * Access: Index 6295 */ 6296 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 6297 6298 /* reg_rmft2_virtual_router 6299 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 6300 * Access: RW 6301 */ 6302 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 6303 6304 enum mlxsw_reg_rmft2_irif_mask { 6305 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 6306 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 6307 }; 6308 6309 /* reg_rmft2_irif_mask 6310 * Ingress RIF mask. 6311 * Access: RW 6312 */ 6313 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 6314 6315 /* reg_rmft2_irif 6316 * Ingress RIF index. 6317 * Access: RW 6318 */ 6319 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 6320 6321 /* reg_rmft2_dip{4,6} 6322 * Destination IPv4/6 address 6323 * Access: RW 6324 */ 6325 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 6326 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 6327 6328 /* reg_rmft2_dip{4,6}_mask 6329 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6330 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6331 * Access: RW 6332 */ 6333 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 6334 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 6335 6336 /* reg_rmft2_sip{4,6} 6337 * Source IPv4/6 address 6338 * Access: RW 6339 */ 6340 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 6341 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 6342 6343 /* reg_rmft2_sip{4,6}_mask 6344 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6345 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6346 * Access: RW 6347 */ 6348 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 6349 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 6350 6351 /* reg_rmft2_flexible_action_set 6352 * ACL action set. The only supported action types in this field and in any 6353 * action-set pointed from here are as follows: 6354 * 00h: ACTION_NULL 6355 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 6356 * 03h: ACTION_TRAP 6357 * 06h: ACTION_QOS 6358 * 08h: ACTION_POLICING_MONITORING 6359 * 10h: ACTION_ROUTER_MC 6360 * Access: RW 6361 */ 6362 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 6363 MLXSW_REG_FLEX_ACTION_SET_LEN); 6364 6365 static inline void 6366 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 6367 u16 virtual_router, 6368 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6369 const char *flex_action_set) 6370 { 6371 MLXSW_REG_ZERO(rmft2, payload); 6372 mlxsw_reg_rmft2_v_set(payload, v); 6373 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 6374 mlxsw_reg_rmft2_offset_set(payload, offset); 6375 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 6376 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 6377 mlxsw_reg_rmft2_irif_set(payload, irif); 6378 if (flex_action_set) 6379 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 6380 flex_action_set); 6381 } 6382 6383 static inline void 6384 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 6385 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6386 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 6387 const char *flexible_action_set) 6388 { 6389 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 6390 irif_mask, irif, flexible_action_set); 6391 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 6392 mlxsw_reg_rmft2_dip4_set(payload, dip4); 6393 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 6394 mlxsw_reg_rmft2_sip4_set(payload, sip4); 6395 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 6396 } 6397 6398 static inline void 6399 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 6400 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6401 struct in6_addr dip6, struct in6_addr dip6_mask, 6402 struct in6_addr sip6, struct in6_addr sip6_mask, 6403 const char *flexible_action_set) 6404 { 6405 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 6406 irif_mask, irif, flexible_action_set); 6407 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 6408 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 6409 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 6410 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 6411 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 6412 } 6413 6414 /* MFCR - Management Fan Control Register 6415 * -------------------------------------- 6416 * This register controls the settings of the Fan Speed PWM mechanism. 6417 */ 6418 #define MLXSW_REG_MFCR_ID 0x9001 6419 #define MLXSW_REG_MFCR_LEN 0x08 6420 6421 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 6422 6423 enum mlxsw_reg_mfcr_pwm_frequency { 6424 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 6425 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 6426 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 6427 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 6428 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 6429 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 6430 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 6431 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 6432 }; 6433 6434 /* reg_mfcr_pwm_frequency 6435 * Controls the frequency of the PWM signal. 6436 * Access: RW 6437 */ 6438 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 6439 6440 #define MLXSW_MFCR_TACHOS_MAX 10 6441 6442 /* reg_mfcr_tacho_active 6443 * Indicates which of the tachometer is active (bit per tachometer). 6444 * Access: RO 6445 */ 6446 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 6447 6448 #define MLXSW_MFCR_PWMS_MAX 5 6449 6450 /* reg_mfcr_pwm_active 6451 * Indicates which of the PWM control is active (bit per PWM). 6452 * Access: RO 6453 */ 6454 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 6455 6456 static inline void 6457 mlxsw_reg_mfcr_pack(char *payload, 6458 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 6459 { 6460 MLXSW_REG_ZERO(mfcr, payload); 6461 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 6462 } 6463 6464 static inline void 6465 mlxsw_reg_mfcr_unpack(char *payload, 6466 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 6467 u16 *p_tacho_active, u8 *p_pwm_active) 6468 { 6469 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 6470 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 6471 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 6472 } 6473 6474 /* MFSC - Management Fan Speed Control Register 6475 * -------------------------------------------- 6476 * This register controls the settings of the Fan Speed PWM mechanism. 6477 */ 6478 #define MLXSW_REG_MFSC_ID 0x9002 6479 #define MLXSW_REG_MFSC_LEN 0x08 6480 6481 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 6482 6483 /* reg_mfsc_pwm 6484 * Fan pwm to control / monitor. 6485 * Access: Index 6486 */ 6487 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 6488 6489 /* reg_mfsc_pwm_duty_cycle 6490 * Controls the duty cycle of the PWM. Value range from 0..255 to 6491 * represent duty cycle of 0%...100%. 6492 * Access: RW 6493 */ 6494 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 6495 6496 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 6497 u8 pwm_duty_cycle) 6498 { 6499 MLXSW_REG_ZERO(mfsc, payload); 6500 mlxsw_reg_mfsc_pwm_set(payload, pwm); 6501 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 6502 } 6503 6504 /* MFSM - Management Fan Speed Measurement 6505 * --------------------------------------- 6506 * This register controls the settings of the Tacho measurements and 6507 * enables reading the Tachometer measurements. 6508 */ 6509 #define MLXSW_REG_MFSM_ID 0x9003 6510 #define MLXSW_REG_MFSM_LEN 0x08 6511 6512 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 6513 6514 /* reg_mfsm_tacho 6515 * Fan tachometer index. 6516 * Access: Index 6517 */ 6518 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 6519 6520 /* reg_mfsm_rpm 6521 * Fan speed (round per minute). 6522 * Access: RO 6523 */ 6524 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 6525 6526 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 6527 { 6528 MLXSW_REG_ZERO(mfsm, payload); 6529 mlxsw_reg_mfsm_tacho_set(payload, tacho); 6530 } 6531 6532 /* MFSL - Management Fan Speed Limit Register 6533 * ------------------------------------------ 6534 * The Fan Speed Limit register is used to configure the fan speed 6535 * event / interrupt notification mechanism. Fan speed threshold are 6536 * defined for both under-speed and over-speed. 6537 */ 6538 #define MLXSW_REG_MFSL_ID 0x9004 6539 #define MLXSW_REG_MFSL_LEN 0x0C 6540 6541 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 6542 6543 /* reg_mfsl_tacho 6544 * Fan tachometer index. 6545 * Access: Index 6546 */ 6547 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 6548 6549 /* reg_mfsl_tach_min 6550 * Tachometer minimum value (minimum RPM). 6551 * Access: RW 6552 */ 6553 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 6554 6555 /* reg_mfsl_tach_max 6556 * Tachometer maximum value (maximum RPM). 6557 * Access: RW 6558 */ 6559 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 6560 6561 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 6562 u16 tach_min, u16 tach_max) 6563 { 6564 MLXSW_REG_ZERO(mfsl, payload); 6565 mlxsw_reg_mfsl_tacho_set(payload, tacho); 6566 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 6567 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 6568 } 6569 6570 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 6571 u16 *p_tach_min, u16 *p_tach_max) 6572 { 6573 if (p_tach_min) 6574 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 6575 6576 if (p_tach_max) 6577 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 6578 } 6579 6580 /* MTCAP - Management Temperature Capabilities 6581 * ------------------------------------------- 6582 * This register exposes the capabilities of the device and 6583 * system temperature sensing. 6584 */ 6585 #define MLXSW_REG_MTCAP_ID 0x9009 6586 #define MLXSW_REG_MTCAP_LEN 0x08 6587 6588 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 6589 6590 /* reg_mtcap_sensor_count 6591 * Number of sensors supported by the device. 6592 * This includes the QSFP module sensors (if exists in the QSFP module). 6593 * Access: RO 6594 */ 6595 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 6596 6597 /* MTMP - Management Temperature 6598 * ----------------------------- 6599 * This register controls the settings of the temperature measurements 6600 * and enables reading the temperature measurements. Note that temperature 6601 * is in 0.125 degrees Celsius. 6602 */ 6603 #define MLXSW_REG_MTMP_ID 0x900A 6604 #define MLXSW_REG_MTMP_LEN 0x20 6605 6606 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 6607 6608 /* reg_mtmp_sensor_index 6609 * Sensors index to access. 6610 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 6611 * (module 0 is mapped to sensor_index 64). 6612 * Access: Index 6613 */ 6614 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 6615 6616 /* Convert to milli degrees Celsius */ 6617 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 6618 6619 /* reg_mtmp_temperature 6620 * Temperature reading from the sensor. Reading is in 0.125 Celsius 6621 * degrees units. 6622 * Access: RO 6623 */ 6624 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 6625 6626 /* reg_mtmp_mte 6627 * Max Temperature Enable - enables measuring the max temperature on a sensor. 6628 * Access: RW 6629 */ 6630 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 6631 6632 /* reg_mtmp_mtr 6633 * Max Temperature Reset - clears the value of the max temperature register. 6634 * Access: WO 6635 */ 6636 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 6637 6638 /* reg_mtmp_max_temperature 6639 * The highest measured temperature from the sensor. 6640 * When the bit mte is cleared, the field max_temperature is reserved. 6641 * Access: RO 6642 */ 6643 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 6644 6645 /* reg_mtmp_tee 6646 * Temperature Event Enable. 6647 * 0 - Do not generate event 6648 * 1 - Generate event 6649 * 2 - Generate single event 6650 * Access: RW 6651 */ 6652 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 6653 6654 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 6655 6656 /* reg_mtmp_temperature_threshold_hi 6657 * High threshold for Temperature Warning Event. In 0.125 Celsius. 6658 * Access: RW 6659 */ 6660 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 6661 6662 /* reg_mtmp_temperature_threshold_lo 6663 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 6664 * Access: RW 6665 */ 6666 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 6667 6668 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 6669 6670 /* reg_mtmp_sensor_name 6671 * Sensor Name 6672 * Access: RO 6673 */ 6674 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 6675 6676 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 6677 bool max_temp_enable, 6678 bool max_temp_reset) 6679 { 6680 MLXSW_REG_ZERO(mtmp, payload); 6681 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 6682 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 6683 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 6684 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 6685 MLXSW_REG_MTMP_THRESH_HI); 6686 } 6687 6688 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 6689 unsigned int *p_max_temp, 6690 char *sensor_name) 6691 { 6692 u16 temp; 6693 6694 if (p_temp) { 6695 temp = mlxsw_reg_mtmp_temperature_get(payload); 6696 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6697 } 6698 if (p_max_temp) { 6699 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 6700 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6701 } 6702 if (sensor_name) 6703 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 6704 } 6705 6706 /* MCIA - Management Cable Info Access 6707 * ----------------------------------- 6708 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 6709 */ 6710 6711 #define MLXSW_REG_MCIA_ID 0x9014 6712 #define MLXSW_REG_MCIA_LEN 0x40 6713 6714 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 6715 6716 /* reg_mcia_l 6717 * Lock bit. Setting this bit will lock the access to the specific 6718 * cable. Used for updating a full page in a cable EPROM. Any access 6719 * other then subsequence writes will fail while the port is locked. 6720 * Access: RW 6721 */ 6722 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 6723 6724 /* reg_mcia_module 6725 * Module number. 6726 * Access: Index 6727 */ 6728 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 6729 6730 /* reg_mcia_status 6731 * Module status. 6732 * Access: RO 6733 */ 6734 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 6735 6736 /* reg_mcia_i2c_device_address 6737 * I2C device address. 6738 * Access: RW 6739 */ 6740 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 6741 6742 /* reg_mcia_page_number 6743 * Page number. 6744 * Access: RW 6745 */ 6746 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 6747 6748 /* reg_mcia_device_address 6749 * Device address. 6750 * Access: RW 6751 */ 6752 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 6753 6754 /* reg_mcia_size 6755 * Number of bytes to read/write (up to 48 bytes). 6756 * Access: RW 6757 */ 6758 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 6759 6760 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 6761 6762 /* reg_mcia_eeprom 6763 * Bytes to read/write. 6764 * Access: RW 6765 */ 6766 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 6767 6768 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 6769 u8 page_number, u16 device_addr, 6770 u8 size, u8 i2c_device_addr) 6771 { 6772 MLXSW_REG_ZERO(mcia, payload); 6773 mlxsw_reg_mcia_module_set(payload, module); 6774 mlxsw_reg_mcia_l_set(payload, lock); 6775 mlxsw_reg_mcia_page_number_set(payload, page_number); 6776 mlxsw_reg_mcia_device_address_set(payload, device_addr); 6777 mlxsw_reg_mcia_size_set(payload, size); 6778 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 6779 } 6780 6781 /* MPAT - Monitoring Port Analyzer Table 6782 * ------------------------------------- 6783 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 6784 * For an enabled analyzer, all fields except e (enable) cannot be modified. 6785 */ 6786 #define MLXSW_REG_MPAT_ID 0x901A 6787 #define MLXSW_REG_MPAT_LEN 0x78 6788 6789 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 6790 6791 /* reg_mpat_pa_id 6792 * Port Analyzer ID. 6793 * Access: Index 6794 */ 6795 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 6796 6797 /* reg_mpat_system_port 6798 * A unique port identifier for the final destination of the packet. 6799 * Access: RW 6800 */ 6801 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 6802 6803 /* reg_mpat_e 6804 * Enable. Indicating the Port Analyzer is enabled. 6805 * Access: RW 6806 */ 6807 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 6808 6809 /* reg_mpat_qos 6810 * Quality Of Service Mode. 6811 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 6812 * PCP, DEI, DSCP or VL) are configured. 6813 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 6814 * same as in the original packet that has triggered the mirroring. For 6815 * SPAN also the pcp,dei are maintained. 6816 * Access: RW 6817 */ 6818 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 6819 6820 /* reg_mpat_be 6821 * Best effort mode. Indicates mirroring traffic should not cause packet 6822 * drop or back pressure, but will discard the mirrored packets. Mirrored 6823 * packets will be forwarded on a best effort manner. 6824 * 0: Do not discard mirrored packets 6825 * 1: Discard mirrored packets if causing congestion 6826 * Access: RW 6827 */ 6828 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 6829 6830 enum mlxsw_reg_mpat_span_type { 6831 /* Local SPAN Ethernet. 6832 * The original packet is not encapsulated. 6833 */ 6834 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 6835 6836 /* Remote SPAN Ethernet VLAN. 6837 * The packet is forwarded to the monitoring port on the monitoring 6838 * VLAN. 6839 */ 6840 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 6841 6842 /* Encapsulated Remote SPAN Ethernet L3 GRE. 6843 * The packet is encapsulated with GRE header. 6844 */ 6845 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 6846 }; 6847 6848 /* reg_mpat_span_type 6849 * SPAN type. 6850 * Access: RW 6851 */ 6852 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 6853 6854 /* Remote SPAN - Ethernet VLAN 6855 * - - - - - - - - - - - - - - 6856 */ 6857 6858 /* reg_mpat_eth_rspan_vid 6859 * Encapsulation header VLAN ID. 6860 * Access: RW 6861 */ 6862 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 6863 6864 /* Encapsulated Remote SPAN - Ethernet L2 6865 * - - - - - - - - - - - - - - - - - - - 6866 */ 6867 6868 enum mlxsw_reg_mpat_eth_rspan_version { 6869 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 6870 }; 6871 6872 /* reg_mpat_eth_rspan_version 6873 * RSPAN mirror header version. 6874 * Access: RW 6875 */ 6876 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 6877 6878 /* reg_mpat_eth_rspan_mac 6879 * Destination MAC address. 6880 * Access: RW 6881 */ 6882 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 6883 6884 /* reg_mpat_eth_rspan_tp 6885 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 6886 * Access: RW 6887 */ 6888 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 6889 6890 /* Encapsulated Remote SPAN - Ethernet L3 6891 * - - - - - - - - - - - - - - - - - - - 6892 */ 6893 6894 enum mlxsw_reg_mpat_eth_rspan_protocol { 6895 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 6896 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 6897 }; 6898 6899 /* reg_mpat_eth_rspan_protocol 6900 * SPAN encapsulation protocol. 6901 * Access: RW 6902 */ 6903 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 6904 6905 /* reg_mpat_eth_rspan_ttl 6906 * Encapsulation header Time-to-Live/HopLimit. 6907 * Access: RW 6908 */ 6909 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 6910 6911 /* reg_mpat_eth_rspan_smac 6912 * Source MAC address 6913 * Access: RW 6914 */ 6915 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 6916 6917 /* reg_mpat_eth_rspan_dip* 6918 * Destination IP address. The IP version is configured by protocol. 6919 * Access: RW 6920 */ 6921 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 6922 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 6923 6924 /* reg_mpat_eth_rspan_sip* 6925 * Source IP address. The IP version is configured by protocol. 6926 * Access: RW 6927 */ 6928 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 6929 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 6930 6931 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 6932 u16 system_port, bool e, 6933 enum mlxsw_reg_mpat_span_type span_type) 6934 { 6935 MLXSW_REG_ZERO(mpat, payload); 6936 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 6937 mlxsw_reg_mpat_system_port_set(payload, system_port); 6938 mlxsw_reg_mpat_e_set(payload, e); 6939 mlxsw_reg_mpat_qos_set(payload, 1); 6940 mlxsw_reg_mpat_be_set(payload, 1); 6941 mlxsw_reg_mpat_span_type_set(payload, span_type); 6942 } 6943 6944 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 6945 { 6946 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 6947 } 6948 6949 static inline void 6950 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 6951 enum mlxsw_reg_mpat_eth_rspan_version version, 6952 const char *mac, 6953 bool tp) 6954 { 6955 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 6956 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 6957 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 6958 } 6959 6960 static inline void 6961 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 6962 const char *smac, 6963 u32 sip, u32 dip) 6964 { 6965 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 6966 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 6967 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 6968 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 6969 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 6970 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 6971 } 6972 6973 static inline void 6974 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 6975 const char *smac, 6976 struct in6_addr sip, struct in6_addr dip) 6977 { 6978 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 6979 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 6980 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 6981 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 6982 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 6983 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 6984 } 6985 6986 /* MPAR - Monitoring Port Analyzer Register 6987 * ---------------------------------------- 6988 * MPAR register is used to query and configure the port analyzer port mirroring 6989 * properties. 6990 */ 6991 #define MLXSW_REG_MPAR_ID 0x901B 6992 #define MLXSW_REG_MPAR_LEN 0x08 6993 6994 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 6995 6996 /* reg_mpar_local_port 6997 * The local port to mirror the packets from. 6998 * Access: Index 6999 */ 7000 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 7001 7002 enum mlxsw_reg_mpar_i_e { 7003 MLXSW_REG_MPAR_TYPE_EGRESS, 7004 MLXSW_REG_MPAR_TYPE_INGRESS, 7005 }; 7006 7007 /* reg_mpar_i_e 7008 * Ingress/Egress 7009 * Access: Index 7010 */ 7011 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 7012 7013 /* reg_mpar_enable 7014 * Enable mirroring 7015 * By default, port mirroring is disabled for all ports. 7016 * Access: RW 7017 */ 7018 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 7019 7020 /* reg_mpar_pa_id 7021 * Port Analyzer ID. 7022 * Access: RW 7023 */ 7024 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 7025 7026 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 7027 enum mlxsw_reg_mpar_i_e i_e, 7028 bool enable, u8 pa_id) 7029 { 7030 MLXSW_REG_ZERO(mpar, payload); 7031 mlxsw_reg_mpar_local_port_set(payload, local_port); 7032 mlxsw_reg_mpar_enable_set(payload, enable); 7033 mlxsw_reg_mpar_i_e_set(payload, i_e); 7034 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 7035 } 7036 7037 /* MRSR - Management Reset and Shutdown Register 7038 * --------------------------------------------- 7039 * MRSR register is used to reset or shutdown the switch or 7040 * the entire system (when applicable). 7041 */ 7042 #define MLXSW_REG_MRSR_ID 0x9023 7043 #define MLXSW_REG_MRSR_LEN 0x08 7044 7045 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 7046 7047 /* reg_mrsr_command 7048 * Reset/shutdown command 7049 * 0 - do nothing 7050 * 1 - software reset 7051 * Access: WO 7052 */ 7053 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 7054 7055 static inline void mlxsw_reg_mrsr_pack(char *payload) 7056 { 7057 MLXSW_REG_ZERO(mrsr, payload); 7058 mlxsw_reg_mrsr_command_set(payload, 1); 7059 } 7060 7061 /* MLCR - Management LED Control Register 7062 * -------------------------------------- 7063 * Controls the system LEDs. 7064 */ 7065 #define MLXSW_REG_MLCR_ID 0x902B 7066 #define MLXSW_REG_MLCR_LEN 0x0C 7067 7068 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 7069 7070 /* reg_mlcr_local_port 7071 * Local port number. 7072 * Access: RW 7073 */ 7074 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 7075 7076 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 7077 7078 /* reg_mlcr_beacon_duration 7079 * Duration of the beacon to be active, in seconds. 7080 * 0x0 - Will turn off the beacon. 7081 * 0xFFFF - Will turn on the beacon until explicitly turned off. 7082 * Access: RW 7083 */ 7084 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 7085 7086 /* reg_mlcr_beacon_remain 7087 * Remaining duration of the beacon, in seconds. 7088 * 0xFFFF indicates an infinite amount of time. 7089 * Access: RO 7090 */ 7091 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 7092 7093 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 7094 bool active) 7095 { 7096 MLXSW_REG_ZERO(mlcr, payload); 7097 mlxsw_reg_mlcr_local_port_set(payload, local_port); 7098 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 7099 MLXSW_REG_MLCR_DURATION_MAX : 0); 7100 } 7101 7102 /* MCQI - Management Component Query Information 7103 * --------------------------------------------- 7104 * This register allows querying information about firmware components. 7105 */ 7106 #define MLXSW_REG_MCQI_ID 0x9061 7107 #define MLXSW_REG_MCQI_BASE_LEN 0x18 7108 #define MLXSW_REG_MCQI_CAP_LEN 0x14 7109 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 7110 7111 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 7112 7113 /* reg_mcqi_component_index 7114 * Index of the accessed component. 7115 * Access: Index 7116 */ 7117 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 7118 7119 enum mlxfw_reg_mcqi_info_type { 7120 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 7121 }; 7122 7123 /* reg_mcqi_info_type 7124 * Component properties set. 7125 * Access: RW 7126 */ 7127 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 7128 7129 /* reg_mcqi_offset 7130 * The requested/returned data offset from the section start, given in bytes. 7131 * Must be DWORD aligned. 7132 * Access: RW 7133 */ 7134 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 7135 7136 /* reg_mcqi_data_size 7137 * The requested/returned data size, given in bytes. If data_size is not DWORD 7138 * aligned, the last bytes are zero padded. 7139 * Access: RW 7140 */ 7141 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 7142 7143 /* reg_mcqi_cap_max_component_size 7144 * Maximum size for this component, given in bytes. 7145 * Access: RO 7146 */ 7147 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 7148 7149 /* reg_mcqi_cap_log_mcda_word_size 7150 * Log 2 of the access word size in bytes. Read and write access must be aligned 7151 * to the word size. Write access must be done for an integer number of words. 7152 * Access: RO 7153 */ 7154 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 7155 7156 /* reg_mcqi_cap_mcda_max_write_size 7157 * Maximal write size for MCDA register 7158 * Access: RO 7159 */ 7160 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 7161 7162 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 7163 { 7164 MLXSW_REG_ZERO(mcqi, payload); 7165 mlxsw_reg_mcqi_component_index_set(payload, component_index); 7166 mlxsw_reg_mcqi_info_type_set(payload, 7167 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 7168 mlxsw_reg_mcqi_offset_set(payload, 0); 7169 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 7170 } 7171 7172 static inline void mlxsw_reg_mcqi_unpack(char *payload, 7173 u32 *p_cap_max_component_size, 7174 u8 *p_cap_log_mcda_word_size, 7175 u16 *p_cap_mcda_max_write_size) 7176 { 7177 *p_cap_max_component_size = 7178 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 7179 *p_cap_log_mcda_word_size = 7180 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 7181 *p_cap_mcda_max_write_size = 7182 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 7183 } 7184 7185 /* MCC - Management Component Control 7186 * ---------------------------------- 7187 * Controls the firmware component and updates the FSM. 7188 */ 7189 #define MLXSW_REG_MCC_ID 0x9062 7190 #define MLXSW_REG_MCC_LEN 0x1C 7191 7192 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 7193 7194 enum mlxsw_reg_mcc_instruction { 7195 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 7196 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 7197 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 7198 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 7199 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 7200 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 7201 }; 7202 7203 /* reg_mcc_instruction 7204 * Command to be executed by the FSM. 7205 * Applicable for write operation only. 7206 * Access: RW 7207 */ 7208 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 7209 7210 /* reg_mcc_component_index 7211 * Index of the accessed component. Applicable only for commands that 7212 * refer to components. Otherwise, this field is reserved. 7213 * Access: Index 7214 */ 7215 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 7216 7217 /* reg_mcc_update_handle 7218 * Token representing the current flow executed by the FSM. 7219 * Access: WO 7220 */ 7221 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 7222 7223 /* reg_mcc_error_code 7224 * Indicates the successful completion of the instruction, or the reason it 7225 * failed 7226 * Access: RO 7227 */ 7228 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 7229 7230 /* reg_mcc_control_state 7231 * Current FSM state 7232 * Access: RO 7233 */ 7234 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 7235 7236 /* reg_mcc_component_size 7237 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 7238 * the size may shorten the update time. Value 0x0 means that size is 7239 * unspecified. 7240 * Access: WO 7241 */ 7242 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 7243 7244 static inline void mlxsw_reg_mcc_pack(char *payload, 7245 enum mlxsw_reg_mcc_instruction instr, 7246 u16 component_index, u32 update_handle, 7247 u32 component_size) 7248 { 7249 MLXSW_REG_ZERO(mcc, payload); 7250 mlxsw_reg_mcc_instruction_set(payload, instr); 7251 mlxsw_reg_mcc_component_index_set(payload, component_index); 7252 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 7253 mlxsw_reg_mcc_component_size_set(payload, component_size); 7254 } 7255 7256 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 7257 u8 *p_error_code, u8 *p_control_state) 7258 { 7259 if (p_update_handle) 7260 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 7261 if (p_error_code) 7262 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 7263 if (p_control_state) 7264 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 7265 } 7266 7267 /* MCDA - Management Component Data Access 7268 * --------------------------------------- 7269 * This register allows reading and writing a firmware component. 7270 */ 7271 #define MLXSW_REG_MCDA_ID 0x9063 7272 #define MLXSW_REG_MCDA_BASE_LEN 0x10 7273 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 7274 #define MLXSW_REG_MCDA_LEN \ 7275 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 7276 7277 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 7278 7279 /* reg_mcda_update_handle 7280 * Token representing the current flow executed by the FSM. 7281 * Access: RW 7282 */ 7283 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 7284 7285 /* reg_mcda_offset 7286 * Offset of accessed address relative to component start. Accesses must be in 7287 * accordance to log_mcda_word_size in MCQI reg. 7288 * Access: RW 7289 */ 7290 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 7291 7292 /* reg_mcda_size 7293 * Size of the data accessed, given in bytes. 7294 * Access: RW 7295 */ 7296 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 7297 7298 /* reg_mcda_data 7299 * Data block accessed. 7300 * Access: RW 7301 */ 7302 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 7303 7304 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 7305 u32 offset, u16 size, u8 *data) 7306 { 7307 int i; 7308 7309 MLXSW_REG_ZERO(mcda, payload); 7310 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 7311 mlxsw_reg_mcda_offset_set(payload, offset); 7312 mlxsw_reg_mcda_size_set(payload, size); 7313 7314 for (i = 0; i < size / 4; i++) 7315 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 7316 } 7317 7318 /* MPSC - Monitoring Packet Sampling Configuration Register 7319 * -------------------------------------------------------- 7320 * MPSC Register is used to configure the Packet Sampling mechanism. 7321 */ 7322 #define MLXSW_REG_MPSC_ID 0x9080 7323 #define MLXSW_REG_MPSC_LEN 0x1C 7324 7325 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 7326 7327 /* reg_mpsc_local_port 7328 * Local port number 7329 * Not supported for CPU port 7330 * Access: Index 7331 */ 7332 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 7333 7334 /* reg_mpsc_e 7335 * Enable sampling on port local_port 7336 * Access: RW 7337 */ 7338 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 7339 7340 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 7341 7342 /* reg_mpsc_rate 7343 * Sampling rate = 1 out of rate packets (with randomization around 7344 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 7345 * Access: RW 7346 */ 7347 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 7348 7349 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 7350 u32 rate) 7351 { 7352 MLXSW_REG_ZERO(mpsc, payload); 7353 mlxsw_reg_mpsc_local_port_set(payload, local_port); 7354 mlxsw_reg_mpsc_e_set(payload, e); 7355 mlxsw_reg_mpsc_rate_set(payload, rate); 7356 } 7357 7358 /* MGPC - Monitoring General Purpose Counter Set Register 7359 * The MGPC register retrieves and sets the General Purpose Counter Set. 7360 */ 7361 #define MLXSW_REG_MGPC_ID 0x9081 7362 #define MLXSW_REG_MGPC_LEN 0x18 7363 7364 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 7365 7366 /* reg_mgpc_counter_set_type 7367 * Counter set type. 7368 * Access: OP 7369 */ 7370 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 7371 7372 /* reg_mgpc_counter_index 7373 * Counter index. 7374 * Access: Index 7375 */ 7376 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 7377 7378 enum mlxsw_reg_mgpc_opcode { 7379 /* Nop */ 7380 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 7381 /* Clear counters */ 7382 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 7383 }; 7384 7385 /* reg_mgpc_opcode 7386 * Opcode. 7387 * Access: OP 7388 */ 7389 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 7390 7391 /* reg_mgpc_byte_counter 7392 * Byte counter value. 7393 * Access: RW 7394 */ 7395 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 7396 7397 /* reg_mgpc_packet_counter 7398 * Packet counter value. 7399 * Access: RW 7400 */ 7401 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 7402 7403 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 7404 enum mlxsw_reg_mgpc_opcode opcode, 7405 enum mlxsw_reg_flow_counter_set_type set_type) 7406 { 7407 MLXSW_REG_ZERO(mgpc, payload); 7408 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 7409 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 7410 mlxsw_reg_mgpc_opcode_set(payload, opcode); 7411 } 7412 7413 /* TIGCR - Tunneling IPinIP General Configuration Register 7414 * ------------------------------------------------------- 7415 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 7416 */ 7417 #define MLXSW_REG_TIGCR_ID 0xA801 7418 #define MLXSW_REG_TIGCR_LEN 0x10 7419 7420 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 7421 7422 /* reg_tigcr_ipip_ttlc 7423 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 7424 * header. 7425 * Access: RW 7426 */ 7427 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 7428 7429 /* reg_tigcr_ipip_ttl_uc 7430 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 7431 * reg_tigcr_ipip_ttlc is unset. 7432 * Access: RW 7433 */ 7434 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 7435 7436 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 7437 { 7438 MLXSW_REG_ZERO(tigcr, payload); 7439 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 7440 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 7441 } 7442 7443 /* SBPR - Shared Buffer Pools Register 7444 * ----------------------------------- 7445 * The SBPR configures and retrieves the shared buffer pools and configuration. 7446 */ 7447 #define MLXSW_REG_SBPR_ID 0xB001 7448 #define MLXSW_REG_SBPR_LEN 0x14 7449 7450 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 7451 7452 /* shared direstion enum for SBPR, SBCM, SBPM */ 7453 enum mlxsw_reg_sbxx_dir { 7454 MLXSW_REG_SBXX_DIR_INGRESS, 7455 MLXSW_REG_SBXX_DIR_EGRESS, 7456 }; 7457 7458 /* reg_sbpr_dir 7459 * Direction. 7460 * Access: Index 7461 */ 7462 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 7463 7464 /* reg_sbpr_pool 7465 * Pool index. 7466 * Access: Index 7467 */ 7468 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 7469 7470 /* reg_sbpr_size 7471 * Pool size in buffer cells. 7472 * Access: RW 7473 */ 7474 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 7475 7476 enum mlxsw_reg_sbpr_mode { 7477 MLXSW_REG_SBPR_MODE_STATIC, 7478 MLXSW_REG_SBPR_MODE_DYNAMIC, 7479 }; 7480 7481 /* reg_sbpr_mode 7482 * Pool quota calculation mode. 7483 * Access: RW 7484 */ 7485 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 7486 7487 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 7488 enum mlxsw_reg_sbxx_dir dir, 7489 enum mlxsw_reg_sbpr_mode mode, u32 size) 7490 { 7491 MLXSW_REG_ZERO(sbpr, payload); 7492 mlxsw_reg_sbpr_pool_set(payload, pool); 7493 mlxsw_reg_sbpr_dir_set(payload, dir); 7494 mlxsw_reg_sbpr_mode_set(payload, mode); 7495 mlxsw_reg_sbpr_size_set(payload, size); 7496 } 7497 7498 /* SBCM - Shared Buffer Class Management Register 7499 * ---------------------------------------------- 7500 * The SBCM register configures and retrieves the shared buffer allocation 7501 * and configuration according to Port-PG, including the binding to pool 7502 * and definition of the associated quota. 7503 */ 7504 #define MLXSW_REG_SBCM_ID 0xB002 7505 #define MLXSW_REG_SBCM_LEN 0x28 7506 7507 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 7508 7509 /* reg_sbcm_local_port 7510 * Local port number. 7511 * For Ingress: excludes CPU port and Router port 7512 * For Egress: excludes IP Router 7513 * Access: Index 7514 */ 7515 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 7516 7517 /* reg_sbcm_pg_buff 7518 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 7519 * For PG buffer: range is 0..cap_max_pg_buffers - 1 7520 * For traffic class: range is 0..cap_max_tclass - 1 7521 * Note that when traffic class is in MC aware mode then the traffic 7522 * classes which are MC aware cannot be configured. 7523 * Access: Index 7524 */ 7525 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 7526 7527 /* reg_sbcm_dir 7528 * Direction. 7529 * Access: Index 7530 */ 7531 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 7532 7533 /* reg_sbcm_min_buff 7534 * Minimum buffer size for the limiter, in cells. 7535 * Access: RW 7536 */ 7537 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 7538 7539 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 7540 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 7541 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 7542 7543 /* reg_sbcm_max_buff 7544 * When the pool associated to the port-pg/tclass is configured to 7545 * static, Maximum buffer size for the limiter configured in cells. 7546 * When the pool associated to the port-pg/tclass is configured to 7547 * dynamic, the max_buff holds the "alpha" parameter, supporting 7548 * the following values: 7549 * 0: 0 7550 * i: (1/128)*2^(i-1), for i=1..14 7551 * 0xFF: Infinity 7552 * Access: RW 7553 */ 7554 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 7555 7556 /* reg_sbcm_pool 7557 * Association of the port-priority to a pool. 7558 * Access: RW 7559 */ 7560 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 7561 7562 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 7563 enum mlxsw_reg_sbxx_dir dir, 7564 u32 min_buff, u32 max_buff, u8 pool) 7565 { 7566 MLXSW_REG_ZERO(sbcm, payload); 7567 mlxsw_reg_sbcm_local_port_set(payload, local_port); 7568 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 7569 mlxsw_reg_sbcm_dir_set(payload, dir); 7570 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 7571 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 7572 mlxsw_reg_sbcm_pool_set(payload, pool); 7573 } 7574 7575 /* SBPM - Shared Buffer Port Management Register 7576 * --------------------------------------------- 7577 * The SBPM register configures and retrieves the shared buffer allocation 7578 * and configuration according to Port-Pool, including the definition 7579 * of the associated quota. 7580 */ 7581 #define MLXSW_REG_SBPM_ID 0xB003 7582 #define MLXSW_REG_SBPM_LEN 0x28 7583 7584 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 7585 7586 /* reg_sbpm_local_port 7587 * Local port number. 7588 * For Ingress: excludes CPU port and Router port 7589 * For Egress: excludes IP Router 7590 * Access: Index 7591 */ 7592 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 7593 7594 /* reg_sbpm_pool 7595 * The pool associated to quota counting on the local_port. 7596 * Access: Index 7597 */ 7598 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 7599 7600 /* reg_sbpm_dir 7601 * Direction. 7602 * Access: Index 7603 */ 7604 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 7605 7606 /* reg_sbpm_buff_occupancy 7607 * Current buffer occupancy in cells. 7608 * Access: RO 7609 */ 7610 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 7611 7612 /* reg_sbpm_clr 7613 * Clear Max Buffer Occupancy 7614 * When this bit is set, max_buff_occupancy field is cleared (and a 7615 * new max value is tracked from the time the clear was performed). 7616 * Access: OP 7617 */ 7618 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 7619 7620 /* reg_sbpm_max_buff_occupancy 7621 * Maximum value of buffer occupancy in cells monitored. Cleared by 7622 * writing to the clr field. 7623 * Access: RO 7624 */ 7625 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 7626 7627 /* reg_sbpm_min_buff 7628 * Minimum buffer size for the limiter, in cells. 7629 * Access: RW 7630 */ 7631 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 7632 7633 /* reg_sbpm_max_buff 7634 * When the pool associated to the port-pg/tclass is configured to 7635 * static, Maximum buffer size for the limiter configured in cells. 7636 * When the pool associated to the port-pg/tclass is configured to 7637 * dynamic, the max_buff holds the "alpha" parameter, supporting 7638 * the following values: 7639 * 0: 0 7640 * i: (1/128)*2^(i-1), for i=1..14 7641 * 0xFF: Infinity 7642 * Access: RW 7643 */ 7644 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 7645 7646 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 7647 enum mlxsw_reg_sbxx_dir dir, bool clr, 7648 u32 min_buff, u32 max_buff) 7649 { 7650 MLXSW_REG_ZERO(sbpm, payload); 7651 mlxsw_reg_sbpm_local_port_set(payload, local_port); 7652 mlxsw_reg_sbpm_pool_set(payload, pool); 7653 mlxsw_reg_sbpm_dir_set(payload, dir); 7654 mlxsw_reg_sbpm_clr_set(payload, clr); 7655 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 7656 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 7657 } 7658 7659 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 7660 u32 *p_max_buff_occupancy) 7661 { 7662 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 7663 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 7664 } 7665 7666 /* SBMM - Shared Buffer Multicast Management Register 7667 * -------------------------------------------------- 7668 * The SBMM register configures and retrieves the shared buffer allocation 7669 * and configuration for MC packets according to Switch-Priority, including 7670 * the binding to pool and definition of the associated quota. 7671 */ 7672 #define MLXSW_REG_SBMM_ID 0xB004 7673 #define MLXSW_REG_SBMM_LEN 0x28 7674 7675 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 7676 7677 /* reg_sbmm_prio 7678 * Switch Priority. 7679 * Access: Index 7680 */ 7681 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 7682 7683 /* reg_sbmm_min_buff 7684 * Minimum buffer size for the limiter, in cells. 7685 * Access: RW 7686 */ 7687 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 7688 7689 /* reg_sbmm_max_buff 7690 * When the pool associated to the port-pg/tclass is configured to 7691 * static, Maximum buffer size for the limiter configured in cells. 7692 * When the pool associated to the port-pg/tclass is configured to 7693 * dynamic, the max_buff holds the "alpha" parameter, supporting 7694 * the following values: 7695 * 0: 0 7696 * i: (1/128)*2^(i-1), for i=1..14 7697 * 0xFF: Infinity 7698 * Access: RW 7699 */ 7700 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 7701 7702 /* reg_sbmm_pool 7703 * Association of the port-priority to a pool. 7704 * Access: RW 7705 */ 7706 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 7707 7708 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 7709 u32 max_buff, u8 pool) 7710 { 7711 MLXSW_REG_ZERO(sbmm, payload); 7712 mlxsw_reg_sbmm_prio_set(payload, prio); 7713 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 7714 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 7715 mlxsw_reg_sbmm_pool_set(payload, pool); 7716 } 7717 7718 /* SBSR - Shared Buffer Status Register 7719 * ------------------------------------ 7720 * The SBSR register retrieves the shared buffer occupancy according to 7721 * Port-Pool. Note that this register enables reading a large amount of data. 7722 * It is the user's responsibility to limit the amount of data to ensure the 7723 * response can match the maximum transfer unit. In case the response exceeds 7724 * the maximum transport unit, it will be truncated with no special notice. 7725 */ 7726 #define MLXSW_REG_SBSR_ID 0xB005 7727 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 7728 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 7729 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 7730 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 7731 MLXSW_REG_SBSR_REC_LEN * \ 7732 MLXSW_REG_SBSR_REC_MAX_COUNT) 7733 7734 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 7735 7736 /* reg_sbsr_clr 7737 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 7738 * field is cleared (and a new max value is tracked from the time the clear 7739 * was performed). 7740 * Access: OP 7741 */ 7742 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 7743 7744 /* reg_sbsr_ingress_port_mask 7745 * Bit vector for all ingress network ports. 7746 * Indicates which of the ports (for which the relevant bit is set) 7747 * are affected by the set operation. Configuration of any other port 7748 * does not change. 7749 * Access: Index 7750 */ 7751 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 7752 7753 /* reg_sbsr_pg_buff_mask 7754 * Bit vector for all switch priority groups. 7755 * Indicates which of the priorities (for which the relevant bit is set) 7756 * are affected by the set operation. Configuration of any other priority 7757 * does not change. 7758 * Range is 0..cap_max_pg_buffers - 1 7759 * Access: Index 7760 */ 7761 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 7762 7763 /* reg_sbsr_egress_port_mask 7764 * Bit vector for all egress network ports. 7765 * Indicates which of the ports (for which the relevant bit is set) 7766 * are affected by the set operation. Configuration of any other port 7767 * does not change. 7768 * Access: Index 7769 */ 7770 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 7771 7772 /* reg_sbsr_tclass_mask 7773 * Bit vector for all traffic classes. 7774 * Indicates which of the traffic classes (for which the relevant bit is 7775 * set) are affected by the set operation. Configuration of any other 7776 * traffic class does not change. 7777 * Range is 0..cap_max_tclass - 1 7778 * Access: Index 7779 */ 7780 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 7781 7782 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 7783 { 7784 MLXSW_REG_ZERO(sbsr, payload); 7785 mlxsw_reg_sbsr_clr_set(payload, clr); 7786 } 7787 7788 /* reg_sbsr_rec_buff_occupancy 7789 * Current buffer occupancy in cells. 7790 * Access: RO 7791 */ 7792 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7793 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 7794 7795 /* reg_sbsr_rec_max_buff_occupancy 7796 * Maximum value of buffer occupancy in cells monitored. Cleared by 7797 * writing to the clr field. 7798 * Access: RO 7799 */ 7800 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7801 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 7802 7803 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 7804 u32 *p_buff_occupancy, 7805 u32 *p_max_buff_occupancy) 7806 { 7807 *p_buff_occupancy = 7808 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 7809 *p_max_buff_occupancy = 7810 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 7811 } 7812 7813 /* SBIB - Shared Buffer Internal Buffer Register 7814 * --------------------------------------------- 7815 * The SBIB register configures per port buffers for internal use. The internal 7816 * buffers consume memory on the port buffers (note that the port buffers are 7817 * used also by PBMC). 7818 * 7819 * For Spectrum this is used for egress mirroring. 7820 */ 7821 #define MLXSW_REG_SBIB_ID 0xB006 7822 #define MLXSW_REG_SBIB_LEN 0x10 7823 7824 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 7825 7826 /* reg_sbib_local_port 7827 * Local port number 7828 * Not supported for CPU port and router port 7829 * Access: Index 7830 */ 7831 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 7832 7833 /* reg_sbib_buff_size 7834 * Units represented in cells 7835 * Allowed range is 0 to (cap_max_headroom_size - 1) 7836 * Default is 0 7837 * Access: RW 7838 */ 7839 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 7840 7841 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 7842 u32 buff_size) 7843 { 7844 MLXSW_REG_ZERO(sbib, payload); 7845 mlxsw_reg_sbib_local_port_set(payload, local_port); 7846 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 7847 } 7848 7849 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 7850 MLXSW_REG(sgcr), 7851 MLXSW_REG(spad), 7852 MLXSW_REG(smid), 7853 MLXSW_REG(sspr), 7854 MLXSW_REG(sfdat), 7855 MLXSW_REG(sfd), 7856 MLXSW_REG(sfn), 7857 MLXSW_REG(spms), 7858 MLXSW_REG(spvid), 7859 MLXSW_REG(spvm), 7860 MLXSW_REG(spaft), 7861 MLXSW_REG(sfgc), 7862 MLXSW_REG(sftr), 7863 MLXSW_REG(sfdf), 7864 MLXSW_REG(sldr), 7865 MLXSW_REG(slcr), 7866 MLXSW_REG(slcor), 7867 MLXSW_REG(spmlr), 7868 MLXSW_REG(svfa), 7869 MLXSW_REG(svpe), 7870 MLXSW_REG(sfmr), 7871 MLXSW_REG(spvmlr), 7872 MLXSW_REG(cwtp), 7873 MLXSW_REG(cwtpm), 7874 MLXSW_REG(ppbt), 7875 MLXSW_REG(pacl), 7876 MLXSW_REG(pagt), 7877 MLXSW_REG(ptar), 7878 MLXSW_REG(ppbs), 7879 MLXSW_REG(prcr), 7880 MLXSW_REG(pefa), 7881 MLXSW_REG(ptce2), 7882 MLXSW_REG(qpcr), 7883 MLXSW_REG(qtct), 7884 MLXSW_REG(qeec), 7885 MLXSW_REG(pmlp), 7886 MLXSW_REG(pmtu), 7887 MLXSW_REG(ptys), 7888 MLXSW_REG(ppad), 7889 MLXSW_REG(paos), 7890 MLXSW_REG(pfcc), 7891 MLXSW_REG(ppcnt), 7892 MLXSW_REG(plib), 7893 MLXSW_REG(pptb), 7894 MLXSW_REG(pbmc), 7895 MLXSW_REG(pspa), 7896 MLXSW_REG(htgt), 7897 MLXSW_REG(hpkt), 7898 MLXSW_REG(rgcr), 7899 MLXSW_REG(ritr), 7900 MLXSW_REG(rtar), 7901 MLXSW_REG(ratr), 7902 MLXSW_REG(rtdp), 7903 MLXSW_REG(rdpm), 7904 MLXSW_REG(ricnt), 7905 MLXSW_REG(rrcr), 7906 MLXSW_REG(ralta), 7907 MLXSW_REG(ralst), 7908 MLXSW_REG(raltb), 7909 MLXSW_REG(ralue), 7910 MLXSW_REG(rauht), 7911 MLXSW_REG(raleu), 7912 MLXSW_REG(rauhtd), 7913 MLXSW_REG(rigr2), 7914 MLXSW_REG(recr2), 7915 MLXSW_REG(rmft2), 7916 MLXSW_REG(mfcr), 7917 MLXSW_REG(mfsc), 7918 MLXSW_REG(mfsm), 7919 MLXSW_REG(mfsl), 7920 MLXSW_REG(mtcap), 7921 MLXSW_REG(mtmp), 7922 MLXSW_REG(mcia), 7923 MLXSW_REG(mpat), 7924 MLXSW_REG(mpar), 7925 MLXSW_REG(mrsr), 7926 MLXSW_REG(mlcr), 7927 MLXSW_REG(mpsc), 7928 MLXSW_REG(mcqi), 7929 MLXSW_REG(mcc), 7930 MLXSW_REG(mcda), 7931 MLXSW_REG(mgpc), 7932 MLXSW_REG(tigcr), 7933 MLXSW_REG(sbpr), 7934 MLXSW_REG(sbcm), 7935 MLXSW_REG(sbpm), 7936 MLXSW_REG(sbmm), 7937 MLXSW_REG(sbsr), 7938 MLXSW_REG(sbib), 7939 }; 7940 7941 static inline const char *mlxsw_reg_id_str(u16 reg_id) 7942 { 7943 const struct mlxsw_reg_info *reg_info; 7944 int i; 7945 7946 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 7947 reg_info = mlxsw_reg_infos[i]; 7948 if (reg_info->id == reg_id) 7949 return reg_info->name; 7950 } 7951 return "*UNKNOWN*"; 7952 } 7953 7954 /* PUDE - Port Up / Down Event 7955 * --------------------------- 7956 * Reports the operational state change of a port. 7957 */ 7958 #define MLXSW_REG_PUDE_LEN 0x10 7959 7960 /* reg_pude_swid 7961 * Switch partition ID with which to associate the port. 7962 * Access: Index 7963 */ 7964 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 7965 7966 /* reg_pude_local_port 7967 * Local port number. 7968 * Access: Index 7969 */ 7970 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 7971 7972 /* reg_pude_admin_status 7973 * Port administrative state (the desired state). 7974 * 1 - Up. 7975 * 2 - Down. 7976 * 3 - Up once. This means that in case of link failure, the port won't go 7977 * into polling mode, but will wait to be re-enabled by software. 7978 * 4 - Disabled by system. Can only be set by hardware. 7979 * Access: RO 7980 */ 7981 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 7982 7983 /* reg_pude_oper_status 7984 * Port operatioanl state. 7985 * 1 - Up. 7986 * 2 - Down. 7987 * 3 - Down by port failure. This means that the device will not let the 7988 * port up again until explicitly specified by software. 7989 * Access: RO 7990 */ 7991 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 7992 7993 #endif 7994