1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 1); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210 /* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217 { 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220 } 2221 2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224 { 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231 } 2232 2233 /* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238 #define MLXSW_REG_PTAR_ID 0x3006 2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247 enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256 }; 2257 2258 /* reg_ptar_op 2259 * Access: OP 2260 */ 2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263 /* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270 enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273 }; 2274 2275 /* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281 /* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291 /* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298 /* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307 /* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322 { 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330 } 2331 2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334 { 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336 } 2337 2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339 { 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341 } 2342 2343 /* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347 #define MLXSW_REG_PPBS_ID 0x300C 2348 #define MLXSW_REG_PPBS_LEN 0x14 2349 2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352 /* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359 /* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367 { 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371 } 2372 2373 /* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377 #define MLXSW_REG_PRCR_ID 0x300D 2378 #define MLXSW_REG_PRCR_LEN 0x40 2379 2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382 enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393 }; 2394 2395 /* reg_prcr_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400 /* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406 /* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412 /* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419 /* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425 /* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437 { 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447 } 2448 2449 /* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454 #define MLXSW_REG_PEFA_ID 0x300F 2455 #define MLXSW_REG_PEFA_LEN 0xB0 2456 2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459 /* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465 /* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474 /* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484 /* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493 { 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500 } 2501 2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503 { 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505 } 2506 2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513 #define MLXSW_REG_PEMRBT_ID 0x3014 2514 #define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518 enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521 }; 2522 2523 /* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528 /* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535 static inline void 2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538 { 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542 } 2543 2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551 #define MLXSW_REG_PTCE2_ID 0x3017 2552 #define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556 /* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562 /* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569 enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585 }; 2586 2587 /* reg_ptce2_op 2588 * Access: OP 2589 */ 2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592 /* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597 /* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606 /* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615 /* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631 /* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642 { 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649 } 2650 2651 /* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655 #define MLXSW_REG_PERPT_ID 0x3021 2656 #define MLXSW_REG_PERPT_LEN 0x80 2657 2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660 /* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667 /* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674 enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679 }; 2680 2681 /* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686 /* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695 /* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701 /* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708 /* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715 /* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721 /* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727 /* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738 { 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743 } 2744 2745 static inline void 2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750 { 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761 } 2762 2763 /* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768 #define MLXSW_REG_PERAR_ID 0x3026 2769 #define MLXSW_REG_PERAR_LEN 0x08 2770 2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773 /* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780 static inline unsigned int 2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782 { 2783 return DIV_ROUND_UP(block_num, 4); 2784 } 2785 2786 /* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798 { 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802 } 2803 2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809 #define MLXSW_REG_PTCE3_ID 0x3027 2810 #define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814 /* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820 enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831 }; 2832 2833 /* reg_ptce3_op 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838 /* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846 /* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853 /* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861 /* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867 /* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874 /* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885 /* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892 /* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904 /* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912 /* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925 /* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935 /* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950 { 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964 } 2965 2966 /* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971 #define MLXSW_REG_PERCR_ID 0x302A 2972 #define MLXSW_REG_PERCR_LEN 0x80 2973 2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976 /* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983 /* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989 /* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995 /* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004 /* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013 { 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019 } 3020 3021 /* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026 #define MLXSW_REG_PERERP_ID 0x302B 3027 #define MLXSW_REG_PERERP_LEN 0x1C 3028 3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031 /* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038 /* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044 /* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050 /* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057 /* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066 /* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075 /* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086 { 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091 } 3092 3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097 { 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105 } 3106 3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111 #define MLXSW_REG_PEABFE_ID 0x3022 3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121 /* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128 /* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 /* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156 static inline void mlxsw_reg_peabfe_pack(char *payload) 3157 { 3158 MLXSW_REG_ZERO(peabfe, payload); 3159 } 3160 3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163 { 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171 } 3172 3173 /* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179 #define MLXSW_REG_IEDR_ID 0x3804 3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189 /* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195 /* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202 /* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209 /* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216 static inline void mlxsw_reg_iedr_pack(char *payload) 3217 { 3218 MLXSW_REG_ZERO(iedr, payload); 3219 } 3220 3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224 { 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232 } 3233 3234 /* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239 #define MLXSW_REG_QPTS_ID 0x4002 3240 #define MLXSW_REG_QPTS_LEN 0x8 3241 3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244 /* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252 enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255 }; 3256 3257 /* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265 { 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270 } 3271 3272 /* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277 #define MLXSW_REG_QPCR_ID 0x4004 3278 #define MLXSW_REG_QPCR_LEN 0x28 3279 3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282 enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285 }; 3286 3287 /* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293 /* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299 /* reg_qpcr_color_aware 3300 * Is the policer aware of colors. 3301 * Must be 0 (unaware) for cpu port. 3302 * Access: RW for unbounded policer. RO for bounded policer. 3303 */ 3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3305 3306 /* reg_qpcr_bytes 3307 * Is policer limit is for bytes per sec or packets per sec. 3308 * 0 - packets 3309 * 1 - bytes 3310 * Access: RW for unbounded policer. RO for bounded policer. 3311 */ 3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3313 3314 enum mlxsw_reg_qpcr_ir_units { 3315 MLXSW_REG_QPCR_IR_UNITS_M, 3316 MLXSW_REG_QPCR_IR_UNITS_K, 3317 }; 3318 3319 /* reg_qpcr_ir_units 3320 * Policer's units for cir and eir fields (for bytes limits only) 3321 * 1 - 10^3 3322 * 0 - 10^6 3323 * Access: OP 3324 */ 3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3326 3327 enum mlxsw_reg_qpcr_rate_type { 3328 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3329 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3330 }; 3331 3332 /* reg_qpcr_rate_type 3333 * Policer can have one limit (single rate) or 2 limits with specific operation 3334 * for packets that exceed the lower rate but not the upper one. 3335 * (For cpu port must be single rate) 3336 * Access: RW for unbounded policer. RO for bounded policer. 3337 */ 3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3339 3340 /* reg_qpc_cbs 3341 * Policer's committed burst size. 3342 * The policer is working with time slices of 50 nano sec. By default every 3343 * slice is granted the proportionate share of the committed rate. If we want to 3344 * allow a slice to exceed that share (while still keeping the rate per sec) we 3345 * can allow burst. The burst size is between the default proportionate share 3346 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3347 * committed rate will result in exceeding the rate). The burst size must be a 3348 * log of 2 and will be determined by 2^cbs. 3349 * Access: RW 3350 */ 3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3352 3353 /* reg_qpcr_cir 3354 * Policer's committed rate. 3355 * The rate used for sungle rate, the lower rate for double rate. 3356 * For bytes limits, the rate will be this value * the unit from ir_units. 3357 * (Resolution error is up to 1%). 3358 * Access: RW 3359 */ 3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3361 3362 /* reg_qpcr_eir 3363 * Policer's exceed rate. 3364 * The higher rate for double rate, reserved for single rate. 3365 * Lower rate for double rate policer. 3366 * For bytes limits, the rate will be this value * the unit from ir_units. 3367 * (Resolution error is up to 1%). 3368 * Access: RW 3369 */ 3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3371 3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3373 3374 /* reg_qpcr_exceed_action. 3375 * What to do with packets between the 2 limits for double rate. 3376 * Access: RW for unbounded policer. RO for bounded policer. 3377 */ 3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3379 3380 enum mlxsw_reg_qpcr_action { 3381 /* Discard */ 3382 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3383 /* Forward and set color to red. 3384 * If the packet is intended to cpu port, it will be dropped. 3385 */ 3386 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3387 }; 3388 3389 /* reg_qpcr_violate_action 3390 * What to do with packets that cross the cir limit (for single rate) or the eir 3391 * limit (for double rate). 3392 * Access: RW for unbounded policer. RO for bounded policer. 3393 */ 3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3395 3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3397 enum mlxsw_reg_qpcr_ir_units ir_units, 3398 bool bytes, u32 cir, u16 cbs) 3399 { 3400 MLXSW_REG_ZERO(qpcr, payload); 3401 mlxsw_reg_qpcr_pid_set(payload, pid); 3402 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3403 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3404 mlxsw_reg_qpcr_violate_action_set(payload, 3405 MLXSW_REG_QPCR_ACTION_DISCARD); 3406 mlxsw_reg_qpcr_cir_set(payload, cir); 3407 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3408 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3409 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3410 } 3411 3412 /* QTCT - QoS Switch Traffic Class Table 3413 * ------------------------------------- 3414 * Configures the mapping between the packet switch priority and the 3415 * traffic class on the transmit port. 3416 */ 3417 #define MLXSW_REG_QTCT_ID 0x400A 3418 #define MLXSW_REG_QTCT_LEN 0x08 3419 3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3421 3422 /* reg_qtct_local_port 3423 * Local port number. 3424 * Access: Index 3425 * 3426 * Note: CPU port is not supported. 3427 */ 3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3429 3430 /* reg_qtct_sub_port 3431 * Virtual port within the physical port. 3432 * Should be set to 0 when virtual ports are not enabled on the port. 3433 * Access: Index 3434 */ 3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3436 3437 /* reg_qtct_switch_prio 3438 * Switch priority. 3439 * Access: Index 3440 */ 3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3442 3443 /* reg_qtct_tclass 3444 * Traffic class. 3445 * Default values: 3446 * switch_prio 0 : tclass 1 3447 * switch_prio 1 : tclass 0 3448 * switch_prio i : tclass i, for i > 1 3449 * Access: RW 3450 */ 3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3452 3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3454 u8 switch_prio, u8 tclass) 3455 { 3456 MLXSW_REG_ZERO(qtct, payload); 3457 mlxsw_reg_qtct_local_port_set(payload, local_port); 3458 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3459 mlxsw_reg_qtct_tclass_set(payload, tclass); 3460 } 3461 3462 /* QEEC - QoS ETS Element Configuration Register 3463 * --------------------------------------------- 3464 * Configures the ETS elements. 3465 */ 3466 #define MLXSW_REG_QEEC_ID 0x400D 3467 #define MLXSW_REG_QEEC_LEN 0x20 3468 3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3470 3471 /* reg_qeec_local_port 3472 * Local port number. 3473 * Access: Index 3474 * 3475 * Note: CPU port is supported. 3476 */ 3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3478 3479 enum mlxsw_reg_qeec_hr { 3480 MLXSW_REG_QEEC_HIERARCY_PORT, 3481 MLXSW_REG_QEEC_HIERARCY_GROUP, 3482 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3483 MLXSW_REG_QEEC_HIERARCY_TC, 3484 }; 3485 3486 /* reg_qeec_element_hierarchy 3487 * 0 - Port 3488 * 1 - Group 3489 * 2 - Subgroup 3490 * 3 - Traffic Class 3491 * Access: Index 3492 */ 3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3494 3495 /* reg_qeec_element_index 3496 * The index of the element in the hierarchy. 3497 * Access: Index 3498 */ 3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3500 3501 /* reg_qeec_next_element_index 3502 * The index of the next (lower) element in the hierarchy. 3503 * Access: RW 3504 * 3505 * Note: Reserved for element_hierarchy 0. 3506 */ 3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3508 3509 /* reg_qeec_mise 3510 * Min shaper configuration enable. Enables configuration of the min 3511 * shaper on this ETS element 3512 * 0 - Disable 3513 * 1 - Enable 3514 * Access: RW 3515 */ 3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3517 3518 enum { 3519 MLXSW_REG_QEEC_BYTES_MODE, 3520 MLXSW_REG_QEEC_PACKETS_MODE, 3521 }; 3522 3523 /* reg_qeec_pb 3524 * Packets or bytes mode. 3525 * 0 - Bytes mode 3526 * 1 - Packets mode 3527 * Access: RW 3528 * 3529 * Note: Used for max shaper configuration. For Spectrum, packets mode 3530 * is supported only for traffic classes of CPU port. 3531 */ 3532 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3533 3534 /* The smallest permitted min shaper rate. */ 3535 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3536 3537 /* reg_qeec_min_shaper_rate 3538 * Min shaper information rate. 3539 * For CPU port, can only be configured for port hierarchy. 3540 * When in bytes mode, value is specified in units of 1000bps. 3541 * Access: RW 3542 */ 3543 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3544 3545 /* reg_qeec_mase 3546 * Max shaper configuration enable. Enables configuration of the max 3547 * shaper on this ETS element. 3548 * 0 - Disable 3549 * 1 - Enable 3550 * Access: RW 3551 */ 3552 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3553 3554 /* A large max rate will disable the max shaper. */ 3555 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3556 3557 /* reg_qeec_max_shaper_rate 3558 * Max shaper information rate. 3559 * For CPU port, can only be configured for port hierarchy. 3560 * When in bytes mode, value is specified in units of 1000bps. 3561 * Access: RW 3562 */ 3563 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3564 3565 /* reg_qeec_de 3566 * DWRR configuration enable. Enables configuration of the dwrr and 3567 * dwrr_weight. 3568 * 0 - Disable 3569 * 1 - Enable 3570 * Access: RW 3571 */ 3572 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3573 3574 /* reg_qeec_dwrr 3575 * Transmission selection algorithm to use on the link going down from 3576 * the ETS element. 3577 * 0 - Strict priority 3578 * 1 - DWRR 3579 * Access: RW 3580 */ 3581 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3582 3583 /* reg_qeec_dwrr_weight 3584 * DWRR weight on the link going down from the ETS element. The 3585 * percentage of bandwidth guaranteed to an ETS element within 3586 * its hierarchy. The sum of all weights across all ETS elements 3587 * within one hierarchy should be equal to 100. Reserved when 3588 * transmission selection algorithm is strict priority. 3589 * Access: RW 3590 */ 3591 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3592 3593 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3594 enum mlxsw_reg_qeec_hr hr, u8 index, 3595 u8 next_index) 3596 { 3597 MLXSW_REG_ZERO(qeec, payload); 3598 mlxsw_reg_qeec_local_port_set(payload, local_port); 3599 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3600 mlxsw_reg_qeec_element_index_set(payload, index); 3601 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3602 } 3603 3604 /* QRWE - QoS ReWrite Enable 3605 * ------------------------- 3606 * This register configures the rewrite enable per receive port. 3607 */ 3608 #define MLXSW_REG_QRWE_ID 0x400F 3609 #define MLXSW_REG_QRWE_LEN 0x08 3610 3611 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3612 3613 /* reg_qrwe_local_port 3614 * Local port number. 3615 * Access: Index 3616 * 3617 * Note: CPU port is supported. No support for router port. 3618 */ 3619 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3620 3621 /* reg_qrwe_dscp 3622 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3623 * Access: RW 3624 */ 3625 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3626 3627 /* reg_qrwe_pcp 3628 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3629 * Access: RW 3630 */ 3631 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3632 3633 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3634 bool rewrite_pcp, bool rewrite_dscp) 3635 { 3636 MLXSW_REG_ZERO(qrwe, payload); 3637 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3638 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3639 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3640 } 3641 3642 /* QPDSM - QoS Priority to DSCP Mapping 3643 * ------------------------------------ 3644 * QoS Priority to DSCP Mapping Register 3645 */ 3646 #define MLXSW_REG_QPDSM_ID 0x4011 3647 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3648 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3649 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3650 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3651 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3652 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3653 3654 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3655 3656 /* reg_qpdsm_local_port 3657 * Local Port. Supported for data packets from CPU port. 3658 * Access: Index 3659 */ 3660 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3661 3662 /* reg_qpdsm_prio_entry_color0_e 3663 * Enable update of the entry for color 0 and a given port. 3664 * Access: WO 3665 */ 3666 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3667 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3668 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3669 3670 /* reg_qpdsm_prio_entry_color0_dscp 3671 * DSCP field in the outer label of the packet for color 0 and a given port. 3672 * Reserved when e=0. 3673 * Access: RW 3674 */ 3675 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3676 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3677 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3678 3679 /* reg_qpdsm_prio_entry_color1_e 3680 * Enable update of the entry for color 1 and a given port. 3681 * Access: WO 3682 */ 3683 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3684 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3685 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3686 3687 /* reg_qpdsm_prio_entry_color1_dscp 3688 * DSCP field in the outer label of the packet for color 1 and a given port. 3689 * Reserved when e=0. 3690 * Access: RW 3691 */ 3692 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3693 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3694 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3695 3696 /* reg_qpdsm_prio_entry_color2_e 3697 * Enable update of the entry for color 2 and a given port. 3698 * Access: WO 3699 */ 3700 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3701 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3702 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3703 3704 /* reg_qpdsm_prio_entry_color2_dscp 3705 * DSCP field in the outer label of the packet for color 2 and a given port. 3706 * Reserved when e=0. 3707 * Access: RW 3708 */ 3709 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3710 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3711 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3712 3713 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3714 { 3715 MLXSW_REG_ZERO(qpdsm, payload); 3716 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3717 } 3718 3719 static inline void 3720 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3721 { 3722 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3723 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3724 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3725 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3726 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3727 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3728 } 3729 3730 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3731 * -------------------------------------------------- 3732 * This register controls the mapping from DSCP field to 3733 * Switch Priority for IP packets. 3734 */ 3735 #define MLXSW_REG_QPDPM_ID 0x4013 3736 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3737 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3738 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3739 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3740 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3741 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3742 3743 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3744 3745 /* reg_qpdpm_local_port 3746 * Local Port. Supported for data packets from CPU port. 3747 * Access: Index 3748 */ 3749 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3750 3751 /* reg_qpdpm_dscp_e 3752 * Enable update of the specific entry. When cleared, the switch_prio and color 3753 * fields are ignored and the previous switch_prio and color values are 3754 * preserved. 3755 * Access: WO 3756 */ 3757 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3758 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3759 3760 /* reg_qpdpm_dscp_prio 3761 * The new Switch Priority value for the relevant DSCP value. 3762 * Access: RW 3763 */ 3764 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3765 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3766 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3767 3768 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3769 { 3770 MLXSW_REG_ZERO(qpdpm, payload); 3771 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3772 } 3773 3774 static inline void 3775 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3776 { 3777 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3778 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3779 } 3780 3781 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3782 * ------------------------------------------------------------------ 3783 * This register configures if the Switch Priority to Traffic Class mapping is 3784 * based on Multicast packet indication. If so, then multicast packets will get 3785 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3786 * QTCT. 3787 * By default, Switch Priority to Traffic Class mapping is not based on 3788 * Multicast packet indication. 3789 */ 3790 #define MLXSW_REG_QTCTM_ID 0x401A 3791 #define MLXSW_REG_QTCTM_LEN 0x08 3792 3793 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3794 3795 /* reg_qtctm_local_port 3796 * Local port number. 3797 * No support for CPU port. 3798 * Access: Index 3799 */ 3800 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3801 3802 /* reg_qtctm_mc 3803 * Multicast Mode 3804 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3805 * indication (default is 0, not based on Multicast packet indication). 3806 */ 3807 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3808 3809 static inline void 3810 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3811 { 3812 MLXSW_REG_ZERO(qtctm, payload); 3813 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3814 mlxsw_reg_qtctm_mc_set(payload, mc); 3815 } 3816 3817 /* PMLP - Ports Module to Local Port Register 3818 * ------------------------------------------ 3819 * Configures the assignment of modules to local ports. 3820 */ 3821 #define MLXSW_REG_PMLP_ID 0x5002 3822 #define MLXSW_REG_PMLP_LEN 0x40 3823 3824 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3825 3826 /* reg_pmlp_rxtx 3827 * 0 - Tx value is used for both Tx and Rx. 3828 * 1 - Rx value is taken from a separte field. 3829 * Access: RW 3830 */ 3831 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3832 3833 /* reg_pmlp_local_port 3834 * Local port number. 3835 * Access: Index 3836 */ 3837 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3838 3839 /* reg_pmlp_width 3840 * 0 - Unmap local port. 3841 * 1 - Lane 0 is used. 3842 * 2 - Lanes 0 and 1 are used. 3843 * 4 - Lanes 0, 1, 2 and 3 are used. 3844 * Access: RW 3845 */ 3846 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3847 3848 /* reg_pmlp_module 3849 * Module number. 3850 * Access: RW 3851 */ 3852 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3853 3854 /* reg_pmlp_tx_lane 3855 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3856 * Access: RW 3857 */ 3858 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3859 3860 /* reg_pmlp_rx_lane 3861 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3862 * equal to Tx lane. 3863 * Access: RW 3864 */ 3865 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3866 3867 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3868 { 3869 MLXSW_REG_ZERO(pmlp, payload); 3870 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3871 } 3872 3873 /* PMTU - Port MTU Register 3874 * ------------------------ 3875 * Configures and reports the port MTU. 3876 */ 3877 #define MLXSW_REG_PMTU_ID 0x5003 3878 #define MLXSW_REG_PMTU_LEN 0x10 3879 3880 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3881 3882 /* reg_pmtu_local_port 3883 * Local port number. 3884 * Access: Index 3885 */ 3886 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3887 3888 /* reg_pmtu_max_mtu 3889 * Maximum MTU. 3890 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3891 * reported, otherwise the minimum between the max_mtu of the different 3892 * types is reported. 3893 * Access: RO 3894 */ 3895 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3896 3897 /* reg_pmtu_admin_mtu 3898 * MTU value to set port to. Must be smaller or equal to max_mtu. 3899 * Note: If port type is Infiniband, then port must be disabled, when its 3900 * MTU is set. 3901 * Access: RW 3902 */ 3903 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3904 3905 /* reg_pmtu_oper_mtu 3906 * The actual MTU configured on the port. Packets exceeding this size 3907 * will be dropped. 3908 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3909 * oper_mtu might be smaller than admin_mtu. 3910 * Access: RO 3911 */ 3912 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3913 3914 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3915 u16 new_mtu) 3916 { 3917 MLXSW_REG_ZERO(pmtu, payload); 3918 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3919 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3920 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3921 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3922 } 3923 3924 /* PTYS - Port Type and Speed Register 3925 * ----------------------------------- 3926 * Configures and reports the port speed type. 3927 * 3928 * Note: When set while the link is up, the changes will not take effect 3929 * until the port transitions from down to up state. 3930 */ 3931 #define MLXSW_REG_PTYS_ID 0x5004 3932 #define MLXSW_REG_PTYS_LEN 0x40 3933 3934 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3935 3936 /* an_disable_admin 3937 * Auto negotiation disable administrative configuration 3938 * 0 - Device doesn't support AN disable. 3939 * 1 - Device supports AN disable. 3940 * Access: RW 3941 */ 3942 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3943 3944 /* reg_ptys_local_port 3945 * Local port number. 3946 * Access: Index 3947 */ 3948 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3949 3950 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3951 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3952 3953 /* reg_ptys_proto_mask 3954 * Protocol mask. Indicates which protocol is used. 3955 * 0 - Infiniband. 3956 * 1 - Fibre Channel. 3957 * 2 - Ethernet. 3958 * Access: Index 3959 */ 3960 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3961 3962 enum { 3963 MLXSW_REG_PTYS_AN_STATUS_NA, 3964 MLXSW_REG_PTYS_AN_STATUS_OK, 3965 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3966 }; 3967 3968 /* reg_ptys_an_status 3969 * Autonegotiation status. 3970 * Access: RO 3971 */ 3972 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3973 3974 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 3975 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 3976 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) 3977 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 3978 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 3979 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 3980 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 3981 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 3982 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 3983 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 3984 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 3985 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 3986 3987 /* reg_ptys_ext_eth_proto_cap 3988 * Extended Ethernet port supported speeds and protocols. 3989 * Access: RO 3990 */ 3991 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 3992 3993 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3994 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3995 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3996 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3997 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3998 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3999 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4000 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4001 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 4002 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4003 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4004 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4005 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4006 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4007 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4008 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4009 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4010 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4011 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4012 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4013 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 4014 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 4015 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 4016 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4017 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4018 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4019 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4020 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4021 4022 /* reg_ptys_eth_proto_cap 4023 * Ethernet port supported speeds and protocols. 4024 * Access: RO 4025 */ 4026 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4027 4028 /* reg_ptys_ib_link_width_cap 4029 * IB port supported widths. 4030 * Access: RO 4031 */ 4032 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4033 4034 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4035 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4036 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4037 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4038 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4039 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4040 4041 /* reg_ptys_ib_proto_cap 4042 * IB port supported speeds and protocols. 4043 * Access: RO 4044 */ 4045 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4046 4047 /* reg_ptys_ext_eth_proto_admin 4048 * Extended speed and protocol to set port to. 4049 * Access: RW 4050 */ 4051 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4052 4053 /* reg_ptys_eth_proto_admin 4054 * Speed and protocol to set port to. 4055 * Access: RW 4056 */ 4057 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4058 4059 /* reg_ptys_ib_link_width_admin 4060 * IB width to set port to. 4061 * Access: RW 4062 */ 4063 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4064 4065 /* reg_ptys_ib_proto_admin 4066 * IB speeds and protocols to set port to. 4067 * Access: RW 4068 */ 4069 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4070 4071 /* reg_ptys_ext_eth_proto_oper 4072 * The extended current speed and protocol configured for the port. 4073 * Access: RO 4074 */ 4075 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4076 4077 /* reg_ptys_eth_proto_oper 4078 * The current speed and protocol configured for the port. 4079 * Access: RO 4080 */ 4081 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4082 4083 /* reg_ptys_ib_link_width_oper 4084 * The current IB width to set port to. 4085 * Access: RO 4086 */ 4087 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4088 4089 /* reg_ptys_ib_proto_oper 4090 * The current IB speed and protocol. 4091 * Access: RO 4092 */ 4093 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4094 4095 enum mlxsw_reg_ptys_connector_type { 4096 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4097 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4098 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4099 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4100 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4101 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4102 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4103 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4104 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4105 }; 4106 4107 /* reg_ptys_connector_type 4108 * Connector type indication. 4109 * Access: RO 4110 */ 4111 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4112 4113 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4114 u32 proto_admin, bool autoneg) 4115 { 4116 MLXSW_REG_ZERO(ptys, payload); 4117 mlxsw_reg_ptys_local_port_set(payload, local_port); 4118 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4119 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4120 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4121 } 4122 4123 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4124 u32 proto_admin, bool autoneg) 4125 { 4126 MLXSW_REG_ZERO(ptys, payload); 4127 mlxsw_reg_ptys_local_port_set(payload, local_port); 4128 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4129 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4130 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4131 } 4132 4133 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4134 u32 *p_eth_proto_cap, 4135 u32 *p_eth_proto_admin, 4136 u32 *p_eth_proto_oper) 4137 { 4138 if (p_eth_proto_cap) 4139 *p_eth_proto_cap = 4140 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4141 if (p_eth_proto_admin) 4142 *p_eth_proto_admin = 4143 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4144 if (p_eth_proto_oper) 4145 *p_eth_proto_oper = 4146 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4147 } 4148 4149 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4150 u32 *p_eth_proto_cap, 4151 u32 *p_eth_proto_admin, 4152 u32 *p_eth_proto_oper) 4153 { 4154 if (p_eth_proto_cap) 4155 *p_eth_proto_cap = 4156 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4157 if (p_eth_proto_admin) 4158 *p_eth_proto_admin = 4159 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4160 if (p_eth_proto_oper) 4161 *p_eth_proto_oper = 4162 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4163 } 4164 4165 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4166 u16 proto_admin, u16 link_width) 4167 { 4168 MLXSW_REG_ZERO(ptys, payload); 4169 mlxsw_reg_ptys_local_port_set(payload, local_port); 4170 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4171 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4172 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4173 } 4174 4175 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4176 u16 *p_ib_link_width_cap, 4177 u16 *p_ib_proto_oper, 4178 u16 *p_ib_link_width_oper) 4179 { 4180 if (p_ib_proto_cap) 4181 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4182 if (p_ib_link_width_cap) 4183 *p_ib_link_width_cap = 4184 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4185 if (p_ib_proto_oper) 4186 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4187 if (p_ib_link_width_oper) 4188 *p_ib_link_width_oper = 4189 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4190 } 4191 4192 /* PPAD - Port Physical Address Register 4193 * ------------------------------------- 4194 * The PPAD register configures the per port physical MAC address. 4195 */ 4196 #define MLXSW_REG_PPAD_ID 0x5005 4197 #define MLXSW_REG_PPAD_LEN 0x10 4198 4199 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4200 4201 /* reg_ppad_single_base_mac 4202 * 0: base_mac, local port should be 0 and mac[7:0] is 4203 * reserved. HW will set incremental 4204 * 1: single_mac - mac of the local_port 4205 * Access: RW 4206 */ 4207 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4208 4209 /* reg_ppad_local_port 4210 * port number, if single_base_mac = 0 then local_port is reserved 4211 * Access: RW 4212 */ 4213 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4214 4215 /* reg_ppad_mac 4216 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4217 * If single_base_mac = 1 - the per port MAC address 4218 * Access: RW 4219 */ 4220 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4221 4222 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4223 u8 local_port) 4224 { 4225 MLXSW_REG_ZERO(ppad, payload); 4226 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4227 mlxsw_reg_ppad_local_port_set(payload, local_port); 4228 } 4229 4230 /* PAOS - Ports Administrative and Operational Status Register 4231 * ----------------------------------------------------------- 4232 * Configures and retrieves per port administrative and operational status. 4233 */ 4234 #define MLXSW_REG_PAOS_ID 0x5006 4235 #define MLXSW_REG_PAOS_LEN 0x10 4236 4237 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4238 4239 /* reg_paos_swid 4240 * Switch partition ID with which to associate the port. 4241 * Note: while external ports uses unique local port numbers (and thus swid is 4242 * redundant), router ports use the same local port number where swid is the 4243 * only indication for the relevant port. 4244 * Access: Index 4245 */ 4246 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4247 4248 /* reg_paos_local_port 4249 * Local port number. 4250 * Access: Index 4251 */ 4252 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4253 4254 /* reg_paos_admin_status 4255 * Port administrative state (the desired state of the port): 4256 * 1 - Up. 4257 * 2 - Down. 4258 * 3 - Up once. This means that in case of link failure, the port won't go 4259 * into polling mode, but will wait to be re-enabled by software. 4260 * 4 - Disabled by system. Can only be set by hardware. 4261 * Access: RW 4262 */ 4263 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4264 4265 /* reg_paos_oper_status 4266 * Port operational state (the current state): 4267 * 1 - Up. 4268 * 2 - Down. 4269 * 3 - Down by port failure. This means that the device will not let the 4270 * port up again until explicitly specified by software. 4271 * Access: RO 4272 */ 4273 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4274 4275 /* reg_paos_ase 4276 * Admin state update enabled. 4277 * Access: WO 4278 */ 4279 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4280 4281 /* reg_paos_ee 4282 * Event update enable. If this bit is set, event generation will be 4283 * updated based on the e field. 4284 * Access: WO 4285 */ 4286 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4287 4288 /* reg_paos_e 4289 * Event generation on operational state change: 4290 * 0 - Do not generate event. 4291 * 1 - Generate Event. 4292 * 2 - Generate Single Event. 4293 * Access: RW 4294 */ 4295 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4296 4297 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4298 enum mlxsw_port_admin_status status) 4299 { 4300 MLXSW_REG_ZERO(paos, payload); 4301 mlxsw_reg_paos_swid_set(payload, 0); 4302 mlxsw_reg_paos_local_port_set(payload, local_port); 4303 mlxsw_reg_paos_admin_status_set(payload, status); 4304 mlxsw_reg_paos_oper_status_set(payload, 0); 4305 mlxsw_reg_paos_ase_set(payload, 1); 4306 mlxsw_reg_paos_ee_set(payload, 1); 4307 mlxsw_reg_paos_e_set(payload, 1); 4308 } 4309 4310 /* PFCC - Ports Flow Control Configuration Register 4311 * ------------------------------------------------ 4312 * Configures and retrieves the per port flow control configuration. 4313 */ 4314 #define MLXSW_REG_PFCC_ID 0x5007 4315 #define MLXSW_REG_PFCC_LEN 0x20 4316 4317 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4318 4319 /* reg_pfcc_local_port 4320 * Local port number. 4321 * Access: Index 4322 */ 4323 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4324 4325 /* reg_pfcc_pnat 4326 * Port number access type. Determines the way local_port is interpreted: 4327 * 0 - Local port number. 4328 * 1 - IB / label port number. 4329 * Access: Index 4330 */ 4331 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4332 4333 /* reg_pfcc_shl_cap 4334 * Send to higher layers capabilities: 4335 * 0 - No capability of sending Pause and PFC frames to higher layers. 4336 * 1 - Device has capability of sending Pause and PFC frames to higher 4337 * layers. 4338 * Access: RO 4339 */ 4340 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4341 4342 /* reg_pfcc_shl_opr 4343 * Send to higher layers operation: 4344 * 0 - Pause and PFC frames are handled by the port (default). 4345 * 1 - Pause and PFC frames are handled by the port and also sent to 4346 * higher layers. Only valid if shl_cap = 1. 4347 * Access: RW 4348 */ 4349 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4350 4351 /* reg_pfcc_ppan 4352 * Pause policy auto negotiation. 4353 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4354 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4355 * based on the auto-negotiation resolution. 4356 * Access: RW 4357 * 4358 * Note: The auto-negotiation advertisement is set according to pptx and 4359 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4360 */ 4361 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4362 4363 /* reg_pfcc_prio_mask_tx 4364 * Bit per priority indicating if Tx flow control policy should be 4365 * updated based on bit pfctx. 4366 * Access: WO 4367 */ 4368 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4369 4370 /* reg_pfcc_prio_mask_rx 4371 * Bit per priority indicating if Rx flow control policy should be 4372 * updated based on bit pfcrx. 4373 * Access: WO 4374 */ 4375 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4376 4377 /* reg_pfcc_pptx 4378 * Admin Pause policy on Tx. 4379 * 0 - Never generate Pause frames (default). 4380 * 1 - Generate Pause frames according to Rx buffer threshold. 4381 * Access: RW 4382 */ 4383 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4384 4385 /* reg_pfcc_aptx 4386 * Active (operational) Pause policy on Tx. 4387 * 0 - Never generate Pause frames. 4388 * 1 - Generate Pause frames according to Rx buffer threshold. 4389 * Access: RO 4390 */ 4391 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4392 4393 /* reg_pfcc_pfctx 4394 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4395 * 0 - Never generate priority Pause frames on the specified priority 4396 * (default). 4397 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4398 * the specified priority. 4399 * Access: RW 4400 * 4401 * Note: pfctx and pptx must be mutually exclusive. 4402 */ 4403 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4404 4405 /* reg_pfcc_pprx 4406 * Admin Pause policy on Rx. 4407 * 0 - Ignore received Pause frames (default). 4408 * 1 - Respect received Pause frames. 4409 * Access: RW 4410 */ 4411 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4412 4413 /* reg_pfcc_aprx 4414 * Active (operational) Pause policy on Rx. 4415 * 0 - Ignore received Pause frames. 4416 * 1 - Respect received Pause frames. 4417 * Access: RO 4418 */ 4419 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4420 4421 /* reg_pfcc_pfcrx 4422 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4423 * 0 - Ignore incoming priority Pause frames on the specified priority 4424 * (default). 4425 * 1 - Respect incoming priority Pause frames on the specified priority. 4426 * Access: RW 4427 */ 4428 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4429 4430 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4431 4432 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4433 { 4434 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4435 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4436 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4437 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4438 } 4439 4440 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4441 { 4442 MLXSW_REG_ZERO(pfcc, payload); 4443 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4444 } 4445 4446 /* PPCNT - Ports Performance Counters Register 4447 * ------------------------------------------- 4448 * The PPCNT register retrieves per port performance counters. 4449 */ 4450 #define MLXSW_REG_PPCNT_ID 0x5008 4451 #define MLXSW_REG_PPCNT_LEN 0x100 4452 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4453 4454 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4455 4456 /* reg_ppcnt_swid 4457 * For HCA: must be always 0. 4458 * Switch partition ID to associate port with. 4459 * Switch partitions are numbered from 0 to 7 inclusively. 4460 * Switch partition 254 indicates stacking ports. 4461 * Switch partition 255 indicates all switch partitions. 4462 * Only valid on Set() operation with local_port=255. 4463 * Access: Index 4464 */ 4465 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4466 4467 /* reg_ppcnt_local_port 4468 * Local port number. 4469 * 255 indicates all ports on the device, and is only allowed 4470 * for Set() operation. 4471 * Access: Index 4472 */ 4473 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4474 4475 /* reg_ppcnt_pnat 4476 * Port number access type: 4477 * 0 - Local port number 4478 * 1 - IB port number 4479 * Access: Index 4480 */ 4481 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4482 4483 enum mlxsw_reg_ppcnt_grp { 4484 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4485 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4486 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4487 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4488 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4489 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4490 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4491 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4492 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4493 }; 4494 4495 /* reg_ppcnt_grp 4496 * Performance counter group. 4497 * Group 63 indicates all groups. Only valid on Set() operation with 4498 * clr bit set. 4499 * 0x0: IEEE 802.3 Counters 4500 * 0x1: RFC 2863 Counters 4501 * 0x2: RFC 2819 Counters 4502 * 0x3: RFC 3635 Counters 4503 * 0x5: Ethernet Extended Counters 4504 * 0x6: Ethernet Discard Counters 4505 * 0x8: Link Level Retransmission Counters 4506 * 0x10: Per Priority Counters 4507 * 0x11: Per Traffic Class Counters 4508 * 0x12: Physical Layer Counters 4509 * 0x13: Per Traffic Class Congestion Counters 4510 * Access: Index 4511 */ 4512 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4513 4514 /* reg_ppcnt_clr 4515 * Clear counters. Setting the clr bit will reset the counter value 4516 * for all counters in the counter group. This bit can be set 4517 * for both Set() and Get() operation. 4518 * Access: OP 4519 */ 4520 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4521 4522 /* reg_ppcnt_prio_tc 4523 * Priority for counter set that support per priority, valid values: 0-7. 4524 * Traffic class for counter set that support per traffic class, 4525 * valid values: 0- cap_max_tclass-1 . 4526 * For HCA: cap_max_tclass is always 8. 4527 * Otherwise must be 0. 4528 * Access: Index 4529 */ 4530 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4531 4532 /* Ethernet IEEE 802.3 Counter Group */ 4533 4534 /* reg_ppcnt_a_frames_transmitted_ok 4535 * Access: RO 4536 */ 4537 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4538 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4539 4540 /* reg_ppcnt_a_frames_received_ok 4541 * Access: RO 4542 */ 4543 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4544 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4545 4546 /* reg_ppcnt_a_frame_check_sequence_errors 4547 * Access: RO 4548 */ 4549 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4550 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4551 4552 /* reg_ppcnt_a_alignment_errors 4553 * Access: RO 4554 */ 4555 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4556 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4557 4558 /* reg_ppcnt_a_octets_transmitted_ok 4559 * Access: RO 4560 */ 4561 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4562 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4563 4564 /* reg_ppcnt_a_octets_received_ok 4565 * Access: RO 4566 */ 4567 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4568 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4569 4570 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4571 * Access: RO 4572 */ 4573 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4574 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4575 4576 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4577 * Access: RO 4578 */ 4579 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4580 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4581 4582 /* reg_ppcnt_a_multicast_frames_received_ok 4583 * Access: RO 4584 */ 4585 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4586 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4587 4588 /* reg_ppcnt_a_broadcast_frames_received_ok 4589 * Access: RO 4590 */ 4591 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4592 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4593 4594 /* reg_ppcnt_a_in_range_length_errors 4595 * Access: RO 4596 */ 4597 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4598 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4599 4600 /* reg_ppcnt_a_out_of_range_length_field 4601 * Access: RO 4602 */ 4603 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4604 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4605 4606 /* reg_ppcnt_a_frame_too_long_errors 4607 * Access: RO 4608 */ 4609 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4610 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4611 4612 /* reg_ppcnt_a_symbol_error_during_carrier 4613 * Access: RO 4614 */ 4615 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4616 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4617 4618 /* reg_ppcnt_a_mac_control_frames_transmitted 4619 * Access: RO 4620 */ 4621 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4622 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4623 4624 /* reg_ppcnt_a_mac_control_frames_received 4625 * Access: RO 4626 */ 4627 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4628 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4629 4630 /* reg_ppcnt_a_unsupported_opcodes_received 4631 * Access: RO 4632 */ 4633 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4634 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4635 4636 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4637 * Access: RO 4638 */ 4639 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4640 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4641 4642 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4643 * Access: RO 4644 */ 4645 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4646 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4647 4648 /* Ethernet RFC 2863 Counter Group */ 4649 4650 /* reg_ppcnt_if_in_discards 4651 * Access: RO 4652 */ 4653 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4654 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4655 4656 /* reg_ppcnt_if_out_discards 4657 * Access: RO 4658 */ 4659 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4660 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4661 4662 /* reg_ppcnt_if_out_errors 4663 * Access: RO 4664 */ 4665 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4666 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4667 4668 /* Ethernet RFC 2819 Counter Group */ 4669 4670 /* reg_ppcnt_ether_stats_undersize_pkts 4671 * Access: RO 4672 */ 4673 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4674 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4675 4676 /* reg_ppcnt_ether_stats_oversize_pkts 4677 * Access: RO 4678 */ 4679 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4680 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4681 4682 /* reg_ppcnt_ether_stats_fragments 4683 * Access: RO 4684 */ 4685 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4686 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4687 4688 /* reg_ppcnt_ether_stats_pkts64octets 4689 * Access: RO 4690 */ 4691 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4692 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4693 4694 /* reg_ppcnt_ether_stats_pkts65to127octets 4695 * Access: RO 4696 */ 4697 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4698 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4699 4700 /* reg_ppcnt_ether_stats_pkts128to255octets 4701 * Access: RO 4702 */ 4703 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4704 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4705 4706 /* reg_ppcnt_ether_stats_pkts256to511octets 4707 * Access: RO 4708 */ 4709 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4710 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4711 4712 /* reg_ppcnt_ether_stats_pkts512to1023octets 4713 * Access: RO 4714 */ 4715 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4716 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4717 4718 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4719 * Access: RO 4720 */ 4721 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4722 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4723 4724 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4725 * Access: RO 4726 */ 4727 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4728 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4729 4730 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4731 * Access: RO 4732 */ 4733 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4734 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4735 4736 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4737 * Access: RO 4738 */ 4739 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4740 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4741 4742 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4743 * Access: RO 4744 */ 4745 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4746 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4747 4748 /* Ethernet RFC 3635 Counter Group */ 4749 4750 /* reg_ppcnt_dot3stats_fcs_errors 4751 * Access: RO 4752 */ 4753 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4754 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4755 4756 /* reg_ppcnt_dot3stats_symbol_errors 4757 * Access: RO 4758 */ 4759 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4760 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4761 4762 /* reg_ppcnt_dot3control_in_unknown_opcodes 4763 * Access: RO 4764 */ 4765 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4766 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4767 4768 /* reg_ppcnt_dot3in_pause_frames 4769 * Access: RO 4770 */ 4771 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4772 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4773 4774 /* Ethernet Extended Counter Group Counters */ 4775 4776 /* reg_ppcnt_ecn_marked 4777 * Access: RO 4778 */ 4779 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4780 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4781 4782 /* Ethernet Discard Counter Group Counters */ 4783 4784 /* reg_ppcnt_ingress_general 4785 * Access: RO 4786 */ 4787 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4788 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4789 4790 /* reg_ppcnt_ingress_policy_engine 4791 * Access: RO 4792 */ 4793 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4794 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4795 4796 /* reg_ppcnt_ingress_vlan_membership 4797 * Access: RO 4798 */ 4799 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4800 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4801 4802 /* reg_ppcnt_ingress_tag_frame_type 4803 * Access: RO 4804 */ 4805 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4806 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4807 4808 /* reg_ppcnt_egress_vlan_membership 4809 * Access: RO 4810 */ 4811 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 4812 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4813 4814 /* reg_ppcnt_loopback_filter 4815 * Access: RO 4816 */ 4817 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 4818 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4819 4820 /* reg_ppcnt_egress_general 4821 * Access: RO 4822 */ 4823 MLXSW_ITEM64(reg, ppcnt, egress_general, 4824 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4825 4826 /* reg_ppcnt_egress_hoq 4827 * Access: RO 4828 */ 4829 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 4830 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4831 4832 /* reg_ppcnt_egress_policy_engine 4833 * Access: RO 4834 */ 4835 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 4836 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4837 4838 /* reg_ppcnt_ingress_tx_link_down 4839 * Access: RO 4840 */ 4841 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 4842 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4843 4844 /* reg_ppcnt_egress_stp_filter 4845 * Access: RO 4846 */ 4847 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 4848 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4849 4850 /* reg_ppcnt_egress_sll 4851 * Access: RO 4852 */ 4853 MLXSW_ITEM64(reg, ppcnt, egress_sll, 4854 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4855 4856 /* Ethernet Per Priority Group Counters */ 4857 4858 /* reg_ppcnt_rx_octets 4859 * Access: RO 4860 */ 4861 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4862 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4863 4864 /* reg_ppcnt_rx_frames 4865 * Access: RO 4866 */ 4867 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4868 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4869 4870 /* reg_ppcnt_tx_octets 4871 * Access: RO 4872 */ 4873 MLXSW_ITEM64(reg, ppcnt, tx_octets, 4874 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4875 4876 /* reg_ppcnt_tx_frames 4877 * Access: RO 4878 */ 4879 MLXSW_ITEM64(reg, ppcnt, tx_frames, 4880 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4881 4882 /* reg_ppcnt_rx_pause 4883 * Access: RO 4884 */ 4885 MLXSW_ITEM64(reg, ppcnt, rx_pause, 4886 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4887 4888 /* reg_ppcnt_rx_pause_duration 4889 * Access: RO 4890 */ 4891 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 4892 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4893 4894 /* reg_ppcnt_tx_pause 4895 * Access: RO 4896 */ 4897 MLXSW_ITEM64(reg, ppcnt, tx_pause, 4898 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4899 4900 /* reg_ppcnt_tx_pause_duration 4901 * Access: RO 4902 */ 4903 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 4904 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4905 4906 /* reg_ppcnt_rx_pause_transition 4907 * Access: RO 4908 */ 4909 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 4910 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4911 4912 /* Ethernet Per Traffic Group Counters */ 4913 4914 /* reg_ppcnt_tc_transmit_queue 4915 * Contains the transmit queue depth in cells of traffic class 4916 * selected by prio_tc and the port selected by local_port. 4917 * The field cannot be cleared. 4918 * Access: RO 4919 */ 4920 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 4921 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4922 4923 /* reg_ppcnt_tc_no_buffer_discard_uc 4924 * The number of unicast packets dropped due to lack of shared 4925 * buffer resources. 4926 * Access: RO 4927 */ 4928 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 4929 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4930 4931 /* Ethernet Per Traffic Class Congestion Group Counters */ 4932 4933 /* reg_ppcnt_wred_discard 4934 * Access: RO 4935 */ 4936 MLXSW_ITEM64(reg, ppcnt, wred_discard, 4937 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4938 4939 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 4940 enum mlxsw_reg_ppcnt_grp grp, 4941 u8 prio_tc) 4942 { 4943 MLXSW_REG_ZERO(ppcnt, payload); 4944 mlxsw_reg_ppcnt_swid_set(payload, 0); 4945 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 4946 mlxsw_reg_ppcnt_pnat_set(payload, 0); 4947 mlxsw_reg_ppcnt_grp_set(payload, grp); 4948 mlxsw_reg_ppcnt_clr_set(payload, 0); 4949 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 4950 } 4951 4952 /* PLIB - Port Local to InfiniBand Port 4953 * ------------------------------------ 4954 * The PLIB register performs mapping from Local Port into InfiniBand Port. 4955 */ 4956 #define MLXSW_REG_PLIB_ID 0x500A 4957 #define MLXSW_REG_PLIB_LEN 0x10 4958 4959 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 4960 4961 /* reg_plib_local_port 4962 * Local port number. 4963 * Access: Index 4964 */ 4965 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 4966 4967 /* reg_plib_ib_port 4968 * InfiniBand port remapping for local_port. 4969 * Access: RW 4970 */ 4971 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 4972 4973 /* PPTB - Port Prio To Buffer Register 4974 * ----------------------------------- 4975 * Configures the switch priority to buffer table. 4976 */ 4977 #define MLXSW_REG_PPTB_ID 0x500B 4978 #define MLXSW_REG_PPTB_LEN 0x10 4979 4980 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 4981 4982 enum { 4983 MLXSW_REG_PPTB_MM_UM, 4984 MLXSW_REG_PPTB_MM_UNICAST, 4985 MLXSW_REG_PPTB_MM_MULTICAST, 4986 }; 4987 4988 /* reg_pptb_mm 4989 * Mapping mode. 4990 * 0 - Map both unicast and multicast packets to the same buffer. 4991 * 1 - Map only unicast packets. 4992 * 2 - Map only multicast packets. 4993 * Access: Index 4994 * 4995 * Note: SwitchX-2 only supports the first option. 4996 */ 4997 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4998 4999 /* reg_pptb_local_port 5000 * Local port number. 5001 * Access: Index 5002 */ 5003 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5004 5005 /* reg_pptb_um 5006 * Enables the update of the untagged_buf field. 5007 * Access: RW 5008 */ 5009 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5010 5011 /* reg_pptb_pm 5012 * Enables the update of the prio_to_buff field. 5013 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5014 * Access: RW 5015 */ 5016 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5017 5018 /* reg_pptb_prio_to_buff 5019 * Mapping of switch priority <i> to one of the allocated receive port 5020 * buffers. 5021 * Access: RW 5022 */ 5023 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5024 5025 /* reg_pptb_pm_msb 5026 * Enables the update of the prio_to_buff field. 5027 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5028 * Access: RW 5029 */ 5030 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5031 5032 /* reg_pptb_untagged_buff 5033 * Mapping of untagged frames to one of the allocated receive port buffers. 5034 * Access: RW 5035 * 5036 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5037 * Spectrum, as it maps untagged packets based on the default switch priority. 5038 */ 5039 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5040 5041 /* reg_pptb_prio_to_buff_msb 5042 * Mapping of switch priority <i+8> to one of the allocated receive port 5043 * buffers. 5044 * Access: RW 5045 */ 5046 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5047 5048 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5049 5050 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5051 { 5052 MLXSW_REG_ZERO(pptb, payload); 5053 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5054 mlxsw_reg_pptb_local_port_set(payload, local_port); 5055 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5056 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5057 } 5058 5059 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5060 u8 buff) 5061 { 5062 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5063 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5064 } 5065 5066 /* PBMC - Port Buffer Management Control Register 5067 * ---------------------------------------------- 5068 * The PBMC register configures and retrieves the port packet buffer 5069 * allocation for different Prios, and the Pause threshold management. 5070 */ 5071 #define MLXSW_REG_PBMC_ID 0x500C 5072 #define MLXSW_REG_PBMC_LEN 0x6C 5073 5074 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5075 5076 /* reg_pbmc_local_port 5077 * Local port number. 5078 * Access: Index 5079 */ 5080 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5081 5082 /* reg_pbmc_xoff_timer_value 5083 * When device generates a pause frame, it uses this value as the pause 5084 * timer (time for the peer port to pause in quota-512 bit time). 5085 * Access: RW 5086 */ 5087 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5088 5089 /* reg_pbmc_xoff_refresh 5090 * The time before a new pause frame should be sent to refresh the pause RW 5091 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5092 * time). 5093 * Access: RW 5094 */ 5095 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5096 5097 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5098 5099 /* reg_pbmc_buf_lossy 5100 * The field indicates if the buffer is lossy. 5101 * 0 - Lossless 5102 * 1 - Lossy 5103 * Access: RW 5104 */ 5105 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5106 5107 /* reg_pbmc_buf_epsb 5108 * Eligible for Port Shared buffer. 5109 * If epsb is set, packets assigned to buffer are allowed to insert the port 5110 * shared buffer. 5111 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5112 * Access: RW 5113 */ 5114 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5115 5116 /* reg_pbmc_buf_size 5117 * The part of the packet buffer array is allocated for the specific buffer. 5118 * Units are represented in cells. 5119 * Access: RW 5120 */ 5121 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5122 5123 /* reg_pbmc_buf_xoff_threshold 5124 * Once the amount of data in the buffer goes above this value, device 5125 * starts sending PFC frames for all priorities associated with the 5126 * buffer. Units are represented in cells. Reserved in case of lossy 5127 * buffer. 5128 * Access: RW 5129 * 5130 * Note: In Spectrum, reserved for buffer[9]. 5131 */ 5132 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5133 0x08, 0x04, false); 5134 5135 /* reg_pbmc_buf_xon_threshold 5136 * When the amount of data in the buffer goes below this value, device 5137 * stops sending PFC frames for the priorities associated with the 5138 * buffer. Units are represented in cells. Reserved in case of lossy 5139 * buffer. 5140 * Access: RW 5141 * 5142 * Note: In Spectrum, reserved for buffer[9]. 5143 */ 5144 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5145 0x08, 0x04, false); 5146 5147 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5148 u16 xoff_timer_value, u16 xoff_refresh) 5149 { 5150 MLXSW_REG_ZERO(pbmc, payload); 5151 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5152 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5153 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5154 } 5155 5156 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5157 int buf_index, 5158 u16 size) 5159 { 5160 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5161 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5162 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5163 } 5164 5165 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5166 int buf_index, u16 size, 5167 u16 threshold) 5168 { 5169 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5170 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5171 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5172 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5173 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5174 } 5175 5176 /* PSPA - Port Switch Partition Allocation 5177 * --------------------------------------- 5178 * Controls the association of a port with a switch partition and enables 5179 * configuring ports as stacking ports. 5180 */ 5181 #define MLXSW_REG_PSPA_ID 0x500D 5182 #define MLXSW_REG_PSPA_LEN 0x8 5183 5184 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5185 5186 /* reg_pspa_swid 5187 * Switch partition ID. 5188 * Access: RW 5189 */ 5190 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5191 5192 /* reg_pspa_local_port 5193 * Local port number. 5194 * Access: Index 5195 */ 5196 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5197 5198 /* reg_pspa_sub_port 5199 * Virtual port within the local port. Set to 0 when virtual ports are 5200 * disabled on the local port. 5201 * Access: Index 5202 */ 5203 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5204 5205 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5206 { 5207 MLXSW_REG_ZERO(pspa, payload); 5208 mlxsw_reg_pspa_swid_set(payload, swid); 5209 mlxsw_reg_pspa_local_port_set(payload, local_port); 5210 mlxsw_reg_pspa_sub_port_set(payload, 0); 5211 } 5212 5213 /* HTGT - Host Trap Group Table 5214 * ---------------------------- 5215 * Configures the properties for forwarding to CPU. 5216 */ 5217 #define MLXSW_REG_HTGT_ID 0x7002 5218 #define MLXSW_REG_HTGT_LEN 0x20 5219 5220 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5221 5222 /* reg_htgt_swid 5223 * Switch partition ID. 5224 * Access: Index 5225 */ 5226 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5227 5228 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5229 5230 /* reg_htgt_type 5231 * CPU path type. 5232 * Access: RW 5233 */ 5234 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5235 5236 enum mlxsw_reg_htgt_trap_group { 5237 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5238 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 5239 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 5240 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5241 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5242 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5243 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 5244 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5245 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5246 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5247 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5248 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 5249 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 5250 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5251 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 5252 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5253 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5254 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 5255 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5256 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 5257 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 5258 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5259 }; 5260 5261 /* reg_htgt_trap_group 5262 * Trap group number. User defined number specifying which trap groups 5263 * should be forwarded to the CPU. The mapping between trap IDs and trap 5264 * groups is configured using HPKT register. 5265 * Access: Index 5266 */ 5267 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5268 5269 enum { 5270 MLXSW_REG_HTGT_POLICER_DISABLE, 5271 MLXSW_REG_HTGT_POLICER_ENABLE, 5272 }; 5273 5274 /* reg_htgt_pide 5275 * Enable policer ID specified using 'pid' field. 5276 * Access: RW 5277 */ 5278 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5279 5280 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5281 5282 /* reg_htgt_pid 5283 * Policer ID for the trap group. 5284 * Access: RW 5285 */ 5286 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5287 5288 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5289 5290 /* reg_htgt_mirror_action 5291 * Mirror action to use. 5292 * 0 - Trap to CPU. 5293 * 1 - Trap to CPU and mirror to a mirroring agent. 5294 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5295 * Access: RW 5296 * 5297 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5298 */ 5299 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5300 5301 /* reg_htgt_mirroring_agent 5302 * Mirroring agent. 5303 * Access: RW 5304 */ 5305 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5306 5307 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5308 5309 /* reg_htgt_priority 5310 * Trap group priority. 5311 * In case a packet matches multiple classification rules, the packet will 5312 * only be trapped once, based on the trap ID associated with the group (via 5313 * register HPKT) with the highest priority. 5314 * Supported values are 0-7, with 7 represnting the highest priority. 5315 * Access: RW 5316 * 5317 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5318 * by the 'trap_group' field. 5319 */ 5320 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5321 5322 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5323 5324 /* reg_htgt_local_path_cpu_tclass 5325 * CPU ingress traffic class for the trap group. 5326 * Access: RW 5327 */ 5328 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5329 5330 enum mlxsw_reg_htgt_local_path_rdq { 5331 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5332 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5333 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5334 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5335 }; 5336 /* reg_htgt_local_path_rdq 5337 * Receive descriptor queue (RDQ) to use for the trap group. 5338 * Access: RW 5339 */ 5340 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5341 5342 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5343 u8 priority, u8 tc) 5344 { 5345 MLXSW_REG_ZERO(htgt, payload); 5346 5347 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5348 mlxsw_reg_htgt_pide_set(payload, 5349 MLXSW_REG_HTGT_POLICER_DISABLE); 5350 } else { 5351 mlxsw_reg_htgt_pide_set(payload, 5352 MLXSW_REG_HTGT_POLICER_ENABLE); 5353 mlxsw_reg_htgt_pid_set(payload, policer_id); 5354 } 5355 5356 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5357 mlxsw_reg_htgt_trap_group_set(payload, group); 5358 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5359 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5360 mlxsw_reg_htgt_priority_set(payload, priority); 5361 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5362 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5363 } 5364 5365 /* HPKT - Host Packet Trap 5366 * ----------------------- 5367 * Configures trap IDs inside trap groups. 5368 */ 5369 #define MLXSW_REG_HPKT_ID 0x7003 5370 #define MLXSW_REG_HPKT_LEN 0x10 5371 5372 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5373 5374 enum { 5375 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5376 MLXSW_REG_HPKT_ACK_REQUIRED, 5377 }; 5378 5379 /* reg_hpkt_ack 5380 * Require acknowledgements from the host for events. 5381 * If set, then the device will wait for the event it sent to be acknowledged 5382 * by the host. This option is only relevant for event trap IDs. 5383 * Access: RW 5384 * 5385 * Note: Currently not supported by firmware. 5386 */ 5387 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5388 5389 enum mlxsw_reg_hpkt_action { 5390 MLXSW_REG_HPKT_ACTION_FORWARD, 5391 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5392 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5393 MLXSW_REG_HPKT_ACTION_DISCARD, 5394 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5395 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5396 }; 5397 5398 /* reg_hpkt_action 5399 * Action to perform on packet when trapped. 5400 * 0 - No action. Forward to CPU based on switching rules. 5401 * 1 - Trap to CPU (CPU receives sole copy). 5402 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5403 * 3 - Discard. 5404 * 4 - Soft discard (allow other traps to act on the packet). 5405 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5406 * Access: RW 5407 * 5408 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5409 * addressed to the CPU. 5410 */ 5411 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5412 5413 /* reg_hpkt_trap_group 5414 * Trap group to associate the trap with. 5415 * Access: RW 5416 */ 5417 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5418 5419 /* reg_hpkt_trap_id 5420 * Trap ID. 5421 * Access: Index 5422 * 5423 * Note: A trap ID can only be associated with a single trap group. The device 5424 * will associate the trap ID with the last trap group configured. 5425 */ 5426 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5427 5428 enum { 5429 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5430 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5431 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5432 }; 5433 5434 /* reg_hpkt_ctrl 5435 * Configure dedicated buffer resources for control packets. 5436 * Ignored by SwitchX-2. 5437 * 0 - Keep factory defaults. 5438 * 1 - Do not use control buffer for this trap ID. 5439 * 2 - Use control buffer for this trap ID. 5440 * Access: RW 5441 */ 5442 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5443 5444 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5445 enum mlxsw_reg_htgt_trap_group trap_group, 5446 bool is_ctrl) 5447 { 5448 MLXSW_REG_ZERO(hpkt, payload); 5449 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5450 mlxsw_reg_hpkt_action_set(payload, action); 5451 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5452 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5453 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5454 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5455 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5456 } 5457 5458 /* RGCR - Router General Configuration Register 5459 * -------------------------------------------- 5460 * The register is used for setting up the router configuration. 5461 */ 5462 #define MLXSW_REG_RGCR_ID 0x8001 5463 #define MLXSW_REG_RGCR_LEN 0x28 5464 5465 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5466 5467 /* reg_rgcr_ipv4_en 5468 * IPv4 router enable. 5469 * Access: RW 5470 */ 5471 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5472 5473 /* reg_rgcr_ipv6_en 5474 * IPv6 router enable. 5475 * Access: RW 5476 */ 5477 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5478 5479 /* reg_rgcr_max_router_interfaces 5480 * Defines the maximum number of active router interfaces for all virtual 5481 * routers. 5482 * Access: RW 5483 */ 5484 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5485 5486 /* reg_rgcr_usp 5487 * Update switch priority and packet color. 5488 * 0 - Preserve the value of Switch Priority and packet color. 5489 * 1 - Recalculate the value of Switch Priority and packet color. 5490 * Access: RW 5491 * 5492 * Note: Not supported by SwitchX and SwitchX-2. 5493 */ 5494 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5495 5496 /* reg_rgcr_pcp_rw 5497 * Indicates how to handle the pcp_rewrite_en value: 5498 * 0 - Preserve the value of pcp_rewrite_en. 5499 * 2 - Disable PCP rewrite. 5500 * 3 - Enable PCP rewrite. 5501 * Access: RW 5502 * 5503 * Note: Not supported by SwitchX and SwitchX-2. 5504 */ 5505 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5506 5507 /* reg_rgcr_activity_dis 5508 * Activity disable: 5509 * 0 - Activity will be set when an entry is hit (default). 5510 * 1 - Activity will not be set when an entry is hit. 5511 * 5512 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5513 * (RALUE). 5514 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5515 * Entry (RAUHT). 5516 * Bits 2:7 are reserved. 5517 * Access: RW 5518 * 5519 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5520 */ 5521 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5522 5523 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5524 bool ipv6_en) 5525 { 5526 MLXSW_REG_ZERO(rgcr, payload); 5527 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5528 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5529 } 5530 5531 /* RITR - Router Interface Table Register 5532 * -------------------------------------- 5533 * The register is used to configure the router interface table. 5534 */ 5535 #define MLXSW_REG_RITR_ID 0x8002 5536 #define MLXSW_REG_RITR_LEN 0x40 5537 5538 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5539 5540 /* reg_ritr_enable 5541 * Enables routing on the router interface. 5542 * Access: RW 5543 */ 5544 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5545 5546 /* reg_ritr_ipv4 5547 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5548 * interface. 5549 * Access: RW 5550 */ 5551 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5552 5553 /* reg_ritr_ipv6 5554 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5555 * interface. 5556 * Access: RW 5557 */ 5558 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5559 5560 /* reg_ritr_ipv4_mc 5561 * IPv4 multicast routing enable. 5562 * Access: RW 5563 */ 5564 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5565 5566 /* reg_ritr_ipv6_mc 5567 * IPv6 multicast routing enable. 5568 * Access: RW 5569 */ 5570 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5571 5572 enum mlxsw_reg_ritr_if_type { 5573 /* VLAN interface. */ 5574 MLXSW_REG_RITR_VLAN_IF, 5575 /* FID interface. */ 5576 MLXSW_REG_RITR_FID_IF, 5577 /* Sub-port interface. */ 5578 MLXSW_REG_RITR_SP_IF, 5579 /* Loopback Interface. */ 5580 MLXSW_REG_RITR_LOOPBACK_IF, 5581 }; 5582 5583 /* reg_ritr_type 5584 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5585 * Access: RW 5586 */ 5587 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5588 5589 enum { 5590 MLXSW_REG_RITR_RIF_CREATE, 5591 MLXSW_REG_RITR_RIF_DEL, 5592 }; 5593 5594 /* reg_ritr_op 5595 * Opcode: 5596 * 0 - Create or edit RIF. 5597 * 1 - Delete RIF. 5598 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5599 * is not supported. An interface must be deleted and re-created in order 5600 * to update properties. 5601 * Access: WO 5602 */ 5603 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5604 5605 /* reg_ritr_rif 5606 * Router interface index. A pointer to the Router Interface Table. 5607 * Access: Index 5608 */ 5609 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5610 5611 /* reg_ritr_ipv4_fe 5612 * IPv4 Forwarding Enable. 5613 * Enables routing of IPv4 traffic on the router interface. When disabled, 5614 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5615 * Not supported in SwitchX-2. 5616 * Access: RW 5617 */ 5618 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5619 5620 /* reg_ritr_ipv6_fe 5621 * IPv6 Forwarding Enable. 5622 * Enables routing of IPv6 traffic on the router interface. When disabled, 5623 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5624 * Not supported in SwitchX-2. 5625 * Access: RW 5626 */ 5627 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5628 5629 /* reg_ritr_ipv4_mc_fe 5630 * IPv4 Multicast Forwarding Enable. 5631 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5632 * will be enabled. 5633 * Access: RW 5634 */ 5635 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5636 5637 /* reg_ritr_ipv6_mc_fe 5638 * IPv6 Multicast Forwarding Enable. 5639 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5640 * will be enabled. 5641 * Access: RW 5642 */ 5643 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5644 5645 /* reg_ritr_lb_en 5646 * Loop-back filter enable for unicast packets. 5647 * If the flag is set then loop-back filter for unicast packets is 5648 * implemented on the RIF. Multicast packets are always subject to 5649 * loop-back filtering. 5650 * Access: RW 5651 */ 5652 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5653 5654 /* reg_ritr_virtual_router 5655 * Virtual router ID associated with the router interface. 5656 * Access: RW 5657 */ 5658 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5659 5660 /* reg_ritr_mtu 5661 * Router interface MTU. 5662 * Access: RW 5663 */ 5664 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5665 5666 /* reg_ritr_if_swid 5667 * Switch partition ID. 5668 * Access: RW 5669 */ 5670 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5671 5672 /* reg_ritr_if_mac 5673 * Router interface MAC address. 5674 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5675 * Access: RW 5676 */ 5677 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5678 5679 /* reg_ritr_if_vrrp_id_ipv6 5680 * VRRP ID for IPv6 5681 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5682 * Access: RW 5683 */ 5684 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5685 5686 /* reg_ritr_if_vrrp_id_ipv4 5687 * VRRP ID for IPv4 5688 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5689 * Access: RW 5690 */ 5691 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5692 5693 /* VLAN Interface */ 5694 5695 /* reg_ritr_vlan_if_vid 5696 * VLAN ID. 5697 * Access: RW 5698 */ 5699 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5700 5701 /* FID Interface */ 5702 5703 /* reg_ritr_fid_if_fid 5704 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5705 * the vFID range are supported. 5706 * Access: RW 5707 */ 5708 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5709 5710 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5711 enum mlxsw_reg_ritr_if_type rif_type, 5712 u16 fid) 5713 { 5714 if (rif_type == MLXSW_REG_RITR_FID_IF) 5715 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5716 else 5717 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5718 } 5719 5720 /* Sub-port Interface */ 5721 5722 /* reg_ritr_sp_if_lag 5723 * LAG indication. When this bit is set the system_port field holds the 5724 * LAG identifier. 5725 * Access: RW 5726 */ 5727 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5728 5729 /* reg_ritr_sp_system_port 5730 * Port unique indentifier. When lag bit is set, this field holds the 5731 * lag_id in bits 0:9. 5732 * Access: RW 5733 */ 5734 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5735 5736 /* reg_ritr_sp_if_vid 5737 * VLAN ID. 5738 * Access: RW 5739 */ 5740 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5741 5742 /* Loopback Interface */ 5743 5744 enum mlxsw_reg_ritr_loopback_protocol { 5745 /* IPinIP IPv4 underlay Unicast */ 5746 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5747 /* IPinIP IPv6 underlay Unicast */ 5748 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5749 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 5750 MLXSW_REG_RITR_LOOPBACK_GENERIC, 5751 }; 5752 5753 /* reg_ritr_loopback_protocol 5754 * Access: RW 5755 */ 5756 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5757 5758 enum mlxsw_reg_ritr_loopback_ipip_type { 5759 /* Tunnel is IPinIP. */ 5760 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5761 /* Tunnel is GRE, no key. */ 5762 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5763 /* Tunnel is GRE, with a key. */ 5764 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5765 }; 5766 5767 /* reg_ritr_loopback_ipip_type 5768 * Encapsulation type. 5769 * Access: RW 5770 */ 5771 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 5772 5773 enum mlxsw_reg_ritr_loopback_ipip_options { 5774 /* The key is defined by gre_key. */ 5775 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 5776 }; 5777 5778 /* reg_ritr_loopback_ipip_options 5779 * Access: RW 5780 */ 5781 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 5782 5783 /* reg_ritr_loopback_ipip_uvr 5784 * Underlay Virtual Router ID. 5785 * Range is 0..cap_max_virtual_routers-1. 5786 * Reserved for Spectrum-2. 5787 * Access: RW 5788 */ 5789 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 5790 5791 /* reg_ritr_loopback_ipip_underlay_rif 5792 * Underlay ingress router interface. 5793 * Reserved for Spectrum. 5794 * Access: RW 5795 */ 5796 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 5797 5798 /* reg_ritr_loopback_ipip_usip* 5799 * Encapsulation Underlay source IP. 5800 * Access: RW 5801 */ 5802 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 5803 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 5804 5805 /* reg_ritr_loopback_ipip_gre_key 5806 * GRE Key. 5807 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 5808 * Access: RW 5809 */ 5810 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 5811 5812 /* Shared between ingress/egress */ 5813 enum mlxsw_reg_ritr_counter_set_type { 5814 /* No Count. */ 5815 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 5816 /* Basic. Used for router interfaces, counting the following: 5817 * - Error and Discard counters. 5818 * - Unicast, Multicast and Broadcast counters. Sharing the 5819 * same set of counters for the different type of traffic 5820 * (IPv4, IPv6 and mpls). 5821 */ 5822 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 5823 }; 5824 5825 /* reg_ritr_ingress_counter_index 5826 * Counter Index for flow counter. 5827 * Access: RW 5828 */ 5829 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 5830 5831 /* reg_ritr_ingress_counter_set_type 5832 * Igress Counter Set Type for router interface counter. 5833 * Access: RW 5834 */ 5835 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 5836 5837 /* reg_ritr_egress_counter_index 5838 * Counter Index for flow counter. 5839 * Access: RW 5840 */ 5841 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 5842 5843 /* reg_ritr_egress_counter_set_type 5844 * Egress Counter Set Type for router interface counter. 5845 * Access: RW 5846 */ 5847 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 5848 5849 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 5850 bool enable, bool egress) 5851 { 5852 enum mlxsw_reg_ritr_counter_set_type set_type; 5853 5854 if (enable) 5855 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 5856 else 5857 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 5858 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 5859 5860 if (egress) 5861 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 5862 else 5863 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 5864 } 5865 5866 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 5867 { 5868 MLXSW_REG_ZERO(ritr, payload); 5869 mlxsw_reg_ritr_rif_set(payload, rif); 5870 } 5871 5872 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 5873 u16 system_port, u16 vid) 5874 { 5875 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 5876 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 5877 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 5878 } 5879 5880 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 5881 enum mlxsw_reg_ritr_if_type type, 5882 u16 rif, u16 vr_id, u16 mtu) 5883 { 5884 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 5885 5886 MLXSW_REG_ZERO(ritr, payload); 5887 mlxsw_reg_ritr_enable_set(payload, enable); 5888 mlxsw_reg_ritr_ipv4_set(payload, 1); 5889 mlxsw_reg_ritr_ipv6_set(payload, 1); 5890 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 5891 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 5892 mlxsw_reg_ritr_type_set(payload, type); 5893 mlxsw_reg_ritr_op_set(payload, op); 5894 mlxsw_reg_ritr_rif_set(payload, rif); 5895 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 5896 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 5897 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 5898 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 5899 mlxsw_reg_ritr_lb_en_set(payload, 1); 5900 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 5901 mlxsw_reg_ritr_mtu_set(payload, mtu); 5902 } 5903 5904 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 5905 { 5906 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 5907 } 5908 5909 static inline void 5910 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 5911 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5912 enum mlxsw_reg_ritr_loopback_ipip_options options, 5913 u16 uvr_id, u16 underlay_rif, u32 gre_key) 5914 { 5915 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 5916 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 5917 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 5918 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 5919 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 5920 } 5921 5922 static inline void 5923 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 5924 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5925 enum mlxsw_reg_ritr_loopback_ipip_options options, 5926 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 5927 { 5928 mlxsw_reg_ritr_loopback_protocol_set(payload, 5929 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 5930 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 5931 uvr_id, underlay_rif, gre_key); 5932 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 5933 } 5934 5935 /* RTAR - Router TCAM Allocation Register 5936 * -------------------------------------- 5937 * This register is used for allocation of regions in the TCAM table. 5938 */ 5939 #define MLXSW_REG_RTAR_ID 0x8004 5940 #define MLXSW_REG_RTAR_LEN 0x20 5941 5942 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 5943 5944 enum mlxsw_reg_rtar_op { 5945 MLXSW_REG_RTAR_OP_ALLOCATE, 5946 MLXSW_REG_RTAR_OP_RESIZE, 5947 MLXSW_REG_RTAR_OP_DEALLOCATE, 5948 }; 5949 5950 /* reg_rtar_op 5951 * Access: WO 5952 */ 5953 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 5954 5955 enum mlxsw_reg_rtar_key_type { 5956 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 5957 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 5958 }; 5959 5960 /* reg_rtar_key_type 5961 * TCAM key type for the region. 5962 * Access: WO 5963 */ 5964 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 5965 5966 /* reg_rtar_region_size 5967 * TCAM region size. When allocating/resizing this is the requested 5968 * size, the response is the actual size. 5969 * Note: Actual size may be larger than requested. 5970 * Reserved for op = Deallocate 5971 * Access: WO 5972 */ 5973 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 5974 5975 static inline void mlxsw_reg_rtar_pack(char *payload, 5976 enum mlxsw_reg_rtar_op op, 5977 enum mlxsw_reg_rtar_key_type key_type, 5978 u16 region_size) 5979 { 5980 MLXSW_REG_ZERO(rtar, payload); 5981 mlxsw_reg_rtar_op_set(payload, op); 5982 mlxsw_reg_rtar_key_type_set(payload, key_type); 5983 mlxsw_reg_rtar_region_size_set(payload, region_size); 5984 } 5985 5986 /* RATR - Router Adjacency Table Register 5987 * -------------------------------------- 5988 * The RATR register is used to configure the Router Adjacency (next-hop) 5989 * Table. 5990 */ 5991 #define MLXSW_REG_RATR_ID 0x8008 5992 #define MLXSW_REG_RATR_LEN 0x2C 5993 5994 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5995 5996 enum mlxsw_reg_ratr_op { 5997 /* Read */ 5998 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5999 /* Read and clear activity */ 6000 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6001 /* Write Adjacency entry */ 6002 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6003 /* Write Adjacency entry only if the activity is cleared. 6004 * The write may not succeed if the activity is set. There is not 6005 * direct feedback if the write has succeeded or not, however 6006 * the get will reveal the actual entry (SW can compare the get 6007 * response to the set command). 6008 */ 6009 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6010 }; 6011 6012 /* reg_ratr_op 6013 * Note that Write operation may also be used for updating 6014 * counter_set_type and counter_index. In this case all other 6015 * fields must not be updated. 6016 * Access: OP 6017 */ 6018 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6019 6020 /* reg_ratr_v 6021 * Valid bit. Indicates if the adjacency entry is valid. 6022 * Note: the device may need some time before reusing an invalidated 6023 * entry. During this time the entry can not be reused. It is 6024 * recommended to use another entry before reusing an invalidated 6025 * entry (e.g. software can put it at the end of the list for 6026 * reusing). Trying to access an invalidated entry not yet cleared 6027 * by the device results with failure indicating "Try Again" status. 6028 * When valid is '0' then egress_router_interface,trap_action, 6029 * adjacency_parameters and counters are reserved 6030 * Access: RW 6031 */ 6032 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6033 6034 /* reg_ratr_a 6035 * Activity. Set for new entries. Set if a packet lookup has hit on 6036 * the specific entry. To clear the a bit, use "clear activity". 6037 * Access: RO 6038 */ 6039 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6040 6041 enum mlxsw_reg_ratr_type { 6042 /* Ethernet */ 6043 MLXSW_REG_RATR_TYPE_ETHERNET, 6044 /* IPoIB Unicast without GRH. 6045 * Reserved for Spectrum. 6046 */ 6047 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6048 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6049 * adjacency). 6050 * Reserved for Spectrum. 6051 */ 6052 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6053 /* IPoIB Multicast. 6054 * Reserved for Spectrum. 6055 */ 6056 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6057 /* MPLS. 6058 * Reserved for SwitchX/-2. 6059 */ 6060 MLXSW_REG_RATR_TYPE_MPLS, 6061 /* IPinIP Encap. 6062 * Reserved for SwitchX/-2. 6063 */ 6064 MLXSW_REG_RATR_TYPE_IPIP, 6065 }; 6066 6067 /* reg_ratr_type 6068 * Adjacency entry type. 6069 * Access: RW 6070 */ 6071 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6072 6073 /* reg_ratr_adjacency_index_low 6074 * Bits 15:0 of index into the adjacency table. 6075 * For SwitchX and SwitchX-2, the adjacency table is linear and 6076 * used for adjacency entries only. 6077 * For Spectrum, the index is to the KVD linear. 6078 * Access: Index 6079 */ 6080 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6081 6082 /* reg_ratr_egress_router_interface 6083 * Range is 0 .. cap_max_router_interfaces - 1 6084 * Access: RW 6085 */ 6086 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6087 6088 enum mlxsw_reg_ratr_trap_action { 6089 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6090 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6091 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6092 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6093 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6094 }; 6095 6096 /* reg_ratr_trap_action 6097 * see mlxsw_reg_ratr_trap_action 6098 * Access: RW 6099 */ 6100 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6101 6102 /* reg_ratr_adjacency_index_high 6103 * Bits 23:16 of the adjacency_index. 6104 * Access: Index 6105 */ 6106 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6107 6108 enum mlxsw_reg_ratr_trap_id { 6109 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6110 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6111 }; 6112 6113 /* reg_ratr_trap_id 6114 * Trap ID to be reported to CPU. 6115 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6116 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6117 * Access: RW 6118 */ 6119 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6120 6121 /* reg_ratr_eth_destination_mac 6122 * MAC address of the destination next-hop. 6123 * Access: RW 6124 */ 6125 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6126 6127 enum mlxsw_reg_ratr_ipip_type { 6128 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6129 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6130 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6131 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6132 }; 6133 6134 /* reg_ratr_ipip_type 6135 * Underlay destination ip type. 6136 * Note: the type field must match the protocol of the router interface. 6137 * Access: RW 6138 */ 6139 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6140 6141 /* reg_ratr_ipip_ipv4_udip 6142 * Underlay ipv4 dip. 6143 * Reserved when ipip_type is IPv6. 6144 * Access: RW 6145 */ 6146 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6147 6148 /* reg_ratr_ipip_ipv6_ptr 6149 * Pointer to IPv6 underlay destination ip address. 6150 * For Spectrum: Pointer to KVD linear space. 6151 * Access: RW 6152 */ 6153 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6154 6155 enum mlxsw_reg_flow_counter_set_type { 6156 /* No count */ 6157 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6158 /* Count packets and bytes */ 6159 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6160 /* Count only packets */ 6161 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6162 }; 6163 6164 /* reg_ratr_counter_set_type 6165 * Counter set type for flow counters 6166 * Access: RW 6167 */ 6168 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6169 6170 /* reg_ratr_counter_index 6171 * Counter index for flow counters 6172 * Access: RW 6173 */ 6174 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6175 6176 static inline void 6177 mlxsw_reg_ratr_pack(char *payload, 6178 enum mlxsw_reg_ratr_op op, bool valid, 6179 enum mlxsw_reg_ratr_type type, 6180 u32 adjacency_index, u16 egress_rif) 6181 { 6182 MLXSW_REG_ZERO(ratr, payload); 6183 mlxsw_reg_ratr_op_set(payload, op); 6184 mlxsw_reg_ratr_v_set(payload, valid); 6185 mlxsw_reg_ratr_type_set(payload, type); 6186 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6187 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6188 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6189 } 6190 6191 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6192 const char *dest_mac) 6193 { 6194 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6195 } 6196 6197 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6198 { 6199 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6200 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6201 } 6202 6203 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6204 bool counter_enable) 6205 { 6206 enum mlxsw_reg_flow_counter_set_type set_type; 6207 6208 if (counter_enable) 6209 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6210 else 6211 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6212 6213 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6214 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6215 } 6216 6217 /* RDPM - Router DSCP to Priority Mapping 6218 * -------------------------------------- 6219 * Controls the mapping from DSCP field to switch priority on routed packets 6220 */ 6221 #define MLXSW_REG_RDPM_ID 0x8009 6222 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6223 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6224 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6225 #define MLXSW_REG_RDPM_LEN 0x40 6226 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6227 MLXSW_REG_RDPM_LEN - \ 6228 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6229 6230 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6231 6232 /* reg_dscp_entry_e 6233 * Enable update of the specific entry 6234 * Access: Index 6235 */ 6236 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6237 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6238 6239 /* reg_dscp_entry_prio 6240 * Switch Priority 6241 * Access: RW 6242 */ 6243 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6244 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6245 6246 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6247 u8 prio) 6248 { 6249 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6250 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6251 } 6252 6253 /* RICNT - Router Interface Counter Register 6254 * ----------------------------------------- 6255 * The RICNT register retrieves per port performance counters 6256 */ 6257 #define MLXSW_REG_RICNT_ID 0x800B 6258 #define MLXSW_REG_RICNT_LEN 0x100 6259 6260 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6261 6262 /* reg_ricnt_counter_index 6263 * Counter index 6264 * Access: RW 6265 */ 6266 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6267 6268 enum mlxsw_reg_ricnt_counter_set_type { 6269 /* No Count. */ 6270 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6271 /* Basic. Used for router interfaces, counting the following: 6272 * - Error and Discard counters. 6273 * - Unicast, Multicast and Broadcast counters. Sharing the 6274 * same set of counters for the different type of traffic 6275 * (IPv4, IPv6 and mpls). 6276 */ 6277 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6278 }; 6279 6280 /* reg_ricnt_counter_set_type 6281 * Counter Set Type for router interface counter 6282 * Access: RW 6283 */ 6284 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6285 6286 enum mlxsw_reg_ricnt_opcode { 6287 /* Nop. Supported only for read access*/ 6288 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6289 /* Clear. Setting the clr bit will reset the counter value for 6290 * all counters of the specified Router Interface. 6291 */ 6292 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6293 }; 6294 6295 /* reg_ricnt_opcode 6296 * Opcode 6297 * Access: RW 6298 */ 6299 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6300 6301 /* reg_ricnt_good_unicast_packets 6302 * good unicast packets. 6303 * Access: RW 6304 */ 6305 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6306 6307 /* reg_ricnt_good_multicast_packets 6308 * good multicast packets. 6309 * Access: RW 6310 */ 6311 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6312 6313 /* reg_ricnt_good_broadcast_packets 6314 * good broadcast packets 6315 * Access: RW 6316 */ 6317 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6318 6319 /* reg_ricnt_good_unicast_bytes 6320 * A count of L3 data and padding octets not including L2 headers 6321 * for good unicast frames. 6322 * Access: RW 6323 */ 6324 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6325 6326 /* reg_ricnt_good_multicast_bytes 6327 * A count of L3 data and padding octets not including L2 headers 6328 * for good multicast frames. 6329 * Access: RW 6330 */ 6331 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6332 6333 /* reg_ritr_good_broadcast_bytes 6334 * A count of L3 data and padding octets not including L2 headers 6335 * for good broadcast frames. 6336 * Access: RW 6337 */ 6338 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6339 6340 /* reg_ricnt_error_packets 6341 * A count of errored frames that do not pass the router checks. 6342 * Access: RW 6343 */ 6344 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6345 6346 /* reg_ricnt_discrad_packets 6347 * A count of non-errored frames that do not pass the router checks. 6348 * Access: RW 6349 */ 6350 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6351 6352 /* reg_ricnt_error_bytes 6353 * A count of L3 data and padding octets not including L2 headers 6354 * for errored frames. 6355 * Access: RW 6356 */ 6357 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6358 6359 /* reg_ricnt_discard_bytes 6360 * A count of L3 data and padding octets not including L2 headers 6361 * for non-errored frames that do not pass the router checks. 6362 * Access: RW 6363 */ 6364 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6365 6366 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6367 enum mlxsw_reg_ricnt_opcode op) 6368 { 6369 MLXSW_REG_ZERO(ricnt, payload); 6370 mlxsw_reg_ricnt_op_set(payload, op); 6371 mlxsw_reg_ricnt_counter_index_set(payload, index); 6372 mlxsw_reg_ricnt_counter_set_type_set(payload, 6373 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6374 } 6375 6376 /* RRCR - Router Rules Copy Register Layout 6377 * ---------------------------------------- 6378 * This register is used for moving and copying route entry rules. 6379 */ 6380 #define MLXSW_REG_RRCR_ID 0x800F 6381 #define MLXSW_REG_RRCR_LEN 0x24 6382 6383 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6384 6385 enum mlxsw_reg_rrcr_op { 6386 /* Move rules */ 6387 MLXSW_REG_RRCR_OP_MOVE, 6388 /* Copy rules */ 6389 MLXSW_REG_RRCR_OP_COPY, 6390 }; 6391 6392 /* reg_rrcr_op 6393 * Access: WO 6394 */ 6395 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6396 6397 /* reg_rrcr_offset 6398 * Offset within the region from which to copy/move. 6399 * Access: Index 6400 */ 6401 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6402 6403 /* reg_rrcr_size 6404 * The number of rules to copy/move. 6405 * Access: WO 6406 */ 6407 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6408 6409 /* reg_rrcr_table_id 6410 * Identifier of the table on which to perform the operation. Encoding is the 6411 * same as in RTAR.key_type 6412 * Access: Index 6413 */ 6414 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6415 6416 /* reg_rrcr_dest_offset 6417 * Offset within the region to which to copy/move 6418 * Access: Index 6419 */ 6420 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6421 6422 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6423 u16 offset, u16 size, 6424 enum mlxsw_reg_rtar_key_type table_id, 6425 u16 dest_offset) 6426 { 6427 MLXSW_REG_ZERO(rrcr, payload); 6428 mlxsw_reg_rrcr_op_set(payload, op); 6429 mlxsw_reg_rrcr_offset_set(payload, offset); 6430 mlxsw_reg_rrcr_size_set(payload, size); 6431 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6432 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6433 } 6434 6435 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6436 * ------------------------------------------------------- 6437 * RALTA is used to allocate the LPM trees of the SHSPM method. 6438 */ 6439 #define MLXSW_REG_RALTA_ID 0x8010 6440 #define MLXSW_REG_RALTA_LEN 0x04 6441 6442 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6443 6444 /* reg_ralta_op 6445 * opcode (valid for Write, must be 0 on Read) 6446 * 0 - allocate a tree 6447 * 1 - deallocate a tree 6448 * Access: OP 6449 */ 6450 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6451 6452 enum mlxsw_reg_ralxx_protocol { 6453 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6454 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6455 }; 6456 6457 /* reg_ralta_protocol 6458 * Protocol. 6459 * Deallocation opcode: Reserved. 6460 * Access: RW 6461 */ 6462 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6463 6464 /* reg_ralta_tree_id 6465 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6466 * the tree identifier (managed by software). 6467 * Note that tree_id 0 is allocated for a default-route tree. 6468 * Access: Index 6469 */ 6470 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6471 6472 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6473 enum mlxsw_reg_ralxx_protocol protocol, 6474 u8 tree_id) 6475 { 6476 MLXSW_REG_ZERO(ralta, payload); 6477 mlxsw_reg_ralta_op_set(payload, !alloc); 6478 mlxsw_reg_ralta_protocol_set(payload, protocol); 6479 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6480 } 6481 6482 /* RALST - Router Algorithmic LPM Structure Tree Register 6483 * ------------------------------------------------------ 6484 * RALST is used to set and query the structure of an LPM tree. 6485 * The structure of the tree must be sorted as a sorted binary tree, while 6486 * each node is a bin that is tagged as the length of the prefixes the lookup 6487 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6488 * of X bits to match with the destination address. The bin 0 indicates 6489 * the default action, when there is no match of any prefix. 6490 */ 6491 #define MLXSW_REG_RALST_ID 0x8011 6492 #define MLXSW_REG_RALST_LEN 0x104 6493 6494 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6495 6496 /* reg_ralst_root_bin 6497 * The bin number of the root bin. 6498 * 0<root_bin=<(length of IP address) 6499 * For a default-route tree configure 0xff 6500 * Access: RW 6501 */ 6502 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6503 6504 /* reg_ralst_tree_id 6505 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6506 * Access: Index 6507 */ 6508 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6509 6510 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6511 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6512 #define MLXSW_REG_RALST_BIN_COUNT 128 6513 6514 /* reg_ralst_left_child_bin 6515 * Holding the children of the bin according to the stored tree's structure. 6516 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6517 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6518 * Access: RW 6519 */ 6520 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6521 6522 /* reg_ralst_right_child_bin 6523 * Holding the children of the bin according to the stored tree's structure. 6524 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6525 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6526 * Access: RW 6527 */ 6528 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6529 false); 6530 6531 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6532 { 6533 MLXSW_REG_ZERO(ralst, payload); 6534 6535 /* Initialize all bins to have no left or right child */ 6536 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6537 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6538 6539 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6540 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6541 } 6542 6543 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6544 u8 left_child_bin, 6545 u8 right_child_bin) 6546 { 6547 int bin_index = bin_number - 1; 6548 6549 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6550 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6551 right_child_bin); 6552 } 6553 6554 /* RALTB - Router Algorithmic LPM Tree Binding Register 6555 * ---------------------------------------------------- 6556 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6557 */ 6558 #define MLXSW_REG_RALTB_ID 0x8012 6559 #define MLXSW_REG_RALTB_LEN 0x04 6560 6561 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6562 6563 /* reg_raltb_virtual_router 6564 * Virtual Router ID 6565 * Range is 0..cap_max_virtual_routers-1 6566 * Access: Index 6567 */ 6568 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6569 6570 /* reg_raltb_protocol 6571 * Protocol. 6572 * Access: Index 6573 */ 6574 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6575 6576 /* reg_raltb_tree_id 6577 * Tree to be used for the {virtual_router, protocol} 6578 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6579 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6580 * Access: RW 6581 */ 6582 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6583 6584 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6585 enum mlxsw_reg_ralxx_protocol protocol, 6586 u8 tree_id) 6587 { 6588 MLXSW_REG_ZERO(raltb, payload); 6589 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6590 mlxsw_reg_raltb_protocol_set(payload, protocol); 6591 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6592 } 6593 6594 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6595 * ----------------------------------------------------- 6596 * RALUE is used to configure and query LPM entries that serve 6597 * the Unicast protocols. 6598 */ 6599 #define MLXSW_REG_RALUE_ID 0x8013 6600 #define MLXSW_REG_RALUE_LEN 0x38 6601 6602 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6603 6604 /* reg_ralue_protocol 6605 * Protocol. 6606 * Access: Index 6607 */ 6608 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6609 6610 enum mlxsw_reg_ralue_op { 6611 /* Read operation. If entry doesn't exist, the operation fails. */ 6612 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6613 /* Clear on read operation. Used to read entry and 6614 * clear Activity bit. 6615 */ 6616 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6617 /* Write operation. Used to write a new entry to the table. All RW 6618 * fields are written for new entry. Activity bit is set 6619 * for new entries. 6620 */ 6621 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6622 /* Update operation. Used to update an existing route entry and 6623 * only update the RW fields that are detailed in the field 6624 * op_u_mask. If entry doesn't exist, the operation fails. 6625 */ 6626 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6627 /* Clear activity. The Activity bit (the field a) is cleared 6628 * for the entry. 6629 */ 6630 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6631 /* Delete operation. Used to delete an existing entry. If entry 6632 * doesn't exist, the operation fails. 6633 */ 6634 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6635 }; 6636 6637 /* reg_ralue_op 6638 * Operation. 6639 * Access: OP 6640 */ 6641 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6642 6643 /* reg_ralue_a 6644 * Activity. Set for new entries. Set if a packet lookup has hit on the 6645 * specific entry, only if the entry is a route. To clear the a bit, use 6646 * "clear activity" op. 6647 * Enabled by activity_dis in RGCR 6648 * Access: RO 6649 */ 6650 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6651 6652 /* reg_ralue_virtual_router 6653 * Virtual Router ID 6654 * Range is 0..cap_max_virtual_routers-1 6655 * Access: Index 6656 */ 6657 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6658 6659 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6660 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6661 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6662 6663 /* reg_ralue_op_u_mask 6664 * opcode update mask. 6665 * On read operation, this field is reserved. 6666 * This field is valid for update opcode, otherwise - reserved. 6667 * This field is a bitmask of the fields that should be updated. 6668 * Access: WO 6669 */ 6670 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6671 6672 /* reg_ralue_prefix_len 6673 * Number of bits in the prefix of the LPM route. 6674 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6675 * two entries in the physical HW table. 6676 * Access: Index 6677 */ 6678 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6679 6680 /* reg_ralue_dip* 6681 * The prefix of the route or of the marker that the object of the LPM 6682 * is compared with. The most significant bits of the dip are the prefix. 6683 * The least significant bits must be '0' if the prefix_len is smaller 6684 * than 128 for IPv6 or smaller than 32 for IPv4. 6685 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6686 * Access: Index 6687 */ 6688 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6689 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6690 6691 enum mlxsw_reg_ralue_entry_type { 6692 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6693 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6694 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6695 }; 6696 6697 /* reg_ralue_entry_type 6698 * Entry type. 6699 * Note - for Marker entries, the action_type and action fields are reserved. 6700 * Access: RW 6701 */ 6702 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6703 6704 /* reg_ralue_bmp_len 6705 * The best match prefix length in the case that there is no match for 6706 * longer prefixes. 6707 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6708 * Note for any update operation with entry_type modification this 6709 * field must be set. 6710 * Access: RW 6711 */ 6712 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6713 6714 enum mlxsw_reg_ralue_action_type { 6715 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6716 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6717 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6718 }; 6719 6720 /* reg_ralue_action_type 6721 * Action Type 6722 * Indicates how the IP address is connected. 6723 * It can be connected to a local subnet through local_erif or can be 6724 * on a remote subnet connected through a next-hop router, 6725 * or transmitted to the CPU. 6726 * Reserved when entry_type = MARKER_ENTRY 6727 * Access: RW 6728 */ 6729 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6730 6731 enum mlxsw_reg_ralue_trap_action { 6732 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6733 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6734 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6735 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6736 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6737 }; 6738 6739 /* reg_ralue_trap_action 6740 * Trap action. 6741 * For IP2ME action, only NOP and MIRROR are possible. 6742 * Access: RW 6743 */ 6744 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6745 6746 /* reg_ralue_trap_id 6747 * Trap ID to be reported to CPU. 6748 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6749 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6750 * Access: RW 6751 */ 6752 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6753 6754 /* reg_ralue_adjacency_index 6755 * Points to the first entry of the group-based ECMP. 6756 * Only relevant in case of REMOTE action. 6757 * Access: RW 6758 */ 6759 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6760 6761 /* reg_ralue_ecmp_size 6762 * Amount of sequential entries starting 6763 * from the adjacency_index (the number of ECMPs). 6764 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6765 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6766 * Only relevant in case of REMOTE action. 6767 * Access: RW 6768 */ 6769 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6770 6771 /* reg_ralue_local_erif 6772 * Egress Router Interface. 6773 * Only relevant in case of LOCAL action. 6774 * Access: RW 6775 */ 6776 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 6777 6778 /* reg_ralue_ip2me_v 6779 * Valid bit for the tunnel_ptr field. 6780 * If valid = 0 then trap to CPU as IP2ME trap ID. 6781 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 6782 * decapsulation then tunnel decapsulation is done. 6783 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 6784 * decapsulation then trap as IP2ME trap ID. 6785 * Only relevant in case of IP2ME action. 6786 * Access: RW 6787 */ 6788 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 6789 6790 /* reg_ralue_ip2me_tunnel_ptr 6791 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 6792 * For Spectrum, pointer to KVD Linear. 6793 * Only relevant in case of IP2ME action. 6794 * Access: RW 6795 */ 6796 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 6797 6798 static inline void mlxsw_reg_ralue_pack(char *payload, 6799 enum mlxsw_reg_ralxx_protocol protocol, 6800 enum mlxsw_reg_ralue_op op, 6801 u16 virtual_router, u8 prefix_len) 6802 { 6803 MLXSW_REG_ZERO(ralue, payload); 6804 mlxsw_reg_ralue_protocol_set(payload, protocol); 6805 mlxsw_reg_ralue_op_set(payload, op); 6806 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 6807 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 6808 mlxsw_reg_ralue_entry_type_set(payload, 6809 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 6810 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 6811 } 6812 6813 static inline void mlxsw_reg_ralue_pack4(char *payload, 6814 enum mlxsw_reg_ralxx_protocol protocol, 6815 enum mlxsw_reg_ralue_op op, 6816 u16 virtual_router, u8 prefix_len, 6817 u32 dip) 6818 { 6819 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6820 mlxsw_reg_ralue_dip4_set(payload, dip); 6821 } 6822 6823 static inline void mlxsw_reg_ralue_pack6(char *payload, 6824 enum mlxsw_reg_ralxx_protocol protocol, 6825 enum mlxsw_reg_ralue_op op, 6826 u16 virtual_router, u8 prefix_len, 6827 const void *dip) 6828 { 6829 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6830 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 6831 } 6832 6833 static inline void 6834 mlxsw_reg_ralue_act_remote_pack(char *payload, 6835 enum mlxsw_reg_ralue_trap_action trap_action, 6836 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 6837 { 6838 mlxsw_reg_ralue_action_type_set(payload, 6839 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 6840 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6841 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6842 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 6843 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 6844 } 6845 6846 static inline void 6847 mlxsw_reg_ralue_act_local_pack(char *payload, 6848 enum mlxsw_reg_ralue_trap_action trap_action, 6849 u16 trap_id, u16 local_erif) 6850 { 6851 mlxsw_reg_ralue_action_type_set(payload, 6852 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 6853 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6854 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6855 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 6856 } 6857 6858 static inline void 6859 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 6860 { 6861 mlxsw_reg_ralue_action_type_set(payload, 6862 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6863 } 6864 6865 static inline void 6866 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 6867 { 6868 mlxsw_reg_ralue_action_type_set(payload, 6869 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6870 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 6871 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 6872 } 6873 6874 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 6875 * ---------------------------------------------------------- 6876 * The RAUHT register is used to configure and query the Unicast Host table in 6877 * devices that implement the Algorithmic LPM. 6878 */ 6879 #define MLXSW_REG_RAUHT_ID 0x8014 6880 #define MLXSW_REG_RAUHT_LEN 0x74 6881 6882 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 6883 6884 enum mlxsw_reg_rauht_type { 6885 MLXSW_REG_RAUHT_TYPE_IPV4, 6886 MLXSW_REG_RAUHT_TYPE_IPV6, 6887 }; 6888 6889 /* reg_rauht_type 6890 * Access: Index 6891 */ 6892 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 6893 6894 enum mlxsw_reg_rauht_op { 6895 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 6896 /* Read operation */ 6897 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 6898 /* Clear on read operation. Used to read entry and clear 6899 * activity bit. 6900 */ 6901 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 6902 /* Add. Used to write a new entry to the table. All R/W fields are 6903 * relevant for new entry. Activity bit is set for new entries. 6904 */ 6905 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 6906 /* Update action. Used to update an existing route entry and 6907 * only update the following fields: 6908 * trap_action, trap_id, mac, counter_set_type, counter_index 6909 */ 6910 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 6911 /* Clear activity. A bit is cleared for the entry. */ 6912 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 6913 /* Delete entry */ 6914 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 6915 /* Delete all host entries on a RIF. In this command, dip 6916 * field is reserved. 6917 */ 6918 }; 6919 6920 /* reg_rauht_op 6921 * Access: OP 6922 */ 6923 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 6924 6925 /* reg_rauht_a 6926 * Activity. Set for new entries. Set if a packet lookup has hit on 6927 * the specific entry. 6928 * To clear the a bit, use "clear activity" op. 6929 * Enabled by activity_dis in RGCR 6930 * Access: RO 6931 */ 6932 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 6933 6934 /* reg_rauht_rif 6935 * Router Interface 6936 * Access: Index 6937 */ 6938 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 6939 6940 /* reg_rauht_dip* 6941 * Destination address. 6942 * Access: Index 6943 */ 6944 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 6945 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 6946 6947 enum mlxsw_reg_rauht_trap_action { 6948 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 6949 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 6950 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 6951 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 6952 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 6953 }; 6954 6955 /* reg_rauht_trap_action 6956 * Access: RW 6957 */ 6958 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 6959 6960 enum mlxsw_reg_rauht_trap_id { 6961 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 6962 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 6963 }; 6964 6965 /* reg_rauht_trap_id 6966 * Trap ID to be reported to CPU. 6967 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6968 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 6969 * trap_id is reserved. 6970 * Access: RW 6971 */ 6972 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 6973 6974 /* reg_rauht_counter_set_type 6975 * Counter set type for flow counters 6976 * Access: RW 6977 */ 6978 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 6979 6980 /* reg_rauht_counter_index 6981 * Counter index for flow counters 6982 * Access: RW 6983 */ 6984 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 6985 6986 /* reg_rauht_mac 6987 * MAC address. 6988 * Access: RW 6989 */ 6990 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 6991 6992 static inline void mlxsw_reg_rauht_pack(char *payload, 6993 enum mlxsw_reg_rauht_op op, u16 rif, 6994 const char *mac) 6995 { 6996 MLXSW_REG_ZERO(rauht, payload); 6997 mlxsw_reg_rauht_op_set(payload, op); 6998 mlxsw_reg_rauht_rif_set(payload, rif); 6999 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7000 } 7001 7002 static inline void mlxsw_reg_rauht_pack4(char *payload, 7003 enum mlxsw_reg_rauht_op op, u16 rif, 7004 const char *mac, u32 dip) 7005 { 7006 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7007 mlxsw_reg_rauht_dip4_set(payload, dip); 7008 } 7009 7010 static inline void mlxsw_reg_rauht_pack6(char *payload, 7011 enum mlxsw_reg_rauht_op op, u16 rif, 7012 const char *mac, const char *dip) 7013 { 7014 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7015 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7016 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7017 } 7018 7019 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7020 u64 counter_index) 7021 { 7022 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7023 mlxsw_reg_rauht_counter_set_type_set(payload, 7024 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7025 } 7026 7027 /* RALEU - Router Algorithmic LPM ECMP Update Register 7028 * --------------------------------------------------- 7029 * The register enables updating the ECMP section in the action for multiple 7030 * LPM Unicast entries in a single operation. The update is executed to 7031 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7032 */ 7033 #define MLXSW_REG_RALEU_ID 0x8015 7034 #define MLXSW_REG_RALEU_LEN 0x28 7035 7036 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7037 7038 /* reg_raleu_protocol 7039 * Protocol. 7040 * Access: Index 7041 */ 7042 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7043 7044 /* reg_raleu_virtual_router 7045 * Virtual Router ID 7046 * Range is 0..cap_max_virtual_routers-1 7047 * Access: Index 7048 */ 7049 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7050 7051 /* reg_raleu_adjacency_index 7052 * Adjacency Index used for matching on the existing entries. 7053 * Access: Index 7054 */ 7055 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7056 7057 /* reg_raleu_ecmp_size 7058 * ECMP Size used for matching on the existing entries. 7059 * Access: Index 7060 */ 7061 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7062 7063 /* reg_raleu_new_adjacency_index 7064 * New Adjacency Index. 7065 * Access: WO 7066 */ 7067 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7068 7069 /* reg_raleu_new_ecmp_size 7070 * New ECMP Size. 7071 * Access: WO 7072 */ 7073 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7074 7075 static inline void mlxsw_reg_raleu_pack(char *payload, 7076 enum mlxsw_reg_ralxx_protocol protocol, 7077 u16 virtual_router, 7078 u32 adjacency_index, u16 ecmp_size, 7079 u32 new_adjacency_index, 7080 u16 new_ecmp_size) 7081 { 7082 MLXSW_REG_ZERO(raleu, payload); 7083 mlxsw_reg_raleu_protocol_set(payload, protocol); 7084 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7085 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7086 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7087 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7088 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7089 } 7090 7091 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7092 * ---------------------------------------------------------------- 7093 * The RAUHTD register allows dumping entries from the Router Unicast Host 7094 * Table. For a given session an entry is dumped no more than one time. The 7095 * first RAUHTD access after reset is a new session. A session ends when the 7096 * num_rec response is smaller than num_rec request or for IPv4 when the 7097 * num_entries is smaller than 4. The clear activity affect the current session 7098 * or the last session if a new session has not started. 7099 */ 7100 #define MLXSW_REG_RAUHTD_ID 0x8018 7101 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7102 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7103 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7104 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7105 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7106 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7107 7108 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7109 7110 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7111 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7112 7113 /* reg_rauhtd_filter_fields 7114 * if a bit is '0' then the relevant field is ignored and dump is done 7115 * regardless of the field value 7116 * Bit0 - filter by activity: entry_a 7117 * Bit3 - filter by entry rip: entry_rif 7118 * Access: Index 7119 */ 7120 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7121 7122 enum mlxsw_reg_rauhtd_op { 7123 MLXSW_REG_RAUHTD_OP_DUMP, 7124 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7125 }; 7126 7127 /* reg_rauhtd_op 7128 * Access: OP 7129 */ 7130 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7131 7132 /* reg_rauhtd_num_rec 7133 * At request: number of records requested 7134 * At response: number of records dumped 7135 * For IPv4, each record has 4 entries at request and up to 4 entries 7136 * at response 7137 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7138 * Access: Index 7139 */ 7140 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7141 7142 /* reg_rauhtd_entry_a 7143 * Dump only if activity has value of entry_a 7144 * Reserved if filter_fields bit0 is '0' 7145 * Access: Index 7146 */ 7147 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7148 7149 enum mlxsw_reg_rauhtd_type { 7150 MLXSW_REG_RAUHTD_TYPE_IPV4, 7151 MLXSW_REG_RAUHTD_TYPE_IPV6, 7152 }; 7153 7154 /* reg_rauhtd_type 7155 * Dump only if record type is: 7156 * 0 - IPv4 7157 * 1 - IPv6 7158 * Access: Index 7159 */ 7160 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7161 7162 /* reg_rauhtd_entry_rif 7163 * Dump only if RIF has value of entry_rif 7164 * Reserved if filter_fields bit3 is '0' 7165 * Access: Index 7166 */ 7167 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7168 7169 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7170 enum mlxsw_reg_rauhtd_type type) 7171 { 7172 MLXSW_REG_ZERO(rauhtd, payload); 7173 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7174 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7175 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7176 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7177 mlxsw_reg_rauhtd_type_set(payload, type); 7178 } 7179 7180 /* reg_rauhtd_ipv4_rec_num_entries 7181 * Number of valid entries in this record: 7182 * 0 - 1 valid entry 7183 * 1 - 2 valid entries 7184 * 2 - 3 valid entries 7185 * 3 - 4 valid entries 7186 * Access: RO 7187 */ 7188 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7189 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7190 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7191 7192 /* reg_rauhtd_rec_type 7193 * Record type. 7194 * 0 - IPv4 7195 * 1 - IPv6 7196 * Access: RO 7197 */ 7198 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7199 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7200 7201 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7202 7203 /* reg_rauhtd_ipv4_ent_a 7204 * Activity. Set for new entries. Set if a packet lookup has hit on the 7205 * specific entry. 7206 * Access: RO 7207 */ 7208 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7209 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7210 7211 /* reg_rauhtd_ipv4_ent_rif 7212 * Router interface. 7213 * Access: RO 7214 */ 7215 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7216 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7217 7218 /* reg_rauhtd_ipv4_ent_dip 7219 * Destination IPv4 address. 7220 * Access: RO 7221 */ 7222 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7223 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7224 7225 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7226 7227 /* reg_rauhtd_ipv6_ent_a 7228 * Activity. Set for new entries. Set if a packet lookup has hit on the 7229 * specific entry. 7230 * Access: RO 7231 */ 7232 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7233 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7234 7235 /* reg_rauhtd_ipv6_ent_rif 7236 * Router interface. 7237 * Access: RO 7238 */ 7239 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7240 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7241 7242 /* reg_rauhtd_ipv6_ent_dip 7243 * Destination IPv6 address. 7244 * Access: RO 7245 */ 7246 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7247 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7248 7249 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7250 int ent_index, u16 *p_rif, 7251 u32 *p_dip) 7252 { 7253 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7254 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7255 } 7256 7257 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7258 int rec_index, u16 *p_rif, 7259 char *p_dip) 7260 { 7261 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7262 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7263 } 7264 7265 /* RTDP - Routing Tunnel Decap Properties Register 7266 * ----------------------------------------------- 7267 * The RTDP register is used for configuring the tunnel decap properties of NVE 7268 * and IPinIP. 7269 */ 7270 #define MLXSW_REG_RTDP_ID 0x8020 7271 #define MLXSW_REG_RTDP_LEN 0x44 7272 7273 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7274 7275 enum mlxsw_reg_rtdp_type { 7276 MLXSW_REG_RTDP_TYPE_NVE, 7277 MLXSW_REG_RTDP_TYPE_IPIP, 7278 }; 7279 7280 /* reg_rtdp_type 7281 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7282 * Access: RW 7283 */ 7284 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7285 7286 /* reg_rtdp_tunnel_index 7287 * Index to the Decap entry. 7288 * For Spectrum, Index to KVD Linear. 7289 * Access: Index 7290 */ 7291 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7292 7293 /* reg_rtdp_egress_router_interface 7294 * Underlay egress router interface. 7295 * Valid range is from 0 to cap_max_router_interfaces - 1 7296 * Access: RW 7297 */ 7298 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7299 7300 /* IPinIP */ 7301 7302 /* reg_rtdp_ipip_irif 7303 * Ingress Router Interface for the overlay router 7304 * Access: RW 7305 */ 7306 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7307 7308 enum mlxsw_reg_rtdp_ipip_sip_check { 7309 /* No sip checks. */ 7310 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7311 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7312 * equal ipv4_usip. 7313 */ 7314 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7315 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7316 * equal ipv6_usip. 7317 */ 7318 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7319 }; 7320 7321 /* reg_rtdp_ipip_sip_check 7322 * SIP check to perform. If decapsulation failed due to these configurations 7323 * then trap_id is IPIP_DECAP_ERROR. 7324 * Access: RW 7325 */ 7326 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7327 7328 /* If set, allow decapsulation of IPinIP (without GRE). */ 7329 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7330 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7331 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7332 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7333 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7334 7335 /* reg_rtdp_ipip_type_check 7336 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7337 * these configurations then trap_id is IPIP_DECAP_ERROR. 7338 * Access: RW 7339 */ 7340 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7341 7342 /* reg_rtdp_ipip_gre_key_check 7343 * Whether GRE key should be checked. When check is enabled: 7344 * - A packet received as IPinIP (without GRE) will always pass. 7345 * - A packet received as IPinGREinIP without a key will not pass the check. 7346 * - A packet received as IPinGREinIP with a key will pass the check only if the 7347 * key in the packet is equal to expected_gre_key. 7348 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7349 * Access: RW 7350 */ 7351 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7352 7353 /* reg_rtdp_ipip_ipv4_usip 7354 * Underlay IPv4 address for ipv4 source address check. 7355 * Reserved when sip_check is not '1'. 7356 * Access: RW 7357 */ 7358 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7359 7360 /* reg_rtdp_ipip_ipv6_usip_ptr 7361 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7362 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7363 * is to the KVD linear. 7364 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7365 * Access: RW 7366 */ 7367 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7368 7369 /* reg_rtdp_ipip_expected_gre_key 7370 * GRE key for checking. 7371 * Reserved when gre_key_check is '0'. 7372 * Access: RW 7373 */ 7374 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7375 7376 static inline void mlxsw_reg_rtdp_pack(char *payload, 7377 enum mlxsw_reg_rtdp_type type, 7378 u32 tunnel_index) 7379 { 7380 MLXSW_REG_ZERO(rtdp, payload); 7381 mlxsw_reg_rtdp_type_set(payload, type); 7382 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7383 } 7384 7385 static inline void 7386 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7387 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7388 unsigned int type_check, bool gre_key_check, 7389 u32 ipv4_usip, u32 expected_gre_key) 7390 { 7391 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7392 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7393 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7394 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7395 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7396 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7397 } 7398 7399 /* RIGR-V2 - Router Interface Group Register Version 2 7400 * --------------------------------------------------- 7401 * The RIGR_V2 register is used to add, remove and query egress interface list 7402 * of a multicast forwarding entry. 7403 */ 7404 #define MLXSW_REG_RIGR2_ID 0x8023 7405 #define MLXSW_REG_RIGR2_LEN 0xB0 7406 7407 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7408 7409 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7410 7411 /* reg_rigr2_rigr_index 7412 * KVD Linear index. 7413 * Access: Index 7414 */ 7415 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7416 7417 /* reg_rigr2_vnext 7418 * Next RIGR Index is valid. 7419 * Access: RW 7420 */ 7421 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7422 7423 /* reg_rigr2_next_rigr_index 7424 * Next RIGR Index. The index is to the KVD linear. 7425 * Reserved when vnxet = '0'. 7426 * Access: RW 7427 */ 7428 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7429 7430 /* reg_rigr2_vrmid 7431 * RMID Index is valid. 7432 * Access: RW 7433 */ 7434 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7435 7436 /* reg_rigr2_rmid_index 7437 * RMID Index. 7438 * Range 0 .. max_mid - 1 7439 * Reserved when vrmid = '0'. 7440 * The index is to the Port Group Table (PGT) 7441 * Access: RW 7442 */ 7443 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7444 7445 /* reg_rigr2_erif_entry_v 7446 * Egress Router Interface is valid. 7447 * Note that low-entries must be set if high-entries are set. For 7448 * example: if erif_entry[2].v is set then erif_entry[1].v and 7449 * erif_entry[0].v must be set. 7450 * Index can be from 0 to cap_mc_erif_list_entries-1 7451 * Access: RW 7452 */ 7453 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7454 7455 /* reg_rigr2_erif_entry_erif 7456 * Egress Router Interface. 7457 * Valid range is from 0 to cap_max_router_interfaces - 1 7458 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7459 * Access: RW 7460 */ 7461 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7462 7463 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7464 bool vnext, u32 next_rigr_index) 7465 { 7466 MLXSW_REG_ZERO(rigr2, payload); 7467 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7468 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7469 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7470 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7471 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7472 } 7473 7474 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7475 bool v, u16 erif) 7476 { 7477 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7478 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7479 } 7480 7481 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7482 * ------------------------------------------------------ 7483 */ 7484 #define MLXSW_REG_RECR2_ID 0x8025 7485 #define MLXSW_REG_RECR2_LEN 0x38 7486 7487 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7488 7489 /* reg_recr2_pp 7490 * Per-port configuration 7491 * Access: Index 7492 */ 7493 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7494 7495 /* reg_recr2_sh 7496 * Symmetric hash 7497 * Access: RW 7498 */ 7499 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7500 7501 /* reg_recr2_seed 7502 * Seed 7503 * Access: RW 7504 */ 7505 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7506 7507 enum { 7508 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7509 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7510 /* Enable IPv4 fields if packet is TCP or UDP */ 7511 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7512 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7513 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7514 /* Enable IPv6 fields if packet is TCP or UDP */ 7515 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7516 /* Enable TCP/UDP header fields if packet is IPv4 */ 7517 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7518 /* Enable TCP/UDP header fields if packet is IPv6 */ 7519 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7520 }; 7521 7522 /* reg_recr2_outer_header_enables 7523 * Bit mask where each bit enables a specific layer to be included in 7524 * the hash calculation. 7525 * Access: RW 7526 */ 7527 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7528 7529 enum { 7530 /* IPv4 Source IP */ 7531 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7532 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7533 /* IPv4 Destination IP */ 7534 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7535 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7536 /* IP Protocol */ 7537 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7538 /* IPv6 Source IP */ 7539 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7540 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7541 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7542 /* IPv6 Destination IP */ 7543 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7544 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7545 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7546 /* IPv6 Next Header */ 7547 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7548 /* IPv6 Flow Label */ 7549 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7550 /* TCP/UDP Source Port */ 7551 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7552 /* TCP/UDP Destination Port */ 7553 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7554 }; 7555 7556 /* reg_recr2_outer_header_fields_enable 7557 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7558 * Access: RW 7559 */ 7560 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7561 7562 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7563 { 7564 int i; 7565 7566 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7567 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7568 true); 7569 } 7570 7571 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7572 { 7573 int i; 7574 7575 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7576 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7577 true); 7578 } 7579 7580 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7581 { 7582 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7583 7584 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7585 7586 i = MLXSW_REG_RECR2_IPV6_SIP8; 7587 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7588 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7589 true); 7590 } 7591 7592 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7593 { 7594 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7595 7596 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7597 7598 i = MLXSW_REG_RECR2_IPV6_DIP8; 7599 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7600 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7601 true); 7602 } 7603 7604 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7605 { 7606 MLXSW_REG_ZERO(recr2, payload); 7607 mlxsw_reg_recr2_pp_set(payload, false); 7608 mlxsw_reg_recr2_sh_set(payload, true); 7609 mlxsw_reg_recr2_seed_set(payload, seed); 7610 } 7611 7612 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7613 * -------------------------------------------------------------- 7614 * The RMFT_V2 register is used to configure and query the multicast table. 7615 */ 7616 #define MLXSW_REG_RMFT2_ID 0x8027 7617 #define MLXSW_REG_RMFT2_LEN 0x174 7618 7619 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7620 7621 /* reg_rmft2_v 7622 * Valid 7623 * Access: RW 7624 */ 7625 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7626 7627 enum mlxsw_reg_rmft2_type { 7628 MLXSW_REG_RMFT2_TYPE_IPV4, 7629 MLXSW_REG_RMFT2_TYPE_IPV6 7630 }; 7631 7632 /* reg_rmft2_type 7633 * Access: Index 7634 */ 7635 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7636 7637 enum mlxsw_sp_reg_rmft2_op { 7638 /* For Write: 7639 * Write operation. Used to write a new entry to the table. All RW 7640 * fields are relevant for new entry. Activity bit is set for new 7641 * entries - Note write with v (Valid) 0 will delete the entry. 7642 * For Query: 7643 * Read operation 7644 */ 7645 MLXSW_REG_RMFT2_OP_READ_WRITE, 7646 }; 7647 7648 /* reg_rmft2_op 7649 * Operation. 7650 * Access: OP 7651 */ 7652 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7653 7654 /* reg_rmft2_a 7655 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7656 * entry. 7657 * Access: RO 7658 */ 7659 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7660 7661 /* reg_rmft2_offset 7662 * Offset within the multicast forwarding table to write to. 7663 * Access: Index 7664 */ 7665 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7666 7667 /* reg_rmft2_virtual_router 7668 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7669 * Access: RW 7670 */ 7671 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7672 7673 enum mlxsw_reg_rmft2_irif_mask { 7674 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7675 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7676 }; 7677 7678 /* reg_rmft2_irif_mask 7679 * Ingress RIF mask. 7680 * Access: RW 7681 */ 7682 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7683 7684 /* reg_rmft2_irif 7685 * Ingress RIF index. 7686 * Access: RW 7687 */ 7688 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7689 7690 /* reg_rmft2_dip{4,6} 7691 * Destination IPv4/6 address 7692 * Access: RW 7693 */ 7694 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7695 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7696 7697 /* reg_rmft2_dip{4,6}_mask 7698 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7699 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7700 * Access: RW 7701 */ 7702 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7703 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7704 7705 /* reg_rmft2_sip{4,6} 7706 * Source IPv4/6 address 7707 * Access: RW 7708 */ 7709 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7710 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7711 7712 /* reg_rmft2_sip{4,6}_mask 7713 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7714 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7715 * Access: RW 7716 */ 7717 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7718 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7719 7720 /* reg_rmft2_flexible_action_set 7721 * ACL action set. The only supported action types in this field and in any 7722 * action-set pointed from here are as follows: 7723 * 00h: ACTION_NULL 7724 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7725 * 03h: ACTION_TRAP 7726 * 06h: ACTION_QOS 7727 * 08h: ACTION_POLICING_MONITORING 7728 * 10h: ACTION_ROUTER_MC 7729 * Access: RW 7730 */ 7731 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7732 MLXSW_REG_FLEX_ACTION_SET_LEN); 7733 7734 static inline void 7735 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7736 u16 virtual_router, 7737 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7738 const char *flex_action_set) 7739 { 7740 MLXSW_REG_ZERO(rmft2, payload); 7741 mlxsw_reg_rmft2_v_set(payload, v); 7742 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7743 mlxsw_reg_rmft2_offset_set(payload, offset); 7744 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7745 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7746 mlxsw_reg_rmft2_irif_set(payload, irif); 7747 if (flex_action_set) 7748 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7749 flex_action_set); 7750 } 7751 7752 static inline void 7753 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7754 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7755 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7756 const char *flexible_action_set) 7757 { 7758 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7759 irif_mask, irif, flexible_action_set); 7760 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7761 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7762 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7763 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7764 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7765 } 7766 7767 static inline void 7768 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7769 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7770 struct in6_addr dip6, struct in6_addr dip6_mask, 7771 struct in6_addr sip6, struct in6_addr sip6_mask, 7772 const char *flexible_action_set) 7773 { 7774 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7775 irif_mask, irif, flexible_action_set); 7776 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 7777 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 7778 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 7779 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 7780 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 7781 } 7782 7783 /* MFCR - Management Fan Control Register 7784 * -------------------------------------- 7785 * This register controls the settings of the Fan Speed PWM mechanism. 7786 */ 7787 #define MLXSW_REG_MFCR_ID 0x9001 7788 #define MLXSW_REG_MFCR_LEN 0x08 7789 7790 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 7791 7792 enum mlxsw_reg_mfcr_pwm_frequency { 7793 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 7794 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 7795 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 7796 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 7797 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 7798 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 7799 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 7800 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 7801 }; 7802 7803 /* reg_mfcr_pwm_frequency 7804 * Controls the frequency of the PWM signal. 7805 * Access: RW 7806 */ 7807 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 7808 7809 #define MLXSW_MFCR_TACHOS_MAX 10 7810 7811 /* reg_mfcr_tacho_active 7812 * Indicates which of the tachometer is active (bit per tachometer). 7813 * Access: RO 7814 */ 7815 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 7816 7817 #define MLXSW_MFCR_PWMS_MAX 5 7818 7819 /* reg_mfcr_pwm_active 7820 * Indicates which of the PWM control is active (bit per PWM). 7821 * Access: RO 7822 */ 7823 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 7824 7825 static inline void 7826 mlxsw_reg_mfcr_pack(char *payload, 7827 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 7828 { 7829 MLXSW_REG_ZERO(mfcr, payload); 7830 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 7831 } 7832 7833 static inline void 7834 mlxsw_reg_mfcr_unpack(char *payload, 7835 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 7836 u16 *p_tacho_active, u8 *p_pwm_active) 7837 { 7838 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 7839 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 7840 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 7841 } 7842 7843 /* MFSC - Management Fan Speed Control Register 7844 * -------------------------------------------- 7845 * This register controls the settings of the Fan Speed PWM mechanism. 7846 */ 7847 #define MLXSW_REG_MFSC_ID 0x9002 7848 #define MLXSW_REG_MFSC_LEN 0x08 7849 7850 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 7851 7852 /* reg_mfsc_pwm 7853 * Fan pwm to control / monitor. 7854 * Access: Index 7855 */ 7856 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 7857 7858 /* reg_mfsc_pwm_duty_cycle 7859 * Controls the duty cycle of the PWM. Value range from 0..255 to 7860 * represent duty cycle of 0%...100%. 7861 * Access: RW 7862 */ 7863 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 7864 7865 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 7866 u8 pwm_duty_cycle) 7867 { 7868 MLXSW_REG_ZERO(mfsc, payload); 7869 mlxsw_reg_mfsc_pwm_set(payload, pwm); 7870 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 7871 } 7872 7873 /* MFSM - Management Fan Speed Measurement 7874 * --------------------------------------- 7875 * This register controls the settings of the Tacho measurements and 7876 * enables reading the Tachometer measurements. 7877 */ 7878 #define MLXSW_REG_MFSM_ID 0x9003 7879 #define MLXSW_REG_MFSM_LEN 0x08 7880 7881 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 7882 7883 /* reg_mfsm_tacho 7884 * Fan tachometer index. 7885 * Access: Index 7886 */ 7887 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 7888 7889 /* reg_mfsm_rpm 7890 * Fan speed (round per minute). 7891 * Access: RO 7892 */ 7893 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 7894 7895 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 7896 { 7897 MLXSW_REG_ZERO(mfsm, payload); 7898 mlxsw_reg_mfsm_tacho_set(payload, tacho); 7899 } 7900 7901 /* MFSL - Management Fan Speed Limit Register 7902 * ------------------------------------------ 7903 * The Fan Speed Limit register is used to configure the fan speed 7904 * event / interrupt notification mechanism. Fan speed threshold are 7905 * defined for both under-speed and over-speed. 7906 */ 7907 #define MLXSW_REG_MFSL_ID 0x9004 7908 #define MLXSW_REG_MFSL_LEN 0x0C 7909 7910 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 7911 7912 /* reg_mfsl_tacho 7913 * Fan tachometer index. 7914 * Access: Index 7915 */ 7916 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 7917 7918 /* reg_mfsl_tach_min 7919 * Tachometer minimum value (minimum RPM). 7920 * Access: RW 7921 */ 7922 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 7923 7924 /* reg_mfsl_tach_max 7925 * Tachometer maximum value (maximum RPM). 7926 * Access: RW 7927 */ 7928 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 7929 7930 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 7931 u16 tach_min, u16 tach_max) 7932 { 7933 MLXSW_REG_ZERO(mfsl, payload); 7934 mlxsw_reg_mfsl_tacho_set(payload, tacho); 7935 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 7936 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 7937 } 7938 7939 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 7940 u16 *p_tach_min, u16 *p_tach_max) 7941 { 7942 if (p_tach_min) 7943 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 7944 7945 if (p_tach_max) 7946 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 7947 } 7948 7949 /* FORE - Fan Out of Range Event Register 7950 * -------------------------------------- 7951 * This register reports the status of the controlled fans compared to the 7952 * range defined by the MFSL register. 7953 */ 7954 #define MLXSW_REG_FORE_ID 0x9007 7955 #define MLXSW_REG_FORE_LEN 0x0C 7956 7957 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 7958 7959 /* fan_under_limit 7960 * Fan speed is below the low limit defined in MFSL register. Each bit relates 7961 * to a single tachometer and indicates the specific tachometer reading is 7962 * below the threshold. 7963 * Access: RO 7964 */ 7965 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 7966 7967 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 7968 bool *fault) 7969 { 7970 u16 limit; 7971 7972 if (fault) { 7973 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 7974 *fault = limit & BIT(tacho); 7975 } 7976 } 7977 7978 /* MTCAP - Management Temperature Capabilities 7979 * ------------------------------------------- 7980 * This register exposes the capabilities of the device and 7981 * system temperature sensing. 7982 */ 7983 #define MLXSW_REG_MTCAP_ID 0x9009 7984 #define MLXSW_REG_MTCAP_LEN 0x08 7985 7986 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 7987 7988 /* reg_mtcap_sensor_count 7989 * Number of sensors supported by the device. 7990 * This includes the QSFP module sensors (if exists in the QSFP module). 7991 * Access: RO 7992 */ 7993 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 7994 7995 /* MTMP - Management Temperature 7996 * ----------------------------- 7997 * This register controls the settings of the temperature measurements 7998 * and enables reading the temperature measurements. Note that temperature 7999 * is in 0.125 degrees Celsius. 8000 */ 8001 #define MLXSW_REG_MTMP_ID 0x900A 8002 #define MLXSW_REG_MTMP_LEN 0x20 8003 8004 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8005 8006 /* reg_mtmp_sensor_index 8007 * Sensors index to access. 8008 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8009 * (module 0 is mapped to sensor_index 64). 8010 * Access: Index 8011 */ 8012 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 8013 8014 /* Convert to milli degrees Celsius */ 8015 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 8016 8017 /* reg_mtmp_temperature 8018 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8019 * degrees units. 8020 * Access: RO 8021 */ 8022 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8023 8024 /* reg_mtmp_mte 8025 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8026 * Access: RW 8027 */ 8028 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8029 8030 /* reg_mtmp_mtr 8031 * Max Temperature Reset - clears the value of the max temperature register. 8032 * Access: WO 8033 */ 8034 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8035 8036 /* reg_mtmp_max_temperature 8037 * The highest measured temperature from the sensor. 8038 * When the bit mte is cleared, the field max_temperature is reserved. 8039 * Access: RO 8040 */ 8041 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8042 8043 /* reg_mtmp_tee 8044 * Temperature Event Enable. 8045 * 0 - Do not generate event 8046 * 1 - Generate event 8047 * 2 - Generate single event 8048 * Access: RW 8049 */ 8050 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8051 8052 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8053 8054 /* reg_mtmp_temperature_threshold_hi 8055 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8056 * Access: RW 8057 */ 8058 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8059 8060 /* reg_mtmp_temperature_threshold_lo 8061 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8062 * Access: RW 8063 */ 8064 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8065 8066 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8067 8068 /* reg_mtmp_sensor_name 8069 * Sensor Name 8070 * Access: RO 8071 */ 8072 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8073 8074 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 8075 bool max_temp_enable, 8076 bool max_temp_reset) 8077 { 8078 MLXSW_REG_ZERO(mtmp, payload); 8079 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8080 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8081 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8082 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8083 MLXSW_REG_MTMP_THRESH_HI); 8084 } 8085 8086 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 8087 unsigned int *p_max_temp, 8088 char *sensor_name) 8089 { 8090 u16 temp; 8091 8092 if (p_temp) { 8093 temp = mlxsw_reg_mtmp_temperature_get(payload); 8094 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8095 } 8096 if (p_max_temp) { 8097 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8098 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8099 } 8100 if (sensor_name) 8101 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8102 } 8103 8104 /* MTBR - Management Temperature Bulk Register 8105 * ------------------------------------------- 8106 * This register is used for bulk temperature reading. 8107 */ 8108 #define MLXSW_REG_MTBR_ID 0x900F 8109 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8110 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8111 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8112 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8113 MLXSW_REG_MTBR_REC_LEN * \ 8114 MLXSW_REG_MTBR_REC_MAX_COUNT) 8115 8116 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8117 8118 /* reg_mtbr_base_sensor_index 8119 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8120 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8121 * Access: Index 8122 */ 8123 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 7); 8124 8125 /* reg_mtbr_num_rec 8126 * Request: Number of records to read 8127 * Response: Number of records read 8128 * See above description for more details. 8129 * Range 1..255 8130 * Access: RW 8131 */ 8132 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8133 8134 /* reg_mtbr_rec_max_temp 8135 * The highest measured temperature from the sensor. 8136 * When the bit mte is cleared, the field max_temperature is reserved. 8137 * Access: RO 8138 */ 8139 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8140 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8141 8142 /* reg_mtbr_rec_temp 8143 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8144 * degrees units. 8145 * Access: RO 8146 */ 8147 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8148 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8149 8150 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 base_sensor_index, 8151 u8 num_rec) 8152 { 8153 MLXSW_REG_ZERO(mtbr, payload); 8154 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8155 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8156 } 8157 8158 /* Error codes from temperatute reading */ 8159 enum mlxsw_reg_mtbr_temp_status { 8160 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8161 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8162 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8163 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8164 }; 8165 8166 /* Base index for reading modules temperature */ 8167 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8168 8169 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8170 u16 *p_temp, u16 *p_max_temp) 8171 { 8172 if (p_temp) 8173 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8174 if (p_max_temp) 8175 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8176 } 8177 8178 /* MCIA - Management Cable Info Access 8179 * ----------------------------------- 8180 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8181 */ 8182 8183 #define MLXSW_REG_MCIA_ID 0x9014 8184 #define MLXSW_REG_MCIA_LEN 0x40 8185 8186 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8187 8188 /* reg_mcia_l 8189 * Lock bit. Setting this bit will lock the access to the specific 8190 * cable. Used for updating a full page in a cable EPROM. Any access 8191 * other then subsequence writes will fail while the port is locked. 8192 * Access: RW 8193 */ 8194 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8195 8196 /* reg_mcia_module 8197 * Module number. 8198 * Access: Index 8199 */ 8200 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8201 8202 /* reg_mcia_status 8203 * Module status. 8204 * Access: RO 8205 */ 8206 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8207 8208 /* reg_mcia_i2c_device_address 8209 * I2C device address. 8210 * Access: RW 8211 */ 8212 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8213 8214 /* reg_mcia_page_number 8215 * Page number. 8216 * Access: RW 8217 */ 8218 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8219 8220 /* reg_mcia_device_address 8221 * Device address. 8222 * Access: RW 8223 */ 8224 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8225 8226 /* reg_mcia_size 8227 * Number of bytes to read/write (up to 48 bytes). 8228 * Access: RW 8229 */ 8230 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8231 8232 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8233 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8234 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8235 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8236 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8237 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8238 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8239 #define MLXSW_REG_MCIA_PAGE0_LO 0 8240 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8241 8242 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8243 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8244 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8245 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8246 }; 8247 8248 enum mlxsw_reg_mcia_eeprom_module_info_id { 8249 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8250 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8251 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8252 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8253 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8254 }; 8255 8256 enum mlxsw_reg_mcia_eeprom_module_info { 8257 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8258 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8259 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8260 }; 8261 8262 /* reg_mcia_eeprom 8263 * Bytes to read/write. 8264 * Access: RW 8265 */ 8266 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8267 8268 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8269 u8 page_number, u16 device_addr, 8270 u8 size, u8 i2c_device_addr) 8271 { 8272 MLXSW_REG_ZERO(mcia, payload); 8273 mlxsw_reg_mcia_module_set(payload, module); 8274 mlxsw_reg_mcia_l_set(payload, lock); 8275 mlxsw_reg_mcia_page_number_set(payload, page_number); 8276 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8277 mlxsw_reg_mcia_size_set(payload, size); 8278 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8279 } 8280 8281 /* MPAT - Monitoring Port Analyzer Table 8282 * ------------------------------------- 8283 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8284 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8285 */ 8286 #define MLXSW_REG_MPAT_ID 0x901A 8287 #define MLXSW_REG_MPAT_LEN 0x78 8288 8289 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8290 8291 /* reg_mpat_pa_id 8292 * Port Analyzer ID. 8293 * Access: Index 8294 */ 8295 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8296 8297 /* reg_mpat_system_port 8298 * A unique port identifier for the final destination of the packet. 8299 * Access: RW 8300 */ 8301 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8302 8303 /* reg_mpat_e 8304 * Enable. Indicating the Port Analyzer is enabled. 8305 * Access: RW 8306 */ 8307 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8308 8309 /* reg_mpat_qos 8310 * Quality Of Service Mode. 8311 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8312 * PCP, DEI, DSCP or VL) are configured. 8313 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8314 * same as in the original packet that has triggered the mirroring. For 8315 * SPAN also the pcp,dei are maintained. 8316 * Access: RW 8317 */ 8318 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8319 8320 /* reg_mpat_be 8321 * Best effort mode. Indicates mirroring traffic should not cause packet 8322 * drop or back pressure, but will discard the mirrored packets. Mirrored 8323 * packets will be forwarded on a best effort manner. 8324 * 0: Do not discard mirrored packets 8325 * 1: Discard mirrored packets if causing congestion 8326 * Access: RW 8327 */ 8328 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8329 8330 enum mlxsw_reg_mpat_span_type { 8331 /* Local SPAN Ethernet. 8332 * The original packet is not encapsulated. 8333 */ 8334 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8335 8336 /* Remote SPAN Ethernet VLAN. 8337 * The packet is forwarded to the monitoring port on the monitoring 8338 * VLAN. 8339 */ 8340 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8341 8342 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8343 * The packet is encapsulated with GRE header. 8344 */ 8345 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8346 }; 8347 8348 /* reg_mpat_span_type 8349 * SPAN type. 8350 * Access: RW 8351 */ 8352 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8353 8354 /* Remote SPAN - Ethernet VLAN 8355 * - - - - - - - - - - - - - - 8356 */ 8357 8358 /* reg_mpat_eth_rspan_vid 8359 * Encapsulation header VLAN ID. 8360 * Access: RW 8361 */ 8362 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8363 8364 /* Encapsulated Remote SPAN - Ethernet L2 8365 * - - - - - - - - - - - - - - - - - - - 8366 */ 8367 8368 enum mlxsw_reg_mpat_eth_rspan_version { 8369 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8370 }; 8371 8372 /* reg_mpat_eth_rspan_version 8373 * RSPAN mirror header version. 8374 * Access: RW 8375 */ 8376 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8377 8378 /* reg_mpat_eth_rspan_mac 8379 * Destination MAC address. 8380 * Access: RW 8381 */ 8382 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8383 8384 /* reg_mpat_eth_rspan_tp 8385 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8386 * Access: RW 8387 */ 8388 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8389 8390 /* Encapsulated Remote SPAN - Ethernet L3 8391 * - - - - - - - - - - - - - - - - - - - 8392 */ 8393 8394 enum mlxsw_reg_mpat_eth_rspan_protocol { 8395 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8396 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8397 }; 8398 8399 /* reg_mpat_eth_rspan_protocol 8400 * SPAN encapsulation protocol. 8401 * Access: RW 8402 */ 8403 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8404 8405 /* reg_mpat_eth_rspan_ttl 8406 * Encapsulation header Time-to-Live/HopLimit. 8407 * Access: RW 8408 */ 8409 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8410 8411 /* reg_mpat_eth_rspan_smac 8412 * Source MAC address 8413 * Access: RW 8414 */ 8415 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8416 8417 /* reg_mpat_eth_rspan_dip* 8418 * Destination IP address. The IP version is configured by protocol. 8419 * Access: RW 8420 */ 8421 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8422 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8423 8424 /* reg_mpat_eth_rspan_sip* 8425 * Source IP address. The IP version is configured by protocol. 8426 * Access: RW 8427 */ 8428 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8429 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8430 8431 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8432 u16 system_port, bool e, 8433 enum mlxsw_reg_mpat_span_type span_type) 8434 { 8435 MLXSW_REG_ZERO(mpat, payload); 8436 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8437 mlxsw_reg_mpat_system_port_set(payload, system_port); 8438 mlxsw_reg_mpat_e_set(payload, e); 8439 mlxsw_reg_mpat_qos_set(payload, 1); 8440 mlxsw_reg_mpat_be_set(payload, 1); 8441 mlxsw_reg_mpat_span_type_set(payload, span_type); 8442 } 8443 8444 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8445 { 8446 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8447 } 8448 8449 static inline void 8450 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8451 enum mlxsw_reg_mpat_eth_rspan_version version, 8452 const char *mac, 8453 bool tp) 8454 { 8455 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8456 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8457 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8458 } 8459 8460 static inline void 8461 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8462 const char *smac, 8463 u32 sip, u32 dip) 8464 { 8465 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8466 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8467 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8468 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8469 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8470 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8471 } 8472 8473 static inline void 8474 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8475 const char *smac, 8476 struct in6_addr sip, struct in6_addr dip) 8477 { 8478 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8479 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8480 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8481 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8482 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8483 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8484 } 8485 8486 /* MPAR - Monitoring Port Analyzer Register 8487 * ---------------------------------------- 8488 * MPAR register is used to query and configure the port analyzer port mirroring 8489 * properties. 8490 */ 8491 #define MLXSW_REG_MPAR_ID 0x901B 8492 #define MLXSW_REG_MPAR_LEN 0x08 8493 8494 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8495 8496 /* reg_mpar_local_port 8497 * The local port to mirror the packets from. 8498 * Access: Index 8499 */ 8500 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8501 8502 enum mlxsw_reg_mpar_i_e { 8503 MLXSW_REG_MPAR_TYPE_EGRESS, 8504 MLXSW_REG_MPAR_TYPE_INGRESS, 8505 }; 8506 8507 /* reg_mpar_i_e 8508 * Ingress/Egress 8509 * Access: Index 8510 */ 8511 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8512 8513 /* reg_mpar_enable 8514 * Enable mirroring 8515 * By default, port mirroring is disabled for all ports. 8516 * Access: RW 8517 */ 8518 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8519 8520 /* reg_mpar_pa_id 8521 * Port Analyzer ID. 8522 * Access: RW 8523 */ 8524 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8525 8526 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8527 enum mlxsw_reg_mpar_i_e i_e, 8528 bool enable, u8 pa_id) 8529 { 8530 MLXSW_REG_ZERO(mpar, payload); 8531 mlxsw_reg_mpar_local_port_set(payload, local_port); 8532 mlxsw_reg_mpar_enable_set(payload, enable); 8533 mlxsw_reg_mpar_i_e_set(payload, i_e); 8534 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8535 } 8536 8537 /* MRSR - Management Reset and Shutdown Register 8538 * --------------------------------------------- 8539 * MRSR register is used to reset or shutdown the switch or 8540 * the entire system (when applicable). 8541 */ 8542 #define MLXSW_REG_MRSR_ID 0x9023 8543 #define MLXSW_REG_MRSR_LEN 0x08 8544 8545 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8546 8547 /* reg_mrsr_command 8548 * Reset/shutdown command 8549 * 0 - do nothing 8550 * 1 - software reset 8551 * Access: WO 8552 */ 8553 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8554 8555 static inline void mlxsw_reg_mrsr_pack(char *payload) 8556 { 8557 MLXSW_REG_ZERO(mrsr, payload); 8558 mlxsw_reg_mrsr_command_set(payload, 1); 8559 } 8560 8561 /* MLCR - Management LED Control Register 8562 * -------------------------------------- 8563 * Controls the system LEDs. 8564 */ 8565 #define MLXSW_REG_MLCR_ID 0x902B 8566 #define MLXSW_REG_MLCR_LEN 0x0C 8567 8568 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8569 8570 /* reg_mlcr_local_port 8571 * Local port number. 8572 * Access: RW 8573 */ 8574 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8575 8576 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8577 8578 /* reg_mlcr_beacon_duration 8579 * Duration of the beacon to be active, in seconds. 8580 * 0x0 - Will turn off the beacon. 8581 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8582 * Access: RW 8583 */ 8584 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8585 8586 /* reg_mlcr_beacon_remain 8587 * Remaining duration of the beacon, in seconds. 8588 * 0xFFFF indicates an infinite amount of time. 8589 * Access: RO 8590 */ 8591 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8592 8593 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8594 bool active) 8595 { 8596 MLXSW_REG_ZERO(mlcr, payload); 8597 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8598 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8599 MLXSW_REG_MLCR_DURATION_MAX : 0); 8600 } 8601 8602 /* MCQI - Management Component Query Information 8603 * --------------------------------------------- 8604 * This register allows querying information about firmware components. 8605 */ 8606 #define MLXSW_REG_MCQI_ID 0x9061 8607 #define MLXSW_REG_MCQI_BASE_LEN 0x18 8608 #define MLXSW_REG_MCQI_CAP_LEN 0x14 8609 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 8610 8611 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 8612 8613 /* reg_mcqi_component_index 8614 * Index of the accessed component. 8615 * Access: Index 8616 */ 8617 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 8618 8619 enum mlxfw_reg_mcqi_info_type { 8620 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 8621 }; 8622 8623 /* reg_mcqi_info_type 8624 * Component properties set. 8625 * Access: RW 8626 */ 8627 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 8628 8629 /* reg_mcqi_offset 8630 * The requested/returned data offset from the section start, given in bytes. 8631 * Must be DWORD aligned. 8632 * Access: RW 8633 */ 8634 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 8635 8636 /* reg_mcqi_data_size 8637 * The requested/returned data size, given in bytes. If data_size is not DWORD 8638 * aligned, the last bytes are zero padded. 8639 * Access: RW 8640 */ 8641 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 8642 8643 /* reg_mcqi_cap_max_component_size 8644 * Maximum size for this component, given in bytes. 8645 * Access: RO 8646 */ 8647 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 8648 8649 /* reg_mcqi_cap_log_mcda_word_size 8650 * Log 2 of the access word size in bytes. Read and write access must be aligned 8651 * to the word size. Write access must be done for an integer number of words. 8652 * Access: RO 8653 */ 8654 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 8655 8656 /* reg_mcqi_cap_mcda_max_write_size 8657 * Maximal write size for MCDA register 8658 * Access: RO 8659 */ 8660 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 8661 8662 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 8663 { 8664 MLXSW_REG_ZERO(mcqi, payload); 8665 mlxsw_reg_mcqi_component_index_set(payload, component_index); 8666 mlxsw_reg_mcqi_info_type_set(payload, 8667 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 8668 mlxsw_reg_mcqi_offset_set(payload, 0); 8669 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 8670 } 8671 8672 static inline void mlxsw_reg_mcqi_unpack(char *payload, 8673 u32 *p_cap_max_component_size, 8674 u8 *p_cap_log_mcda_word_size, 8675 u16 *p_cap_mcda_max_write_size) 8676 { 8677 *p_cap_max_component_size = 8678 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 8679 *p_cap_log_mcda_word_size = 8680 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 8681 *p_cap_mcda_max_write_size = 8682 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 8683 } 8684 8685 /* MCC - Management Component Control 8686 * ---------------------------------- 8687 * Controls the firmware component and updates the FSM. 8688 */ 8689 #define MLXSW_REG_MCC_ID 0x9062 8690 #define MLXSW_REG_MCC_LEN 0x1C 8691 8692 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 8693 8694 enum mlxsw_reg_mcc_instruction { 8695 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 8696 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 8697 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 8698 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 8699 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 8700 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 8701 }; 8702 8703 /* reg_mcc_instruction 8704 * Command to be executed by the FSM. 8705 * Applicable for write operation only. 8706 * Access: RW 8707 */ 8708 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 8709 8710 /* reg_mcc_component_index 8711 * Index of the accessed component. Applicable only for commands that 8712 * refer to components. Otherwise, this field is reserved. 8713 * Access: Index 8714 */ 8715 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 8716 8717 /* reg_mcc_update_handle 8718 * Token representing the current flow executed by the FSM. 8719 * Access: WO 8720 */ 8721 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 8722 8723 /* reg_mcc_error_code 8724 * Indicates the successful completion of the instruction, or the reason it 8725 * failed 8726 * Access: RO 8727 */ 8728 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 8729 8730 /* reg_mcc_control_state 8731 * Current FSM state 8732 * Access: RO 8733 */ 8734 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 8735 8736 /* reg_mcc_component_size 8737 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 8738 * the size may shorten the update time. Value 0x0 means that size is 8739 * unspecified. 8740 * Access: WO 8741 */ 8742 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 8743 8744 static inline void mlxsw_reg_mcc_pack(char *payload, 8745 enum mlxsw_reg_mcc_instruction instr, 8746 u16 component_index, u32 update_handle, 8747 u32 component_size) 8748 { 8749 MLXSW_REG_ZERO(mcc, payload); 8750 mlxsw_reg_mcc_instruction_set(payload, instr); 8751 mlxsw_reg_mcc_component_index_set(payload, component_index); 8752 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 8753 mlxsw_reg_mcc_component_size_set(payload, component_size); 8754 } 8755 8756 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 8757 u8 *p_error_code, u8 *p_control_state) 8758 { 8759 if (p_update_handle) 8760 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 8761 if (p_error_code) 8762 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 8763 if (p_control_state) 8764 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 8765 } 8766 8767 /* MCDA - Management Component Data Access 8768 * --------------------------------------- 8769 * This register allows reading and writing a firmware component. 8770 */ 8771 #define MLXSW_REG_MCDA_ID 0x9063 8772 #define MLXSW_REG_MCDA_BASE_LEN 0x10 8773 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 8774 #define MLXSW_REG_MCDA_LEN \ 8775 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 8776 8777 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 8778 8779 /* reg_mcda_update_handle 8780 * Token representing the current flow executed by the FSM. 8781 * Access: RW 8782 */ 8783 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 8784 8785 /* reg_mcda_offset 8786 * Offset of accessed address relative to component start. Accesses must be in 8787 * accordance to log_mcda_word_size in MCQI reg. 8788 * Access: RW 8789 */ 8790 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 8791 8792 /* reg_mcda_size 8793 * Size of the data accessed, given in bytes. 8794 * Access: RW 8795 */ 8796 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 8797 8798 /* reg_mcda_data 8799 * Data block accessed. 8800 * Access: RW 8801 */ 8802 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 8803 8804 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 8805 u32 offset, u16 size, u8 *data) 8806 { 8807 int i; 8808 8809 MLXSW_REG_ZERO(mcda, payload); 8810 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 8811 mlxsw_reg_mcda_offset_set(payload, offset); 8812 mlxsw_reg_mcda_size_set(payload, size); 8813 8814 for (i = 0; i < size / 4; i++) 8815 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 8816 } 8817 8818 /* MPSC - Monitoring Packet Sampling Configuration Register 8819 * -------------------------------------------------------- 8820 * MPSC Register is used to configure the Packet Sampling mechanism. 8821 */ 8822 #define MLXSW_REG_MPSC_ID 0x9080 8823 #define MLXSW_REG_MPSC_LEN 0x1C 8824 8825 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 8826 8827 /* reg_mpsc_local_port 8828 * Local port number 8829 * Not supported for CPU port 8830 * Access: Index 8831 */ 8832 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 8833 8834 /* reg_mpsc_e 8835 * Enable sampling on port local_port 8836 * Access: RW 8837 */ 8838 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 8839 8840 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 8841 8842 /* reg_mpsc_rate 8843 * Sampling rate = 1 out of rate packets (with randomization around 8844 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 8845 * Access: RW 8846 */ 8847 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 8848 8849 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 8850 u32 rate) 8851 { 8852 MLXSW_REG_ZERO(mpsc, payload); 8853 mlxsw_reg_mpsc_local_port_set(payload, local_port); 8854 mlxsw_reg_mpsc_e_set(payload, e); 8855 mlxsw_reg_mpsc_rate_set(payload, rate); 8856 } 8857 8858 /* MGPC - Monitoring General Purpose Counter Set Register 8859 * The MGPC register retrieves and sets the General Purpose Counter Set. 8860 */ 8861 #define MLXSW_REG_MGPC_ID 0x9081 8862 #define MLXSW_REG_MGPC_LEN 0x18 8863 8864 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 8865 8866 /* reg_mgpc_counter_set_type 8867 * Counter set type. 8868 * Access: OP 8869 */ 8870 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 8871 8872 /* reg_mgpc_counter_index 8873 * Counter index. 8874 * Access: Index 8875 */ 8876 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 8877 8878 enum mlxsw_reg_mgpc_opcode { 8879 /* Nop */ 8880 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 8881 /* Clear counters */ 8882 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 8883 }; 8884 8885 /* reg_mgpc_opcode 8886 * Opcode. 8887 * Access: OP 8888 */ 8889 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 8890 8891 /* reg_mgpc_byte_counter 8892 * Byte counter value. 8893 * Access: RW 8894 */ 8895 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 8896 8897 /* reg_mgpc_packet_counter 8898 * Packet counter value. 8899 * Access: RW 8900 */ 8901 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 8902 8903 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 8904 enum mlxsw_reg_mgpc_opcode opcode, 8905 enum mlxsw_reg_flow_counter_set_type set_type) 8906 { 8907 MLXSW_REG_ZERO(mgpc, payload); 8908 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 8909 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 8910 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8911 } 8912 8913 /* MPRS - Monitoring Parsing State Register 8914 * ---------------------------------------- 8915 * The MPRS register is used for setting up the parsing for hash, 8916 * policy-engine and routing. 8917 */ 8918 #define MLXSW_REG_MPRS_ID 0x9083 8919 #define MLXSW_REG_MPRS_LEN 0x14 8920 8921 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 8922 8923 /* reg_mprs_parsing_depth 8924 * Minimum parsing depth. 8925 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 8926 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 8927 * Access: RW 8928 */ 8929 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 8930 8931 /* reg_mprs_parsing_en 8932 * Parsing enable. 8933 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 8934 * NVGRE. Default is enabled. Reserved when SwitchX-2. 8935 * Access: RW 8936 */ 8937 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 8938 8939 /* reg_mprs_vxlan_udp_dport 8940 * VxLAN UDP destination port. 8941 * Used for identifying VxLAN packets and for dport field in 8942 * encapsulation. Default is 4789. 8943 * Access: RW 8944 */ 8945 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 8946 8947 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 8948 u16 vxlan_udp_dport) 8949 { 8950 MLXSW_REG_ZERO(mprs, payload); 8951 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 8952 mlxsw_reg_mprs_parsing_en_set(payload, true); 8953 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 8954 } 8955 8956 /* TNGCR - Tunneling NVE General Configuration Register 8957 * ---------------------------------------------------- 8958 * The TNGCR register is used for setting up the NVE Tunneling configuration. 8959 */ 8960 #define MLXSW_REG_TNGCR_ID 0xA001 8961 #define MLXSW_REG_TNGCR_LEN 0x44 8962 8963 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 8964 8965 enum mlxsw_reg_tngcr_type { 8966 MLXSW_REG_TNGCR_TYPE_VXLAN, 8967 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 8968 MLXSW_REG_TNGCR_TYPE_GENEVE, 8969 MLXSW_REG_TNGCR_TYPE_NVGRE, 8970 }; 8971 8972 /* reg_tngcr_type 8973 * Tunnel type for encapsulation and decapsulation. The types are mutually 8974 * exclusive. 8975 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 8976 * Access: RW 8977 */ 8978 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 8979 8980 /* reg_tngcr_nve_valid 8981 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 8982 * Access: RW 8983 */ 8984 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 8985 8986 /* reg_tngcr_nve_ttl_uc 8987 * The TTL for NVE tunnel encapsulation underlay unicast packets. 8988 * Access: RW 8989 */ 8990 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 8991 8992 /* reg_tngcr_nve_ttl_mc 8993 * The TTL for NVE tunnel encapsulation underlay multicast packets. 8994 * Access: RW 8995 */ 8996 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 8997 8998 enum { 8999 /* Do not copy flow label. Calculate flow label using nve_flh. */ 9000 MLXSW_REG_TNGCR_FL_NO_COPY, 9001 /* Copy flow label from inner packet if packet is IPv6 and 9002 * encapsulation is by IPv6. Otherwise, calculate flow label using 9003 * nve_flh. 9004 */ 9005 MLXSW_REG_TNGCR_FL_COPY, 9006 }; 9007 9008 /* reg_tngcr_nve_flc 9009 * For NVE tunnel encapsulation: Flow label copy from inner packet. 9010 * Access: RW 9011 */ 9012 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 9013 9014 enum { 9015 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 9016 * uses {nve_fl_prefix, nve_fl_suffix}. 9017 */ 9018 MLXSW_REG_TNGCR_FL_NO_HASH, 9019 /* 8 LSBs of the flow label are calculated from ECMP hash of the 9020 * inner packet. 12 MSBs are configured by nve_fl_prefix. 9021 */ 9022 MLXSW_REG_TNGCR_FL_HASH, 9023 }; 9024 9025 /* reg_tngcr_nve_flh 9026 * NVE flow label hash. 9027 * Access: RW 9028 */ 9029 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 9030 9031 /* reg_tngcr_nve_fl_prefix 9032 * NVE flow label prefix. Constant 12 MSBs of the flow label. 9033 * Access: RW 9034 */ 9035 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 9036 9037 /* reg_tngcr_nve_fl_suffix 9038 * NVE flow label suffix. Constant 8 LSBs of the flow label. 9039 * Reserved when nve_flh=1 and for Spectrum. 9040 * Access: RW 9041 */ 9042 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 9043 9044 enum { 9045 /* Source UDP port is fixed (default '0') */ 9046 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 9047 /* Source UDP port is calculated based on hash */ 9048 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 9049 }; 9050 9051 /* reg_tngcr_nve_udp_sport_type 9052 * NVE UDP source port type. 9053 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 9054 * When the source UDP port is calculated based on hash, then the 8 LSBs 9055 * are calculated from hash the 8 MSBs are configured by 9056 * nve_udp_sport_prefix. 9057 * Access: RW 9058 */ 9059 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 9060 9061 /* reg_tngcr_nve_udp_sport_prefix 9062 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 9063 * Reserved when NVE type is NVGRE. 9064 * Access: RW 9065 */ 9066 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 9067 9068 /* reg_tngcr_nve_group_size_mc 9069 * The amount of sequential linked lists of MC entries. The first linked 9070 * list is configured by SFD.underlay_mc_ptr. 9071 * Valid values: 1, 2, 4, 8, 16, 32, 64 9072 * The linked list are configured by TNUMT. 9073 * The hash is set by LAG hash. 9074 * Access: RW 9075 */ 9076 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 9077 9078 /* reg_tngcr_nve_group_size_flood 9079 * The amount of sequential linked lists of flooding entries. The first 9080 * linked list is configured by SFMR.nve_tunnel_flood_ptr 9081 * Valid values: 1, 2, 4, 8, 16, 32, 64 9082 * The linked list are configured by TNUMT. 9083 * The hash is set by LAG hash. 9084 * Access: RW 9085 */ 9086 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 9087 9088 /* reg_tngcr_learn_enable 9089 * During decapsulation, whether to learn from NVE port. 9090 * Reserved when Spectrum-2. See TNPC. 9091 * Access: RW 9092 */ 9093 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 9094 9095 /* reg_tngcr_underlay_virtual_router 9096 * Underlay virtual router. 9097 * Reserved when Spectrum-2. 9098 * Access: RW 9099 */ 9100 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 9101 9102 /* reg_tngcr_underlay_rif 9103 * Underlay ingress router interface. RIF type should be loopback generic. 9104 * Reserved when Spectrum. 9105 * Access: RW 9106 */ 9107 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 9108 9109 /* reg_tngcr_usipv4 9110 * Underlay source IPv4 address of the NVE. 9111 * Access: RW 9112 */ 9113 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 9114 9115 /* reg_tngcr_usipv6 9116 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 9117 * modified under traffic of NVE tunneling encapsulation. 9118 * Access: RW 9119 */ 9120 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 9121 9122 static inline void mlxsw_reg_tngcr_pack(char *payload, 9123 enum mlxsw_reg_tngcr_type type, 9124 bool valid, u8 ttl) 9125 { 9126 MLXSW_REG_ZERO(tngcr, payload); 9127 mlxsw_reg_tngcr_type_set(payload, type); 9128 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 9129 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 9130 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 9131 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 9132 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 9133 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 9134 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 9135 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 9136 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 9137 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 9138 } 9139 9140 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 9141 * ------------------------------------------------------- 9142 * The TNUMT register is for building the underlay MC table. It is used 9143 * for MC, flooding and BC traffic into the NVE tunnel. 9144 */ 9145 #define MLXSW_REG_TNUMT_ID 0xA003 9146 #define MLXSW_REG_TNUMT_LEN 0x20 9147 9148 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 9149 9150 enum mlxsw_reg_tnumt_record_type { 9151 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 9152 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 9153 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 9154 }; 9155 9156 /* reg_tnumt_record_type 9157 * Record type. 9158 * Access: RW 9159 */ 9160 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 9161 9162 enum mlxsw_reg_tnumt_tunnel_port { 9163 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 9164 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 9165 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 9166 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 9167 }; 9168 9169 /* reg_tnumt_tunnel_port 9170 * Tunnel port. 9171 * Access: RW 9172 */ 9173 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 9174 9175 /* reg_tnumt_underlay_mc_ptr 9176 * Index to the underlay multicast table. 9177 * For Spectrum the index is to the KVD linear. 9178 * Access: Index 9179 */ 9180 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 9181 9182 /* reg_tnumt_vnext 9183 * The next_underlay_mc_ptr is valid. 9184 * Access: RW 9185 */ 9186 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 9187 9188 /* reg_tnumt_next_underlay_mc_ptr 9189 * The next index to the underlay multicast table. 9190 * Access: RW 9191 */ 9192 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 9193 9194 /* reg_tnumt_record_size 9195 * Number of IP addresses in the record. 9196 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 9197 * Access: RW 9198 */ 9199 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 9200 9201 /* reg_tnumt_udip 9202 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 9203 * Access: RW 9204 */ 9205 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 9206 9207 /* reg_tnumt_udip_ptr 9208 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 9209 * i >= size. The IPv6 addresses are configured by RIPS. 9210 * Access: RW 9211 */ 9212 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 9213 9214 static inline void mlxsw_reg_tnumt_pack(char *payload, 9215 enum mlxsw_reg_tnumt_record_type type, 9216 enum mlxsw_reg_tnumt_tunnel_port tport, 9217 u32 underlay_mc_ptr, bool vnext, 9218 u32 next_underlay_mc_ptr, 9219 u8 record_size) 9220 { 9221 MLXSW_REG_ZERO(tnumt, payload); 9222 mlxsw_reg_tnumt_record_type_set(payload, type); 9223 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 9224 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 9225 mlxsw_reg_tnumt_vnext_set(payload, vnext); 9226 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 9227 mlxsw_reg_tnumt_record_size_set(payload, record_size); 9228 } 9229 9230 /* TNQCR - Tunneling NVE QoS Configuration Register 9231 * ------------------------------------------------ 9232 * The TNQCR register configures how QoS is set in encapsulation into the 9233 * underlay network. 9234 */ 9235 #define MLXSW_REG_TNQCR_ID 0xA010 9236 #define MLXSW_REG_TNQCR_LEN 0x0C 9237 9238 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 9239 9240 /* reg_tnqcr_enc_set_dscp 9241 * For encapsulation: How to set DSCP field: 9242 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 9243 * (outer) IP header. If there is no IP header, use TNQDR.dscp 9244 * 1 - Set the DSCP field as TNQDR.dscp 9245 * Access: RW 9246 */ 9247 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 9248 9249 static inline void mlxsw_reg_tnqcr_pack(char *payload) 9250 { 9251 MLXSW_REG_ZERO(tnqcr, payload); 9252 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 9253 } 9254 9255 /* TNQDR - Tunneling NVE QoS Default Register 9256 * ------------------------------------------ 9257 * The TNQDR register configures the default QoS settings for NVE 9258 * encapsulation. 9259 */ 9260 #define MLXSW_REG_TNQDR_ID 0xA011 9261 #define MLXSW_REG_TNQDR_LEN 0x08 9262 9263 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 9264 9265 /* reg_tnqdr_local_port 9266 * Local port number (receive port). CPU port is supported. 9267 * Access: Index 9268 */ 9269 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 9270 9271 /* reg_tnqdr_dscp 9272 * For encapsulation, the default DSCP. 9273 * Access: RW 9274 */ 9275 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 9276 9277 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 9278 { 9279 MLXSW_REG_ZERO(tnqdr, payload); 9280 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 9281 mlxsw_reg_tnqdr_dscp_set(payload, 0); 9282 } 9283 9284 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 9285 * -------------------------------------------------------- 9286 * The TNEEM register maps ECN of the IP header at the ingress to the 9287 * encapsulation to the ECN of the underlay network. 9288 */ 9289 #define MLXSW_REG_TNEEM_ID 0xA012 9290 #define MLXSW_REG_TNEEM_LEN 0x0C 9291 9292 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 9293 9294 /* reg_tneem_overlay_ecn 9295 * ECN of the IP header in the overlay network. 9296 * Access: Index 9297 */ 9298 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 9299 9300 /* reg_tneem_underlay_ecn 9301 * ECN of the IP header in the underlay network. 9302 * Access: RW 9303 */ 9304 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 9305 9306 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 9307 u8 underlay_ecn) 9308 { 9309 MLXSW_REG_ZERO(tneem, payload); 9310 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 9311 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 9312 } 9313 9314 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 9315 * -------------------------------------------------------- 9316 * The TNDEM register configures the actions that are done in the 9317 * decapsulation. 9318 */ 9319 #define MLXSW_REG_TNDEM_ID 0xA013 9320 #define MLXSW_REG_TNDEM_LEN 0x0C 9321 9322 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 9323 9324 /* reg_tndem_underlay_ecn 9325 * ECN field of the IP header in the underlay network. 9326 * Access: Index 9327 */ 9328 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 9329 9330 /* reg_tndem_overlay_ecn 9331 * ECN field of the IP header in the overlay network. 9332 * Access: Index 9333 */ 9334 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 9335 9336 /* reg_tndem_eip_ecn 9337 * Egress IP ECN. ECN field of the IP header of the packet which goes out 9338 * from the decapsulation. 9339 * Access: RW 9340 */ 9341 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 9342 9343 /* reg_tndem_trap_en 9344 * Trap enable: 9345 * 0 - No trap due to decap ECN 9346 * 1 - Trap enable with trap_id 9347 * Access: RW 9348 */ 9349 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 9350 9351 /* reg_tndem_trap_id 9352 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 9353 * Reserved when trap_en is '0'. 9354 * Access: RW 9355 */ 9356 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 9357 9358 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 9359 u8 overlay_ecn, u8 ecn, bool trap_en, 9360 u16 trap_id) 9361 { 9362 MLXSW_REG_ZERO(tndem, payload); 9363 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 9364 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 9365 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 9366 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 9367 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 9368 } 9369 9370 /* TNPC - Tunnel Port Configuration Register 9371 * ----------------------------------------- 9372 * The TNPC register is used for tunnel port configuration. 9373 * Reserved when Spectrum. 9374 */ 9375 #define MLXSW_REG_TNPC_ID 0xA020 9376 #define MLXSW_REG_TNPC_LEN 0x18 9377 9378 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 9379 9380 enum mlxsw_reg_tnpc_tunnel_port { 9381 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 9382 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 9383 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 9384 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 9385 }; 9386 9387 /* reg_tnpc_tunnel_port 9388 * Tunnel port. 9389 * Access: Index 9390 */ 9391 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 9392 9393 /* reg_tnpc_learn_enable_v6 9394 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 9395 * Access: RW 9396 */ 9397 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 9398 9399 /* reg_tnpc_learn_enable_v4 9400 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 9401 * Access: RW 9402 */ 9403 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 9404 9405 static inline void mlxsw_reg_tnpc_pack(char *payload, 9406 enum mlxsw_reg_tnpc_tunnel_port tport, 9407 bool learn_enable) 9408 { 9409 MLXSW_REG_ZERO(tnpc, payload); 9410 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 9411 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 9412 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 9413 } 9414 9415 /* TIGCR - Tunneling IPinIP General Configuration Register 9416 * ------------------------------------------------------- 9417 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 9418 */ 9419 #define MLXSW_REG_TIGCR_ID 0xA801 9420 #define MLXSW_REG_TIGCR_LEN 0x10 9421 9422 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 9423 9424 /* reg_tigcr_ipip_ttlc 9425 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 9426 * header. 9427 * Access: RW 9428 */ 9429 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 9430 9431 /* reg_tigcr_ipip_ttl_uc 9432 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 9433 * reg_tigcr_ipip_ttlc is unset. 9434 * Access: RW 9435 */ 9436 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 9437 9438 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 9439 { 9440 MLXSW_REG_ZERO(tigcr, payload); 9441 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 9442 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 9443 } 9444 9445 /* SBPR - Shared Buffer Pools Register 9446 * ----------------------------------- 9447 * The SBPR configures and retrieves the shared buffer pools and configuration. 9448 */ 9449 #define MLXSW_REG_SBPR_ID 0xB001 9450 #define MLXSW_REG_SBPR_LEN 0x14 9451 9452 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 9453 9454 /* shared direstion enum for SBPR, SBCM, SBPM */ 9455 enum mlxsw_reg_sbxx_dir { 9456 MLXSW_REG_SBXX_DIR_INGRESS, 9457 MLXSW_REG_SBXX_DIR_EGRESS, 9458 }; 9459 9460 /* reg_sbpr_dir 9461 * Direction. 9462 * Access: Index 9463 */ 9464 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 9465 9466 /* reg_sbpr_pool 9467 * Pool index. 9468 * Access: Index 9469 */ 9470 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 9471 9472 /* reg_sbpr_infi_size 9473 * Size is infinite. 9474 * Access: RW 9475 */ 9476 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 9477 9478 /* reg_sbpr_size 9479 * Pool size in buffer cells. 9480 * Reserved when infi_size = 1. 9481 * Access: RW 9482 */ 9483 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 9484 9485 enum mlxsw_reg_sbpr_mode { 9486 MLXSW_REG_SBPR_MODE_STATIC, 9487 MLXSW_REG_SBPR_MODE_DYNAMIC, 9488 }; 9489 9490 /* reg_sbpr_mode 9491 * Pool quota calculation mode. 9492 * Access: RW 9493 */ 9494 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 9495 9496 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 9497 enum mlxsw_reg_sbxx_dir dir, 9498 enum mlxsw_reg_sbpr_mode mode, u32 size, 9499 bool infi_size) 9500 { 9501 MLXSW_REG_ZERO(sbpr, payload); 9502 mlxsw_reg_sbpr_pool_set(payload, pool); 9503 mlxsw_reg_sbpr_dir_set(payload, dir); 9504 mlxsw_reg_sbpr_mode_set(payload, mode); 9505 mlxsw_reg_sbpr_size_set(payload, size); 9506 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 9507 } 9508 9509 /* SBCM - Shared Buffer Class Management Register 9510 * ---------------------------------------------- 9511 * The SBCM register configures and retrieves the shared buffer allocation 9512 * and configuration according to Port-PG, including the binding to pool 9513 * and definition of the associated quota. 9514 */ 9515 #define MLXSW_REG_SBCM_ID 0xB002 9516 #define MLXSW_REG_SBCM_LEN 0x28 9517 9518 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 9519 9520 /* reg_sbcm_local_port 9521 * Local port number. 9522 * For Ingress: excludes CPU port and Router port 9523 * For Egress: excludes IP Router 9524 * Access: Index 9525 */ 9526 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 9527 9528 /* reg_sbcm_pg_buff 9529 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 9530 * For PG buffer: range is 0..cap_max_pg_buffers - 1 9531 * For traffic class: range is 0..cap_max_tclass - 1 9532 * Note that when traffic class is in MC aware mode then the traffic 9533 * classes which are MC aware cannot be configured. 9534 * Access: Index 9535 */ 9536 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 9537 9538 /* reg_sbcm_dir 9539 * Direction. 9540 * Access: Index 9541 */ 9542 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 9543 9544 /* reg_sbcm_min_buff 9545 * Minimum buffer size for the limiter, in cells. 9546 * Access: RW 9547 */ 9548 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 9549 9550 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 9551 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 9552 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 9553 9554 /* reg_sbcm_infi_max 9555 * Max buffer is infinite. 9556 * Access: RW 9557 */ 9558 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 9559 9560 /* reg_sbcm_max_buff 9561 * When the pool associated to the port-pg/tclass is configured to 9562 * static, Maximum buffer size for the limiter configured in cells. 9563 * When the pool associated to the port-pg/tclass is configured to 9564 * dynamic, the max_buff holds the "alpha" parameter, supporting 9565 * the following values: 9566 * 0: 0 9567 * i: (1/128)*2^(i-1), for i=1..14 9568 * 0xFF: Infinity 9569 * Reserved when infi_max = 1. 9570 * Access: RW 9571 */ 9572 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 9573 9574 /* reg_sbcm_pool 9575 * Association of the port-priority to a pool. 9576 * Access: RW 9577 */ 9578 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 9579 9580 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 9581 enum mlxsw_reg_sbxx_dir dir, 9582 u32 min_buff, u32 max_buff, 9583 bool infi_max, u8 pool) 9584 { 9585 MLXSW_REG_ZERO(sbcm, payload); 9586 mlxsw_reg_sbcm_local_port_set(payload, local_port); 9587 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 9588 mlxsw_reg_sbcm_dir_set(payload, dir); 9589 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 9590 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 9591 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 9592 mlxsw_reg_sbcm_pool_set(payload, pool); 9593 } 9594 9595 /* SBPM - Shared Buffer Port Management Register 9596 * --------------------------------------------- 9597 * The SBPM register configures and retrieves the shared buffer allocation 9598 * and configuration according to Port-Pool, including the definition 9599 * of the associated quota. 9600 */ 9601 #define MLXSW_REG_SBPM_ID 0xB003 9602 #define MLXSW_REG_SBPM_LEN 0x28 9603 9604 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 9605 9606 /* reg_sbpm_local_port 9607 * Local port number. 9608 * For Ingress: excludes CPU port and Router port 9609 * For Egress: excludes IP Router 9610 * Access: Index 9611 */ 9612 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 9613 9614 /* reg_sbpm_pool 9615 * The pool associated to quota counting on the local_port. 9616 * Access: Index 9617 */ 9618 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 9619 9620 /* reg_sbpm_dir 9621 * Direction. 9622 * Access: Index 9623 */ 9624 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 9625 9626 /* reg_sbpm_buff_occupancy 9627 * Current buffer occupancy in cells. 9628 * Access: RO 9629 */ 9630 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 9631 9632 /* reg_sbpm_clr 9633 * Clear Max Buffer Occupancy 9634 * When this bit is set, max_buff_occupancy field is cleared (and a 9635 * new max value is tracked from the time the clear was performed). 9636 * Access: OP 9637 */ 9638 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 9639 9640 /* reg_sbpm_max_buff_occupancy 9641 * Maximum value of buffer occupancy in cells monitored. Cleared by 9642 * writing to the clr field. 9643 * Access: RO 9644 */ 9645 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 9646 9647 /* reg_sbpm_min_buff 9648 * Minimum buffer size for the limiter, in cells. 9649 * Access: RW 9650 */ 9651 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 9652 9653 /* reg_sbpm_max_buff 9654 * When the pool associated to the port-pg/tclass is configured to 9655 * static, Maximum buffer size for the limiter configured in cells. 9656 * When the pool associated to the port-pg/tclass is configured to 9657 * dynamic, the max_buff holds the "alpha" parameter, supporting 9658 * the following values: 9659 * 0: 0 9660 * i: (1/128)*2^(i-1), for i=1..14 9661 * 0xFF: Infinity 9662 * Access: RW 9663 */ 9664 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 9665 9666 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 9667 enum mlxsw_reg_sbxx_dir dir, bool clr, 9668 u32 min_buff, u32 max_buff) 9669 { 9670 MLXSW_REG_ZERO(sbpm, payload); 9671 mlxsw_reg_sbpm_local_port_set(payload, local_port); 9672 mlxsw_reg_sbpm_pool_set(payload, pool); 9673 mlxsw_reg_sbpm_dir_set(payload, dir); 9674 mlxsw_reg_sbpm_clr_set(payload, clr); 9675 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 9676 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 9677 } 9678 9679 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 9680 u32 *p_max_buff_occupancy) 9681 { 9682 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 9683 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 9684 } 9685 9686 /* SBMM - Shared Buffer Multicast Management Register 9687 * -------------------------------------------------- 9688 * The SBMM register configures and retrieves the shared buffer allocation 9689 * and configuration for MC packets according to Switch-Priority, including 9690 * the binding to pool and definition of the associated quota. 9691 */ 9692 #define MLXSW_REG_SBMM_ID 0xB004 9693 #define MLXSW_REG_SBMM_LEN 0x28 9694 9695 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 9696 9697 /* reg_sbmm_prio 9698 * Switch Priority. 9699 * Access: Index 9700 */ 9701 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 9702 9703 /* reg_sbmm_min_buff 9704 * Minimum buffer size for the limiter, in cells. 9705 * Access: RW 9706 */ 9707 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 9708 9709 /* reg_sbmm_max_buff 9710 * When the pool associated to the port-pg/tclass is configured to 9711 * static, Maximum buffer size for the limiter configured in cells. 9712 * When the pool associated to the port-pg/tclass is configured to 9713 * dynamic, the max_buff holds the "alpha" parameter, supporting 9714 * the following values: 9715 * 0: 0 9716 * i: (1/128)*2^(i-1), for i=1..14 9717 * 0xFF: Infinity 9718 * Access: RW 9719 */ 9720 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 9721 9722 /* reg_sbmm_pool 9723 * Association of the port-priority to a pool. 9724 * Access: RW 9725 */ 9726 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 9727 9728 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 9729 u32 max_buff, u8 pool) 9730 { 9731 MLXSW_REG_ZERO(sbmm, payload); 9732 mlxsw_reg_sbmm_prio_set(payload, prio); 9733 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 9734 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 9735 mlxsw_reg_sbmm_pool_set(payload, pool); 9736 } 9737 9738 /* SBSR - Shared Buffer Status Register 9739 * ------------------------------------ 9740 * The SBSR register retrieves the shared buffer occupancy according to 9741 * Port-Pool. Note that this register enables reading a large amount of data. 9742 * It is the user's responsibility to limit the amount of data to ensure the 9743 * response can match the maximum transfer unit. In case the response exceeds 9744 * the maximum transport unit, it will be truncated with no special notice. 9745 */ 9746 #define MLXSW_REG_SBSR_ID 0xB005 9747 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 9748 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 9749 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 9750 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 9751 MLXSW_REG_SBSR_REC_LEN * \ 9752 MLXSW_REG_SBSR_REC_MAX_COUNT) 9753 9754 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 9755 9756 /* reg_sbsr_clr 9757 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 9758 * field is cleared (and a new max value is tracked from the time the clear 9759 * was performed). 9760 * Access: OP 9761 */ 9762 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 9763 9764 /* reg_sbsr_ingress_port_mask 9765 * Bit vector for all ingress network ports. 9766 * Indicates which of the ports (for which the relevant bit is set) 9767 * are affected by the set operation. Configuration of any other port 9768 * does not change. 9769 * Access: Index 9770 */ 9771 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 9772 9773 /* reg_sbsr_pg_buff_mask 9774 * Bit vector for all switch priority groups. 9775 * Indicates which of the priorities (for which the relevant bit is set) 9776 * are affected by the set operation. Configuration of any other priority 9777 * does not change. 9778 * Range is 0..cap_max_pg_buffers - 1 9779 * Access: Index 9780 */ 9781 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 9782 9783 /* reg_sbsr_egress_port_mask 9784 * Bit vector for all egress network ports. 9785 * Indicates which of the ports (for which the relevant bit is set) 9786 * are affected by the set operation. Configuration of any other port 9787 * does not change. 9788 * Access: Index 9789 */ 9790 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 9791 9792 /* reg_sbsr_tclass_mask 9793 * Bit vector for all traffic classes. 9794 * Indicates which of the traffic classes (for which the relevant bit is 9795 * set) are affected by the set operation. Configuration of any other 9796 * traffic class does not change. 9797 * Range is 0..cap_max_tclass - 1 9798 * Access: Index 9799 */ 9800 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 9801 9802 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 9803 { 9804 MLXSW_REG_ZERO(sbsr, payload); 9805 mlxsw_reg_sbsr_clr_set(payload, clr); 9806 } 9807 9808 /* reg_sbsr_rec_buff_occupancy 9809 * Current buffer occupancy in cells. 9810 * Access: RO 9811 */ 9812 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9813 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 9814 9815 /* reg_sbsr_rec_max_buff_occupancy 9816 * Maximum value of buffer occupancy in cells monitored. Cleared by 9817 * writing to the clr field. 9818 * Access: RO 9819 */ 9820 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9821 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 9822 9823 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 9824 u32 *p_buff_occupancy, 9825 u32 *p_max_buff_occupancy) 9826 { 9827 *p_buff_occupancy = 9828 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 9829 *p_max_buff_occupancy = 9830 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 9831 } 9832 9833 /* SBIB - Shared Buffer Internal Buffer Register 9834 * --------------------------------------------- 9835 * The SBIB register configures per port buffers for internal use. The internal 9836 * buffers consume memory on the port buffers (note that the port buffers are 9837 * used also by PBMC). 9838 * 9839 * For Spectrum this is used for egress mirroring. 9840 */ 9841 #define MLXSW_REG_SBIB_ID 0xB006 9842 #define MLXSW_REG_SBIB_LEN 0x10 9843 9844 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 9845 9846 /* reg_sbib_local_port 9847 * Local port number 9848 * Not supported for CPU port and router port 9849 * Access: Index 9850 */ 9851 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 9852 9853 /* reg_sbib_buff_size 9854 * Units represented in cells 9855 * Allowed range is 0 to (cap_max_headroom_size - 1) 9856 * Default is 0 9857 * Access: RW 9858 */ 9859 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 9860 9861 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 9862 u32 buff_size) 9863 { 9864 MLXSW_REG_ZERO(sbib, payload); 9865 mlxsw_reg_sbib_local_port_set(payload, local_port); 9866 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 9867 } 9868 9869 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 9870 MLXSW_REG(sgcr), 9871 MLXSW_REG(spad), 9872 MLXSW_REG(smid), 9873 MLXSW_REG(sspr), 9874 MLXSW_REG(sfdat), 9875 MLXSW_REG(sfd), 9876 MLXSW_REG(sfn), 9877 MLXSW_REG(spms), 9878 MLXSW_REG(spvid), 9879 MLXSW_REG(spvm), 9880 MLXSW_REG(spaft), 9881 MLXSW_REG(sfgc), 9882 MLXSW_REG(sftr), 9883 MLXSW_REG(sfdf), 9884 MLXSW_REG(sldr), 9885 MLXSW_REG(slcr), 9886 MLXSW_REG(slcor), 9887 MLXSW_REG(spmlr), 9888 MLXSW_REG(svfa), 9889 MLXSW_REG(svpe), 9890 MLXSW_REG(sfmr), 9891 MLXSW_REG(spvmlr), 9892 MLXSW_REG(cwtp), 9893 MLXSW_REG(cwtpm), 9894 MLXSW_REG(pgcr), 9895 MLXSW_REG(ppbt), 9896 MLXSW_REG(pacl), 9897 MLXSW_REG(pagt), 9898 MLXSW_REG(ptar), 9899 MLXSW_REG(ppbs), 9900 MLXSW_REG(prcr), 9901 MLXSW_REG(pefa), 9902 MLXSW_REG(pemrbt), 9903 MLXSW_REG(ptce2), 9904 MLXSW_REG(perpt), 9905 MLXSW_REG(peabfe), 9906 MLXSW_REG(perar), 9907 MLXSW_REG(ptce3), 9908 MLXSW_REG(percr), 9909 MLXSW_REG(pererp), 9910 MLXSW_REG(iedr), 9911 MLXSW_REG(qpts), 9912 MLXSW_REG(qpcr), 9913 MLXSW_REG(qtct), 9914 MLXSW_REG(qeec), 9915 MLXSW_REG(qrwe), 9916 MLXSW_REG(qpdsm), 9917 MLXSW_REG(qpdpm), 9918 MLXSW_REG(qtctm), 9919 MLXSW_REG(pmlp), 9920 MLXSW_REG(pmtu), 9921 MLXSW_REG(ptys), 9922 MLXSW_REG(ppad), 9923 MLXSW_REG(paos), 9924 MLXSW_REG(pfcc), 9925 MLXSW_REG(ppcnt), 9926 MLXSW_REG(plib), 9927 MLXSW_REG(pptb), 9928 MLXSW_REG(pbmc), 9929 MLXSW_REG(pspa), 9930 MLXSW_REG(htgt), 9931 MLXSW_REG(hpkt), 9932 MLXSW_REG(rgcr), 9933 MLXSW_REG(ritr), 9934 MLXSW_REG(rtar), 9935 MLXSW_REG(ratr), 9936 MLXSW_REG(rtdp), 9937 MLXSW_REG(rdpm), 9938 MLXSW_REG(ricnt), 9939 MLXSW_REG(rrcr), 9940 MLXSW_REG(ralta), 9941 MLXSW_REG(ralst), 9942 MLXSW_REG(raltb), 9943 MLXSW_REG(ralue), 9944 MLXSW_REG(rauht), 9945 MLXSW_REG(raleu), 9946 MLXSW_REG(rauhtd), 9947 MLXSW_REG(rigr2), 9948 MLXSW_REG(recr2), 9949 MLXSW_REG(rmft2), 9950 MLXSW_REG(mfcr), 9951 MLXSW_REG(mfsc), 9952 MLXSW_REG(mfsm), 9953 MLXSW_REG(mfsl), 9954 MLXSW_REG(fore), 9955 MLXSW_REG(mtcap), 9956 MLXSW_REG(mtmp), 9957 MLXSW_REG(mtbr), 9958 MLXSW_REG(mcia), 9959 MLXSW_REG(mpat), 9960 MLXSW_REG(mpar), 9961 MLXSW_REG(mrsr), 9962 MLXSW_REG(mlcr), 9963 MLXSW_REG(mpsc), 9964 MLXSW_REG(mcqi), 9965 MLXSW_REG(mcc), 9966 MLXSW_REG(mcda), 9967 MLXSW_REG(mgpc), 9968 MLXSW_REG(mprs), 9969 MLXSW_REG(tngcr), 9970 MLXSW_REG(tnumt), 9971 MLXSW_REG(tnqcr), 9972 MLXSW_REG(tnqdr), 9973 MLXSW_REG(tneem), 9974 MLXSW_REG(tndem), 9975 MLXSW_REG(tnpc), 9976 MLXSW_REG(tigcr), 9977 MLXSW_REG(sbpr), 9978 MLXSW_REG(sbcm), 9979 MLXSW_REG(sbpm), 9980 MLXSW_REG(sbmm), 9981 MLXSW_REG(sbsr), 9982 MLXSW_REG(sbib), 9983 }; 9984 9985 static inline const char *mlxsw_reg_id_str(u16 reg_id) 9986 { 9987 const struct mlxsw_reg_info *reg_info; 9988 int i; 9989 9990 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 9991 reg_info = mlxsw_reg_infos[i]; 9992 if (reg_info->id == reg_id) 9993 return reg_info->name; 9994 } 9995 return "*UNKNOWN*"; 9996 } 9997 9998 /* PUDE - Port Up / Down Event 9999 * --------------------------- 10000 * Reports the operational state change of a port. 10001 */ 10002 #define MLXSW_REG_PUDE_LEN 0x10 10003 10004 /* reg_pude_swid 10005 * Switch partition ID with which to associate the port. 10006 * Access: Index 10007 */ 10008 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 10009 10010 /* reg_pude_local_port 10011 * Local port number. 10012 * Access: Index 10013 */ 10014 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 10015 10016 /* reg_pude_admin_status 10017 * Port administrative state (the desired state). 10018 * 1 - Up. 10019 * 2 - Down. 10020 * 3 - Up once. This means that in case of link failure, the port won't go 10021 * into polling mode, but will wait to be re-enabled by software. 10022 * 4 - Disabled by system. Can only be set by hardware. 10023 * Access: RO 10024 */ 10025 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 10026 10027 /* reg_pude_oper_status 10028 * Port operatioanl state. 10029 * 1 - Up. 10030 * 2 - Down. 10031 * 3 - Down by port failure. This means that the device will not let the 10032 * port up again until explicitly specified by software. 10033 * Access: RO 10034 */ 10035 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 10036 10037 #endif 10038