1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 0); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210 /* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217 { 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220 } 2221 2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224 { 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231 } 2232 2233 /* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238 #define MLXSW_REG_PTAR_ID 0x3006 2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247 enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256 }; 2257 2258 /* reg_ptar_op 2259 * Access: OP 2260 */ 2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263 /* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270 enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273 }; 2274 2275 /* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281 /* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291 /* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298 /* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307 /* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322 { 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330 } 2331 2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334 { 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336 } 2337 2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339 { 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341 } 2342 2343 /* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347 #define MLXSW_REG_PPBS_ID 0x300C 2348 #define MLXSW_REG_PPBS_LEN 0x14 2349 2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352 /* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359 /* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367 { 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371 } 2372 2373 /* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377 #define MLXSW_REG_PRCR_ID 0x300D 2378 #define MLXSW_REG_PRCR_LEN 0x40 2379 2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382 enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393 }; 2394 2395 /* reg_prcr_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400 /* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406 /* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412 /* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419 /* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425 /* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437 { 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447 } 2448 2449 /* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454 #define MLXSW_REG_PEFA_ID 0x300F 2455 #define MLXSW_REG_PEFA_LEN 0xB0 2456 2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459 /* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465 /* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474 /* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484 /* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493 { 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500 } 2501 2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503 { 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505 } 2506 2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513 #define MLXSW_REG_PEMRBT_ID 0x3014 2514 #define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518 enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521 }; 2522 2523 /* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528 /* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535 static inline void 2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538 { 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542 } 2543 2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551 #define MLXSW_REG_PTCE2_ID 0x3017 2552 #define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556 /* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562 /* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569 enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585 }; 2586 2587 /* reg_ptce2_op 2588 * Access: OP 2589 */ 2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592 /* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597 /* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606 /* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615 /* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631 /* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642 { 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649 } 2650 2651 /* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655 #define MLXSW_REG_PERPT_ID 0x3021 2656 #define MLXSW_REG_PERPT_LEN 0x80 2657 2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660 /* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667 /* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674 enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679 }; 2680 2681 /* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686 /* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695 /* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701 /* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708 /* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715 /* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721 /* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727 /* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738 { 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743 } 2744 2745 static inline void 2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750 { 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761 } 2762 2763 /* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768 #define MLXSW_REG_PERAR_ID 0x3026 2769 #define MLXSW_REG_PERAR_LEN 0x08 2770 2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773 /* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780 static inline unsigned int 2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782 { 2783 return DIV_ROUND_UP(block_num, 4); 2784 } 2785 2786 /* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798 { 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802 } 2803 2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809 #define MLXSW_REG_PTCE3_ID 0x3027 2810 #define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814 /* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820 enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831 }; 2832 2833 /* reg_ptce3_op 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838 /* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846 /* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853 /* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861 /* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867 /* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874 /* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885 /* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892 /* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904 /* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912 /* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925 /* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935 /* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950 { 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964 } 2965 2966 /* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971 #define MLXSW_REG_PERCR_ID 0x302A 2972 #define MLXSW_REG_PERCR_LEN 0x80 2973 2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976 /* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983 /* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989 /* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995 /* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004 /* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013 { 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019 } 3020 3021 /* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026 #define MLXSW_REG_PERERP_ID 0x302B 3027 #define MLXSW_REG_PERERP_LEN 0x1C 3028 3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031 /* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038 /* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044 /* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050 /* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057 /* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066 /* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075 /* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086 { 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091 } 3092 3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097 { 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105 } 3106 3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111 #define MLXSW_REG_PEABFE_ID 0x3022 3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121 /* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128 /* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 /* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156 static inline void mlxsw_reg_peabfe_pack(char *payload) 3157 { 3158 MLXSW_REG_ZERO(peabfe, payload); 3159 } 3160 3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163 { 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171 } 3172 3173 /* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179 #define MLXSW_REG_IEDR_ID 0x3804 3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189 /* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195 /* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202 /* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209 /* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216 static inline void mlxsw_reg_iedr_pack(char *payload) 3217 { 3218 MLXSW_REG_ZERO(iedr, payload); 3219 } 3220 3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224 { 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232 } 3233 3234 /* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239 #define MLXSW_REG_QPTS_ID 0x4002 3240 #define MLXSW_REG_QPTS_LEN 0x8 3241 3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244 /* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252 enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255 }; 3256 3257 /* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265 { 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270 } 3271 3272 /* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277 #define MLXSW_REG_QPCR_ID 0x4004 3278 #define MLXSW_REG_QPCR_LEN 0x28 3279 3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282 enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285 }; 3286 3287 /* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293 /* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299 /* reg_qpcr_color_aware 3300 * Is the policer aware of colors. 3301 * Must be 0 (unaware) for cpu port. 3302 * Access: RW for unbounded policer. RO for bounded policer. 3303 */ 3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3305 3306 /* reg_qpcr_bytes 3307 * Is policer limit is for bytes per sec or packets per sec. 3308 * 0 - packets 3309 * 1 - bytes 3310 * Access: RW for unbounded policer. RO for bounded policer. 3311 */ 3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3313 3314 enum mlxsw_reg_qpcr_ir_units { 3315 MLXSW_REG_QPCR_IR_UNITS_M, 3316 MLXSW_REG_QPCR_IR_UNITS_K, 3317 }; 3318 3319 /* reg_qpcr_ir_units 3320 * Policer's units for cir and eir fields (for bytes limits only) 3321 * 1 - 10^3 3322 * 0 - 10^6 3323 * Access: OP 3324 */ 3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3326 3327 enum mlxsw_reg_qpcr_rate_type { 3328 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3329 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3330 }; 3331 3332 /* reg_qpcr_rate_type 3333 * Policer can have one limit (single rate) or 2 limits with specific operation 3334 * for packets that exceed the lower rate but not the upper one. 3335 * (For cpu port must be single rate) 3336 * Access: RW for unbounded policer. RO for bounded policer. 3337 */ 3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3339 3340 /* reg_qpc_cbs 3341 * Policer's committed burst size. 3342 * The policer is working with time slices of 50 nano sec. By default every 3343 * slice is granted the proportionate share of the committed rate. If we want to 3344 * allow a slice to exceed that share (while still keeping the rate per sec) we 3345 * can allow burst. The burst size is between the default proportionate share 3346 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3347 * committed rate will result in exceeding the rate). The burst size must be a 3348 * log of 2 and will be determined by 2^cbs. 3349 * Access: RW 3350 */ 3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3352 3353 /* reg_qpcr_cir 3354 * Policer's committed rate. 3355 * The rate used for sungle rate, the lower rate for double rate. 3356 * For bytes limits, the rate will be this value * the unit from ir_units. 3357 * (Resolution error is up to 1%). 3358 * Access: RW 3359 */ 3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3361 3362 /* reg_qpcr_eir 3363 * Policer's exceed rate. 3364 * The higher rate for double rate, reserved for single rate. 3365 * Lower rate for double rate policer. 3366 * For bytes limits, the rate will be this value * the unit from ir_units. 3367 * (Resolution error is up to 1%). 3368 * Access: RW 3369 */ 3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3371 3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3373 3374 /* reg_qpcr_exceed_action. 3375 * What to do with packets between the 2 limits for double rate. 3376 * Access: RW for unbounded policer. RO for bounded policer. 3377 */ 3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3379 3380 enum mlxsw_reg_qpcr_action { 3381 /* Discard */ 3382 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3383 /* Forward and set color to red. 3384 * If the packet is intended to cpu port, it will be dropped. 3385 */ 3386 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3387 }; 3388 3389 /* reg_qpcr_violate_action 3390 * What to do with packets that cross the cir limit (for single rate) or the eir 3391 * limit (for double rate). 3392 * Access: RW for unbounded policer. RO for bounded policer. 3393 */ 3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3395 3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3397 enum mlxsw_reg_qpcr_ir_units ir_units, 3398 bool bytes, u32 cir, u16 cbs) 3399 { 3400 MLXSW_REG_ZERO(qpcr, payload); 3401 mlxsw_reg_qpcr_pid_set(payload, pid); 3402 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3403 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3404 mlxsw_reg_qpcr_violate_action_set(payload, 3405 MLXSW_REG_QPCR_ACTION_DISCARD); 3406 mlxsw_reg_qpcr_cir_set(payload, cir); 3407 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3408 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3409 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3410 } 3411 3412 /* QTCT - QoS Switch Traffic Class Table 3413 * ------------------------------------- 3414 * Configures the mapping between the packet switch priority and the 3415 * traffic class on the transmit port. 3416 */ 3417 #define MLXSW_REG_QTCT_ID 0x400A 3418 #define MLXSW_REG_QTCT_LEN 0x08 3419 3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3421 3422 /* reg_qtct_local_port 3423 * Local port number. 3424 * Access: Index 3425 * 3426 * Note: CPU port is not supported. 3427 */ 3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3429 3430 /* reg_qtct_sub_port 3431 * Virtual port within the physical port. 3432 * Should be set to 0 when virtual ports are not enabled on the port. 3433 * Access: Index 3434 */ 3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3436 3437 /* reg_qtct_switch_prio 3438 * Switch priority. 3439 * Access: Index 3440 */ 3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3442 3443 /* reg_qtct_tclass 3444 * Traffic class. 3445 * Default values: 3446 * switch_prio 0 : tclass 1 3447 * switch_prio 1 : tclass 0 3448 * switch_prio i : tclass i, for i > 1 3449 * Access: RW 3450 */ 3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3452 3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3454 u8 switch_prio, u8 tclass) 3455 { 3456 MLXSW_REG_ZERO(qtct, payload); 3457 mlxsw_reg_qtct_local_port_set(payload, local_port); 3458 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3459 mlxsw_reg_qtct_tclass_set(payload, tclass); 3460 } 3461 3462 /* QEEC - QoS ETS Element Configuration Register 3463 * --------------------------------------------- 3464 * Configures the ETS elements. 3465 */ 3466 #define MLXSW_REG_QEEC_ID 0x400D 3467 #define MLXSW_REG_QEEC_LEN 0x20 3468 3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3470 3471 /* reg_qeec_local_port 3472 * Local port number. 3473 * Access: Index 3474 * 3475 * Note: CPU port is supported. 3476 */ 3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3478 3479 enum mlxsw_reg_qeec_hr { 3480 MLXSW_REG_QEEC_HR_PORT, 3481 MLXSW_REG_QEEC_HR_GROUP, 3482 MLXSW_REG_QEEC_HR_SUBGROUP, 3483 MLXSW_REG_QEEC_HR_TC, 3484 }; 3485 3486 /* reg_qeec_element_hierarchy 3487 * 0 - Port 3488 * 1 - Group 3489 * 2 - Subgroup 3490 * 3 - Traffic Class 3491 * Access: Index 3492 */ 3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3494 3495 /* reg_qeec_element_index 3496 * The index of the element in the hierarchy. 3497 * Access: Index 3498 */ 3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3500 3501 /* reg_qeec_next_element_index 3502 * The index of the next (lower) element in the hierarchy. 3503 * Access: RW 3504 * 3505 * Note: Reserved for element_hierarchy 0. 3506 */ 3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3508 3509 /* reg_qeec_mise 3510 * Min shaper configuration enable. Enables configuration of the min 3511 * shaper on this ETS element 3512 * 0 - Disable 3513 * 1 - Enable 3514 * Access: RW 3515 */ 3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3517 3518 /* reg_qeec_ptps 3519 * PTP shaper 3520 * 0: regular shaper mode 3521 * 1: PTP oriented shaper 3522 * Allowed only for hierarchy 0 3523 * Not supported for CPU port 3524 * Note that ptps mode may affect the shaper rates of all hierarchies 3525 * Supported only on Spectrum-1 3526 * Access: RW 3527 */ 3528 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3529 3530 enum { 3531 MLXSW_REG_QEEC_BYTES_MODE, 3532 MLXSW_REG_QEEC_PACKETS_MODE, 3533 }; 3534 3535 /* reg_qeec_pb 3536 * Packets or bytes mode. 3537 * 0 - Bytes mode 3538 * 1 - Packets mode 3539 * Access: RW 3540 * 3541 * Note: Used for max shaper configuration. For Spectrum, packets mode 3542 * is supported only for traffic classes of CPU port. 3543 */ 3544 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3545 3546 /* The smallest permitted min shaper rate. */ 3547 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3548 3549 /* reg_qeec_min_shaper_rate 3550 * Min shaper information rate. 3551 * For CPU port, can only be configured for port hierarchy. 3552 * When in bytes mode, value is specified in units of 1000bps. 3553 * Access: RW 3554 */ 3555 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3556 3557 /* reg_qeec_mase 3558 * Max shaper configuration enable. Enables configuration of the max 3559 * shaper on this ETS element. 3560 * 0 - Disable 3561 * 1 - Enable 3562 * Access: RW 3563 */ 3564 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3565 3566 /* The largest max shaper value possible to disable the shaper. */ 3567 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3568 3569 /* reg_qeec_max_shaper_rate 3570 * Max shaper information rate. 3571 * For CPU port, can only be configured for port hierarchy. 3572 * When in bytes mode, value is specified in units of 1000bps. 3573 * Access: RW 3574 */ 3575 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3576 3577 /* reg_qeec_de 3578 * DWRR configuration enable. Enables configuration of the dwrr and 3579 * dwrr_weight. 3580 * 0 - Disable 3581 * 1 - Enable 3582 * Access: RW 3583 */ 3584 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3585 3586 /* reg_qeec_dwrr 3587 * Transmission selection algorithm to use on the link going down from 3588 * the ETS element. 3589 * 0 - Strict priority 3590 * 1 - DWRR 3591 * Access: RW 3592 */ 3593 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3594 3595 /* reg_qeec_dwrr_weight 3596 * DWRR weight on the link going down from the ETS element. The 3597 * percentage of bandwidth guaranteed to an ETS element within 3598 * its hierarchy. The sum of all weights across all ETS elements 3599 * within one hierarchy should be equal to 100. Reserved when 3600 * transmission selection algorithm is strict priority. 3601 * Access: RW 3602 */ 3603 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3604 3605 /* reg_qeec_max_shaper_bs 3606 * Max shaper burst size 3607 * Burst size is 2^max_shaper_bs * 512 bits 3608 * For Spectrum-1: Range is: 5..25 3609 * For Spectrum-2: Range is: 11..25 3610 * Reserved when ptps = 1 3611 * Access: RW 3612 */ 3613 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3614 3615 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3616 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3617 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3618 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 5 3619 3620 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3621 enum mlxsw_reg_qeec_hr hr, u8 index, 3622 u8 next_index) 3623 { 3624 MLXSW_REG_ZERO(qeec, payload); 3625 mlxsw_reg_qeec_local_port_set(payload, local_port); 3626 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3627 mlxsw_reg_qeec_element_index_set(payload, index); 3628 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3629 } 3630 3631 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3632 bool ptps) 3633 { 3634 MLXSW_REG_ZERO(qeec, payload); 3635 mlxsw_reg_qeec_local_port_set(payload, local_port); 3636 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3637 mlxsw_reg_qeec_ptps_set(payload, ptps); 3638 } 3639 3640 /* QRWE - QoS ReWrite Enable 3641 * ------------------------- 3642 * This register configures the rewrite enable per receive port. 3643 */ 3644 #define MLXSW_REG_QRWE_ID 0x400F 3645 #define MLXSW_REG_QRWE_LEN 0x08 3646 3647 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3648 3649 /* reg_qrwe_local_port 3650 * Local port number. 3651 * Access: Index 3652 * 3653 * Note: CPU port is supported. No support for router port. 3654 */ 3655 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3656 3657 /* reg_qrwe_dscp 3658 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3659 * Access: RW 3660 */ 3661 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3662 3663 /* reg_qrwe_pcp 3664 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3665 * Access: RW 3666 */ 3667 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3668 3669 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3670 bool rewrite_pcp, bool rewrite_dscp) 3671 { 3672 MLXSW_REG_ZERO(qrwe, payload); 3673 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3674 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3675 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3676 } 3677 3678 /* QPDSM - QoS Priority to DSCP Mapping 3679 * ------------------------------------ 3680 * QoS Priority to DSCP Mapping Register 3681 */ 3682 #define MLXSW_REG_QPDSM_ID 0x4011 3683 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3684 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3685 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3686 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3687 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3688 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3689 3690 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3691 3692 /* reg_qpdsm_local_port 3693 * Local Port. Supported for data packets from CPU port. 3694 * Access: Index 3695 */ 3696 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3697 3698 /* reg_qpdsm_prio_entry_color0_e 3699 * Enable update of the entry for color 0 and a given port. 3700 * Access: WO 3701 */ 3702 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3703 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3704 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3705 3706 /* reg_qpdsm_prio_entry_color0_dscp 3707 * DSCP field in the outer label of the packet for color 0 and a given port. 3708 * Reserved when e=0. 3709 * Access: RW 3710 */ 3711 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3712 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3713 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3714 3715 /* reg_qpdsm_prio_entry_color1_e 3716 * Enable update of the entry for color 1 and a given port. 3717 * Access: WO 3718 */ 3719 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3720 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3721 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3722 3723 /* reg_qpdsm_prio_entry_color1_dscp 3724 * DSCP field in the outer label of the packet for color 1 and a given port. 3725 * Reserved when e=0. 3726 * Access: RW 3727 */ 3728 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3729 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3730 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3731 3732 /* reg_qpdsm_prio_entry_color2_e 3733 * Enable update of the entry for color 2 and a given port. 3734 * Access: WO 3735 */ 3736 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3737 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3738 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3739 3740 /* reg_qpdsm_prio_entry_color2_dscp 3741 * DSCP field in the outer label of the packet for color 2 and a given port. 3742 * Reserved when e=0. 3743 * Access: RW 3744 */ 3745 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3746 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3747 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3748 3749 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3750 { 3751 MLXSW_REG_ZERO(qpdsm, payload); 3752 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3753 } 3754 3755 static inline void 3756 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3757 { 3758 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3759 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3760 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3761 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3762 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3763 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3764 } 3765 3766 /* QPDP - QoS Port DSCP to Priority Mapping Register 3767 * ------------------------------------------------- 3768 * This register controls the port default Switch Priority and Color. The 3769 * default Switch Priority and Color are used for frames where the trust state 3770 * uses default values. All member ports of a LAG should be configured with the 3771 * same default values. 3772 */ 3773 #define MLXSW_REG_QPDP_ID 0x4007 3774 #define MLXSW_REG_QPDP_LEN 0x8 3775 3776 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 3777 3778 /* reg_qpdp_local_port 3779 * Local Port. Supported for data packets from CPU port. 3780 * Access: Index 3781 */ 3782 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 3783 3784 /* reg_qpdp_switch_prio 3785 * Default port Switch Priority (default 0) 3786 * Access: RW 3787 */ 3788 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 3789 3790 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 3791 u8 switch_prio) 3792 { 3793 MLXSW_REG_ZERO(qpdp, payload); 3794 mlxsw_reg_qpdp_local_port_set(payload, local_port); 3795 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 3796 } 3797 3798 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3799 * -------------------------------------------------- 3800 * This register controls the mapping from DSCP field to 3801 * Switch Priority for IP packets. 3802 */ 3803 #define MLXSW_REG_QPDPM_ID 0x4013 3804 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3805 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3806 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3807 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3808 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3809 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3810 3811 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3812 3813 /* reg_qpdpm_local_port 3814 * Local Port. Supported for data packets from CPU port. 3815 * Access: Index 3816 */ 3817 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3818 3819 /* reg_qpdpm_dscp_e 3820 * Enable update of the specific entry. When cleared, the switch_prio and color 3821 * fields are ignored and the previous switch_prio and color values are 3822 * preserved. 3823 * Access: WO 3824 */ 3825 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3826 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3827 3828 /* reg_qpdpm_dscp_prio 3829 * The new Switch Priority value for the relevant DSCP value. 3830 * Access: RW 3831 */ 3832 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3833 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3834 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3835 3836 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3837 { 3838 MLXSW_REG_ZERO(qpdpm, payload); 3839 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3840 } 3841 3842 static inline void 3843 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3844 { 3845 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3846 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3847 } 3848 3849 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3850 * ------------------------------------------------------------------ 3851 * This register configures if the Switch Priority to Traffic Class mapping is 3852 * based on Multicast packet indication. If so, then multicast packets will get 3853 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3854 * QTCT. 3855 * By default, Switch Priority to Traffic Class mapping is not based on 3856 * Multicast packet indication. 3857 */ 3858 #define MLXSW_REG_QTCTM_ID 0x401A 3859 #define MLXSW_REG_QTCTM_LEN 0x08 3860 3861 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3862 3863 /* reg_qtctm_local_port 3864 * Local port number. 3865 * No support for CPU port. 3866 * Access: Index 3867 */ 3868 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3869 3870 /* reg_qtctm_mc 3871 * Multicast Mode 3872 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3873 * indication (default is 0, not based on Multicast packet indication). 3874 */ 3875 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3876 3877 static inline void 3878 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3879 { 3880 MLXSW_REG_ZERO(qtctm, payload); 3881 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3882 mlxsw_reg_qtctm_mc_set(payload, mc); 3883 } 3884 3885 /* QPSC - QoS PTP Shaper Configuration Register 3886 * -------------------------------------------- 3887 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 3888 * Supported only on Spectrum-1. 3889 */ 3890 #define MLXSW_REG_QPSC_ID 0x401B 3891 #define MLXSW_REG_QPSC_LEN 0x28 3892 3893 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 3894 3895 enum mlxsw_reg_qpsc_port_speed { 3896 MLXSW_REG_QPSC_PORT_SPEED_100M, 3897 MLXSW_REG_QPSC_PORT_SPEED_1G, 3898 MLXSW_REG_QPSC_PORT_SPEED_10G, 3899 MLXSW_REG_QPSC_PORT_SPEED_25G, 3900 }; 3901 3902 /* reg_qpsc_port_speed 3903 * Port speed. 3904 * Access: Index 3905 */ 3906 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 3907 3908 /* reg_qpsc_shaper_time_exp 3909 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3910 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3911 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3912 * Access: RW 3913 */ 3914 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 3915 3916 /* reg_qpsc_shaper_time_mantissa 3917 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3918 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3919 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3920 * Access: RW 3921 */ 3922 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 3923 3924 /* reg_qpsc_shaper_inc 3925 * Number of tokens added to shaper on each update. 3926 * Units of 8B. 3927 * Access: RW 3928 */ 3929 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 3930 3931 /* reg_qpsc_shaper_bs 3932 * Max shaper Burst size. 3933 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 3934 * Range is: 5..25 (from 2KB..2GB) 3935 * Access: RW 3936 */ 3937 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 3938 3939 /* reg_qpsc_ptsc_we 3940 * Write enable to port_to_shaper_credits. 3941 * Access: WO 3942 */ 3943 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 3944 3945 /* reg_qpsc_port_to_shaper_credits 3946 * For split ports: range 1..57 3947 * For non-split ports: range 1..112 3948 * Written only when ptsc_we is set. 3949 * Access: RW 3950 */ 3951 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 3952 3953 /* reg_qpsc_ing_timestamp_inc 3954 * Ingress timestamp increment. 3955 * 2's complement. 3956 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 3957 * value for all ports. 3958 * Same units as used by MTPPTR. 3959 * Access: RW 3960 */ 3961 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 3962 3963 /* reg_qpsc_egr_timestamp_inc 3964 * Egress timestamp increment. 3965 * 2's complement. 3966 * The timestamp of MTPPTR at egress will be incremented by this value. Global 3967 * value for all ports. 3968 * Same units as used by MTPPTR. 3969 * Access: RW 3970 */ 3971 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 3972 3973 static inline void 3974 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 3975 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 3976 u8 shaper_bs, u8 port_to_shaper_credits, 3977 int ing_timestamp_inc, int egr_timestamp_inc) 3978 { 3979 MLXSW_REG_ZERO(qpsc, payload); 3980 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 3981 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 3982 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 3983 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 3984 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 3985 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 3986 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 3987 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 3988 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 3989 } 3990 3991 /* PMLP - Ports Module to Local Port Register 3992 * ------------------------------------------ 3993 * Configures the assignment of modules to local ports. 3994 */ 3995 #define MLXSW_REG_PMLP_ID 0x5002 3996 #define MLXSW_REG_PMLP_LEN 0x40 3997 3998 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3999 4000 /* reg_pmlp_rxtx 4001 * 0 - Tx value is used for both Tx and Rx. 4002 * 1 - Rx value is taken from a separte field. 4003 * Access: RW 4004 */ 4005 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4006 4007 /* reg_pmlp_local_port 4008 * Local port number. 4009 * Access: Index 4010 */ 4011 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4012 4013 /* reg_pmlp_width 4014 * 0 - Unmap local port. 4015 * 1 - Lane 0 is used. 4016 * 2 - Lanes 0 and 1 are used. 4017 * 4 - Lanes 0, 1, 2 and 3 are used. 4018 * 8 - Lanes 0-7 are used. 4019 * Access: RW 4020 */ 4021 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4022 4023 /* reg_pmlp_module 4024 * Module number. 4025 * Access: RW 4026 */ 4027 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4028 4029 /* reg_pmlp_tx_lane 4030 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4031 * Access: RW 4032 */ 4033 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4034 4035 /* reg_pmlp_rx_lane 4036 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4037 * equal to Tx lane. 4038 * Access: RW 4039 */ 4040 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4041 4042 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4043 { 4044 MLXSW_REG_ZERO(pmlp, payload); 4045 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4046 } 4047 4048 /* PMTU - Port MTU Register 4049 * ------------------------ 4050 * Configures and reports the port MTU. 4051 */ 4052 #define MLXSW_REG_PMTU_ID 0x5003 4053 #define MLXSW_REG_PMTU_LEN 0x10 4054 4055 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4056 4057 /* reg_pmtu_local_port 4058 * Local port number. 4059 * Access: Index 4060 */ 4061 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4062 4063 /* reg_pmtu_max_mtu 4064 * Maximum MTU. 4065 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4066 * reported, otherwise the minimum between the max_mtu of the different 4067 * types is reported. 4068 * Access: RO 4069 */ 4070 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4071 4072 /* reg_pmtu_admin_mtu 4073 * MTU value to set port to. Must be smaller or equal to max_mtu. 4074 * Note: If port type is Infiniband, then port must be disabled, when its 4075 * MTU is set. 4076 * Access: RW 4077 */ 4078 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4079 4080 /* reg_pmtu_oper_mtu 4081 * The actual MTU configured on the port. Packets exceeding this size 4082 * will be dropped. 4083 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4084 * oper_mtu might be smaller than admin_mtu. 4085 * Access: RO 4086 */ 4087 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4088 4089 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4090 u16 new_mtu) 4091 { 4092 MLXSW_REG_ZERO(pmtu, payload); 4093 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4094 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4095 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4096 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4097 } 4098 4099 /* PTYS - Port Type and Speed Register 4100 * ----------------------------------- 4101 * Configures and reports the port speed type. 4102 * 4103 * Note: When set while the link is up, the changes will not take effect 4104 * until the port transitions from down to up state. 4105 */ 4106 #define MLXSW_REG_PTYS_ID 0x5004 4107 #define MLXSW_REG_PTYS_LEN 0x40 4108 4109 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4110 4111 /* an_disable_admin 4112 * Auto negotiation disable administrative configuration 4113 * 0 - Device doesn't support AN disable. 4114 * 1 - Device supports AN disable. 4115 * Access: RW 4116 */ 4117 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4118 4119 /* reg_ptys_local_port 4120 * Local port number. 4121 * Access: Index 4122 */ 4123 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4124 4125 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4126 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4127 4128 /* reg_ptys_proto_mask 4129 * Protocol mask. Indicates which protocol is used. 4130 * 0 - Infiniband. 4131 * 1 - Fibre Channel. 4132 * 2 - Ethernet. 4133 * Access: Index 4134 */ 4135 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4136 4137 enum { 4138 MLXSW_REG_PTYS_AN_STATUS_NA, 4139 MLXSW_REG_PTYS_AN_STATUS_OK, 4140 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4141 }; 4142 4143 /* reg_ptys_an_status 4144 * Autonegotiation status. 4145 * Access: RO 4146 */ 4147 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4148 4149 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4150 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4151 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) 4152 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4153 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4154 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4155 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4156 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4157 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4158 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4159 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4160 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4161 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4162 4163 /* reg_ptys_ext_eth_proto_cap 4164 * Extended Ethernet port supported speeds and protocols. 4165 * Access: RO 4166 */ 4167 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4168 4169 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4170 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4171 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4172 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4173 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4174 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 4175 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4176 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4177 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4178 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4179 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4180 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4181 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4182 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4183 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4184 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4185 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4186 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4187 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4188 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 4189 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 4190 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 4191 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4192 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4193 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4194 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4195 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4196 4197 /* reg_ptys_eth_proto_cap 4198 * Ethernet port supported speeds and protocols. 4199 * Access: RO 4200 */ 4201 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4202 4203 /* reg_ptys_ib_link_width_cap 4204 * IB port supported widths. 4205 * Access: RO 4206 */ 4207 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4208 4209 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4210 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4211 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4212 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4213 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4214 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4215 4216 /* reg_ptys_ib_proto_cap 4217 * IB port supported speeds and protocols. 4218 * Access: RO 4219 */ 4220 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4221 4222 /* reg_ptys_ext_eth_proto_admin 4223 * Extended speed and protocol to set port to. 4224 * Access: RW 4225 */ 4226 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4227 4228 /* reg_ptys_eth_proto_admin 4229 * Speed and protocol to set port to. 4230 * Access: RW 4231 */ 4232 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4233 4234 /* reg_ptys_ib_link_width_admin 4235 * IB width to set port to. 4236 * Access: RW 4237 */ 4238 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4239 4240 /* reg_ptys_ib_proto_admin 4241 * IB speeds and protocols to set port to. 4242 * Access: RW 4243 */ 4244 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4245 4246 /* reg_ptys_ext_eth_proto_oper 4247 * The extended current speed and protocol configured for the port. 4248 * Access: RO 4249 */ 4250 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4251 4252 /* reg_ptys_eth_proto_oper 4253 * The current speed and protocol configured for the port. 4254 * Access: RO 4255 */ 4256 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4257 4258 /* reg_ptys_ib_link_width_oper 4259 * The current IB width to set port to. 4260 * Access: RO 4261 */ 4262 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4263 4264 /* reg_ptys_ib_proto_oper 4265 * The current IB speed and protocol. 4266 * Access: RO 4267 */ 4268 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4269 4270 enum mlxsw_reg_ptys_connector_type { 4271 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4272 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4273 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4274 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4275 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4276 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4277 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4278 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4279 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4280 }; 4281 4282 /* reg_ptys_connector_type 4283 * Connector type indication. 4284 * Access: RO 4285 */ 4286 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4287 4288 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4289 u32 proto_admin, bool autoneg) 4290 { 4291 MLXSW_REG_ZERO(ptys, payload); 4292 mlxsw_reg_ptys_local_port_set(payload, local_port); 4293 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4294 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4295 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4296 } 4297 4298 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4299 u32 proto_admin, bool autoneg) 4300 { 4301 MLXSW_REG_ZERO(ptys, payload); 4302 mlxsw_reg_ptys_local_port_set(payload, local_port); 4303 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4304 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4305 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4306 } 4307 4308 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4309 u32 *p_eth_proto_cap, 4310 u32 *p_eth_proto_admin, 4311 u32 *p_eth_proto_oper) 4312 { 4313 if (p_eth_proto_cap) 4314 *p_eth_proto_cap = 4315 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4316 if (p_eth_proto_admin) 4317 *p_eth_proto_admin = 4318 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4319 if (p_eth_proto_oper) 4320 *p_eth_proto_oper = 4321 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4322 } 4323 4324 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4325 u32 *p_eth_proto_cap, 4326 u32 *p_eth_proto_admin, 4327 u32 *p_eth_proto_oper) 4328 { 4329 if (p_eth_proto_cap) 4330 *p_eth_proto_cap = 4331 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4332 if (p_eth_proto_admin) 4333 *p_eth_proto_admin = 4334 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4335 if (p_eth_proto_oper) 4336 *p_eth_proto_oper = 4337 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4338 } 4339 4340 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4341 u16 proto_admin, u16 link_width) 4342 { 4343 MLXSW_REG_ZERO(ptys, payload); 4344 mlxsw_reg_ptys_local_port_set(payload, local_port); 4345 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4346 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4347 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4348 } 4349 4350 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4351 u16 *p_ib_link_width_cap, 4352 u16 *p_ib_proto_oper, 4353 u16 *p_ib_link_width_oper) 4354 { 4355 if (p_ib_proto_cap) 4356 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4357 if (p_ib_link_width_cap) 4358 *p_ib_link_width_cap = 4359 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4360 if (p_ib_proto_oper) 4361 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4362 if (p_ib_link_width_oper) 4363 *p_ib_link_width_oper = 4364 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4365 } 4366 4367 /* PPAD - Port Physical Address Register 4368 * ------------------------------------- 4369 * The PPAD register configures the per port physical MAC address. 4370 */ 4371 #define MLXSW_REG_PPAD_ID 0x5005 4372 #define MLXSW_REG_PPAD_LEN 0x10 4373 4374 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4375 4376 /* reg_ppad_single_base_mac 4377 * 0: base_mac, local port should be 0 and mac[7:0] is 4378 * reserved. HW will set incremental 4379 * 1: single_mac - mac of the local_port 4380 * Access: RW 4381 */ 4382 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4383 4384 /* reg_ppad_local_port 4385 * port number, if single_base_mac = 0 then local_port is reserved 4386 * Access: RW 4387 */ 4388 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4389 4390 /* reg_ppad_mac 4391 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4392 * If single_base_mac = 1 - the per port MAC address 4393 * Access: RW 4394 */ 4395 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4396 4397 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4398 u8 local_port) 4399 { 4400 MLXSW_REG_ZERO(ppad, payload); 4401 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4402 mlxsw_reg_ppad_local_port_set(payload, local_port); 4403 } 4404 4405 /* PAOS - Ports Administrative and Operational Status Register 4406 * ----------------------------------------------------------- 4407 * Configures and retrieves per port administrative and operational status. 4408 */ 4409 #define MLXSW_REG_PAOS_ID 0x5006 4410 #define MLXSW_REG_PAOS_LEN 0x10 4411 4412 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4413 4414 /* reg_paos_swid 4415 * Switch partition ID with which to associate the port. 4416 * Note: while external ports uses unique local port numbers (and thus swid is 4417 * redundant), router ports use the same local port number where swid is the 4418 * only indication for the relevant port. 4419 * Access: Index 4420 */ 4421 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4422 4423 /* reg_paos_local_port 4424 * Local port number. 4425 * Access: Index 4426 */ 4427 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4428 4429 /* reg_paos_admin_status 4430 * Port administrative state (the desired state of the port): 4431 * 1 - Up. 4432 * 2 - Down. 4433 * 3 - Up once. This means that in case of link failure, the port won't go 4434 * into polling mode, but will wait to be re-enabled by software. 4435 * 4 - Disabled by system. Can only be set by hardware. 4436 * Access: RW 4437 */ 4438 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4439 4440 /* reg_paos_oper_status 4441 * Port operational state (the current state): 4442 * 1 - Up. 4443 * 2 - Down. 4444 * 3 - Down by port failure. This means that the device will not let the 4445 * port up again until explicitly specified by software. 4446 * Access: RO 4447 */ 4448 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4449 4450 /* reg_paos_ase 4451 * Admin state update enabled. 4452 * Access: WO 4453 */ 4454 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4455 4456 /* reg_paos_ee 4457 * Event update enable. If this bit is set, event generation will be 4458 * updated based on the e field. 4459 * Access: WO 4460 */ 4461 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4462 4463 /* reg_paos_e 4464 * Event generation on operational state change: 4465 * 0 - Do not generate event. 4466 * 1 - Generate Event. 4467 * 2 - Generate Single Event. 4468 * Access: RW 4469 */ 4470 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4471 4472 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4473 enum mlxsw_port_admin_status status) 4474 { 4475 MLXSW_REG_ZERO(paos, payload); 4476 mlxsw_reg_paos_swid_set(payload, 0); 4477 mlxsw_reg_paos_local_port_set(payload, local_port); 4478 mlxsw_reg_paos_admin_status_set(payload, status); 4479 mlxsw_reg_paos_oper_status_set(payload, 0); 4480 mlxsw_reg_paos_ase_set(payload, 1); 4481 mlxsw_reg_paos_ee_set(payload, 1); 4482 mlxsw_reg_paos_e_set(payload, 1); 4483 } 4484 4485 /* PFCC - Ports Flow Control Configuration Register 4486 * ------------------------------------------------ 4487 * Configures and retrieves the per port flow control configuration. 4488 */ 4489 #define MLXSW_REG_PFCC_ID 0x5007 4490 #define MLXSW_REG_PFCC_LEN 0x20 4491 4492 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4493 4494 /* reg_pfcc_local_port 4495 * Local port number. 4496 * Access: Index 4497 */ 4498 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4499 4500 /* reg_pfcc_pnat 4501 * Port number access type. Determines the way local_port is interpreted: 4502 * 0 - Local port number. 4503 * 1 - IB / label port number. 4504 * Access: Index 4505 */ 4506 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4507 4508 /* reg_pfcc_shl_cap 4509 * Send to higher layers capabilities: 4510 * 0 - No capability of sending Pause and PFC frames to higher layers. 4511 * 1 - Device has capability of sending Pause and PFC frames to higher 4512 * layers. 4513 * Access: RO 4514 */ 4515 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4516 4517 /* reg_pfcc_shl_opr 4518 * Send to higher layers operation: 4519 * 0 - Pause and PFC frames are handled by the port (default). 4520 * 1 - Pause and PFC frames are handled by the port and also sent to 4521 * higher layers. Only valid if shl_cap = 1. 4522 * Access: RW 4523 */ 4524 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4525 4526 /* reg_pfcc_ppan 4527 * Pause policy auto negotiation. 4528 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4529 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4530 * based on the auto-negotiation resolution. 4531 * Access: RW 4532 * 4533 * Note: The auto-negotiation advertisement is set according to pptx and 4534 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4535 */ 4536 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4537 4538 /* reg_pfcc_prio_mask_tx 4539 * Bit per priority indicating if Tx flow control policy should be 4540 * updated based on bit pfctx. 4541 * Access: WO 4542 */ 4543 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4544 4545 /* reg_pfcc_prio_mask_rx 4546 * Bit per priority indicating if Rx flow control policy should be 4547 * updated based on bit pfcrx. 4548 * Access: WO 4549 */ 4550 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4551 4552 /* reg_pfcc_pptx 4553 * Admin Pause policy on Tx. 4554 * 0 - Never generate Pause frames (default). 4555 * 1 - Generate Pause frames according to Rx buffer threshold. 4556 * Access: RW 4557 */ 4558 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4559 4560 /* reg_pfcc_aptx 4561 * Active (operational) Pause policy on Tx. 4562 * 0 - Never generate Pause frames. 4563 * 1 - Generate Pause frames according to Rx buffer threshold. 4564 * Access: RO 4565 */ 4566 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4567 4568 /* reg_pfcc_pfctx 4569 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4570 * 0 - Never generate priority Pause frames on the specified priority 4571 * (default). 4572 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4573 * the specified priority. 4574 * Access: RW 4575 * 4576 * Note: pfctx and pptx must be mutually exclusive. 4577 */ 4578 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4579 4580 /* reg_pfcc_pprx 4581 * Admin Pause policy on Rx. 4582 * 0 - Ignore received Pause frames (default). 4583 * 1 - Respect received Pause frames. 4584 * Access: RW 4585 */ 4586 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4587 4588 /* reg_pfcc_aprx 4589 * Active (operational) Pause policy on Rx. 4590 * 0 - Ignore received Pause frames. 4591 * 1 - Respect received Pause frames. 4592 * Access: RO 4593 */ 4594 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4595 4596 /* reg_pfcc_pfcrx 4597 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4598 * 0 - Ignore incoming priority Pause frames on the specified priority 4599 * (default). 4600 * 1 - Respect incoming priority Pause frames on the specified priority. 4601 * Access: RW 4602 */ 4603 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4604 4605 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4606 4607 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4608 { 4609 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4610 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4611 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4612 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4613 } 4614 4615 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4616 { 4617 MLXSW_REG_ZERO(pfcc, payload); 4618 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4619 } 4620 4621 /* PPCNT - Ports Performance Counters Register 4622 * ------------------------------------------- 4623 * The PPCNT register retrieves per port performance counters. 4624 */ 4625 #define MLXSW_REG_PPCNT_ID 0x5008 4626 #define MLXSW_REG_PPCNT_LEN 0x100 4627 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4628 4629 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4630 4631 /* reg_ppcnt_swid 4632 * For HCA: must be always 0. 4633 * Switch partition ID to associate port with. 4634 * Switch partitions are numbered from 0 to 7 inclusively. 4635 * Switch partition 254 indicates stacking ports. 4636 * Switch partition 255 indicates all switch partitions. 4637 * Only valid on Set() operation with local_port=255. 4638 * Access: Index 4639 */ 4640 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4641 4642 /* reg_ppcnt_local_port 4643 * Local port number. 4644 * 255 indicates all ports on the device, and is only allowed 4645 * for Set() operation. 4646 * Access: Index 4647 */ 4648 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4649 4650 /* reg_ppcnt_pnat 4651 * Port number access type: 4652 * 0 - Local port number 4653 * 1 - IB port number 4654 * Access: Index 4655 */ 4656 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4657 4658 enum mlxsw_reg_ppcnt_grp { 4659 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4660 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4661 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4662 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4663 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4664 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4665 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4666 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4667 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4668 }; 4669 4670 /* reg_ppcnt_grp 4671 * Performance counter group. 4672 * Group 63 indicates all groups. Only valid on Set() operation with 4673 * clr bit set. 4674 * 0x0: IEEE 802.3 Counters 4675 * 0x1: RFC 2863 Counters 4676 * 0x2: RFC 2819 Counters 4677 * 0x3: RFC 3635 Counters 4678 * 0x5: Ethernet Extended Counters 4679 * 0x6: Ethernet Discard Counters 4680 * 0x8: Link Level Retransmission Counters 4681 * 0x10: Per Priority Counters 4682 * 0x11: Per Traffic Class Counters 4683 * 0x12: Physical Layer Counters 4684 * 0x13: Per Traffic Class Congestion Counters 4685 * Access: Index 4686 */ 4687 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4688 4689 /* reg_ppcnt_clr 4690 * Clear counters. Setting the clr bit will reset the counter value 4691 * for all counters in the counter group. This bit can be set 4692 * for both Set() and Get() operation. 4693 * Access: OP 4694 */ 4695 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4696 4697 /* reg_ppcnt_prio_tc 4698 * Priority for counter set that support per priority, valid values: 0-7. 4699 * Traffic class for counter set that support per traffic class, 4700 * valid values: 0- cap_max_tclass-1 . 4701 * For HCA: cap_max_tclass is always 8. 4702 * Otherwise must be 0. 4703 * Access: Index 4704 */ 4705 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4706 4707 /* Ethernet IEEE 802.3 Counter Group */ 4708 4709 /* reg_ppcnt_a_frames_transmitted_ok 4710 * Access: RO 4711 */ 4712 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4713 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4714 4715 /* reg_ppcnt_a_frames_received_ok 4716 * Access: RO 4717 */ 4718 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4719 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4720 4721 /* reg_ppcnt_a_frame_check_sequence_errors 4722 * Access: RO 4723 */ 4724 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4725 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4726 4727 /* reg_ppcnt_a_alignment_errors 4728 * Access: RO 4729 */ 4730 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4731 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4732 4733 /* reg_ppcnt_a_octets_transmitted_ok 4734 * Access: RO 4735 */ 4736 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4737 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4738 4739 /* reg_ppcnt_a_octets_received_ok 4740 * Access: RO 4741 */ 4742 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4743 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4744 4745 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4746 * Access: RO 4747 */ 4748 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4749 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4750 4751 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4752 * Access: RO 4753 */ 4754 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4755 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4756 4757 /* reg_ppcnt_a_multicast_frames_received_ok 4758 * Access: RO 4759 */ 4760 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4761 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4762 4763 /* reg_ppcnt_a_broadcast_frames_received_ok 4764 * Access: RO 4765 */ 4766 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4767 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4768 4769 /* reg_ppcnt_a_in_range_length_errors 4770 * Access: RO 4771 */ 4772 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4773 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4774 4775 /* reg_ppcnt_a_out_of_range_length_field 4776 * Access: RO 4777 */ 4778 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4779 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4780 4781 /* reg_ppcnt_a_frame_too_long_errors 4782 * Access: RO 4783 */ 4784 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4785 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4786 4787 /* reg_ppcnt_a_symbol_error_during_carrier 4788 * Access: RO 4789 */ 4790 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4791 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4792 4793 /* reg_ppcnt_a_mac_control_frames_transmitted 4794 * Access: RO 4795 */ 4796 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4797 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4798 4799 /* reg_ppcnt_a_mac_control_frames_received 4800 * Access: RO 4801 */ 4802 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4803 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4804 4805 /* reg_ppcnt_a_unsupported_opcodes_received 4806 * Access: RO 4807 */ 4808 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4809 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4810 4811 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4812 * Access: RO 4813 */ 4814 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4815 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4816 4817 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4818 * Access: RO 4819 */ 4820 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4821 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4822 4823 /* Ethernet RFC 2863 Counter Group */ 4824 4825 /* reg_ppcnt_if_in_discards 4826 * Access: RO 4827 */ 4828 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4829 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4830 4831 /* reg_ppcnt_if_out_discards 4832 * Access: RO 4833 */ 4834 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4835 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4836 4837 /* reg_ppcnt_if_out_errors 4838 * Access: RO 4839 */ 4840 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4841 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4842 4843 /* Ethernet RFC 2819 Counter Group */ 4844 4845 /* reg_ppcnt_ether_stats_undersize_pkts 4846 * Access: RO 4847 */ 4848 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4849 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4850 4851 /* reg_ppcnt_ether_stats_oversize_pkts 4852 * Access: RO 4853 */ 4854 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4855 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4856 4857 /* reg_ppcnt_ether_stats_fragments 4858 * Access: RO 4859 */ 4860 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4861 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4862 4863 /* reg_ppcnt_ether_stats_pkts64octets 4864 * Access: RO 4865 */ 4866 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4867 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4868 4869 /* reg_ppcnt_ether_stats_pkts65to127octets 4870 * Access: RO 4871 */ 4872 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4873 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4874 4875 /* reg_ppcnt_ether_stats_pkts128to255octets 4876 * Access: RO 4877 */ 4878 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4879 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4880 4881 /* reg_ppcnt_ether_stats_pkts256to511octets 4882 * Access: RO 4883 */ 4884 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4885 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4886 4887 /* reg_ppcnt_ether_stats_pkts512to1023octets 4888 * Access: RO 4889 */ 4890 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4891 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4892 4893 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4894 * Access: RO 4895 */ 4896 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4897 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4898 4899 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4900 * Access: RO 4901 */ 4902 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4903 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4904 4905 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4906 * Access: RO 4907 */ 4908 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4909 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4910 4911 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4912 * Access: RO 4913 */ 4914 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4915 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4916 4917 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4918 * Access: RO 4919 */ 4920 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4921 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4922 4923 /* Ethernet RFC 3635 Counter Group */ 4924 4925 /* reg_ppcnt_dot3stats_fcs_errors 4926 * Access: RO 4927 */ 4928 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4929 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4930 4931 /* reg_ppcnt_dot3stats_symbol_errors 4932 * Access: RO 4933 */ 4934 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4935 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4936 4937 /* reg_ppcnt_dot3control_in_unknown_opcodes 4938 * Access: RO 4939 */ 4940 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4941 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4942 4943 /* reg_ppcnt_dot3in_pause_frames 4944 * Access: RO 4945 */ 4946 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4947 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4948 4949 /* Ethernet Extended Counter Group Counters */ 4950 4951 /* reg_ppcnt_ecn_marked 4952 * Access: RO 4953 */ 4954 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4955 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4956 4957 /* Ethernet Discard Counter Group Counters */ 4958 4959 /* reg_ppcnt_ingress_general 4960 * Access: RO 4961 */ 4962 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4963 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4964 4965 /* reg_ppcnt_ingress_policy_engine 4966 * Access: RO 4967 */ 4968 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4969 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4970 4971 /* reg_ppcnt_ingress_vlan_membership 4972 * Access: RO 4973 */ 4974 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4975 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4976 4977 /* reg_ppcnt_ingress_tag_frame_type 4978 * Access: RO 4979 */ 4980 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4981 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4982 4983 /* reg_ppcnt_egress_vlan_membership 4984 * Access: RO 4985 */ 4986 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 4987 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4988 4989 /* reg_ppcnt_loopback_filter 4990 * Access: RO 4991 */ 4992 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 4993 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4994 4995 /* reg_ppcnt_egress_general 4996 * Access: RO 4997 */ 4998 MLXSW_ITEM64(reg, ppcnt, egress_general, 4999 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5000 5001 /* reg_ppcnt_egress_hoq 5002 * Access: RO 5003 */ 5004 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5005 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5006 5007 /* reg_ppcnt_egress_policy_engine 5008 * Access: RO 5009 */ 5010 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5011 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5012 5013 /* reg_ppcnt_ingress_tx_link_down 5014 * Access: RO 5015 */ 5016 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5017 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5018 5019 /* reg_ppcnt_egress_stp_filter 5020 * Access: RO 5021 */ 5022 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5023 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5024 5025 /* reg_ppcnt_egress_sll 5026 * Access: RO 5027 */ 5028 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5029 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5030 5031 /* Ethernet Per Priority Group Counters */ 5032 5033 /* reg_ppcnt_rx_octets 5034 * Access: RO 5035 */ 5036 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5037 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5038 5039 /* reg_ppcnt_rx_frames 5040 * Access: RO 5041 */ 5042 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5043 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5044 5045 /* reg_ppcnt_tx_octets 5046 * Access: RO 5047 */ 5048 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5049 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5050 5051 /* reg_ppcnt_tx_frames 5052 * Access: RO 5053 */ 5054 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5055 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5056 5057 /* reg_ppcnt_rx_pause 5058 * Access: RO 5059 */ 5060 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5061 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5062 5063 /* reg_ppcnt_rx_pause_duration 5064 * Access: RO 5065 */ 5066 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5067 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5068 5069 /* reg_ppcnt_tx_pause 5070 * Access: RO 5071 */ 5072 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5073 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5074 5075 /* reg_ppcnt_tx_pause_duration 5076 * Access: RO 5077 */ 5078 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5079 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5080 5081 /* reg_ppcnt_rx_pause_transition 5082 * Access: RO 5083 */ 5084 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5085 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5086 5087 /* Ethernet Per Traffic Group Counters */ 5088 5089 /* reg_ppcnt_tc_transmit_queue 5090 * Contains the transmit queue depth in cells of traffic class 5091 * selected by prio_tc and the port selected by local_port. 5092 * The field cannot be cleared. 5093 * Access: RO 5094 */ 5095 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5096 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5097 5098 /* reg_ppcnt_tc_no_buffer_discard_uc 5099 * The number of unicast packets dropped due to lack of shared 5100 * buffer resources. 5101 * Access: RO 5102 */ 5103 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5104 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5105 5106 /* Ethernet Per Traffic Class Congestion Group Counters */ 5107 5108 /* reg_ppcnt_wred_discard 5109 * Access: RO 5110 */ 5111 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5112 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5113 5114 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5115 enum mlxsw_reg_ppcnt_grp grp, 5116 u8 prio_tc) 5117 { 5118 MLXSW_REG_ZERO(ppcnt, payload); 5119 mlxsw_reg_ppcnt_swid_set(payload, 0); 5120 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5121 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5122 mlxsw_reg_ppcnt_grp_set(payload, grp); 5123 mlxsw_reg_ppcnt_clr_set(payload, 0); 5124 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5125 } 5126 5127 /* PLIB - Port Local to InfiniBand Port 5128 * ------------------------------------ 5129 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5130 */ 5131 #define MLXSW_REG_PLIB_ID 0x500A 5132 #define MLXSW_REG_PLIB_LEN 0x10 5133 5134 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5135 5136 /* reg_plib_local_port 5137 * Local port number. 5138 * Access: Index 5139 */ 5140 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5141 5142 /* reg_plib_ib_port 5143 * InfiniBand port remapping for local_port. 5144 * Access: RW 5145 */ 5146 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5147 5148 /* PPTB - Port Prio To Buffer Register 5149 * ----------------------------------- 5150 * Configures the switch priority to buffer table. 5151 */ 5152 #define MLXSW_REG_PPTB_ID 0x500B 5153 #define MLXSW_REG_PPTB_LEN 0x10 5154 5155 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5156 5157 enum { 5158 MLXSW_REG_PPTB_MM_UM, 5159 MLXSW_REG_PPTB_MM_UNICAST, 5160 MLXSW_REG_PPTB_MM_MULTICAST, 5161 }; 5162 5163 /* reg_pptb_mm 5164 * Mapping mode. 5165 * 0 - Map both unicast and multicast packets to the same buffer. 5166 * 1 - Map only unicast packets. 5167 * 2 - Map only multicast packets. 5168 * Access: Index 5169 * 5170 * Note: SwitchX-2 only supports the first option. 5171 */ 5172 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5173 5174 /* reg_pptb_local_port 5175 * Local port number. 5176 * Access: Index 5177 */ 5178 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5179 5180 /* reg_pptb_um 5181 * Enables the update of the untagged_buf field. 5182 * Access: RW 5183 */ 5184 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5185 5186 /* reg_pptb_pm 5187 * Enables the update of the prio_to_buff field. 5188 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5189 * Access: RW 5190 */ 5191 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5192 5193 /* reg_pptb_prio_to_buff 5194 * Mapping of switch priority <i> to one of the allocated receive port 5195 * buffers. 5196 * Access: RW 5197 */ 5198 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5199 5200 /* reg_pptb_pm_msb 5201 * Enables the update of the prio_to_buff field. 5202 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5203 * Access: RW 5204 */ 5205 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5206 5207 /* reg_pptb_untagged_buff 5208 * Mapping of untagged frames to one of the allocated receive port buffers. 5209 * Access: RW 5210 * 5211 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5212 * Spectrum, as it maps untagged packets based on the default switch priority. 5213 */ 5214 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5215 5216 /* reg_pptb_prio_to_buff_msb 5217 * Mapping of switch priority <i+8> to one of the allocated receive port 5218 * buffers. 5219 * Access: RW 5220 */ 5221 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5222 5223 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5224 5225 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5226 { 5227 MLXSW_REG_ZERO(pptb, payload); 5228 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5229 mlxsw_reg_pptb_local_port_set(payload, local_port); 5230 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5231 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5232 } 5233 5234 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5235 u8 buff) 5236 { 5237 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5238 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5239 } 5240 5241 /* PBMC - Port Buffer Management Control Register 5242 * ---------------------------------------------- 5243 * The PBMC register configures and retrieves the port packet buffer 5244 * allocation for different Prios, and the Pause threshold management. 5245 */ 5246 #define MLXSW_REG_PBMC_ID 0x500C 5247 #define MLXSW_REG_PBMC_LEN 0x6C 5248 5249 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5250 5251 /* reg_pbmc_local_port 5252 * Local port number. 5253 * Access: Index 5254 */ 5255 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5256 5257 /* reg_pbmc_xoff_timer_value 5258 * When device generates a pause frame, it uses this value as the pause 5259 * timer (time for the peer port to pause in quota-512 bit time). 5260 * Access: RW 5261 */ 5262 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5263 5264 /* reg_pbmc_xoff_refresh 5265 * The time before a new pause frame should be sent to refresh the pause RW 5266 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5267 * time). 5268 * Access: RW 5269 */ 5270 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5271 5272 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5273 5274 /* reg_pbmc_buf_lossy 5275 * The field indicates if the buffer is lossy. 5276 * 0 - Lossless 5277 * 1 - Lossy 5278 * Access: RW 5279 */ 5280 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5281 5282 /* reg_pbmc_buf_epsb 5283 * Eligible for Port Shared buffer. 5284 * If epsb is set, packets assigned to buffer are allowed to insert the port 5285 * shared buffer. 5286 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5287 * Access: RW 5288 */ 5289 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5290 5291 /* reg_pbmc_buf_size 5292 * The part of the packet buffer array is allocated for the specific buffer. 5293 * Units are represented in cells. 5294 * Access: RW 5295 */ 5296 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5297 5298 /* reg_pbmc_buf_xoff_threshold 5299 * Once the amount of data in the buffer goes above this value, device 5300 * starts sending PFC frames for all priorities associated with the 5301 * buffer. Units are represented in cells. Reserved in case of lossy 5302 * buffer. 5303 * Access: RW 5304 * 5305 * Note: In Spectrum, reserved for buffer[9]. 5306 */ 5307 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5308 0x08, 0x04, false); 5309 5310 /* reg_pbmc_buf_xon_threshold 5311 * When the amount of data in the buffer goes below this value, device 5312 * stops sending PFC frames for the priorities associated with the 5313 * buffer. Units are represented in cells. Reserved in case of lossy 5314 * buffer. 5315 * Access: RW 5316 * 5317 * Note: In Spectrum, reserved for buffer[9]. 5318 */ 5319 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5320 0x08, 0x04, false); 5321 5322 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5323 u16 xoff_timer_value, u16 xoff_refresh) 5324 { 5325 MLXSW_REG_ZERO(pbmc, payload); 5326 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5327 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5328 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5329 } 5330 5331 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5332 int buf_index, 5333 u16 size) 5334 { 5335 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5336 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5337 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5338 } 5339 5340 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5341 int buf_index, u16 size, 5342 u16 threshold) 5343 { 5344 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5345 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5346 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5347 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5348 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5349 } 5350 5351 /* PSPA - Port Switch Partition Allocation 5352 * --------------------------------------- 5353 * Controls the association of a port with a switch partition and enables 5354 * configuring ports as stacking ports. 5355 */ 5356 #define MLXSW_REG_PSPA_ID 0x500D 5357 #define MLXSW_REG_PSPA_LEN 0x8 5358 5359 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5360 5361 /* reg_pspa_swid 5362 * Switch partition ID. 5363 * Access: RW 5364 */ 5365 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5366 5367 /* reg_pspa_local_port 5368 * Local port number. 5369 * Access: Index 5370 */ 5371 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5372 5373 /* reg_pspa_sub_port 5374 * Virtual port within the local port. Set to 0 when virtual ports are 5375 * disabled on the local port. 5376 * Access: Index 5377 */ 5378 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5379 5380 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5381 { 5382 MLXSW_REG_ZERO(pspa, payload); 5383 mlxsw_reg_pspa_swid_set(payload, swid); 5384 mlxsw_reg_pspa_local_port_set(payload, local_port); 5385 mlxsw_reg_pspa_sub_port_set(payload, 0); 5386 } 5387 5388 /* PPLR - Port Physical Loopback Register 5389 * -------------------------------------- 5390 * This register allows configuration of the port's loopback mode. 5391 */ 5392 #define MLXSW_REG_PPLR_ID 0x5018 5393 #define MLXSW_REG_PPLR_LEN 0x8 5394 5395 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5396 5397 /* reg_pplr_local_port 5398 * Local port number. 5399 * Access: Index 5400 */ 5401 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5402 5403 /* Phy local loopback. When set the port's egress traffic is looped back 5404 * to the receiver and the port transmitter is disabled. 5405 */ 5406 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5407 5408 /* reg_pplr_lb_en 5409 * Loopback enable. 5410 * Access: RW 5411 */ 5412 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5413 5414 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5415 bool phy_local) 5416 { 5417 MLXSW_REG_ZERO(pplr, payload); 5418 mlxsw_reg_pplr_local_port_set(payload, local_port); 5419 mlxsw_reg_pplr_lb_en_set(payload, 5420 phy_local ? 5421 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5422 } 5423 5424 /* PMTM - Port Module Type Mapping Register 5425 * ---------------------------------------- 5426 * The PMTM allows query or configuration of module types. 5427 */ 5428 #define MLXSW_REG_PMTM_ID 0x5067 5429 #define MLXSW_REG_PMTM_LEN 0x10 5430 5431 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5432 5433 /* reg_pmtm_module 5434 * Module number. 5435 * Access: Index 5436 */ 5437 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5438 5439 enum mlxsw_reg_pmtm_module_type { 5440 /* Backplane with 4 lanes */ 5441 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5442 /* QSFP */ 5443 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5444 /* SFP */ 5445 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5446 /* Backplane with single lane */ 5447 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5448 /* Backplane with two lane */ 5449 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5450 /* Chip2Chip4x */ 5451 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5452 /* Chip2Chip2x */ 5453 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5454 /* Chip2Chip1x */ 5455 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5456 /* QSFP-DD */ 5457 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5458 /* OSFP */ 5459 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5460 /* SFP-DD */ 5461 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5462 /* DSFP */ 5463 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5464 /* Chip2Chip8x */ 5465 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5466 }; 5467 5468 /* reg_pmtm_module_type 5469 * Module type. 5470 * Access: RW 5471 */ 5472 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5473 5474 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5475 { 5476 MLXSW_REG_ZERO(pmtm, payload); 5477 mlxsw_reg_pmtm_module_set(payload, module); 5478 } 5479 5480 static inline void 5481 mlxsw_reg_pmtm_unpack(char *payload, 5482 enum mlxsw_reg_pmtm_module_type *module_type) 5483 { 5484 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5485 } 5486 5487 /* HTGT - Host Trap Group Table 5488 * ---------------------------- 5489 * Configures the properties for forwarding to CPU. 5490 */ 5491 #define MLXSW_REG_HTGT_ID 0x7002 5492 #define MLXSW_REG_HTGT_LEN 0x20 5493 5494 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5495 5496 /* reg_htgt_swid 5497 * Switch partition ID. 5498 * Access: Index 5499 */ 5500 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5501 5502 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5503 5504 /* reg_htgt_type 5505 * CPU path type. 5506 * Access: RW 5507 */ 5508 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5509 5510 enum mlxsw_reg_htgt_trap_group { 5511 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5512 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 5513 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 5514 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5515 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5516 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5517 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 5518 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5519 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5520 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5521 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5522 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 5523 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 5524 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5525 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 5526 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5527 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5528 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 5529 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5530 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 5531 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 5532 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5533 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5534 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5535 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5536 5537 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5538 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5539 }; 5540 5541 enum mlxsw_reg_htgt_discard_trap_group { 5542 MLXSW_REG_HTGT_DISCARD_TRAP_GROUP_BASE = MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5543 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5544 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5545 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5546 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5547 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5548 }; 5549 5550 /* reg_htgt_trap_group 5551 * Trap group number. User defined number specifying which trap groups 5552 * should be forwarded to the CPU. The mapping between trap IDs and trap 5553 * groups is configured using HPKT register. 5554 * Access: Index 5555 */ 5556 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5557 5558 enum { 5559 MLXSW_REG_HTGT_POLICER_DISABLE, 5560 MLXSW_REG_HTGT_POLICER_ENABLE, 5561 }; 5562 5563 /* reg_htgt_pide 5564 * Enable policer ID specified using 'pid' field. 5565 * Access: RW 5566 */ 5567 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5568 5569 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5570 5571 /* reg_htgt_pid 5572 * Policer ID for the trap group. 5573 * Access: RW 5574 */ 5575 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5576 5577 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5578 5579 /* reg_htgt_mirror_action 5580 * Mirror action to use. 5581 * 0 - Trap to CPU. 5582 * 1 - Trap to CPU and mirror to a mirroring agent. 5583 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5584 * Access: RW 5585 * 5586 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5587 */ 5588 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5589 5590 /* reg_htgt_mirroring_agent 5591 * Mirroring agent. 5592 * Access: RW 5593 */ 5594 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5595 5596 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5597 5598 /* reg_htgt_priority 5599 * Trap group priority. 5600 * In case a packet matches multiple classification rules, the packet will 5601 * only be trapped once, based on the trap ID associated with the group (via 5602 * register HPKT) with the highest priority. 5603 * Supported values are 0-7, with 7 represnting the highest priority. 5604 * Access: RW 5605 * 5606 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5607 * by the 'trap_group' field. 5608 */ 5609 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5610 5611 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5612 5613 /* reg_htgt_local_path_cpu_tclass 5614 * CPU ingress traffic class for the trap group. 5615 * Access: RW 5616 */ 5617 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5618 5619 enum mlxsw_reg_htgt_local_path_rdq { 5620 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5621 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5622 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5623 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5624 }; 5625 /* reg_htgt_local_path_rdq 5626 * Receive descriptor queue (RDQ) to use for the trap group. 5627 * Access: RW 5628 */ 5629 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5630 5631 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5632 u8 priority, u8 tc) 5633 { 5634 MLXSW_REG_ZERO(htgt, payload); 5635 5636 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5637 mlxsw_reg_htgt_pide_set(payload, 5638 MLXSW_REG_HTGT_POLICER_DISABLE); 5639 } else { 5640 mlxsw_reg_htgt_pide_set(payload, 5641 MLXSW_REG_HTGT_POLICER_ENABLE); 5642 mlxsw_reg_htgt_pid_set(payload, policer_id); 5643 } 5644 5645 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5646 mlxsw_reg_htgt_trap_group_set(payload, group); 5647 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5648 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5649 mlxsw_reg_htgt_priority_set(payload, priority); 5650 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5651 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5652 } 5653 5654 /* HPKT - Host Packet Trap 5655 * ----------------------- 5656 * Configures trap IDs inside trap groups. 5657 */ 5658 #define MLXSW_REG_HPKT_ID 0x7003 5659 #define MLXSW_REG_HPKT_LEN 0x10 5660 5661 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5662 5663 enum { 5664 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5665 MLXSW_REG_HPKT_ACK_REQUIRED, 5666 }; 5667 5668 /* reg_hpkt_ack 5669 * Require acknowledgements from the host for events. 5670 * If set, then the device will wait for the event it sent to be acknowledged 5671 * by the host. This option is only relevant for event trap IDs. 5672 * Access: RW 5673 * 5674 * Note: Currently not supported by firmware. 5675 */ 5676 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5677 5678 enum mlxsw_reg_hpkt_action { 5679 MLXSW_REG_HPKT_ACTION_FORWARD, 5680 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5681 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5682 MLXSW_REG_HPKT_ACTION_DISCARD, 5683 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5684 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5685 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 5686 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 5687 }; 5688 5689 /* reg_hpkt_action 5690 * Action to perform on packet when trapped. 5691 * 0 - No action. Forward to CPU based on switching rules. 5692 * 1 - Trap to CPU (CPU receives sole copy). 5693 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5694 * 3 - Discard. 5695 * 4 - Soft discard (allow other traps to act on the packet). 5696 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5697 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 5698 * 15 - Restore the firmware's default action. 5699 * Access: RW 5700 * 5701 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5702 * addressed to the CPU. 5703 */ 5704 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5705 5706 /* reg_hpkt_trap_group 5707 * Trap group to associate the trap with. 5708 * Access: RW 5709 */ 5710 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5711 5712 /* reg_hpkt_trap_id 5713 * Trap ID. 5714 * Access: Index 5715 * 5716 * Note: A trap ID can only be associated with a single trap group. The device 5717 * will associate the trap ID with the last trap group configured. 5718 */ 5719 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5720 5721 enum { 5722 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5723 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5724 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5725 }; 5726 5727 /* reg_hpkt_ctrl 5728 * Configure dedicated buffer resources for control packets. 5729 * Ignored by SwitchX-2. 5730 * 0 - Keep factory defaults. 5731 * 1 - Do not use control buffer for this trap ID. 5732 * 2 - Use control buffer for this trap ID. 5733 * Access: RW 5734 */ 5735 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5736 5737 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5738 enum mlxsw_reg_htgt_trap_group trap_group, 5739 bool is_ctrl) 5740 { 5741 MLXSW_REG_ZERO(hpkt, payload); 5742 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5743 mlxsw_reg_hpkt_action_set(payload, action); 5744 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5745 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5746 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5747 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5748 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5749 } 5750 5751 /* RGCR - Router General Configuration Register 5752 * -------------------------------------------- 5753 * The register is used for setting up the router configuration. 5754 */ 5755 #define MLXSW_REG_RGCR_ID 0x8001 5756 #define MLXSW_REG_RGCR_LEN 0x28 5757 5758 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5759 5760 /* reg_rgcr_ipv4_en 5761 * IPv4 router enable. 5762 * Access: RW 5763 */ 5764 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5765 5766 /* reg_rgcr_ipv6_en 5767 * IPv6 router enable. 5768 * Access: RW 5769 */ 5770 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5771 5772 /* reg_rgcr_max_router_interfaces 5773 * Defines the maximum number of active router interfaces for all virtual 5774 * routers. 5775 * Access: RW 5776 */ 5777 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5778 5779 /* reg_rgcr_usp 5780 * Update switch priority and packet color. 5781 * 0 - Preserve the value of Switch Priority and packet color. 5782 * 1 - Recalculate the value of Switch Priority and packet color. 5783 * Access: RW 5784 * 5785 * Note: Not supported by SwitchX and SwitchX-2. 5786 */ 5787 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5788 5789 /* reg_rgcr_pcp_rw 5790 * Indicates how to handle the pcp_rewrite_en value: 5791 * 0 - Preserve the value of pcp_rewrite_en. 5792 * 2 - Disable PCP rewrite. 5793 * 3 - Enable PCP rewrite. 5794 * Access: RW 5795 * 5796 * Note: Not supported by SwitchX and SwitchX-2. 5797 */ 5798 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5799 5800 /* reg_rgcr_activity_dis 5801 * Activity disable: 5802 * 0 - Activity will be set when an entry is hit (default). 5803 * 1 - Activity will not be set when an entry is hit. 5804 * 5805 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5806 * (RALUE). 5807 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5808 * Entry (RAUHT). 5809 * Bits 2:7 are reserved. 5810 * Access: RW 5811 * 5812 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5813 */ 5814 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5815 5816 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5817 bool ipv6_en) 5818 { 5819 MLXSW_REG_ZERO(rgcr, payload); 5820 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5821 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5822 } 5823 5824 /* RITR - Router Interface Table Register 5825 * -------------------------------------- 5826 * The register is used to configure the router interface table. 5827 */ 5828 #define MLXSW_REG_RITR_ID 0x8002 5829 #define MLXSW_REG_RITR_LEN 0x40 5830 5831 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5832 5833 /* reg_ritr_enable 5834 * Enables routing on the router interface. 5835 * Access: RW 5836 */ 5837 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5838 5839 /* reg_ritr_ipv4 5840 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5841 * interface. 5842 * Access: RW 5843 */ 5844 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5845 5846 /* reg_ritr_ipv6 5847 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5848 * interface. 5849 * Access: RW 5850 */ 5851 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5852 5853 /* reg_ritr_ipv4_mc 5854 * IPv4 multicast routing enable. 5855 * Access: RW 5856 */ 5857 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5858 5859 /* reg_ritr_ipv6_mc 5860 * IPv6 multicast routing enable. 5861 * Access: RW 5862 */ 5863 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5864 5865 enum mlxsw_reg_ritr_if_type { 5866 /* VLAN interface. */ 5867 MLXSW_REG_RITR_VLAN_IF, 5868 /* FID interface. */ 5869 MLXSW_REG_RITR_FID_IF, 5870 /* Sub-port interface. */ 5871 MLXSW_REG_RITR_SP_IF, 5872 /* Loopback Interface. */ 5873 MLXSW_REG_RITR_LOOPBACK_IF, 5874 }; 5875 5876 /* reg_ritr_type 5877 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5878 * Access: RW 5879 */ 5880 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5881 5882 enum { 5883 MLXSW_REG_RITR_RIF_CREATE, 5884 MLXSW_REG_RITR_RIF_DEL, 5885 }; 5886 5887 /* reg_ritr_op 5888 * Opcode: 5889 * 0 - Create or edit RIF. 5890 * 1 - Delete RIF. 5891 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5892 * is not supported. An interface must be deleted and re-created in order 5893 * to update properties. 5894 * Access: WO 5895 */ 5896 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5897 5898 /* reg_ritr_rif 5899 * Router interface index. A pointer to the Router Interface Table. 5900 * Access: Index 5901 */ 5902 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5903 5904 /* reg_ritr_ipv4_fe 5905 * IPv4 Forwarding Enable. 5906 * Enables routing of IPv4 traffic on the router interface. When disabled, 5907 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5908 * Not supported in SwitchX-2. 5909 * Access: RW 5910 */ 5911 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5912 5913 /* reg_ritr_ipv6_fe 5914 * IPv6 Forwarding Enable. 5915 * Enables routing of IPv6 traffic on the router interface. When disabled, 5916 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5917 * Not supported in SwitchX-2. 5918 * Access: RW 5919 */ 5920 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5921 5922 /* reg_ritr_ipv4_mc_fe 5923 * IPv4 Multicast Forwarding Enable. 5924 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5925 * will be enabled. 5926 * Access: RW 5927 */ 5928 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5929 5930 /* reg_ritr_ipv6_mc_fe 5931 * IPv6 Multicast Forwarding Enable. 5932 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5933 * will be enabled. 5934 * Access: RW 5935 */ 5936 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5937 5938 /* reg_ritr_lb_en 5939 * Loop-back filter enable for unicast packets. 5940 * If the flag is set then loop-back filter for unicast packets is 5941 * implemented on the RIF. Multicast packets are always subject to 5942 * loop-back filtering. 5943 * Access: RW 5944 */ 5945 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5946 5947 /* reg_ritr_virtual_router 5948 * Virtual router ID associated with the router interface. 5949 * Access: RW 5950 */ 5951 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5952 5953 /* reg_ritr_mtu 5954 * Router interface MTU. 5955 * Access: RW 5956 */ 5957 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5958 5959 /* reg_ritr_if_swid 5960 * Switch partition ID. 5961 * Access: RW 5962 */ 5963 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5964 5965 /* reg_ritr_if_mac 5966 * Router interface MAC address. 5967 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5968 * Access: RW 5969 */ 5970 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5971 5972 /* reg_ritr_if_vrrp_id_ipv6 5973 * VRRP ID for IPv6 5974 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5975 * Access: RW 5976 */ 5977 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5978 5979 /* reg_ritr_if_vrrp_id_ipv4 5980 * VRRP ID for IPv4 5981 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5982 * Access: RW 5983 */ 5984 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5985 5986 /* VLAN Interface */ 5987 5988 /* reg_ritr_vlan_if_vid 5989 * VLAN ID. 5990 * Access: RW 5991 */ 5992 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5993 5994 /* FID Interface */ 5995 5996 /* reg_ritr_fid_if_fid 5997 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5998 * the vFID range are supported. 5999 * Access: RW 6000 */ 6001 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6002 6003 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6004 enum mlxsw_reg_ritr_if_type rif_type, 6005 u16 fid) 6006 { 6007 if (rif_type == MLXSW_REG_RITR_FID_IF) 6008 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6009 else 6010 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6011 } 6012 6013 /* Sub-port Interface */ 6014 6015 /* reg_ritr_sp_if_lag 6016 * LAG indication. When this bit is set the system_port field holds the 6017 * LAG identifier. 6018 * Access: RW 6019 */ 6020 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6021 6022 /* reg_ritr_sp_system_port 6023 * Port unique indentifier. When lag bit is set, this field holds the 6024 * lag_id in bits 0:9. 6025 * Access: RW 6026 */ 6027 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6028 6029 /* reg_ritr_sp_if_vid 6030 * VLAN ID. 6031 * Access: RW 6032 */ 6033 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6034 6035 /* Loopback Interface */ 6036 6037 enum mlxsw_reg_ritr_loopback_protocol { 6038 /* IPinIP IPv4 underlay Unicast */ 6039 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6040 /* IPinIP IPv6 underlay Unicast */ 6041 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6042 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6043 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6044 }; 6045 6046 /* reg_ritr_loopback_protocol 6047 * Access: RW 6048 */ 6049 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6050 6051 enum mlxsw_reg_ritr_loopback_ipip_type { 6052 /* Tunnel is IPinIP. */ 6053 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6054 /* Tunnel is GRE, no key. */ 6055 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6056 /* Tunnel is GRE, with a key. */ 6057 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6058 }; 6059 6060 /* reg_ritr_loopback_ipip_type 6061 * Encapsulation type. 6062 * Access: RW 6063 */ 6064 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6065 6066 enum mlxsw_reg_ritr_loopback_ipip_options { 6067 /* The key is defined by gre_key. */ 6068 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6069 }; 6070 6071 /* reg_ritr_loopback_ipip_options 6072 * Access: RW 6073 */ 6074 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6075 6076 /* reg_ritr_loopback_ipip_uvr 6077 * Underlay Virtual Router ID. 6078 * Range is 0..cap_max_virtual_routers-1. 6079 * Reserved for Spectrum-2. 6080 * Access: RW 6081 */ 6082 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6083 6084 /* reg_ritr_loopback_ipip_underlay_rif 6085 * Underlay ingress router interface. 6086 * Reserved for Spectrum. 6087 * Access: RW 6088 */ 6089 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6090 6091 /* reg_ritr_loopback_ipip_usip* 6092 * Encapsulation Underlay source IP. 6093 * Access: RW 6094 */ 6095 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6096 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6097 6098 /* reg_ritr_loopback_ipip_gre_key 6099 * GRE Key. 6100 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6101 * Access: RW 6102 */ 6103 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6104 6105 /* Shared between ingress/egress */ 6106 enum mlxsw_reg_ritr_counter_set_type { 6107 /* No Count. */ 6108 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6109 /* Basic. Used for router interfaces, counting the following: 6110 * - Error and Discard counters. 6111 * - Unicast, Multicast and Broadcast counters. Sharing the 6112 * same set of counters for the different type of traffic 6113 * (IPv4, IPv6 and mpls). 6114 */ 6115 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6116 }; 6117 6118 /* reg_ritr_ingress_counter_index 6119 * Counter Index for flow counter. 6120 * Access: RW 6121 */ 6122 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6123 6124 /* reg_ritr_ingress_counter_set_type 6125 * Igress Counter Set Type for router interface counter. 6126 * Access: RW 6127 */ 6128 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6129 6130 /* reg_ritr_egress_counter_index 6131 * Counter Index for flow counter. 6132 * Access: RW 6133 */ 6134 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6135 6136 /* reg_ritr_egress_counter_set_type 6137 * Egress Counter Set Type for router interface counter. 6138 * Access: RW 6139 */ 6140 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6141 6142 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6143 bool enable, bool egress) 6144 { 6145 enum mlxsw_reg_ritr_counter_set_type set_type; 6146 6147 if (enable) 6148 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6149 else 6150 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6151 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6152 6153 if (egress) 6154 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6155 else 6156 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6157 } 6158 6159 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6160 { 6161 MLXSW_REG_ZERO(ritr, payload); 6162 mlxsw_reg_ritr_rif_set(payload, rif); 6163 } 6164 6165 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6166 u16 system_port, u16 vid) 6167 { 6168 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6169 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6170 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6171 } 6172 6173 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6174 enum mlxsw_reg_ritr_if_type type, 6175 u16 rif, u16 vr_id, u16 mtu) 6176 { 6177 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6178 6179 MLXSW_REG_ZERO(ritr, payload); 6180 mlxsw_reg_ritr_enable_set(payload, enable); 6181 mlxsw_reg_ritr_ipv4_set(payload, 1); 6182 mlxsw_reg_ritr_ipv6_set(payload, 1); 6183 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6184 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6185 mlxsw_reg_ritr_type_set(payload, type); 6186 mlxsw_reg_ritr_op_set(payload, op); 6187 mlxsw_reg_ritr_rif_set(payload, rif); 6188 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6189 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6190 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6191 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6192 mlxsw_reg_ritr_lb_en_set(payload, 1); 6193 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6194 mlxsw_reg_ritr_mtu_set(payload, mtu); 6195 } 6196 6197 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6198 { 6199 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6200 } 6201 6202 static inline void 6203 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6204 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6205 enum mlxsw_reg_ritr_loopback_ipip_options options, 6206 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6207 { 6208 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6209 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6210 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6211 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6212 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6213 } 6214 6215 static inline void 6216 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6217 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6218 enum mlxsw_reg_ritr_loopback_ipip_options options, 6219 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6220 { 6221 mlxsw_reg_ritr_loopback_protocol_set(payload, 6222 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6223 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6224 uvr_id, underlay_rif, gre_key); 6225 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6226 } 6227 6228 /* RTAR - Router TCAM Allocation Register 6229 * -------------------------------------- 6230 * This register is used for allocation of regions in the TCAM table. 6231 */ 6232 #define MLXSW_REG_RTAR_ID 0x8004 6233 #define MLXSW_REG_RTAR_LEN 0x20 6234 6235 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6236 6237 enum mlxsw_reg_rtar_op { 6238 MLXSW_REG_RTAR_OP_ALLOCATE, 6239 MLXSW_REG_RTAR_OP_RESIZE, 6240 MLXSW_REG_RTAR_OP_DEALLOCATE, 6241 }; 6242 6243 /* reg_rtar_op 6244 * Access: WO 6245 */ 6246 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6247 6248 enum mlxsw_reg_rtar_key_type { 6249 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6250 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6251 }; 6252 6253 /* reg_rtar_key_type 6254 * TCAM key type for the region. 6255 * Access: WO 6256 */ 6257 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6258 6259 /* reg_rtar_region_size 6260 * TCAM region size. When allocating/resizing this is the requested 6261 * size, the response is the actual size. 6262 * Note: Actual size may be larger than requested. 6263 * Reserved for op = Deallocate 6264 * Access: WO 6265 */ 6266 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6267 6268 static inline void mlxsw_reg_rtar_pack(char *payload, 6269 enum mlxsw_reg_rtar_op op, 6270 enum mlxsw_reg_rtar_key_type key_type, 6271 u16 region_size) 6272 { 6273 MLXSW_REG_ZERO(rtar, payload); 6274 mlxsw_reg_rtar_op_set(payload, op); 6275 mlxsw_reg_rtar_key_type_set(payload, key_type); 6276 mlxsw_reg_rtar_region_size_set(payload, region_size); 6277 } 6278 6279 /* RATR - Router Adjacency Table Register 6280 * -------------------------------------- 6281 * The RATR register is used to configure the Router Adjacency (next-hop) 6282 * Table. 6283 */ 6284 #define MLXSW_REG_RATR_ID 0x8008 6285 #define MLXSW_REG_RATR_LEN 0x2C 6286 6287 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6288 6289 enum mlxsw_reg_ratr_op { 6290 /* Read */ 6291 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6292 /* Read and clear activity */ 6293 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6294 /* Write Adjacency entry */ 6295 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6296 /* Write Adjacency entry only if the activity is cleared. 6297 * The write may not succeed if the activity is set. There is not 6298 * direct feedback if the write has succeeded or not, however 6299 * the get will reveal the actual entry (SW can compare the get 6300 * response to the set command). 6301 */ 6302 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6303 }; 6304 6305 /* reg_ratr_op 6306 * Note that Write operation may also be used for updating 6307 * counter_set_type and counter_index. In this case all other 6308 * fields must not be updated. 6309 * Access: OP 6310 */ 6311 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6312 6313 /* reg_ratr_v 6314 * Valid bit. Indicates if the adjacency entry is valid. 6315 * Note: the device may need some time before reusing an invalidated 6316 * entry. During this time the entry can not be reused. It is 6317 * recommended to use another entry before reusing an invalidated 6318 * entry (e.g. software can put it at the end of the list for 6319 * reusing). Trying to access an invalidated entry not yet cleared 6320 * by the device results with failure indicating "Try Again" status. 6321 * When valid is '0' then egress_router_interface,trap_action, 6322 * adjacency_parameters and counters are reserved 6323 * Access: RW 6324 */ 6325 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6326 6327 /* reg_ratr_a 6328 * Activity. Set for new entries. Set if a packet lookup has hit on 6329 * the specific entry. To clear the a bit, use "clear activity". 6330 * Access: RO 6331 */ 6332 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6333 6334 enum mlxsw_reg_ratr_type { 6335 /* Ethernet */ 6336 MLXSW_REG_RATR_TYPE_ETHERNET, 6337 /* IPoIB Unicast without GRH. 6338 * Reserved for Spectrum. 6339 */ 6340 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6341 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6342 * adjacency). 6343 * Reserved for Spectrum. 6344 */ 6345 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6346 /* IPoIB Multicast. 6347 * Reserved for Spectrum. 6348 */ 6349 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6350 /* MPLS. 6351 * Reserved for SwitchX/-2. 6352 */ 6353 MLXSW_REG_RATR_TYPE_MPLS, 6354 /* IPinIP Encap. 6355 * Reserved for SwitchX/-2. 6356 */ 6357 MLXSW_REG_RATR_TYPE_IPIP, 6358 }; 6359 6360 /* reg_ratr_type 6361 * Adjacency entry type. 6362 * Access: RW 6363 */ 6364 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6365 6366 /* reg_ratr_adjacency_index_low 6367 * Bits 15:0 of index into the adjacency table. 6368 * For SwitchX and SwitchX-2, the adjacency table is linear and 6369 * used for adjacency entries only. 6370 * For Spectrum, the index is to the KVD linear. 6371 * Access: Index 6372 */ 6373 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6374 6375 /* reg_ratr_egress_router_interface 6376 * Range is 0 .. cap_max_router_interfaces - 1 6377 * Access: RW 6378 */ 6379 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6380 6381 enum mlxsw_reg_ratr_trap_action { 6382 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6383 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6384 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6385 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6386 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6387 }; 6388 6389 /* reg_ratr_trap_action 6390 * see mlxsw_reg_ratr_trap_action 6391 * Access: RW 6392 */ 6393 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6394 6395 /* reg_ratr_adjacency_index_high 6396 * Bits 23:16 of the adjacency_index. 6397 * Access: Index 6398 */ 6399 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6400 6401 enum mlxsw_reg_ratr_trap_id { 6402 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6403 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6404 }; 6405 6406 /* reg_ratr_trap_id 6407 * Trap ID to be reported to CPU. 6408 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6409 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6410 * Access: RW 6411 */ 6412 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6413 6414 /* reg_ratr_eth_destination_mac 6415 * MAC address of the destination next-hop. 6416 * Access: RW 6417 */ 6418 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6419 6420 enum mlxsw_reg_ratr_ipip_type { 6421 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6422 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6423 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6424 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6425 }; 6426 6427 /* reg_ratr_ipip_type 6428 * Underlay destination ip type. 6429 * Note: the type field must match the protocol of the router interface. 6430 * Access: RW 6431 */ 6432 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6433 6434 /* reg_ratr_ipip_ipv4_udip 6435 * Underlay ipv4 dip. 6436 * Reserved when ipip_type is IPv6. 6437 * Access: RW 6438 */ 6439 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6440 6441 /* reg_ratr_ipip_ipv6_ptr 6442 * Pointer to IPv6 underlay destination ip address. 6443 * For Spectrum: Pointer to KVD linear space. 6444 * Access: RW 6445 */ 6446 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6447 6448 enum mlxsw_reg_flow_counter_set_type { 6449 /* No count */ 6450 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6451 /* Count packets and bytes */ 6452 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6453 /* Count only packets */ 6454 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6455 }; 6456 6457 /* reg_ratr_counter_set_type 6458 * Counter set type for flow counters 6459 * Access: RW 6460 */ 6461 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6462 6463 /* reg_ratr_counter_index 6464 * Counter index for flow counters 6465 * Access: RW 6466 */ 6467 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6468 6469 static inline void 6470 mlxsw_reg_ratr_pack(char *payload, 6471 enum mlxsw_reg_ratr_op op, bool valid, 6472 enum mlxsw_reg_ratr_type type, 6473 u32 adjacency_index, u16 egress_rif) 6474 { 6475 MLXSW_REG_ZERO(ratr, payload); 6476 mlxsw_reg_ratr_op_set(payload, op); 6477 mlxsw_reg_ratr_v_set(payload, valid); 6478 mlxsw_reg_ratr_type_set(payload, type); 6479 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6480 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6481 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6482 } 6483 6484 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6485 const char *dest_mac) 6486 { 6487 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6488 } 6489 6490 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6491 { 6492 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6493 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6494 } 6495 6496 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6497 bool counter_enable) 6498 { 6499 enum mlxsw_reg_flow_counter_set_type set_type; 6500 6501 if (counter_enable) 6502 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6503 else 6504 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6505 6506 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6507 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6508 } 6509 6510 /* RDPM - Router DSCP to Priority Mapping 6511 * -------------------------------------- 6512 * Controls the mapping from DSCP field to switch priority on routed packets 6513 */ 6514 #define MLXSW_REG_RDPM_ID 0x8009 6515 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6516 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6517 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6518 #define MLXSW_REG_RDPM_LEN 0x40 6519 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6520 MLXSW_REG_RDPM_LEN - \ 6521 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6522 6523 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6524 6525 /* reg_dscp_entry_e 6526 * Enable update of the specific entry 6527 * Access: Index 6528 */ 6529 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6530 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6531 6532 /* reg_dscp_entry_prio 6533 * Switch Priority 6534 * Access: RW 6535 */ 6536 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6537 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6538 6539 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6540 u8 prio) 6541 { 6542 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6543 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6544 } 6545 6546 /* RICNT - Router Interface Counter Register 6547 * ----------------------------------------- 6548 * The RICNT register retrieves per port performance counters 6549 */ 6550 #define MLXSW_REG_RICNT_ID 0x800B 6551 #define MLXSW_REG_RICNT_LEN 0x100 6552 6553 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6554 6555 /* reg_ricnt_counter_index 6556 * Counter index 6557 * Access: RW 6558 */ 6559 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6560 6561 enum mlxsw_reg_ricnt_counter_set_type { 6562 /* No Count. */ 6563 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6564 /* Basic. Used for router interfaces, counting the following: 6565 * - Error and Discard counters. 6566 * - Unicast, Multicast and Broadcast counters. Sharing the 6567 * same set of counters for the different type of traffic 6568 * (IPv4, IPv6 and mpls). 6569 */ 6570 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6571 }; 6572 6573 /* reg_ricnt_counter_set_type 6574 * Counter Set Type for router interface counter 6575 * Access: RW 6576 */ 6577 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6578 6579 enum mlxsw_reg_ricnt_opcode { 6580 /* Nop. Supported only for read access*/ 6581 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6582 /* Clear. Setting the clr bit will reset the counter value for 6583 * all counters of the specified Router Interface. 6584 */ 6585 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6586 }; 6587 6588 /* reg_ricnt_opcode 6589 * Opcode 6590 * Access: RW 6591 */ 6592 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6593 6594 /* reg_ricnt_good_unicast_packets 6595 * good unicast packets. 6596 * Access: RW 6597 */ 6598 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6599 6600 /* reg_ricnt_good_multicast_packets 6601 * good multicast packets. 6602 * Access: RW 6603 */ 6604 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6605 6606 /* reg_ricnt_good_broadcast_packets 6607 * good broadcast packets 6608 * Access: RW 6609 */ 6610 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6611 6612 /* reg_ricnt_good_unicast_bytes 6613 * A count of L3 data and padding octets not including L2 headers 6614 * for good unicast frames. 6615 * Access: RW 6616 */ 6617 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6618 6619 /* reg_ricnt_good_multicast_bytes 6620 * A count of L3 data and padding octets not including L2 headers 6621 * for good multicast frames. 6622 * Access: RW 6623 */ 6624 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6625 6626 /* reg_ritr_good_broadcast_bytes 6627 * A count of L3 data and padding octets not including L2 headers 6628 * for good broadcast frames. 6629 * Access: RW 6630 */ 6631 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6632 6633 /* reg_ricnt_error_packets 6634 * A count of errored frames that do not pass the router checks. 6635 * Access: RW 6636 */ 6637 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6638 6639 /* reg_ricnt_discrad_packets 6640 * A count of non-errored frames that do not pass the router checks. 6641 * Access: RW 6642 */ 6643 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6644 6645 /* reg_ricnt_error_bytes 6646 * A count of L3 data and padding octets not including L2 headers 6647 * for errored frames. 6648 * Access: RW 6649 */ 6650 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6651 6652 /* reg_ricnt_discard_bytes 6653 * A count of L3 data and padding octets not including L2 headers 6654 * for non-errored frames that do not pass the router checks. 6655 * Access: RW 6656 */ 6657 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6658 6659 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6660 enum mlxsw_reg_ricnt_opcode op) 6661 { 6662 MLXSW_REG_ZERO(ricnt, payload); 6663 mlxsw_reg_ricnt_op_set(payload, op); 6664 mlxsw_reg_ricnt_counter_index_set(payload, index); 6665 mlxsw_reg_ricnt_counter_set_type_set(payload, 6666 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6667 } 6668 6669 /* RRCR - Router Rules Copy Register Layout 6670 * ---------------------------------------- 6671 * This register is used for moving and copying route entry rules. 6672 */ 6673 #define MLXSW_REG_RRCR_ID 0x800F 6674 #define MLXSW_REG_RRCR_LEN 0x24 6675 6676 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6677 6678 enum mlxsw_reg_rrcr_op { 6679 /* Move rules */ 6680 MLXSW_REG_RRCR_OP_MOVE, 6681 /* Copy rules */ 6682 MLXSW_REG_RRCR_OP_COPY, 6683 }; 6684 6685 /* reg_rrcr_op 6686 * Access: WO 6687 */ 6688 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6689 6690 /* reg_rrcr_offset 6691 * Offset within the region from which to copy/move. 6692 * Access: Index 6693 */ 6694 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6695 6696 /* reg_rrcr_size 6697 * The number of rules to copy/move. 6698 * Access: WO 6699 */ 6700 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6701 6702 /* reg_rrcr_table_id 6703 * Identifier of the table on which to perform the operation. Encoding is the 6704 * same as in RTAR.key_type 6705 * Access: Index 6706 */ 6707 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6708 6709 /* reg_rrcr_dest_offset 6710 * Offset within the region to which to copy/move 6711 * Access: Index 6712 */ 6713 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6714 6715 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6716 u16 offset, u16 size, 6717 enum mlxsw_reg_rtar_key_type table_id, 6718 u16 dest_offset) 6719 { 6720 MLXSW_REG_ZERO(rrcr, payload); 6721 mlxsw_reg_rrcr_op_set(payload, op); 6722 mlxsw_reg_rrcr_offset_set(payload, offset); 6723 mlxsw_reg_rrcr_size_set(payload, size); 6724 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6725 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6726 } 6727 6728 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6729 * ------------------------------------------------------- 6730 * RALTA is used to allocate the LPM trees of the SHSPM method. 6731 */ 6732 #define MLXSW_REG_RALTA_ID 0x8010 6733 #define MLXSW_REG_RALTA_LEN 0x04 6734 6735 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6736 6737 /* reg_ralta_op 6738 * opcode (valid for Write, must be 0 on Read) 6739 * 0 - allocate a tree 6740 * 1 - deallocate a tree 6741 * Access: OP 6742 */ 6743 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6744 6745 enum mlxsw_reg_ralxx_protocol { 6746 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6747 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6748 }; 6749 6750 /* reg_ralta_protocol 6751 * Protocol. 6752 * Deallocation opcode: Reserved. 6753 * Access: RW 6754 */ 6755 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6756 6757 /* reg_ralta_tree_id 6758 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6759 * the tree identifier (managed by software). 6760 * Note that tree_id 0 is allocated for a default-route tree. 6761 * Access: Index 6762 */ 6763 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6764 6765 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6766 enum mlxsw_reg_ralxx_protocol protocol, 6767 u8 tree_id) 6768 { 6769 MLXSW_REG_ZERO(ralta, payload); 6770 mlxsw_reg_ralta_op_set(payload, !alloc); 6771 mlxsw_reg_ralta_protocol_set(payload, protocol); 6772 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6773 } 6774 6775 /* RALST - Router Algorithmic LPM Structure Tree Register 6776 * ------------------------------------------------------ 6777 * RALST is used to set and query the structure of an LPM tree. 6778 * The structure of the tree must be sorted as a sorted binary tree, while 6779 * each node is a bin that is tagged as the length of the prefixes the lookup 6780 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6781 * of X bits to match with the destination address. The bin 0 indicates 6782 * the default action, when there is no match of any prefix. 6783 */ 6784 #define MLXSW_REG_RALST_ID 0x8011 6785 #define MLXSW_REG_RALST_LEN 0x104 6786 6787 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6788 6789 /* reg_ralst_root_bin 6790 * The bin number of the root bin. 6791 * 0<root_bin=<(length of IP address) 6792 * For a default-route tree configure 0xff 6793 * Access: RW 6794 */ 6795 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6796 6797 /* reg_ralst_tree_id 6798 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6799 * Access: Index 6800 */ 6801 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6802 6803 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6804 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6805 #define MLXSW_REG_RALST_BIN_COUNT 128 6806 6807 /* reg_ralst_left_child_bin 6808 * Holding the children of the bin according to the stored tree's structure. 6809 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6810 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6811 * Access: RW 6812 */ 6813 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6814 6815 /* reg_ralst_right_child_bin 6816 * Holding the children of the bin according to the stored tree's structure. 6817 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6818 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6819 * Access: RW 6820 */ 6821 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6822 false); 6823 6824 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6825 { 6826 MLXSW_REG_ZERO(ralst, payload); 6827 6828 /* Initialize all bins to have no left or right child */ 6829 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6830 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6831 6832 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6833 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6834 } 6835 6836 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6837 u8 left_child_bin, 6838 u8 right_child_bin) 6839 { 6840 int bin_index = bin_number - 1; 6841 6842 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6843 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6844 right_child_bin); 6845 } 6846 6847 /* RALTB - Router Algorithmic LPM Tree Binding Register 6848 * ---------------------------------------------------- 6849 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6850 */ 6851 #define MLXSW_REG_RALTB_ID 0x8012 6852 #define MLXSW_REG_RALTB_LEN 0x04 6853 6854 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6855 6856 /* reg_raltb_virtual_router 6857 * Virtual Router ID 6858 * Range is 0..cap_max_virtual_routers-1 6859 * Access: Index 6860 */ 6861 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6862 6863 /* reg_raltb_protocol 6864 * Protocol. 6865 * Access: Index 6866 */ 6867 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6868 6869 /* reg_raltb_tree_id 6870 * Tree to be used for the {virtual_router, protocol} 6871 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6872 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6873 * Access: RW 6874 */ 6875 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6876 6877 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6878 enum mlxsw_reg_ralxx_protocol protocol, 6879 u8 tree_id) 6880 { 6881 MLXSW_REG_ZERO(raltb, payload); 6882 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6883 mlxsw_reg_raltb_protocol_set(payload, protocol); 6884 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6885 } 6886 6887 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6888 * ----------------------------------------------------- 6889 * RALUE is used to configure and query LPM entries that serve 6890 * the Unicast protocols. 6891 */ 6892 #define MLXSW_REG_RALUE_ID 0x8013 6893 #define MLXSW_REG_RALUE_LEN 0x38 6894 6895 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6896 6897 /* reg_ralue_protocol 6898 * Protocol. 6899 * Access: Index 6900 */ 6901 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6902 6903 enum mlxsw_reg_ralue_op { 6904 /* Read operation. If entry doesn't exist, the operation fails. */ 6905 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6906 /* Clear on read operation. Used to read entry and 6907 * clear Activity bit. 6908 */ 6909 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6910 /* Write operation. Used to write a new entry to the table. All RW 6911 * fields are written for new entry. Activity bit is set 6912 * for new entries. 6913 */ 6914 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6915 /* Update operation. Used to update an existing route entry and 6916 * only update the RW fields that are detailed in the field 6917 * op_u_mask. If entry doesn't exist, the operation fails. 6918 */ 6919 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6920 /* Clear activity. The Activity bit (the field a) is cleared 6921 * for the entry. 6922 */ 6923 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6924 /* Delete operation. Used to delete an existing entry. If entry 6925 * doesn't exist, the operation fails. 6926 */ 6927 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6928 }; 6929 6930 /* reg_ralue_op 6931 * Operation. 6932 * Access: OP 6933 */ 6934 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6935 6936 /* reg_ralue_a 6937 * Activity. Set for new entries. Set if a packet lookup has hit on the 6938 * specific entry, only if the entry is a route. To clear the a bit, use 6939 * "clear activity" op. 6940 * Enabled by activity_dis in RGCR 6941 * Access: RO 6942 */ 6943 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6944 6945 /* reg_ralue_virtual_router 6946 * Virtual Router ID 6947 * Range is 0..cap_max_virtual_routers-1 6948 * Access: Index 6949 */ 6950 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6951 6952 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6953 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6954 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6955 6956 /* reg_ralue_op_u_mask 6957 * opcode update mask. 6958 * On read operation, this field is reserved. 6959 * This field is valid for update opcode, otherwise - reserved. 6960 * This field is a bitmask of the fields that should be updated. 6961 * Access: WO 6962 */ 6963 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6964 6965 /* reg_ralue_prefix_len 6966 * Number of bits in the prefix of the LPM route. 6967 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6968 * two entries in the physical HW table. 6969 * Access: Index 6970 */ 6971 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6972 6973 /* reg_ralue_dip* 6974 * The prefix of the route or of the marker that the object of the LPM 6975 * is compared with. The most significant bits of the dip are the prefix. 6976 * The least significant bits must be '0' if the prefix_len is smaller 6977 * than 128 for IPv6 or smaller than 32 for IPv4. 6978 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6979 * Access: Index 6980 */ 6981 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6982 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6983 6984 enum mlxsw_reg_ralue_entry_type { 6985 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6986 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6987 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6988 }; 6989 6990 /* reg_ralue_entry_type 6991 * Entry type. 6992 * Note - for Marker entries, the action_type and action fields are reserved. 6993 * Access: RW 6994 */ 6995 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6996 6997 /* reg_ralue_bmp_len 6998 * The best match prefix length in the case that there is no match for 6999 * longer prefixes. 7000 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7001 * Note for any update operation with entry_type modification this 7002 * field must be set. 7003 * Access: RW 7004 */ 7005 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7006 7007 enum mlxsw_reg_ralue_action_type { 7008 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7009 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7010 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7011 }; 7012 7013 /* reg_ralue_action_type 7014 * Action Type 7015 * Indicates how the IP address is connected. 7016 * It can be connected to a local subnet through local_erif or can be 7017 * on a remote subnet connected through a next-hop router, 7018 * or transmitted to the CPU. 7019 * Reserved when entry_type = MARKER_ENTRY 7020 * Access: RW 7021 */ 7022 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7023 7024 enum mlxsw_reg_ralue_trap_action { 7025 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7026 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7027 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7028 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7029 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7030 }; 7031 7032 /* reg_ralue_trap_action 7033 * Trap action. 7034 * For IP2ME action, only NOP and MIRROR are possible. 7035 * Access: RW 7036 */ 7037 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7038 7039 /* reg_ralue_trap_id 7040 * Trap ID to be reported to CPU. 7041 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7042 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7043 * Access: RW 7044 */ 7045 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7046 7047 /* reg_ralue_adjacency_index 7048 * Points to the first entry of the group-based ECMP. 7049 * Only relevant in case of REMOTE action. 7050 * Access: RW 7051 */ 7052 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7053 7054 /* reg_ralue_ecmp_size 7055 * Amount of sequential entries starting 7056 * from the adjacency_index (the number of ECMPs). 7057 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7058 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7059 * Only relevant in case of REMOTE action. 7060 * Access: RW 7061 */ 7062 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7063 7064 /* reg_ralue_local_erif 7065 * Egress Router Interface. 7066 * Only relevant in case of LOCAL action. 7067 * Access: RW 7068 */ 7069 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7070 7071 /* reg_ralue_ip2me_v 7072 * Valid bit for the tunnel_ptr field. 7073 * If valid = 0 then trap to CPU as IP2ME trap ID. 7074 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7075 * decapsulation then tunnel decapsulation is done. 7076 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7077 * decapsulation then trap as IP2ME trap ID. 7078 * Only relevant in case of IP2ME action. 7079 * Access: RW 7080 */ 7081 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7082 7083 /* reg_ralue_ip2me_tunnel_ptr 7084 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7085 * For Spectrum, pointer to KVD Linear. 7086 * Only relevant in case of IP2ME action. 7087 * Access: RW 7088 */ 7089 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7090 7091 static inline void mlxsw_reg_ralue_pack(char *payload, 7092 enum mlxsw_reg_ralxx_protocol protocol, 7093 enum mlxsw_reg_ralue_op op, 7094 u16 virtual_router, u8 prefix_len) 7095 { 7096 MLXSW_REG_ZERO(ralue, payload); 7097 mlxsw_reg_ralue_protocol_set(payload, protocol); 7098 mlxsw_reg_ralue_op_set(payload, op); 7099 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7100 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7101 mlxsw_reg_ralue_entry_type_set(payload, 7102 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7103 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7104 } 7105 7106 static inline void mlxsw_reg_ralue_pack4(char *payload, 7107 enum mlxsw_reg_ralxx_protocol protocol, 7108 enum mlxsw_reg_ralue_op op, 7109 u16 virtual_router, u8 prefix_len, 7110 u32 dip) 7111 { 7112 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7113 mlxsw_reg_ralue_dip4_set(payload, dip); 7114 } 7115 7116 static inline void mlxsw_reg_ralue_pack6(char *payload, 7117 enum mlxsw_reg_ralxx_protocol protocol, 7118 enum mlxsw_reg_ralue_op op, 7119 u16 virtual_router, u8 prefix_len, 7120 const void *dip) 7121 { 7122 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7123 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7124 } 7125 7126 static inline void 7127 mlxsw_reg_ralue_act_remote_pack(char *payload, 7128 enum mlxsw_reg_ralue_trap_action trap_action, 7129 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7130 { 7131 mlxsw_reg_ralue_action_type_set(payload, 7132 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7133 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7134 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7135 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7136 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7137 } 7138 7139 static inline void 7140 mlxsw_reg_ralue_act_local_pack(char *payload, 7141 enum mlxsw_reg_ralue_trap_action trap_action, 7142 u16 trap_id, u16 local_erif) 7143 { 7144 mlxsw_reg_ralue_action_type_set(payload, 7145 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7146 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7147 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7148 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7149 } 7150 7151 static inline void 7152 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7153 { 7154 mlxsw_reg_ralue_action_type_set(payload, 7155 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7156 } 7157 7158 static inline void 7159 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7160 { 7161 mlxsw_reg_ralue_action_type_set(payload, 7162 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7163 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7164 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7165 } 7166 7167 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7168 * ---------------------------------------------------------- 7169 * The RAUHT register is used to configure and query the Unicast Host table in 7170 * devices that implement the Algorithmic LPM. 7171 */ 7172 #define MLXSW_REG_RAUHT_ID 0x8014 7173 #define MLXSW_REG_RAUHT_LEN 0x74 7174 7175 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7176 7177 enum mlxsw_reg_rauht_type { 7178 MLXSW_REG_RAUHT_TYPE_IPV4, 7179 MLXSW_REG_RAUHT_TYPE_IPV6, 7180 }; 7181 7182 /* reg_rauht_type 7183 * Access: Index 7184 */ 7185 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7186 7187 enum mlxsw_reg_rauht_op { 7188 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7189 /* Read operation */ 7190 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7191 /* Clear on read operation. Used to read entry and clear 7192 * activity bit. 7193 */ 7194 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7195 /* Add. Used to write a new entry to the table. All R/W fields are 7196 * relevant for new entry. Activity bit is set for new entries. 7197 */ 7198 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7199 /* Update action. Used to update an existing route entry and 7200 * only update the following fields: 7201 * trap_action, trap_id, mac, counter_set_type, counter_index 7202 */ 7203 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7204 /* Clear activity. A bit is cleared for the entry. */ 7205 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7206 /* Delete entry */ 7207 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7208 /* Delete all host entries on a RIF. In this command, dip 7209 * field is reserved. 7210 */ 7211 }; 7212 7213 /* reg_rauht_op 7214 * Access: OP 7215 */ 7216 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7217 7218 /* reg_rauht_a 7219 * Activity. Set for new entries. Set if a packet lookup has hit on 7220 * the specific entry. 7221 * To clear the a bit, use "clear activity" op. 7222 * Enabled by activity_dis in RGCR 7223 * Access: RO 7224 */ 7225 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7226 7227 /* reg_rauht_rif 7228 * Router Interface 7229 * Access: Index 7230 */ 7231 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7232 7233 /* reg_rauht_dip* 7234 * Destination address. 7235 * Access: Index 7236 */ 7237 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7238 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7239 7240 enum mlxsw_reg_rauht_trap_action { 7241 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7242 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7243 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7244 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7245 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7246 }; 7247 7248 /* reg_rauht_trap_action 7249 * Access: RW 7250 */ 7251 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7252 7253 enum mlxsw_reg_rauht_trap_id { 7254 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7255 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7256 }; 7257 7258 /* reg_rauht_trap_id 7259 * Trap ID to be reported to CPU. 7260 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7261 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7262 * trap_id is reserved. 7263 * Access: RW 7264 */ 7265 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7266 7267 /* reg_rauht_counter_set_type 7268 * Counter set type for flow counters 7269 * Access: RW 7270 */ 7271 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7272 7273 /* reg_rauht_counter_index 7274 * Counter index for flow counters 7275 * Access: RW 7276 */ 7277 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7278 7279 /* reg_rauht_mac 7280 * MAC address. 7281 * Access: RW 7282 */ 7283 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7284 7285 static inline void mlxsw_reg_rauht_pack(char *payload, 7286 enum mlxsw_reg_rauht_op op, u16 rif, 7287 const char *mac) 7288 { 7289 MLXSW_REG_ZERO(rauht, payload); 7290 mlxsw_reg_rauht_op_set(payload, op); 7291 mlxsw_reg_rauht_rif_set(payload, rif); 7292 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7293 } 7294 7295 static inline void mlxsw_reg_rauht_pack4(char *payload, 7296 enum mlxsw_reg_rauht_op op, u16 rif, 7297 const char *mac, u32 dip) 7298 { 7299 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7300 mlxsw_reg_rauht_dip4_set(payload, dip); 7301 } 7302 7303 static inline void mlxsw_reg_rauht_pack6(char *payload, 7304 enum mlxsw_reg_rauht_op op, u16 rif, 7305 const char *mac, const char *dip) 7306 { 7307 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7308 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7309 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7310 } 7311 7312 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7313 u64 counter_index) 7314 { 7315 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7316 mlxsw_reg_rauht_counter_set_type_set(payload, 7317 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7318 } 7319 7320 /* RALEU - Router Algorithmic LPM ECMP Update Register 7321 * --------------------------------------------------- 7322 * The register enables updating the ECMP section in the action for multiple 7323 * LPM Unicast entries in a single operation. The update is executed to 7324 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7325 */ 7326 #define MLXSW_REG_RALEU_ID 0x8015 7327 #define MLXSW_REG_RALEU_LEN 0x28 7328 7329 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7330 7331 /* reg_raleu_protocol 7332 * Protocol. 7333 * Access: Index 7334 */ 7335 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7336 7337 /* reg_raleu_virtual_router 7338 * Virtual Router ID 7339 * Range is 0..cap_max_virtual_routers-1 7340 * Access: Index 7341 */ 7342 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7343 7344 /* reg_raleu_adjacency_index 7345 * Adjacency Index used for matching on the existing entries. 7346 * Access: Index 7347 */ 7348 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7349 7350 /* reg_raleu_ecmp_size 7351 * ECMP Size used for matching on the existing entries. 7352 * Access: Index 7353 */ 7354 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7355 7356 /* reg_raleu_new_adjacency_index 7357 * New Adjacency Index. 7358 * Access: WO 7359 */ 7360 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7361 7362 /* reg_raleu_new_ecmp_size 7363 * New ECMP Size. 7364 * Access: WO 7365 */ 7366 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7367 7368 static inline void mlxsw_reg_raleu_pack(char *payload, 7369 enum mlxsw_reg_ralxx_protocol protocol, 7370 u16 virtual_router, 7371 u32 adjacency_index, u16 ecmp_size, 7372 u32 new_adjacency_index, 7373 u16 new_ecmp_size) 7374 { 7375 MLXSW_REG_ZERO(raleu, payload); 7376 mlxsw_reg_raleu_protocol_set(payload, protocol); 7377 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7378 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7379 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7380 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7381 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7382 } 7383 7384 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7385 * ---------------------------------------------------------------- 7386 * The RAUHTD register allows dumping entries from the Router Unicast Host 7387 * Table. For a given session an entry is dumped no more than one time. The 7388 * first RAUHTD access after reset is a new session. A session ends when the 7389 * num_rec response is smaller than num_rec request or for IPv4 when the 7390 * num_entries is smaller than 4. The clear activity affect the current session 7391 * or the last session if a new session has not started. 7392 */ 7393 #define MLXSW_REG_RAUHTD_ID 0x8018 7394 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7395 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7396 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7397 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7398 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7399 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7400 7401 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7402 7403 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7404 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7405 7406 /* reg_rauhtd_filter_fields 7407 * if a bit is '0' then the relevant field is ignored and dump is done 7408 * regardless of the field value 7409 * Bit0 - filter by activity: entry_a 7410 * Bit3 - filter by entry rip: entry_rif 7411 * Access: Index 7412 */ 7413 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7414 7415 enum mlxsw_reg_rauhtd_op { 7416 MLXSW_REG_RAUHTD_OP_DUMP, 7417 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7418 }; 7419 7420 /* reg_rauhtd_op 7421 * Access: OP 7422 */ 7423 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7424 7425 /* reg_rauhtd_num_rec 7426 * At request: number of records requested 7427 * At response: number of records dumped 7428 * For IPv4, each record has 4 entries at request and up to 4 entries 7429 * at response 7430 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7431 * Access: Index 7432 */ 7433 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7434 7435 /* reg_rauhtd_entry_a 7436 * Dump only if activity has value of entry_a 7437 * Reserved if filter_fields bit0 is '0' 7438 * Access: Index 7439 */ 7440 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7441 7442 enum mlxsw_reg_rauhtd_type { 7443 MLXSW_REG_RAUHTD_TYPE_IPV4, 7444 MLXSW_REG_RAUHTD_TYPE_IPV6, 7445 }; 7446 7447 /* reg_rauhtd_type 7448 * Dump only if record type is: 7449 * 0 - IPv4 7450 * 1 - IPv6 7451 * Access: Index 7452 */ 7453 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7454 7455 /* reg_rauhtd_entry_rif 7456 * Dump only if RIF has value of entry_rif 7457 * Reserved if filter_fields bit3 is '0' 7458 * Access: Index 7459 */ 7460 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7461 7462 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7463 enum mlxsw_reg_rauhtd_type type) 7464 { 7465 MLXSW_REG_ZERO(rauhtd, payload); 7466 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7467 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7468 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7469 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7470 mlxsw_reg_rauhtd_type_set(payload, type); 7471 } 7472 7473 /* reg_rauhtd_ipv4_rec_num_entries 7474 * Number of valid entries in this record: 7475 * 0 - 1 valid entry 7476 * 1 - 2 valid entries 7477 * 2 - 3 valid entries 7478 * 3 - 4 valid entries 7479 * Access: RO 7480 */ 7481 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7482 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7483 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7484 7485 /* reg_rauhtd_rec_type 7486 * Record type. 7487 * 0 - IPv4 7488 * 1 - IPv6 7489 * Access: RO 7490 */ 7491 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7492 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7493 7494 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7495 7496 /* reg_rauhtd_ipv4_ent_a 7497 * Activity. Set for new entries. Set if a packet lookup has hit on the 7498 * specific entry. 7499 * Access: RO 7500 */ 7501 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7502 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7503 7504 /* reg_rauhtd_ipv4_ent_rif 7505 * Router interface. 7506 * Access: RO 7507 */ 7508 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7509 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7510 7511 /* reg_rauhtd_ipv4_ent_dip 7512 * Destination IPv4 address. 7513 * Access: RO 7514 */ 7515 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7516 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7517 7518 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7519 7520 /* reg_rauhtd_ipv6_ent_a 7521 * Activity. Set for new entries. Set if a packet lookup has hit on the 7522 * specific entry. 7523 * Access: RO 7524 */ 7525 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7526 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7527 7528 /* reg_rauhtd_ipv6_ent_rif 7529 * Router interface. 7530 * Access: RO 7531 */ 7532 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7533 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7534 7535 /* reg_rauhtd_ipv6_ent_dip 7536 * Destination IPv6 address. 7537 * Access: RO 7538 */ 7539 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7540 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7541 7542 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7543 int ent_index, u16 *p_rif, 7544 u32 *p_dip) 7545 { 7546 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7547 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7548 } 7549 7550 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7551 int rec_index, u16 *p_rif, 7552 char *p_dip) 7553 { 7554 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7555 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7556 } 7557 7558 /* RTDP - Routing Tunnel Decap Properties Register 7559 * ----------------------------------------------- 7560 * The RTDP register is used for configuring the tunnel decap properties of NVE 7561 * and IPinIP. 7562 */ 7563 #define MLXSW_REG_RTDP_ID 0x8020 7564 #define MLXSW_REG_RTDP_LEN 0x44 7565 7566 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7567 7568 enum mlxsw_reg_rtdp_type { 7569 MLXSW_REG_RTDP_TYPE_NVE, 7570 MLXSW_REG_RTDP_TYPE_IPIP, 7571 }; 7572 7573 /* reg_rtdp_type 7574 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7575 * Access: RW 7576 */ 7577 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7578 7579 /* reg_rtdp_tunnel_index 7580 * Index to the Decap entry. 7581 * For Spectrum, Index to KVD Linear. 7582 * Access: Index 7583 */ 7584 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7585 7586 /* reg_rtdp_egress_router_interface 7587 * Underlay egress router interface. 7588 * Valid range is from 0 to cap_max_router_interfaces - 1 7589 * Access: RW 7590 */ 7591 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7592 7593 /* IPinIP */ 7594 7595 /* reg_rtdp_ipip_irif 7596 * Ingress Router Interface for the overlay router 7597 * Access: RW 7598 */ 7599 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7600 7601 enum mlxsw_reg_rtdp_ipip_sip_check { 7602 /* No sip checks. */ 7603 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7604 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7605 * equal ipv4_usip. 7606 */ 7607 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7608 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7609 * equal ipv6_usip. 7610 */ 7611 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7612 }; 7613 7614 /* reg_rtdp_ipip_sip_check 7615 * SIP check to perform. If decapsulation failed due to these configurations 7616 * then trap_id is IPIP_DECAP_ERROR. 7617 * Access: RW 7618 */ 7619 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7620 7621 /* If set, allow decapsulation of IPinIP (without GRE). */ 7622 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7623 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7624 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7625 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7626 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7627 7628 /* reg_rtdp_ipip_type_check 7629 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7630 * these configurations then trap_id is IPIP_DECAP_ERROR. 7631 * Access: RW 7632 */ 7633 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7634 7635 /* reg_rtdp_ipip_gre_key_check 7636 * Whether GRE key should be checked. When check is enabled: 7637 * - A packet received as IPinIP (without GRE) will always pass. 7638 * - A packet received as IPinGREinIP without a key will not pass the check. 7639 * - A packet received as IPinGREinIP with a key will pass the check only if the 7640 * key in the packet is equal to expected_gre_key. 7641 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7642 * Access: RW 7643 */ 7644 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7645 7646 /* reg_rtdp_ipip_ipv4_usip 7647 * Underlay IPv4 address for ipv4 source address check. 7648 * Reserved when sip_check is not '1'. 7649 * Access: RW 7650 */ 7651 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7652 7653 /* reg_rtdp_ipip_ipv6_usip_ptr 7654 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7655 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7656 * is to the KVD linear. 7657 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7658 * Access: RW 7659 */ 7660 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7661 7662 /* reg_rtdp_ipip_expected_gre_key 7663 * GRE key for checking. 7664 * Reserved when gre_key_check is '0'. 7665 * Access: RW 7666 */ 7667 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7668 7669 static inline void mlxsw_reg_rtdp_pack(char *payload, 7670 enum mlxsw_reg_rtdp_type type, 7671 u32 tunnel_index) 7672 { 7673 MLXSW_REG_ZERO(rtdp, payload); 7674 mlxsw_reg_rtdp_type_set(payload, type); 7675 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7676 } 7677 7678 static inline void 7679 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7680 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7681 unsigned int type_check, bool gre_key_check, 7682 u32 ipv4_usip, u32 expected_gre_key) 7683 { 7684 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7685 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7686 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7687 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7688 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7689 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7690 } 7691 7692 /* RIGR-V2 - Router Interface Group Register Version 2 7693 * --------------------------------------------------- 7694 * The RIGR_V2 register is used to add, remove and query egress interface list 7695 * of a multicast forwarding entry. 7696 */ 7697 #define MLXSW_REG_RIGR2_ID 0x8023 7698 #define MLXSW_REG_RIGR2_LEN 0xB0 7699 7700 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7701 7702 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7703 7704 /* reg_rigr2_rigr_index 7705 * KVD Linear index. 7706 * Access: Index 7707 */ 7708 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7709 7710 /* reg_rigr2_vnext 7711 * Next RIGR Index is valid. 7712 * Access: RW 7713 */ 7714 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7715 7716 /* reg_rigr2_next_rigr_index 7717 * Next RIGR Index. The index is to the KVD linear. 7718 * Reserved when vnxet = '0'. 7719 * Access: RW 7720 */ 7721 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7722 7723 /* reg_rigr2_vrmid 7724 * RMID Index is valid. 7725 * Access: RW 7726 */ 7727 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7728 7729 /* reg_rigr2_rmid_index 7730 * RMID Index. 7731 * Range 0 .. max_mid - 1 7732 * Reserved when vrmid = '0'. 7733 * The index is to the Port Group Table (PGT) 7734 * Access: RW 7735 */ 7736 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7737 7738 /* reg_rigr2_erif_entry_v 7739 * Egress Router Interface is valid. 7740 * Note that low-entries must be set if high-entries are set. For 7741 * example: if erif_entry[2].v is set then erif_entry[1].v and 7742 * erif_entry[0].v must be set. 7743 * Index can be from 0 to cap_mc_erif_list_entries-1 7744 * Access: RW 7745 */ 7746 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7747 7748 /* reg_rigr2_erif_entry_erif 7749 * Egress Router Interface. 7750 * Valid range is from 0 to cap_max_router_interfaces - 1 7751 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7752 * Access: RW 7753 */ 7754 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7755 7756 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7757 bool vnext, u32 next_rigr_index) 7758 { 7759 MLXSW_REG_ZERO(rigr2, payload); 7760 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7761 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7762 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7763 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7764 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7765 } 7766 7767 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7768 bool v, u16 erif) 7769 { 7770 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7771 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7772 } 7773 7774 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7775 * ------------------------------------------------------ 7776 */ 7777 #define MLXSW_REG_RECR2_ID 0x8025 7778 #define MLXSW_REG_RECR2_LEN 0x38 7779 7780 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7781 7782 /* reg_recr2_pp 7783 * Per-port configuration 7784 * Access: Index 7785 */ 7786 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7787 7788 /* reg_recr2_sh 7789 * Symmetric hash 7790 * Access: RW 7791 */ 7792 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7793 7794 /* reg_recr2_seed 7795 * Seed 7796 * Access: RW 7797 */ 7798 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7799 7800 enum { 7801 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7802 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7803 /* Enable IPv4 fields if packet is TCP or UDP */ 7804 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7805 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7806 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7807 /* Enable IPv6 fields if packet is TCP or UDP */ 7808 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7809 /* Enable TCP/UDP header fields if packet is IPv4 */ 7810 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7811 /* Enable TCP/UDP header fields if packet is IPv6 */ 7812 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7813 }; 7814 7815 /* reg_recr2_outer_header_enables 7816 * Bit mask where each bit enables a specific layer to be included in 7817 * the hash calculation. 7818 * Access: RW 7819 */ 7820 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7821 7822 enum { 7823 /* IPv4 Source IP */ 7824 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7825 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7826 /* IPv4 Destination IP */ 7827 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7828 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7829 /* IP Protocol */ 7830 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7831 /* IPv6 Source IP */ 7832 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7833 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7834 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7835 /* IPv6 Destination IP */ 7836 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7837 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7838 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7839 /* IPv6 Next Header */ 7840 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7841 /* IPv6 Flow Label */ 7842 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7843 /* TCP/UDP Source Port */ 7844 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7845 /* TCP/UDP Destination Port */ 7846 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7847 }; 7848 7849 /* reg_recr2_outer_header_fields_enable 7850 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7851 * Access: RW 7852 */ 7853 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7854 7855 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7856 { 7857 int i; 7858 7859 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7860 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7861 true); 7862 } 7863 7864 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7865 { 7866 int i; 7867 7868 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7869 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7870 true); 7871 } 7872 7873 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7874 { 7875 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7876 7877 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7878 7879 i = MLXSW_REG_RECR2_IPV6_SIP8; 7880 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7881 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7882 true); 7883 } 7884 7885 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7886 { 7887 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7888 7889 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7890 7891 i = MLXSW_REG_RECR2_IPV6_DIP8; 7892 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7893 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7894 true); 7895 } 7896 7897 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7898 { 7899 MLXSW_REG_ZERO(recr2, payload); 7900 mlxsw_reg_recr2_pp_set(payload, false); 7901 mlxsw_reg_recr2_sh_set(payload, true); 7902 mlxsw_reg_recr2_seed_set(payload, seed); 7903 } 7904 7905 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7906 * -------------------------------------------------------------- 7907 * The RMFT_V2 register is used to configure and query the multicast table. 7908 */ 7909 #define MLXSW_REG_RMFT2_ID 0x8027 7910 #define MLXSW_REG_RMFT2_LEN 0x174 7911 7912 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7913 7914 /* reg_rmft2_v 7915 * Valid 7916 * Access: RW 7917 */ 7918 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7919 7920 enum mlxsw_reg_rmft2_type { 7921 MLXSW_REG_RMFT2_TYPE_IPV4, 7922 MLXSW_REG_RMFT2_TYPE_IPV6 7923 }; 7924 7925 /* reg_rmft2_type 7926 * Access: Index 7927 */ 7928 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7929 7930 enum mlxsw_sp_reg_rmft2_op { 7931 /* For Write: 7932 * Write operation. Used to write a new entry to the table. All RW 7933 * fields are relevant for new entry. Activity bit is set for new 7934 * entries - Note write with v (Valid) 0 will delete the entry. 7935 * For Query: 7936 * Read operation 7937 */ 7938 MLXSW_REG_RMFT2_OP_READ_WRITE, 7939 }; 7940 7941 /* reg_rmft2_op 7942 * Operation. 7943 * Access: OP 7944 */ 7945 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7946 7947 /* reg_rmft2_a 7948 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7949 * entry. 7950 * Access: RO 7951 */ 7952 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7953 7954 /* reg_rmft2_offset 7955 * Offset within the multicast forwarding table to write to. 7956 * Access: Index 7957 */ 7958 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7959 7960 /* reg_rmft2_virtual_router 7961 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7962 * Access: RW 7963 */ 7964 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7965 7966 enum mlxsw_reg_rmft2_irif_mask { 7967 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7968 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7969 }; 7970 7971 /* reg_rmft2_irif_mask 7972 * Ingress RIF mask. 7973 * Access: RW 7974 */ 7975 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7976 7977 /* reg_rmft2_irif 7978 * Ingress RIF index. 7979 * Access: RW 7980 */ 7981 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7982 7983 /* reg_rmft2_dip{4,6} 7984 * Destination IPv4/6 address 7985 * Access: RW 7986 */ 7987 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7988 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7989 7990 /* reg_rmft2_dip{4,6}_mask 7991 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7992 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7993 * Access: RW 7994 */ 7995 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7996 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7997 7998 /* reg_rmft2_sip{4,6} 7999 * Source IPv4/6 address 8000 * Access: RW 8001 */ 8002 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8003 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8004 8005 /* reg_rmft2_sip{4,6}_mask 8006 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8007 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8008 * Access: RW 8009 */ 8010 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8011 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8012 8013 /* reg_rmft2_flexible_action_set 8014 * ACL action set. The only supported action types in this field and in any 8015 * action-set pointed from here are as follows: 8016 * 00h: ACTION_NULL 8017 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8018 * 03h: ACTION_TRAP 8019 * 06h: ACTION_QOS 8020 * 08h: ACTION_POLICING_MONITORING 8021 * 10h: ACTION_ROUTER_MC 8022 * Access: RW 8023 */ 8024 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8025 MLXSW_REG_FLEX_ACTION_SET_LEN); 8026 8027 static inline void 8028 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8029 u16 virtual_router, 8030 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8031 const char *flex_action_set) 8032 { 8033 MLXSW_REG_ZERO(rmft2, payload); 8034 mlxsw_reg_rmft2_v_set(payload, v); 8035 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8036 mlxsw_reg_rmft2_offset_set(payload, offset); 8037 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8038 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8039 mlxsw_reg_rmft2_irif_set(payload, irif); 8040 if (flex_action_set) 8041 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8042 flex_action_set); 8043 } 8044 8045 static inline void 8046 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8047 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8048 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8049 const char *flexible_action_set) 8050 { 8051 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8052 irif_mask, irif, flexible_action_set); 8053 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8054 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8055 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8056 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8057 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8058 } 8059 8060 static inline void 8061 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8062 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8063 struct in6_addr dip6, struct in6_addr dip6_mask, 8064 struct in6_addr sip6, struct in6_addr sip6_mask, 8065 const char *flexible_action_set) 8066 { 8067 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8068 irif_mask, irif, flexible_action_set); 8069 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8070 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8071 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8072 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8073 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8074 } 8075 8076 /* MFCR - Management Fan Control Register 8077 * -------------------------------------- 8078 * This register controls the settings of the Fan Speed PWM mechanism. 8079 */ 8080 #define MLXSW_REG_MFCR_ID 0x9001 8081 #define MLXSW_REG_MFCR_LEN 0x08 8082 8083 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8084 8085 enum mlxsw_reg_mfcr_pwm_frequency { 8086 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8087 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8088 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8089 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8090 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8091 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8092 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8093 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8094 }; 8095 8096 /* reg_mfcr_pwm_frequency 8097 * Controls the frequency of the PWM signal. 8098 * Access: RW 8099 */ 8100 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8101 8102 #define MLXSW_MFCR_TACHOS_MAX 10 8103 8104 /* reg_mfcr_tacho_active 8105 * Indicates which of the tachometer is active (bit per tachometer). 8106 * Access: RO 8107 */ 8108 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8109 8110 #define MLXSW_MFCR_PWMS_MAX 5 8111 8112 /* reg_mfcr_pwm_active 8113 * Indicates which of the PWM control is active (bit per PWM). 8114 * Access: RO 8115 */ 8116 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8117 8118 static inline void 8119 mlxsw_reg_mfcr_pack(char *payload, 8120 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8121 { 8122 MLXSW_REG_ZERO(mfcr, payload); 8123 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8124 } 8125 8126 static inline void 8127 mlxsw_reg_mfcr_unpack(char *payload, 8128 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8129 u16 *p_tacho_active, u8 *p_pwm_active) 8130 { 8131 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8132 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8133 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8134 } 8135 8136 /* MFSC - Management Fan Speed Control Register 8137 * -------------------------------------------- 8138 * This register controls the settings of the Fan Speed PWM mechanism. 8139 */ 8140 #define MLXSW_REG_MFSC_ID 0x9002 8141 #define MLXSW_REG_MFSC_LEN 0x08 8142 8143 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8144 8145 /* reg_mfsc_pwm 8146 * Fan pwm to control / monitor. 8147 * Access: Index 8148 */ 8149 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8150 8151 /* reg_mfsc_pwm_duty_cycle 8152 * Controls the duty cycle of the PWM. Value range from 0..255 to 8153 * represent duty cycle of 0%...100%. 8154 * Access: RW 8155 */ 8156 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8157 8158 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8159 u8 pwm_duty_cycle) 8160 { 8161 MLXSW_REG_ZERO(mfsc, payload); 8162 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8163 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8164 } 8165 8166 /* MFSM - Management Fan Speed Measurement 8167 * --------------------------------------- 8168 * This register controls the settings of the Tacho measurements and 8169 * enables reading the Tachometer measurements. 8170 */ 8171 #define MLXSW_REG_MFSM_ID 0x9003 8172 #define MLXSW_REG_MFSM_LEN 0x08 8173 8174 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8175 8176 /* reg_mfsm_tacho 8177 * Fan tachometer index. 8178 * Access: Index 8179 */ 8180 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8181 8182 /* reg_mfsm_rpm 8183 * Fan speed (round per minute). 8184 * Access: RO 8185 */ 8186 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8187 8188 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8189 { 8190 MLXSW_REG_ZERO(mfsm, payload); 8191 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8192 } 8193 8194 /* MFSL - Management Fan Speed Limit Register 8195 * ------------------------------------------ 8196 * The Fan Speed Limit register is used to configure the fan speed 8197 * event / interrupt notification mechanism. Fan speed threshold are 8198 * defined for both under-speed and over-speed. 8199 */ 8200 #define MLXSW_REG_MFSL_ID 0x9004 8201 #define MLXSW_REG_MFSL_LEN 0x0C 8202 8203 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8204 8205 /* reg_mfsl_tacho 8206 * Fan tachometer index. 8207 * Access: Index 8208 */ 8209 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8210 8211 /* reg_mfsl_tach_min 8212 * Tachometer minimum value (minimum RPM). 8213 * Access: RW 8214 */ 8215 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8216 8217 /* reg_mfsl_tach_max 8218 * Tachometer maximum value (maximum RPM). 8219 * Access: RW 8220 */ 8221 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8222 8223 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8224 u16 tach_min, u16 tach_max) 8225 { 8226 MLXSW_REG_ZERO(mfsl, payload); 8227 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8228 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8229 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8230 } 8231 8232 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8233 u16 *p_tach_min, u16 *p_tach_max) 8234 { 8235 if (p_tach_min) 8236 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8237 8238 if (p_tach_max) 8239 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8240 } 8241 8242 /* FORE - Fan Out of Range Event Register 8243 * -------------------------------------- 8244 * This register reports the status of the controlled fans compared to the 8245 * range defined by the MFSL register. 8246 */ 8247 #define MLXSW_REG_FORE_ID 0x9007 8248 #define MLXSW_REG_FORE_LEN 0x0C 8249 8250 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8251 8252 /* fan_under_limit 8253 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8254 * to a single tachometer and indicates the specific tachometer reading is 8255 * below the threshold. 8256 * Access: RO 8257 */ 8258 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8259 8260 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8261 bool *fault) 8262 { 8263 u16 limit; 8264 8265 if (fault) { 8266 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8267 *fault = limit & BIT(tacho); 8268 } 8269 } 8270 8271 /* MTCAP - Management Temperature Capabilities 8272 * ------------------------------------------- 8273 * This register exposes the capabilities of the device and 8274 * system temperature sensing. 8275 */ 8276 #define MLXSW_REG_MTCAP_ID 0x9009 8277 #define MLXSW_REG_MTCAP_LEN 0x08 8278 8279 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8280 8281 /* reg_mtcap_sensor_count 8282 * Number of sensors supported by the device. 8283 * This includes the QSFP module sensors (if exists in the QSFP module). 8284 * Access: RO 8285 */ 8286 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8287 8288 /* MTMP - Management Temperature 8289 * ----------------------------- 8290 * This register controls the settings of the temperature measurements 8291 * and enables reading the temperature measurements. Note that temperature 8292 * is in 0.125 degrees Celsius. 8293 */ 8294 #define MLXSW_REG_MTMP_ID 0x900A 8295 #define MLXSW_REG_MTMP_LEN 0x20 8296 8297 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8298 8299 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8300 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8301 /* reg_mtmp_sensor_index 8302 * Sensors index to access. 8303 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8304 * (module 0 is mapped to sensor_index 64). 8305 * Access: Index 8306 */ 8307 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8308 8309 /* Convert to milli degrees Celsius */ 8310 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8311 ((v_) >= 0) ? ((v_) * 125) : \ 8312 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8313 * 125)); }) 8314 8315 /* reg_mtmp_temperature 8316 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8317 * degrees units. 8318 * Access: RO 8319 */ 8320 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8321 8322 /* reg_mtmp_mte 8323 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8324 * Access: RW 8325 */ 8326 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8327 8328 /* reg_mtmp_mtr 8329 * Max Temperature Reset - clears the value of the max temperature register. 8330 * Access: WO 8331 */ 8332 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8333 8334 /* reg_mtmp_max_temperature 8335 * The highest measured temperature from the sensor. 8336 * When the bit mte is cleared, the field max_temperature is reserved. 8337 * Access: RO 8338 */ 8339 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8340 8341 /* reg_mtmp_tee 8342 * Temperature Event Enable. 8343 * 0 - Do not generate event 8344 * 1 - Generate event 8345 * 2 - Generate single event 8346 * Access: RW 8347 */ 8348 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8349 8350 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8351 8352 /* reg_mtmp_temperature_threshold_hi 8353 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8354 * Access: RW 8355 */ 8356 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8357 8358 /* reg_mtmp_temperature_threshold_lo 8359 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8360 * Access: RW 8361 */ 8362 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8363 8364 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8365 8366 /* reg_mtmp_sensor_name 8367 * Sensor Name 8368 * Access: RO 8369 */ 8370 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8371 8372 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8373 bool max_temp_enable, 8374 bool max_temp_reset) 8375 { 8376 MLXSW_REG_ZERO(mtmp, payload); 8377 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8378 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8379 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8380 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8381 MLXSW_REG_MTMP_THRESH_HI); 8382 } 8383 8384 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8385 int *p_max_temp, char *sensor_name) 8386 { 8387 s16 temp; 8388 8389 if (p_temp) { 8390 temp = mlxsw_reg_mtmp_temperature_get(payload); 8391 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8392 } 8393 if (p_max_temp) { 8394 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8395 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8396 } 8397 if (sensor_name) 8398 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8399 } 8400 8401 /* MTBR - Management Temperature Bulk Register 8402 * ------------------------------------------- 8403 * This register is used for bulk temperature reading. 8404 */ 8405 #define MLXSW_REG_MTBR_ID 0x900F 8406 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8407 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8408 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8409 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8410 MLXSW_REG_MTBR_REC_LEN * \ 8411 MLXSW_REG_MTBR_REC_MAX_COUNT) 8412 8413 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8414 8415 /* reg_mtbr_base_sensor_index 8416 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8417 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8418 * Access: Index 8419 */ 8420 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8421 8422 /* reg_mtbr_num_rec 8423 * Request: Number of records to read 8424 * Response: Number of records read 8425 * See above description for more details. 8426 * Range 1..255 8427 * Access: RW 8428 */ 8429 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8430 8431 /* reg_mtbr_rec_max_temp 8432 * The highest measured temperature from the sensor. 8433 * When the bit mte is cleared, the field max_temperature is reserved. 8434 * Access: RO 8435 */ 8436 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8437 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8438 8439 /* reg_mtbr_rec_temp 8440 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8441 * degrees units. 8442 * Access: RO 8443 */ 8444 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8445 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8446 8447 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8448 u8 num_rec) 8449 { 8450 MLXSW_REG_ZERO(mtbr, payload); 8451 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8452 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8453 } 8454 8455 /* Error codes from temperatute reading */ 8456 enum mlxsw_reg_mtbr_temp_status { 8457 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8458 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8459 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8460 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8461 }; 8462 8463 /* Base index for reading modules temperature */ 8464 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8465 8466 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8467 u16 *p_temp, u16 *p_max_temp) 8468 { 8469 if (p_temp) 8470 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8471 if (p_max_temp) 8472 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8473 } 8474 8475 /* MCIA - Management Cable Info Access 8476 * ----------------------------------- 8477 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8478 */ 8479 8480 #define MLXSW_REG_MCIA_ID 0x9014 8481 #define MLXSW_REG_MCIA_LEN 0x40 8482 8483 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8484 8485 /* reg_mcia_l 8486 * Lock bit. Setting this bit will lock the access to the specific 8487 * cable. Used for updating a full page in a cable EPROM. Any access 8488 * other then subsequence writes will fail while the port is locked. 8489 * Access: RW 8490 */ 8491 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8492 8493 /* reg_mcia_module 8494 * Module number. 8495 * Access: Index 8496 */ 8497 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8498 8499 /* reg_mcia_status 8500 * Module status. 8501 * Access: RO 8502 */ 8503 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8504 8505 /* reg_mcia_i2c_device_address 8506 * I2C device address. 8507 * Access: RW 8508 */ 8509 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8510 8511 /* reg_mcia_page_number 8512 * Page number. 8513 * Access: RW 8514 */ 8515 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8516 8517 /* reg_mcia_device_address 8518 * Device address. 8519 * Access: RW 8520 */ 8521 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8522 8523 /* reg_mcia_size 8524 * Number of bytes to read/write (up to 48 bytes). 8525 * Access: RW 8526 */ 8527 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8528 8529 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8530 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 8531 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8532 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8533 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8534 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8535 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8536 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8537 #define MLXSW_REG_MCIA_PAGE0_LO 0 8538 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8539 8540 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8541 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8542 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8543 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8544 }; 8545 8546 enum mlxsw_reg_mcia_eeprom_module_info_id { 8547 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8548 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8549 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8550 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8551 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8552 }; 8553 8554 enum mlxsw_reg_mcia_eeprom_module_info { 8555 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8556 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8557 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8558 }; 8559 8560 /* reg_mcia_eeprom 8561 * Bytes to read/write. 8562 * Access: RW 8563 */ 8564 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8565 8566 /* This is used to access the optional upper pages (1-3) in the QSFP+ 8567 * memory map. Page 1 is available on offset 256 through 383, page 2 - 8568 * on offset 384 through 511, page 3 - on offset 512 through 639. 8569 */ 8570 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 8571 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 8572 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 8573 8574 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8575 u8 page_number, u16 device_addr, 8576 u8 size, u8 i2c_device_addr) 8577 { 8578 MLXSW_REG_ZERO(mcia, payload); 8579 mlxsw_reg_mcia_module_set(payload, module); 8580 mlxsw_reg_mcia_l_set(payload, lock); 8581 mlxsw_reg_mcia_page_number_set(payload, page_number); 8582 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8583 mlxsw_reg_mcia_size_set(payload, size); 8584 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8585 } 8586 8587 /* MPAT - Monitoring Port Analyzer Table 8588 * ------------------------------------- 8589 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8590 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8591 */ 8592 #define MLXSW_REG_MPAT_ID 0x901A 8593 #define MLXSW_REG_MPAT_LEN 0x78 8594 8595 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8596 8597 /* reg_mpat_pa_id 8598 * Port Analyzer ID. 8599 * Access: Index 8600 */ 8601 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8602 8603 /* reg_mpat_system_port 8604 * A unique port identifier for the final destination of the packet. 8605 * Access: RW 8606 */ 8607 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8608 8609 /* reg_mpat_e 8610 * Enable. Indicating the Port Analyzer is enabled. 8611 * Access: RW 8612 */ 8613 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8614 8615 /* reg_mpat_qos 8616 * Quality Of Service Mode. 8617 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8618 * PCP, DEI, DSCP or VL) are configured. 8619 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8620 * same as in the original packet that has triggered the mirroring. For 8621 * SPAN also the pcp,dei are maintained. 8622 * Access: RW 8623 */ 8624 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8625 8626 /* reg_mpat_be 8627 * Best effort mode. Indicates mirroring traffic should not cause packet 8628 * drop or back pressure, but will discard the mirrored packets. Mirrored 8629 * packets will be forwarded on a best effort manner. 8630 * 0: Do not discard mirrored packets 8631 * 1: Discard mirrored packets if causing congestion 8632 * Access: RW 8633 */ 8634 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8635 8636 enum mlxsw_reg_mpat_span_type { 8637 /* Local SPAN Ethernet. 8638 * The original packet is not encapsulated. 8639 */ 8640 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8641 8642 /* Remote SPAN Ethernet VLAN. 8643 * The packet is forwarded to the monitoring port on the monitoring 8644 * VLAN. 8645 */ 8646 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8647 8648 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8649 * The packet is encapsulated with GRE header. 8650 */ 8651 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8652 }; 8653 8654 /* reg_mpat_span_type 8655 * SPAN type. 8656 * Access: RW 8657 */ 8658 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8659 8660 /* Remote SPAN - Ethernet VLAN 8661 * - - - - - - - - - - - - - - 8662 */ 8663 8664 /* reg_mpat_eth_rspan_vid 8665 * Encapsulation header VLAN ID. 8666 * Access: RW 8667 */ 8668 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8669 8670 /* Encapsulated Remote SPAN - Ethernet L2 8671 * - - - - - - - - - - - - - - - - - - - 8672 */ 8673 8674 enum mlxsw_reg_mpat_eth_rspan_version { 8675 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8676 }; 8677 8678 /* reg_mpat_eth_rspan_version 8679 * RSPAN mirror header version. 8680 * Access: RW 8681 */ 8682 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8683 8684 /* reg_mpat_eth_rspan_mac 8685 * Destination MAC address. 8686 * Access: RW 8687 */ 8688 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8689 8690 /* reg_mpat_eth_rspan_tp 8691 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8692 * Access: RW 8693 */ 8694 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8695 8696 /* Encapsulated Remote SPAN - Ethernet L3 8697 * - - - - - - - - - - - - - - - - - - - 8698 */ 8699 8700 enum mlxsw_reg_mpat_eth_rspan_protocol { 8701 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8702 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8703 }; 8704 8705 /* reg_mpat_eth_rspan_protocol 8706 * SPAN encapsulation protocol. 8707 * Access: RW 8708 */ 8709 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8710 8711 /* reg_mpat_eth_rspan_ttl 8712 * Encapsulation header Time-to-Live/HopLimit. 8713 * Access: RW 8714 */ 8715 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8716 8717 /* reg_mpat_eth_rspan_smac 8718 * Source MAC address 8719 * Access: RW 8720 */ 8721 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8722 8723 /* reg_mpat_eth_rspan_dip* 8724 * Destination IP address. The IP version is configured by protocol. 8725 * Access: RW 8726 */ 8727 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8728 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8729 8730 /* reg_mpat_eth_rspan_sip* 8731 * Source IP address. The IP version is configured by protocol. 8732 * Access: RW 8733 */ 8734 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8735 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8736 8737 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8738 u16 system_port, bool e, 8739 enum mlxsw_reg_mpat_span_type span_type) 8740 { 8741 MLXSW_REG_ZERO(mpat, payload); 8742 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8743 mlxsw_reg_mpat_system_port_set(payload, system_port); 8744 mlxsw_reg_mpat_e_set(payload, e); 8745 mlxsw_reg_mpat_qos_set(payload, 1); 8746 mlxsw_reg_mpat_be_set(payload, 1); 8747 mlxsw_reg_mpat_span_type_set(payload, span_type); 8748 } 8749 8750 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8751 { 8752 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8753 } 8754 8755 static inline void 8756 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8757 enum mlxsw_reg_mpat_eth_rspan_version version, 8758 const char *mac, 8759 bool tp) 8760 { 8761 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8762 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8763 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8764 } 8765 8766 static inline void 8767 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8768 const char *smac, 8769 u32 sip, u32 dip) 8770 { 8771 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8772 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8773 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8774 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8775 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8776 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8777 } 8778 8779 static inline void 8780 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8781 const char *smac, 8782 struct in6_addr sip, struct in6_addr dip) 8783 { 8784 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8785 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8786 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8787 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8788 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8789 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8790 } 8791 8792 /* MPAR - Monitoring Port Analyzer Register 8793 * ---------------------------------------- 8794 * MPAR register is used to query and configure the port analyzer port mirroring 8795 * properties. 8796 */ 8797 #define MLXSW_REG_MPAR_ID 0x901B 8798 #define MLXSW_REG_MPAR_LEN 0x0C 8799 8800 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8801 8802 /* reg_mpar_local_port 8803 * The local port to mirror the packets from. 8804 * Access: Index 8805 */ 8806 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8807 8808 enum mlxsw_reg_mpar_i_e { 8809 MLXSW_REG_MPAR_TYPE_EGRESS, 8810 MLXSW_REG_MPAR_TYPE_INGRESS, 8811 }; 8812 8813 /* reg_mpar_i_e 8814 * Ingress/Egress 8815 * Access: Index 8816 */ 8817 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8818 8819 /* reg_mpar_enable 8820 * Enable mirroring 8821 * By default, port mirroring is disabled for all ports. 8822 * Access: RW 8823 */ 8824 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8825 8826 /* reg_mpar_pa_id 8827 * Port Analyzer ID. 8828 * Access: RW 8829 */ 8830 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8831 8832 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8833 enum mlxsw_reg_mpar_i_e i_e, 8834 bool enable, u8 pa_id) 8835 { 8836 MLXSW_REG_ZERO(mpar, payload); 8837 mlxsw_reg_mpar_local_port_set(payload, local_port); 8838 mlxsw_reg_mpar_enable_set(payload, enable); 8839 mlxsw_reg_mpar_i_e_set(payload, i_e); 8840 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8841 } 8842 8843 /* MGIR - Management General Information Register 8844 * ---------------------------------------------- 8845 * MGIR register allows software to query the hardware and firmware general 8846 * information. 8847 */ 8848 #define MLXSW_REG_MGIR_ID 0x9020 8849 #define MLXSW_REG_MGIR_LEN 0x9C 8850 8851 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 8852 8853 /* reg_mgir_hw_info_device_hw_revision 8854 * Access: RO 8855 */ 8856 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 8857 8858 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 8859 8860 /* reg_mgir_fw_info_psid 8861 * PSID (ASCII string). 8862 * Access: RO 8863 */ 8864 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 8865 8866 /* reg_mgir_fw_info_extended_major 8867 * Access: RO 8868 */ 8869 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 8870 8871 /* reg_mgir_fw_info_extended_minor 8872 * Access: RO 8873 */ 8874 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 8875 8876 /* reg_mgir_fw_info_extended_sub_minor 8877 * Access: RO 8878 */ 8879 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 8880 8881 static inline void mlxsw_reg_mgir_pack(char *payload) 8882 { 8883 MLXSW_REG_ZERO(mgir, payload); 8884 } 8885 8886 static inline void 8887 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 8888 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 8889 { 8890 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 8891 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 8892 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 8893 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 8894 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 8895 } 8896 8897 /* MRSR - Management Reset and Shutdown Register 8898 * --------------------------------------------- 8899 * MRSR register is used to reset or shutdown the switch or 8900 * the entire system (when applicable). 8901 */ 8902 #define MLXSW_REG_MRSR_ID 0x9023 8903 #define MLXSW_REG_MRSR_LEN 0x08 8904 8905 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8906 8907 /* reg_mrsr_command 8908 * Reset/shutdown command 8909 * 0 - do nothing 8910 * 1 - software reset 8911 * Access: WO 8912 */ 8913 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8914 8915 static inline void mlxsw_reg_mrsr_pack(char *payload) 8916 { 8917 MLXSW_REG_ZERO(mrsr, payload); 8918 mlxsw_reg_mrsr_command_set(payload, 1); 8919 } 8920 8921 /* MLCR - Management LED Control Register 8922 * -------------------------------------- 8923 * Controls the system LEDs. 8924 */ 8925 #define MLXSW_REG_MLCR_ID 0x902B 8926 #define MLXSW_REG_MLCR_LEN 0x0C 8927 8928 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8929 8930 /* reg_mlcr_local_port 8931 * Local port number. 8932 * Access: RW 8933 */ 8934 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8935 8936 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8937 8938 /* reg_mlcr_beacon_duration 8939 * Duration of the beacon to be active, in seconds. 8940 * 0x0 - Will turn off the beacon. 8941 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8942 * Access: RW 8943 */ 8944 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8945 8946 /* reg_mlcr_beacon_remain 8947 * Remaining duration of the beacon, in seconds. 8948 * 0xFFFF indicates an infinite amount of time. 8949 * Access: RO 8950 */ 8951 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8952 8953 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8954 bool active) 8955 { 8956 MLXSW_REG_ZERO(mlcr, payload); 8957 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8958 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8959 MLXSW_REG_MLCR_DURATION_MAX : 0); 8960 } 8961 8962 /* MTPPS - Management Pulse Per Second Register 8963 * -------------------------------------------- 8964 * This register provides the device PPS capabilities, configure the PPS in and 8965 * out modules and holds the PPS in time stamp. 8966 */ 8967 #define MLXSW_REG_MTPPS_ID 0x9053 8968 #define MLXSW_REG_MTPPS_LEN 0x3C 8969 8970 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 8971 8972 /* reg_mtpps_enable 8973 * Enables the PPS functionality the specific pin. 8974 * A boolean variable. 8975 * Access: RW 8976 */ 8977 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 8978 8979 enum mlxsw_reg_mtpps_pin_mode { 8980 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 8981 }; 8982 8983 /* reg_mtpps_pin_mode 8984 * Pin mode to be used. The mode must comply with the supported modes of the 8985 * requested pin. 8986 * Access: RW 8987 */ 8988 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 8989 8990 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 8991 8992 /* reg_mtpps_pin 8993 * Pin to be configured or queried out of the supported pins. 8994 * Access: Index 8995 */ 8996 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 8997 8998 /* reg_mtpps_time_stamp 8999 * When pin_mode = pps_in, the latched device time when it was triggered from 9000 * the external GPIO pin. 9001 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 9002 * time to generate next output signal. 9003 * Time is in units of device clock. 9004 * Access: RW 9005 */ 9006 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 9007 9008 static inline void 9009 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 9010 { 9011 MLXSW_REG_ZERO(mtpps, payload); 9012 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 9013 mlxsw_reg_mtpps_pin_mode_set(payload, 9014 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 9015 mlxsw_reg_mtpps_enable_set(payload, true); 9016 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 9017 } 9018 9019 /* MTUTC - Management UTC Register 9020 * ------------------------------- 9021 * Configures the HW UTC counter. 9022 */ 9023 #define MLXSW_REG_MTUTC_ID 0x9055 9024 #define MLXSW_REG_MTUTC_LEN 0x1C 9025 9026 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 9027 9028 enum mlxsw_reg_mtutc_operation { 9029 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 9030 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 9031 }; 9032 9033 /* reg_mtutc_operation 9034 * Operation. 9035 * Access: OP 9036 */ 9037 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 9038 9039 /* reg_mtutc_freq_adjustment 9040 * Frequency adjustment: Every PPS the HW frequency will be 9041 * adjusted by this value. Units of HW clock, where HW counts 9042 * 10^9 HW clocks for 1 HW second. 9043 * Access: RW 9044 */ 9045 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 9046 9047 /* reg_mtutc_utc_sec 9048 * UTC seconds. 9049 * Access: WO 9050 */ 9051 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 9052 9053 static inline void 9054 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 9055 u32 freq_adj, u32 utc_sec) 9056 { 9057 MLXSW_REG_ZERO(mtutc, payload); 9058 mlxsw_reg_mtutc_operation_set(payload, oper); 9059 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 9060 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 9061 } 9062 9063 /* MCQI - Management Component Query Information 9064 * --------------------------------------------- 9065 * This register allows querying information about firmware components. 9066 */ 9067 #define MLXSW_REG_MCQI_ID 0x9061 9068 #define MLXSW_REG_MCQI_BASE_LEN 0x18 9069 #define MLXSW_REG_MCQI_CAP_LEN 0x14 9070 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9071 9072 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9073 9074 /* reg_mcqi_component_index 9075 * Index of the accessed component. 9076 * Access: Index 9077 */ 9078 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9079 9080 enum mlxfw_reg_mcqi_info_type { 9081 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9082 }; 9083 9084 /* reg_mcqi_info_type 9085 * Component properties set. 9086 * Access: RW 9087 */ 9088 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9089 9090 /* reg_mcqi_offset 9091 * The requested/returned data offset from the section start, given in bytes. 9092 * Must be DWORD aligned. 9093 * Access: RW 9094 */ 9095 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9096 9097 /* reg_mcqi_data_size 9098 * The requested/returned data size, given in bytes. If data_size is not DWORD 9099 * aligned, the last bytes are zero padded. 9100 * Access: RW 9101 */ 9102 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9103 9104 /* reg_mcqi_cap_max_component_size 9105 * Maximum size for this component, given in bytes. 9106 * Access: RO 9107 */ 9108 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9109 9110 /* reg_mcqi_cap_log_mcda_word_size 9111 * Log 2 of the access word size in bytes. Read and write access must be aligned 9112 * to the word size. Write access must be done for an integer number of words. 9113 * Access: RO 9114 */ 9115 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9116 9117 /* reg_mcqi_cap_mcda_max_write_size 9118 * Maximal write size for MCDA register 9119 * Access: RO 9120 */ 9121 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9122 9123 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9124 { 9125 MLXSW_REG_ZERO(mcqi, payload); 9126 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9127 mlxsw_reg_mcqi_info_type_set(payload, 9128 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9129 mlxsw_reg_mcqi_offset_set(payload, 0); 9130 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9131 } 9132 9133 static inline void mlxsw_reg_mcqi_unpack(char *payload, 9134 u32 *p_cap_max_component_size, 9135 u8 *p_cap_log_mcda_word_size, 9136 u16 *p_cap_mcda_max_write_size) 9137 { 9138 *p_cap_max_component_size = 9139 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9140 *p_cap_log_mcda_word_size = 9141 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9142 *p_cap_mcda_max_write_size = 9143 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9144 } 9145 9146 /* MCC - Management Component Control 9147 * ---------------------------------- 9148 * Controls the firmware component and updates the FSM. 9149 */ 9150 #define MLXSW_REG_MCC_ID 0x9062 9151 #define MLXSW_REG_MCC_LEN 0x1C 9152 9153 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9154 9155 enum mlxsw_reg_mcc_instruction { 9156 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9157 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9158 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9159 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9160 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9161 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9162 }; 9163 9164 /* reg_mcc_instruction 9165 * Command to be executed by the FSM. 9166 * Applicable for write operation only. 9167 * Access: RW 9168 */ 9169 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9170 9171 /* reg_mcc_component_index 9172 * Index of the accessed component. Applicable only for commands that 9173 * refer to components. Otherwise, this field is reserved. 9174 * Access: Index 9175 */ 9176 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9177 9178 /* reg_mcc_update_handle 9179 * Token representing the current flow executed by the FSM. 9180 * Access: WO 9181 */ 9182 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9183 9184 /* reg_mcc_error_code 9185 * Indicates the successful completion of the instruction, or the reason it 9186 * failed 9187 * Access: RO 9188 */ 9189 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9190 9191 /* reg_mcc_control_state 9192 * Current FSM state 9193 * Access: RO 9194 */ 9195 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9196 9197 /* reg_mcc_component_size 9198 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9199 * the size may shorten the update time. Value 0x0 means that size is 9200 * unspecified. 9201 * Access: WO 9202 */ 9203 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9204 9205 static inline void mlxsw_reg_mcc_pack(char *payload, 9206 enum mlxsw_reg_mcc_instruction instr, 9207 u16 component_index, u32 update_handle, 9208 u32 component_size) 9209 { 9210 MLXSW_REG_ZERO(mcc, payload); 9211 mlxsw_reg_mcc_instruction_set(payload, instr); 9212 mlxsw_reg_mcc_component_index_set(payload, component_index); 9213 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9214 mlxsw_reg_mcc_component_size_set(payload, component_size); 9215 } 9216 9217 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9218 u8 *p_error_code, u8 *p_control_state) 9219 { 9220 if (p_update_handle) 9221 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9222 if (p_error_code) 9223 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9224 if (p_control_state) 9225 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9226 } 9227 9228 /* MCDA - Management Component Data Access 9229 * --------------------------------------- 9230 * This register allows reading and writing a firmware component. 9231 */ 9232 #define MLXSW_REG_MCDA_ID 0x9063 9233 #define MLXSW_REG_MCDA_BASE_LEN 0x10 9234 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9235 #define MLXSW_REG_MCDA_LEN \ 9236 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9237 9238 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9239 9240 /* reg_mcda_update_handle 9241 * Token representing the current flow executed by the FSM. 9242 * Access: RW 9243 */ 9244 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9245 9246 /* reg_mcda_offset 9247 * Offset of accessed address relative to component start. Accesses must be in 9248 * accordance to log_mcda_word_size in MCQI reg. 9249 * Access: RW 9250 */ 9251 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9252 9253 /* reg_mcda_size 9254 * Size of the data accessed, given in bytes. 9255 * Access: RW 9256 */ 9257 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9258 9259 /* reg_mcda_data 9260 * Data block accessed. 9261 * Access: RW 9262 */ 9263 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9264 9265 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9266 u32 offset, u16 size, u8 *data) 9267 { 9268 int i; 9269 9270 MLXSW_REG_ZERO(mcda, payload); 9271 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9272 mlxsw_reg_mcda_offset_set(payload, offset); 9273 mlxsw_reg_mcda_size_set(payload, size); 9274 9275 for (i = 0; i < size / 4; i++) 9276 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9277 } 9278 9279 /* MPSC - Monitoring Packet Sampling Configuration Register 9280 * -------------------------------------------------------- 9281 * MPSC Register is used to configure the Packet Sampling mechanism. 9282 */ 9283 #define MLXSW_REG_MPSC_ID 0x9080 9284 #define MLXSW_REG_MPSC_LEN 0x1C 9285 9286 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9287 9288 /* reg_mpsc_local_port 9289 * Local port number 9290 * Not supported for CPU port 9291 * Access: Index 9292 */ 9293 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9294 9295 /* reg_mpsc_e 9296 * Enable sampling on port local_port 9297 * Access: RW 9298 */ 9299 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9300 9301 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9302 9303 /* reg_mpsc_rate 9304 * Sampling rate = 1 out of rate packets (with randomization around 9305 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9306 * Access: RW 9307 */ 9308 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9309 9310 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9311 u32 rate) 9312 { 9313 MLXSW_REG_ZERO(mpsc, payload); 9314 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9315 mlxsw_reg_mpsc_e_set(payload, e); 9316 mlxsw_reg_mpsc_rate_set(payload, rate); 9317 } 9318 9319 /* MGPC - Monitoring General Purpose Counter Set Register 9320 * The MGPC register retrieves and sets the General Purpose Counter Set. 9321 */ 9322 #define MLXSW_REG_MGPC_ID 0x9081 9323 #define MLXSW_REG_MGPC_LEN 0x18 9324 9325 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9326 9327 /* reg_mgpc_counter_set_type 9328 * Counter set type. 9329 * Access: OP 9330 */ 9331 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9332 9333 /* reg_mgpc_counter_index 9334 * Counter index. 9335 * Access: Index 9336 */ 9337 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9338 9339 enum mlxsw_reg_mgpc_opcode { 9340 /* Nop */ 9341 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9342 /* Clear counters */ 9343 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9344 }; 9345 9346 /* reg_mgpc_opcode 9347 * Opcode. 9348 * Access: OP 9349 */ 9350 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9351 9352 /* reg_mgpc_byte_counter 9353 * Byte counter value. 9354 * Access: RW 9355 */ 9356 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9357 9358 /* reg_mgpc_packet_counter 9359 * Packet counter value. 9360 * Access: RW 9361 */ 9362 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9363 9364 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9365 enum mlxsw_reg_mgpc_opcode opcode, 9366 enum mlxsw_reg_flow_counter_set_type set_type) 9367 { 9368 MLXSW_REG_ZERO(mgpc, payload); 9369 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9370 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9371 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9372 } 9373 9374 /* MPRS - Monitoring Parsing State Register 9375 * ---------------------------------------- 9376 * The MPRS register is used for setting up the parsing for hash, 9377 * policy-engine and routing. 9378 */ 9379 #define MLXSW_REG_MPRS_ID 0x9083 9380 #define MLXSW_REG_MPRS_LEN 0x14 9381 9382 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9383 9384 /* reg_mprs_parsing_depth 9385 * Minimum parsing depth. 9386 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9387 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9388 * Access: RW 9389 */ 9390 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9391 9392 /* reg_mprs_parsing_en 9393 * Parsing enable. 9394 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9395 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9396 * Access: RW 9397 */ 9398 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9399 9400 /* reg_mprs_vxlan_udp_dport 9401 * VxLAN UDP destination port. 9402 * Used for identifying VxLAN packets and for dport field in 9403 * encapsulation. Default is 4789. 9404 * Access: RW 9405 */ 9406 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9407 9408 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9409 u16 vxlan_udp_dport) 9410 { 9411 MLXSW_REG_ZERO(mprs, payload); 9412 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9413 mlxsw_reg_mprs_parsing_en_set(payload, true); 9414 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9415 } 9416 9417 /* MOGCR - Monitoring Global Configuration Register 9418 * ------------------------------------------------ 9419 */ 9420 #define MLXSW_REG_MOGCR_ID 0x9086 9421 #define MLXSW_REG_MOGCR_LEN 0x20 9422 9423 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9424 9425 /* reg_mogcr_ptp_iftc 9426 * PTP Ingress FIFO Trap Clear 9427 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9428 * to this value. Default 0. 9429 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9430 * Access: RW 9431 */ 9432 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9433 9434 /* reg_mogcr_ptp_eftc 9435 * PTP Egress FIFO Trap Clear 9436 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9437 * to this value. Default 0. 9438 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9439 * Access: RW 9440 */ 9441 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9442 9443 /* MTPPPC - Time Precision Packet Port Configuration 9444 * ------------------------------------------------- 9445 * This register serves for configuration of which PTP messages should be 9446 * timestamped. This is a global configuration, despite the register name. 9447 * 9448 * Reserved when Spectrum-2. 9449 */ 9450 #define MLXSW_REG_MTPPPC_ID 0x9090 9451 #define MLXSW_REG_MTPPPC_LEN 0x28 9452 9453 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 9454 9455 /* reg_mtpppc_ing_timestamp_message_type 9456 * Bitwise vector of PTP message types to timestamp at ingress. 9457 * MessageType field as defined by IEEE 1588 9458 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9459 * Default all 0 9460 * Access: RW 9461 */ 9462 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 9463 9464 /* reg_mtpppc_egr_timestamp_message_type 9465 * Bitwise vector of PTP message types to timestamp at egress. 9466 * MessageType field as defined by IEEE 1588 9467 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9468 * Default all 0 9469 * Access: RW 9470 */ 9471 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 9472 9473 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 9474 { 9475 MLXSW_REG_ZERO(mtpppc, payload); 9476 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 9477 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 9478 } 9479 9480 /* MTPPTR - Time Precision Packet Timestamping Reading 9481 * --------------------------------------------------- 9482 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 9483 * There is a trap for packets which are latched to the timestamp FIFO, thus the 9484 * SW knows which FIFO to read. Note that packets enter the FIFO before been 9485 * trapped. The sequence number is used to synchronize the timestamp FIFO 9486 * entries and the trapped packets. 9487 * Reserved when Spectrum-2. 9488 */ 9489 9490 #define MLXSW_REG_MTPPTR_ID 0x9091 9491 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 9492 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 9493 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 9494 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 9495 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 9496 9497 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 9498 9499 /* reg_mtpptr_local_port 9500 * Not supported for CPU port. 9501 * Access: Index 9502 */ 9503 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 9504 9505 enum mlxsw_reg_mtpptr_dir { 9506 MLXSW_REG_MTPPTR_DIR_INGRESS, 9507 MLXSW_REG_MTPPTR_DIR_EGRESS, 9508 }; 9509 9510 /* reg_mtpptr_dir 9511 * Direction. 9512 * Access: Index 9513 */ 9514 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 9515 9516 /* reg_mtpptr_clr 9517 * Clear the records. 9518 * Access: OP 9519 */ 9520 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 9521 9522 /* reg_mtpptr_num_rec 9523 * Number of valid records in the response 9524 * Range 0.. cap_ptp_timestamp_fifo 9525 * Access: RO 9526 */ 9527 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 9528 9529 /* reg_mtpptr_rec_message_type 9530 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 9531 * (e.g. Bit0: Sync, Bit1: Delay_Req) 9532 * Access: RO 9533 */ 9534 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 9535 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 9536 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9537 9538 /* reg_mtpptr_rec_domain_number 9539 * DomainNumber field as defined by IEEE 1588 9540 * Access: RO 9541 */ 9542 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 9543 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 9544 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9545 9546 /* reg_mtpptr_rec_sequence_id 9547 * SequenceId field as defined by IEEE 1588 9548 * Access: RO 9549 */ 9550 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 9551 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 9552 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 9553 9554 /* reg_mtpptr_rec_timestamp_high 9555 * Timestamp of when the PTP packet has passed through the port Units of PLL 9556 * clock time. 9557 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 9558 * Access: RO 9559 */ 9560 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 9561 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9562 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 9563 9564 /* reg_mtpptr_rec_timestamp_low 9565 * See rec_timestamp_high. 9566 * Access: RO 9567 */ 9568 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 9569 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9570 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 9571 9572 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 9573 unsigned int rec, 9574 u8 *p_message_type, 9575 u8 *p_domain_number, 9576 u16 *p_sequence_id, 9577 u64 *p_timestamp) 9578 { 9579 u32 timestamp_high, timestamp_low; 9580 9581 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 9582 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 9583 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 9584 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 9585 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 9586 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 9587 } 9588 9589 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 9590 * --------------------------------------------------------- 9591 * This register is used for configuring under which trap to deliver PTP 9592 * packets depending on type of the packet. 9593 */ 9594 #define MLXSW_REG_MTPTPT_ID 0x9092 9595 #define MLXSW_REG_MTPTPT_LEN 0x08 9596 9597 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 9598 9599 enum mlxsw_reg_mtptpt_trap_id { 9600 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 9601 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 9602 }; 9603 9604 /* reg_mtptpt_trap_id 9605 * Trap id. 9606 * Access: Index 9607 */ 9608 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 9609 9610 /* reg_mtptpt_message_type 9611 * Bitwise vector of PTP message types to trap. This is a necessary but 9612 * non-sufficient condition since need to enable also per port. See MTPPPC. 9613 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 9614 * Bit0: Sync, Bit1: Delay_Req) 9615 */ 9616 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 9617 9618 static inline void mlxsw_reg_mtptptp_pack(char *payload, 9619 enum mlxsw_reg_mtptpt_trap_id trap_id, 9620 u16 message_type) 9621 { 9622 MLXSW_REG_ZERO(mtptpt, payload); 9623 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 9624 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 9625 } 9626 9627 /* MGPIR - Management General Peripheral Information Register 9628 * ---------------------------------------------------------- 9629 * MGPIR register allows software to query the hardware and 9630 * firmware general information of peripheral entities. 9631 */ 9632 #define MLXSW_REG_MGPIR_ID 0x9100 9633 #define MLXSW_REG_MGPIR_LEN 0xA0 9634 9635 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 9636 9637 enum mlxsw_reg_mgpir_device_type { 9638 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 9639 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 9640 }; 9641 9642 /* device_type 9643 * Access: RO 9644 */ 9645 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 9646 9647 /* devices_per_flash 9648 * Number of devices of device_type per flash (can be shared by few devices). 9649 * Access: RO 9650 */ 9651 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 9652 9653 /* num_of_devices 9654 * Number of devices of device_type. 9655 * Access: RO 9656 */ 9657 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 9658 9659 /* num_of_modules 9660 * Number of modules. 9661 * Access: RO 9662 */ 9663 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 9664 9665 static inline void mlxsw_reg_mgpir_pack(char *payload) 9666 { 9667 MLXSW_REG_ZERO(mgpir, payload); 9668 } 9669 9670 static inline void 9671 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 9672 enum mlxsw_reg_mgpir_device_type *device_type, 9673 u8 *devices_per_flash, u8 *num_of_modules) 9674 { 9675 if (num_of_devices) 9676 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 9677 if (device_type) 9678 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 9679 if (devices_per_flash) 9680 *devices_per_flash = 9681 mlxsw_reg_mgpir_devices_per_flash_get(payload); 9682 if (num_of_modules) 9683 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 9684 } 9685 9686 /* TNGCR - Tunneling NVE General Configuration Register 9687 * ---------------------------------------------------- 9688 * The TNGCR register is used for setting up the NVE Tunneling configuration. 9689 */ 9690 #define MLXSW_REG_TNGCR_ID 0xA001 9691 #define MLXSW_REG_TNGCR_LEN 0x44 9692 9693 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 9694 9695 enum mlxsw_reg_tngcr_type { 9696 MLXSW_REG_TNGCR_TYPE_VXLAN, 9697 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 9698 MLXSW_REG_TNGCR_TYPE_GENEVE, 9699 MLXSW_REG_TNGCR_TYPE_NVGRE, 9700 }; 9701 9702 /* reg_tngcr_type 9703 * Tunnel type for encapsulation and decapsulation. The types are mutually 9704 * exclusive. 9705 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 9706 * Access: RW 9707 */ 9708 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 9709 9710 /* reg_tngcr_nve_valid 9711 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 9712 * Access: RW 9713 */ 9714 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 9715 9716 /* reg_tngcr_nve_ttl_uc 9717 * The TTL for NVE tunnel encapsulation underlay unicast packets. 9718 * Access: RW 9719 */ 9720 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 9721 9722 /* reg_tngcr_nve_ttl_mc 9723 * The TTL for NVE tunnel encapsulation underlay multicast packets. 9724 * Access: RW 9725 */ 9726 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 9727 9728 enum { 9729 /* Do not copy flow label. Calculate flow label using nve_flh. */ 9730 MLXSW_REG_TNGCR_FL_NO_COPY, 9731 /* Copy flow label from inner packet if packet is IPv6 and 9732 * encapsulation is by IPv6. Otherwise, calculate flow label using 9733 * nve_flh. 9734 */ 9735 MLXSW_REG_TNGCR_FL_COPY, 9736 }; 9737 9738 /* reg_tngcr_nve_flc 9739 * For NVE tunnel encapsulation: Flow label copy from inner packet. 9740 * Access: RW 9741 */ 9742 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 9743 9744 enum { 9745 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 9746 * uses {nve_fl_prefix, nve_fl_suffix}. 9747 */ 9748 MLXSW_REG_TNGCR_FL_NO_HASH, 9749 /* 8 LSBs of the flow label are calculated from ECMP hash of the 9750 * inner packet. 12 MSBs are configured by nve_fl_prefix. 9751 */ 9752 MLXSW_REG_TNGCR_FL_HASH, 9753 }; 9754 9755 /* reg_tngcr_nve_flh 9756 * NVE flow label hash. 9757 * Access: RW 9758 */ 9759 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 9760 9761 /* reg_tngcr_nve_fl_prefix 9762 * NVE flow label prefix. Constant 12 MSBs of the flow label. 9763 * Access: RW 9764 */ 9765 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 9766 9767 /* reg_tngcr_nve_fl_suffix 9768 * NVE flow label suffix. Constant 8 LSBs of the flow label. 9769 * Reserved when nve_flh=1 and for Spectrum. 9770 * Access: RW 9771 */ 9772 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 9773 9774 enum { 9775 /* Source UDP port is fixed (default '0') */ 9776 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 9777 /* Source UDP port is calculated based on hash */ 9778 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 9779 }; 9780 9781 /* reg_tngcr_nve_udp_sport_type 9782 * NVE UDP source port type. 9783 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 9784 * When the source UDP port is calculated based on hash, then the 8 LSBs 9785 * are calculated from hash the 8 MSBs are configured by 9786 * nve_udp_sport_prefix. 9787 * Access: RW 9788 */ 9789 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 9790 9791 /* reg_tngcr_nve_udp_sport_prefix 9792 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 9793 * Reserved when NVE type is NVGRE. 9794 * Access: RW 9795 */ 9796 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 9797 9798 /* reg_tngcr_nve_group_size_mc 9799 * The amount of sequential linked lists of MC entries. The first linked 9800 * list is configured by SFD.underlay_mc_ptr. 9801 * Valid values: 1, 2, 4, 8, 16, 32, 64 9802 * The linked list are configured by TNUMT. 9803 * The hash is set by LAG hash. 9804 * Access: RW 9805 */ 9806 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 9807 9808 /* reg_tngcr_nve_group_size_flood 9809 * The amount of sequential linked lists of flooding entries. The first 9810 * linked list is configured by SFMR.nve_tunnel_flood_ptr 9811 * Valid values: 1, 2, 4, 8, 16, 32, 64 9812 * The linked list are configured by TNUMT. 9813 * The hash is set by LAG hash. 9814 * Access: RW 9815 */ 9816 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 9817 9818 /* reg_tngcr_learn_enable 9819 * During decapsulation, whether to learn from NVE port. 9820 * Reserved when Spectrum-2. See TNPC. 9821 * Access: RW 9822 */ 9823 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 9824 9825 /* reg_tngcr_underlay_virtual_router 9826 * Underlay virtual router. 9827 * Reserved when Spectrum-2. 9828 * Access: RW 9829 */ 9830 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 9831 9832 /* reg_tngcr_underlay_rif 9833 * Underlay ingress router interface. RIF type should be loopback generic. 9834 * Reserved when Spectrum. 9835 * Access: RW 9836 */ 9837 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 9838 9839 /* reg_tngcr_usipv4 9840 * Underlay source IPv4 address of the NVE. 9841 * Access: RW 9842 */ 9843 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 9844 9845 /* reg_tngcr_usipv6 9846 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 9847 * modified under traffic of NVE tunneling encapsulation. 9848 * Access: RW 9849 */ 9850 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 9851 9852 static inline void mlxsw_reg_tngcr_pack(char *payload, 9853 enum mlxsw_reg_tngcr_type type, 9854 bool valid, u8 ttl) 9855 { 9856 MLXSW_REG_ZERO(tngcr, payload); 9857 mlxsw_reg_tngcr_type_set(payload, type); 9858 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 9859 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 9860 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 9861 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 9862 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 9863 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 9864 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 9865 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 9866 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 9867 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 9868 } 9869 9870 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 9871 * ------------------------------------------------------- 9872 * The TNUMT register is for building the underlay MC table. It is used 9873 * for MC, flooding and BC traffic into the NVE tunnel. 9874 */ 9875 #define MLXSW_REG_TNUMT_ID 0xA003 9876 #define MLXSW_REG_TNUMT_LEN 0x20 9877 9878 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 9879 9880 enum mlxsw_reg_tnumt_record_type { 9881 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 9882 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 9883 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 9884 }; 9885 9886 /* reg_tnumt_record_type 9887 * Record type. 9888 * Access: RW 9889 */ 9890 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 9891 9892 enum mlxsw_reg_tnumt_tunnel_port { 9893 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 9894 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 9895 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 9896 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 9897 }; 9898 9899 /* reg_tnumt_tunnel_port 9900 * Tunnel port. 9901 * Access: RW 9902 */ 9903 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 9904 9905 /* reg_tnumt_underlay_mc_ptr 9906 * Index to the underlay multicast table. 9907 * For Spectrum the index is to the KVD linear. 9908 * Access: Index 9909 */ 9910 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 9911 9912 /* reg_tnumt_vnext 9913 * The next_underlay_mc_ptr is valid. 9914 * Access: RW 9915 */ 9916 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 9917 9918 /* reg_tnumt_next_underlay_mc_ptr 9919 * The next index to the underlay multicast table. 9920 * Access: RW 9921 */ 9922 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 9923 9924 /* reg_tnumt_record_size 9925 * Number of IP addresses in the record. 9926 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 9927 * Access: RW 9928 */ 9929 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 9930 9931 /* reg_tnumt_udip 9932 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 9933 * Access: RW 9934 */ 9935 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 9936 9937 /* reg_tnumt_udip_ptr 9938 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 9939 * i >= size. The IPv6 addresses are configured by RIPS. 9940 * Access: RW 9941 */ 9942 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 9943 9944 static inline void mlxsw_reg_tnumt_pack(char *payload, 9945 enum mlxsw_reg_tnumt_record_type type, 9946 enum mlxsw_reg_tnumt_tunnel_port tport, 9947 u32 underlay_mc_ptr, bool vnext, 9948 u32 next_underlay_mc_ptr, 9949 u8 record_size) 9950 { 9951 MLXSW_REG_ZERO(tnumt, payload); 9952 mlxsw_reg_tnumt_record_type_set(payload, type); 9953 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 9954 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 9955 mlxsw_reg_tnumt_vnext_set(payload, vnext); 9956 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 9957 mlxsw_reg_tnumt_record_size_set(payload, record_size); 9958 } 9959 9960 /* TNQCR - Tunneling NVE QoS Configuration Register 9961 * ------------------------------------------------ 9962 * The TNQCR register configures how QoS is set in encapsulation into the 9963 * underlay network. 9964 */ 9965 #define MLXSW_REG_TNQCR_ID 0xA010 9966 #define MLXSW_REG_TNQCR_LEN 0x0C 9967 9968 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 9969 9970 /* reg_tnqcr_enc_set_dscp 9971 * For encapsulation: How to set DSCP field: 9972 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 9973 * (outer) IP header. If there is no IP header, use TNQDR.dscp 9974 * 1 - Set the DSCP field as TNQDR.dscp 9975 * Access: RW 9976 */ 9977 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 9978 9979 static inline void mlxsw_reg_tnqcr_pack(char *payload) 9980 { 9981 MLXSW_REG_ZERO(tnqcr, payload); 9982 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 9983 } 9984 9985 /* TNQDR - Tunneling NVE QoS Default Register 9986 * ------------------------------------------ 9987 * The TNQDR register configures the default QoS settings for NVE 9988 * encapsulation. 9989 */ 9990 #define MLXSW_REG_TNQDR_ID 0xA011 9991 #define MLXSW_REG_TNQDR_LEN 0x08 9992 9993 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 9994 9995 /* reg_tnqdr_local_port 9996 * Local port number (receive port). CPU port is supported. 9997 * Access: Index 9998 */ 9999 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 10000 10001 /* reg_tnqdr_dscp 10002 * For encapsulation, the default DSCP. 10003 * Access: RW 10004 */ 10005 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 10006 10007 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 10008 { 10009 MLXSW_REG_ZERO(tnqdr, payload); 10010 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 10011 mlxsw_reg_tnqdr_dscp_set(payload, 0); 10012 } 10013 10014 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 10015 * -------------------------------------------------------- 10016 * The TNEEM register maps ECN of the IP header at the ingress to the 10017 * encapsulation to the ECN of the underlay network. 10018 */ 10019 #define MLXSW_REG_TNEEM_ID 0xA012 10020 #define MLXSW_REG_TNEEM_LEN 0x0C 10021 10022 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 10023 10024 /* reg_tneem_overlay_ecn 10025 * ECN of the IP header in the overlay network. 10026 * Access: Index 10027 */ 10028 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 10029 10030 /* reg_tneem_underlay_ecn 10031 * ECN of the IP header in the underlay network. 10032 * Access: RW 10033 */ 10034 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 10035 10036 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 10037 u8 underlay_ecn) 10038 { 10039 MLXSW_REG_ZERO(tneem, payload); 10040 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 10041 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 10042 } 10043 10044 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 10045 * -------------------------------------------------------- 10046 * The TNDEM register configures the actions that are done in the 10047 * decapsulation. 10048 */ 10049 #define MLXSW_REG_TNDEM_ID 0xA013 10050 #define MLXSW_REG_TNDEM_LEN 0x0C 10051 10052 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 10053 10054 /* reg_tndem_underlay_ecn 10055 * ECN field of the IP header in the underlay network. 10056 * Access: Index 10057 */ 10058 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 10059 10060 /* reg_tndem_overlay_ecn 10061 * ECN field of the IP header in the overlay network. 10062 * Access: Index 10063 */ 10064 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10065 10066 /* reg_tndem_eip_ecn 10067 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10068 * from the decapsulation. 10069 * Access: RW 10070 */ 10071 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10072 10073 /* reg_tndem_trap_en 10074 * Trap enable: 10075 * 0 - No trap due to decap ECN 10076 * 1 - Trap enable with trap_id 10077 * Access: RW 10078 */ 10079 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10080 10081 /* reg_tndem_trap_id 10082 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10083 * Reserved when trap_en is '0'. 10084 * Access: RW 10085 */ 10086 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10087 10088 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10089 u8 overlay_ecn, u8 ecn, bool trap_en, 10090 u16 trap_id) 10091 { 10092 MLXSW_REG_ZERO(tndem, payload); 10093 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10094 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10095 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10096 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10097 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10098 } 10099 10100 /* TNPC - Tunnel Port Configuration Register 10101 * ----------------------------------------- 10102 * The TNPC register is used for tunnel port configuration. 10103 * Reserved when Spectrum. 10104 */ 10105 #define MLXSW_REG_TNPC_ID 0xA020 10106 #define MLXSW_REG_TNPC_LEN 0x18 10107 10108 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10109 10110 enum mlxsw_reg_tnpc_tunnel_port { 10111 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 10112 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 10113 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 10114 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 10115 }; 10116 10117 /* reg_tnpc_tunnel_port 10118 * Tunnel port. 10119 * Access: Index 10120 */ 10121 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10122 10123 /* reg_tnpc_learn_enable_v6 10124 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10125 * Access: RW 10126 */ 10127 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10128 10129 /* reg_tnpc_learn_enable_v4 10130 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10131 * Access: RW 10132 */ 10133 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10134 10135 static inline void mlxsw_reg_tnpc_pack(char *payload, 10136 enum mlxsw_reg_tnpc_tunnel_port tport, 10137 bool learn_enable) 10138 { 10139 MLXSW_REG_ZERO(tnpc, payload); 10140 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10141 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10142 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10143 } 10144 10145 /* TIGCR - Tunneling IPinIP General Configuration Register 10146 * ------------------------------------------------------- 10147 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10148 */ 10149 #define MLXSW_REG_TIGCR_ID 0xA801 10150 #define MLXSW_REG_TIGCR_LEN 0x10 10151 10152 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10153 10154 /* reg_tigcr_ipip_ttlc 10155 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10156 * header. 10157 * Access: RW 10158 */ 10159 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10160 10161 /* reg_tigcr_ipip_ttl_uc 10162 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10163 * reg_tigcr_ipip_ttlc is unset. 10164 * Access: RW 10165 */ 10166 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10167 10168 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10169 { 10170 MLXSW_REG_ZERO(tigcr, payload); 10171 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10172 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10173 } 10174 10175 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 10176 * ----------------------------------------------------------- 10177 * The TIEEM register maps ECN of the IP header at the ingress to the 10178 * encapsulation to the ECN of the underlay network. 10179 */ 10180 #define MLXSW_REG_TIEEM_ID 0xA812 10181 #define MLXSW_REG_TIEEM_LEN 0x0C 10182 10183 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 10184 10185 /* reg_tieem_overlay_ecn 10186 * ECN of the IP header in the overlay network. 10187 * Access: Index 10188 */ 10189 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 10190 10191 /* reg_tineem_underlay_ecn 10192 * ECN of the IP header in the underlay network. 10193 * Access: RW 10194 */ 10195 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 10196 10197 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 10198 u8 underlay_ecn) 10199 { 10200 MLXSW_REG_ZERO(tieem, payload); 10201 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 10202 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 10203 } 10204 10205 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 10206 * ----------------------------------------------------------- 10207 * The TIDEM register configures the actions that are done in the 10208 * decapsulation. 10209 */ 10210 #define MLXSW_REG_TIDEM_ID 0xA813 10211 #define MLXSW_REG_TIDEM_LEN 0x0C 10212 10213 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 10214 10215 /* reg_tidem_underlay_ecn 10216 * ECN field of the IP header in the underlay network. 10217 * Access: Index 10218 */ 10219 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 10220 10221 /* reg_tidem_overlay_ecn 10222 * ECN field of the IP header in the overlay network. 10223 * Access: Index 10224 */ 10225 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 10226 10227 /* reg_tidem_eip_ecn 10228 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10229 * from the decapsulation. 10230 * Access: RW 10231 */ 10232 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 10233 10234 /* reg_tidem_trap_en 10235 * Trap enable: 10236 * 0 - No trap due to decap ECN 10237 * 1 - Trap enable with trap_id 10238 * Access: RW 10239 */ 10240 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 10241 10242 /* reg_tidem_trap_id 10243 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10244 * Reserved when trap_en is '0'. 10245 * Access: RW 10246 */ 10247 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 10248 10249 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 10250 u8 overlay_ecn, u8 eip_ecn, 10251 bool trap_en, u16 trap_id) 10252 { 10253 MLXSW_REG_ZERO(tidem, payload); 10254 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 10255 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 10256 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 10257 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 10258 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 10259 } 10260 10261 /* SBPR - Shared Buffer Pools Register 10262 * ----------------------------------- 10263 * The SBPR configures and retrieves the shared buffer pools and configuration. 10264 */ 10265 #define MLXSW_REG_SBPR_ID 0xB001 10266 #define MLXSW_REG_SBPR_LEN 0x14 10267 10268 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10269 10270 /* shared direstion enum for SBPR, SBCM, SBPM */ 10271 enum mlxsw_reg_sbxx_dir { 10272 MLXSW_REG_SBXX_DIR_INGRESS, 10273 MLXSW_REG_SBXX_DIR_EGRESS, 10274 }; 10275 10276 /* reg_sbpr_dir 10277 * Direction. 10278 * Access: Index 10279 */ 10280 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10281 10282 /* reg_sbpr_pool 10283 * Pool index. 10284 * Access: Index 10285 */ 10286 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 10287 10288 /* reg_sbpr_infi_size 10289 * Size is infinite. 10290 * Access: RW 10291 */ 10292 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 10293 10294 /* reg_sbpr_size 10295 * Pool size in buffer cells. 10296 * Reserved when infi_size = 1. 10297 * Access: RW 10298 */ 10299 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 10300 10301 enum mlxsw_reg_sbpr_mode { 10302 MLXSW_REG_SBPR_MODE_STATIC, 10303 MLXSW_REG_SBPR_MODE_DYNAMIC, 10304 }; 10305 10306 /* reg_sbpr_mode 10307 * Pool quota calculation mode. 10308 * Access: RW 10309 */ 10310 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 10311 10312 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 10313 enum mlxsw_reg_sbxx_dir dir, 10314 enum mlxsw_reg_sbpr_mode mode, u32 size, 10315 bool infi_size) 10316 { 10317 MLXSW_REG_ZERO(sbpr, payload); 10318 mlxsw_reg_sbpr_pool_set(payload, pool); 10319 mlxsw_reg_sbpr_dir_set(payload, dir); 10320 mlxsw_reg_sbpr_mode_set(payload, mode); 10321 mlxsw_reg_sbpr_size_set(payload, size); 10322 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 10323 } 10324 10325 /* SBCM - Shared Buffer Class Management Register 10326 * ---------------------------------------------- 10327 * The SBCM register configures and retrieves the shared buffer allocation 10328 * and configuration according to Port-PG, including the binding to pool 10329 * and definition of the associated quota. 10330 */ 10331 #define MLXSW_REG_SBCM_ID 0xB002 10332 #define MLXSW_REG_SBCM_LEN 0x28 10333 10334 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 10335 10336 /* reg_sbcm_local_port 10337 * Local port number. 10338 * For Ingress: excludes CPU port and Router port 10339 * For Egress: excludes IP Router 10340 * Access: Index 10341 */ 10342 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 10343 10344 /* reg_sbcm_pg_buff 10345 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 10346 * For PG buffer: range is 0..cap_max_pg_buffers - 1 10347 * For traffic class: range is 0..cap_max_tclass - 1 10348 * Note that when traffic class is in MC aware mode then the traffic 10349 * classes which are MC aware cannot be configured. 10350 * Access: Index 10351 */ 10352 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 10353 10354 /* reg_sbcm_dir 10355 * Direction. 10356 * Access: Index 10357 */ 10358 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 10359 10360 /* reg_sbcm_min_buff 10361 * Minimum buffer size for the limiter, in cells. 10362 * Access: RW 10363 */ 10364 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 10365 10366 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 10367 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 10368 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 10369 10370 /* reg_sbcm_infi_max 10371 * Max buffer is infinite. 10372 * Access: RW 10373 */ 10374 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 10375 10376 /* reg_sbcm_max_buff 10377 * When the pool associated to the port-pg/tclass is configured to 10378 * static, Maximum buffer size for the limiter configured in cells. 10379 * When the pool associated to the port-pg/tclass is configured to 10380 * dynamic, the max_buff holds the "alpha" parameter, supporting 10381 * the following values: 10382 * 0: 0 10383 * i: (1/128)*2^(i-1), for i=1..14 10384 * 0xFF: Infinity 10385 * Reserved when infi_max = 1. 10386 * Access: RW 10387 */ 10388 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 10389 10390 /* reg_sbcm_pool 10391 * Association of the port-priority to a pool. 10392 * Access: RW 10393 */ 10394 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 10395 10396 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 10397 enum mlxsw_reg_sbxx_dir dir, 10398 u32 min_buff, u32 max_buff, 10399 bool infi_max, u8 pool) 10400 { 10401 MLXSW_REG_ZERO(sbcm, payload); 10402 mlxsw_reg_sbcm_local_port_set(payload, local_port); 10403 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 10404 mlxsw_reg_sbcm_dir_set(payload, dir); 10405 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 10406 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 10407 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 10408 mlxsw_reg_sbcm_pool_set(payload, pool); 10409 } 10410 10411 /* SBPM - Shared Buffer Port Management Register 10412 * --------------------------------------------- 10413 * The SBPM register configures and retrieves the shared buffer allocation 10414 * and configuration according to Port-Pool, including the definition 10415 * of the associated quota. 10416 */ 10417 #define MLXSW_REG_SBPM_ID 0xB003 10418 #define MLXSW_REG_SBPM_LEN 0x28 10419 10420 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 10421 10422 /* reg_sbpm_local_port 10423 * Local port number. 10424 * For Ingress: excludes CPU port and Router port 10425 * For Egress: excludes IP Router 10426 * Access: Index 10427 */ 10428 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 10429 10430 /* reg_sbpm_pool 10431 * The pool associated to quota counting on the local_port. 10432 * Access: Index 10433 */ 10434 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 10435 10436 /* reg_sbpm_dir 10437 * Direction. 10438 * Access: Index 10439 */ 10440 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 10441 10442 /* reg_sbpm_buff_occupancy 10443 * Current buffer occupancy in cells. 10444 * Access: RO 10445 */ 10446 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 10447 10448 /* reg_sbpm_clr 10449 * Clear Max Buffer Occupancy 10450 * When this bit is set, max_buff_occupancy field is cleared (and a 10451 * new max value is tracked from the time the clear was performed). 10452 * Access: OP 10453 */ 10454 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 10455 10456 /* reg_sbpm_max_buff_occupancy 10457 * Maximum value of buffer occupancy in cells monitored. Cleared by 10458 * writing to the clr field. 10459 * Access: RO 10460 */ 10461 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 10462 10463 /* reg_sbpm_min_buff 10464 * Minimum buffer size for the limiter, in cells. 10465 * Access: RW 10466 */ 10467 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 10468 10469 /* reg_sbpm_max_buff 10470 * When the pool associated to the port-pg/tclass is configured to 10471 * static, Maximum buffer size for the limiter configured in cells. 10472 * When the pool associated to the port-pg/tclass is configured to 10473 * dynamic, the max_buff holds the "alpha" parameter, supporting 10474 * the following values: 10475 * 0: 0 10476 * i: (1/128)*2^(i-1), for i=1..14 10477 * 0xFF: Infinity 10478 * Access: RW 10479 */ 10480 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 10481 10482 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 10483 enum mlxsw_reg_sbxx_dir dir, bool clr, 10484 u32 min_buff, u32 max_buff) 10485 { 10486 MLXSW_REG_ZERO(sbpm, payload); 10487 mlxsw_reg_sbpm_local_port_set(payload, local_port); 10488 mlxsw_reg_sbpm_pool_set(payload, pool); 10489 mlxsw_reg_sbpm_dir_set(payload, dir); 10490 mlxsw_reg_sbpm_clr_set(payload, clr); 10491 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 10492 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 10493 } 10494 10495 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 10496 u32 *p_max_buff_occupancy) 10497 { 10498 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 10499 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 10500 } 10501 10502 /* SBMM - Shared Buffer Multicast Management Register 10503 * -------------------------------------------------- 10504 * The SBMM register configures and retrieves the shared buffer allocation 10505 * and configuration for MC packets according to Switch-Priority, including 10506 * the binding to pool and definition of the associated quota. 10507 */ 10508 #define MLXSW_REG_SBMM_ID 0xB004 10509 #define MLXSW_REG_SBMM_LEN 0x28 10510 10511 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 10512 10513 /* reg_sbmm_prio 10514 * Switch Priority. 10515 * Access: Index 10516 */ 10517 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 10518 10519 /* reg_sbmm_min_buff 10520 * Minimum buffer size for the limiter, in cells. 10521 * Access: RW 10522 */ 10523 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 10524 10525 /* reg_sbmm_max_buff 10526 * When the pool associated to the port-pg/tclass is configured to 10527 * static, Maximum buffer size for the limiter configured in cells. 10528 * When the pool associated to the port-pg/tclass is configured to 10529 * dynamic, the max_buff holds the "alpha" parameter, supporting 10530 * the following values: 10531 * 0: 0 10532 * i: (1/128)*2^(i-1), for i=1..14 10533 * 0xFF: Infinity 10534 * Access: RW 10535 */ 10536 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 10537 10538 /* reg_sbmm_pool 10539 * Association of the port-priority to a pool. 10540 * Access: RW 10541 */ 10542 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 10543 10544 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 10545 u32 max_buff, u8 pool) 10546 { 10547 MLXSW_REG_ZERO(sbmm, payload); 10548 mlxsw_reg_sbmm_prio_set(payload, prio); 10549 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 10550 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 10551 mlxsw_reg_sbmm_pool_set(payload, pool); 10552 } 10553 10554 /* SBSR - Shared Buffer Status Register 10555 * ------------------------------------ 10556 * The SBSR register retrieves the shared buffer occupancy according to 10557 * Port-Pool. Note that this register enables reading a large amount of data. 10558 * It is the user's responsibility to limit the amount of data to ensure the 10559 * response can match the maximum transfer unit. In case the response exceeds 10560 * the maximum transport unit, it will be truncated with no special notice. 10561 */ 10562 #define MLXSW_REG_SBSR_ID 0xB005 10563 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 10564 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 10565 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 10566 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 10567 MLXSW_REG_SBSR_REC_LEN * \ 10568 MLXSW_REG_SBSR_REC_MAX_COUNT) 10569 10570 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 10571 10572 /* reg_sbsr_clr 10573 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 10574 * field is cleared (and a new max value is tracked from the time the clear 10575 * was performed). 10576 * Access: OP 10577 */ 10578 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 10579 10580 /* reg_sbsr_ingress_port_mask 10581 * Bit vector for all ingress network ports. 10582 * Indicates which of the ports (for which the relevant bit is set) 10583 * are affected by the set operation. Configuration of any other port 10584 * does not change. 10585 * Access: Index 10586 */ 10587 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 10588 10589 /* reg_sbsr_pg_buff_mask 10590 * Bit vector for all switch priority groups. 10591 * Indicates which of the priorities (for which the relevant bit is set) 10592 * are affected by the set operation. Configuration of any other priority 10593 * does not change. 10594 * Range is 0..cap_max_pg_buffers - 1 10595 * Access: Index 10596 */ 10597 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 10598 10599 /* reg_sbsr_egress_port_mask 10600 * Bit vector for all egress network ports. 10601 * Indicates which of the ports (for which the relevant bit is set) 10602 * are affected by the set operation. Configuration of any other port 10603 * does not change. 10604 * Access: Index 10605 */ 10606 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 10607 10608 /* reg_sbsr_tclass_mask 10609 * Bit vector for all traffic classes. 10610 * Indicates which of the traffic classes (for which the relevant bit is 10611 * set) are affected by the set operation. Configuration of any other 10612 * traffic class does not change. 10613 * Range is 0..cap_max_tclass - 1 10614 * Access: Index 10615 */ 10616 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 10617 10618 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 10619 { 10620 MLXSW_REG_ZERO(sbsr, payload); 10621 mlxsw_reg_sbsr_clr_set(payload, clr); 10622 } 10623 10624 /* reg_sbsr_rec_buff_occupancy 10625 * Current buffer occupancy in cells. 10626 * Access: RO 10627 */ 10628 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10629 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 10630 10631 /* reg_sbsr_rec_max_buff_occupancy 10632 * Maximum value of buffer occupancy in cells monitored. Cleared by 10633 * writing to the clr field. 10634 * Access: RO 10635 */ 10636 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10637 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 10638 10639 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 10640 u32 *p_buff_occupancy, 10641 u32 *p_max_buff_occupancy) 10642 { 10643 *p_buff_occupancy = 10644 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 10645 *p_max_buff_occupancy = 10646 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 10647 } 10648 10649 /* SBIB - Shared Buffer Internal Buffer Register 10650 * --------------------------------------------- 10651 * The SBIB register configures per port buffers for internal use. The internal 10652 * buffers consume memory on the port buffers (note that the port buffers are 10653 * used also by PBMC). 10654 * 10655 * For Spectrum this is used for egress mirroring. 10656 */ 10657 #define MLXSW_REG_SBIB_ID 0xB006 10658 #define MLXSW_REG_SBIB_LEN 0x10 10659 10660 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 10661 10662 /* reg_sbib_local_port 10663 * Local port number 10664 * Not supported for CPU port and router port 10665 * Access: Index 10666 */ 10667 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 10668 10669 /* reg_sbib_buff_size 10670 * Units represented in cells 10671 * Allowed range is 0 to (cap_max_headroom_size - 1) 10672 * Default is 0 10673 * Access: RW 10674 */ 10675 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 10676 10677 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 10678 u32 buff_size) 10679 { 10680 MLXSW_REG_ZERO(sbib, payload); 10681 mlxsw_reg_sbib_local_port_set(payload, local_port); 10682 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 10683 } 10684 10685 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 10686 MLXSW_REG(sgcr), 10687 MLXSW_REG(spad), 10688 MLXSW_REG(smid), 10689 MLXSW_REG(sspr), 10690 MLXSW_REG(sfdat), 10691 MLXSW_REG(sfd), 10692 MLXSW_REG(sfn), 10693 MLXSW_REG(spms), 10694 MLXSW_REG(spvid), 10695 MLXSW_REG(spvm), 10696 MLXSW_REG(spaft), 10697 MLXSW_REG(sfgc), 10698 MLXSW_REG(sftr), 10699 MLXSW_REG(sfdf), 10700 MLXSW_REG(sldr), 10701 MLXSW_REG(slcr), 10702 MLXSW_REG(slcor), 10703 MLXSW_REG(spmlr), 10704 MLXSW_REG(svfa), 10705 MLXSW_REG(svpe), 10706 MLXSW_REG(sfmr), 10707 MLXSW_REG(spvmlr), 10708 MLXSW_REG(cwtp), 10709 MLXSW_REG(cwtpm), 10710 MLXSW_REG(pgcr), 10711 MLXSW_REG(ppbt), 10712 MLXSW_REG(pacl), 10713 MLXSW_REG(pagt), 10714 MLXSW_REG(ptar), 10715 MLXSW_REG(ppbs), 10716 MLXSW_REG(prcr), 10717 MLXSW_REG(pefa), 10718 MLXSW_REG(pemrbt), 10719 MLXSW_REG(ptce2), 10720 MLXSW_REG(perpt), 10721 MLXSW_REG(peabfe), 10722 MLXSW_REG(perar), 10723 MLXSW_REG(ptce3), 10724 MLXSW_REG(percr), 10725 MLXSW_REG(pererp), 10726 MLXSW_REG(iedr), 10727 MLXSW_REG(qpts), 10728 MLXSW_REG(qpcr), 10729 MLXSW_REG(qtct), 10730 MLXSW_REG(qeec), 10731 MLXSW_REG(qrwe), 10732 MLXSW_REG(qpdsm), 10733 MLXSW_REG(qpdp), 10734 MLXSW_REG(qpdpm), 10735 MLXSW_REG(qtctm), 10736 MLXSW_REG(qpsc), 10737 MLXSW_REG(pmlp), 10738 MLXSW_REG(pmtu), 10739 MLXSW_REG(ptys), 10740 MLXSW_REG(ppad), 10741 MLXSW_REG(paos), 10742 MLXSW_REG(pfcc), 10743 MLXSW_REG(ppcnt), 10744 MLXSW_REG(plib), 10745 MLXSW_REG(pptb), 10746 MLXSW_REG(pbmc), 10747 MLXSW_REG(pspa), 10748 MLXSW_REG(pplr), 10749 MLXSW_REG(pmtm), 10750 MLXSW_REG(htgt), 10751 MLXSW_REG(hpkt), 10752 MLXSW_REG(rgcr), 10753 MLXSW_REG(ritr), 10754 MLXSW_REG(rtar), 10755 MLXSW_REG(ratr), 10756 MLXSW_REG(rtdp), 10757 MLXSW_REG(rdpm), 10758 MLXSW_REG(ricnt), 10759 MLXSW_REG(rrcr), 10760 MLXSW_REG(ralta), 10761 MLXSW_REG(ralst), 10762 MLXSW_REG(raltb), 10763 MLXSW_REG(ralue), 10764 MLXSW_REG(rauht), 10765 MLXSW_REG(raleu), 10766 MLXSW_REG(rauhtd), 10767 MLXSW_REG(rigr2), 10768 MLXSW_REG(recr2), 10769 MLXSW_REG(rmft2), 10770 MLXSW_REG(mfcr), 10771 MLXSW_REG(mfsc), 10772 MLXSW_REG(mfsm), 10773 MLXSW_REG(mfsl), 10774 MLXSW_REG(fore), 10775 MLXSW_REG(mtcap), 10776 MLXSW_REG(mtmp), 10777 MLXSW_REG(mtbr), 10778 MLXSW_REG(mcia), 10779 MLXSW_REG(mpat), 10780 MLXSW_REG(mpar), 10781 MLXSW_REG(mgir), 10782 MLXSW_REG(mrsr), 10783 MLXSW_REG(mlcr), 10784 MLXSW_REG(mtpps), 10785 MLXSW_REG(mtutc), 10786 MLXSW_REG(mpsc), 10787 MLXSW_REG(mcqi), 10788 MLXSW_REG(mcc), 10789 MLXSW_REG(mcda), 10790 MLXSW_REG(mgpc), 10791 MLXSW_REG(mprs), 10792 MLXSW_REG(mogcr), 10793 MLXSW_REG(mtpppc), 10794 MLXSW_REG(mtpptr), 10795 MLXSW_REG(mtptpt), 10796 MLXSW_REG(mgpir), 10797 MLXSW_REG(tngcr), 10798 MLXSW_REG(tnumt), 10799 MLXSW_REG(tnqcr), 10800 MLXSW_REG(tnqdr), 10801 MLXSW_REG(tneem), 10802 MLXSW_REG(tndem), 10803 MLXSW_REG(tnpc), 10804 MLXSW_REG(tigcr), 10805 MLXSW_REG(tieem), 10806 MLXSW_REG(tidem), 10807 MLXSW_REG(sbpr), 10808 MLXSW_REG(sbcm), 10809 MLXSW_REG(sbpm), 10810 MLXSW_REG(sbmm), 10811 MLXSW_REG(sbsr), 10812 MLXSW_REG(sbib), 10813 }; 10814 10815 static inline const char *mlxsw_reg_id_str(u16 reg_id) 10816 { 10817 const struct mlxsw_reg_info *reg_info; 10818 int i; 10819 10820 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 10821 reg_info = mlxsw_reg_infos[i]; 10822 if (reg_info->id == reg_id) 10823 return reg_info->name; 10824 } 10825 return "*UNKNOWN*"; 10826 } 10827 10828 /* PUDE - Port Up / Down Event 10829 * --------------------------- 10830 * Reports the operational state change of a port. 10831 */ 10832 #define MLXSW_REG_PUDE_LEN 0x10 10833 10834 /* reg_pude_swid 10835 * Switch partition ID with which to associate the port. 10836 * Access: Index 10837 */ 10838 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 10839 10840 /* reg_pude_local_port 10841 * Local port number. 10842 * Access: Index 10843 */ 10844 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 10845 10846 /* reg_pude_admin_status 10847 * Port administrative state (the desired state). 10848 * 1 - Up. 10849 * 2 - Down. 10850 * 3 - Up once. This means that in case of link failure, the port won't go 10851 * into polling mode, but will wait to be re-enabled by software. 10852 * 4 - Disabled by system. Can only be set by hardware. 10853 * Access: RO 10854 */ 10855 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 10856 10857 /* reg_pude_oper_status 10858 * Port operatioanl state. 10859 * 1 - Up. 10860 * 2 - Down. 10861 * 3 - Down by port failure. This means that the device will not let the 10862 * port up again until explicitly specified by software. 10863 * Access: RO 10864 */ 10865 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 10866 10867 #endif 10868