1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the names of the copyright holders nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") version 2 as published by the Free 22 * Software Foundation. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _MLXSW_REG_H 38 #define _MLXSW_REG_H 39 40 #include <linux/string.h> 41 #include <linux/bitops.h> 42 #include <linux/if_vlan.h> 43 44 #include "item.h" 45 #include "port.h" 46 47 struct mlxsw_reg_info { 48 u16 id; 49 u16 len; /* In u8 */ 50 }; 51 52 #define MLXSW_REG(type) (&mlxsw_reg_##type) 53 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 54 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 55 56 /* SGCR - Switch General Configuration Register 57 * -------------------------------------------- 58 * This register is used for configuration of the switch capabilities. 59 */ 60 #define MLXSW_REG_SGCR_ID 0x2000 61 #define MLXSW_REG_SGCR_LEN 0x10 62 63 static const struct mlxsw_reg_info mlxsw_reg_sgcr = { 64 .id = MLXSW_REG_SGCR_ID, 65 .len = MLXSW_REG_SGCR_LEN, 66 }; 67 68 /* reg_sgcr_llb 69 * Link Local Broadcast (Default=0) 70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 71 * packets and ignore the IGMP snooping entries. 72 * Access: RW 73 */ 74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 75 76 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 77 { 78 MLXSW_REG_ZERO(sgcr, payload); 79 mlxsw_reg_sgcr_llb_set(payload, !!llb); 80 } 81 82 /* SPAD - Switch Physical Address Register 83 * --------------------------------------- 84 * The SPAD register configures the switch physical MAC address. 85 */ 86 #define MLXSW_REG_SPAD_ID 0x2002 87 #define MLXSW_REG_SPAD_LEN 0x10 88 89 static const struct mlxsw_reg_info mlxsw_reg_spad = { 90 .id = MLXSW_REG_SPAD_ID, 91 .len = MLXSW_REG_SPAD_LEN, 92 }; 93 94 /* reg_spad_base_mac 95 * Base MAC address for the switch partitions. 96 * Per switch partition MAC address is equal to: 97 * base_mac + swid 98 * Access: RW 99 */ 100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 101 102 /* SMID - Switch Multicast ID 103 * -------------------------- 104 * The MID record maps from a MID (Multicast ID), which is a unique identifier 105 * of the multicast group within the stacking domain, into a list of local 106 * ports into which the packet is replicated. 107 */ 108 #define MLXSW_REG_SMID_ID 0x2007 109 #define MLXSW_REG_SMID_LEN 0x240 110 111 static const struct mlxsw_reg_info mlxsw_reg_smid = { 112 .id = MLXSW_REG_SMID_ID, 113 .len = MLXSW_REG_SMID_LEN, 114 }; 115 116 /* reg_smid_swid 117 * Switch partition ID. 118 * Access: Index 119 */ 120 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 121 122 /* reg_smid_mid 123 * Multicast identifier - global identifier that represents the multicast group 124 * across all devices. 125 * Access: Index 126 */ 127 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 128 129 /* reg_smid_port 130 * Local port memebership (1 bit per port). 131 * Access: RW 132 */ 133 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 134 135 /* reg_smid_port_mask 136 * Local port mask (1 bit per port). 137 * Access: W 138 */ 139 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 140 141 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 142 u8 port, bool set) 143 { 144 MLXSW_REG_ZERO(smid, payload); 145 mlxsw_reg_smid_swid_set(payload, 0); 146 mlxsw_reg_smid_mid_set(payload, mid); 147 mlxsw_reg_smid_port_set(payload, port, set); 148 mlxsw_reg_smid_port_mask_set(payload, port, 1); 149 } 150 151 /* SSPR - Switch System Port Record Register 152 * ----------------------------------------- 153 * Configures the system port to local port mapping. 154 */ 155 #define MLXSW_REG_SSPR_ID 0x2008 156 #define MLXSW_REG_SSPR_LEN 0x8 157 158 static const struct mlxsw_reg_info mlxsw_reg_sspr = { 159 .id = MLXSW_REG_SSPR_ID, 160 .len = MLXSW_REG_SSPR_LEN, 161 }; 162 163 /* reg_sspr_m 164 * Master - if set, then the record describes the master system port. 165 * This is needed in case a local port is mapped into several system ports 166 * (for multipathing). That number will be reported as the source system 167 * port when packets are forwarded to the CPU. Only one master port is allowed 168 * per local port. 169 * 170 * Note: Must be set for Spectrum. 171 * Access: RW 172 */ 173 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 174 175 /* reg_sspr_local_port 176 * Local port number. 177 * 178 * Access: RW 179 */ 180 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 181 182 /* reg_sspr_sub_port 183 * Virtual port within the physical port. 184 * Should be set to 0 when virtual ports are not enabled on the port. 185 * 186 * Access: RW 187 */ 188 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 189 190 /* reg_sspr_system_port 191 * Unique identifier within the stacking domain that represents all the ports 192 * that are available in the system (external ports). 193 * 194 * Currently, only single-ASIC configurations are supported, so we default to 195 * 1:1 mapping between system ports and local ports. 196 * Access: Index 197 */ 198 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 199 200 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 201 { 202 MLXSW_REG_ZERO(sspr, payload); 203 mlxsw_reg_sspr_m_set(payload, 1); 204 mlxsw_reg_sspr_local_port_set(payload, local_port); 205 mlxsw_reg_sspr_sub_port_set(payload, 0); 206 mlxsw_reg_sspr_system_port_set(payload, local_port); 207 } 208 209 /* SFDAT - Switch Filtering Database Aging Time 210 * -------------------------------------------- 211 * Controls the Switch aging time. Aging time is able to be set per Switch 212 * Partition. 213 */ 214 #define MLXSW_REG_SFDAT_ID 0x2009 215 #define MLXSW_REG_SFDAT_LEN 0x8 216 217 static const struct mlxsw_reg_info mlxsw_reg_sfdat = { 218 .id = MLXSW_REG_SFDAT_ID, 219 .len = MLXSW_REG_SFDAT_LEN, 220 }; 221 222 /* reg_sfdat_swid 223 * Switch partition ID. 224 * Access: Index 225 */ 226 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 227 228 /* reg_sfdat_age_time 229 * Aging time in seconds 230 * Min - 10 seconds 231 * Max - 1,000,000 seconds 232 * Default is 300 seconds. 233 * Access: RW 234 */ 235 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 236 237 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 238 { 239 MLXSW_REG_ZERO(sfdat, payload); 240 mlxsw_reg_sfdat_swid_set(payload, 0); 241 mlxsw_reg_sfdat_age_time_set(payload, age_time); 242 } 243 244 /* SFD - Switch Filtering Database 245 * ------------------------------- 246 * The following register defines the access to the filtering database. 247 * The register supports querying, adding, removing and modifying the database. 248 * The access is optimized for bulk updates in which case more than one 249 * FDB record is present in the same command. 250 */ 251 #define MLXSW_REG_SFD_ID 0x200A 252 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 253 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 254 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 255 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 256 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 257 258 static const struct mlxsw_reg_info mlxsw_reg_sfd = { 259 .id = MLXSW_REG_SFD_ID, 260 .len = MLXSW_REG_SFD_LEN, 261 }; 262 263 /* reg_sfd_swid 264 * Switch partition ID for queries. Reserved on Write. 265 * Access: Index 266 */ 267 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 268 269 enum mlxsw_reg_sfd_op { 270 /* Dump entire FDB a (process according to record_locator) */ 271 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 272 /* Query records by {MAC, VID/FID} value */ 273 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 274 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 275 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 276 /* Test. Response indicates if each of the records could be 277 * added to the FDB. 278 */ 279 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 280 /* Add/modify. Aged-out records cannot be added. This command removes 281 * the learning notification of the {MAC, VID/FID}. Response includes 282 * the entries that were added to the FDB. 283 */ 284 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 285 /* Remove record by {MAC, VID/FID}. This command also removes 286 * the learning notification and aged-out notifications 287 * of the {MAC, VID/FID}. The response provides current (pre-removal) 288 * entries as non-aged-out. 289 */ 290 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 291 /* Remove learned notification by {MAC, VID/FID}. The response provides 292 * the removed learning notification. 293 */ 294 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 295 }; 296 297 /* reg_sfd_op 298 * Operation. 299 * Access: OP 300 */ 301 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 302 303 /* reg_sfd_record_locator 304 * Used for querying the FDB. Use record_locator=0 to initiate the 305 * query. When a record is returned, a new record_locator is 306 * returned to be used in the subsequent query. 307 * Reserved for database update. 308 * Access: Index 309 */ 310 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 311 312 /* reg_sfd_num_rec 313 * Request: Number of records to read/add/modify/remove 314 * Response: Number of records read/added/replaced/removed 315 * See above description for more details. 316 * Ranges 0..64 317 * Access: RW 318 */ 319 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 320 321 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 322 u32 record_locator) 323 { 324 MLXSW_REG_ZERO(sfd, payload); 325 mlxsw_reg_sfd_op_set(payload, op); 326 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 327 } 328 329 /* reg_sfd_rec_swid 330 * Switch partition ID. 331 * Access: Index 332 */ 333 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 334 MLXSW_REG_SFD_REC_LEN, 0x00, false); 335 336 enum mlxsw_reg_sfd_rec_type { 337 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 338 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 339 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 340 }; 341 342 /* reg_sfd_rec_type 343 * FDB record type. 344 * Access: RW 345 */ 346 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 347 MLXSW_REG_SFD_REC_LEN, 0x00, false); 348 349 enum mlxsw_reg_sfd_rec_policy { 350 /* Replacement disabled, aging disabled. */ 351 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 352 /* (mlag remote): Replacement enabled, aging disabled, 353 * learning notification enabled on this port. 354 */ 355 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 356 /* (ingress device): Replacement enabled, aging enabled. */ 357 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 358 }; 359 360 /* reg_sfd_rec_policy 361 * Policy. 362 * Access: RW 363 */ 364 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 365 MLXSW_REG_SFD_REC_LEN, 0x00, false); 366 367 /* reg_sfd_rec_a 368 * Activity. Set for new static entries. Set for static entries if a frame SMAC 369 * lookup hits on the entry. 370 * To clear the a bit, use "query and clear activity" op. 371 * Access: RO 372 */ 373 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 374 MLXSW_REG_SFD_REC_LEN, 0x00, false); 375 376 /* reg_sfd_rec_mac 377 * MAC address. 378 * Access: Index 379 */ 380 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 381 MLXSW_REG_SFD_REC_LEN, 0x02); 382 383 enum mlxsw_reg_sfd_rec_action { 384 /* forward */ 385 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 386 /* forward and trap, trap_id is FDB_TRAP */ 387 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 388 /* trap and do not forward, trap_id is FDB_TRAP */ 389 MLXSW_REG_SFD_REC_ACTION_TRAP = 3, 390 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 391 }; 392 393 /* reg_sfd_rec_action 394 * Action to apply on the packet. 395 * Note: Dynamic entries can only be configured with NOP action. 396 * Access: RW 397 */ 398 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 399 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 400 401 /* reg_sfd_uc_sub_port 402 * VEPA channel on local port. 403 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 404 * VEPA is not enabled. 405 * Access: RW 406 */ 407 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 408 MLXSW_REG_SFD_REC_LEN, 0x08, false); 409 410 /* reg_sfd_uc_fid_vid 411 * Filtering ID or VLAN ID 412 * For SwitchX and SwitchX-2: 413 * - Dynamic entries (policy 2,3) use FID 414 * - Static entries (policy 0) use VID 415 * - When independent learning is configured, VID=FID 416 * For Spectrum: use FID for both Dynamic and Static entries. 417 * VID should not be used. 418 * Access: Index 419 */ 420 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 421 MLXSW_REG_SFD_REC_LEN, 0x08, false); 422 423 /* reg_sfd_uc_system_port 424 * Unique port identifier for the final destination of the packet. 425 * Access: RW 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 428 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 429 430 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 431 enum mlxsw_reg_sfd_rec_type rec_type, 432 const char *mac, 433 enum mlxsw_reg_sfd_rec_action action) 434 { 435 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 436 437 if (rec_index >= num_rec) 438 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 439 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 440 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 441 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 442 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 443 } 444 445 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 446 enum mlxsw_reg_sfd_rec_policy policy, 447 const char *mac, u16 fid_vid, 448 enum mlxsw_reg_sfd_rec_action action, 449 u8 local_port) 450 { 451 mlxsw_reg_sfd_rec_pack(payload, rec_index, 452 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 453 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 454 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 455 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 456 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 457 } 458 459 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 460 char *mac, u16 *p_fid_vid, 461 u8 *p_local_port) 462 { 463 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 464 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 465 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 466 } 467 468 /* reg_sfd_uc_lag_sub_port 469 * LAG sub port. 470 * Must be 0 if multichannel VEPA is not enabled. 471 * Access: RW 472 */ 473 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 474 MLXSW_REG_SFD_REC_LEN, 0x08, false); 475 476 /* reg_sfd_uc_lag_fid_vid 477 * Filtering ID or VLAN ID 478 * For SwitchX and SwitchX-2: 479 * - Dynamic entries (policy 2,3) use FID 480 * - Static entries (policy 0) use VID 481 * - When independent learning is configured, VID=FID 482 * For Spectrum: use FID for both Dynamic and Static entries. 483 * VID should not be used. 484 * Access: Index 485 */ 486 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 487 MLXSW_REG_SFD_REC_LEN, 0x08, false); 488 489 /* reg_sfd_uc_lag_lag_vid 490 * Indicates VID in case of vFIDs. Reserved for FIDs. 491 * Access: RW 492 */ 493 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 494 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 495 496 /* reg_sfd_uc_lag_lag_id 497 * LAG Identifier - pointer into the LAG descriptor table. 498 * Access: RW 499 */ 500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 501 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 502 503 static inline void 504 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 505 enum mlxsw_reg_sfd_rec_policy policy, 506 const char *mac, u16 fid_vid, 507 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 508 u16 lag_id) 509 { 510 mlxsw_reg_sfd_rec_pack(payload, rec_index, 511 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 512 mac, action); 513 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 514 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 515 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 516 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 517 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 518 } 519 520 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 521 char *mac, u16 *p_vid, 522 u16 *p_lag_id) 523 { 524 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 525 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 526 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 527 } 528 529 /* reg_sfd_mc_pgi 530 * 531 * Multicast port group index - index into the port group table. 532 * Value 0x1FFF indicates the pgi should point to the MID entry. 533 * For Spectrum this value must be set to 0x1FFF 534 * Access: RW 535 */ 536 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 537 MLXSW_REG_SFD_REC_LEN, 0x08, false); 538 539 /* reg_sfd_mc_fid_vid 540 * 541 * Filtering ID or VLAN ID 542 * Access: Index 543 */ 544 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 545 MLXSW_REG_SFD_REC_LEN, 0x08, false); 546 547 /* reg_sfd_mc_mid 548 * 549 * Multicast identifier - global identifier that represents the multicast 550 * group across all devices. 551 * Access: RW 552 */ 553 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 554 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 555 556 static inline void 557 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 558 const char *mac, u16 fid_vid, 559 enum mlxsw_reg_sfd_rec_action action, u16 mid) 560 { 561 mlxsw_reg_sfd_rec_pack(payload, rec_index, 562 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 563 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 564 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 565 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 566 } 567 568 /* SFN - Switch FDB Notification Register 569 * ------------------------------------------- 570 * The switch provides notifications on newly learned FDB entries and 571 * aged out entries. The notifications can be polled by software. 572 */ 573 #define MLXSW_REG_SFN_ID 0x200B 574 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 575 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 576 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 577 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 578 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 579 580 static const struct mlxsw_reg_info mlxsw_reg_sfn = { 581 .id = MLXSW_REG_SFN_ID, 582 .len = MLXSW_REG_SFN_LEN, 583 }; 584 585 /* reg_sfn_swid 586 * Switch partition ID. 587 * Access: Index 588 */ 589 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 590 591 /* reg_sfn_num_rec 592 * Request: Number of learned notifications and aged-out notification 593 * records requested. 594 * Response: Number of notification records returned (must be smaller 595 * than or equal to the value requested) 596 * Ranges 0..64 597 * Access: OP 598 */ 599 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 600 601 static inline void mlxsw_reg_sfn_pack(char *payload) 602 { 603 MLXSW_REG_ZERO(sfn, payload); 604 mlxsw_reg_sfn_swid_set(payload, 0); 605 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 606 } 607 608 /* reg_sfn_rec_swid 609 * Switch partition ID. 610 * Access: RO 611 */ 612 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 613 MLXSW_REG_SFN_REC_LEN, 0x00, false); 614 615 enum mlxsw_reg_sfn_rec_type { 616 /* MAC addresses learned on a regular port. */ 617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 618 /* MAC addresses learned on a LAG port. */ 619 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 620 /* Aged-out MAC address on a regular port. */ 621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 622 /* Aged-out MAC address on a LAG port. */ 623 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 624 }; 625 626 /* reg_sfn_rec_type 627 * Notification record type. 628 * Access: RO 629 */ 630 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 631 MLXSW_REG_SFN_REC_LEN, 0x00, false); 632 633 /* reg_sfn_rec_mac 634 * MAC address. 635 * Access: RO 636 */ 637 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 638 MLXSW_REG_SFN_REC_LEN, 0x02); 639 640 /* reg_sfn_mac_sub_port 641 * VEPA channel on the local port. 642 * 0 if multichannel VEPA is not enabled. 643 * Access: RO 644 */ 645 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 646 MLXSW_REG_SFN_REC_LEN, 0x08, false); 647 648 /* reg_sfn_mac_fid 649 * Filtering identifier. 650 * Access: RO 651 */ 652 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 653 MLXSW_REG_SFN_REC_LEN, 0x08, false); 654 655 /* reg_sfn_mac_system_port 656 * Unique port identifier for the final destination of the packet. 657 * Access: RO 658 */ 659 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 660 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 661 662 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 663 char *mac, u16 *p_vid, 664 u8 *p_local_port) 665 { 666 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 667 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 668 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 669 } 670 671 /* reg_sfn_mac_lag_lag_id 672 * LAG ID (pointer into the LAG descriptor table). 673 * Access: RO 674 */ 675 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 676 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 677 678 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 679 char *mac, u16 *p_vid, 680 u16 *p_lag_id) 681 { 682 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 683 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 684 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 685 } 686 687 /* SPMS - Switch Port MSTP/RSTP State Register 688 * ------------------------------------------- 689 * Configures the spanning tree state of a physical port. 690 */ 691 #define MLXSW_REG_SPMS_ID 0x200D 692 #define MLXSW_REG_SPMS_LEN 0x404 693 694 static const struct mlxsw_reg_info mlxsw_reg_spms = { 695 .id = MLXSW_REG_SPMS_ID, 696 .len = MLXSW_REG_SPMS_LEN, 697 }; 698 699 /* reg_spms_local_port 700 * Local port number. 701 * Access: Index 702 */ 703 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 704 705 enum mlxsw_reg_spms_state { 706 MLXSW_REG_SPMS_STATE_NO_CHANGE, 707 MLXSW_REG_SPMS_STATE_DISCARDING, 708 MLXSW_REG_SPMS_STATE_LEARNING, 709 MLXSW_REG_SPMS_STATE_FORWARDING, 710 }; 711 712 /* reg_spms_state 713 * Spanning tree state of each VLAN ID (VID) of the local port. 714 * 0 - Do not change spanning tree state (used only when writing). 715 * 1 - Discarding. No learning or forwarding to/from this port (default). 716 * 2 - Learning. Port is learning, but not forwarding. 717 * 3 - Forwarding. Port is learning and forwarding. 718 * Access: RW 719 */ 720 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 721 722 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 723 { 724 MLXSW_REG_ZERO(spms, payload); 725 mlxsw_reg_spms_local_port_set(payload, local_port); 726 } 727 728 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 729 enum mlxsw_reg_spms_state state) 730 { 731 mlxsw_reg_spms_state_set(payload, vid, state); 732 } 733 734 /* SPVID - Switch Port VID 735 * ----------------------- 736 * The switch port VID configures the default VID for a port. 737 */ 738 #define MLXSW_REG_SPVID_ID 0x200E 739 #define MLXSW_REG_SPVID_LEN 0x08 740 741 static const struct mlxsw_reg_info mlxsw_reg_spvid = { 742 .id = MLXSW_REG_SPVID_ID, 743 .len = MLXSW_REG_SPVID_LEN, 744 }; 745 746 /* reg_spvid_local_port 747 * Local port number. 748 * Access: Index 749 */ 750 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 751 752 /* reg_spvid_sub_port 753 * Virtual port within the physical port. 754 * Should be set to 0 when virtual ports are not enabled on the port. 755 * Access: Index 756 */ 757 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 758 759 /* reg_spvid_pvid 760 * Port default VID 761 * Access: RW 762 */ 763 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 764 765 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 766 { 767 MLXSW_REG_ZERO(spvid, payload); 768 mlxsw_reg_spvid_local_port_set(payload, local_port); 769 mlxsw_reg_spvid_pvid_set(payload, pvid); 770 } 771 772 /* SPVM - Switch Port VLAN Membership 773 * ---------------------------------- 774 * The Switch Port VLAN Membership register configures the VLAN membership 775 * of a port in a VLAN denoted by VID. VLAN membership is managed per 776 * virtual port. The register can be used to add and remove VID(s) from a port. 777 */ 778 #define MLXSW_REG_SPVM_ID 0x200F 779 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 780 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 781 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256 782 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 783 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 784 785 static const struct mlxsw_reg_info mlxsw_reg_spvm = { 786 .id = MLXSW_REG_SPVM_ID, 787 .len = MLXSW_REG_SPVM_LEN, 788 }; 789 790 /* reg_spvm_pt 791 * Priority tagged. If this bit is set, packets forwarded to the port with 792 * untagged VLAN membership (u bit is set) will be tagged with priority tag 793 * (VID=0) 794 * Access: RW 795 */ 796 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 797 798 /* reg_spvm_pte 799 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 800 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 801 * Access: WO 802 */ 803 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 804 805 /* reg_spvm_local_port 806 * Local port number. 807 * Access: Index 808 */ 809 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 810 811 /* reg_spvm_sub_port 812 * Virtual port within the physical port. 813 * Should be set to 0 when virtual ports are not enabled on the port. 814 * Access: Index 815 */ 816 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 817 818 /* reg_spvm_num_rec 819 * Number of records to update. Each record contains: i, e, u, vid. 820 * Access: OP 821 */ 822 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 823 824 /* reg_spvm_rec_i 825 * Ingress membership in VLAN ID. 826 * Access: Index 827 */ 828 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 829 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 830 MLXSW_REG_SPVM_REC_LEN, 0, false); 831 832 /* reg_spvm_rec_e 833 * Egress membership in VLAN ID. 834 * Access: Index 835 */ 836 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 837 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 838 MLXSW_REG_SPVM_REC_LEN, 0, false); 839 840 /* reg_spvm_rec_u 841 * Untagged - port is an untagged member - egress transmission uses untagged 842 * frames on VID<n> 843 * Access: Index 844 */ 845 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 846 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 847 MLXSW_REG_SPVM_REC_LEN, 0, false); 848 849 /* reg_spvm_rec_vid 850 * Egress membership in VLAN ID. 851 * Access: Index 852 */ 853 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 854 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 855 MLXSW_REG_SPVM_REC_LEN, 0, false); 856 857 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 858 u16 vid_begin, u16 vid_end, 859 bool is_member, bool untagged) 860 { 861 int size = vid_end - vid_begin + 1; 862 int i; 863 864 MLXSW_REG_ZERO(spvm, payload); 865 mlxsw_reg_spvm_local_port_set(payload, local_port); 866 mlxsw_reg_spvm_num_rec_set(payload, size); 867 868 for (i = 0; i < size; i++) { 869 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 870 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 871 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 872 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 873 } 874 } 875 876 /* SFGC - Switch Flooding Group Configuration 877 * ------------------------------------------ 878 * The following register controls the association of flooding tables and MIDs 879 * to packet types used for flooding. 880 */ 881 #define MLXSW_REG_SFGC_ID 0x2011 882 #define MLXSW_REG_SFGC_LEN 0x10 883 884 static const struct mlxsw_reg_info mlxsw_reg_sfgc = { 885 .id = MLXSW_REG_SFGC_ID, 886 .len = MLXSW_REG_SFGC_LEN, 887 }; 888 889 enum mlxsw_reg_sfgc_type { 890 MLXSW_REG_SFGC_TYPE_BROADCAST, 891 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 892 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 893 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 894 MLXSW_REG_SFGC_TYPE_RESERVED, 895 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 896 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 897 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 898 MLXSW_REG_SFGC_TYPE_MAX, 899 }; 900 901 /* reg_sfgc_type 902 * The traffic type to reach the flooding table. 903 * Access: Index 904 */ 905 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 906 907 enum mlxsw_reg_sfgc_bridge_type { 908 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 909 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 910 }; 911 912 /* reg_sfgc_bridge_type 913 * Access: Index 914 * 915 * Note: SwitchX-2 only supports 802.1Q mode. 916 */ 917 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 918 919 enum mlxsw_flood_table_type { 920 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 921 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 922 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 923 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3, 924 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 925 }; 926 927 /* reg_sfgc_table_type 928 * See mlxsw_flood_table_type 929 * Access: RW 930 * 931 * Note: FID offset and FID types are not supported in SwitchX-2. 932 */ 933 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 934 935 /* reg_sfgc_flood_table 936 * Flooding table index to associate with the specific type on the specific 937 * switch partition. 938 * Access: RW 939 */ 940 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 941 942 /* reg_sfgc_mid 943 * The multicast ID for the swid. Not supported for Spectrum 944 * Access: RW 945 */ 946 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 947 948 /* reg_sfgc_counter_set_type 949 * Counter Set Type for flow counters. 950 * Access: RW 951 */ 952 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 953 954 /* reg_sfgc_counter_index 955 * Counter Index for flow counters. 956 * Access: RW 957 */ 958 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 959 960 static inline void 961 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 962 enum mlxsw_reg_sfgc_bridge_type bridge_type, 963 enum mlxsw_flood_table_type table_type, 964 unsigned int flood_table) 965 { 966 MLXSW_REG_ZERO(sfgc, payload); 967 mlxsw_reg_sfgc_type_set(payload, type); 968 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 969 mlxsw_reg_sfgc_table_type_set(payload, table_type); 970 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 971 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 972 } 973 974 /* SFTR - Switch Flooding Table Register 975 * ------------------------------------- 976 * The switch flooding table is used for flooding packet replication. The table 977 * defines a bit mask of ports for packet replication. 978 */ 979 #define MLXSW_REG_SFTR_ID 0x2012 980 #define MLXSW_REG_SFTR_LEN 0x420 981 982 static const struct mlxsw_reg_info mlxsw_reg_sftr = { 983 .id = MLXSW_REG_SFTR_ID, 984 .len = MLXSW_REG_SFTR_LEN, 985 }; 986 987 /* reg_sftr_swid 988 * Switch partition ID with which to associate the port. 989 * Access: Index 990 */ 991 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 992 993 /* reg_sftr_flood_table 994 * Flooding table index to associate with the specific type on the specific 995 * switch partition. 996 * Access: Index 997 */ 998 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 999 1000 /* reg_sftr_index 1001 * Index. Used as an index into the Flooding Table in case the table is 1002 * configured to use VID / FID or FID Offset. 1003 * Access: Index 1004 */ 1005 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1006 1007 /* reg_sftr_table_type 1008 * See mlxsw_flood_table_type 1009 * Access: RW 1010 */ 1011 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1012 1013 /* reg_sftr_range 1014 * Range of entries to update 1015 * Access: Index 1016 */ 1017 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1018 1019 /* reg_sftr_port 1020 * Local port membership (1 bit per port). 1021 * Access: RW 1022 */ 1023 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1024 1025 /* reg_sftr_cpu_port_mask 1026 * CPU port mask (1 bit per port). 1027 * Access: W 1028 */ 1029 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1030 1031 static inline void mlxsw_reg_sftr_pack(char *payload, 1032 unsigned int flood_table, 1033 unsigned int index, 1034 enum mlxsw_flood_table_type table_type, 1035 unsigned int range, u8 port, bool set) 1036 { 1037 MLXSW_REG_ZERO(sftr, payload); 1038 mlxsw_reg_sftr_swid_set(payload, 0); 1039 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1040 mlxsw_reg_sftr_index_set(payload, index); 1041 mlxsw_reg_sftr_table_type_set(payload, table_type); 1042 mlxsw_reg_sftr_range_set(payload, range); 1043 mlxsw_reg_sftr_port_set(payload, port, set); 1044 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1045 } 1046 1047 /* SFDF - Switch Filtering DB Flush 1048 * -------------------------------- 1049 * The switch filtering DB flush register is used to flush the FDB. 1050 * Note that FDB notifications are flushed as well. 1051 */ 1052 #define MLXSW_REG_SFDF_ID 0x2013 1053 #define MLXSW_REG_SFDF_LEN 0x14 1054 1055 static const struct mlxsw_reg_info mlxsw_reg_sfdf = { 1056 .id = MLXSW_REG_SFDF_ID, 1057 .len = MLXSW_REG_SFDF_LEN, 1058 }; 1059 1060 /* reg_sfdf_swid 1061 * Switch partition ID. 1062 * Access: Index 1063 */ 1064 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1065 1066 enum mlxsw_reg_sfdf_flush_type { 1067 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1068 MLXSW_REG_SFDF_FLUSH_PER_FID, 1069 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1070 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1071 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1072 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1073 }; 1074 1075 /* reg_sfdf_flush_type 1076 * Flush type. 1077 * 0 - All SWID dynamic entries are flushed. 1078 * 1 - All FID dynamic entries are flushed. 1079 * 2 - All dynamic entries pointing to port are flushed. 1080 * 3 - All FID dynamic entries pointing to port are flushed. 1081 * 4 - All dynamic entries pointing to LAG are flushed. 1082 * 5 - All FID dynamic entries pointing to LAG are flushed. 1083 * Access: RW 1084 */ 1085 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1086 1087 /* reg_sfdf_flush_static 1088 * Static. 1089 * 0 - Flush only dynamic entries. 1090 * 1 - Flush both dynamic and static entries. 1091 * Access: RW 1092 */ 1093 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1094 1095 static inline void mlxsw_reg_sfdf_pack(char *payload, 1096 enum mlxsw_reg_sfdf_flush_type type) 1097 { 1098 MLXSW_REG_ZERO(sfdf, payload); 1099 mlxsw_reg_sfdf_flush_type_set(payload, type); 1100 mlxsw_reg_sfdf_flush_static_set(payload, true); 1101 } 1102 1103 /* reg_sfdf_fid 1104 * FID to flush. 1105 * Access: RW 1106 */ 1107 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1108 1109 /* reg_sfdf_system_port 1110 * Port to flush. 1111 * Access: RW 1112 */ 1113 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1114 1115 /* reg_sfdf_port_fid_system_port 1116 * Port to flush, pointed to by FID. 1117 * Access: RW 1118 */ 1119 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1120 1121 /* reg_sfdf_lag_id 1122 * LAG ID to flush. 1123 * Access: RW 1124 */ 1125 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1126 1127 /* reg_sfdf_lag_fid_lag_id 1128 * LAG ID to flush, pointed to by FID. 1129 * Access: RW 1130 */ 1131 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1132 1133 /* SLDR - Switch LAG Descriptor Register 1134 * ----------------------------------------- 1135 * The switch LAG descriptor register is populated by LAG descriptors. 1136 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1137 * max_lag-1. 1138 */ 1139 #define MLXSW_REG_SLDR_ID 0x2014 1140 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1141 1142 static const struct mlxsw_reg_info mlxsw_reg_sldr = { 1143 .id = MLXSW_REG_SLDR_ID, 1144 .len = MLXSW_REG_SLDR_LEN, 1145 }; 1146 1147 enum mlxsw_reg_sldr_op { 1148 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1149 MLXSW_REG_SLDR_OP_LAG_CREATE, 1150 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1151 /* Ports that appear in the list have the Distributor enabled */ 1152 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1153 /* Removes ports from the disributor list */ 1154 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1155 }; 1156 1157 /* reg_sldr_op 1158 * Operation. 1159 * Access: RW 1160 */ 1161 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1162 1163 /* reg_sldr_lag_id 1164 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1165 * Access: Index 1166 */ 1167 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1168 1169 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1170 { 1171 MLXSW_REG_ZERO(sldr, payload); 1172 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1173 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1174 } 1175 1176 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1177 { 1178 MLXSW_REG_ZERO(sldr, payload); 1179 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1180 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1181 } 1182 1183 /* reg_sldr_num_ports 1184 * The number of member ports of the LAG. 1185 * Reserved for Create / Destroy operations 1186 * For Add / Remove operations - indicates the number of ports in the list. 1187 * Access: RW 1188 */ 1189 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1190 1191 /* reg_sldr_system_port 1192 * System port. 1193 * Access: RW 1194 */ 1195 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1196 1197 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1198 u8 local_port) 1199 { 1200 MLXSW_REG_ZERO(sldr, payload); 1201 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1202 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1203 mlxsw_reg_sldr_num_ports_set(payload, 1); 1204 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1205 } 1206 1207 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1208 u8 local_port) 1209 { 1210 MLXSW_REG_ZERO(sldr, payload); 1211 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1212 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1213 mlxsw_reg_sldr_num_ports_set(payload, 1); 1214 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1215 } 1216 1217 /* SLCR - Switch LAG Configuration 2 Register 1218 * ------------------------------------------- 1219 * The Switch LAG Configuration register is used for configuring the 1220 * LAG properties of the switch. 1221 */ 1222 #define MLXSW_REG_SLCR_ID 0x2015 1223 #define MLXSW_REG_SLCR_LEN 0x10 1224 1225 static const struct mlxsw_reg_info mlxsw_reg_slcr = { 1226 .id = MLXSW_REG_SLCR_ID, 1227 .len = MLXSW_REG_SLCR_LEN, 1228 }; 1229 1230 enum mlxsw_reg_slcr_pp { 1231 /* Global Configuration (for all ports) */ 1232 MLXSW_REG_SLCR_PP_GLOBAL, 1233 /* Per port configuration, based on local_port field */ 1234 MLXSW_REG_SLCR_PP_PER_PORT, 1235 }; 1236 1237 /* reg_slcr_pp 1238 * Per Port Configuration 1239 * Note: Reading at Global mode results in reading port 1 configuration. 1240 * Access: Index 1241 */ 1242 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1243 1244 /* reg_slcr_local_port 1245 * Local port number 1246 * Supported from CPU port 1247 * Not supported from router port 1248 * Reserved when pp = Global Configuration 1249 * Access: Index 1250 */ 1251 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1252 1253 enum mlxsw_reg_slcr_type { 1254 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1255 MLXSW_REG_SLCR_TYPE_XOR, 1256 MLXSW_REG_SLCR_TYPE_RANDOM, 1257 }; 1258 1259 /* reg_slcr_type 1260 * Hash type 1261 * Access: RW 1262 */ 1263 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1264 1265 /* Ingress port */ 1266 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1267 /* SMAC - for IPv4 and IPv6 packets */ 1268 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1269 /* SMAC - for non-IP packets */ 1270 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1271 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1272 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1273 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1274 /* DMAC - for IPv4 and IPv6 packets */ 1275 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1276 /* DMAC - for non-IP packets */ 1277 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1278 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1279 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1280 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1281 /* Ethertype - for IPv4 and IPv6 packets */ 1282 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1283 /* Ethertype - for non-IP packets */ 1284 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1285 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1286 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1287 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1288 /* VLAN ID - for IPv4 and IPv6 packets */ 1289 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1290 /* VLAN ID - for non-IP packets */ 1291 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1292 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1293 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1294 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1295 /* Source IP address (can be IPv4 or IPv6) */ 1296 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1297 /* Destination IP address (can be IPv4 or IPv6) */ 1298 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1299 /* TCP/UDP source port */ 1300 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1301 /* TCP/UDP destination port*/ 1302 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1303 /* IPv4 Protocol/IPv6 Next Header */ 1304 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1305 /* IPv6 Flow label */ 1306 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1307 /* SID - FCoE source ID */ 1308 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1309 /* DID - FCoE destination ID */ 1310 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1311 /* OXID - FCoE originator exchange ID */ 1312 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1313 /* Destination QP number - for RoCE packets */ 1314 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1315 1316 /* reg_slcr_lag_hash 1317 * LAG hashing configuration. This is a bitmask, in which each set 1318 * bit includes the corresponding item in the LAG hash calculation. 1319 * The default lag_hash contains SMAC, DMAC, VLANID and 1320 * Ethertype (for all packet types). 1321 * Access: RW 1322 */ 1323 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1324 1325 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1326 { 1327 MLXSW_REG_ZERO(slcr, payload); 1328 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1329 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR); 1330 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1331 } 1332 1333 /* SLCOR - Switch LAG Collector Register 1334 * ------------------------------------- 1335 * The Switch LAG Collector register controls the Local Port membership 1336 * in a LAG and enablement of the collector. 1337 */ 1338 #define MLXSW_REG_SLCOR_ID 0x2016 1339 #define MLXSW_REG_SLCOR_LEN 0x10 1340 1341 static const struct mlxsw_reg_info mlxsw_reg_slcor = { 1342 .id = MLXSW_REG_SLCOR_ID, 1343 .len = MLXSW_REG_SLCOR_LEN, 1344 }; 1345 1346 enum mlxsw_reg_slcor_col { 1347 /* Port is added with collector disabled */ 1348 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1349 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1350 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1351 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1352 }; 1353 1354 /* reg_slcor_col 1355 * Collector configuration 1356 * Access: RW 1357 */ 1358 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1359 1360 /* reg_slcor_local_port 1361 * Local port number 1362 * Not supported for CPU port 1363 * Access: Index 1364 */ 1365 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1366 1367 /* reg_slcor_lag_id 1368 * LAG Identifier. Index into the LAG descriptor table. 1369 * Access: Index 1370 */ 1371 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1372 1373 /* reg_slcor_port_index 1374 * Port index in the LAG list. Only valid on Add Port to LAG col. 1375 * Valid range is from 0 to cap_max_lag_members-1 1376 * Access: RW 1377 */ 1378 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1379 1380 static inline void mlxsw_reg_slcor_pack(char *payload, 1381 u8 local_port, u16 lag_id, 1382 enum mlxsw_reg_slcor_col col) 1383 { 1384 MLXSW_REG_ZERO(slcor, payload); 1385 mlxsw_reg_slcor_col_set(payload, col); 1386 mlxsw_reg_slcor_local_port_set(payload, local_port); 1387 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1388 } 1389 1390 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1391 u8 local_port, u16 lag_id, 1392 u8 port_index) 1393 { 1394 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1395 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1396 mlxsw_reg_slcor_port_index_set(payload, port_index); 1397 } 1398 1399 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1400 u8 local_port, u16 lag_id) 1401 { 1402 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1403 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1404 } 1405 1406 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1407 u8 local_port, u16 lag_id) 1408 { 1409 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1410 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1411 } 1412 1413 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1414 u8 local_port, u16 lag_id) 1415 { 1416 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1417 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1418 } 1419 1420 /* SPMLR - Switch Port MAC Learning Register 1421 * ----------------------------------------- 1422 * Controls the Switch MAC learning policy per port. 1423 */ 1424 #define MLXSW_REG_SPMLR_ID 0x2018 1425 #define MLXSW_REG_SPMLR_LEN 0x8 1426 1427 static const struct mlxsw_reg_info mlxsw_reg_spmlr = { 1428 .id = MLXSW_REG_SPMLR_ID, 1429 .len = MLXSW_REG_SPMLR_LEN, 1430 }; 1431 1432 /* reg_spmlr_local_port 1433 * Local port number. 1434 * Access: Index 1435 */ 1436 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1437 1438 /* reg_spmlr_sub_port 1439 * Virtual port within the physical port. 1440 * Should be set to 0 when virtual ports are not enabled on the port. 1441 * Access: Index 1442 */ 1443 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1444 1445 enum mlxsw_reg_spmlr_learn_mode { 1446 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1447 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1448 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1449 }; 1450 1451 /* reg_spmlr_learn_mode 1452 * Learning mode on the port. 1453 * 0 - Learning disabled. 1454 * 2 - Learning enabled. 1455 * 3 - Security mode. 1456 * 1457 * In security mode the switch does not learn MACs on the port, but uses the 1458 * SMAC to see if it exists on another ingress port. If so, the packet is 1459 * classified as a bad packet and is discarded unless the software registers 1460 * to receive port security error packets usign HPKT. 1461 */ 1462 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1463 1464 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1465 enum mlxsw_reg_spmlr_learn_mode mode) 1466 { 1467 MLXSW_REG_ZERO(spmlr, payload); 1468 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1469 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1470 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1471 } 1472 1473 /* SVFA - Switch VID to FID Allocation Register 1474 * -------------------------------------------- 1475 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1476 * virtualized ports. 1477 */ 1478 #define MLXSW_REG_SVFA_ID 0x201C 1479 #define MLXSW_REG_SVFA_LEN 0x10 1480 1481 static const struct mlxsw_reg_info mlxsw_reg_svfa = { 1482 .id = MLXSW_REG_SVFA_ID, 1483 .len = MLXSW_REG_SVFA_LEN, 1484 }; 1485 1486 /* reg_svfa_swid 1487 * Switch partition ID. 1488 * Access: Index 1489 */ 1490 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1491 1492 /* reg_svfa_local_port 1493 * Local port number. 1494 * Access: Index 1495 * 1496 * Note: Reserved for 802.1Q FIDs. 1497 */ 1498 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1499 1500 enum mlxsw_reg_svfa_mt { 1501 MLXSW_REG_SVFA_MT_VID_TO_FID, 1502 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1503 }; 1504 1505 /* reg_svfa_mapping_table 1506 * Mapping table: 1507 * 0 - VID to FID 1508 * 1 - {Port, VID} to FID 1509 * Access: Index 1510 * 1511 * Note: Reserved for SwitchX-2. 1512 */ 1513 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1514 1515 /* reg_svfa_v 1516 * Valid. 1517 * Valid if set. 1518 * Access: RW 1519 * 1520 * Note: Reserved for SwitchX-2. 1521 */ 1522 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1523 1524 /* reg_svfa_fid 1525 * Filtering ID. 1526 * Access: RW 1527 */ 1528 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1529 1530 /* reg_svfa_vid 1531 * VLAN ID. 1532 * Access: Index 1533 */ 1534 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1535 1536 /* reg_svfa_counter_set_type 1537 * Counter set type for flow counters. 1538 * Access: RW 1539 * 1540 * Note: Reserved for SwitchX-2. 1541 */ 1542 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1543 1544 /* reg_svfa_counter_index 1545 * Counter index for flow counters. 1546 * Access: RW 1547 * 1548 * Note: Reserved for SwitchX-2. 1549 */ 1550 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1551 1552 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1553 enum mlxsw_reg_svfa_mt mt, bool valid, 1554 u16 fid, u16 vid) 1555 { 1556 MLXSW_REG_ZERO(svfa, payload); 1557 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1558 mlxsw_reg_svfa_swid_set(payload, 0); 1559 mlxsw_reg_svfa_local_port_set(payload, local_port); 1560 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1561 mlxsw_reg_svfa_v_set(payload, valid); 1562 mlxsw_reg_svfa_fid_set(payload, fid); 1563 mlxsw_reg_svfa_vid_set(payload, vid); 1564 } 1565 1566 /* SVPE - Switch Virtual-Port Enabling Register 1567 * -------------------------------------------- 1568 * Enables port virtualization. 1569 */ 1570 #define MLXSW_REG_SVPE_ID 0x201E 1571 #define MLXSW_REG_SVPE_LEN 0x4 1572 1573 static const struct mlxsw_reg_info mlxsw_reg_svpe = { 1574 .id = MLXSW_REG_SVPE_ID, 1575 .len = MLXSW_REG_SVPE_LEN, 1576 }; 1577 1578 /* reg_svpe_local_port 1579 * Local port number 1580 * Access: Index 1581 * 1582 * Note: CPU port is not supported (uses VLAN mode only). 1583 */ 1584 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1585 1586 /* reg_svpe_vp_en 1587 * Virtual port enable. 1588 * 0 - Disable, VLAN mode (VID to FID). 1589 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1590 * Access: RW 1591 */ 1592 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1593 1594 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1595 bool enable) 1596 { 1597 MLXSW_REG_ZERO(svpe, payload); 1598 mlxsw_reg_svpe_local_port_set(payload, local_port); 1599 mlxsw_reg_svpe_vp_en_set(payload, enable); 1600 } 1601 1602 /* SFMR - Switch FID Management Register 1603 * ------------------------------------- 1604 * Creates and configures FIDs. 1605 */ 1606 #define MLXSW_REG_SFMR_ID 0x201F 1607 #define MLXSW_REG_SFMR_LEN 0x18 1608 1609 static const struct mlxsw_reg_info mlxsw_reg_sfmr = { 1610 .id = MLXSW_REG_SFMR_ID, 1611 .len = MLXSW_REG_SFMR_LEN, 1612 }; 1613 1614 enum mlxsw_reg_sfmr_op { 1615 MLXSW_REG_SFMR_OP_CREATE_FID, 1616 MLXSW_REG_SFMR_OP_DESTROY_FID, 1617 }; 1618 1619 /* reg_sfmr_op 1620 * Operation. 1621 * 0 - Create or edit FID. 1622 * 1 - Destroy FID. 1623 * Access: WO 1624 */ 1625 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1626 1627 /* reg_sfmr_fid 1628 * Filtering ID. 1629 * Access: Index 1630 */ 1631 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1632 1633 /* reg_sfmr_fid_offset 1634 * FID offset. 1635 * Used to point into the flooding table selected by SFGC register if 1636 * the table is of type FID-Offset. Otherwise, this field is reserved. 1637 * Access: RW 1638 */ 1639 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1640 1641 /* reg_sfmr_vtfp 1642 * Valid Tunnel Flood Pointer. 1643 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1644 * Access: RW 1645 * 1646 * Note: Reserved for 802.1Q FIDs. 1647 */ 1648 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1649 1650 /* reg_sfmr_nve_tunnel_flood_ptr 1651 * Underlay Flooding and BC Pointer. 1652 * Used as a pointer to the first entry of the group based link lists of 1653 * flooding or BC entries (for NVE tunnels). 1654 * Access: RW 1655 */ 1656 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1657 1658 /* reg_sfmr_vv 1659 * VNI Valid. 1660 * If not set, then vni is reserved. 1661 * Access: RW 1662 * 1663 * Note: Reserved for 802.1Q FIDs. 1664 */ 1665 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1666 1667 /* reg_sfmr_vni 1668 * Virtual Network Identifier. 1669 * Access: RW 1670 * 1671 * Note: A given VNI can only be assigned to one FID. 1672 */ 1673 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1674 1675 static inline void mlxsw_reg_sfmr_pack(char *payload, 1676 enum mlxsw_reg_sfmr_op op, u16 fid, 1677 u16 fid_offset) 1678 { 1679 MLXSW_REG_ZERO(sfmr, payload); 1680 mlxsw_reg_sfmr_op_set(payload, op); 1681 mlxsw_reg_sfmr_fid_set(payload, fid); 1682 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1683 mlxsw_reg_sfmr_vtfp_set(payload, false); 1684 mlxsw_reg_sfmr_vv_set(payload, false); 1685 } 1686 1687 /* SPVMLR - Switch Port VLAN MAC Learning Register 1688 * ----------------------------------------------- 1689 * Controls the switch MAC learning policy per {Port, VID}. 1690 */ 1691 #define MLXSW_REG_SPVMLR_ID 0x2020 1692 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1693 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1694 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256 1695 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1696 MLXSW_REG_SPVMLR_REC_LEN * \ 1697 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1698 1699 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = { 1700 .id = MLXSW_REG_SPVMLR_ID, 1701 .len = MLXSW_REG_SPVMLR_LEN, 1702 }; 1703 1704 /* reg_spvmlr_local_port 1705 * Local ingress port. 1706 * Access: Index 1707 * 1708 * Note: CPU port is not supported. 1709 */ 1710 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1711 1712 /* reg_spvmlr_num_rec 1713 * Number of records to update. 1714 * Access: OP 1715 */ 1716 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1717 1718 /* reg_spvmlr_rec_learn_enable 1719 * 0 - Disable learning for {Port, VID}. 1720 * 1 - Enable learning for {Port, VID}. 1721 * Access: RW 1722 */ 1723 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1724 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1725 1726 /* reg_spvmlr_rec_vid 1727 * VLAN ID to be added/removed from port or for querying. 1728 * Access: Index 1729 */ 1730 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1731 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1732 1733 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1734 u16 vid_begin, u16 vid_end, 1735 bool learn_enable) 1736 { 1737 int num_rec = vid_end - vid_begin + 1; 1738 int i; 1739 1740 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1741 1742 MLXSW_REG_ZERO(spvmlr, payload); 1743 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1744 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1745 1746 for (i = 0; i < num_rec; i++) { 1747 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1748 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1749 } 1750 } 1751 1752 /* PMLP - Ports Module to Local Port Register 1753 * ------------------------------------------ 1754 * Configures the assignment of modules to local ports. 1755 */ 1756 #define MLXSW_REG_PMLP_ID 0x5002 1757 #define MLXSW_REG_PMLP_LEN 0x40 1758 1759 static const struct mlxsw_reg_info mlxsw_reg_pmlp = { 1760 .id = MLXSW_REG_PMLP_ID, 1761 .len = MLXSW_REG_PMLP_LEN, 1762 }; 1763 1764 /* reg_pmlp_rxtx 1765 * 0 - Tx value is used for both Tx and Rx. 1766 * 1 - Rx value is taken from a separte field. 1767 * Access: RW 1768 */ 1769 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 1770 1771 /* reg_pmlp_local_port 1772 * Local port number. 1773 * Access: Index 1774 */ 1775 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 1776 1777 /* reg_pmlp_width 1778 * 0 - Unmap local port. 1779 * 1 - Lane 0 is used. 1780 * 2 - Lanes 0 and 1 are used. 1781 * 4 - Lanes 0, 1, 2 and 3 are used. 1782 * Access: RW 1783 */ 1784 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 1785 1786 /* reg_pmlp_module 1787 * Module number. 1788 * Access: RW 1789 */ 1790 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 1791 1792 /* reg_pmlp_tx_lane 1793 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 1794 * Access: RW 1795 */ 1796 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 1797 1798 /* reg_pmlp_rx_lane 1799 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 1800 * equal to Tx lane. 1801 * Access: RW 1802 */ 1803 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 1804 1805 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 1806 { 1807 MLXSW_REG_ZERO(pmlp, payload); 1808 mlxsw_reg_pmlp_local_port_set(payload, local_port); 1809 } 1810 1811 /* PMTU - Port MTU Register 1812 * ------------------------ 1813 * Configures and reports the port MTU. 1814 */ 1815 #define MLXSW_REG_PMTU_ID 0x5003 1816 #define MLXSW_REG_PMTU_LEN 0x10 1817 1818 static const struct mlxsw_reg_info mlxsw_reg_pmtu = { 1819 .id = MLXSW_REG_PMTU_ID, 1820 .len = MLXSW_REG_PMTU_LEN, 1821 }; 1822 1823 /* reg_pmtu_local_port 1824 * Local port number. 1825 * Access: Index 1826 */ 1827 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 1828 1829 /* reg_pmtu_max_mtu 1830 * Maximum MTU. 1831 * When port type (e.g. Ethernet) is configured, the relevant MTU is 1832 * reported, otherwise the minimum between the max_mtu of the different 1833 * types is reported. 1834 * Access: RO 1835 */ 1836 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 1837 1838 /* reg_pmtu_admin_mtu 1839 * MTU value to set port to. Must be smaller or equal to max_mtu. 1840 * Note: If port type is Infiniband, then port must be disabled, when its 1841 * MTU is set. 1842 * Access: RW 1843 */ 1844 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 1845 1846 /* reg_pmtu_oper_mtu 1847 * The actual MTU configured on the port. Packets exceeding this size 1848 * will be dropped. 1849 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 1850 * oper_mtu might be smaller than admin_mtu. 1851 * Access: RO 1852 */ 1853 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 1854 1855 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 1856 u16 new_mtu) 1857 { 1858 MLXSW_REG_ZERO(pmtu, payload); 1859 mlxsw_reg_pmtu_local_port_set(payload, local_port); 1860 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 1861 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 1862 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 1863 } 1864 1865 /* PTYS - Port Type and Speed Register 1866 * ----------------------------------- 1867 * Configures and reports the port speed type. 1868 * 1869 * Note: When set while the link is up, the changes will not take effect 1870 * until the port transitions from down to up state. 1871 */ 1872 #define MLXSW_REG_PTYS_ID 0x5004 1873 #define MLXSW_REG_PTYS_LEN 0x40 1874 1875 static const struct mlxsw_reg_info mlxsw_reg_ptys = { 1876 .id = MLXSW_REG_PTYS_ID, 1877 .len = MLXSW_REG_PTYS_LEN, 1878 }; 1879 1880 /* reg_ptys_local_port 1881 * Local port number. 1882 * Access: Index 1883 */ 1884 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 1885 1886 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 1887 1888 /* reg_ptys_proto_mask 1889 * Protocol mask. Indicates which protocol is used. 1890 * 0 - Infiniband. 1891 * 1 - Fibre Channel. 1892 * 2 - Ethernet. 1893 * Access: Index 1894 */ 1895 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 1896 1897 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 1898 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 1899 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 1900 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 1901 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 1902 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 1903 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 1904 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 1905 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 1906 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 1907 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 1908 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 1909 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 1910 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 1911 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 1912 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 1913 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 1914 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 1915 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 1916 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 1917 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 1918 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 1919 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 1920 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 1921 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 1922 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 1923 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 1924 1925 /* reg_ptys_eth_proto_cap 1926 * Ethernet port supported speeds and protocols. 1927 * Access: RO 1928 */ 1929 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 1930 1931 /* reg_ptys_eth_proto_admin 1932 * Speed and protocol to set port to. 1933 * Access: RW 1934 */ 1935 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 1936 1937 /* reg_ptys_eth_proto_oper 1938 * The current speed and protocol configured for the port. 1939 * Access: RO 1940 */ 1941 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 1942 1943 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port, 1944 u32 proto_admin) 1945 { 1946 MLXSW_REG_ZERO(ptys, payload); 1947 mlxsw_reg_ptys_local_port_set(payload, local_port); 1948 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 1949 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 1950 } 1951 1952 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap, 1953 u32 *p_eth_proto_adm, 1954 u32 *p_eth_proto_oper) 1955 { 1956 if (p_eth_proto_cap) 1957 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 1958 if (p_eth_proto_adm) 1959 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 1960 if (p_eth_proto_oper) 1961 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 1962 } 1963 1964 /* PPAD - Port Physical Address Register 1965 * ------------------------------------- 1966 * The PPAD register configures the per port physical MAC address. 1967 */ 1968 #define MLXSW_REG_PPAD_ID 0x5005 1969 #define MLXSW_REG_PPAD_LEN 0x10 1970 1971 static const struct mlxsw_reg_info mlxsw_reg_ppad = { 1972 .id = MLXSW_REG_PPAD_ID, 1973 .len = MLXSW_REG_PPAD_LEN, 1974 }; 1975 1976 /* reg_ppad_single_base_mac 1977 * 0: base_mac, local port should be 0 and mac[7:0] is 1978 * reserved. HW will set incremental 1979 * 1: single_mac - mac of the local_port 1980 * Access: RW 1981 */ 1982 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 1983 1984 /* reg_ppad_local_port 1985 * port number, if single_base_mac = 0 then local_port is reserved 1986 * Access: RW 1987 */ 1988 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 1989 1990 /* reg_ppad_mac 1991 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 1992 * If single_base_mac = 1 - the per port MAC address 1993 * Access: RW 1994 */ 1995 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 1996 1997 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 1998 u8 local_port) 1999 { 2000 MLXSW_REG_ZERO(ppad, payload); 2001 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 2002 mlxsw_reg_ppad_local_port_set(payload, local_port); 2003 } 2004 2005 /* PAOS - Ports Administrative and Operational Status Register 2006 * ----------------------------------------------------------- 2007 * Configures and retrieves per port administrative and operational status. 2008 */ 2009 #define MLXSW_REG_PAOS_ID 0x5006 2010 #define MLXSW_REG_PAOS_LEN 0x10 2011 2012 static const struct mlxsw_reg_info mlxsw_reg_paos = { 2013 .id = MLXSW_REG_PAOS_ID, 2014 .len = MLXSW_REG_PAOS_LEN, 2015 }; 2016 2017 /* reg_paos_swid 2018 * Switch partition ID with which to associate the port. 2019 * Note: while external ports uses unique local port numbers (and thus swid is 2020 * redundant), router ports use the same local port number where swid is the 2021 * only indication for the relevant port. 2022 * Access: Index 2023 */ 2024 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 2025 2026 /* reg_paos_local_port 2027 * Local port number. 2028 * Access: Index 2029 */ 2030 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 2031 2032 /* reg_paos_admin_status 2033 * Port administrative state (the desired state of the port): 2034 * 1 - Up. 2035 * 2 - Down. 2036 * 3 - Up once. This means that in case of link failure, the port won't go 2037 * into polling mode, but will wait to be re-enabled by software. 2038 * 4 - Disabled by system. Can only be set by hardware. 2039 * Access: RW 2040 */ 2041 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 2042 2043 /* reg_paos_oper_status 2044 * Port operational state (the current state): 2045 * 1 - Up. 2046 * 2 - Down. 2047 * 3 - Down by port failure. This means that the device will not let the 2048 * port up again until explicitly specified by software. 2049 * Access: RO 2050 */ 2051 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 2052 2053 /* reg_paos_ase 2054 * Admin state update enabled. 2055 * Access: WO 2056 */ 2057 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 2058 2059 /* reg_paos_ee 2060 * Event update enable. If this bit is set, event generation will be 2061 * updated based on the e field. 2062 * Access: WO 2063 */ 2064 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 2065 2066 /* reg_paos_e 2067 * Event generation on operational state change: 2068 * 0 - Do not generate event. 2069 * 1 - Generate Event. 2070 * 2 - Generate Single Event. 2071 * Access: RW 2072 */ 2073 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 2074 2075 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 2076 enum mlxsw_port_admin_status status) 2077 { 2078 MLXSW_REG_ZERO(paos, payload); 2079 mlxsw_reg_paos_swid_set(payload, 0); 2080 mlxsw_reg_paos_local_port_set(payload, local_port); 2081 mlxsw_reg_paos_admin_status_set(payload, status); 2082 mlxsw_reg_paos_oper_status_set(payload, 0); 2083 mlxsw_reg_paos_ase_set(payload, 1); 2084 mlxsw_reg_paos_ee_set(payload, 1); 2085 mlxsw_reg_paos_e_set(payload, 1); 2086 } 2087 2088 /* PPCNT - Ports Performance Counters Register 2089 * ------------------------------------------- 2090 * The PPCNT register retrieves per port performance counters. 2091 */ 2092 #define MLXSW_REG_PPCNT_ID 0x5008 2093 #define MLXSW_REG_PPCNT_LEN 0x100 2094 2095 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = { 2096 .id = MLXSW_REG_PPCNT_ID, 2097 .len = MLXSW_REG_PPCNT_LEN, 2098 }; 2099 2100 /* reg_ppcnt_swid 2101 * For HCA: must be always 0. 2102 * Switch partition ID to associate port with. 2103 * Switch partitions are numbered from 0 to 7 inclusively. 2104 * Switch partition 254 indicates stacking ports. 2105 * Switch partition 255 indicates all switch partitions. 2106 * Only valid on Set() operation with local_port=255. 2107 * Access: Index 2108 */ 2109 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 2110 2111 /* reg_ppcnt_local_port 2112 * Local port number. 2113 * 255 indicates all ports on the device, and is only allowed 2114 * for Set() operation. 2115 * Access: Index 2116 */ 2117 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 2118 2119 /* reg_ppcnt_pnat 2120 * Port number access type: 2121 * 0 - Local port number 2122 * 1 - IB port number 2123 * Access: Index 2124 */ 2125 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 2126 2127 /* reg_ppcnt_grp 2128 * Performance counter group. 2129 * Group 63 indicates all groups. Only valid on Set() operation with 2130 * clr bit set. 2131 * 0x0: IEEE 802.3 Counters 2132 * 0x1: RFC 2863 Counters 2133 * 0x2: RFC 2819 Counters 2134 * 0x3: RFC 3635 Counters 2135 * 0x5: Ethernet Extended Counters 2136 * 0x8: Link Level Retransmission Counters 2137 * 0x10: Per Priority Counters 2138 * 0x11: Per Traffic Class Counters 2139 * 0x12: Physical Layer Counters 2140 * Access: Index 2141 */ 2142 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 2143 2144 /* reg_ppcnt_clr 2145 * Clear counters. Setting the clr bit will reset the counter value 2146 * for all counters in the counter group. This bit can be set 2147 * for both Set() and Get() operation. 2148 * Access: OP 2149 */ 2150 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 2151 2152 /* reg_ppcnt_prio_tc 2153 * Priority for counter set that support per priority, valid values: 0-7. 2154 * Traffic class for counter set that support per traffic class, 2155 * valid values: 0- cap_max_tclass-1 . 2156 * For HCA: cap_max_tclass is always 8. 2157 * Otherwise must be 0. 2158 * Access: Index 2159 */ 2160 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 2161 2162 /* reg_ppcnt_a_frames_transmitted_ok 2163 * Access: RO 2164 */ 2165 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 2166 0x08 + 0x00, 0, 64); 2167 2168 /* reg_ppcnt_a_frames_received_ok 2169 * Access: RO 2170 */ 2171 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 2172 0x08 + 0x08, 0, 64); 2173 2174 /* reg_ppcnt_a_frame_check_sequence_errors 2175 * Access: RO 2176 */ 2177 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 2178 0x08 + 0x10, 0, 64); 2179 2180 /* reg_ppcnt_a_alignment_errors 2181 * Access: RO 2182 */ 2183 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 2184 0x08 + 0x18, 0, 64); 2185 2186 /* reg_ppcnt_a_octets_transmitted_ok 2187 * Access: RO 2188 */ 2189 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 2190 0x08 + 0x20, 0, 64); 2191 2192 /* reg_ppcnt_a_octets_received_ok 2193 * Access: RO 2194 */ 2195 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 2196 0x08 + 0x28, 0, 64); 2197 2198 /* reg_ppcnt_a_multicast_frames_xmitted_ok 2199 * Access: RO 2200 */ 2201 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 2202 0x08 + 0x30, 0, 64); 2203 2204 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 2205 * Access: RO 2206 */ 2207 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 2208 0x08 + 0x38, 0, 64); 2209 2210 /* reg_ppcnt_a_multicast_frames_received_ok 2211 * Access: RO 2212 */ 2213 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 2214 0x08 + 0x40, 0, 64); 2215 2216 /* reg_ppcnt_a_broadcast_frames_received_ok 2217 * Access: RO 2218 */ 2219 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 2220 0x08 + 0x48, 0, 64); 2221 2222 /* reg_ppcnt_a_in_range_length_errors 2223 * Access: RO 2224 */ 2225 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 2226 0x08 + 0x50, 0, 64); 2227 2228 /* reg_ppcnt_a_out_of_range_length_field 2229 * Access: RO 2230 */ 2231 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 2232 0x08 + 0x58, 0, 64); 2233 2234 /* reg_ppcnt_a_frame_too_long_errors 2235 * Access: RO 2236 */ 2237 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 2238 0x08 + 0x60, 0, 64); 2239 2240 /* reg_ppcnt_a_symbol_error_during_carrier 2241 * Access: RO 2242 */ 2243 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 2244 0x08 + 0x68, 0, 64); 2245 2246 /* reg_ppcnt_a_mac_control_frames_transmitted 2247 * Access: RO 2248 */ 2249 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 2250 0x08 + 0x70, 0, 64); 2251 2252 /* reg_ppcnt_a_mac_control_frames_received 2253 * Access: RO 2254 */ 2255 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 2256 0x08 + 0x78, 0, 64); 2257 2258 /* reg_ppcnt_a_unsupported_opcodes_received 2259 * Access: RO 2260 */ 2261 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 2262 0x08 + 0x80, 0, 64); 2263 2264 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 2265 * Access: RO 2266 */ 2267 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 2268 0x08 + 0x88, 0, 64); 2269 2270 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 2271 * Access: RO 2272 */ 2273 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 2274 0x08 + 0x90, 0, 64); 2275 2276 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port) 2277 { 2278 MLXSW_REG_ZERO(ppcnt, payload); 2279 mlxsw_reg_ppcnt_swid_set(payload, 0); 2280 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 2281 mlxsw_reg_ppcnt_pnat_set(payload, 0); 2282 mlxsw_reg_ppcnt_grp_set(payload, 0); 2283 mlxsw_reg_ppcnt_clr_set(payload, 0); 2284 mlxsw_reg_ppcnt_prio_tc_set(payload, 0); 2285 } 2286 2287 /* PBMC - Port Buffer Management Control Register 2288 * ---------------------------------------------- 2289 * The PBMC register configures and retrieves the port packet buffer 2290 * allocation for different Prios, and the Pause threshold management. 2291 */ 2292 #define MLXSW_REG_PBMC_ID 0x500C 2293 #define MLXSW_REG_PBMC_LEN 0x68 2294 2295 static const struct mlxsw_reg_info mlxsw_reg_pbmc = { 2296 .id = MLXSW_REG_PBMC_ID, 2297 .len = MLXSW_REG_PBMC_LEN, 2298 }; 2299 2300 /* reg_pbmc_local_port 2301 * Local port number. 2302 * Access: Index 2303 */ 2304 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 2305 2306 /* reg_pbmc_xoff_timer_value 2307 * When device generates a pause frame, it uses this value as the pause 2308 * timer (time for the peer port to pause in quota-512 bit time). 2309 * Access: RW 2310 */ 2311 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 2312 2313 /* reg_pbmc_xoff_refresh 2314 * The time before a new pause frame should be sent to refresh the pause RW 2315 * state. Using the same units as xoff_timer_value above (in quota-512 bit 2316 * time). 2317 * Access: RW 2318 */ 2319 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 2320 2321 /* reg_pbmc_buf_lossy 2322 * The field indicates if the buffer is lossy. 2323 * 0 - Lossless 2324 * 1 - Lossy 2325 * Access: RW 2326 */ 2327 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 2328 2329 /* reg_pbmc_buf_epsb 2330 * Eligible for Port Shared buffer. 2331 * If epsb is set, packets assigned to buffer are allowed to insert the port 2332 * shared buffer. 2333 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 2334 * Access: RW 2335 */ 2336 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 2337 2338 /* reg_pbmc_buf_size 2339 * The part of the packet buffer array is allocated for the specific buffer. 2340 * Units are represented in cells. 2341 * Access: RW 2342 */ 2343 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 2344 2345 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 2346 u16 xoff_timer_value, u16 xoff_refresh) 2347 { 2348 MLXSW_REG_ZERO(pbmc, payload); 2349 mlxsw_reg_pbmc_local_port_set(payload, local_port); 2350 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 2351 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 2352 } 2353 2354 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 2355 int buf_index, 2356 u16 size) 2357 { 2358 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 2359 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 2360 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 2361 } 2362 2363 /* PSPA - Port Switch Partition Allocation 2364 * --------------------------------------- 2365 * Controls the association of a port with a switch partition and enables 2366 * configuring ports as stacking ports. 2367 */ 2368 #define MLXSW_REG_PSPA_ID 0x500D 2369 #define MLXSW_REG_PSPA_LEN 0x8 2370 2371 static const struct mlxsw_reg_info mlxsw_reg_pspa = { 2372 .id = MLXSW_REG_PSPA_ID, 2373 .len = MLXSW_REG_PSPA_LEN, 2374 }; 2375 2376 /* reg_pspa_swid 2377 * Switch partition ID. 2378 * Access: RW 2379 */ 2380 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 2381 2382 /* reg_pspa_local_port 2383 * Local port number. 2384 * Access: Index 2385 */ 2386 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 2387 2388 /* reg_pspa_sub_port 2389 * Virtual port within the local port. Set to 0 when virtual ports are 2390 * disabled on the local port. 2391 * Access: Index 2392 */ 2393 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 2394 2395 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 2396 { 2397 MLXSW_REG_ZERO(pspa, payload); 2398 mlxsw_reg_pspa_swid_set(payload, swid); 2399 mlxsw_reg_pspa_local_port_set(payload, local_port); 2400 mlxsw_reg_pspa_sub_port_set(payload, 0); 2401 } 2402 2403 /* HTGT - Host Trap Group Table 2404 * ---------------------------- 2405 * Configures the properties for forwarding to CPU. 2406 */ 2407 #define MLXSW_REG_HTGT_ID 0x7002 2408 #define MLXSW_REG_HTGT_LEN 0x100 2409 2410 static const struct mlxsw_reg_info mlxsw_reg_htgt = { 2411 .id = MLXSW_REG_HTGT_ID, 2412 .len = MLXSW_REG_HTGT_LEN, 2413 }; 2414 2415 /* reg_htgt_swid 2416 * Switch partition ID. 2417 * Access: Index 2418 */ 2419 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 2420 2421 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 2422 2423 /* reg_htgt_type 2424 * CPU path type. 2425 * Access: RW 2426 */ 2427 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 2428 2429 enum mlxsw_reg_htgt_trap_group { 2430 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 2431 MLXSW_REG_HTGT_TRAP_GROUP_RX, 2432 MLXSW_REG_HTGT_TRAP_GROUP_CTRL, 2433 }; 2434 2435 /* reg_htgt_trap_group 2436 * Trap group number. User defined number specifying which trap groups 2437 * should be forwarded to the CPU. The mapping between trap IDs and trap 2438 * groups is configured using HPKT register. 2439 * Access: Index 2440 */ 2441 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 2442 2443 enum { 2444 MLXSW_REG_HTGT_POLICER_DISABLE, 2445 MLXSW_REG_HTGT_POLICER_ENABLE, 2446 }; 2447 2448 /* reg_htgt_pide 2449 * Enable policer ID specified using 'pid' field. 2450 * Access: RW 2451 */ 2452 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 2453 2454 /* reg_htgt_pid 2455 * Policer ID for the trap group. 2456 * Access: RW 2457 */ 2458 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 2459 2460 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 2461 2462 /* reg_htgt_mirror_action 2463 * Mirror action to use. 2464 * 0 - Trap to CPU. 2465 * 1 - Trap to CPU and mirror to a mirroring agent. 2466 * 2 - Mirror to a mirroring agent and do not trap to CPU. 2467 * Access: RW 2468 * 2469 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 2470 */ 2471 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 2472 2473 /* reg_htgt_mirroring_agent 2474 * Mirroring agent. 2475 * Access: RW 2476 */ 2477 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 2478 2479 /* reg_htgt_priority 2480 * Trap group priority. 2481 * In case a packet matches multiple classification rules, the packet will 2482 * only be trapped once, based on the trap ID associated with the group (via 2483 * register HPKT) with the highest priority. 2484 * Supported values are 0-7, with 7 represnting the highest priority. 2485 * Access: RW 2486 * 2487 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 2488 * by the 'trap_group' field. 2489 */ 2490 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 2491 2492 /* reg_htgt_local_path_cpu_tclass 2493 * CPU ingress traffic class for the trap group. 2494 * Access: RW 2495 */ 2496 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 2497 2498 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15 2499 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14 2500 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13 2501 2502 /* reg_htgt_local_path_rdq 2503 * Receive descriptor queue (RDQ) to use for the trap group. 2504 * Access: RW 2505 */ 2506 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 2507 2508 static inline void mlxsw_reg_htgt_pack(char *payload, 2509 enum mlxsw_reg_htgt_trap_group group) 2510 { 2511 u8 swid, rdq; 2512 2513 MLXSW_REG_ZERO(htgt, payload); 2514 switch (group) { 2515 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD: 2516 swid = MLXSW_PORT_SWID_ALL_SWIDS; 2517 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD; 2518 break; 2519 case MLXSW_REG_HTGT_TRAP_GROUP_RX: 2520 swid = 0; 2521 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX; 2522 break; 2523 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL: 2524 swid = 0; 2525 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL; 2526 break; 2527 } 2528 mlxsw_reg_htgt_swid_set(payload, swid); 2529 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 2530 mlxsw_reg_htgt_trap_group_set(payload, group); 2531 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE); 2532 mlxsw_reg_htgt_pid_set(payload, 0); 2533 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 2534 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 2535 mlxsw_reg_htgt_priority_set(payload, 0); 2536 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7); 2537 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq); 2538 } 2539 2540 /* HPKT - Host Packet Trap 2541 * ----------------------- 2542 * Configures trap IDs inside trap groups. 2543 */ 2544 #define MLXSW_REG_HPKT_ID 0x7003 2545 #define MLXSW_REG_HPKT_LEN 0x10 2546 2547 static const struct mlxsw_reg_info mlxsw_reg_hpkt = { 2548 .id = MLXSW_REG_HPKT_ID, 2549 .len = MLXSW_REG_HPKT_LEN, 2550 }; 2551 2552 enum { 2553 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 2554 MLXSW_REG_HPKT_ACK_REQUIRED, 2555 }; 2556 2557 /* reg_hpkt_ack 2558 * Require acknowledgements from the host for events. 2559 * If set, then the device will wait for the event it sent to be acknowledged 2560 * by the host. This option is only relevant for event trap IDs. 2561 * Access: RW 2562 * 2563 * Note: Currently not supported by firmware. 2564 */ 2565 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 2566 2567 enum mlxsw_reg_hpkt_action { 2568 MLXSW_REG_HPKT_ACTION_FORWARD, 2569 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 2570 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 2571 MLXSW_REG_HPKT_ACTION_DISCARD, 2572 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 2573 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 2574 }; 2575 2576 /* reg_hpkt_action 2577 * Action to perform on packet when trapped. 2578 * 0 - No action. Forward to CPU based on switching rules. 2579 * 1 - Trap to CPU (CPU receives sole copy). 2580 * 2 - Mirror to CPU (CPU receives a replica of the packet). 2581 * 3 - Discard. 2582 * 4 - Soft discard (allow other traps to act on the packet). 2583 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 2584 * Access: RW 2585 * 2586 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 2587 * addressed to the CPU. 2588 */ 2589 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 2590 2591 /* reg_hpkt_trap_group 2592 * Trap group to associate the trap with. 2593 * Access: RW 2594 */ 2595 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 2596 2597 /* reg_hpkt_trap_id 2598 * Trap ID. 2599 * Access: Index 2600 * 2601 * Note: A trap ID can only be associated with a single trap group. The device 2602 * will associate the trap ID with the last trap group configured. 2603 */ 2604 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 2605 2606 enum { 2607 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 2608 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 2609 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 2610 }; 2611 2612 /* reg_hpkt_ctrl 2613 * Configure dedicated buffer resources for control packets. 2614 * 0 - Keep factory defaults. 2615 * 1 - Do not use control buffer for this trap ID. 2616 * 2 - Use control buffer for this trap ID. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 2620 2621 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id) 2622 { 2623 enum mlxsw_reg_htgt_trap_group trap_group; 2624 2625 MLXSW_REG_ZERO(hpkt, payload); 2626 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 2627 mlxsw_reg_hpkt_action_set(payload, action); 2628 switch (trap_id) { 2629 case MLXSW_TRAP_ID_ETHEMAD: 2630 case MLXSW_TRAP_ID_PUDE: 2631 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD; 2632 break; 2633 default: 2634 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX; 2635 break; 2636 } 2637 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 2638 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 2639 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT); 2640 } 2641 2642 /* MFCR - Management Fan Control Register 2643 * -------------------------------------- 2644 * This register controls the settings of the Fan Speed PWM mechanism. 2645 */ 2646 #define MLXSW_REG_MFCR_ID 0x9001 2647 #define MLXSW_REG_MFCR_LEN 0x08 2648 2649 static const struct mlxsw_reg_info mlxsw_reg_mfcr = { 2650 .id = MLXSW_REG_MFCR_ID, 2651 .len = MLXSW_REG_MFCR_LEN, 2652 }; 2653 2654 enum mlxsw_reg_mfcr_pwm_frequency { 2655 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 2656 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 2657 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 2658 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 2659 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 2660 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 2661 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 2662 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 2663 }; 2664 2665 /* reg_mfcr_pwm_frequency 2666 * Controls the frequency of the PWM signal. 2667 * Access: RW 2668 */ 2669 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6); 2670 2671 #define MLXSW_MFCR_TACHOS_MAX 10 2672 2673 /* reg_mfcr_tacho_active 2674 * Indicates which of the tachometer is active (bit per tachometer). 2675 * Access: RO 2676 */ 2677 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 2678 2679 #define MLXSW_MFCR_PWMS_MAX 5 2680 2681 /* reg_mfcr_pwm_active 2682 * Indicates which of the PWM control is active (bit per PWM). 2683 * Access: RO 2684 */ 2685 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 2686 2687 static inline void 2688 mlxsw_reg_mfcr_pack(char *payload, 2689 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 2690 { 2691 MLXSW_REG_ZERO(mfcr, payload); 2692 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 2693 } 2694 2695 static inline void 2696 mlxsw_reg_mfcr_unpack(char *payload, 2697 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 2698 u16 *p_tacho_active, u8 *p_pwm_active) 2699 { 2700 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 2701 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 2702 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 2703 } 2704 2705 /* MFSC - Management Fan Speed Control Register 2706 * -------------------------------------------- 2707 * This register controls the settings of the Fan Speed PWM mechanism. 2708 */ 2709 #define MLXSW_REG_MFSC_ID 0x9002 2710 #define MLXSW_REG_MFSC_LEN 0x08 2711 2712 static const struct mlxsw_reg_info mlxsw_reg_mfsc = { 2713 .id = MLXSW_REG_MFSC_ID, 2714 .len = MLXSW_REG_MFSC_LEN, 2715 }; 2716 2717 /* reg_mfsc_pwm 2718 * Fan pwm to control / monitor. 2719 * Access: Index 2720 */ 2721 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 2722 2723 /* reg_mfsc_pwm_duty_cycle 2724 * Controls the duty cycle of the PWM. Value range from 0..255 to 2725 * represent duty cycle of 0%...100%. 2726 * Access: RW 2727 */ 2728 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 2729 2730 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 2731 u8 pwm_duty_cycle) 2732 { 2733 MLXSW_REG_ZERO(mfsc, payload); 2734 mlxsw_reg_mfsc_pwm_set(payload, pwm); 2735 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 2736 } 2737 2738 /* MFSM - Management Fan Speed Measurement 2739 * --------------------------------------- 2740 * This register controls the settings of the Tacho measurements and 2741 * enables reading the Tachometer measurements. 2742 */ 2743 #define MLXSW_REG_MFSM_ID 0x9003 2744 #define MLXSW_REG_MFSM_LEN 0x08 2745 2746 static const struct mlxsw_reg_info mlxsw_reg_mfsm = { 2747 .id = MLXSW_REG_MFSM_ID, 2748 .len = MLXSW_REG_MFSM_LEN, 2749 }; 2750 2751 /* reg_mfsm_tacho 2752 * Fan tachometer index. 2753 * Access: Index 2754 */ 2755 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 2756 2757 /* reg_mfsm_rpm 2758 * Fan speed (round per minute). 2759 * Access: RO 2760 */ 2761 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 2762 2763 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 2764 { 2765 MLXSW_REG_ZERO(mfsm, payload); 2766 mlxsw_reg_mfsm_tacho_set(payload, tacho); 2767 } 2768 2769 /* MTCAP - Management Temperature Capabilities 2770 * ------------------------------------------- 2771 * This register exposes the capabilities of the device and 2772 * system temperature sensing. 2773 */ 2774 #define MLXSW_REG_MTCAP_ID 0x9009 2775 #define MLXSW_REG_MTCAP_LEN 0x08 2776 2777 static const struct mlxsw_reg_info mlxsw_reg_mtcap = { 2778 .id = MLXSW_REG_MTCAP_ID, 2779 .len = MLXSW_REG_MTCAP_LEN, 2780 }; 2781 2782 /* reg_mtcap_sensor_count 2783 * Number of sensors supported by the device. 2784 * This includes the QSFP module sensors (if exists in the QSFP module). 2785 * Access: RO 2786 */ 2787 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 2788 2789 /* MTMP - Management Temperature 2790 * ----------------------------- 2791 * This register controls the settings of the temperature measurements 2792 * and enables reading the temperature measurements. Note that temperature 2793 * is in 0.125 degrees Celsius. 2794 */ 2795 #define MLXSW_REG_MTMP_ID 0x900A 2796 #define MLXSW_REG_MTMP_LEN 0x20 2797 2798 static const struct mlxsw_reg_info mlxsw_reg_mtmp = { 2799 .id = MLXSW_REG_MTMP_ID, 2800 .len = MLXSW_REG_MTMP_LEN, 2801 }; 2802 2803 /* reg_mtmp_sensor_index 2804 * Sensors index to access. 2805 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 2806 * (module 0 is mapped to sensor_index 64). 2807 * Access: Index 2808 */ 2809 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 2810 2811 /* Convert to milli degrees Celsius */ 2812 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 2813 2814 /* reg_mtmp_temperature 2815 * Temperature reading from the sensor. Reading is in 0.125 Celsius 2816 * degrees units. 2817 * Access: RO 2818 */ 2819 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 2820 2821 /* reg_mtmp_mte 2822 * Max Temperature Enable - enables measuring the max temperature on a sensor. 2823 * Access: RW 2824 */ 2825 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 2826 2827 /* reg_mtmp_mtr 2828 * Max Temperature Reset - clears the value of the max temperature register. 2829 * Access: WO 2830 */ 2831 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 2832 2833 /* reg_mtmp_max_temperature 2834 * The highest measured temperature from the sensor. 2835 * When the bit mte is cleared, the field max_temperature is reserved. 2836 * Access: RO 2837 */ 2838 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 2839 2840 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 2841 2842 /* reg_mtmp_sensor_name 2843 * Sensor Name 2844 * Access: RO 2845 */ 2846 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 2847 2848 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 2849 bool max_temp_enable, 2850 bool max_temp_reset) 2851 { 2852 MLXSW_REG_ZERO(mtmp, payload); 2853 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 2854 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 2855 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 2856 } 2857 2858 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 2859 unsigned int *p_max_temp, 2860 char *sensor_name) 2861 { 2862 u16 temp; 2863 2864 if (p_temp) { 2865 temp = mlxsw_reg_mtmp_temperature_get(payload); 2866 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 2867 } 2868 if (p_max_temp) { 2869 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 2870 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 2871 } 2872 if (sensor_name) 2873 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 2874 } 2875 2876 /* MLCR - Management LED Control Register 2877 * -------------------------------------- 2878 * Controls the system LEDs. 2879 */ 2880 #define MLXSW_REG_MLCR_ID 0x902B 2881 #define MLXSW_REG_MLCR_LEN 0x0C 2882 2883 static const struct mlxsw_reg_info mlxsw_reg_mlcr = { 2884 .id = MLXSW_REG_MLCR_ID, 2885 .len = MLXSW_REG_MLCR_LEN, 2886 }; 2887 2888 /* reg_mlcr_local_port 2889 * Local port number. 2890 * Access: RW 2891 */ 2892 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 2893 2894 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 2895 2896 /* reg_mlcr_beacon_duration 2897 * Duration of the beacon to be active, in seconds. 2898 * 0x0 - Will turn off the beacon. 2899 * 0xFFFF - Will turn on the beacon until explicitly turned off. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 2903 2904 /* reg_mlcr_beacon_remain 2905 * Remaining duration of the beacon, in seconds. 2906 * 0xFFFF indicates an infinite amount of time. 2907 * Access: RO 2908 */ 2909 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 2910 2911 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 2912 bool active) 2913 { 2914 MLXSW_REG_ZERO(mlcr, payload); 2915 mlxsw_reg_mlcr_local_port_set(payload, local_port); 2916 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 2917 MLXSW_REG_MLCR_DURATION_MAX : 0); 2918 } 2919 2920 /* SBPR - Shared Buffer Pools Register 2921 * ----------------------------------- 2922 * The SBPR configures and retrieves the shared buffer pools and configuration. 2923 */ 2924 #define MLXSW_REG_SBPR_ID 0xB001 2925 #define MLXSW_REG_SBPR_LEN 0x14 2926 2927 static const struct mlxsw_reg_info mlxsw_reg_sbpr = { 2928 .id = MLXSW_REG_SBPR_ID, 2929 .len = MLXSW_REG_SBPR_LEN, 2930 }; 2931 2932 enum mlxsw_reg_sbpr_dir { 2933 MLXSW_REG_SBPR_DIR_INGRESS, 2934 MLXSW_REG_SBPR_DIR_EGRESS, 2935 }; 2936 2937 /* reg_sbpr_dir 2938 * Direction. 2939 * Access: Index 2940 */ 2941 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 2942 2943 /* reg_sbpr_pool 2944 * Pool index. 2945 * Access: Index 2946 */ 2947 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 2948 2949 /* reg_sbpr_size 2950 * Pool size in buffer cells. 2951 * Access: RW 2952 */ 2953 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 2954 2955 enum mlxsw_reg_sbpr_mode { 2956 MLXSW_REG_SBPR_MODE_STATIC, 2957 MLXSW_REG_SBPR_MODE_DYNAMIC, 2958 }; 2959 2960 /* reg_sbpr_mode 2961 * Pool quota calculation mode. 2962 * Access: RW 2963 */ 2964 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 2965 2966 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 2967 enum mlxsw_reg_sbpr_dir dir, 2968 enum mlxsw_reg_sbpr_mode mode, u32 size) 2969 { 2970 MLXSW_REG_ZERO(sbpr, payload); 2971 mlxsw_reg_sbpr_pool_set(payload, pool); 2972 mlxsw_reg_sbpr_dir_set(payload, dir); 2973 mlxsw_reg_sbpr_mode_set(payload, mode); 2974 mlxsw_reg_sbpr_size_set(payload, size); 2975 } 2976 2977 /* SBCM - Shared Buffer Class Management Register 2978 * ---------------------------------------------- 2979 * The SBCM register configures and retrieves the shared buffer allocation 2980 * and configuration according to Port-PG, including the binding to pool 2981 * and definition of the associated quota. 2982 */ 2983 #define MLXSW_REG_SBCM_ID 0xB002 2984 #define MLXSW_REG_SBCM_LEN 0x28 2985 2986 static const struct mlxsw_reg_info mlxsw_reg_sbcm = { 2987 .id = MLXSW_REG_SBCM_ID, 2988 .len = MLXSW_REG_SBCM_LEN, 2989 }; 2990 2991 /* reg_sbcm_local_port 2992 * Local port number. 2993 * For Ingress: excludes CPU port and Router port 2994 * For Egress: excludes IP Router 2995 * Access: Index 2996 */ 2997 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 2998 2999 /* reg_sbcm_pg_buff 3000 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 3001 * For PG buffer: range is 0..cap_max_pg_buffers - 1 3002 * For traffic class: range is 0..cap_max_tclass - 1 3003 * Note that when traffic class is in MC aware mode then the traffic 3004 * classes which are MC aware cannot be configured. 3005 * Access: Index 3006 */ 3007 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 3008 3009 enum mlxsw_reg_sbcm_dir { 3010 MLXSW_REG_SBCM_DIR_INGRESS, 3011 MLXSW_REG_SBCM_DIR_EGRESS, 3012 }; 3013 3014 /* reg_sbcm_dir 3015 * Direction. 3016 * Access: Index 3017 */ 3018 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 3019 3020 /* reg_sbcm_min_buff 3021 * Minimum buffer size for the limiter, in cells. 3022 * Access: RW 3023 */ 3024 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 3025 3026 /* reg_sbcm_max_buff 3027 * When the pool associated to the port-pg/tclass is configured to 3028 * static, Maximum buffer size for the limiter configured in cells. 3029 * When the pool associated to the port-pg/tclass is configured to 3030 * dynamic, the max_buff holds the "alpha" parameter, supporting 3031 * the following values: 3032 * 0: 0 3033 * i: (1/128)*2^(i-1), for i=1..14 3034 * 0xFF: Infinity 3035 * Access: RW 3036 */ 3037 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 3038 3039 /* reg_sbcm_pool 3040 * Association of the port-priority to a pool. 3041 * Access: RW 3042 */ 3043 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 3044 3045 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 3046 enum mlxsw_reg_sbcm_dir dir, 3047 u32 min_buff, u32 max_buff, u8 pool) 3048 { 3049 MLXSW_REG_ZERO(sbcm, payload); 3050 mlxsw_reg_sbcm_local_port_set(payload, local_port); 3051 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 3052 mlxsw_reg_sbcm_dir_set(payload, dir); 3053 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 3054 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 3055 mlxsw_reg_sbcm_pool_set(payload, pool); 3056 } 3057 3058 /* SBPM - Shared Buffer Class Management Register 3059 * ---------------------------------------------- 3060 * The SBPM register configures and retrieves the shared buffer allocation 3061 * and configuration according to Port-Pool, including the definition 3062 * of the associated quota. 3063 */ 3064 #define MLXSW_REG_SBPM_ID 0xB003 3065 #define MLXSW_REG_SBPM_LEN 0x28 3066 3067 static const struct mlxsw_reg_info mlxsw_reg_sbpm = { 3068 .id = MLXSW_REG_SBPM_ID, 3069 .len = MLXSW_REG_SBPM_LEN, 3070 }; 3071 3072 /* reg_sbpm_local_port 3073 * Local port number. 3074 * For Ingress: excludes CPU port and Router port 3075 * For Egress: excludes IP Router 3076 * Access: Index 3077 */ 3078 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 3079 3080 /* reg_sbpm_pool 3081 * The pool associated to quota counting on the local_port. 3082 * Access: Index 3083 */ 3084 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 3085 3086 enum mlxsw_reg_sbpm_dir { 3087 MLXSW_REG_SBPM_DIR_INGRESS, 3088 MLXSW_REG_SBPM_DIR_EGRESS, 3089 }; 3090 3091 /* reg_sbpm_dir 3092 * Direction. 3093 * Access: Index 3094 */ 3095 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 3096 3097 /* reg_sbpm_min_buff 3098 * Minimum buffer size for the limiter, in cells. 3099 * Access: RW 3100 */ 3101 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 3102 3103 /* reg_sbpm_max_buff 3104 * When the pool associated to the port-pg/tclass is configured to 3105 * static, Maximum buffer size for the limiter configured in cells. 3106 * When the pool associated to the port-pg/tclass is configured to 3107 * dynamic, the max_buff holds the "alpha" parameter, supporting 3108 * the following values: 3109 * 0: 0 3110 * i: (1/128)*2^(i-1), for i=1..14 3111 * 0xFF: Infinity 3112 * Access: RW 3113 */ 3114 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 3115 3116 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 3117 enum mlxsw_reg_sbpm_dir dir, 3118 u32 min_buff, u32 max_buff) 3119 { 3120 MLXSW_REG_ZERO(sbpm, payload); 3121 mlxsw_reg_sbpm_local_port_set(payload, local_port); 3122 mlxsw_reg_sbpm_pool_set(payload, pool); 3123 mlxsw_reg_sbpm_dir_set(payload, dir); 3124 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 3125 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 3126 } 3127 3128 /* SBMM - Shared Buffer Multicast Management Register 3129 * -------------------------------------------------- 3130 * The SBMM register configures and retrieves the shared buffer allocation 3131 * and configuration for MC packets according to Switch-Priority, including 3132 * the binding to pool and definition of the associated quota. 3133 */ 3134 #define MLXSW_REG_SBMM_ID 0xB004 3135 #define MLXSW_REG_SBMM_LEN 0x28 3136 3137 static const struct mlxsw_reg_info mlxsw_reg_sbmm = { 3138 .id = MLXSW_REG_SBMM_ID, 3139 .len = MLXSW_REG_SBMM_LEN, 3140 }; 3141 3142 /* reg_sbmm_prio 3143 * Switch Priority. 3144 * Access: Index 3145 */ 3146 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 3147 3148 /* reg_sbmm_min_buff 3149 * Minimum buffer size for the limiter, in cells. 3150 * Access: RW 3151 */ 3152 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 3153 3154 /* reg_sbmm_max_buff 3155 * When the pool associated to the port-pg/tclass is configured to 3156 * static, Maximum buffer size for the limiter configured in cells. 3157 * When the pool associated to the port-pg/tclass is configured to 3158 * dynamic, the max_buff holds the "alpha" parameter, supporting 3159 * the following values: 3160 * 0: 0 3161 * i: (1/128)*2^(i-1), for i=1..14 3162 * 0xFF: Infinity 3163 * Access: RW 3164 */ 3165 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 3166 3167 /* reg_sbmm_pool 3168 * Association of the port-priority to a pool. 3169 * Access: RW 3170 */ 3171 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 3172 3173 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 3174 u32 max_buff, u8 pool) 3175 { 3176 MLXSW_REG_ZERO(sbmm, payload); 3177 mlxsw_reg_sbmm_prio_set(payload, prio); 3178 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 3179 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 3180 mlxsw_reg_sbmm_pool_set(payload, pool); 3181 } 3182 3183 static inline const char *mlxsw_reg_id_str(u16 reg_id) 3184 { 3185 switch (reg_id) { 3186 case MLXSW_REG_SGCR_ID: 3187 return "SGCR"; 3188 case MLXSW_REG_SPAD_ID: 3189 return "SPAD"; 3190 case MLXSW_REG_SMID_ID: 3191 return "SMID"; 3192 case MLXSW_REG_SSPR_ID: 3193 return "SSPR"; 3194 case MLXSW_REG_SFDAT_ID: 3195 return "SFDAT"; 3196 case MLXSW_REG_SFD_ID: 3197 return "SFD"; 3198 case MLXSW_REG_SFN_ID: 3199 return "SFN"; 3200 case MLXSW_REG_SPMS_ID: 3201 return "SPMS"; 3202 case MLXSW_REG_SPVID_ID: 3203 return "SPVID"; 3204 case MLXSW_REG_SPVM_ID: 3205 return "SPVM"; 3206 case MLXSW_REG_SFGC_ID: 3207 return "SFGC"; 3208 case MLXSW_REG_SFTR_ID: 3209 return "SFTR"; 3210 case MLXSW_REG_SFDF_ID: 3211 return "SFDF"; 3212 case MLXSW_REG_SLDR_ID: 3213 return "SLDR"; 3214 case MLXSW_REG_SLCR_ID: 3215 return "SLCR"; 3216 case MLXSW_REG_SLCOR_ID: 3217 return "SLCOR"; 3218 case MLXSW_REG_SPMLR_ID: 3219 return "SPMLR"; 3220 case MLXSW_REG_SVFA_ID: 3221 return "SVFA"; 3222 case MLXSW_REG_SVPE_ID: 3223 return "SVPE"; 3224 case MLXSW_REG_SFMR_ID: 3225 return "SFMR"; 3226 case MLXSW_REG_SPVMLR_ID: 3227 return "SPVMLR"; 3228 case MLXSW_REG_PMLP_ID: 3229 return "PMLP"; 3230 case MLXSW_REG_PMTU_ID: 3231 return "PMTU"; 3232 case MLXSW_REG_PTYS_ID: 3233 return "PTYS"; 3234 case MLXSW_REG_PPAD_ID: 3235 return "PPAD"; 3236 case MLXSW_REG_PAOS_ID: 3237 return "PAOS"; 3238 case MLXSW_REG_PPCNT_ID: 3239 return "PPCNT"; 3240 case MLXSW_REG_PBMC_ID: 3241 return "PBMC"; 3242 case MLXSW_REG_PSPA_ID: 3243 return "PSPA"; 3244 case MLXSW_REG_HTGT_ID: 3245 return "HTGT"; 3246 case MLXSW_REG_HPKT_ID: 3247 return "HPKT"; 3248 case MLXSW_REG_MFCR_ID: 3249 return "MFCR"; 3250 case MLXSW_REG_MFSC_ID: 3251 return "MFSC"; 3252 case MLXSW_REG_MFSM_ID: 3253 return "MFSM"; 3254 case MLXSW_REG_MTCAP_ID: 3255 return "MTCAP"; 3256 case MLXSW_REG_MTMP_ID: 3257 return "MTMP"; 3258 case MLXSW_REG_MLCR_ID: 3259 return "MLCR"; 3260 case MLXSW_REG_SBPR_ID: 3261 return "SBPR"; 3262 case MLXSW_REG_SBCM_ID: 3263 return "SBCM"; 3264 case MLXSW_REG_SBPM_ID: 3265 return "SBPM"; 3266 case MLXSW_REG_SBMM_ID: 3267 return "SBMM"; 3268 default: 3269 return "*UNKNOWN*"; 3270 } 3271 } 3272 3273 /* PUDE - Port Up / Down Event 3274 * --------------------------- 3275 * Reports the operational state change of a port. 3276 */ 3277 #define MLXSW_REG_PUDE_LEN 0x10 3278 3279 /* reg_pude_swid 3280 * Switch partition ID with which to associate the port. 3281 * Access: Index 3282 */ 3283 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 3284 3285 /* reg_pude_local_port 3286 * Local port number. 3287 * Access: Index 3288 */ 3289 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 3290 3291 /* reg_pude_admin_status 3292 * Port administrative state (the desired state). 3293 * 1 - Up. 3294 * 2 - Down. 3295 * 3 - Up once. This means that in case of link failure, the port won't go 3296 * into polling mode, but will wait to be re-enabled by software. 3297 * 4 - Disabled by system. Can only be set by hardware. 3298 * Access: RO 3299 */ 3300 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 3301 3302 /* reg_pude_oper_status 3303 * Port operatioanl state. 3304 * 1 - Up. 3305 * 2 - Down. 3306 * 3 - Down by port failure. This means that the device will not let the 3307 * port up again until explicitly specified by software. 3308 * Access: RO 3309 */ 3310 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 3311 3312 #endif 3313