1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 1); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_acl_id 2203 * ACL identifier 2204 * Access: RW 2205 */ 2206 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2207 2208 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2209 { 2210 MLXSW_REG_ZERO(pagt, payload); 2211 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2212 } 2213 2214 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2215 u16 acl_id) 2216 { 2217 u8 size = mlxsw_reg_pagt_size_get(payload); 2218 2219 if (index >= size) 2220 mlxsw_reg_pagt_size_set(payload, index + 1); 2221 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2222 } 2223 2224 /* PTAR - Policy-Engine TCAM Allocation Register 2225 * --------------------------------------------- 2226 * This register is used for allocation of regions in the TCAM. 2227 * Note: Query method is not supported on this register. 2228 */ 2229 #define MLXSW_REG_PTAR_ID 0x3006 2230 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2231 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2232 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2233 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2234 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2235 2236 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2237 2238 enum mlxsw_reg_ptar_op { 2239 /* allocate a TCAM region */ 2240 MLXSW_REG_PTAR_OP_ALLOC, 2241 /* resize a TCAM region */ 2242 MLXSW_REG_PTAR_OP_RESIZE, 2243 /* deallocate TCAM region */ 2244 MLXSW_REG_PTAR_OP_FREE, 2245 /* test allocation */ 2246 MLXSW_REG_PTAR_OP_TEST, 2247 }; 2248 2249 /* reg_ptar_op 2250 * Access: OP 2251 */ 2252 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2253 2254 /* reg_ptar_action_set_type 2255 * Type of action set to be used on this region. 2256 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2257 * Access: WO 2258 */ 2259 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2260 2261 enum mlxsw_reg_ptar_key_type { 2262 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2263 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2264 }; 2265 2266 /* reg_ptar_key_type 2267 * TCAM key type for the region. 2268 * Access: WO 2269 */ 2270 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2271 2272 /* reg_ptar_region_size 2273 * TCAM region size. When allocating/resizing this is the requested size, 2274 * the response is the actual size. Note that actual size may be 2275 * larger than requested. 2276 * Allowed range 1 .. cap_max_rules-1 2277 * Reserved during op deallocate. 2278 * Access: WO 2279 */ 2280 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2281 2282 /* reg_ptar_region_id 2283 * Region identifier 2284 * Range 0 .. cap_max_regions-1 2285 * Access: Index 2286 */ 2287 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2288 2289 /* reg_ptar_tcam_region_info 2290 * Opaque object that represents the TCAM region. 2291 * Returned when allocating a region. 2292 * Provided by software for ACL generation and region deallocation and resize. 2293 * Access: RW 2294 */ 2295 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2296 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2297 2298 /* reg_ptar_flexible_key_id 2299 * Identifier of the Flexible Key. 2300 * Only valid if key_type == "FLEX_KEY" 2301 * The key size will be rounded up to one of the following values: 2302 * 9B, 18B, 36B, 54B. 2303 * This field is reserved for in resize operation. 2304 * Access: WO 2305 */ 2306 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2307 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2308 2309 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2310 enum mlxsw_reg_ptar_key_type key_type, 2311 u16 region_size, u16 region_id, 2312 const char *tcam_region_info) 2313 { 2314 MLXSW_REG_ZERO(ptar, payload); 2315 mlxsw_reg_ptar_op_set(payload, op); 2316 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2317 mlxsw_reg_ptar_key_type_set(payload, key_type); 2318 mlxsw_reg_ptar_region_size_set(payload, region_size); 2319 mlxsw_reg_ptar_region_id_set(payload, region_id); 2320 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2321 } 2322 2323 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2324 u16 key_id) 2325 { 2326 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2327 } 2328 2329 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2330 { 2331 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2332 } 2333 2334 /* PPBS - Policy-Engine Policy Based Switching Register 2335 * ---------------------------------------------------- 2336 * This register retrieves and sets Policy Based Switching Table entries. 2337 */ 2338 #define MLXSW_REG_PPBS_ID 0x300C 2339 #define MLXSW_REG_PPBS_LEN 0x14 2340 2341 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2342 2343 /* reg_ppbs_pbs_ptr 2344 * Index into the PBS table. 2345 * For Spectrum, the index points to the KVD Linear. 2346 * Access: Index 2347 */ 2348 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2349 2350 /* reg_ppbs_system_port 2351 * Unique port identifier for the final destination of the packet. 2352 * Access: RW 2353 */ 2354 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2355 2356 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2357 u16 system_port) 2358 { 2359 MLXSW_REG_ZERO(ppbs, payload); 2360 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2361 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2362 } 2363 2364 /* PRCR - Policy-Engine Rules Copy Register 2365 * ---------------------------------------- 2366 * This register is used for accessing rules within a TCAM region. 2367 */ 2368 #define MLXSW_REG_PRCR_ID 0x300D 2369 #define MLXSW_REG_PRCR_LEN 0x40 2370 2371 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2372 2373 enum mlxsw_reg_prcr_op { 2374 /* Move rules. Moves the rules from "tcam_region_info" starting 2375 * at offset "offset" to "dest_tcam_region_info" 2376 * at offset "dest_offset." 2377 */ 2378 MLXSW_REG_PRCR_OP_MOVE, 2379 /* Copy rules. Copies the rules from "tcam_region_info" starting 2380 * at offset "offset" to "dest_tcam_region_info" 2381 * at offset "dest_offset." 2382 */ 2383 MLXSW_REG_PRCR_OP_COPY, 2384 }; 2385 2386 /* reg_prcr_op 2387 * Access: OP 2388 */ 2389 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2390 2391 /* reg_prcr_offset 2392 * Offset within the source region to copy/move from. 2393 * Access: Index 2394 */ 2395 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2396 2397 /* reg_prcr_size 2398 * The number of rules to copy/move. 2399 * Access: WO 2400 */ 2401 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2402 2403 /* reg_prcr_tcam_region_info 2404 * Opaque object that represents the source TCAM region. 2405 * Access: Index 2406 */ 2407 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2408 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2409 2410 /* reg_prcr_dest_offset 2411 * Offset within the source region to copy/move to. 2412 * Access: Index 2413 */ 2414 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2415 2416 /* reg_prcr_dest_tcam_region_info 2417 * Opaque object that represents the destination TCAM region. 2418 * Access: Index 2419 */ 2420 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2421 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2422 2423 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2424 const char *src_tcam_region_info, 2425 u16 src_offset, 2426 const char *dest_tcam_region_info, 2427 u16 dest_offset, u16 size) 2428 { 2429 MLXSW_REG_ZERO(prcr, payload); 2430 mlxsw_reg_prcr_op_set(payload, op); 2431 mlxsw_reg_prcr_offset_set(payload, src_offset); 2432 mlxsw_reg_prcr_size_set(payload, size); 2433 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2434 src_tcam_region_info); 2435 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2436 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2437 dest_tcam_region_info); 2438 } 2439 2440 /* PEFA - Policy-Engine Extended Flexible Action Register 2441 * ------------------------------------------------------ 2442 * This register is used for accessing an extended flexible action entry 2443 * in the central KVD Linear Database. 2444 */ 2445 #define MLXSW_REG_PEFA_ID 0x300F 2446 #define MLXSW_REG_PEFA_LEN 0xB0 2447 2448 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2449 2450 /* reg_pefa_index 2451 * Index in the KVD Linear Centralized Database. 2452 * Access: Index 2453 */ 2454 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2455 2456 /* reg_pefa_a 2457 * Index in the KVD Linear Centralized Database. 2458 * Activity 2459 * For a new entry: set if ca=0, clear if ca=1 2460 * Set if a packet lookup has hit on the specific entry 2461 * Access: RO 2462 */ 2463 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2464 2465 /* reg_pefa_ca 2466 * Clear activity 2467 * When write: activity is according to this field 2468 * When read: after reading the activity is cleared according to ca 2469 * Access: OP 2470 */ 2471 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2472 2473 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2474 2475 /* reg_pefa_flex_action_set 2476 * Action-set to perform when rule is matched. 2477 * Must be zero padded if action set is shorter. 2478 * Access: RW 2479 */ 2480 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2481 2482 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2483 const char *flex_action_set) 2484 { 2485 MLXSW_REG_ZERO(pefa, payload); 2486 mlxsw_reg_pefa_index_set(payload, index); 2487 mlxsw_reg_pefa_ca_set(payload, ca); 2488 if (flex_action_set) 2489 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2490 flex_action_set); 2491 } 2492 2493 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2494 { 2495 *p_a = mlxsw_reg_pefa_a_get(payload); 2496 } 2497 2498 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2499 * ----------------------------------------------------- 2500 * This register is used for accessing rules within a TCAM region. 2501 * It is a new version of PTCE in order to support wider key, 2502 * mask and action within a TCAM region. This register is not supported 2503 * by SwitchX and SwitchX-2. 2504 */ 2505 #define MLXSW_REG_PTCE2_ID 0x3017 2506 #define MLXSW_REG_PTCE2_LEN 0x1D8 2507 2508 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2509 2510 /* reg_ptce2_v 2511 * Valid. 2512 * Access: RW 2513 */ 2514 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2515 2516 /* reg_ptce2_a 2517 * Activity. Set if a packet lookup has hit on the specific entry. 2518 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2519 * Access: RO 2520 */ 2521 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2522 2523 enum mlxsw_reg_ptce2_op { 2524 /* Read operation. */ 2525 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2526 /* clear on read operation. Used to read entry 2527 * and clear Activity bit. 2528 */ 2529 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2530 /* Write operation. Used to write a new entry to the table. 2531 * All R/W fields are relevant for new entry. Activity bit is set 2532 * for new entries - Note write with v = 0 will delete the entry. 2533 */ 2534 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2535 /* Update action. Only action set will be updated. */ 2536 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2537 /* Clear activity. A bit is cleared for the entry. */ 2538 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2539 }; 2540 2541 /* reg_ptce2_op 2542 * Access: OP 2543 */ 2544 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2545 2546 /* reg_ptce2_offset 2547 * Access: Index 2548 */ 2549 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2550 2551 /* reg_ptce2_priority 2552 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2553 * Note: priority does not have to be unique per rule. 2554 * Within a region, higher priority should have lower offset (no limitation 2555 * between regions in a multi-region). 2556 * Access: RW 2557 */ 2558 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2559 2560 /* reg_ptce2_tcam_region_info 2561 * Opaque object that represents the TCAM region. 2562 * Access: Index 2563 */ 2564 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2565 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2566 2567 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2568 2569 /* reg_ptce2_flex_key_blocks 2570 * ACL Key. 2571 * Access: RW 2572 */ 2573 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2574 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2575 2576 /* reg_ptce2_mask 2577 * mask- in the same size as key. A bit that is set directs the TCAM 2578 * to compare the corresponding bit in key. A bit that is clear directs 2579 * the TCAM to ignore the corresponding bit in key. 2580 * Access: RW 2581 */ 2582 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2583 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2584 2585 /* reg_ptce2_flex_action_set 2586 * ACL action set. 2587 * Access: RW 2588 */ 2589 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2590 MLXSW_REG_FLEX_ACTION_SET_LEN); 2591 2592 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2593 enum mlxsw_reg_ptce2_op op, 2594 const char *tcam_region_info, 2595 u16 offset, u32 priority) 2596 { 2597 MLXSW_REG_ZERO(ptce2, payload); 2598 mlxsw_reg_ptce2_v_set(payload, valid); 2599 mlxsw_reg_ptce2_op_set(payload, op); 2600 mlxsw_reg_ptce2_offset_set(payload, offset); 2601 mlxsw_reg_ptce2_priority_set(payload, priority); 2602 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2603 } 2604 2605 /* PERPT - Policy-Engine ERP Table Register 2606 * ---------------------------------------- 2607 * This register adds and removes eRPs from the eRP table. 2608 */ 2609 #define MLXSW_REG_PERPT_ID 0x3021 2610 #define MLXSW_REG_PERPT_LEN 0x80 2611 2612 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2613 2614 /* reg_perpt_erpt_bank 2615 * eRP table bank. 2616 * Range 0 .. cap_max_erp_table_banks - 1 2617 * Access: Index 2618 */ 2619 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2620 2621 /* reg_perpt_erpt_index 2622 * Index to eRP table within the eRP bank. 2623 * Range is 0 .. cap_max_erp_table_bank_size - 1 2624 * Access: Index 2625 */ 2626 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2627 2628 enum mlxsw_reg_perpt_key_size { 2629 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2630 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2631 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2632 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2633 }; 2634 2635 /* reg_perpt_key_size 2636 * Access: OP 2637 */ 2638 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2639 2640 /* reg_perpt_bf_bypass 2641 * 0 - The eRP is used only if bloom filter state is set for the given 2642 * rule. 2643 * 1 - The eRP is used regardless of bloom filter state. 2644 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2645 * Access: RW 2646 */ 2647 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2648 2649 /* reg_perpt_erp_id 2650 * eRP ID for use by the rules. 2651 * Access: RW 2652 */ 2653 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2654 2655 /* reg_perpt_erpt_base_bank 2656 * Base eRP table bank, points to head of erp_vector 2657 * Range is 0 .. cap_max_erp_table_banks - 1 2658 * Access: OP 2659 */ 2660 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2661 2662 /* reg_perpt_erpt_base_index 2663 * Base index to eRP table within the eRP bank 2664 * Range is 0 .. cap_max_erp_table_bank_size - 1 2665 * Access: OP 2666 */ 2667 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2668 2669 /* reg_perpt_erp_index_in_vector 2670 * eRP index in the vector. 2671 * Access: OP 2672 */ 2673 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2674 2675 /* reg_perpt_erp_vector 2676 * eRP vector. 2677 * Access: OP 2678 */ 2679 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2680 2681 /* reg_perpt_mask 2682 * Mask 2683 * 0 - A-TCAM will ignore the bit in key 2684 * 1 - A-TCAM will compare the bit in key 2685 * Access: RW 2686 */ 2687 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2688 2689 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2690 unsigned long *erp_vector, 2691 unsigned long size) 2692 { 2693 unsigned long bit; 2694 2695 for_each_set_bit(bit, erp_vector, size) 2696 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2697 } 2698 2699 static inline void 2700 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2701 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2702 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2703 char *mask) 2704 { 2705 MLXSW_REG_ZERO(perpt, payload); 2706 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2707 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2708 mlxsw_reg_perpt_key_size_set(payload, key_size); 2709 mlxsw_reg_perpt_bf_bypass_set(payload, true); 2710 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2711 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2712 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2713 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2714 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2715 } 2716 2717 /* PERAR - Policy-Engine Region Association Register 2718 * ------------------------------------------------- 2719 * This register associates a hw region for region_id's. Changing on the fly 2720 * is supported by the device. 2721 */ 2722 #define MLXSW_REG_PERAR_ID 0x3026 2723 #define MLXSW_REG_PERAR_LEN 0x08 2724 2725 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2726 2727 /* reg_perar_region_id 2728 * Region identifier 2729 * Range 0 .. cap_max_regions-1 2730 * Access: Index 2731 */ 2732 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2733 2734 static inline unsigned int 2735 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2736 { 2737 return DIV_ROUND_UP(block_num, 4); 2738 } 2739 2740 /* reg_perar_hw_region 2741 * HW Region 2742 * Range 0 .. cap_max_regions-1 2743 * Default: hw_region = region_id 2744 * For a 8 key block region, 2 consecutive regions are used 2745 * For a 12 key block region, 3 consecutive regions are used 2746 * Access: RW 2747 */ 2748 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2749 2750 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2751 u16 hw_region) 2752 { 2753 MLXSW_REG_ZERO(perar, payload); 2754 mlxsw_reg_perar_region_id_set(payload, region_id); 2755 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2756 } 2757 2758 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2759 * ----------------------------------------------------- 2760 * This register is a new version of PTCE-V2 in order to support the 2761 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2762 */ 2763 #define MLXSW_REG_PTCE3_ID 0x3027 2764 #define MLXSW_REG_PTCE3_LEN 0xF0 2765 2766 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2767 2768 /* reg_ptce3_v 2769 * Valid. 2770 * Access: RW 2771 */ 2772 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2773 2774 enum mlxsw_reg_ptce3_op { 2775 /* Write operation. Used to write a new entry to the table. 2776 * All R/W fields are relevant for new entry. Activity bit is set 2777 * for new entries. Write with v = 0 will delete the entry. Must 2778 * not be used if an entry exists. 2779 */ 2780 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2781 /* Update operation */ 2782 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2783 /* Read operation */ 2784 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2785 }; 2786 2787 /* reg_ptce3_op 2788 * Access: OP 2789 */ 2790 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2791 2792 /* reg_ptce3_priority 2793 * Priority of the rule. Higher values win. 2794 * For Spectrum-2 range is 1..cap_kvd_size - 1 2795 * Note: Priority does not have to be unique per rule. 2796 * Access: RW 2797 */ 2798 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2799 2800 /* reg_ptce3_tcam_region_info 2801 * Opaque object that represents the TCAM region. 2802 * Access: Index 2803 */ 2804 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2805 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2806 2807 /* reg_ptce3_flex2_key_blocks 2808 * ACL key. The key must be masked according to eRP (if exists) or 2809 * according to master mask. 2810 * Access: Index 2811 */ 2812 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2813 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2814 2815 /* reg_ptce3_erp_id 2816 * eRP ID. 2817 * Access: Index 2818 */ 2819 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2820 2821 /* reg_ptce3_delta_start 2822 * Start point of delta_value and delta_mask, in bits. Must not exceed 2823 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2824 * Access: Index 2825 */ 2826 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2827 2828 /* reg_ptce3_delta_mask 2829 * Delta mask. 2830 * 0 - Ignore relevant bit in delta_value 2831 * 1 - Compare relevant bit in delta_value 2832 * Delta mask must not be set for reserved fields in the key blocks. 2833 * Note: No delta when no eRPs. Thus, for regions with 2834 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2835 * Access: Index 2836 */ 2837 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2838 2839 /* reg_ptce3_delta_value 2840 * Delta value. 2841 * Bits which are masked by delta_mask must be 0. 2842 * Access: Index 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2845 2846 /* reg_ptce3_prune_vector 2847 * Pruning vector relative to the PERPT.erp_id. 2848 * Used for reducing lookups. 2849 * 0 - NEED: Do a lookup using the eRP. 2850 * 1 - PRUNE: Do not perform a lookup using the eRP. 2851 * Maybe be modified by PEAPBL and PEAPBM. 2852 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2853 * all 1's or all 0's. 2854 * Access: RW 2855 */ 2856 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2857 2858 /* reg_ptce3_prune_ctcam 2859 * Pruning on C-TCAM. Used for reducing lookups. 2860 * 0 - NEED: Do a lookup in the C-TCAM. 2861 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2862 * Access: RW 2863 */ 2864 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2865 2866 /* reg_ptce3_large_exists 2867 * Large entry key ID exists. 2868 * Within the region: 2869 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2870 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2871 * For rule delete: The MSB of the key will be removed. 2872 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2873 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2874 * For rule delete: The MSB of the key will not be removed. 2875 * Access: WO 2876 */ 2877 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2878 2879 /* reg_ptce3_large_entry_key_id 2880 * Large entry key ID. 2881 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2882 * blocks. Must be different for different keys which have the same common 2883 * 6 key blocks (MSB, blocks 6..11) key within a region. 2884 * Range is 0..cap_max_pe_large_key_id - 1 2885 * Access: RW 2886 */ 2887 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2888 2889 /* reg_ptce3_action_pointer 2890 * Pointer to action. 2891 * Range is 0..cap_max_kvd_action_sets - 1 2892 * Access: RW 2893 */ 2894 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2895 2896 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2897 enum mlxsw_reg_ptce3_op op, 2898 u32 priority, 2899 const char *tcam_region_info, 2900 const char *key, u8 erp_id, 2901 u16 delta_start, u8 delta_mask, 2902 u8 delta_value, bool large_exists, 2903 u32 lkey_id, u32 action_pointer) 2904 { 2905 MLXSW_REG_ZERO(ptce3, payload); 2906 mlxsw_reg_ptce3_v_set(payload, valid); 2907 mlxsw_reg_ptce3_op_set(payload, op); 2908 mlxsw_reg_ptce3_priority_set(payload, priority); 2909 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2910 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2911 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2912 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2913 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2914 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2915 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2916 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2917 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2918 } 2919 2920 /* PERCR - Policy-Engine Region Configuration Register 2921 * --------------------------------------------------- 2922 * This register configures the region parameters. The region_id must be 2923 * allocated. 2924 */ 2925 #define MLXSW_REG_PERCR_ID 0x302A 2926 #define MLXSW_REG_PERCR_LEN 0x80 2927 2928 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2929 2930 /* reg_percr_region_id 2931 * Region identifier. 2932 * Range 0..cap_max_regions-1 2933 * Access: Index 2934 */ 2935 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2936 2937 /* reg_percr_atcam_ignore_prune 2938 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2939 * Access: RW 2940 */ 2941 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2942 2943 /* reg_percr_ctcam_ignore_prune 2944 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2945 * Access: RW 2946 */ 2947 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2948 2949 /* reg_percr_bf_bypass 2950 * Bloom filter bypass. 2951 * 0 - Bloom filter is used (default) 2952 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2953 * region_id or eRP. See PERPT.bf_bypass 2954 * Access: RW 2955 */ 2956 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 2957 2958 /* reg_percr_master_mask 2959 * Master mask. Logical OR mask of all masks of all rules of a region 2960 * (both A-TCAM and C-TCAM). When there are no eRPs 2961 * (erpt_pointer_valid = 0), then this provides the mask. 2962 * Access: RW 2963 */ 2964 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 2965 2966 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 2967 { 2968 MLXSW_REG_ZERO(percr, payload); 2969 mlxsw_reg_percr_region_id_set(payload, region_id); 2970 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 2971 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 2972 mlxsw_reg_percr_bf_bypass_set(payload, true); 2973 } 2974 2975 /* PERERP - Policy-Engine Region eRP Register 2976 * ------------------------------------------ 2977 * This register configures the region eRP. The region_id must be 2978 * allocated. 2979 */ 2980 #define MLXSW_REG_PERERP_ID 0x302B 2981 #define MLXSW_REG_PERERP_LEN 0x1C 2982 2983 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 2984 2985 /* reg_pererp_region_id 2986 * Region identifier. 2987 * Range 0..cap_max_regions-1 2988 * Access: Index 2989 */ 2990 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 2991 2992 /* reg_pererp_ctcam_le 2993 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 2994 * Access: RW 2995 */ 2996 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 2997 2998 /* reg_pererp_erpt_pointer_valid 2999 * erpt_pointer is valid. 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3003 3004 /* reg_pererp_erpt_bank_pointer 3005 * Pointer to eRP table bank. May be modified at any time. 3006 * Range 0..cap_max_erp_table_banks-1 3007 * Reserved when erpt_pointer_valid = 0 3008 */ 3009 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3010 3011 /* reg_pererp_erpt_pointer 3012 * Pointer to eRP table within the eRP bank. Can be changed for an 3013 * existing region. 3014 * Range 0..cap_max_erp_table_size-1 3015 * Reserved when erpt_pointer_valid = 0 3016 * Access: RW 3017 */ 3018 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3019 3020 /* reg_pererp_erpt_vector 3021 * Vector of allowed eRP indexes starting from erpt_pointer within the 3022 * erpt_bank_pointer. Next entries will be in next bank. 3023 * Note that eRP index is used and not eRP ID. 3024 * Reserved when erpt_pointer_valid = 0 3025 * Access: RW 3026 */ 3027 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3028 3029 /* reg_pererp_master_rp_id 3030 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3031 * for the lookup. Can be changed for an existing region. 3032 * Reserved when erpt_pointer_valid = 1 3033 * Access: RW 3034 */ 3035 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3036 3037 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3038 unsigned long *erp_vector, 3039 unsigned long size) 3040 { 3041 unsigned long bit; 3042 3043 for_each_set_bit(bit, erp_vector, size) 3044 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3045 } 3046 3047 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3048 bool ctcam_le, bool erpt_pointer_valid, 3049 u8 erpt_bank_pointer, u8 erpt_pointer, 3050 u8 master_rp_id) 3051 { 3052 MLXSW_REG_ZERO(pererp, payload); 3053 mlxsw_reg_pererp_region_id_set(payload, region_id); 3054 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3055 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3056 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3057 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3058 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3059 } 3060 3061 /* IEDR - Infrastructure Entry Delete Register 3062 * ---------------------------------------------------- 3063 * This register is used for deleting entries from the entry tables. 3064 * It is legitimate to attempt to delete a nonexisting entry (the device will 3065 * respond as a good flow). 3066 */ 3067 #define MLXSW_REG_IEDR_ID 0x3804 3068 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3069 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3070 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3071 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3072 MLXSW_REG_IEDR_REC_LEN * \ 3073 MLXSW_REG_IEDR_REC_MAX_COUNT) 3074 3075 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3076 3077 /* reg_iedr_num_rec 3078 * Number of records. 3079 * Access: OP 3080 */ 3081 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3082 3083 /* reg_iedr_rec_type 3084 * Resource type. 3085 * Access: OP 3086 */ 3087 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3088 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3089 3090 /* reg_iedr_rec_size 3091 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3092 * Access: OP 3093 */ 3094 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3095 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3096 3097 /* reg_iedr_rec_index_start 3098 * Resource index start. 3099 * Access: OP 3100 */ 3101 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3102 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3103 3104 static inline void mlxsw_reg_iedr_pack(char *payload) 3105 { 3106 MLXSW_REG_ZERO(iedr, payload); 3107 } 3108 3109 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3110 u8 rec_type, u16 rec_size, 3111 u32 rec_index_start) 3112 { 3113 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3114 3115 if (rec_index >= num_rec) 3116 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3117 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3118 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3119 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3120 } 3121 3122 /* QPTS - QoS Priority Trust State Register 3123 * ---------------------------------------- 3124 * This register controls the port policy to calculate the switch priority and 3125 * packet color based on incoming packet fields. 3126 */ 3127 #define MLXSW_REG_QPTS_ID 0x4002 3128 #define MLXSW_REG_QPTS_LEN 0x8 3129 3130 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3131 3132 /* reg_qpts_local_port 3133 * Local port number. 3134 * Access: Index 3135 * 3136 * Note: CPU port is supported. 3137 */ 3138 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3139 3140 enum mlxsw_reg_qpts_trust_state { 3141 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3142 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3143 }; 3144 3145 /* reg_qpts_trust_state 3146 * Trust state for a given port. 3147 * Access: RW 3148 */ 3149 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3150 3151 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3152 enum mlxsw_reg_qpts_trust_state ts) 3153 { 3154 MLXSW_REG_ZERO(qpts, payload); 3155 3156 mlxsw_reg_qpts_local_port_set(payload, local_port); 3157 mlxsw_reg_qpts_trust_state_set(payload, ts); 3158 } 3159 3160 /* QPCR - QoS Policer Configuration Register 3161 * ----------------------------------------- 3162 * The QPCR register is used to create policers - that limit 3163 * the rate of bytes or packets via some trap group. 3164 */ 3165 #define MLXSW_REG_QPCR_ID 0x4004 3166 #define MLXSW_REG_QPCR_LEN 0x28 3167 3168 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3169 3170 enum mlxsw_reg_qpcr_g { 3171 MLXSW_REG_QPCR_G_GLOBAL = 2, 3172 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3173 }; 3174 3175 /* reg_qpcr_g 3176 * The policer type. 3177 * Access: Index 3178 */ 3179 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3180 3181 /* reg_qpcr_pid 3182 * Policer ID. 3183 * Access: Index 3184 */ 3185 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3186 3187 /* reg_qpcr_color_aware 3188 * Is the policer aware of colors. 3189 * Must be 0 (unaware) for cpu port. 3190 * Access: RW for unbounded policer. RO for bounded policer. 3191 */ 3192 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3193 3194 /* reg_qpcr_bytes 3195 * Is policer limit is for bytes per sec or packets per sec. 3196 * 0 - packets 3197 * 1 - bytes 3198 * Access: RW for unbounded policer. RO for bounded policer. 3199 */ 3200 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3201 3202 enum mlxsw_reg_qpcr_ir_units { 3203 MLXSW_REG_QPCR_IR_UNITS_M, 3204 MLXSW_REG_QPCR_IR_UNITS_K, 3205 }; 3206 3207 /* reg_qpcr_ir_units 3208 * Policer's units for cir and eir fields (for bytes limits only) 3209 * 1 - 10^3 3210 * 0 - 10^6 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3214 3215 enum mlxsw_reg_qpcr_rate_type { 3216 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3217 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3218 }; 3219 3220 /* reg_qpcr_rate_type 3221 * Policer can have one limit (single rate) or 2 limits with specific operation 3222 * for packets that exceed the lower rate but not the upper one. 3223 * (For cpu port must be single rate) 3224 * Access: RW for unbounded policer. RO for bounded policer. 3225 */ 3226 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3227 3228 /* reg_qpc_cbs 3229 * Policer's committed burst size. 3230 * The policer is working with time slices of 50 nano sec. By default every 3231 * slice is granted the proportionate share of the committed rate. If we want to 3232 * allow a slice to exceed that share (while still keeping the rate per sec) we 3233 * can allow burst. The burst size is between the default proportionate share 3234 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3235 * committed rate will result in exceeding the rate). The burst size must be a 3236 * log of 2 and will be determined by 2^cbs. 3237 * Access: RW 3238 */ 3239 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3240 3241 /* reg_qpcr_cir 3242 * Policer's committed rate. 3243 * The rate used for sungle rate, the lower rate for double rate. 3244 * For bytes limits, the rate will be this value * the unit from ir_units. 3245 * (Resolution error is up to 1%). 3246 * Access: RW 3247 */ 3248 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3249 3250 /* reg_qpcr_eir 3251 * Policer's exceed rate. 3252 * The higher rate for double rate, reserved for single rate. 3253 * Lower rate for double rate policer. 3254 * For bytes limits, the rate will be this value * the unit from ir_units. 3255 * (Resolution error is up to 1%). 3256 * Access: RW 3257 */ 3258 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3259 3260 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3261 3262 /* reg_qpcr_exceed_action. 3263 * What to do with packets between the 2 limits for double rate. 3264 * Access: RW for unbounded policer. RO for bounded policer. 3265 */ 3266 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3267 3268 enum mlxsw_reg_qpcr_action { 3269 /* Discard */ 3270 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3271 /* Forward and set color to red. 3272 * If the packet is intended to cpu port, it will be dropped. 3273 */ 3274 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3275 }; 3276 3277 /* reg_qpcr_violate_action 3278 * What to do with packets that cross the cir limit (for single rate) or the eir 3279 * limit (for double rate). 3280 * Access: RW for unbounded policer. RO for bounded policer. 3281 */ 3282 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3283 3284 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3285 enum mlxsw_reg_qpcr_ir_units ir_units, 3286 bool bytes, u32 cir, u16 cbs) 3287 { 3288 MLXSW_REG_ZERO(qpcr, payload); 3289 mlxsw_reg_qpcr_pid_set(payload, pid); 3290 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3291 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3292 mlxsw_reg_qpcr_violate_action_set(payload, 3293 MLXSW_REG_QPCR_ACTION_DISCARD); 3294 mlxsw_reg_qpcr_cir_set(payload, cir); 3295 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3296 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3297 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3298 } 3299 3300 /* QTCT - QoS Switch Traffic Class Table 3301 * ------------------------------------- 3302 * Configures the mapping between the packet switch priority and the 3303 * traffic class on the transmit port. 3304 */ 3305 #define MLXSW_REG_QTCT_ID 0x400A 3306 #define MLXSW_REG_QTCT_LEN 0x08 3307 3308 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3309 3310 /* reg_qtct_local_port 3311 * Local port number. 3312 * Access: Index 3313 * 3314 * Note: CPU port is not supported. 3315 */ 3316 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3317 3318 /* reg_qtct_sub_port 3319 * Virtual port within the physical port. 3320 * Should be set to 0 when virtual ports are not enabled on the port. 3321 * Access: Index 3322 */ 3323 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3324 3325 /* reg_qtct_switch_prio 3326 * Switch priority. 3327 * Access: Index 3328 */ 3329 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3330 3331 /* reg_qtct_tclass 3332 * Traffic class. 3333 * Default values: 3334 * switch_prio 0 : tclass 1 3335 * switch_prio 1 : tclass 0 3336 * switch_prio i : tclass i, for i > 1 3337 * Access: RW 3338 */ 3339 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3340 3341 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3342 u8 switch_prio, u8 tclass) 3343 { 3344 MLXSW_REG_ZERO(qtct, payload); 3345 mlxsw_reg_qtct_local_port_set(payload, local_port); 3346 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3347 mlxsw_reg_qtct_tclass_set(payload, tclass); 3348 } 3349 3350 /* QEEC - QoS ETS Element Configuration Register 3351 * --------------------------------------------- 3352 * Configures the ETS elements. 3353 */ 3354 #define MLXSW_REG_QEEC_ID 0x400D 3355 #define MLXSW_REG_QEEC_LEN 0x20 3356 3357 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3358 3359 /* reg_qeec_local_port 3360 * Local port number. 3361 * Access: Index 3362 * 3363 * Note: CPU port is supported. 3364 */ 3365 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3366 3367 enum mlxsw_reg_qeec_hr { 3368 MLXSW_REG_QEEC_HIERARCY_PORT, 3369 MLXSW_REG_QEEC_HIERARCY_GROUP, 3370 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3371 MLXSW_REG_QEEC_HIERARCY_TC, 3372 }; 3373 3374 /* reg_qeec_element_hierarchy 3375 * 0 - Port 3376 * 1 - Group 3377 * 2 - Subgroup 3378 * 3 - Traffic Class 3379 * Access: Index 3380 */ 3381 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3382 3383 /* reg_qeec_element_index 3384 * The index of the element in the hierarchy. 3385 * Access: Index 3386 */ 3387 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3388 3389 /* reg_qeec_next_element_index 3390 * The index of the next (lower) element in the hierarchy. 3391 * Access: RW 3392 * 3393 * Note: Reserved for element_hierarchy 0. 3394 */ 3395 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3396 3397 /* reg_qeec_mise 3398 * Min shaper configuration enable. Enables configuration of the min 3399 * shaper on this ETS element 3400 * 0 - Disable 3401 * 1 - Enable 3402 * Access: RW 3403 */ 3404 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3405 3406 enum { 3407 MLXSW_REG_QEEC_BYTES_MODE, 3408 MLXSW_REG_QEEC_PACKETS_MODE, 3409 }; 3410 3411 /* reg_qeec_pb 3412 * Packets or bytes mode. 3413 * 0 - Bytes mode 3414 * 1 - Packets mode 3415 * Access: RW 3416 * 3417 * Note: Used for max shaper configuration. For Spectrum, packets mode 3418 * is supported only for traffic classes of CPU port. 3419 */ 3420 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3421 3422 /* The smallest permitted min shaper rate. */ 3423 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3424 3425 /* reg_qeec_min_shaper_rate 3426 * Min shaper information rate. 3427 * For CPU port, can only be configured for port hierarchy. 3428 * When in bytes mode, value is specified in units of 1000bps. 3429 * Access: RW 3430 */ 3431 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3432 3433 /* reg_qeec_mase 3434 * Max shaper configuration enable. Enables configuration of the max 3435 * shaper on this ETS element. 3436 * 0 - Disable 3437 * 1 - Enable 3438 * Access: RW 3439 */ 3440 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3441 3442 /* A large max rate will disable the max shaper. */ 3443 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3444 3445 /* reg_qeec_max_shaper_rate 3446 * Max shaper information rate. 3447 * For CPU port, can only be configured for port hierarchy. 3448 * When in bytes mode, value is specified in units of 1000bps. 3449 * Access: RW 3450 */ 3451 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3452 3453 /* reg_qeec_de 3454 * DWRR configuration enable. Enables configuration of the dwrr and 3455 * dwrr_weight. 3456 * 0 - Disable 3457 * 1 - Enable 3458 * Access: RW 3459 */ 3460 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3461 3462 /* reg_qeec_dwrr 3463 * Transmission selection algorithm to use on the link going down from 3464 * the ETS element. 3465 * 0 - Strict priority 3466 * 1 - DWRR 3467 * Access: RW 3468 */ 3469 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3470 3471 /* reg_qeec_dwrr_weight 3472 * DWRR weight on the link going down from the ETS element. The 3473 * percentage of bandwidth guaranteed to an ETS element within 3474 * its hierarchy. The sum of all weights across all ETS elements 3475 * within one hierarchy should be equal to 100. Reserved when 3476 * transmission selection algorithm is strict priority. 3477 * Access: RW 3478 */ 3479 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3480 3481 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3482 enum mlxsw_reg_qeec_hr hr, u8 index, 3483 u8 next_index) 3484 { 3485 MLXSW_REG_ZERO(qeec, payload); 3486 mlxsw_reg_qeec_local_port_set(payload, local_port); 3487 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3488 mlxsw_reg_qeec_element_index_set(payload, index); 3489 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3490 } 3491 3492 /* QRWE - QoS ReWrite Enable 3493 * ------------------------- 3494 * This register configures the rewrite enable per receive port. 3495 */ 3496 #define MLXSW_REG_QRWE_ID 0x400F 3497 #define MLXSW_REG_QRWE_LEN 0x08 3498 3499 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3500 3501 /* reg_qrwe_local_port 3502 * Local port number. 3503 * Access: Index 3504 * 3505 * Note: CPU port is supported. No support for router port. 3506 */ 3507 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3508 3509 /* reg_qrwe_dscp 3510 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3511 * Access: RW 3512 */ 3513 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3514 3515 /* reg_qrwe_pcp 3516 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3517 * Access: RW 3518 */ 3519 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3520 3521 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3522 bool rewrite_pcp, bool rewrite_dscp) 3523 { 3524 MLXSW_REG_ZERO(qrwe, payload); 3525 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3526 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3527 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3528 } 3529 3530 /* QPDSM - QoS Priority to DSCP Mapping 3531 * ------------------------------------ 3532 * QoS Priority to DSCP Mapping Register 3533 */ 3534 #define MLXSW_REG_QPDSM_ID 0x4011 3535 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3536 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3537 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3538 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3539 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3540 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3541 3542 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3543 3544 /* reg_qpdsm_local_port 3545 * Local Port. Supported for data packets from CPU port. 3546 * Access: Index 3547 */ 3548 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3549 3550 /* reg_qpdsm_prio_entry_color0_e 3551 * Enable update of the entry for color 0 and a given port. 3552 * Access: WO 3553 */ 3554 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3555 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3556 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3557 3558 /* reg_qpdsm_prio_entry_color0_dscp 3559 * DSCP field in the outer label of the packet for color 0 and a given port. 3560 * Reserved when e=0. 3561 * Access: RW 3562 */ 3563 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3564 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3565 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3566 3567 /* reg_qpdsm_prio_entry_color1_e 3568 * Enable update of the entry for color 1 and a given port. 3569 * Access: WO 3570 */ 3571 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3572 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3573 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3574 3575 /* reg_qpdsm_prio_entry_color1_dscp 3576 * DSCP field in the outer label of the packet for color 1 and a given port. 3577 * Reserved when e=0. 3578 * Access: RW 3579 */ 3580 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3581 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3582 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3583 3584 /* reg_qpdsm_prio_entry_color2_e 3585 * Enable update of the entry for color 2 and a given port. 3586 * Access: WO 3587 */ 3588 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3589 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3590 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3591 3592 /* reg_qpdsm_prio_entry_color2_dscp 3593 * DSCP field in the outer label of the packet for color 2 and a given port. 3594 * Reserved when e=0. 3595 * Access: RW 3596 */ 3597 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3598 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3599 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3600 3601 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3602 { 3603 MLXSW_REG_ZERO(qpdsm, payload); 3604 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3605 } 3606 3607 static inline void 3608 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3609 { 3610 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3611 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3612 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3613 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3614 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3615 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3616 } 3617 3618 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3619 * -------------------------------------------------- 3620 * This register controls the mapping from DSCP field to 3621 * Switch Priority for IP packets. 3622 */ 3623 #define MLXSW_REG_QPDPM_ID 0x4013 3624 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3625 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3626 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3627 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3628 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3629 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3630 3631 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3632 3633 /* reg_qpdpm_local_port 3634 * Local Port. Supported for data packets from CPU port. 3635 * Access: Index 3636 */ 3637 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3638 3639 /* reg_qpdpm_dscp_e 3640 * Enable update of the specific entry. When cleared, the switch_prio and color 3641 * fields are ignored and the previous switch_prio and color values are 3642 * preserved. 3643 * Access: WO 3644 */ 3645 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3646 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3647 3648 /* reg_qpdpm_dscp_prio 3649 * The new Switch Priority value for the relevant DSCP value. 3650 * Access: RW 3651 */ 3652 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3653 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3654 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3655 3656 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3657 { 3658 MLXSW_REG_ZERO(qpdpm, payload); 3659 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3660 } 3661 3662 static inline void 3663 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3664 { 3665 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3666 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3667 } 3668 3669 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3670 * ------------------------------------------------------------------ 3671 * This register configures if the Switch Priority to Traffic Class mapping is 3672 * based on Multicast packet indication. If so, then multicast packets will get 3673 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3674 * QTCT. 3675 * By default, Switch Priority to Traffic Class mapping is not based on 3676 * Multicast packet indication. 3677 */ 3678 #define MLXSW_REG_QTCTM_ID 0x401A 3679 #define MLXSW_REG_QTCTM_LEN 0x08 3680 3681 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3682 3683 /* reg_qtctm_local_port 3684 * Local port number. 3685 * No support for CPU port. 3686 * Access: Index 3687 */ 3688 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3689 3690 /* reg_qtctm_mc 3691 * Multicast Mode 3692 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3693 * indication (default is 0, not based on Multicast packet indication). 3694 */ 3695 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3696 3697 static inline void 3698 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3699 { 3700 MLXSW_REG_ZERO(qtctm, payload); 3701 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3702 mlxsw_reg_qtctm_mc_set(payload, mc); 3703 } 3704 3705 /* PMLP - Ports Module to Local Port Register 3706 * ------------------------------------------ 3707 * Configures the assignment of modules to local ports. 3708 */ 3709 #define MLXSW_REG_PMLP_ID 0x5002 3710 #define MLXSW_REG_PMLP_LEN 0x40 3711 3712 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3713 3714 /* reg_pmlp_rxtx 3715 * 0 - Tx value is used for both Tx and Rx. 3716 * 1 - Rx value is taken from a separte field. 3717 * Access: RW 3718 */ 3719 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3720 3721 /* reg_pmlp_local_port 3722 * Local port number. 3723 * Access: Index 3724 */ 3725 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3726 3727 /* reg_pmlp_width 3728 * 0 - Unmap local port. 3729 * 1 - Lane 0 is used. 3730 * 2 - Lanes 0 and 1 are used. 3731 * 4 - Lanes 0, 1, 2 and 3 are used. 3732 * Access: RW 3733 */ 3734 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3735 3736 /* reg_pmlp_module 3737 * Module number. 3738 * Access: RW 3739 */ 3740 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3741 3742 /* reg_pmlp_tx_lane 3743 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3744 * Access: RW 3745 */ 3746 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3747 3748 /* reg_pmlp_rx_lane 3749 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3750 * equal to Tx lane. 3751 * Access: RW 3752 */ 3753 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3754 3755 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3756 { 3757 MLXSW_REG_ZERO(pmlp, payload); 3758 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3759 } 3760 3761 /* PMTU - Port MTU Register 3762 * ------------------------ 3763 * Configures and reports the port MTU. 3764 */ 3765 #define MLXSW_REG_PMTU_ID 0x5003 3766 #define MLXSW_REG_PMTU_LEN 0x10 3767 3768 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3769 3770 /* reg_pmtu_local_port 3771 * Local port number. 3772 * Access: Index 3773 */ 3774 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3775 3776 /* reg_pmtu_max_mtu 3777 * Maximum MTU. 3778 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3779 * reported, otherwise the minimum between the max_mtu of the different 3780 * types is reported. 3781 * Access: RO 3782 */ 3783 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3784 3785 /* reg_pmtu_admin_mtu 3786 * MTU value to set port to. Must be smaller or equal to max_mtu. 3787 * Note: If port type is Infiniband, then port must be disabled, when its 3788 * MTU is set. 3789 * Access: RW 3790 */ 3791 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3792 3793 /* reg_pmtu_oper_mtu 3794 * The actual MTU configured on the port. Packets exceeding this size 3795 * will be dropped. 3796 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3797 * oper_mtu might be smaller than admin_mtu. 3798 * Access: RO 3799 */ 3800 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3801 3802 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3803 u16 new_mtu) 3804 { 3805 MLXSW_REG_ZERO(pmtu, payload); 3806 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3807 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3808 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3809 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3810 } 3811 3812 /* PTYS - Port Type and Speed Register 3813 * ----------------------------------- 3814 * Configures and reports the port speed type. 3815 * 3816 * Note: When set while the link is up, the changes will not take effect 3817 * until the port transitions from down to up state. 3818 */ 3819 #define MLXSW_REG_PTYS_ID 0x5004 3820 #define MLXSW_REG_PTYS_LEN 0x40 3821 3822 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3823 3824 /* an_disable_admin 3825 * Auto negotiation disable administrative configuration 3826 * 0 - Device doesn't support AN disable. 3827 * 1 - Device supports AN disable. 3828 * Access: RW 3829 */ 3830 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3831 3832 /* reg_ptys_local_port 3833 * Local port number. 3834 * Access: Index 3835 */ 3836 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3837 3838 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3839 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3840 3841 /* reg_ptys_proto_mask 3842 * Protocol mask. Indicates which protocol is used. 3843 * 0 - Infiniband. 3844 * 1 - Fibre Channel. 3845 * 2 - Ethernet. 3846 * Access: Index 3847 */ 3848 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3849 3850 enum { 3851 MLXSW_REG_PTYS_AN_STATUS_NA, 3852 MLXSW_REG_PTYS_AN_STATUS_OK, 3853 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3854 }; 3855 3856 /* reg_ptys_an_status 3857 * Autonegotiation status. 3858 * Access: RO 3859 */ 3860 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3861 3862 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3863 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3864 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3865 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3866 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3867 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3868 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 3869 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 3870 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 3871 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 3872 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 3873 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 3874 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 3875 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 3876 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 3877 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 3878 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 3879 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 3880 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 3881 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 3882 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 3883 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 3884 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 3885 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 3886 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 3887 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 3888 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 3889 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 3890 3891 /* reg_ptys_eth_proto_cap 3892 * Ethernet port supported speeds and protocols. 3893 * Access: RO 3894 */ 3895 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 3896 3897 /* reg_ptys_ib_link_width_cap 3898 * IB port supported widths. 3899 * Access: RO 3900 */ 3901 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 3902 3903 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 3904 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 3905 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 3906 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 3907 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 3908 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 3909 3910 /* reg_ptys_ib_proto_cap 3911 * IB port supported speeds and protocols. 3912 * Access: RO 3913 */ 3914 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 3915 3916 /* reg_ptys_eth_proto_admin 3917 * Speed and protocol to set port to. 3918 * Access: RW 3919 */ 3920 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 3921 3922 /* reg_ptys_ib_link_width_admin 3923 * IB width to set port to. 3924 * Access: RW 3925 */ 3926 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 3927 3928 /* reg_ptys_ib_proto_admin 3929 * IB speeds and protocols to set port to. 3930 * Access: RW 3931 */ 3932 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 3933 3934 /* reg_ptys_eth_proto_oper 3935 * The current speed and protocol configured for the port. 3936 * Access: RO 3937 */ 3938 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 3939 3940 /* reg_ptys_ib_link_width_oper 3941 * The current IB width to set port to. 3942 * Access: RO 3943 */ 3944 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 3945 3946 /* reg_ptys_ib_proto_oper 3947 * The current IB speed and protocol. 3948 * Access: RO 3949 */ 3950 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 3951 3952 /* reg_ptys_eth_proto_lp_advertise 3953 * The protocols that were advertised by the link partner during 3954 * autonegotiation. 3955 * Access: RO 3956 */ 3957 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3958 3959 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3960 u32 proto_admin, bool autoneg) 3961 { 3962 MLXSW_REG_ZERO(ptys, payload); 3963 mlxsw_reg_ptys_local_port_set(payload, local_port); 3964 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 3965 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 3966 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 3967 } 3968 3969 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 3970 u32 *p_eth_proto_cap, 3971 u32 *p_eth_proto_adm, 3972 u32 *p_eth_proto_oper) 3973 { 3974 if (p_eth_proto_cap) 3975 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 3976 if (p_eth_proto_adm) 3977 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 3978 if (p_eth_proto_oper) 3979 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 3980 } 3981 3982 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 3983 u16 proto_admin, u16 link_width) 3984 { 3985 MLXSW_REG_ZERO(ptys, payload); 3986 mlxsw_reg_ptys_local_port_set(payload, local_port); 3987 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 3988 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 3989 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 3990 } 3991 3992 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 3993 u16 *p_ib_link_width_cap, 3994 u16 *p_ib_proto_oper, 3995 u16 *p_ib_link_width_oper) 3996 { 3997 if (p_ib_proto_cap) 3998 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 3999 if (p_ib_link_width_cap) 4000 *p_ib_link_width_cap = 4001 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4002 if (p_ib_proto_oper) 4003 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4004 if (p_ib_link_width_oper) 4005 *p_ib_link_width_oper = 4006 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4007 } 4008 4009 /* PPAD - Port Physical Address Register 4010 * ------------------------------------- 4011 * The PPAD register configures the per port physical MAC address. 4012 */ 4013 #define MLXSW_REG_PPAD_ID 0x5005 4014 #define MLXSW_REG_PPAD_LEN 0x10 4015 4016 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4017 4018 /* reg_ppad_single_base_mac 4019 * 0: base_mac, local port should be 0 and mac[7:0] is 4020 * reserved. HW will set incremental 4021 * 1: single_mac - mac of the local_port 4022 * Access: RW 4023 */ 4024 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4025 4026 /* reg_ppad_local_port 4027 * port number, if single_base_mac = 0 then local_port is reserved 4028 * Access: RW 4029 */ 4030 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4031 4032 /* reg_ppad_mac 4033 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4034 * If single_base_mac = 1 - the per port MAC address 4035 * Access: RW 4036 */ 4037 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4038 4039 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4040 u8 local_port) 4041 { 4042 MLXSW_REG_ZERO(ppad, payload); 4043 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4044 mlxsw_reg_ppad_local_port_set(payload, local_port); 4045 } 4046 4047 /* PAOS - Ports Administrative and Operational Status Register 4048 * ----------------------------------------------------------- 4049 * Configures and retrieves per port administrative and operational status. 4050 */ 4051 #define MLXSW_REG_PAOS_ID 0x5006 4052 #define MLXSW_REG_PAOS_LEN 0x10 4053 4054 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4055 4056 /* reg_paos_swid 4057 * Switch partition ID with which to associate the port. 4058 * Note: while external ports uses unique local port numbers (and thus swid is 4059 * redundant), router ports use the same local port number where swid is the 4060 * only indication for the relevant port. 4061 * Access: Index 4062 */ 4063 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4064 4065 /* reg_paos_local_port 4066 * Local port number. 4067 * Access: Index 4068 */ 4069 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4070 4071 /* reg_paos_admin_status 4072 * Port administrative state (the desired state of the port): 4073 * 1 - Up. 4074 * 2 - Down. 4075 * 3 - Up once. This means that in case of link failure, the port won't go 4076 * into polling mode, but will wait to be re-enabled by software. 4077 * 4 - Disabled by system. Can only be set by hardware. 4078 * Access: RW 4079 */ 4080 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4081 4082 /* reg_paos_oper_status 4083 * Port operational state (the current state): 4084 * 1 - Up. 4085 * 2 - Down. 4086 * 3 - Down by port failure. This means that the device will not let the 4087 * port up again until explicitly specified by software. 4088 * Access: RO 4089 */ 4090 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4091 4092 /* reg_paos_ase 4093 * Admin state update enabled. 4094 * Access: WO 4095 */ 4096 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4097 4098 /* reg_paos_ee 4099 * Event update enable. If this bit is set, event generation will be 4100 * updated based on the e field. 4101 * Access: WO 4102 */ 4103 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4104 4105 /* reg_paos_e 4106 * Event generation on operational state change: 4107 * 0 - Do not generate event. 4108 * 1 - Generate Event. 4109 * 2 - Generate Single Event. 4110 * Access: RW 4111 */ 4112 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4113 4114 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4115 enum mlxsw_port_admin_status status) 4116 { 4117 MLXSW_REG_ZERO(paos, payload); 4118 mlxsw_reg_paos_swid_set(payload, 0); 4119 mlxsw_reg_paos_local_port_set(payload, local_port); 4120 mlxsw_reg_paos_admin_status_set(payload, status); 4121 mlxsw_reg_paos_oper_status_set(payload, 0); 4122 mlxsw_reg_paos_ase_set(payload, 1); 4123 mlxsw_reg_paos_ee_set(payload, 1); 4124 mlxsw_reg_paos_e_set(payload, 1); 4125 } 4126 4127 /* PFCC - Ports Flow Control Configuration Register 4128 * ------------------------------------------------ 4129 * Configures and retrieves the per port flow control configuration. 4130 */ 4131 #define MLXSW_REG_PFCC_ID 0x5007 4132 #define MLXSW_REG_PFCC_LEN 0x20 4133 4134 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4135 4136 /* reg_pfcc_local_port 4137 * Local port number. 4138 * Access: Index 4139 */ 4140 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4141 4142 /* reg_pfcc_pnat 4143 * Port number access type. Determines the way local_port is interpreted: 4144 * 0 - Local port number. 4145 * 1 - IB / label port number. 4146 * Access: Index 4147 */ 4148 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4149 4150 /* reg_pfcc_shl_cap 4151 * Send to higher layers capabilities: 4152 * 0 - No capability of sending Pause and PFC frames to higher layers. 4153 * 1 - Device has capability of sending Pause and PFC frames to higher 4154 * layers. 4155 * Access: RO 4156 */ 4157 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4158 4159 /* reg_pfcc_shl_opr 4160 * Send to higher layers operation: 4161 * 0 - Pause and PFC frames are handled by the port (default). 4162 * 1 - Pause and PFC frames are handled by the port and also sent to 4163 * higher layers. Only valid if shl_cap = 1. 4164 * Access: RW 4165 */ 4166 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4167 4168 /* reg_pfcc_ppan 4169 * Pause policy auto negotiation. 4170 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4171 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4172 * based on the auto-negotiation resolution. 4173 * Access: RW 4174 * 4175 * Note: The auto-negotiation advertisement is set according to pptx and 4176 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4177 */ 4178 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4179 4180 /* reg_pfcc_prio_mask_tx 4181 * Bit per priority indicating if Tx flow control policy should be 4182 * updated based on bit pfctx. 4183 * Access: WO 4184 */ 4185 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4186 4187 /* reg_pfcc_prio_mask_rx 4188 * Bit per priority indicating if Rx flow control policy should be 4189 * updated based on bit pfcrx. 4190 * Access: WO 4191 */ 4192 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4193 4194 /* reg_pfcc_pptx 4195 * Admin Pause policy on Tx. 4196 * 0 - Never generate Pause frames (default). 4197 * 1 - Generate Pause frames according to Rx buffer threshold. 4198 * Access: RW 4199 */ 4200 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4201 4202 /* reg_pfcc_aptx 4203 * Active (operational) Pause policy on Tx. 4204 * 0 - Never generate Pause frames. 4205 * 1 - Generate Pause frames according to Rx buffer threshold. 4206 * Access: RO 4207 */ 4208 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4209 4210 /* reg_pfcc_pfctx 4211 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4212 * 0 - Never generate priority Pause frames on the specified priority 4213 * (default). 4214 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4215 * the specified priority. 4216 * Access: RW 4217 * 4218 * Note: pfctx and pptx must be mutually exclusive. 4219 */ 4220 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4221 4222 /* reg_pfcc_pprx 4223 * Admin Pause policy on Rx. 4224 * 0 - Ignore received Pause frames (default). 4225 * 1 - Respect received Pause frames. 4226 * Access: RW 4227 */ 4228 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4229 4230 /* reg_pfcc_aprx 4231 * Active (operational) Pause policy on Rx. 4232 * 0 - Ignore received Pause frames. 4233 * 1 - Respect received Pause frames. 4234 * Access: RO 4235 */ 4236 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4237 4238 /* reg_pfcc_pfcrx 4239 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4240 * 0 - Ignore incoming priority Pause frames on the specified priority 4241 * (default). 4242 * 1 - Respect incoming priority Pause frames on the specified priority. 4243 * Access: RW 4244 */ 4245 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4246 4247 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4248 4249 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4250 { 4251 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4252 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4253 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4254 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4255 } 4256 4257 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4258 { 4259 MLXSW_REG_ZERO(pfcc, payload); 4260 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4261 } 4262 4263 /* PPCNT - Ports Performance Counters Register 4264 * ------------------------------------------- 4265 * The PPCNT register retrieves per port performance counters. 4266 */ 4267 #define MLXSW_REG_PPCNT_ID 0x5008 4268 #define MLXSW_REG_PPCNT_LEN 0x100 4269 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4270 4271 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4272 4273 /* reg_ppcnt_swid 4274 * For HCA: must be always 0. 4275 * Switch partition ID to associate port with. 4276 * Switch partitions are numbered from 0 to 7 inclusively. 4277 * Switch partition 254 indicates stacking ports. 4278 * Switch partition 255 indicates all switch partitions. 4279 * Only valid on Set() operation with local_port=255. 4280 * Access: Index 4281 */ 4282 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4283 4284 /* reg_ppcnt_local_port 4285 * Local port number. 4286 * 255 indicates all ports on the device, and is only allowed 4287 * for Set() operation. 4288 * Access: Index 4289 */ 4290 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4291 4292 /* reg_ppcnt_pnat 4293 * Port number access type: 4294 * 0 - Local port number 4295 * 1 - IB port number 4296 * Access: Index 4297 */ 4298 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4299 4300 enum mlxsw_reg_ppcnt_grp { 4301 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4302 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4303 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4304 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4305 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4306 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4307 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4308 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4309 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4310 }; 4311 4312 /* reg_ppcnt_grp 4313 * Performance counter group. 4314 * Group 63 indicates all groups. Only valid on Set() operation with 4315 * clr bit set. 4316 * 0x0: IEEE 802.3 Counters 4317 * 0x1: RFC 2863 Counters 4318 * 0x2: RFC 2819 Counters 4319 * 0x3: RFC 3635 Counters 4320 * 0x5: Ethernet Extended Counters 4321 * 0x6: Ethernet Discard Counters 4322 * 0x8: Link Level Retransmission Counters 4323 * 0x10: Per Priority Counters 4324 * 0x11: Per Traffic Class Counters 4325 * 0x12: Physical Layer Counters 4326 * 0x13: Per Traffic Class Congestion Counters 4327 * Access: Index 4328 */ 4329 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4330 4331 /* reg_ppcnt_clr 4332 * Clear counters. Setting the clr bit will reset the counter value 4333 * for all counters in the counter group. This bit can be set 4334 * for both Set() and Get() operation. 4335 * Access: OP 4336 */ 4337 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4338 4339 /* reg_ppcnt_prio_tc 4340 * Priority for counter set that support per priority, valid values: 0-7. 4341 * Traffic class for counter set that support per traffic class, 4342 * valid values: 0- cap_max_tclass-1 . 4343 * For HCA: cap_max_tclass is always 8. 4344 * Otherwise must be 0. 4345 * Access: Index 4346 */ 4347 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4348 4349 /* Ethernet IEEE 802.3 Counter Group */ 4350 4351 /* reg_ppcnt_a_frames_transmitted_ok 4352 * Access: RO 4353 */ 4354 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4356 4357 /* reg_ppcnt_a_frames_received_ok 4358 * Access: RO 4359 */ 4360 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4361 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4362 4363 /* reg_ppcnt_a_frame_check_sequence_errors 4364 * Access: RO 4365 */ 4366 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4367 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4368 4369 /* reg_ppcnt_a_alignment_errors 4370 * Access: RO 4371 */ 4372 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4373 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4374 4375 /* reg_ppcnt_a_octets_transmitted_ok 4376 * Access: RO 4377 */ 4378 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4379 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4380 4381 /* reg_ppcnt_a_octets_received_ok 4382 * Access: RO 4383 */ 4384 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4385 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4386 4387 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4388 * Access: RO 4389 */ 4390 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4391 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4392 4393 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4394 * Access: RO 4395 */ 4396 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4397 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4398 4399 /* reg_ppcnt_a_multicast_frames_received_ok 4400 * Access: RO 4401 */ 4402 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4403 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4404 4405 /* reg_ppcnt_a_broadcast_frames_received_ok 4406 * Access: RO 4407 */ 4408 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4409 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4410 4411 /* reg_ppcnt_a_in_range_length_errors 4412 * Access: RO 4413 */ 4414 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4415 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4416 4417 /* reg_ppcnt_a_out_of_range_length_field 4418 * Access: RO 4419 */ 4420 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4421 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4422 4423 /* reg_ppcnt_a_frame_too_long_errors 4424 * Access: RO 4425 */ 4426 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4427 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4428 4429 /* reg_ppcnt_a_symbol_error_during_carrier 4430 * Access: RO 4431 */ 4432 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4433 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4434 4435 /* reg_ppcnt_a_mac_control_frames_transmitted 4436 * Access: RO 4437 */ 4438 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4439 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4440 4441 /* reg_ppcnt_a_mac_control_frames_received 4442 * Access: RO 4443 */ 4444 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4445 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4446 4447 /* reg_ppcnt_a_unsupported_opcodes_received 4448 * Access: RO 4449 */ 4450 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4451 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4452 4453 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4454 * Access: RO 4455 */ 4456 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4457 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4458 4459 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4460 * Access: RO 4461 */ 4462 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4463 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4464 4465 /* Ethernet RFC 2863 Counter Group */ 4466 4467 /* reg_ppcnt_if_in_discards 4468 * Access: RO 4469 */ 4470 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4471 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4472 4473 /* reg_ppcnt_if_out_discards 4474 * Access: RO 4475 */ 4476 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4477 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4478 4479 /* reg_ppcnt_if_out_errors 4480 * Access: RO 4481 */ 4482 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4483 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4484 4485 /* Ethernet RFC 2819 Counter Group */ 4486 4487 /* reg_ppcnt_ether_stats_undersize_pkts 4488 * Access: RO 4489 */ 4490 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4491 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4492 4493 /* reg_ppcnt_ether_stats_oversize_pkts 4494 * Access: RO 4495 */ 4496 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4497 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4498 4499 /* reg_ppcnt_ether_stats_fragments 4500 * Access: RO 4501 */ 4502 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4503 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4504 4505 /* reg_ppcnt_ether_stats_pkts64octets 4506 * Access: RO 4507 */ 4508 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4509 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4510 4511 /* reg_ppcnt_ether_stats_pkts65to127octets 4512 * Access: RO 4513 */ 4514 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4515 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4516 4517 /* reg_ppcnt_ether_stats_pkts128to255octets 4518 * Access: RO 4519 */ 4520 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4521 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4522 4523 /* reg_ppcnt_ether_stats_pkts256to511octets 4524 * Access: RO 4525 */ 4526 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4527 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4528 4529 /* reg_ppcnt_ether_stats_pkts512to1023octets 4530 * Access: RO 4531 */ 4532 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4533 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4534 4535 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4536 * Access: RO 4537 */ 4538 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4539 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4540 4541 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4542 * Access: RO 4543 */ 4544 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4545 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4546 4547 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4548 * Access: RO 4549 */ 4550 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4551 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4552 4553 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4554 * Access: RO 4555 */ 4556 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4557 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4558 4559 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4560 * Access: RO 4561 */ 4562 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4563 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4564 4565 /* Ethernet RFC 3635 Counter Group */ 4566 4567 /* reg_ppcnt_dot3stats_fcs_errors 4568 * Access: RO 4569 */ 4570 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4571 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4572 4573 /* reg_ppcnt_dot3stats_symbol_errors 4574 * Access: RO 4575 */ 4576 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4577 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4578 4579 /* reg_ppcnt_dot3control_in_unknown_opcodes 4580 * Access: RO 4581 */ 4582 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4583 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4584 4585 /* reg_ppcnt_dot3in_pause_frames 4586 * Access: RO 4587 */ 4588 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4589 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4590 4591 /* Ethernet Extended Counter Group Counters */ 4592 4593 /* reg_ppcnt_ecn_marked 4594 * Access: RO 4595 */ 4596 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4597 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4598 4599 /* Ethernet Discard Counter Group Counters */ 4600 4601 /* reg_ppcnt_ingress_general 4602 * Access: RO 4603 */ 4604 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4605 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4606 4607 /* reg_ppcnt_ingress_policy_engine 4608 * Access: RO 4609 */ 4610 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4611 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4612 4613 /* reg_ppcnt_ingress_vlan_membership 4614 * Access: RO 4615 */ 4616 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4617 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4618 4619 /* reg_ppcnt_ingress_tag_frame_type 4620 * Access: RO 4621 */ 4622 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4623 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4624 4625 /* reg_ppcnt_egress_vlan_membership 4626 * Access: RO 4627 */ 4628 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 4629 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4630 4631 /* reg_ppcnt_loopback_filter 4632 * Access: RO 4633 */ 4634 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 4635 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4636 4637 /* reg_ppcnt_egress_general 4638 * Access: RO 4639 */ 4640 MLXSW_ITEM64(reg, ppcnt, egress_general, 4641 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4642 4643 /* reg_ppcnt_egress_hoq 4644 * Access: RO 4645 */ 4646 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 4647 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4648 4649 /* reg_ppcnt_egress_policy_engine 4650 * Access: RO 4651 */ 4652 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 4653 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4654 4655 /* reg_ppcnt_ingress_tx_link_down 4656 * Access: RO 4657 */ 4658 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 4659 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4660 4661 /* reg_ppcnt_egress_stp_filter 4662 * Access: RO 4663 */ 4664 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 4665 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4666 4667 /* reg_ppcnt_egress_sll 4668 * Access: RO 4669 */ 4670 MLXSW_ITEM64(reg, ppcnt, egress_sll, 4671 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4672 4673 /* Ethernet Per Priority Group Counters */ 4674 4675 /* reg_ppcnt_rx_octets 4676 * Access: RO 4677 */ 4678 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4679 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4680 4681 /* reg_ppcnt_rx_frames 4682 * Access: RO 4683 */ 4684 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4685 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4686 4687 /* reg_ppcnt_tx_octets 4688 * Access: RO 4689 */ 4690 MLXSW_ITEM64(reg, ppcnt, tx_octets, 4691 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4692 4693 /* reg_ppcnt_tx_frames 4694 * Access: RO 4695 */ 4696 MLXSW_ITEM64(reg, ppcnt, tx_frames, 4697 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4698 4699 /* reg_ppcnt_rx_pause 4700 * Access: RO 4701 */ 4702 MLXSW_ITEM64(reg, ppcnt, rx_pause, 4703 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4704 4705 /* reg_ppcnt_rx_pause_duration 4706 * Access: RO 4707 */ 4708 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 4709 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4710 4711 /* reg_ppcnt_tx_pause 4712 * Access: RO 4713 */ 4714 MLXSW_ITEM64(reg, ppcnt, tx_pause, 4715 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4716 4717 /* reg_ppcnt_tx_pause_duration 4718 * Access: RO 4719 */ 4720 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 4721 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4722 4723 /* reg_ppcnt_rx_pause_transition 4724 * Access: RO 4725 */ 4726 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 4727 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4728 4729 /* Ethernet Per Traffic Group Counters */ 4730 4731 /* reg_ppcnt_tc_transmit_queue 4732 * Contains the transmit queue depth in cells of traffic class 4733 * selected by prio_tc and the port selected by local_port. 4734 * The field cannot be cleared. 4735 * Access: RO 4736 */ 4737 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 4738 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4739 4740 /* reg_ppcnt_tc_no_buffer_discard_uc 4741 * The number of unicast packets dropped due to lack of shared 4742 * buffer resources. 4743 * Access: RO 4744 */ 4745 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 4746 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4747 4748 /* Ethernet Per Traffic Class Congestion Group Counters */ 4749 4750 /* reg_ppcnt_wred_discard 4751 * Access: RO 4752 */ 4753 MLXSW_ITEM64(reg, ppcnt, wred_discard, 4754 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4755 4756 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 4757 enum mlxsw_reg_ppcnt_grp grp, 4758 u8 prio_tc) 4759 { 4760 MLXSW_REG_ZERO(ppcnt, payload); 4761 mlxsw_reg_ppcnt_swid_set(payload, 0); 4762 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 4763 mlxsw_reg_ppcnt_pnat_set(payload, 0); 4764 mlxsw_reg_ppcnt_grp_set(payload, grp); 4765 mlxsw_reg_ppcnt_clr_set(payload, 0); 4766 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 4767 } 4768 4769 /* PLIB - Port Local to InfiniBand Port 4770 * ------------------------------------ 4771 * The PLIB register performs mapping from Local Port into InfiniBand Port. 4772 */ 4773 #define MLXSW_REG_PLIB_ID 0x500A 4774 #define MLXSW_REG_PLIB_LEN 0x10 4775 4776 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 4777 4778 /* reg_plib_local_port 4779 * Local port number. 4780 * Access: Index 4781 */ 4782 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 4783 4784 /* reg_plib_ib_port 4785 * InfiniBand port remapping for local_port. 4786 * Access: RW 4787 */ 4788 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 4789 4790 /* PPTB - Port Prio To Buffer Register 4791 * ----------------------------------- 4792 * Configures the switch priority to buffer table. 4793 */ 4794 #define MLXSW_REG_PPTB_ID 0x500B 4795 #define MLXSW_REG_PPTB_LEN 0x10 4796 4797 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 4798 4799 enum { 4800 MLXSW_REG_PPTB_MM_UM, 4801 MLXSW_REG_PPTB_MM_UNICAST, 4802 MLXSW_REG_PPTB_MM_MULTICAST, 4803 }; 4804 4805 /* reg_pptb_mm 4806 * Mapping mode. 4807 * 0 - Map both unicast and multicast packets to the same buffer. 4808 * 1 - Map only unicast packets. 4809 * 2 - Map only multicast packets. 4810 * Access: Index 4811 * 4812 * Note: SwitchX-2 only supports the first option. 4813 */ 4814 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4815 4816 /* reg_pptb_local_port 4817 * Local port number. 4818 * Access: Index 4819 */ 4820 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 4821 4822 /* reg_pptb_um 4823 * Enables the update of the untagged_buf field. 4824 * Access: RW 4825 */ 4826 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 4827 4828 /* reg_pptb_pm 4829 * Enables the update of the prio_to_buff field. 4830 * Bit <i> is a flag for updating the mapping for switch priority <i>. 4831 * Access: RW 4832 */ 4833 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 4834 4835 /* reg_pptb_prio_to_buff 4836 * Mapping of switch priority <i> to one of the allocated receive port 4837 * buffers. 4838 * Access: RW 4839 */ 4840 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 4841 4842 /* reg_pptb_pm_msb 4843 * Enables the update of the prio_to_buff field. 4844 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 4845 * Access: RW 4846 */ 4847 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 4848 4849 /* reg_pptb_untagged_buff 4850 * Mapping of untagged frames to one of the allocated receive port buffers. 4851 * Access: RW 4852 * 4853 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 4854 * Spectrum, as it maps untagged packets based on the default switch priority. 4855 */ 4856 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 4857 4858 /* reg_pptb_prio_to_buff_msb 4859 * Mapping of switch priority <i+8> to one of the allocated receive port 4860 * buffers. 4861 * Access: RW 4862 */ 4863 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 4864 4865 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 4866 4867 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 4868 { 4869 MLXSW_REG_ZERO(pptb, payload); 4870 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 4871 mlxsw_reg_pptb_local_port_set(payload, local_port); 4872 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4873 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4874 } 4875 4876 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 4877 u8 buff) 4878 { 4879 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 4880 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 4881 } 4882 4883 /* PBMC - Port Buffer Management Control Register 4884 * ---------------------------------------------- 4885 * The PBMC register configures and retrieves the port packet buffer 4886 * allocation for different Prios, and the Pause threshold management. 4887 */ 4888 #define MLXSW_REG_PBMC_ID 0x500C 4889 #define MLXSW_REG_PBMC_LEN 0x6C 4890 4891 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 4892 4893 /* reg_pbmc_local_port 4894 * Local port number. 4895 * Access: Index 4896 */ 4897 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 4898 4899 /* reg_pbmc_xoff_timer_value 4900 * When device generates a pause frame, it uses this value as the pause 4901 * timer (time for the peer port to pause in quota-512 bit time). 4902 * Access: RW 4903 */ 4904 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 4905 4906 /* reg_pbmc_xoff_refresh 4907 * The time before a new pause frame should be sent to refresh the pause RW 4908 * state. Using the same units as xoff_timer_value above (in quota-512 bit 4909 * time). 4910 * Access: RW 4911 */ 4912 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 4913 4914 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 4915 4916 /* reg_pbmc_buf_lossy 4917 * The field indicates if the buffer is lossy. 4918 * 0 - Lossless 4919 * 1 - Lossy 4920 * Access: RW 4921 */ 4922 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 4923 4924 /* reg_pbmc_buf_epsb 4925 * Eligible for Port Shared buffer. 4926 * If epsb is set, packets assigned to buffer are allowed to insert the port 4927 * shared buffer. 4928 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 4929 * Access: RW 4930 */ 4931 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 4932 4933 /* reg_pbmc_buf_size 4934 * The part of the packet buffer array is allocated for the specific buffer. 4935 * Units are represented in cells. 4936 * Access: RW 4937 */ 4938 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 4939 4940 /* reg_pbmc_buf_xoff_threshold 4941 * Once the amount of data in the buffer goes above this value, device 4942 * starts sending PFC frames for all priorities associated with the 4943 * buffer. Units are represented in cells. Reserved in case of lossy 4944 * buffer. 4945 * Access: RW 4946 * 4947 * Note: In Spectrum, reserved for buffer[9]. 4948 */ 4949 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 4950 0x08, 0x04, false); 4951 4952 /* reg_pbmc_buf_xon_threshold 4953 * When the amount of data in the buffer goes below this value, device 4954 * stops sending PFC frames for the priorities associated with the 4955 * buffer. Units are represented in cells. Reserved in case of lossy 4956 * buffer. 4957 * Access: RW 4958 * 4959 * Note: In Spectrum, reserved for buffer[9]. 4960 */ 4961 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 4962 0x08, 0x04, false); 4963 4964 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 4965 u16 xoff_timer_value, u16 xoff_refresh) 4966 { 4967 MLXSW_REG_ZERO(pbmc, payload); 4968 mlxsw_reg_pbmc_local_port_set(payload, local_port); 4969 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 4970 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 4971 } 4972 4973 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 4974 int buf_index, 4975 u16 size) 4976 { 4977 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 4978 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4979 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4980 } 4981 4982 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 4983 int buf_index, u16 size, 4984 u16 threshold) 4985 { 4986 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 4987 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4988 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4989 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 4990 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 4991 } 4992 4993 /* PSPA - Port Switch Partition Allocation 4994 * --------------------------------------- 4995 * Controls the association of a port with a switch partition and enables 4996 * configuring ports as stacking ports. 4997 */ 4998 #define MLXSW_REG_PSPA_ID 0x500D 4999 #define MLXSW_REG_PSPA_LEN 0x8 5000 5001 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5002 5003 /* reg_pspa_swid 5004 * Switch partition ID. 5005 * Access: RW 5006 */ 5007 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5008 5009 /* reg_pspa_local_port 5010 * Local port number. 5011 * Access: Index 5012 */ 5013 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5014 5015 /* reg_pspa_sub_port 5016 * Virtual port within the local port. Set to 0 when virtual ports are 5017 * disabled on the local port. 5018 * Access: Index 5019 */ 5020 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5021 5022 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5023 { 5024 MLXSW_REG_ZERO(pspa, payload); 5025 mlxsw_reg_pspa_swid_set(payload, swid); 5026 mlxsw_reg_pspa_local_port_set(payload, local_port); 5027 mlxsw_reg_pspa_sub_port_set(payload, 0); 5028 } 5029 5030 /* HTGT - Host Trap Group Table 5031 * ---------------------------- 5032 * Configures the properties for forwarding to CPU. 5033 */ 5034 #define MLXSW_REG_HTGT_ID 0x7002 5035 #define MLXSW_REG_HTGT_LEN 0x20 5036 5037 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5038 5039 /* reg_htgt_swid 5040 * Switch partition ID. 5041 * Access: Index 5042 */ 5043 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5044 5045 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5046 5047 /* reg_htgt_type 5048 * CPU path type. 5049 * Access: RW 5050 */ 5051 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5052 5053 enum mlxsw_reg_htgt_trap_group { 5054 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5055 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 5056 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 5057 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5058 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5059 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5060 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 5061 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5062 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5063 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5064 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5065 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 5066 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 5067 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5068 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 5069 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5070 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5071 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 5072 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5073 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 5074 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 5075 }; 5076 5077 /* reg_htgt_trap_group 5078 * Trap group number. User defined number specifying which trap groups 5079 * should be forwarded to the CPU. The mapping between trap IDs and trap 5080 * groups is configured using HPKT register. 5081 * Access: Index 5082 */ 5083 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5084 5085 enum { 5086 MLXSW_REG_HTGT_POLICER_DISABLE, 5087 MLXSW_REG_HTGT_POLICER_ENABLE, 5088 }; 5089 5090 /* reg_htgt_pide 5091 * Enable policer ID specified using 'pid' field. 5092 * Access: RW 5093 */ 5094 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5095 5096 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5097 5098 /* reg_htgt_pid 5099 * Policer ID for the trap group. 5100 * Access: RW 5101 */ 5102 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5103 5104 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5105 5106 /* reg_htgt_mirror_action 5107 * Mirror action to use. 5108 * 0 - Trap to CPU. 5109 * 1 - Trap to CPU and mirror to a mirroring agent. 5110 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5111 * Access: RW 5112 * 5113 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5114 */ 5115 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5116 5117 /* reg_htgt_mirroring_agent 5118 * Mirroring agent. 5119 * Access: RW 5120 */ 5121 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5122 5123 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5124 5125 /* reg_htgt_priority 5126 * Trap group priority. 5127 * In case a packet matches multiple classification rules, the packet will 5128 * only be trapped once, based on the trap ID associated with the group (via 5129 * register HPKT) with the highest priority. 5130 * Supported values are 0-7, with 7 represnting the highest priority. 5131 * Access: RW 5132 * 5133 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5134 * by the 'trap_group' field. 5135 */ 5136 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5137 5138 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5139 5140 /* reg_htgt_local_path_cpu_tclass 5141 * CPU ingress traffic class for the trap group. 5142 * Access: RW 5143 */ 5144 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5145 5146 enum mlxsw_reg_htgt_local_path_rdq { 5147 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5148 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5149 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5150 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5151 }; 5152 /* reg_htgt_local_path_rdq 5153 * Receive descriptor queue (RDQ) to use for the trap group. 5154 * Access: RW 5155 */ 5156 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5157 5158 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5159 u8 priority, u8 tc) 5160 { 5161 MLXSW_REG_ZERO(htgt, payload); 5162 5163 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5164 mlxsw_reg_htgt_pide_set(payload, 5165 MLXSW_REG_HTGT_POLICER_DISABLE); 5166 } else { 5167 mlxsw_reg_htgt_pide_set(payload, 5168 MLXSW_REG_HTGT_POLICER_ENABLE); 5169 mlxsw_reg_htgt_pid_set(payload, policer_id); 5170 } 5171 5172 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5173 mlxsw_reg_htgt_trap_group_set(payload, group); 5174 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5175 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5176 mlxsw_reg_htgt_priority_set(payload, priority); 5177 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5178 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5179 } 5180 5181 /* HPKT - Host Packet Trap 5182 * ----------------------- 5183 * Configures trap IDs inside trap groups. 5184 */ 5185 #define MLXSW_REG_HPKT_ID 0x7003 5186 #define MLXSW_REG_HPKT_LEN 0x10 5187 5188 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5189 5190 enum { 5191 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5192 MLXSW_REG_HPKT_ACK_REQUIRED, 5193 }; 5194 5195 /* reg_hpkt_ack 5196 * Require acknowledgements from the host for events. 5197 * If set, then the device will wait for the event it sent to be acknowledged 5198 * by the host. This option is only relevant for event trap IDs. 5199 * Access: RW 5200 * 5201 * Note: Currently not supported by firmware. 5202 */ 5203 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5204 5205 enum mlxsw_reg_hpkt_action { 5206 MLXSW_REG_HPKT_ACTION_FORWARD, 5207 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5208 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5209 MLXSW_REG_HPKT_ACTION_DISCARD, 5210 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5211 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5212 }; 5213 5214 /* reg_hpkt_action 5215 * Action to perform on packet when trapped. 5216 * 0 - No action. Forward to CPU based on switching rules. 5217 * 1 - Trap to CPU (CPU receives sole copy). 5218 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5219 * 3 - Discard. 5220 * 4 - Soft discard (allow other traps to act on the packet). 5221 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5222 * Access: RW 5223 * 5224 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5225 * addressed to the CPU. 5226 */ 5227 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5228 5229 /* reg_hpkt_trap_group 5230 * Trap group to associate the trap with. 5231 * Access: RW 5232 */ 5233 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5234 5235 /* reg_hpkt_trap_id 5236 * Trap ID. 5237 * Access: Index 5238 * 5239 * Note: A trap ID can only be associated with a single trap group. The device 5240 * will associate the trap ID with the last trap group configured. 5241 */ 5242 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5243 5244 enum { 5245 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5246 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5247 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5248 }; 5249 5250 /* reg_hpkt_ctrl 5251 * Configure dedicated buffer resources for control packets. 5252 * Ignored by SwitchX-2. 5253 * 0 - Keep factory defaults. 5254 * 1 - Do not use control buffer for this trap ID. 5255 * 2 - Use control buffer for this trap ID. 5256 * Access: RW 5257 */ 5258 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5259 5260 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5261 enum mlxsw_reg_htgt_trap_group trap_group, 5262 bool is_ctrl) 5263 { 5264 MLXSW_REG_ZERO(hpkt, payload); 5265 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5266 mlxsw_reg_hpkt_action_set(payload, action); 5267 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5268 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5269 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5270 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5271 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5272 } 5273 5274 /* RGCR - Router General Configuration Register 5275 * -------------------------------------------- 5276 * The register is used for setting up the router configuration. 5277 */ 5278 #define MLXSW_REG_RGCR_ID 0x8001 5279 #define MLXSW_REG_RGCR_LEN 0x28 5280 5281 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5282 5283 /* reg_rgcr_ipv4_en 5284 * IPv4 router enable. 5285 * Access: RW 5286 */ 5287 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5288 5289 /* reg_rgcr_ipv6_en 5290 * IPv6 router enable. 5291 * Access: RW 5292 */ 5293 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5294 5295 /* reg_rgcr_max_router_interfaces 5296 * Defines the maximum number of active router interfaces for all virtual 5297 * routers. 5298 * Access: RW 5299 */ 5300 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5301 5302 /* reg_rgcr_usp 5303 * Update switch priority and packet color. 5304 * 0 - Preserve the value of Switch Priority and packet color. 5305 * 1 - Recalculate the value of Switch Priority and packet color. 5306 * Access: RW 5307 * 5308 * Note: Not supported by SwitchX and SwitchX-2. 5309 */ 5310 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5311 5312 /* reg_rgcr_pcp_rw 5313 * Indicates how to handle the pcp_rewrite_en value: 5314 * 0 - Preserve the value of pcp_rewrite_en. 5315 * 2 - Disable PCP rewrite. 5316 * 3 - Enable PCP rewrite. 5317 * Access: RW 5318 * 5319 * Note: Not supported by SwitchX and SwitchX-2. 5320 */ 5321 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5322 5323 /* reg_rgcr_activity_dis 5324 * Activity disable: 5325 * 0 - Activity will be set when an entry is hit (default). 5326 * 1 - Activity will not be set when an entry is hit. 5327 * 5328 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5329 * (RALUE). 5330 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5331 * Entry (RAUHT). 5332 * Bits 2:7 are reserved. 5333 * Access: RW 5334 * 5335 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5336 */ 5337 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5338 5339 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5340 bool ipv6_en) 5341 { 5342 MLXSW_REG_ZERO(rgcr, payload); 5343 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5344 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5345 } 5346 5347 /* RITR - Router Interface Table Register 5348 * -------------------------------------- 5349 * The register is used to configure the router interface table. 5350 */ 5351 #define MLXSW_REG_RITR_ID 0x8002 5352 #define MLXSW_REG_RITR_LEN 0x40 5353 5354 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5355 5356 /* reg_ritr_enable 5357 * Enables routing on the router interface. 5358 * Access: RW 5359 */ 5360 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5361 5362 /* reg_ritr_ipv4 5363 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5364 * interface. 5365 * Access: RW 5366 */ 5367 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5368 5369 /* reg_ritr_ipv6 5370 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5371 * interface. 5372 * Access: RW 5373 */ 5374 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5375 5376 /* reg_ritr_ipv4_mc 5377 * IPv4 multicast routing enable. 5378 * Access: RW 5379 */ 5380 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5381 5382 /* reg_ritr_ipv6_mc 5383 * IPv6 multicast routing enable. 5384 * Access: RW 5385 */ 5386 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5387 5388 enum mlxsw_reg_ritr_if_type { 5389 /* VLAN interface. */ 5390 MLXSW_REG_RITR_VLAN_IF, 5391 /* FID interface. */ 5392 MLXSW_REG_RITR_FID_IF, 5393 /* Sub-port interface. */ 5394 MLXSW_REG_RITR_SP_IF, 5395 /* Loopback Interface. */ 5396 MLXSW_REG_RITR_LOOPBACK_IF, 5397 }; 5398 5399 /* reg_ritr_type 5400 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5401 * Access: RW 5402 */ 5403 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5404 5405 enum { 5406 MLXSW_REG_RITR_RIF_CREATE, 5407 MLXSW_REG_RITR_RIF_DEL, 5408 }; 5409 5410 /* reg_ritr_op 5411 * Opcode: 5412 * 0 - Create or edit RIF. 5413 * 1 - Delete RIF. 5414 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5415 * is not supported. An interface must be deleted and re-created in order 5416 * to update properties. 5417 * Access: WO 5418 */ 5419 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5420 5421 /* reg_ritr_rif 5422 * Router interface index. A pointer to the Router Interface Table. 5423 * Access: Index 5424 */ 5425 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5426 5427 /* reg_ritr_ipv4_fe 5428 * IPv4 Forwarding Enable. 5429 * Enables routing of IPv4 traffic on the router interface. When disabled, 5430 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5431 * Not supported in SwitchX-2. 5432 * Access: RW 5433 */ 5434 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5435 5436 /* reg_ritr_ipv6_fe 5437 * IPv6 Forwarding Enable. 5438 * Enables routing of IPv6 traffic on the router interface. When disabled, 5439 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5440 * Not supported in SwitchX-2. 5441 * Access: RW 5442 */ 5443 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5444 5445 /* reg_ritr_ipv4_mc_fe 5446 * IPv4 Multicast Forwarding Enable. 5447 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5448 * will be enabled. 5449 * Access: RW 5450 */ 5451 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5452 5453 /* reg_ritr_ipv6_mc_fe 5454 * IPv6 Multicast Forwarding Enable. 5455 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5456 * will be enabled. 5457 * Access: RW 5458 */ 5459 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5460 5461 /* reg_ritr_lb_en 5462 * Loop-back filter enable for unicast packets. 5463 * If the flag is set then loop-back filter for unicast packets is 5464 * implemented on the RIF. Multicast packets are always subject to 5465 * loop-back filtering. 5466 * Access: RW 5467 */ 5468 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5469 5470 /* reg_ritr_virtual_router 5471 * Virtual router ID associated with the router interface. 5472 * Access: RW 5473 */ 5474 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5475 5476 /* reg_ritr_mtu 5477 * Router interface MTU. 5478 * Access: RW 5479 */ 5480 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5481 5482 /* reg_ritr_if_swid 5483 * Switch partition ID. 5484 * Access: RW 5485 */ 5486 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5487 5488 /* reg_ritr_if_mac 5489 * Router interface MAC address. 5490 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5491 * Access: RW 5492 */ 5493 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5494 5495 /* reg_ritr_if_vrrp_id_ipv6 5496 * VRRP ID for IPv6 5497 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5498 * Access: RW 5499 */ 5500 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5501 5502 /* reg_ritr_if_vrrp_id_ipv4 5503 * VRRP ID for IPv4 5504 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5505 * Access: RW 5506 */ 5507 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5508 5509 /* VLAN Interface */ 5510 5511 /* reg_ritr_vlan_if_vid 5512 * VLAN ID. 5513 * Access: RW 5514 */ 5515 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5516 5517 /* FID Interface */ 5518 5519 /* reg_ritr_fid_if_fid 5520 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5521 * the vFID range are supported. 5522 * Access: RW 5523 */ 5524 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5525 5526 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5527 enum mlxsw_reg_ritr_if_type rif_type, 5528 u16 fid) 5529 { 5530 if (rif_type == MLXSW_REG_RITR_FID_IF) 5531 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5532 else 5533 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5534 } 5535 5536 /* Sub-port Interface */ 5537 5538 /* reg_ritr_sp_if_lag 5539 * LAG indication. When this bit is set the system_port field holds the 5540 * LAG identifier. 5541 * Access: RW 5542 */ 5543 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5544 5545 /* reg_ritr_sp_system_port 5546 * Port unique indentifier. When lag bit is set, this field holds the 5547 * lag_id in bits 0:9. 5548 * Access: RW 5549 */ 5550 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5551 5552 /* reg_ritr_sp_if_vid 5553 * VLAN ID. 5554 * Access: RW 5555 */ 5556 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5557 5558 /* Loopback Interface */ 5559 5560 enum mlxsw_reg_ritr_loopback_protocol { 5561 /* IPinIP IPv4 underlay Unicast */ 5562 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5563 /* IPinIP IPv6 underlay Unicast */ 5564 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5565 }; 5566 5567 /* reg_ritr_loopback_protocol 5568 * Access: RW 5569 */ 5570 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5571 5572 enum mlxsw_reg_ritr_loopback_ipip_type { 5573 /* Tunnel is IPinIP. */ 5574 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5575 /* Tunnel is GRE, no key. */ 5576 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5577 /* Tunnel is GRE, with a key. */ 5578 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5579 }; 5580 5581 /* reg_ritr_loopback_ipip_type 5582 * Encapsulation type. 5583 * Access: RW 5584 */ 5585 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 5586 5587 enum mlxsw_reg_ritr_loopback_ipip_options { 5588 /* The key is defined by gre_key. */ 5589 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 5590 }; 5591 5592 /* reg_ritr_loopback_ipip_options 5593 * Access: RW 5594 */ 5595 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 5596 5597 /* reg_ritr_loopback_ipip_uvr 5598 * Underlay Virtual Router ID. 5599 * Range is 0..cap_max_virtual_routers-1. 5600 * Reserved for Spectrum-2. 5601 * Access: RW 5602 */ 5603 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 5604 5605 /* reg_ritr_loopback_ipip_usip* 5606 * Encapsulation Underlay source IP. 5607 * Access: RW 5608 */ 5609 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 5610 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 5611 5612 /* reg_ritr_loopback_ipip_gre_key 5613 * GRE Key. 5614 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 5615 * Access: RW 5616 */ 5617 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 5618 5619 /* Shared between ingress/egress */ 5620 enum mlxsw_reg_ritr_counter_set_type { 5621 /* No Count. */ 5622 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 5623 /* Basic. Used for router interfaces, counting the following: 5624 * - Error and Discard counters. 5625 * - Unicast, Multicast and Broadcast counters. Sharing the 5626 * same set of counters for the different type of traffic 5627 * (IPv4, IPv6 and mpls). 5628 */ 5629 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 5630 }; 5631 5632 /* reg_ritr_ingress_counter_index 5633 * Counter Index for flow counter. 5634 * Access: RW 5635 */ 5636 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 5637 5638 /* reg_ritr_ingress_counter_set_type 5639 * Igress Counter Set Type for router interface counter. 5640 * Access: RW 5641 */ 5642 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 5643 5644 /* reg_ritr_egress_counter_index 5645 * Counter Index for flow counter. 5646 * Access: RW 5647 */ 5648 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 5649 5650 /* reg_ritr_egress_counter_set_type 5651 * Egress Counter Set Type for router interface counter. 5652 * Access: RW 5653 */ 5654 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 5655 5656 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 5657 bool enable, bool egress) 5658 { 5659 enum mlxsw_reg_ritr_counter_set_type set_type; 5660 5661 if (enable) 5662 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 5663 else 5664 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 5665 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 5666 5667 if (egress) 5668 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 5669 else 5670 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 5671 } 5672 5673 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 5674 { 5675 MLXSW_REG_ZERO(ritr, payload); 5676 mlxsw_reg_ritr_rif_set(payload, rif); 5677 } 5678 5679 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 5680 u16 system_port, u16 vid) 5681 { 5682 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 5683 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 5684 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 5685 } 5686 5687 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 5688 enum mlxsw_reg_ritr_if_type type, 5689 u16 rif, u16 vr_id, u16 mtu) 5690 { 5691 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 5692 5693 MLXSW_REG_ZERO(ritr, payload); 5694 mlxsw_reg_ritr_enable_set(payload, enable); 5695 mlxsw_reg_ritr_ipv4_set(payload, 1); 5696 mlxsw_reg_ritr_ipv6_set(payload, 1); 5697 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 5698 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 5699 mlxsw_reg_ritr_type_set(payload, type); 5700 mlxsw_reg_ritr_op_set(payload, op); 5701 mlxsw_reg_ritr_rif_set(payload, rif); 5702 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 5703 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 5704 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 5705 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 5706 mlxsw_reg_ritr_lb_en_set(payload, 1); 5707 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 5708 mlxsw_reg_ritr_mtu_set(payload, mtu); 5709 } 5710 5711 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 5712 { 5713 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 5714 } 5715 5716 static inline void 5717 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 5718 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5719 enum mlxsw_reg_ritr_loopback_ipip_options options, 5720 u16 uvr_id, u32 gre_key) 5721 { 5722 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 5723 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 5724 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 5725 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 5726 } 5727 5728 static inline void 5729 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 5730 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5731 enum mlxsw_reg_ritr_loopback_ipip_options options, 5732 u16 uvr_id, u32 usip, u32 gre_key) 5733 { 5734 mlxsw_reg_ritr_loopback_protocol_set(payload, 5735 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 5736 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 5737 uvr_id, gre_key); 5738 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 5739 } 5740 5741 /* RTAR - Router TCAM Allocation Register 5742 * -------------------------------------- 5743 * This register is used for allocation of regions in the TCAM table. 5744 */ 5745 #define MLXSW_REG_RTAR_ID 0x8004 5746 #define MLXSW_REG_RTAR_LEN 0x20 5747 5748 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 5749 5750 enum mlxsw_reg_rtar_op { 5751 MLXSW_REG_RTAR_OP_ALLOCATE, 5752 MLXSW_REG_RTAR_OP_RESIZE, 5753 MLXSW_REG_RTAR_OP_DEALLOCATE, 5754 }; 5755 5756 /* reg_rtar_op 5757 * Access: WO 5758 */ 5759 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 5760 5761 enum mlxsw_reg_rtar_key_type { 5762 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 5763 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 5764 }; 5765 5766 /* reg_rtar_key_type 5767 * TCAM key type for the region. 5768 * Access: WO 5769 */ 5770 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 5771 5772 /* reg_rtar_region_size 5773 * TCAM region size. When allocating/resizing this is the requested 5774 * size, the response is the actual size. 5775 * Note: Actual size may be larger than requested. 5776 * Reserved for op = Deallocate 5777 * Access: WO 5778 */ 5779 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 5780 5781 static inline void mlxsw_reg_rtar_pack(char *payload, 5782 enum mlxsw_reg_rtar_op op, 5783 enum mlxsw_reg_rtar_key_type key_type, 5784 u16 region_size) 5785 { 5786 MLXSW_REG_ZERO(rtar, payload); 5787 mlxsw_reg_rtar_op_set(payload, op); 5788 mlxsw_reg_rtar_key_type_set(payload, key_type); 5789 mlxsw_reg_rtar_region_size_set(payload, region_size); 5790 } 5791 5792 /* RATR - Router Adjacency Table Register 5793 * -------------------------------------- 5794 * The RATR register is used to configure the Router Adjacency (next-hop) 5795 * Table. 5796 */ 5797 #define MLXSW_REG_RATR_ID 0x8008 5798 #define MLXSW_REG_RATR_LEN 0x2C 5799 5800 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5801 5802 enum mlxsw_reg_ratr_op { 5803 /* Read */ 5804 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5805 /* Read and clear activity */ 5806 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 5807 /* Write Adjacency entry */ 5808 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 5809 /* Write Adjacency entry only if the activity is cleared. 5810 * The write may not succeed if the activity is set. There is not 5811 * direct feedback if the write has succeeded or not, however 5812 * the get will reveal the actual entry (SW can compare the get 5813 * response to the set command). 5814 */ 5815 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 5816 }; 5817 5818 /* reg_ratr_op 5819 * Note that Write operation may also be used for updating 5820 * counter_set_type and counter_index. In this case all other 5821 * fields must not be updated. 5822 * Access: OP 5823 */ 5824 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 5825 5826 /* reg_ratr_v 5827 * Valid bit. Indicates if the adjacency entry is valid. 5828 * Note: the device may need some time before reusing an invalidated 5829 * entry. During this time the entry can not be reused. It is 5830 * recommended to use another entry before reusing an invalidated 5831 * entry (e.g. software can put it at the end of the list for 5832 * reusing). Trying to access an invalidated entry not yet cleared 5833 * by the device results with failure indicating "Try Again" status. 5834 * When valid is '0' then egress_router_interface,trap_action, 5835 * adjacency_parameters and counters are reserved 5836 * Access: RW 5837 */ 5838 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 5839 5840 /* reg_ratr_a 5841 * Activity. Set for new entries. Set if a packet lookup has hit on 5842 * the specific entry. To clear the a bit, use "clear activity". 5843 * Access: RO 5844 */ 5845 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 5846 5847 enum mlxsw_reg_ratr_type { 5848 /* Ethernet */ 5849 MLXSW_REG_RATR_TYPE_ETHERNET, 5850 /* IPoIB Unicast without GRH. 5851 * Reserved for Spectrum. 5852 */ 5853 MLXSW_REG_RATR_TYPE_IPOIB_UC, 5854 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 5855 * adjacency). 5856 * Reserved for Spectrum. 5857 */ 5858 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 5859 /* IPoIB Multicast. 5860 * Reserved for Spectrum. 5861 */ 5862 MLXSW_REG_RATR_TYPE_IPOIB_MC, 5863 /* MPLS. 5864 * Reserved for SwitchX/-2. 5865 */ 5866 MLXSW_REG_RATR_TYPE_MPLS, 5867 /* IPinIP Encap. 5868 * Reserved for SwitchX/-2. 5869 */ 5870 MLXSW_REG_RATR_TYPE_IPIP, 5871 }; 5872 5873 /* reg_ratr_type 5874 * Adjacency entry type. 5875 * Access: RW 5876 */ 5877 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 5878 5879 /* reg_ratr_adjacency_index_low 5880 * Bits 15:0 of index into the adjacency table. 5881 * For SwitchX and SwitchX-2, the adjacency table is linear and 5882 * used for adjacency entries only. 5883 * For Spectrum, the index is to the KVD linear. 5884 * Access: Index 5885 */ 5886 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 5887 5888 /* reg_ratr_egress_router_interface 5889 * Range is 0 .. cap_max_router_interfaces - 1 5890 * Access: RW 5891 */ 5892 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 5893 5894 enum mlxsw_reg_ratr_trap_action { 5895 MLXSW_REG_RATR_TRAP_ACTION_NOP, 5896 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 5897 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 5898 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 5899 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 5900 }; 5901 5902 /* reg_ratr_trap_action 5903 * see mlxsw_reg_ratr_trap_action 5904 * Access: RW 5905 */ 5906 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 5907 5908 /* reg_ratr_adjacency_index_high 5909 * Bits 23:16 of the adjacency_index. 5910 * Access: Index 5911 */ 5912 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 5913 5914 enum mlxsw_reg_ratr_trap_id { 5915 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 5916 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 5917 }; 5918 5919 /* reg_ratr_trap_id 5920 * Trap ID to be reported to CPU. 5921 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5922 * For trap_action of NOP, MIRROR and DISCARD_ERROR 5923 * Access: RW 5924 */ 5925 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 5926 5927 /* reg_ratr_eth_destination_mac 5928 * MAC address of the destination next-hop. 5929 * Access: RW 5930 */ 5931 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 5932 5933 enum mlxsw_reg_ratr_ipip_type { 5934 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 5935 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 5936 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 5937 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 5938 }; 5939 5940 /* reg_ratr_ipip_type 5941 * Underlay destination ip type. 5942 * Note: the type field must match the protocol of the router interface. 5943 * Access: RW 5944 */ 5945 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 5946 5947 /* reg_ratr_ipip_ipv4_udip 5948 * Underlay ipv4 dip. 5949 * Reserved when ipip_type is IPv6. 5950 * Access: RW 5951 */ 5952 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 5953 5954 /* reg_ratr_ipip_ipv6_ptr 5955 * Pointer to IPv6 underlay destination ip address. 5956 * For Spectrum: Pointer to KVD linear space. 5957 * Access: RW 5958 */ 5959 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 5960 5961 enum mlxsw_reg_flow_counter_set_type { 5962 /* No count */ 5963 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 5964 /* Count packets and bytes */ 5965 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 5966 /* Count only packets */ 5967 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 5968 }; 5969 5970 /* reg_ratr_counter_set_type 5971 * Counter set type for flow counters 5972 * Access: RW 5973 */ 5974 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 5975 5976 /* reg_ratr_counter_index 5977 * Counter index for flow counters 5978 * Access: RW 5979 */ 5980 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 5981 5982 static inline void 5983 mlxsw_reg_ratr_pack(char *payload, 5984 enum mlxsw_reg_ratr_op op, bool valid, 5985 enum mlxsw_reg_ratr_type type, 5986 u32 adjacency_index, u16 egress_rif) 5987 { 5988 MLXSW_REG_ZERO(ratr, payload); 5989 mlxsw_reg_ratr_op_set(payload, op); 5990 mlxsw_reg_ratr_v_set(payload, valid); 5991 mlxsw_reg_ratr_type_set(payload, type); 5992 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 5993 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 5994 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 5995 } 5996 5997 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 5998 const char *dest_mac) 5999 { 6000 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6001 } 6002 6003 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6004 { 6005 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6006 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6007 } 6008 6009 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6010 bool counter_enable) 6011 { 6012 enum mlxsw_reg_flow_counter_set_type set_type; 6013 6014 if (counter_enable) 6015 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6016 else 6017 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6018 6019 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6020 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6021 } 6022 6023 /* RDPM - Router DSCP to Priority Mapping 6024 * -------------------------------------- 6025 * Controls the mapping from DSCP field to switch priority on routed packets 6026 */ 6027 #define MLXSW_REG_RDPM_ID 0x8009 6028 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6029 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6030 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6031 #define MLXSW_REG_RDPM_LEN 0x40 6032 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6033 MLXSW_REG_RDPM_LEN - \ 6034 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6035 6036 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6037 6038 /* reg_dscp_entry_e 6039 * Enable update of the specific entry 6040 * Access: Index 6041 */ 6042 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6043 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6044 6045 /* reg_dscp_entry_prio 6046 * Switch Priority 6047 * Access: RW 6048 */ 6049 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6050 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6051 6052 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6053 u8 prio) 6054 { 6055 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6056 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6057 } 6058 6059 /* RICNT - Router Interface Counter Register 6060 * ----------------------------------------- 6061 * The RICNT register retrieves per port performance counters 6062 */ 6063 #define MLXSW_REG_RICNT_ID 0x800B 6064 #define MLXSW_REG_RICNT_LEN 0x100 6065 6066 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6067 6068 /* reg_ricnt_counter_index 6069 * Counter index 6070 * Access: RW 6071 */ 6072 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6073 6074 enum mlxsw_reg_ricnt_counter_set_type { 6075 /* No Count. */ 6076 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6077 /* Basic. Used for router interfaces, counting the following: 6078 * - Error and Discard counters. 6079 * - Unicast, Multicast and Broadcast counters. Sharing the 6080 * same set of counters for the different type of traffic 6081 * (IPv4, IPv6 and mpls). 6082 */ 6083 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6084 }; 6085 6086 /* reg_ricnt_counter_set_type 6087 * Counter Set Type for router interface counter 6088 * Access: RW 6089 */ 6090 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6091 6092 enum mlxsw_reg_ricnt_opcode { 6093 /* Nop. Supported only for read access*/ 6094 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6095 /* Clear. Setting the clr bit will reset the counter value for 6096 * all counters of the specified Router Interface. 6097 */ 6098 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6099 }; 6100 6101 /* reg_ricnt_opcode 6102 * Opcode 6103 * Access: RW 6104 */ 6105 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6106 6107 /* reg_ricnt_good_unicast_packets 6108 * good unicast packets. 6109 * Access: RW 6110 */ 6111 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6112 6113 /* reg_ricnt_good_multicast_packets 6114 * good multicast packets. 6115 * Access: RW 6116 */ 6117 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6118 6119 /* reg_ricnt_good_broadcast_packets 6120 * good broadcast packets 6121 * Access: RW 6122 */ 6123 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6124 6125 /* reg_ricnt_good_unicast_bytes 6126 * A count of L3 data and padding octets not including L2 headers 6127 * for good unicast frames. 6128 * Access: RW 6129 */ 6130 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6131 6132 /* reg_ricnt_good_multicast_bytes 6133 * A count of L3 data and padding octets not including L2 headers 6134 * for good multicast frames. 6135 * Access: RW 6136 */ 6137 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6138 6139 /* reg_ritr_good_broadcast_bytes 6140 * A count of L3 data and padding octets not including L2 headers 6141 * for good broadcast frames. 6142 * Access: RW 6143 */ 6144 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6145 6146 /* reg_ricnt_error_packets 6147 * A count of errored frames that do not pass the router checks. 6148 * Access: RW 6149 */ 6150 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6151 6152 /* reg_ricnt_discrad_packets 6153 * A count of non-errored frames that do not pass the router checks. 6154 * Access: RW 6155 */ 6156 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6157 6158 /* reg_ricnt_error_bytes 6159 * A count of L3 data and padding octets not including L2 headers 6160 * for errored frames. 6161 * Access: RW 6162 */ 6163 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6164 6165 /* reg_ricnt_discard_bytes 6166 * A count of L3 data and padding octets not including L2 headers 6167 * for non-errored frames that do not pass the router checks. 6168 * Access: RW 6169 */ 6170 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6171 6172 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6173 enum mlxsw_reg_ricnt_opcode op) 6174 { 6175 MLXSW_REG_ZERO(ricnt, payload); 6176 mlxsw_reg_ricnt_op_set(payload, op); 6177 mlxsw_reg_ricnt_counter_index_set(payload, index); 6178 mlxsw_reg_ricnt_counter_set_type_set(payload, 6179 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6180 } 6181 6182 /* RRCR - Router Rules Copy Register Layout 6183 * ---------------------------------------- 6184 * This register is used for moving and copying route entry rules. 6185 */ 6186 #define MLXSW_REG_RRCR_ID 0x800F 6187 #define MLXSW_REG_RRCR_LEN 0x24 6188 6189 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6190 6191 enum mlxsw_reg_rrcr_op { 6192 /* Move rules */ 6193 MLXSW_REG_RRCR_OP_MOVE, 6194 /* Copy rules */ 6195 MLXSW_REG_RRCR_OP_COPY, 6196 }; 6197 6198 /* reg_rrcr_op 6199 * Access: WO 6200 */ 6201 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6202 6203 /* reg_rrcr_offset 6204 * Offset within the region from which to copy/move. 6205 * Access: Index 6206 */ 6207 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6208 6209 /* reg_rrcr_size 6210 * The number of rules to copy/move. 6211 * Access: WO 6212 */ 6213 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6214 6215 /* reg_rrcr_table_id 6216 * Identifier of the table on which to perform the operation. Encoding is the 6217 * same as in RTAR.key_type 6218 * Access: Index 6219 */ 6220 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6221 6222 /* reg_rrcr_dest_offset 6223 * Offset within the region to which to copy/move 6224 * Access: Index 6225 */ 6226 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6227 6228 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6229 u16 offset, u16 size, 6230 enum mlxsw_reg_rtar_key_type table_id, 6231 u16 dest_offset) 6232 { 6233 MLXSW_REG_ZERO(rrcr, payload); 6234 mlxsw_reg_rrcr_op_set(payload, op); 6235 mlxsw_reg_rrcr_offset_set(payload, offset); 6236 mlxsw_reg_rrcr_size_set(payload, size); 6237 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6238 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6239 } 6240 6241 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6242 * ------------------------------------------------------- 6243 * RALTA is used to allocate the LPM trees of the SHSPM method. 6244 */ 6245 #define MLXSW_REG_RALTA_ID 0x8010 6246 #define MLXSW_REG_RALTA_LEN 0x04 6247 6248 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6249 6250 /* reg_ralta_op 6251 * opcode (valid for Write, must be 0 on Read) 6252 * 0 - allocate a tree 6253 * 1 - deallocate a tree 6254 * Access: OP 6255 */ 6256 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6257 6258 enum mlxsw_reg_ralxx_protocol { 6259 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6260 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6261 }; 6262 6263 /* reg_ralta_protocol 6264 * Protocol. 6265 * Deallocation opcode: Reserved. 6266 * Access: RW 6267 */ 6268 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6269 6270 /* reg_ralta_tree_id 6271 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6272 * the tree identifier (managed by software). 6273 * Note that tree_id 0 is allocated for a default-route tree. 6274 * Access: Index 6275 */ 6276 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6277 6278 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6279 enum mlxsw_reg_ralxx_protocol protocol, 6280 u8 tree_id) 6281 { 6282 MLXSW_REG_ZERO(ralta, payload); 6283 mlxsw_reg_ralta_op_set(payload, !alloc); 6284 mlxsw_reg_ralta_protocol_set(payload, protocol); 6285 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6286 } 6287 6288 /* RALST - Router Algorithmic LPM Structure Tree Register 6289 * ------------------------------------------------------ 6290 * RALST is used to set and query the structure of an LPM tree. 6291 * The structure of the tree must be sorted as a sorted binary tree, while 6292 * each node is a bin that is tagged as the length of the prefixes the lookup 6293 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6294 * of X bits to match with the destination address. The bin 0 indicates 6295 * the default action, when there is no match of any prefix. 6296 */ 6297 #define MLXSW_REG_RALST_ID 0x8011 6298 #define MLXSW_REG_RALST_LEN 0x104 6299 6300 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6301 6302 /* reg_ralst_root_bin 6303 * The bin number of the root bin. 6304 * 0<root_bin=<(length of IP address) 6305 * For a default-route tree configure 0xff 6306 * Access: RW 6307 */ 6308 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6309 6310 /* reg_ralst_tree_id 6311 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6312 * Access: Index 6313 */ 6314 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6315 6316 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6317 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6318 #define MLXSW_REG_RALST_BIN_COUNT 128 6319 6320 /* reg_ralst_left_child_bin 6321 * Holding the children of the bin according to the stored tree's structure. 6322 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6323 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6324 * Access: RW 6325 */ 6326 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6327 6328 /* reg_ralst_right_child_bin 6329 * Holding the children of the bin according to the stored tree's structure. 6330 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6331 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6332 * Access: RW 6333 */ 6334 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6335 false); 6336 6337 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6338 { 6339 MLXSW_REG_ZERO(ralst, payload); 6340 6341 /* Initialize all bins to have no left or right child */ 6342 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6343 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6344 6345 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6346 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6347 } 6348 6349 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6350 u8 left_child_bin, 6351 u8 right_child_bin) 6352 { 6353 int bin_index = bin_number - 1; 6354 6355 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6356 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6357 right_child_bin); 6358 } 6359 6360 /* RALTB - Router Algorithmic LPM Tree Binding Register 6361 * ---------------------------------------------------- 6362 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6363 */ 6364 #define MLXSW_REG_RALTB_ID 0x8012 6365 #define MLXSW_REG_RALTB_LEN 0x04 6366 6367 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6368 6369 /* reg_raltb_virtual_router 6370 * Virtual Router ID 6371 * Range is 0..cap_max_virtual_routers-1 6372 * Access: Index 6373 */ 6374 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6375 6376 /* reg_raltb_protocol 6377 * Protocol. 6378 * Access: Index 6379 */ 6380 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6381 6382 /* reg_raltb_tree_id 6383 * Tree to be used for the {virtual_router, protocol} 6384 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6385 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6386 * Access: RW 6387 */ 6388 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6389 6390 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6391 enum mlxsw_reg_ralxx_protocol protocol, 6392 u8 tree_id) 6393 { 6394 MLXSW_REG_ZERO(raltb, payload); 6395 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6396 mlxsw_reg_raltb_protocol_set(payload, protocol); 6397 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6398 } 6399 6400 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6401 * ----------------------------------------------------- 6402 * RALUE is used to configure and query LPM entries that serve 6403 * the Unicast protocols. 6404 */ 6405 #define MLXSW_REG_RALUE_ID 0x8013 6406 #define MLXSW_REG_RALUE_LEN 0x38 6407 6408 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6409 6410 /* reg_ralue_protocol 6411 * Protocol. 6412 * Access: Index 6413 */ 6414 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6415 6416 enum mlxsw_reg_ralue_op { 6417 /* Read operation. If entry doesn't exist, the operation fails. */ 6418 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6419 /* Clear on read operation. Used to read entry and 6420 * clear Activity bit. 6421 */ 6422 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6423 /* Write operation. Used to write a new entry to the table. All RW 6424 * fields are written for new entry. Activity bit is set 6425 * for new entries. 6426 */ 6427 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6428 /* Update operation. Used to update an existing route entry and 6429 * only update the RW fields that are detailed in the field 6430 * op_u_mask. If entry doesn't exist, the operation fails. 6431 */ 6432 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6433 /* Clear activity. The Activity bit (the field a) is cleared 6434 * for the entry. 6435 */ 6436 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6437 /* Delete operation. Used to delete an existing entry. If entry 6438 * doesn't exist, the operation fails. 6439 */ 6440 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6441 }; 6442 6443 /* reg_ralue_op 6444 * Operation. 6445 * Access: OP 6446 */ 6447 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6448 6449 /* reg_ralue_a 6450 * Activity. Set for new entries. Set if a packet lookup has hit on the 6451 * specific entry, only if the entry is a route. To clear the a bit, use 6452 * "clear activity" op. 6453 * Enabled by activity_dis in RGCR 6454 * Access: RO 6455 */ 6456 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6457 6458 /* reg_ralue_virtual_router 6459 * Virtual Router ID 6460 * Range is 0..cap_max_virtual_routers-1 6461 * Access: Index 6462 */ 6463 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6464 6465 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6466 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6467 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6468 6469 /* reg_ralue_op_u_mask 6470 * opcode update mask. 6471 * On read operation, this field is reserved. 6472 * This field is valid for update opcode, otherwise - reserved. 6473 * This field is a bitmask of the fields that should be updated. 6474 * Access: WO 6475 */ 6476 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6477 6478 /* reg_ralue_prefix_len 6479 * Number of bits in the prefix of the LPM route. 6480 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6481 * two entries in the physical HW table. 6482 * Access: Index 6483 */ 6484 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6485 6486 /* reg_ralue_dip* 6487 * The prefix of the route or of the marker that the object of the LPM 6488 * is compared with. The most significant bits of the dip are the prefix. 6489 * The least significant bits must be '0' if the prefix_len is smaller 6490 * than 128 for IPv6 or smaller than 32 for IPv4. 6491 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6492 * Access: Index 6493 */ 6494 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6495 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6496 6497 enum mlxsw_reg_ralue_entry_type { 6498 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6499 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6500 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6501 }; 6502 6503 /* reg_ralue_entry_type 6504 * Entry type. 6505 * Note - for Marker entries, the action_type and action fields are reserved. 6506 * Access: RW 6507 */ 6508 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6509 6510 /* reg_ralue_bmp_len 6511 * The best match prefix length in the case that there is no match for 6512 * longer prefixes. 6513 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6514 * Note for any update operation with entry_type modification this 6515 * field must be set. 6516 * Access: RW 6517 */ 6518 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6519 6520 enum mlxsw_reg_ralue_action_type { 6521 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6522 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6523 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6524 }; 6525 6526 /* reg_ralue_action_type 6527 * Action Type 6528 * Indicates how the IP address is connected. 6529 * It can be connected to a local subnet through local_erif or can be 6530 * on a remote subnet connected through a next-hop router, 6531 * or transmitted to the CPU. 6532 * Reserved when entry_type = MARKER_ENTRY 6533 * Access: RW 6534 */ 6535 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6536 6537 enum mlxsw_reg_ralue_trap_action { 6538 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6539 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6540 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6541 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6542 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6543 }; 6544 6545 /* reg_ralue_trap_action 6546 * Trap action. 6547 * For IP2ME action, only NOP and MIRROR are possible. 6548 * Access: RW 6549 */ 6550 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6551 6552 /* reg_ralue_trap_id 6553 * Trap ID to be reported to CPU. 6554 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6555 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6556 * Access: RW 6557 */ 6558 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6559 6560 /* reg_ralue_adjacency_index 6561 * Points to the first entry of the group-based ECMP. 6562 * Only relevant in case of REMOTE action. 6563 * Access: RW 6564 */ 6565 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6566 6567 /* reg_ralue_ecmp_size 6568 * Amount of sequential entries starting 6569 * from the adjacency_index (the number of ECMPs). 6570 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6571 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6572 * Only relevant in case of REMOTE action. 6573 * Access: RW 6574 */ 6575 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6576 6577 /* reg_ralue_local_erif 6578 * Egress Router Interface. 6579 * Only relevant in case of LOCAL action. 6580 * Access: RW 6581 */ 6582 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 6583 6584 /* reg_ralue_ip2me_v 6585 * Valid bit for the tunnel_ptr field. 6586 * If valid = 0 then trap to CPU as IP2ME trap ID. 6587 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 6588 * decapsulation then tunnel decapsulation is done. 6589 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 6590 * decapsulation then trap as IP2ME trap ID. 6591 * Only relevant in case of IP2ME action. 6592 * Access: RW 6593 */ 6594 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 6595 6596 /* reg_ralue_ip2me_tunnel_ptr 6597 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 6598 * For Spectrum, pointer to KVD Linear. 6599 * Only relevant in case of IP2ME action. 6600 * Access: RW 6601 */ 6602 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 6603 6604 static inline void mlxsw_reg_ralue_pack(char *payload, 6605 enum mlxsw_reg_ralxx_protocol protocol, 6606 enum mlxsw_reg_ralue_op op, 6607 u16 virtual_router, u8 prefix_len) 6608 { 6609 MLXSW_REG_ZERO(ralue, payload); 6610 mlxsw_reg_ralue_protocol_set(payload, protocol); 6611 mlxsw_reg_ralue_op_set(payload, op); 6612 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 6613 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 6614 mlxsw_reg_ralue_entry_type_set(payload, 6615 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 6616 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 6617 } 6618 6619 static inline void mlxsw_reg_ralue_pack4(char *payload, 6620 enum mlxsw_reg_ralxx_protocol protocol, 6621 enum mlxsw_reg_ralue_op op, 6622 u16 virtual_router, u8 prefix_len, 6623 u32 dip) 6624 { 6625 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6626 mlxsw_reg_ralue_dip4_set(payload, dip); 6627 } 6628 6629 static inline void mlxsw_reg_ralue_pack6(char *payload, 6630 enum mlxsw_reg_ralxx_protocol protocol, 6631 enum mlxsw_reg_ralue_op op, 6632 u16 virtual_router, u8 prefix_len, 6633 const void *dip) 6634 { 6635 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6636 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 6637 } 6638 6639 static inline void 6640 mlxsw_reg_ralue_act_remote_pack(char *payload, 6641 enum mlxsw_reg_ralue_trap_action trap_action, 6642 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 6643 { 6644 mlxsw_reg_ralue_action_type_set(payload, 6645 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 6646 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6647 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6648 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 6649 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 6650 } 6651 6652 static inline void 6653 mlxsw_reg_ralue_act_local_pack(char *payload, 6654 enum mlxsw_reg_ralue_trap_action trap_action, 6655 u16 trap_id, u16 local_erif) 6656 { 6657 mlxsw_reg_ralue_action_type_set(payload, 6658 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 6659 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6660 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6661 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 6662 } 6663 6664 static inline void 6665 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 6666 { 6667 mlxsw_reg_ralue_action_type_set(payload, 6668 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6669 } 6670 6671 static inline void 6672 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 6673 { 6674 mlxsw_reg_ralue_action_type_set(payload, 6675 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6676 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 6677 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 6678 } 6679 6680 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 6681 * ---------------------------------------------------------- 6682 * The RAUHT register is used to configure and query the Unicast Host table in 6683 * devices that implement the Algorithmic LPM. 6684 */ 6685 #define MLXSW_REG_RAUHT_ID 0x8014 6686 #define MLXSW_REG_RAUHT_LEN 0x74 6687 6688 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 6689 6690 enum mlxsw_reg_rauht_type { 6691 MLXSW_REG_RAUHT_TYPE_IPV4, 6692 MLXSW_REG_RAUHT_TYPE_IPV6, 6693 }; 6694 6695 /* reg_rauht_type 6696 * Access: Index 6697 */ 6698 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 6699 6700 enum mlxsw_reg_rauht_op { 6701 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 6702 /* Read operation */ 6703 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 6704 /* Clear on read operation. Used to read entry and clear 6705 * activity bit. 6706 */ 6707 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 6708 /* Add. Used to write a new entry to the table. All R/W fields are 6709 * relevant for new entry. Activity bit is set for new entries. 6710 */ 6711 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 6712 /* Update action. Used to update an existing route entry and 6713 * only update the following fields: 6714 * trap_action, trap_id, mac, counter_set_type, counter_index 6715 */ 6716 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 6717 /* Clear activity. A bit is cleared for the entry. */ 6718 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 6719 /* Delete entry */ 6720 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 6721 /* Delete all host entries on a RIF. In this command, dip 6722 * field is reserved. 6723 */ 6724 }; 6725 6726 /* reg_rauht_op 6727 * Access: OP 6728 */ 6729 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 6730 6731 /* reg_rauht_a 6732 * Activity. Set for new entries. Set if a packet lookup has hit on 6733 * the specific entry. 6734 * To clear the a bit, use "clear activity" op. 6735 * Enabled by activity_dis in RGCR 6736 * Access: RO 6737 */ 6738 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 6739 6740 /* reg_rauht_rif 6741 * Router Interface 6742 * Access: Index 6743 */ 6744 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 6745 6746 /* reg_rauht_dip* 6747 * Destination address. 6748 * Access: Index 6749 */ 6750 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 6751 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 6752 6753 enum mlxsw_reg_rauht_trap_action { 6754 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 6755 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 6756 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 6757 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 6758 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 6759 }; 6760 6761 /* reg_rauht_trap_action 6762 * Access: RW 6763 */ 6764 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 6765 6766 enum mlxsw_reg_rauht_trap_id { 6767 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 6768 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 6769 }; 6770 6771 /* reg_rauht_trap_id 6772 * Trap ID to be reported to CPU. 6773 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6774 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 6775 * trap_id is reserved. 6776 * Access: RW 6777 */ 6778 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 6779 6780 /* reg_rauht_counter_set_type 6781 * Counter set type for flow counters 6782 * Access: RW 6783 */ 6784 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 6785 6786 /* reg_rauht_counter_index 6787 * Counter index for flow counters 6788 * Access: RW 6789 */ 6790 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 6791 6792 /* reg_rauht_mac 6793 * MAC address. 6794 * Access: RW 6795 */ 6796 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 6797 6798 static inline void mlxsw_reg_rauht_pack(char *payload, 6799 enum mlxsw_reg_rauht_op op, u16 rif, 6800 const char *mac) 6801 { 6802 MLXSW_REG_ZERO(rauht, payload); 6803 mlxsw_reg_rauht_op_set(payload, op); 6804 mlxsw_reg_rauht_rif_set(payload, rif); 6805 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 6806 } 6807 6808 static inline void mlxsw_reg_rauht_pack4(char *payload, 6809 enum mlxsw_reg_rauht_op op, u16 rif, 6810 const char *mac, u32 dip) 6811 { 6812 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6813 mlxsw_reg_rauht_dip4_set(payload, dip); 6814 } 6815 6816 static inline void mlxsw_reg_rauht_pack6(char *payload, 6817 enum mlxsw_reg_rauht_op op, u16 rif, 6818 const char *mac, const char *dip) 6819 { 6820 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6821 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 6822 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 6823 } 6824 6825 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 6826 u64 counter_index) 6827 { 6828 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 6829 mlxsw_reg_rauht_counter_set_type_set(payload, 6830 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 6831 } 6832 6833 /* RALEU - Router Algorithmic LPM ECMP Update Register 6834 * --------------------------------------------------- 6835 * The register enables updating the ECMP section in the action for multiple 6836 * LPM Unicast entries in a single operation. The update is executed to 6837 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 6838 */ 6839 #define MLXSW_REG_RALEU_ID 0x8015 6840 #define MLXSW_REG_RALEU_LEN 0x28 6841 6842 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 6843 6844 /* reg_raleu_protocol 6845 * Protocol. 6846 * Access: Index 6847 */ 6848 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 6849 6850 /* reg_raleu_virtual_router 6851 * Virtual Router ID 6852 * Range is 0..cap_max_virtual_routers-1 6853 * Access: Index 6854 */ 6855 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 6856 6857 /* reg_raleu_adjacency_index 6858 * Adjacency Index used for matching on the existing entries. 6859 * Access: Index 6860 */ 6861 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 6862 6863 /* reg_raleu_ecmp_size 6864 * ECMP Size used for matching on the existing entries. 6865 * Access: Index 6866 */ 6867 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 6868 6869 /* reg_raleu_new_adjacency_index 6870 * New Adjacency Index. 6871 * Access: WO 6872 */ 6873 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 6874 6875 /* reg_raleu_new_ecmp_size 6876 * New ECMP Size. 6877 * Access: WO 6878 */ 6879 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 6880 6881 static inline void mlxsw_reg_raleu_pack(char *payload, 6882 enum mlxsw_reg_ralxx_protocol protocol, 6883 u16 virtual_router, 6884 u32 adjacency_index, u16 ecmp_size, 6885 u32 new_adjacency_index, 6886 u16 new_ecmp_size) 6887 { 6888 MLXSW_REG_ZERO(raleu, payload); 6889 mlxsw_reg_raleu_protocol_set(payload, protocol); 6890 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 6891 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 6892 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 6893 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 6894 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 6895 } 6896 6897 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 6898 * ---------------------------------------------------------------- 6899 * The RAUHTD register allows dumping entries from the Router Unicast Host 6900 * Table. For a given session an entry is dumped no more than one time. The 6901 * first RAUHTD access after reset is a new session. A session ends when the 6902 * num_rec response is smaller than num_rec request or for IPv4 when the 6903 * num_entries is smaller than 4. The clear activity affect the current session 6904 * or the last session if a new session has not started. 6905 */ 6906 #define MLXSW_REG_RAUHTD_ID 0x8018 6907 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 6908 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 6909 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 6910 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 6911 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 6912 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 6913 6914 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 6915 6916 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 6917 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 6918 6919 /* reg_rauhtd_filter_fields 6920 * if a bit is '0' then the relevant field is ignored and dump is done 6921 * regardless of the field value 6922 * Bit0 - filter by activity: entry_a 6923 * Bit3 - filter by entry rip: entry_rif 6924 * Access: Index 6925 */ 6926 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 6927 6928 enum mlxsw_reg_rauhtd_op { 6929 MLXSW_REG_RAUHTD_OP_DUMP, 6930 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 6931 }; 6932 6933 /* reg_rauhtd_op 6934 * Access: OP 6935 */ 6936 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 6937 6938 /* reg_rauhtd_num_rec 6939 * At request: number of records requested 6940 * At response: number of records dumped 6941 * For IPv4, each record has 4 entries at request and up to 4 entries 6942 * at response 6943 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 6944 * Access: Index 6945 */ 6946 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 6947 6948 /* reg_rauhtd_entry_a 6949 * Dump only if activity has value of entry_a 6950 * Reserved if filter_fields bit0 is '0' 6951 * Access: Index 6952 */ 6953 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 6954 6955 enum mlxsw_reg_rauhtd_type { 6956 MLXSW_REG_RAUHTD_TYPE_IPV4, 6957 MLXSW_REG_RAUHTD_TYPE_IPV6, 6958 }; 6959 6960 /* reg_rauhtd_type 6961 * Dump only if record type is: 6962 * 0 - IPv4 6963 * 1 - IPv6 6964 * Access: Index 6965 */ 6966 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 6967 6968 /* reg_rauhtd_entry_rif 6969 * Dump only if RIF has value of entry_rif 6970 * Reserved if filter_fields bit3 is '0' 6971 * Access: Index 6972 */ 6973 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 6974 6975 static inline void mlxsw_reg_rauhtd_pack(char *payload, 6976 enum mlxsw_reg_rauhtd_type type) 6977 { 6978 MLXSW_REG_ZERO(rauhtd, payload); 6979 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 6980 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 6981 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 6982 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 6983 mlxsw_reg_rauhtd_type_set(payload, type); 6984 } 6985 6986 /* reg_rauhtd_ipv4_rec_num_entries 6987 * Number of valid entries in this record: 6988 * 0 - 1 valid entry 6989 * 1 - 2 valid entries 6990 * 2 - 3 valid entries 6991 * 3 - 4 valid entries 6992 * Access: RO 6993 */ 6994 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 6995 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 6996 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 6997 6998 /* reg_rauhtd_rec_type 6999 * Record type. 7000 * 0 - IPv4 7001 * 1 - IPv6 7002 * Access: RO 7003 */ 7004 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7005 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7006 7007 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7008 7009 /* reg_rauhtd_ipv4_ent_a 7010 * Activity. Set for new entries. Set if a packet lookup has hit on the 7011 * specific entry. 7012 * Access: RO 7013 */ 7014 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7015 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7016 7017 /* reg_rauhtd_ipv4_ent_rif 7018 * Router interface. 7019 * Access: RO 7020 */ 7021 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7022 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7023 7024 /* reg_rauhtd_ipv4_ent_dip 7025 * Destination IPv4 address. 7026 * Access: RO 7027 */ 7028 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7029 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7030 7031 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7032 7033 /* reg_rauhtd_ipv6_ent_a 7034 * Activity. Set for new entries. Set if a packet lookup has hit on the 7035 * specific entry. 7036 * Access: RO 7037 */ 7038 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7039 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7040 7041 /* reg_rauhtd_ipv6_ent_rif 7042 * Router interface. 7043 * Access: RO 7044 */ 7045 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7046 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7047 7048 /* reg_rauhtd_ipv6_ent_dip 7049 * Destination IPv6 address. 7050 * Access: RO 7051 */ 7052 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7053 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7054 7055 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7056 int ent_index, u16 *p_rif, 7057 u32 *p_dip) 7058 { 7059 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7060 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7061 } 7062 7063 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7064 int rec_index, u16 *p_rif, 7065 char *p_dip) 7066 { 7067 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7068 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7069 } 7070 7071 /* RTDP - Routing Tunnel Decap Properties Register 7072 * ----------------------------------------------- 7073 * The RTDP register is used for configuring the tunnel decap properties of NVE 7074 * and IPinIP. 7075 */ 7076 #define MLXSW_REG_RTDP_ID 0x8020 7077 #define MLXSW_REG_RTDP_LEN 0x44 7078 7079 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7080 7081 enum mlxsw_reg_rtdp_type { 7082 MLXSW_REG_RTDP_TYPE_NVE, 7083 MLXSW_REG_RTDP_TYPE_IPIP, 7084 }; 7085 7086 /* reg_rtdp_type 7087 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7088 * Access: RW 7089 */ 7090 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7091 7092 /* reg_rtdp_tunnel_index 7093 * Index to the Decap entry. 7094 * For Spectrum, Index to KVD Linear. 7095 * Access: Index 7096 */ 7097 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7098 7099 /* IPinIP */ 7100 7101 /* reg_rtdp_ipip_irif 7102 * Ingress Router Interface for the overlay router 7103 * Access: RW 7104 */ 7105 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7106 7107 enum mlxsw_reg_rtdp_ipip_sip_check { 7108 /* No sip checks. */ 7109 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7110 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7111 * equal ipv4_usip. 7112 */ 7113 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7114 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7115 * equal ipv6_usip. 7116 */ 7117 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7118 }; 7119 7120 /* reg_rtdp_ipip_sip_check 7121 * SIP check to perform. If decapsulation failed due to these configurations 7122 * then trap_id is IPIP_DECAP_ERROR. 7123 * Access: RW 7124 */ 7125 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7126 7127 /* If set, allow decapsulation of IPinIP (without GRE). */ 7128 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7129 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7130 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7131 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7132 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7133 7134 /* reg_rtdp_ipip_type_check 7135 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7136 * these configurations then trap_id is IPIP_DECAP_ERROR. 7137 * Access: RW 7138 */ 7139 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7140 7141 /* reg_rtdp_ipip_gre_key_check 7142 * Whether GRE key should be checked. When check is enabled: 7143 * - A packet received as IPinIP (without GRE) will always pass. 7144 * - A packet received as IPinGREinIP without a key will not pass the check. 7145 * - A packet received as IPinGREinIP with a key will pass the check only if the 7146 * key in the packet is equal to expected_gre_key. 7147 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7148 * Access: RW 7149 */ 7150 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7151 7152 /* reg_rtdp_ipip_ipv4_usip 7153 * Underlay IPv4 address for ipv4 source address check. 7154 * Reserved when sip_check is not '1'. 7155 * Access: RW 7156 */ 7157 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7158 7159 /* reg_rtdp_ipip_ipv6_usip_ptr 7160 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7161 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7162 * is to the KVD linear. 7163 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7164 * Access: RW 7165 */ 7166 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7167 7168 /* reg_rtdp_ipip_expected_gre_key 7169 * GRE key for checking. 7170 * Reserved when gre_key_check is '0'. 7171 * Access: RW 7172 */ 7173 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7174 7175 static inline void mlxsw_reg_rtdp_pack(char *payload, 7176 enum mlxsw_reg_rtdp_type type, 7177 u32 tunnel_index) 7178 { 7179 MLXSW_REG_ZERO(rtdp, payload); 7180 mlxsw_reg_rtdp_type_set(payload, type); 7181 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7182 } 7183 7184 static inline void 7185 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7186 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7187 unsigned int type_check, bool gre_key_check, 7188 u32 ipv4_usip, u32 expected_gre_key) 7189 { 7190 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7191 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7192 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7193 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7194 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7195 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7196 } 7197 7198 /* RIGR-V2 - Router Interface Group Register Version 2 7199 * --------------------------------------------------- 7200 * The RIGR_V2 register is used to add, remove and query egress interface list 7201 * of a multicast forwarding entry. 7202 */ 7203 #define MLXSW_REG_RIGR2_ID 0x8023 7204 #define MLXSW_REG_RIGR2_LEN 0xB0 7205 7206 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7207 7208 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7209 7210 /* reg_rigr2_rigr_index 7211 * KVD Linear index. 7212 * Access: Index 7213 */ 7214 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7215 7216 /* reg_rigr2_vnext 7217 * Next RIGR Index is valid. 7218 * Access: RW 7219 */ 7220 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7221 7222 /* reg_rigr2_next_rigr_index 7223 * Next RIGR Index. The index is to the KVD linear. 7224 * Reserved when vnxet = '0'. 7225 * Access: RW 7226 */ 7227 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7228 7229 /* reg_rigr2_vrmid 7230 * RMID Index is valid. 7231 * Access: RW 7232 */ 7233 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7234 7235 /* reg_rigr2_rmid_index 7236 * RMID Index. 7237 * Range 0 .. max_mid - 1 7238 * Reserved when vrmid = '0'. 7239 * The index is to the Port Group Table (PGT) 7240 * Access: RW 7241 */ 7242 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7243 7244 /* reg_rigr2_erif_entry_v 7245 * Egress Router Interface is valid. 7246 * Note that low-entries must be set if high-entries are set. For 7247 * example: if erif_entry[2].v is set then erif_entry[1].v and 7248 * erif_entry[0].v must be set. 7249 * Index can be from 0 to cap_mc_erif_list_entries-1 7250 * Access: RW 7251 */ 7252 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7253 7254 /* reg_rigr2_erif_entry_erif 7255 * Egress Router Interface. 7256 * Valid range is from 0 to cap_max_router_interfaces - 1 7257 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7258 * Access: RW 7259 */ 7260 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7261 7262 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7263 bool vnext, u32 next_rigr_index) 7264 { 7265 MLXSW_REG_ZERO(rigr2, payload); 7266 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7267 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7268 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7269 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7270 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7271 } 7272 7273 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7274 bool v, u16 erif) 7275 { 7276 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7277 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7278 } 7279 7280 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7281 * ------------------------------------------------------ 7282 */ 7283 #define MLXSW_REG_RECR2_ID 0x8025 7284 #define MLXSW_REG_RECR2_LEN 0x38 7285 7286 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7287 7288 /* reg_recr2_pp 7289 * Per-port configuration 7290 * Access: Index 7291 */ 7292 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7293 7294 /* reg_recr2_sh 7295 * Symmetric hash 7296 * Access: RW 7297 */ 7298 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7299 7300 /* reg_recr2_seed 7301 * Seed 7302 * Access: RW 7303 */ 7304 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7305 7306 enum { 7307 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7308 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7309 /* Enable IPv4 fields if packet is TCP or UDP */ 7310 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7311 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7312 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7313 /* Enable IPv6 fields if packet is TCP or UDP */ 7314 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7315 /* Enable TCP/UDP header fields if packet is IPv4 */ 7316 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7317 /* Enable TCP/UDP header fields if packet is IPv6 */ 7318 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7319 }; 7320 7321 /* reg_recr2_outer_header_enables 7322 * Bit mask where each bit enables a specific layer to be included in 7323 * the hash calculation. 7324 * Access: RW 7325 */ 7326 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7327 7328 enum { 7329 /* IPv4 Source IP */ 7330 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7331 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7332 /* IPv4 Destination IP */ 7333 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7334 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7335 /* IP Protocol */ 7336 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7337 /* IPv6 Source IP */ 7338 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7339 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7340 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7341 /* IPv6 Destination IP */ 7342 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7343 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7344 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7345 /* IPv6 Next Header */ 7346 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7347 /* IPv6 Flow Label */ 7348 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7349 /* TCP/UDP Source Port */ 7350 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7351 /* TCP/UDP Destination Port */ 7352 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7353 }; 7354 7355 /* reg_recr2_outer_header_fields_enable 7356 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7357 * Access: RW 7358 */ 7359 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7360 7361 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7362 { 7363 int i; 7364 7365 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7366 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7367 true); 7368 } 7369 7370 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7371 { 7372 int i; 7373 7374 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7375 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7376 true); 7377 } 7378 7379 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7380 { 7381 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7382 7383 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7384 7385 i = MLXSW_REG_RECR2_IPV6_SIP8; 7386 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7387 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7388 true); 7389 } 7390 7391 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7392 { 7393 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7394 7395 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7396 7397 i = MLXSW_REG_RECR2_IPV6_DIP8; 7398 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7399 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7400 true); 7401 } 7402 7403 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7404 { 7405 MLXSW_REG_ZERO(recr2, payload); 7406 mlxsw_reg_recr2_pp_set(payload, false); 7407 mlxsw_reg_recr2_sh_set(payload, true); 7408 mlxsw_reg_recr2_seed_set(payload, seed); 7409 } 7410 7411 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7412 * -------------------------------------------------------------- 7413 * The RMFT_V2 register is used to configure and query the multicast table. 7414 */ 7415 #define MLXSW_REG_RMFT2_ID 0x8027 7416 #define MLXSW_REG_RMFT2_LEN 0x174 7417 7418 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7419 7420 /* reg_rmft2_v 7421 * Valid 7422 * Access: RW 7423 */ 7424 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7425 7426 enum mlxsw_reg_rmft2_type { 7427 MLXSW_REG_RMFT2_TYPE_IPV4, 7428 MLXSW_REG_RMFT2_TYPE_IPV6 7429 }; 7430 7431 /* reg_rmft2_type 7432 * Access: Index 7433 */ 7434 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7435 7436 enum mlxsw_sp_reg_rmft2_op { 7437 /* For Write: 7438 * Write operation. Used to write a new entry to the table. All RW 7439 * fields are relevant for new entry. Activity bit is set for new 7440 * entries - Note write with v (Valid) 0 will delete the entry. 7441 * For Query: 7442 * Read operation 7443 */ 7444 MLXSW_REG_RMFT2_OP_READ_WRITE, 7445 }; 7446 7447 /* reg_rmft2_op 7448 * Operation. 7449 * Access: OP 7450 */ 7451 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7452 7453 /* reg_rmft2_a 7454 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7455 * entry. 7456 * Access: RO 7457 */ 7458 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7459 7460 /* reg_rmft2_offset 7461 * Offset within the multicast forwarding table to write to. 7462 * Access: Index 7463 */ 7464 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7465 7466 /* reg_rmft2_virtual_router 7467 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7468 * Access: RW 7469 */ 7470 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7471 7472 enum mlxsw_reg_rmft2_irif_mask { 7473 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7474 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7475 }; 7476 7477 /* reg_rmft2_irif_mask 7478 * Ingress RIF mask. 7479 * Access: RW 7480 */ 7481 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7482 7483 /* reg_rmft2_irif 7484 * Ingress RIF index. 7485 * Access: RW 7486 */ 7487 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7488 7489 /* reg_rmft2_dip{4,6} 7490 * Destination IPv4/6 address 7491 * Access: RW 7492 */ 7493 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7494 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7495 7496 /* reg_rmft2_dip{4,6}_mask 7497 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7498 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7499 * Access: RW 7500 */ 7501 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7502 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7503 7504 /* reg_rmft2_sip{4,6} 7505 * Source IPv4/6 address 7506 * Access: RW 7507 */ 7508 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7509 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7510 7511 /* reg_rmft2_sip{4,6}_mask 7512 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7513 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7514 * Access: RW 7515 */ 7516 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7517 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7518 7519 /* reg_rmft2_flexible_action_set 7520 * ACL action set. The only supported action types in this field and in any 7521 * action-set pointed from here are as follows: 7522 * 00h: ACTION_NULL 7523 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7524 * 03h: ACTION_TRAP 7525 * 06h: ACTION_QOS 7526 * 08h: ACTION_POLICING_MONITORING 7527 * 10h: ACTION_ROUTER_MC 7528 * Access: RW 7529 */ 7530 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7531 MLXSW_REG_FLEX_ACTION_SET_LEN); 7532 7533 static inline void 7534 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7535 u16 virtual_router, 7536 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7537 const char *flex_action_set) 7538 { 7539 MLXSW_REG_ZERO(rmft2, payload); 7540 mlxsw_reg_rmft2_v_set(payload, v); 7541 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7542 mlxsw_reg_rmft2_offset_set(payload, offset); 7543 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7544 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7545 mlxsw_reg_rmft2_irif_set(payload, irif); 7546 if (flex_action_set) 7547 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7548 flex_action_set); 7549 } 7550 7551 static inline void 7552 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7553 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7554 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7555 const char *flexible_action_set) 7556 { 7557 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7558 irif_mask, irif, flexible_action_set); 7559 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7560 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7561 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7562 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7563 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7564 } 7565 7566 static inline void 7567 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7568 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7569 struct in6_addr dip6, struct in6_addr dip6_mask, 7570 struct in6_addr sip6, struct in6_addr sip6_mask, 7571 const char *flexible_action_set) 7572 { 7573 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7574 irif_mask, irif, flexible_action_set); 7575 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 7576 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 7577 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 7578 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 7579 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 7580 } 7581 7582 /* MFCR - Management Fan Control Register 7583 * -------------------------------------- 7584 * This register controls the settings of the Fan Speed PWM mechanism. 7585 */ 7586 #define MLXSW_REG_MFCR_ID 0x9001 7587 #define MLXSW_REG_MFCR_LEN 0x08 7588 7589 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 7590 7591 enum mlxsw_reg_mfcr_pwm_frequency { 7592 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 7593 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 7594 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 7595 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 7596 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 7597 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 7598 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 7599 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 7600 }; 7601 7602 /* reg_mfcr_pwm_frequency 7603 * Controls the frequency of the PWM signal. 7604 * Access: RW 7605 */ 7606 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 7607 7608 #define MLXSW_MFCR_TACHOS_MAX 10 7609 7610 /* reg_mfcr_tacho_active 7611 * Indicates which of the tachometer is active (bit per tachometer). 7612 * Access: RO 7613 */ 7614 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 7615 7616 #define MLXSW_MFCR_PWMS_MAX 5 7617 7618 /* reg_mfcr_pwm_active 7619 * Indicates which of the PWM control is active (bit per PWM). 7620 * Access: RO 7621 */ 7622 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 7623 7624 static inline void 7625 mlxsw_reg_mfcr_pack(char *payload, 7626 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 7627 { 7628 MLXSW_REG_ZERO(mfcr, payload); 7629 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 7630 } 7631 7632 static inline void 7633 mlxsw_reg_mfcr_unpack(char *payload, 7634 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 7635 u16 *p_tacho_active, u8 *p_pwm_active) 7636 { 7637 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 7638 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 7639 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 7640 } 7641 7642 /* MFSC - Management Fan Speed Control Register 7643 * -------------------------------------------- 7644 * This register controls the settings of the Fan Speed PWM mechanism. 7645 */ 7646 #define MLXSW_REG_MFSC_ID 0x9002 7647 #define MLXSW_REG_MFSC_LEN 0x08 7648 7649 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 7650 7651 /* reg_mfsc_pwm 7652 * Fan pwm to control / monitor. 7653 * Access: Index 7654 */ 7655 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 7656 7657 /* reg_mfsc_pwm_duty_cycle 7658 * Controls the duty cycle of the PWM. Value range from 0..255 to 7659 * represent duty cycle of 0%...100%. 7660 * Access: RW 7661 */ 7662 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 7663 7664 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 7665 u8 pwm_duty_cycle) 7666 { 7667 MLXSW_REG_ZERO(mfsc, payload); 7668 mlxsw_reg_mfsc_pwm_set(payload, pwm); 7669 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 7670 } 7671 7672 /* MFSM - Management Fan Speed Measurement 7673 * --------------------------------------- 7674 * This register controls the settings of the Tacho measurements and 7675 * enables reading the Tachometer measurements. 7676 */ 7677 #define MLXSW_REG_MFSM_ID 0x9003 7678 #define MLXSW_REG_MFSM_LEN 0x08 7679 7680 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 7681 7682 /* reg_mfsm_tacho 7683 * Fan tachometer index. 7684 * Access: Index 7685 */ 7686 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 7687 7688 /* reg_mfsm_rpm 7689 * Fan speed (round per minute). 7690 * Access: RO 7691 */ 7692 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 7693 7694 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 7695 { 7696 MLXSW_REG_ZERO(mfsm, payload); 7697 mlxsw_reg_mfsm_tacho_set(payload, tacho); 7698 } 7699 7700 /* MFSL - Management Fan Speed Limit Register 7701 * ------------------------------------------ 7702 * The Fan Speed Limit register is used to configure the fan speed 7703 * event / interrupt notification mechanism. Fan speed threshold are 7704 * defined for both under-speed and over-speed. 7705 */ 7706 #define MLXSW_REG_MFSL_ID 0x9004 7707 #define MLXSW_REG_MFSL_LEN 0x0C 7708 7709 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 7710 7711 /* reg_mfsl_tacho 7712 * Fan tachometer index. 7713 * Access: Index 7714 */ 7715 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 7716 7717 /* reg_mfsl_tach_min 7718 * Tachometer minimum value (minimum RPM). 7719 * Access: RW 7720 */ 7721 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 7722 7723 /* reg_mfsl_tach_max 7724 * Tachometer maximum value (maximum RPM). 7725 * Access: RW 7726 */ 7727 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 7728 7729 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 7730 u16 tach_min, u16 tach_max) 7731 { 7732 MLXSW_REG_ZERO(mfsl, payload); 7733 mlxsw_reg_mfsl_tacho_set(payload, tacho); 7734 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 7735 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 7736 } 7737 7738 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 7739 u16 *p_tach_min, u16 *p_tach_max) 7740 { 7741 if (p_tach_min) 7742 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 7743 7744 if (p_tach_max) 7745 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 7746 } 7747 7748 /* MTCAP - Management Temperature Capabilities 7749 * ------------------------------------------- 7750 * This register exposes the capabilities of the device and 7751 * system temperature sensing. 7752 */ 7753 #define MLXSW_REG_MTCAP_ID 0x9009 7754 #define MLXSW_REG_MTCAP_LEN 0x08 7755 7756 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 7757 7758 /* reg_mtcap_sensor_count 7759 * Number of sensors supported by the device. 7760 * This includes the QSFP module sensors (if exists in the QSFP module). 7761 * Access: RO 7762 */ 7763 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 7764 7765 /* MTMP - Management Temperature 7766 * ----------------------------- 7767 * This register controls the settings of the temperature measurements 7768 * and enables reading the temperature measurements. Note that temperature 7769 * is in 0.125 degrees Celsius. 7770 */ 7771 #define MLXSW_REG_MTMP_ID 0x900A 7772 #define MLXSW_REG_MTMP_LEN 0x20 7773 7774 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 7775 7776 /* reg_mtmp_sensor_index 7777 * Sensors index to access. 7778 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 7779 * (module 0 is mapped to sensor_index 64). 7780 * Access: Index 7781 */ 7782 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 7783 7784 /* Convert to milli degrees Celsius */ 7785 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 7786 7787 /* reg_mtmp_temperature 7788 * Temperature reading from the sensor. Reading is in 0.125 Celsius 7789 * degrees units. 7790 * Access: RO 7791 */ 7792 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 7793 7794 /* reg_mtmp_mte 7795 * Max Temperature Enable - enables measuring the max temperature on a sensor. 7796 * Access: RW 7797 */ 7798 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 7799 7800 /* reg_mtmp_mtr 7801 * Max Temperature Reset - clears the value of the max temperature register. 7802 * Access: WO 7803 */ 7804 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 7805 7806 /* reg_mtmp_max_temperature 7807 * The highest measured temperature from the sensor. 7808 * When the bit mte is cleared, the field max_temperature is reserved. 7809 * Access: RO 7810 */ 7811 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 7812 7813 /* reg_mtmp_tee 7814 * Temperature Event Enable. 7815 * 0 - Do not generate event 7816 * 1 - Generate event 7817 * 2 - Generate single event 7818 * Access: RW 7819 */ 7820 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 7821 7822 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 7823 7824 /* reg_mtmp_temperature_threshold_hi 7825 * High threshold for Temperature Warning Event. In 0.125 Celsius. 7826 * Access: RW 7827 */ 7828 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 7829 7830 /* reg_mtmp_temperature_threshold_lo 7831 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 7832 * Access: RW 7833 */ 7834 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 7835 7836 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 7837 7838 /* reg_mtmp_sensor_name 7839 * Sensor Name 7840 * Access: RO 7841 */ 7842 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 7843 7844 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 7845 bool max_temp_enable, 7846 bool max_temp_reset) 7847 { 7848 MLXSW_REG_ZERO(mtmp, payload); 7849 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 7850 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 7851 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 7852 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 7853 MLXSW_REG_MTMP_THRESH_HI); 7854 } 7855 7856 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 7857 unsigned int *p_max_temp, 7858 char *sensor_name) 7859 { 7860 u16 temp; 7861 7862 if (p_temp) { 7863 temp = mlxsw_reg_mtmp_temperature_get(payload); 7864 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7865 } 7866 if (p_max_temp) { 7867 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 7868 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7869 } 7870 if (sensor_name) 7871 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 7872 } 7873 7874 /* MCIA - Management Cable Info Access 7875 * ----------------------------------- 7876 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 7877 */ 7878 7879 #define MLXSW_REG_MCIA_ID 0x9014 7880 #define MLXSW_REG_MCIA_LEN 0x40 7881 7882 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 7883 7884 /* reg_mcia_l 7885 * Lock bit. Setting this bit will lock the access to the specific 7886 * cable. Used for updating a full page in a cable EPROM. Any access 7887 * other then subsequence writes will fail while the port is locked. 7888 * Access: RW 7889 */ 7890 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 7891 7892 /* reg_mcia_module 7893 * Module number. 7894 * Access: Index 7895 */ 7896 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 7897 7898 /* reg_mcia_status 7899 * Module status. 7900 * Access: RO 7901 */ 7902 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 7903 7904 /* reg_mcia_i2c_device_address 7905 * I2C device address. 7906 * Access: RW 7907 */ 7908 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 7909 7910 /* reg_mcia_page_number 7911 * Page number. 7912 * Access: RW 7913 */ 7914 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 7915 7916 /* reg_mcia_device_address 7917 * Device address. 7918 * Access: RW 7919 */ 7920 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 7921 7922 /* reg_mcia_size 7923 * Number of bytes to read/write (up to 48 bytes). 7924 * Access: RW 7925 */ 7926 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 7927 7928 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 7929 7930 /* reg_mcia_eeprom 7931 * Bytes to read/write. 7932 * Access: RW 7933 */ 7934 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 7935 7936 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 7937 u8 page_number, u16 device_addr, 7938 u8 size, u8 i2c_device_addr) 7939 { 7940 MLXSW_REG_ZERO(mcia, payload); 7941 mlxsw_reg_mcia_module_set(payload, module); 7942 mlxsw_reg_mcia_l_set(payload, lock); 7943 mlxsw_reg_mcia_page_number_set(payload, page_number); 7944 mlxsw_reg_mcia_device_address_set(payload, device_addr); 7945 mlxsw_reg_mcia_size_set(payload, size); 7946 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 7947 } 7948 7949 /* MPAT - Monitoring Port Analyzer Table 7950 * ------------------------------------- 7951 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 7952 * For an enabled analyzer, all fields except e (enable) cannot be modified. 7953 */ 7954 #define MLXSW_REG_MPAT_ID 0x901A 7955 #define MLXSW_REG_MPAT_LEN 0x78 7956 7957 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 7958 7959 /* reg_mpat_pa_id 7960 * Port Analyzer ID. 7961 * Access: Index 7962 */ 7963 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 7964 7965 /* reg_mpat_system_port 7966 * A unique port identifier for the final destination of the packet. 7967 * Access: RW 7968 */ 7969 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 7970 7971 /* reg_mpat_e 7972 * Enable. Indicating the Port Analyzer is enabled. 7973 * Access: RW 7974 */ 7975 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 7976 7977 /* reg_mpat_qos 7978 * Quality Of Service Mode. 7979 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 7980 * PCP, DEI, DSCP or VL) are configured. 7981 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 7982 * same as in the original packet that has triggered the mirroring. For 7983 * SPAN also the pcp,dei are maintained. 7984 * Access: RW 7985 */ 7986 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 7987 7988 /* reg_mpat_be 7989 * Best effort mode. Indicates mirroring traffic should not cause packet 7990 * drop or back pressure, but will discard the mirrored packets. Mirrored 7991 * packets will be forwarded on a best effort manner. 7992 * 0: Do not discard mirrored packets 7993 * 1: Discard mirrored packets if causing congestion 7994 * Access: RW 7995 */ 7996 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 7997 7998 enum mlxsw_reg_mpat_span_type { 7999 /* Local SPAN Ethernet. 8000 * The original packet is not encapsulated. 8001 */ 8002 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8003 8004 /* Remote SPAN Ethernet VLAN. 8005 * The packet is forwarded to the monitoring port on the monitoring 8006 * VLAN. 8007 */ 8008 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8009 8010 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8011 * The packet is encapsulated with GRE header. 8012 */ 8013 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8014 }; 8015 8016 /* reg_mpat_span_type 8017 * SPAN type. 8018 * Access: RW 8019 */ 8020 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8021 8022 /* Remote SPAN - Ethernet VLAN 8023 * - - - - - - - - - - - - - - 8024 */ 8025 8026 /* reg_mpat_eth_rspan_vid 8027 * Encapsulation header VLAN ID. 8028 * Access: RW 8029 */ 8030 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8031 8032 /* Encapsulated Remote SPAN - Ethernet L2 8033 * - - - - - - - - - - - - - - - - - - - 8034 */ 8035 8036 enum mlxsw_reg_mpat_eth_rspan_version { 8037 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8038 }; 8039 8040 /* reg_mpat_eth_rspan_version 8041 * RSPAN mirror header version. 8042 * Access: RW 8043 */ 8044 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8045 8046 /* reg_mpat_eth_rspan_mac 8047 * Destination MAC address. 8048 * Access: RW 8049 */ 8050 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8051 8052 /* reg_mpat_eth_rspan_tp 8053 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8054 * Access: RW 8055 */ 8056 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8057 8058 /* Encapsulated Remote SPAN - Ethernet L3 8059 * - - - - - - - - - - - - - - - - - - - 8060 */ 8061 8062 enum mlxsw_reg_mpat_eth_rspan_protocol { 8063 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8064 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8065 }; 8066 8067 /* reg_mpat_eth_rspan_protocol 8068 * SPAN encapsulation protocol. 8069 * Access: RW 8070 */ 8071 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8072 8073 /* reg_mpat_eth_rspan_ttl 8074 * Encapsulation header Time-to-Live/HopLimit. 8075 * Access: RW 8076 */ 8077 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8078 8079 /* reg_mpat_eth_rspan_smac 8080 * Source MAC address 8081 * Access: RW 8082 */ 8083 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8084 8085 /* reg_mpat_eth_rspan_dip* 8086 * Destination IP address. The IP version is configured by protocol. 8087 * Access: RW 8088 */ 8089 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8090 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8091 8092 /* reg_mpat_eth_rspan_sip* 8093 * Source IP address. The IP version is configured by protocol. 8094 * Access: RW 8095 */ 8096 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8097 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8098 8099 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8100 u16 system_port, bool e, 8101 enum mlxsw_reg_mpat_span_type span_type) 8102 { 8103 MLXSW_REG_ZERO(mpat, payload); 8104 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8105 mlxsw_reg_mpat_system_port_set(payload, system_port); 8106 mlxsw_reg_mpat_e_set(payload, e); 8107 mlxsw_reg_mpat_qos_set(payload, 1); 8108 mlxsw_reg_mpat_be_set(payload, 1); 8109 mlxsw_reg_mpat_span_type_set(payload, span_type); 8110 } 8111 8112 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8113 { 8114 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8115 } 8116 8117 static inline void 8118 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8119 enum mlxsw_reg_mpat_eth_rspan_version version, 8120 const char *mac, 8121 bool tp) 8122 { 8123 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8124 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8125 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8126 } 8127 8128 static inline void 8129 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8130 const char *smac, 8131 u32 sip, u32 dip) 8132 { 8133 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8134 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8135 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8136 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8137 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8138 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8139 } 8140 8141 static inline void 8142 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8143 const char *smac, 8144 struct in6_addr sip, struct in6_addr dip) 8145 { 8146 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8147 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8148 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8149 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8150 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8151 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8152 } 8153 8154 /* MPAR - Monitoring Port Analyzer Register 8155 * ---------------------------------------- 8156 * MPAR register is used to query and configure the port analyzer port mirroring 8157 * properties. 8158 */ 8159 #define MLXSW_REG_MPAR_ID 0x901B 8160 #define MLXSW_REG_MPAR_LEN 0x08 8161 8162 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8163 8164 /* reg_mpar_local_port 8165 * The local port to mirror the packets from. 8166 * Access: Index 8167 */ 8168 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8169 8170 enum mlxsw_reg_mpar_i_e { 8171 MLXSW_REG_MPAR_TYPE_EGRESS, 8172 MLXSW_REG_MPAR_TYPE_INGRESS, 8173 }; 8174 8175 /* reg_mpar_i_e 8176 * Ingress/Egress 8177 * Access: Index 8178 */ 8179 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8180 8181 /* reg_mpar_enable 8182 * Enable mirroring 8183 * By default, port mirroring is disabled for all ports. 8184 * Access: RW 8185 */ 8186 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8187 8188 /* reg_mpar_pa_id 8189 * Port Analyzer ID. 8190 * Access: RW 8191 */ 8192 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8193 8194 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8195 enum mlxsw_reg_mpar_i_e i_e, 8196 bool enable, u8 pa_id) 8197 { 8198 MLXSW_REG_ZERO(mpar, payload); 8199 mlxsw_reg_mpar_local_port_set(payload, local_port); 8200 mlxsw_reg_mpar_enable_set(payload, enable); 8201 mlxsw_reg_mpar_i_e_set(payload, i_e); 8202 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8203 } 8204 8205 /* MRSR - Management Reset and Shutdown Register 8206 * --------------------------------------------- 8207 * MRSR register is used to reset or shutdown the switch or 8208 * the entire system (when applicable). 8209 */ 8210 #define MLXSW_REG_MRSR_ID 0x9023 8211 #define MLXSW_REG_MRSR_LEN 0x08 8212 8213 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8214 8215 /* reg_mrsr_command 8216 * Reset/shutdown command 8217 * 0 - do nothing 8218 * 1 - software reset 8219 * Access: WO 8220 */ 8221 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8222 8223 static inline void mlxsw_reg_mrsr_pack(char *payload) 8224 { 8225 MLXSW_REG_ZERO(mrsr, payload); 8226 mlxsw_reg_mrsr_command_set(payload, 1); 8227 } 8228 8229 /* MLCR - Management LED Control Register 8230 * -------------------------------------- 8231 * Controls the system LEDs. 8232 */ 8233 #define MLXSW_REG_MLCR_ID 0x902B 8234 #define MLXSW_REG_MLCR_LEN 0x0C 8235 8236 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8237 8238 /* reg_mlcr_local_port 8239 * Local port number. 8240 * Access: RW 8241 */ 8242 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8243 8244 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8245 8246 /* reg_mlcr_beacon_duration 8247 * Duration of the beacon to be active, in seconds. 8248 * 0x0 - Will turn off the beacon. 8249 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8250 * Access: RW 8251 */ 8252 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8253 8254 /* reg_mlcr_beacon_remain 8255 * Remaining duration of the beacon, in seconds. 8256 * 0xFFFF indicates an infinite amount of time. 8257 * Access: RO 8258 */ 8259 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8260 8261 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8262 bool active) 8263 { 8264 MLXSW_REG_ZERO(mlcr, payload); 8265 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8266 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8267 MLXSW_REG_MLCR_DURATION_MAX : 0); 8268 } 8269 8270 /* MCQI - Management Component Query Information 8271 * --------------------------------------------- 8272 * This register allows querying information about firmware components. 8273 */ 8274 #define MLXSW_REG_MCQI_ID 0x9061 8275 #define MLXSW_REG_MCQI_BASE_LEN 0x18 8276 #define MLXSW_REG_MCQI_CAP_LEN 0x14 8277 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 8278 8279 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 8280 8281 /* reg_mcqi_component_index 8282 * Index of the accessed component. 8283 * Access: Index 8284 */ 8285 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 8286 8287 enum mlxfw_reg_mcqi_info_type { 8288 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 8289 }; 8290 8291 /* reg_mcqi_info_type 8292 * Component properties set. 8293 * Access: RW 8294 */ 8295 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 8296 8297 /* reg_mcqi_offset 8298 * The requested/returned data offset from the section start, given in bytes. 8299 * Must be DWORD aligned. 8300 * Access: RW 8301 */ 8302 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 8303 8304 /* reg_mcqi_data_size 8305 * The requested/returned data size, given in bytes. If data_size is not DWORD 8306 * aligned, the last bytes are zero padded. 8307 * Access: RW 8308 */ 8309 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 8310 8311 /* reg_mcqi_cap_max_component_size 8312 * Maximum size for this component, given in bytes. 8313 * Access: RO 8314 */ 8315 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 8316 8317 /* reg_mcqi_cap_log_mcda_word_size 8318 * Log 2 of the access word size in bytes. Read and write access must be aligned 8319 * to the word size. Write access must be done for an integer number of words. 8320 * Access: RO 8321 */ 8322 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 8323 8324 /* reg_mcqi_cap_mcda_max_write_size 8325 * Maximal write size for MCDA register 8326 * Access: RO 8327 */ 8328 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 8329 8330 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 8331 { 8332 MLXSW_REG_ZERO(mcqi, payload); 8333 mlxsw_reg_mcqi_component_index_set(payload, component_index); 8334 mlxsw_reg_mcqi_info_type_set(payload, 8335 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 8336 mlxsw_reg_mcqi_offset_set(payload, 0); 8337 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 8338 } 8339 8340 static inline void mlxsw_reg_mcqi_unpack(char *payload, 8341 u32 *p_cap_max_component_size, 8342 u8 *p_cap_log_mcda_word_size, 8343 u16 *p_cap_mcda_max_write_size) 8344 { 8345 *p_cap_max_component_size = 8346 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 8347 *p_cap_log_mcda_word_size = 8348 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 8349 *p_cap_mcda_max_write_size = 8350 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 8351 } 8352 8353 /* MCC - Management Component Control 8354 * ---------------------------------- 8355 * Controls the firmware component and updates the FSM. 8356 */ 8357 #define MLXSW_REG_MCC_ID 0x9062 8358 #define MLXSW_REG_MCC_LEN 0x1C 8359 8360 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 8361 8362 enum mlxsw_reg_mcc_instruction { 8363 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 8364 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 8365 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 8366 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 8367 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 8368 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 8369 }; 8370 8371 /* reg_mcc_instruction 8372 * Command to be executed by the FSM. 8373 * Applicable for write operation only. 8374 * Access: RW 8375 */ 8376 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 8377 8378 /* reg_mcc_component_index 8379 * Index of the accessed component. Applicable only for commands that 8380 * refer to components. Otherwise, this field is reserved. 8381 * Access: Index 8382 */ 8383 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 8384 8385 /* reg_mcc_update_handle 8386 * Token representing the current flow executed by the FSM. 8387 * Access: WO 8388 */ 8389 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 8390 8391 /* reg_mcc_error_code 8392 * Indicates the successful completion of the instruction, or the reason it 8393 * failed 8394 * Access: RO 8395 */ 8396 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 8397 8398 /* reg_mcc_control_state 8399 * Current FSM state 8400 * Access: RO 8401 */ 8402 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 8403 8404 /* reg_mcc_component_size 8405 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 8406 * the size may shorten the update time. Value 0x0 means that size is 8407 * unspecified. 8408 * Access: WO 8409 */ 8410 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 8411 8412 static inline void mlxsw_reg_mcc_pack(char *payload, 8413 enum mlxsw_reg_mcc_instruction instr, 8414 u16 component_index, u32 update_handle, 8415 u32 component_size) 8416 { 8417 MLXSW_REG_ZERO(mcc, payload); 8418 mlxsw_reg_mcc_instruction_set(payload, instr); 8419 mlxsw_reg_mcc_component_index_set(payload, component_index); 8420 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 8421 mlxsw_reg_mcc_component_size_set(payload, component_size); 8422 } 8423 8424 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 8425 u8 *p_error_code, u8 *p_control_state) 8426 { 8427 if (p_update_handle) 8428 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 8429 if (p_error_code) 8430 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 8431 if (p_control_state) 8432 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 8433 } 8434 8435 /* MCDA - Management Component Data Access 8436 * --------------------------------------- 8437 * This register allows reading and writing a firmware component. 8438 */ 8439 #define MLXSW_REG_MCDA_ID 0x9063 8440 #define MLXSW_REG_MCDA_BASE_LEN 0x10 8441 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 8442 #define MLXSW_REG_MCDA_LEN \ 8443 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 8444 8445 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 8446 8447 /* reg_mcda_update_handle 8448 * Token representing the current flow executed by the FSM. 8449 * Access: RW 8450 */ 8451 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 8452 8453 /* reg_mcda_offset 8454 * Offset of accessed address relative to component start. Accesses must be in 8455 * accordance to log_mcda_word_size in MCQI reg. 8456 * Access: RW 8457 */ 8458 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 8459 8460 /* reg_mcda_size 8461 * Size of the data accessed, given in bytes. 8462 * Access: RW 8463 */ 8464 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 8465 8466 /* reg_mcda_data 8467 * Data block accessed. 8468 * Access: RW 8469 */ 8470 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 8471 8472 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 8473 u32 offset, u16 size, u8 *data) 8474 { 8475 int i; 8476 8477 MLXSW_REG_ZERO(mcda, payload); 8478 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 8479 mlxsw_reg_mcda_offset_set(payload, offset); 8480 mlxsw_reg_mcda_size_set(payload, size); 8481 8482 for (i = 0; i < size / 4; i++) 8483 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 8484 } 8485 8486 /* MPSC - Monitoring Packet Sampling Configuration Register 8487 * -------------------------------------------------------- 8488 * MPSC Register is used to configure the Packet Sampling mechanism. 8489 */ 8490 #define MLXSW_REG_MPSC_ID 0x9080 8491 #define MLXSW_REG_MPSC_LEN 0x1C 8492 8493 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 8494 8495 /* reg_mpsc_local_port 8496 * Local port number 8497 * Not supported for CPU port 8498 * Access: Index 8499 */ 8500 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 8501 8502 /* reg_mpsc_e 8503 * Enable sampling on port local_port 8504 * Access: RW 8505 */ 8506 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 8507 8508 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 8509 8510 /* reg_mpsc_rate 8511 * Sampling rate = 1 out of rate packets (with randomization around 8512 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 8513 * Access: RW 8514 */ 8515 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 8516 8517 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 8518 u32 rate) 8519 { 8520 MLXSW_REG_ZERO(mpsc, payload); 8521 mlxsw_reg_mpsc_local_port_set(payload, local_port); 8522 mlxsw_reg_mpsc_e_set(payload, e); 8523 mlxsw_reg_mpsc_rate_set(payload, rate); 8524 } 8525 8526 /* MGPC - Monitoring General Purpose Counter Set Register 8527 * The MGPC register retrieves and sets the General Purpose Counter Set. 8528 */ 8529 #define MLXSW_REG_MGPC_ID 0x9081 8530 #define MLXSW_REG_MGPC_LEN 0x18 8531 8532 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 8533 8534 /* reg_mgpc_counter_set_type 8535 * Counter set type. 8536 * Access: OP 8537 */ 8538 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 8539 8540 /* reg_mgpc_counter_index 8541 * Counter index. 8542 * Access: Index 8543 */ 8544 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 8545 8546 enum mlxsw_reg_mgpc_opcode { 8547 /* Nop */ 8548 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 8549 /* Clear counters */ 8550 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 8551 }; 8552 8553 /* reg_mgpc_opcode 8554 * Opcode. 8555 * Access: OP 8556 */ 8557 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 8558 8559 /* reg_mgpc_byte_counter 8560 * Byte counter value. 8561 * Access: RW 8562 */ 8563 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 8564 8565 /* reg_mgpc_packet_counter 8566 * Packet counter value. 8567 * Access: RW 8568 */ 8569 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 8570 8571 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 8572 enum mlxsw_reg_mgpc_opcode opcode, 8573 enum mlxsw_reg_flow_counter_set_type set_type) 8574 { 8575 MLXSW_REG_ZERO(mgpc, payload); 8576 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 8577 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 8578 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8579 } 8580 8581 /* MPRS - Monitoring Parsing State Register 8582 * ---------------------------------------- 8583 * The MPRS register is used for setting up the parsing for hash, 8584 * policy-engine and routing. 8585 */ 8586 #define MLXSW_REG_MPRS_ID 0x9083 8587 #define MLXSW_REG_MPRS_LEN 0x14 8588 8589 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 8590 8591 /* reg_mprs_parsing_depth 8592 * Minimum parsing depth. 8593 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 8594 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 8595 * Access: RW 8596 */ 8597 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 8598 8599 /* reg_mprs_parsing_en 8600 * Parsing enable. 8601 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 8602 * NVGRE. Default is enabled. Reserved when SwitchX-2. 8603 * Access: RW 8604 */ 8605 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 8606 8607 /* reg_mprs_vxlan_udp_dport 8608 * VxLAN UDP destination port. 8609 * Used for identifying VxLAN packets and for dport field in 8610 * encapsulation. Default is 4789. 8611 * Access: RW 8612 */ 8613 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 8614 8615 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 8616 u16 vxlan_udp_dport) 8617 { 8618 MLXSW_REG_ZERO(mprs, payload); 8619 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 8620 mlxsw_reg_mprs_parsing_en_set(payload, true); 8621 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 8622 } 8623 8624 /* TNGCR - Tunneling NVE General Configuration Register 8625 * ---------------------------------------------------- 8626 * The TNGCR register is used for setting up the NVE Tunneling configuration. 8627 */ 8628 #define MLXSW_REG_TNGCR_ID 0xA001 8629 #define MLXSW_REG_TNGCR_LEN 0x44 8630 8631 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 8632 8633 enum mlxsw_reg_tngcr_type { 8634 MLXSW_REG_TNGCR_TYPE_VXLAN, 8635 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 8636 MLXSW_REG_TNGCR_TYPE_GENEVE, 8637 MLXSW_REG_TNGCR_TYPE_NVGRE, 8638 }; 8639 8640 /* reg_tngcr_type 8641 * Tunnel type for encapsulation and decapsulation. The types are mutually 8642 * exclusive. 8643 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 8644 * Access: RW 8645 */ 8646 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 8647 8648 /* reg_tngcr_nve_valid 8649 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 8650 * Access: RW 8651 */ 8652 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 8653 8654 /* reg_tngcr_nve_ttl_uc 8655 * The TTL for NVE tunnel encapsulation underlay unicast packets. 8656 * Access: RW 8657 */ 8658 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 8659 8660 /* reg_tngcr_nve_ttl_mc 8661 * The TTL for NVE tunnel encapsulation underlay multicast packets. 8662 * Access: RW 8663 */ 8664 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 8665 8666 enum { 8667 /* Do not copy flow label. Calculate flow label using nve_flh. */ 8668 MLXSW_REG_TNGCR_FL_NO_COPY, 8669 /* Copy flow label from inner packet if packet is IPv6 and 8670 * encapsulation is by IPv6. Otherwise, calculate flow label using 8671 * nve_flh. 8672 */ 8673 MLXSW_REG_TNGCR_FL_COPY, 8674 }; 8675 8676 /* reg_tngcr_nve_flc 8677 * For NVE tunnel encapsulation: Flow label copy from inner packet. 8678 * Access: RW 8679 */ 8680 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 8681 8682 enum { 8683 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 8684 * uses {nve_fl_prefix, nve_fl_suffix}. 8685 */ 8686 MLXSW_REG_TNGCR_FL_NO_HASH, 8687 /* 8 LSBs of the flow label are calculated from ECMP hash of the 8688 * inner packet. 12 MSBs are configured by nve_fl_prefix. 8689 */ 8690 MLXSW_REG_TNGCR_FL_HASH, 8691 }; 8692 8693 /* reg_tngcr_nve_flh 8694 * NVE flow label hash. 8695 * Access: RW 8696 */ 8697 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 8698 8699 /* reg_tngcr_nve_fl_prefix 8700 * NVE flow label prefix. Constant 12 MSBs of the flow label. 8701 * Access: RW 8702 */ 8703 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 8704 8705 /* reg_tngcr_nve_fl_suffix 8706 * NVE flow label suffix. Constant 8 LSBs of the flow label. 8707 * Reserved when nve_flh=1 and for Spectrum. 8708 * Access: RW 8709 */ 8710 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 8711 8712 enum { 8713 /* Source UDP port is fixed (default '0') */ 8714 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 8715 /* Source UDP port is calculated based on hash */ 8716 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 8717 }; 8718 8719 /* reg_tngcr_nve_udp_sport_type 8720 * NVE UDP source port type. 8721 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 8722 * When the source UDP port is calculated based on hash, then the 8 LSBs 8723 * are calculated from hash the 8 MSBs are configured by 8724 * nve_udp_sport_prefix. 8725 * Access: RW 8726 */ 8727 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 8728 8729 /* reg_tngcr_nve_udp_sport_prefix 8730 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 8731 * Reserved when NVE type is NVGRE. 8732 * Access: RW 8733 */ 8734 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 8735 8736 /* reg_tngcr_nve_group_size_mc 8737 * The amount of sequential linked lists of MC entries. The first linked 8738 * list is configured by SFD.underlay_mc_ptr. 8739 * Valid values: 1, 2, 4, 8, 16, 32, 64 8740 * The linked list are configured by TNUMT. 8741 * The hash is set by LAG hash. 8742 * Access: RW 8743 */ 8744 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 8745 8746 /* reg_tngcr_nve_group_size_flood 8747 * The amount of sequential linked lists of flooding entries. The first 8748 * linked list is configured by SFMR.nve_tunnel_flood_ptr 8749 * Valid values: 1, 2, 4, 8, 16, 32, 64 8750 * The linked list are configured by TNUMT. 8751 * The hash is set by LAG hash. 8752 * Access: RW 8753 */ 8754 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 8755 8756 /* reg_tngcr_learn_enable 8757 * During decapsulation, whether to learn from NVE port. 8758 * Reserved when Spectrum-2. See TNPC. 8759 * Access: RW 8760 */ 8761 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 8762 8763 /* reg_tngcr_underlay_virtual_router 8764 * Underlay virtual router. 8765 * Reserved when Spectrum-2. 8766 * Access: RW 8767 */ 8768 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 8769 8770 /* reg_tngcr_underlay_rif 8771 * Underlay ingress router interface. RIF type should be loopback generic. 8772 * Reserved when Spectrum. 8773 * Access: RW 8774 */ 8775 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 8776 8777 /* reg_tngcr_usipv4 8778 * Underlay source IPv4 address of the NVE. 8779 * Access: RW 8780 */ 8781 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 8782 8783 /* reg_tngcr_usipv6 8784 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 8785 * modified under traffic of NVE tunneling encapsulation. 8786 * Access: RW 8787 */ 8788 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 8789 8790 static inline void mlxsw_reg_tngcr_pack(char *payload, 8791 enum mlxsw_reg_tngcr_type type, 8792 bool valid, u8 ttl) 8793 { 8794 MLXSW_REG_ZERO(tngcr, payload); 8795 mlxsw_reg_tngcr_type_set(payload, type); 8796 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 8797 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 8798 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 8799 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 8800 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 8801 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 8802 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 8803 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 8804 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 8805 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 8806 } 8807 8808 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 8809 * ------------------------------------------------------- 8810 * The TNUMT register is for building the underlay MC table. It is used 8811 * for MC, flooding and BC traffic into the NVE tunnel. 8812 */ 8813 #define MLXSW_REG_TNUMT_ID 0xA003 8814 #define MLXSW_REG_TNUMT_LEN 0x20 8815 8816 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 8817 8818 enum mlxsw_reg_tnumt_record_type { 8819 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 8820 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 8821 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 8822 }; 8823 8824 /* reg_tnumt_record_type 8825 * Record type. 8826 * Access: RW 8827 */ 8828 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 8829 8830 enum mlxsw_reg_tnumt_tunnel_port { 8831 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 8832 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 8833 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 8834 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 8835 }; 8836 8837 /* reg_tnumt_tunnel_port 8838 * Tunnel port. 8839 * Access: RW 8840 */ 8841 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 8842 8843 /* reg_tnumt_underlay_mc_ptr 8844 * Index to the underlay multicast table. 8845 * For Spectrum the index is to the KVD linear. 8846 * Access: Index 8847 */ 8848 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 8849 8850 /* reg_tnumt_vnext 8851 * The next_underlay_mc_ptr is valid. 8852 * Access: RW 8853 */ 8854 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 8855 8856 /* reg_tnumt_next_underlay_mc_ptr 8857 * The next index to the underlay multicast table. 8858 * Access: RW 8859 */ 8860 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 8861 8862 /* reg_tnumt_record_size 8863 * Number of IP addresses in the record. 8864 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 8865 * Access: RW 8866 */ 8867 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 8868 8869 /* reg_tnumt_udip 8870 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 8871 * Access: RW 8872 */ 8873 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 8874 8875 /* reg_tnumt_udip_ptr 8876 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 8877 * i >= size. The IPv6 addresses are configured by RIPS. 8878 * Access: RW 8879 */ 8880 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 8881 8882 static inline void mlxsw_reg_tnumt_pack(char *payload, 8883 enum mlxsw_reg_tnumt_record_type type, 8884 enum mlxsw_reg_tnumt_tunnel_port tport, 8885 u32 underlay_mc_ptr, bool vnext, 8886 u32 next_underlay_mc_ptr, 8887 u8 record_size) 8888 { 8889 MLXSW_REG_ZERO(tnumt, payload); 8890 mlxsw_reg_tnumt_record_type_set(payload, type); 8891 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 8892 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 8893 mlxsw_reg_tnumt_vnext_set(payload, vnext); 8894 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 8895 mlxsw_reg_tnumt_record_size_set(payload, record_size); 8896 } 8897 8898 /* TNQCR - Tunneling NVE QoS Configuration Register 8899 * ------------------------------------------------ 8900 * The TNQCR register configures how QoS is set in encapsulation into the 8901 * underlay network. 8902 */ 8903 #define MLXSW_REG_TNQCR_ID 0xA010 8904 #define MLXSW_REG_TNQCR_LEN 0x0C 8905 8906 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 8907 8908 /* reg_tnqcr_enc_set_dscp 8909 * For encapsulation: How to set DSCP field: 8910 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 8911 * (outer) IP header. If there is no IP header, use TNQDR.dscp 8912 * 1 - Set the DSCP field as TNQDR.dscp 8913 * Access: RW 8914 */ 8915 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 8916 8917 static inline void mlxsw_reg_tnqcr_pack(char *payload) 8918 { 8919 MLXSW_REG_ZERO(tnqcr, payload); 8920 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 8921 } 8922 8923 /* TNQDR - Tunneling NVE QoS Default Register 8924 * ------------------------------------------ 8925 * The TNQDR register configures the default QoS settings for NVE 8926 * encapsulation. 8927 */ 8928 #define MLXSW_REG_TNQDR_ID 0xA011 8929 #define MLXSW_REG_TNQDR_LEN 0x08 8930 8931 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 8932 8933 /* reg_tnqdr_local_port 8934 * Local port number (receive port). CPU port is supported. 8935 * Access: Index 8936 */ 8937 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 8938 8939 /* reg_tnqdr_dscp 8940 * For encapsulation, the default DSCP. 8941 * Access: RW 8942 */ 8943 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 8944 8945 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 8946 { 8947 MLXSW_REG_ZERO(tnqdr, payload); 8948 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 8949 mlxsw_reg_tnqdr_dscp_set(payload, 0); 8950 } 8951 8952 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 8953 * -------------------------------------------------------- 8954 * The TNEEM register maps ECN of the IP header at the ingress to the 8955 * encapsulation to the ECN of the underlay network. 8956 */ 8957 #define MLXSW_REG_TNEEM_ID 0xA012 8958 #define MLXSW_REG_TNEEM_LEN 0x0C 8959 8960 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 8961 8962 /* reg_tneem_overlay_ecn 8963 * ECN of the IP header in the overlay network. 8964 * Access: Index 8965 */ 8966 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 8967 8968 /* reg_tneem_underlay_ecn 8969 * ECN of the IP header in the underlay network. 8970 * Access: RW 8971 */ 8972 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 8973 8974 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 8975 u8 underlay_ecn) 8976 { 8977 MLXSW_REG_ZERO(tneem, payload); 8978 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 8979 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 8980 } 8981 8982 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 8983 * -------------------------------------------------------- 8984 * The TNDEM register configures the actions that are done in the 8985 * decapsulation. 8986 */ 8987 #define MLXSW_REG_TNDEM_ID 0xA013 8988 #define MLXSW_REG_TNDEM_LEN 0x0C 8989 8990 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 8991 8992 /* reg_tndem_underlay_ecn 8993 * ECN field of the IP header in the underlay network. 8994 * Access: Index 8995 */ 8996 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 8997 8998 /* reg_tndem_overlay_ecn 8999 * ECN field of the IP header in the overlay network. 9000 * Access: Index 9001 */ 9002 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 9003 9004 /* reg_tndem_eip_ecn 9005 * Egress IP ECN. ECN field of the IP header of the packet which goes out 9006 * from the decapsulation. 9007 * Access: RW 9008 */ 9009 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 9010 9011 /* reg_tndem_trap_en 9012 * Trap enable: 9013 * 0 - No trap due to decap ECN 9014 * 1 - Trap enable with trap_id 9015 * Access: RW 9016 */ 9017 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 9018 9019 /* reg_tndem_trap_id 9020 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 9021 * Reserved when trap_en is '0'. 9022 * Access: RW 9023 */ 9024 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 9025 9026 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 9027 u8 overlay_ecn, u8 ecn, bool trap_en, 9028 u16 trap_id) 9029 { 9030 MLXSW_REG_ZERO(tndem, payload); 9031 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 9032 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 9033 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 9034 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 9035 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 9036 } 9037 9038 /* TNPC - Tunnel Port Configuration Register 9039 * ----------------------------------------- 9040 * The TNPC register is used for tunnel port configuration. 9041 * Reserved when Spectrum. 9042 */ 9043 #define MLXSW_REG_TNPC_ID 0xA020 9044 #define MLXSW_REG_TNPC_LEN 0x18 9045 9046 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 9047 9048 enum mlxsw_reg_tnpc_tunnel_port { 9049 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 9050 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 9051 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 9052 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 9053 }; 9054 9055 /* reg_tnpc_tunnel_port 9056 * Tunnel port. 9057 * Access: Index 9058 */ 9059 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 9060 9061 /* reg_tnpc_learn_enable_v6 9062 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 9063 * Access: RW 9064 */ 9065 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 9066 9067 /* reg_tnpc_learn_enable_v4 9068 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 9069 * Access: RW 9070 */ 9071 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 9072 9073 static inline void mlxsw_reg_tnpc_pack(char *payload, 9074 enum mlxsw_reg_tnpc_tunnel_port tport, 9075 bool learn_enable) 9076 { 9077 MLXSW_REG_ZERO(tnpc, payload); 9078 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 9079 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 9080 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 9081 } 9082 9083 /* TIGCR - Tunneling IPinIP General Configuration Register 9084 * ------------------------------------------------------- 9085 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 9086 */ 9087 #define MLXSW_REG_TIGCR_ID 0xA801 9088 #define MLXSW_REG_TIGCR_LEN 0x10 9089 9090 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 9091 9092 /* reg_tigcr_ipip_ttlc 9093 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 9094 * header. 9095 * Access: RW 9096 */ 9097 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 9098 9099 /* reg_tigcr_ipip_ttl_uc 9100 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 9101 * reg_tigcr_ipip_ttlc is unset. 9102 * Access: RW 9103 */ 9104 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 9105 9106 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 9107 { 9108 MLXSW_REG_ZERO(tigcr, payload); 9109 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 9110 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 9111 } 9112 9113 /* SBPR - Shared Buffer Pools Register 9114 * ----------------------------------- 9115 * The SBPR configures and retrieves the shared buffer pools and configuration. 9116 */ 9117 #define MLXSW_REG_SBPR_ID 0xB001 9118 #define MLXSW_REG_SBPR_LEN 0x14 9119 9120 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 9121 9122 /* shared direstion enum for SBPR, SBCM, SBPM */ 9123 enum mlxsw_reg_sbxx_dir { 9124 MLXSW_REG_SBXX_DIR_INGRESS, 9125 MLXSW_REG_SBXX_DIR_EGRESS, 9126 }; 9127 9128 /* reg_sbpr_dir 9129 * Direction. 9130 * Access: Index 9131 */ 9132 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 9133 9134 /* reg_sbpr_pool 9135 * Pool index. 9136 * Access: Index 9137 */ 9138 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 9139 9140 /* reg_sbpr_infi_size 9141 * Size is infinite. 9142 * Access: RW 9143 */ 9144 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 9145 9146 /* reg_sbpr_size 9147 * Pool size in buffer cells. 9148 * Reserved when infi_size = 1. 9149 * Access: RW 9150 */ 9151 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 9152 9153 enum mlxsw_reg_sbpr_mode { 9154 MLXSW_REG_SBPR_MODE_STATIC, 9155 MLXSW_REG_SBPR_MODE_DYNAMIC, 9156 }; 9157 9158 /* reg_sbpr_mode 9159 * Pool quota calculation mode. 9160 * Access: RW 9161 */ 9162 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 9163 9164 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 9165 enum mlxsw_reg_sbxx_dir dir, 9166 enum mlxsw_reg_sbpr_mode mode, u32 size, 9167 bool infi_size) 9168 { 9169 MLXSW_REG_ZERO(sbpr, payload); 9170 mlxsw_reg_sbpr_pool_set(payload, pool); 9171 mlxsw_reg_sbpr_dir_set(payload, dir); 9172 mlxsw_reg_sbpr_mode_set(payload, mode); 9173 mlxsw_reg_sbpr_size_set(payload, size); 9174 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 9175 } 9176 9177 /* SBCM - Shared Buffer Class Management Register 9178 * ---------------------------------------------- 9179 * The SBCM register configures and retrieves the shared buffer allocation 9180 * and configuration according to Port-PG, including the binding to pool 9181 * and definition of the associated quota. 9182 */ 9183 #define MLXSW_REG_SBCM_ID 0xB002 9184 #define MLXSW_REG_SBCM_LEN 0x28 9185 9186 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 9187 9188 /* reg_sbcm_local_port 9189 * Local port number. 9190 * For Ingress: excludes CPU port and Router port 9191 * For Egress: excludes IP Router 9192 * Access: Index 9193 */ 9194 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 9195 9196 /* reg_sbcm_pg_buff 9197 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 9198 * For PG buffer: range is 0..cap_max_pg_buffers - 1 9199 * For traffic class: range is 0..cap_max_tclass - 1 9200 * Note that when traffic class is in MC aware mode then the traffic 9201 * classes which are MC aware cannot be configured. 9202 * Access: Index 9203 */ 9204 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 9205 9206 /* reg_sbcm_dir 9207 * Direction. 9208 * Access: Index 9209 */ 9210 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 9211 9212 /* reg_sbcm_min_buff 9213 * Minimum buffer size for the limiter, in cells. 9214 * Access: RW 9215 */ 9216 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 9217 9218 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 9219 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 9220 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 9221 9222 /* reg_sbcm_infi_max 9223 * Max buffer is infinite. 9224 * Access: RW 9225 */ 9226 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 9227 9228 /* reg_sbcm_max_buff 9229 * When the pool associated to the port-pg/tclass is configured to 9230 * static, Maximum buffer size for the limiter configured in cells. 9231 * When the pool associated to the port-pg/tclass is configured to 9232 * dynamic, the max_buff holds the "alpha" parameter, supporting 9233 * the following values: 9234 * 0: 0 9235 * i: (1/128)*2^(i-1), for i=1..14 9236 * 0xFF: Infinity 9237 * Reserved when infi_max = 1. 9238 * Access: RW 9239 */ 9240 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 9241 9242 /* reg_sbcm_pool 9243 * Association of the port-priority to a pool. 9244 * Access: RW 9245 */ 9246 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 9247 9248 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 9249 enum mlxsw_reg_sbxx_dir dir, 9250 u32 min_buff, u32 max_buff, 9251 bool infi_max, u8 pool) 9252 { 9253 MLXSW_REG_ZERO(sbcm, payload); 9254 mlxsw_reg_sbcm_local_port_set(payload, local_port); 9255 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 9256 mlxsw_reg_sbcm_dir_set(payload, dir); 9257 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 9258 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 9259 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 9260 mlxsw_reg_sbcm_pool_set(payload, pool); 9261 } 9262 9263 /* SBPM - Shared Buffer Port Management Register 9264 * --------------------------------------------- 9265 * The SBPM register configures and retrieves the shared buffer allocation 9266 * and configuration according to Port-Pool, including the definition 9267 * of the associated quota. 9268 */ 9269 #define MLXSW_REG_SBPM_ID 0xB003 9270 #define MLXSW_REG_SBPM_LEN 0x28 9271 9272 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 9273 9274 /* reg_sbpm_local_port 9275 * Local port number. 9276 * For Ingress: excludes CPU port and Router port 9277 * For Egress: excludes IP Router 9278 * Access: Index 9279 */ 9280 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 9281 9282 /* reg_sbpm_pool 9283 * The pool associated to quota counting on the local_port. 9284 * Access: Index 9285 */ 9286 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 9287 9288 /* reg_sbpm_dir 9289 * Direction. 9290 * Access: Index 9291 */ 9292 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 9293 9294 /* reg_sbpm_buff_occupancy 9295 * Current buffer occupancy in cells. 9296 * Access: RO 9297 */ 9298 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 9299 9300 /* reg_sbpm_clr 9301 * Clear Max Buffer Occupancy 9302 * When this bit is set, max_buff_occupancy field is cleared (and a 9303 * new max value is tracked from the time the clear was performed). 9304 * Access: OP 9305 */ 9306 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 9307 9308 /* reg_sbpm_max_buff_occupancy 9309 * Maximum value of buffer occupancy in cells monitored. Cleared by 9310 * writing to the clr field. 9311 * Access: RO 9312 */ 9313 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 9314 9315 /* reg_sbpm_min_buff 9316 * Minimum buffer size for the limiter, in cells. 9317 * Access: RW 9318 */ 9319 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 9320 9321 /* reg_sbpm_max_buff 9322 * When the pool associated to the port-pg/tclass is configured to 9323 * static, Maximum buffer size for the limiter configured in cells. 9324 * When the pool associated to the port-pg/tclass is configured to 9325 * dynamic, the max_buff holds the "alpha" parameter, supporting 9326 * the following values: 9327 * 0: 0 9328 * i: (1/128)*2^(i-1), for i=1..14 9329 * 0xFF: Infinity 9330 * Access: RW 9331 */ 9332 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 9333 9334 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 9335 enum mlxsw_reg_sbxx_dir dir, bool clr, 9336 u32 min_buff, u32 max_buff) 9337 { 9338 MLXSW_REG_ZERO(sbpm, payload); 9339 mlxsw_reg_sbpm_local_port_set(payload, local_port); 9340 mlxsw_reg_sbpm_pool_set(payload, pool); 9341 mlxsw_reg_sbpm_dir_set(payload, dir); 9342 mlxsw_reg_sbpm_clr_set(payload, clr); 9343 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 9344 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 9345 } 9346 9347 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 9348 u32 *p_max_buff_occupancy) 9349 { 9350 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 9351 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 9352 } 9353 9354 /* SBMM - Shared Buffer Multicast Management Register 9355 * -------------------------------------------------- 9356 * The SBMM register configures and retrieves the shared buffer allocation 9357 * and configuration for MC packets according to Switch-Priority, including 9358 * the binding to pool and definition of the associated quota. 9359 */ 9360 #define MLXSW_REG_SBMM_ID 0xB004 9361 #define MLXSW_REG_SBMM_LEN 0x28 9362 9363 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 9364 9365 /* reg_sbmm_prio 9366 * Switch Priority. 9367 * Access: Index 9368 */ 9369 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 9370 9371 /* reg_sbmm_min_buff 9372 * Minimum buffer size for the limiter, in cells. 9373 * Access: RW 9374 */ 9375 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 9376 9377 /* reg_sbmm_max_buff 9378 * When the pool associated to the port-pg/tclass is configured to 9379 * static, Maximum buffer size for the limiter configured in cells. 9380 * When the pool associated to the port-pg/tclass is configured to 9381 * dynamic, the max_buff holds the "alpha" parameter, supporting 9382 * the following values: 9383 * 0: 0 9384 * i: (1/128)*2^(i-1), for i=1..14 9385 * 0xFF: Infinity 9386 * Access: RW 9387 */ 9388 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 9389 9390 /* reg_sbmm_pool 9391 * Association of the port-priority to a pool. 9392 * Access: RW 9393 */ 9394 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 9395 9396 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 9397 u32 max_buff, u8 pool) 9398 { 9399 MLXSW_REG_ZERO(sbmm, payload); 9400 mlxsw_reg_sbmm_prio_set(payload, prio); 9401 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 9402 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 9403 mlxsw_reg_sbmm_pool_set(payload, pool); 9404 } 9405 9406 /* SBSR - Shared Buffer Status Register 9407 * ------------------------------------ 9408 * The SBSR register retrieves the shared buffer occupancy according to 9409 * Port-Pool. Note that this register enables reading a large amount of data. 9410 * It is the user's responsibility to limit the amount of data to ensure the 9411 * response can match the maximum transfer unit. In case the response exceeds 9412 * the maximum transport unit, it will be truncated with no special notice. 9413 */ 9414 #define MLXSW_REG_SBSR_ID 0xB005 9415 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 9416 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 9417 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 9418 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 9419 MLXSW_REG_SBSR_REC_LEN * \ 9420 MLXSW_REG_SBSR_REC_MAX_COUNT) 9421 9422 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 9423 9424 /* reg_sbsr_clr 9425 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 9426 * field is cleared (and a new max value is tracked from the time the clear 9427 * was performed). 9428 * Access: OP 9429 */ 9430 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 9431 9432 /* reg_sbsr_ingress_port_mask 9433 * Bit vector for all ingress network ports. 9434 * Indicates which of the ports (for which the relevant bit is set) 9435 * are affected by the set operation. Configuration of any other port 9436 * does not change. 9437 * Access: Index 9438 */ 9439 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 9440 9441 /* reg_sbsr_pg_buff_mask 9442 * Bit vector for all switch priority groups. 9443 * Indicates which of the priorities (for which the relevant bit is set) 9444 * are affected by the set operation. Configuration of any other priority 9445 * does not change. 9446 * Range is 0..cap_max_pg_buffers - 1 9447 * Access: Index 9448 */ 9449 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 9450 9451 /* reg_sbsr_egress_port_mask 9452 * Bit vector for all egress network ports. 9453 * Indicates which of the ports (for which the relevant bit is set) 9454 * are affected by the set operation. Configuration of any other port 9455 * does not change. 9456 * Access: Index 9457 */ 9458 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 9459 9460 /* reg_sbsr_tclass_mask 9461 * Bit vector for all traffic classes. 9462 * Indicates which of the traffic classes (for which the relevant bit is 9463 * set) are affected by the set operation. Configuration of any other 9464 * traffic class does not change. 9465 * Range is 0..cap_max_tclass - 1 9466 * Access: Index 9467 */ 9468 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 9469 9470 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 9471 { 9472 MLXSW_REG_ZERO(sbsr, payload); 9473 mlxsw_reg_sbsr_clr_set(payload, clr); 9474 } 9475 9476 /* reg_sbsr_rec_buff_occupancy 9477 * Current buffer occupancy in cells. 9478 * Access: RO 9479 */ 9480 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9481 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 9482 9483 /* reg_sbsr_rec_max_buff_occupancy 9484 * Maximum value of buffer occupancy in cells monitored. Cleared by 9485 * writing to the clr field. 9486 * Access: RO 9487 */ 9488 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9489 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 9490 9491 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 9492 u32 *p_buff_occupancy, 9493 u32 *p_max_buff_occupancy) 9494 { 9495 *p_buff_occupancy = 9496 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 9497 *p_max_buff_occupancy = 9498 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 9499 } 9500 9501 /* SBIB - Shared Buffer Internal Buffer Register 9502 * --------------------------------------------- 9503 * The SBIB register configures per port buffers for internal use. The internal 9504 * buffers consume memory on the port buffers (note that the port buffers are 9505 * used also by PBMC). 9506 * 9507 * For Spectrum this is used for egress mirroring. 9508 */ 9509 #define MLXSW_REG_SBIB_ID 0xB006 9510 #define MLXSW_REG_SBIB_LEN 0x10 9511 9512 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 9513 9514 /* reg_sbib_local_port 9515 * Local port number 9516 * Not supported for CPU port and router port 9517 * Access: Index 9518 */ 9519 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 9520 9521 /* reg_sbib_buff_size 9522 * Units represented in cells 9523 * Allowed range is 0 to (cap_max_headroom_size - 1) 9524 * Default is 0 9525 * Access: RW 9526 */ 9527 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 9528 9529 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 9530 u32 buff_size) 9531 { 9532 MLXSW_REG_ZERO(sbib, payload); 9533 mlxsw_reg_sbib_local_port_set(payload, local_port); 9534 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 9535 } 9536 9537 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 9538 MLXSW_REG(sgcr), 9539 MLXSW_REG(spad), 9540 MLXSW_REG(smid), 9541 MLXSW_REG(sspr), 9542 MLXSW_REG(sfdat), 9543 MLXSW_REG(sfd), 9544 MLXSW_REG(sfn), 9545 MLXSW_REG(spms), 9546 MLXSW_REG(spvid), 9547 MLXSW_REG(spvm), 9548 MLXSW_REG(spaft), 9549 MLXSW_REG(sfgc), 9550 MLXSW_REG(sftr), 9551 MLXSW_REG(sfdf), 9552 MLXSW_REG(sldr), 9553 MLXSW_REG(slcr), 9554 MLXSW_REG(slcor), 9555 MLXSW_REG(spmlr), 9556 MLXSW_REG(svfa), 9557 MLXSW_REG(svpe), 9558 MLXSW_REG(sfmr), 9559 MLXSW_REG(spvmlr), 9560 MLXSW_REG(cwtp), 9561 MLXSW_REG(cwtpm), 9562 MLXSW_REG(pgcr), 9563 MLXSW_REG(ppbt), 9564 MLXSW_REG(pacl), 9565 MLXSW_REG(pagt), 9566 MLXSW_REG(ptar), 9567 MLXSW_REG(ppbs), 9568 MLXSW_REG(prcr), 9569 MLXSW_REG(pefa), 9570 MLXSW_REG(ptce2), 9571 MLXSW_REG(perpt), 9572 MLXSW_REG(perar), 9573 MLXSW_REG(ptce3), 9574 MLXSW_REG(percr), 9575 MLXSW_REG(pererp), 9576 MLXSW_REG(iedr), 9577 MLXSW_REG(qpts), 9578 MLXSW_REG(qpcr), 9579 MLXSW_REG(qtct), 9580 MLXSW_REG(qeec), 9581 MLXSW_REG(qrwe), 9582 MLXSW_REG(qpdsm), 9583 MLXSW_REG(qpdpm), 9584 MLXSW_REG(qtctm), 9585 MLXSW_REG(pmlp), 9586 MLXSW_REG(pmtu), 9587 MLXSW_REG(ptys), 9588 MLXSW_REG(ppad), 9589 MLXSW_REG(paos), 9590 MLXSW_REG(pfcc), 9591 MLXSW_REG(ppcnt), 9592 MLXSW_REG(plib), 9593 MLXSW_REG(pptb), 9594 MLXSW_REG(pbmc), 9595 MLXSW_REG(pspa), 9596 MLXSW_REG(htgt), 9597 MLXSW_REG(hpkt), 9598 MLXSW_REG(rgcr), 9599 MLXSW_REG(ritr), 9600 MLXSW_REG(rtar), 9601 MLXSW_REG(ratr), 9602 MLXSW_REG(rtdp), 9603 MLXSW_REG(rdpm), 9604 MLXSW_REG(ricnt), 9605 MLXSW_REG(rrcr), 9606 MLXSW_REG(ralta), 9607 MLXSW_REG(ralst), 9608 MLXSW_REG(raltb), 9609 MLXSW_REG(ralue), 9610 MLXSW_REG(rauht), 9611 MLXSW_REG(raleu), 9612 MLXSW_REG(rauhtd), 9613 MLXSW_REG(rigr2), 9614 MLXSW_REG(recr2), 9615 MLXSW_REG(rmft2), 9616 MLXSW_REG(mfcr), 9617 MLXSW_REG(mfsc), 9618 MLXSW_REG(mfsm), 9619 MLXSW_REG(mfsl), 9620 MLXSW_REG(mtcap), 9621 MLXSW_REG(mtmp), 9622 MLXSW_REG(mcia), 9623 MLXSW_REG(mpat), 9624 MLXSW_REG(mpar), 9625 MLXSW_REG(mrsr), 9626 MLXSW_REG(mlcr), 9627 MLXSW_REG(mpsc), 9628 MLXSW_REG(mcqi), 9629 MLXSW_REG(mcc), 9630 MLXSW_REG(mcda), 9631 MLXSW_REG(mgpc), 9632 MLXSW_REG(mprs), 9633 MLXSW_REG(tngcr), 9634 MLXSW_REG(tnumt), 9635 MLXSW_REG(tnqcr), 9636 MLXSW_REG(tnqdr), 9637 MLXSW_REG(tneem), 9638 MLXSW_REG(tndem), 9639 MLXSW_REG(tnpc), 9640 MLXSW_REG(tigcr), 9641 MLXSW_REG(sbpr), 9642 MLXSW_REG(sbcm), 9643 MLXSW_REG(sbpm), 9644 MLXSW_REG(sbmm), 9645 MLXSW_REG(sbsr), 9646 MLXSW_REG(sbib), 9647 }; 9648 9649 static inline const char *mlxsw_reg_id_str(u16 reg_id) 9650 { 9651 const struct mlxsw_reg_info *reg_info; 9652 int i; 9653 9654 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 9655 reg_info = mlxsw_reg_infos[i]; 9656 if (reg_info->id == reg_id) 9657 return reg_info->name; 9658 } 9659 return "*UNKNOWN*"; 9660 } 9661 9662 /* PUDE - Port Up / Down Event 9663 * --------------------------- 9664 * Reports the operational state change of a port. 9665 */ 9666 #define MLXSW_REG_PUDE_LEN 0x10 9667 9668 /* reg_pude_swid 9669 * Switch partition ID with which to associate the port. 9670 * Access: Index 9671 */ 9672 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 9673 9674 /* reg_pude_local_port 9675 * Local port number. 9676 * Access: Index 9677 */ 9678 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 9679 9680 /* reg_pude_admin_status 9681 * Port administrative state (the desired state). 9682 * 1 - Up. 9683 * 2 - Down. 9684 * 3 - Up once. This means that in case of link failure, the port won't go 9685 * into polling mode, but will wait to be re-enabled by software. 9686 * 4 - Disabled by system. Can only be set by hardware. 9687 * Access: RO 9688 */ 9689 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 9690 9691 /* reg_pude_oper_status 9692 * Port operatioanl state. 9693 * 1 - Up. 9694 * 2 - Down. 9695 * 3 - Down by port failure. This means that the device will not let the 9696 * port up again until explicitly specified by software. 9697 * Access: RO 9698 */ 9699 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 9700 9701 #endif 9702