1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com> 8 * Copyright (c) 2017 Petr Machata <petrm@mellanox.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the names of the copyright holders nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MLXSW_REG_H 40 #define _MLXSW_REG_H 41 42 #include <linux/string.h> 43 #include <linux/bitops.h> 44 #include <linux/if_vlan.h> 45 46 #include "item.h" 47 #include "port.h" 48 49 struct mlxsw_reg_info { 50 u16 id; 51 u16 len; /* In u8 */ 52 const char *name; 53 }; 54 55 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 56 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 57 .id = _id, \ 58 .len = _len, \ 59 .name = #_name, \ 60 } 61 62 #define MLXSW_REG(type) (&mlxsw_reg_##type) 63 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 64 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 65 66 /* SGCR - Switch General Configuration Register 67 * -------------------------------------------- 68 * This register is used for configuration of the switch capabilities. 69 */ 70 #define MLXSW_REG_SGCR_ID 0x2000 71 #define MLXSW_REG_SGCR_LEN 0x10 72 73 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 74 75 /* reg_sgcr_llb 76 * Link Local Broadcast (Default=0) 77 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 78 * packets and ignore the IGMP snooping entries. 79 * Access: RW 80 */ 81 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 82 83 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 84 { 85 MLXSW_REG_ZERO(sgcr, payload); 86 mlxsw_reg_sgcr_llb_set(payload, !!llb); 87 } 88 89 /* SPAD - Switch Physical Address Register 90 * --------------------------------------- 91 * The SPAD register configures the switch physical MAC address. 92 */ 93 #define MLXSW_REG_SPAD_ID 0x2002 94 #define MLXSW_REG_SPAD_LEN 0x10 95 96 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 97 98 /* reg_spad_base_mac 99 * Base MAC address for the switch partitions. 100 * Per switch partition MAC address is equal to: 101 * base_mac + swid 102 * Access: RW 103 */ 104 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 105 106 /* SMID - Switch Multicast ID 107 * -------------------------- 108 * The MID record maps from a MID (Multicast ID), which is a unique identifier 109 * of the multicast group within the stacking domain, into a list of local 110 * ports into which the packet is replicated. 111 */ 112 #define MLXSW_REG_SMID_ID 0x2007 113 #define MLXSW_REG_SMID_LEN 0x240 114 115 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 116 117 /* reg_smid_swid 118 * Switch partition ID. 119 * Access: Index 120 */ 121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 122 123 /* reg_smid_mid 124 * Multicast identifier - global identifier that represents the multicast group 125 * across all devices. 126 * Access: Index 127 */ 128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 129 130 /* reg_smid_port 131 * Local port memebership (1 bit per port). 132 * Access: RW 133 */ 134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 135 136 /* reg_smid_port_mask 137 * Local port mask (1 bit per port). 138 * Access: W 139 */ 140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 141 142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 143 u8 port, bool set) 144 { 145 MLXSW_REG_ZERO(smid, payload); 146 mlxsw_reg_smid_swid_set(payload, 0); 147 mlxsw_reg_smid_mid_set(payload, mid); 148 mlxsw_reg_smid_port_set(payload, port, set); 149 mlxsw_reg_smid_port_mask_set(payload, port, 1); 150 } 151 152 /* SSPR - Switch System Port Record Register 153 * ----------------------------------------- 154 * Configures the system port to local port mapping. 155 */ 156 #define MLXSW_REG_SSPR_ID 0x2008 157 #define MLXSW_REG_SSPR_LEN 0x8 158 159 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 160 161 /* reg_sspr_m 162 * Master - if set, then the record describes the master system port. 163 * This is needed in case a local port is mapped into several system ports 164 * (for multipathing). That number will be reported as the source system 165 * port when packets are forwarded to the CPU. Only one master port is allowed 166 * per local port. 167 * 168 * Note: Must be set for Spectrum. 169 * Access: RW 170 */ 171 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 172 173 /* reg_sspr_local_port 174 * Local port number. 175 * 176 * Access: RW 177 */ 178 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 179 180 /* reg_sspr_sub_port 181 * Virtual port within the physical port. 182 * Should be set to 0 when virtual ports are not enabled on the port. 183 * 184 * Access: RW 185 */ 186 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 187 188 /* reg_sspr_system_port 189 * Unique identifier within the stacking domain that represents all the ports 190 * that are available in the system (external ports). 191 * 192 * Currently, only single-ASIC configurations are supported, so we default to 193 * 1:1 mapping between system ports and local ports. 194 * Access: Index 195 */ 196 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 197 198 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 199 { 200 MLXSW_REG_ZERO(sspr, payload); 201 mlxsw_reg_sspr_m_set(payload, 1); 202 mlxsw_reg_sspr_local_port_set(payload, local_port); 203 mlxsw_reg_sspr_sub_port_set(payload, 0); 204 mlxsw_reg_sspr_system_port_set(payload, local_port); 205 } 206 207 /* SFDAT - Switch Filtering Database Aging Time 208 * -------------------------------------------- 209 * Controls the Switch aging time. Aging time is able to be set per Switch 210 * Partition. 211 */ 212 #define MLXSW_REG_SFDAT_ID 0x2009 213 #define MLXSW_REG_SFDAT_LEN 0x8 214 215 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 216 217 /* reg_sfdat_swid 218 * Switch partition ID. 219 * Access: Index 220 */ 221 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 222 223 /* reg_sfdat_age_time 224 * Aging time in seconds 225 * Min - 10 seconds 226 * Max - 1,000,000 seconds 227 * Default is 300 seconds. 228 * Access: RW 229 */ 230 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 231 232 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 233 { 234 MLXSW_REG_ZERO(sfdat, payload); 235 mlxsw_reg_sfdat_swid_set(payload, 0); 236 mlxsw_reg_sfdat_age_time_set(payload, age_time); 237 } 238 239 /* SFD - Switch Filtering Database 240 * ------------------------------- 241 * The following register defines the access to the filtering database. 242 * The register supports querying, adding, removing and modifying the database. 243 * The access is optimized for bulk updates in which case more than one 244 * FDB record is present in the same command. 245 */ 246 #define MLXSW_REG_SFD_ID 0x200A 247 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 248 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 249 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 250 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 251 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 252 253 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 254 255 /* reg_sfd_swid 256 * Switch partition ID for queries. Reserved on Write. 257 * Access: Index 258 */ 259 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 260 261 enum mlxsw_reg_sfd_op { 262 /* Dump entire FDB a (process according to record_locator) */ 263 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 264 /* Query records by {MAC, VID/FID} value */ 265 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 266 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 267 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 268 /* Test. Response indicates if each of the records could be 269 * added to the FDB. 270 */ 271 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 272 /* Add/modify. Aged-out records cannot be added. This command removes 273 * the learning notification of the {MAC, VID/FID}. Response includes 274 * the entries that were added to the FDB. 275 */ 276 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 277 /* Remove record by {MAC, VID/FID}. This command also removes 278 * the learning notification and aged-out notifications 279 * of the {MAC, VID/FID}. The response provides current (pre-removal) 280 * entries as non-aged-out. 281 */ 282 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 283 /* Remove learned notification by {MAC, VID/FID}. The response provides 284 * the removed learning notification. 285 */ 286 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 287 }; 288 289 /* reg_sfd_op 290 * Operation. 291 * Access: OP 292 */ 293 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 294 295 /* reg_sfd_record_locator 296 * Used for querying the FDB. Use record_locator=0 to initiate the 297 * query. When a record is returned, a new record_locator is 298 * returned to be used in the subsequent query. 299 * Reserved for database update. 300 * Access: Index 301 */ 302 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 303 304 /* reg_sfd_num_rec 305 * Request: Number of records to read/add/modify/remove 306 * Response: Number of records read/added/replaced/removed 307 * See above description for more details. 308 * Ranges 0..64 309 * Access: RW 310 */ 311 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 312 313 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 314 u32 record_locator) 315 { 316 MLXSW_REG_ZERO(sfd, payload); 317 mlxsw_reg_sfd_op_set(payload, op); 318 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 319 } 320 321 /* reg_sfd_rec_swid 322 * Switch partition ID. 323 * Access: Index 324 */ 325 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 326 MLXSW_REG_SFD_REC_LEN, 0x00, false); 327 328 enum mlxsw_reg_sfd_rec_type { 329 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 330 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 331 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 332 }; 333 334 /* reg_sfd_rec_type 335 * FDB record type. 336 * Access: RW 337 */ 338 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 339 MLXSW_REG_SFD_REC_LEN, 0x00, false); 340 341 enum mlxsw_reg_sfd_rec_policy { 342 /* Replacement disabled, aging disabled. */ 343 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 344 /* (mlag remote): Replacement enabled, aging disabled, 345 * learning notification enabled on this port. 346 */ 347 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 348 /* (ingress device): Replacement enabled, aging enabled. */ 349 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 350 }; 351 352 /* reg_sfd_rec_policy 353 * Policy. 354 * Access: RW 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 357 MLXSW_REG_SFD_REC_LEN, 0x00, false); 358 359 /* reg_sfd_rec_a 360 * Activity. Set for new static entries. Set for static entries if a frame SMAC 361 * lookup hits on the entry. 362 * To clear the a bit, use "query and clear activity" op. 363 * Access: RO 364 */ 365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 366 MLXSW_REG_SFD_REC_LEN, 0x00, false); 367 368 /* reg_sfd_rec_mac 369 * MAC address. 370 * Access: Index 371 */ 372 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 373 MLXSW_REG_SFD_REC_LEN, 0x02); 374 375 enum mlxsw_reg_sfd_rec_action { 376 /* forward */ 377 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 378 /* forward and trap, trap_id is FDB_TRAP */ 379 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 380 /* trap and do not forward, trap_id is FDB_TRAP */ 381 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 382 /* forward to IP router */ 383 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 384 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 385 }; 386 387 /* reg_sfd_rec_action 388 * Action to apply on the packet. 389 * Note: Dynamic entries can only be configured with NOP action. 390 * Access: RW 391 */ 392 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 393 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 394 395 /* reg_sfd_uc_sub_port 396 * VEPA channel on local port. 397 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 398 * VEPA is not enabled. 399 * Access: RW 400 */ 401 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 402 MLXSW_REG_SFD_REC_LEN, 0x08, false); 403 404 /* reg_sfd_uc_fid_vid 405 * Filtering ID or VLAN ID 406 * For SwitchX and SwitchX-2: 407 * - Dynamic entries (policy 2,3) use FID 408 * - Static entries (policy 0) use VID 409 * - When independent learning is configured, VID=FID 410 * For Spectrum: use FID for both Dynamic and Static entries. 411 * VID should not be used. 412 * Access: Index 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_system_port 418 * Unique port identifier for the final destination of the packet. 419 * Access: RW 420 */ 421 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 422 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 423 424 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 425 enum mlxsw_reg_sfd_rec_type rec_type, 426 const char *mac, 427 enum mlxsw_reg_sfd_rec_action action) 428 { 429 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 430 431 if (rec_index >= num_rec) 432 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 433 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 434 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 435 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 436 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 437 } 438 439 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 440 enum mlxsw_reg_sfd_rec_policy policy, 441 const char *mac, u16 fid_vid, 442 enum mlxsw_reg_sfd_rec_action action, 443 u8 local_port) 444 { 445 mlxsw_reg_sfd_rec_pack(payload, rec_index, 446 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 448 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 449 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 450 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 451 } 452 453 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 454 char *mac, u16 *p_fid_vid, 455 u8 *p_local_port) 456 { 457 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 458 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 459 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 460 } 461 462 /* reg_sfd_uc_lag_sub_port 463 * LAG sub port. 464 * Must be 0 if multichannel VEPA is not enabled. 465 * Access: RW 466 */ 467 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 468 MLXSW_REG_SFD_REC_LEN, 0x08, false); 469 470 /* reg_sfd_uc_lag_fid_vid 471 * Filtering ID or VLAN ID 472 * For SwitchX and SwitchX-2: 473 * - Dynamic entries (policy 2,3) use FID 474 * - Static entries (policy 0) use VID 475 * - When independent learning is configured, VID=FID 476 * For Spectrum: use FID for both Dynamic and Static entries. 477 * VID should not be used. 478 * Access: Index 479 */ 480 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 481 MLXSW_REG_SFD_REC_LEN, 0x08, false); 482 483 /* reg_sfd_uc_lag_lag_vid 484 * Indicates VID in case of vFIDs. Reserved for FIDs. 485 * Access: RW 486 */ 487 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 488 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 489 490 /* reg_sfd_uc_lag_lag_id 491 * LAG Identifier - pointer into the LAG descriptor table. 492 * Access: RW 493 */ 494 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 495 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 496 497 static inline void 498 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 499 enum mlxsw_reg_sfd_rec_policy policy, 500 const char *mac, u16 fid_vid, 501 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 502 u16 lag_id) 503 { 504 mlxsw_reg_sfd_rec_pack(payload, rec_index, 505 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 506 mac, action); 507 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 508 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 509 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 510 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 511 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 512 } 513 514 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 515 char *mac, u16 *p_vid, 516 u16 *p_lag_id) 517 { 518 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 519 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 520 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 521 } 522 523 /* reg_sfd_mc_pgi 524 * 525 * Multicast port group index - index into the port group table. 526 * Value 0x1FFF indicates the pgi should point to the MID entry. 527 * For Spectrum this value must be set to 0x1FFF 528 * Access: RW 529 */ 530 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 531 MLXSW_REG_SFD_REC_LEN, 0x08, false); 532 533 /* reg_sfd_mc_fid_vid 534 * 535 * Filtering ID or VLAN ID 536 * Access: Index 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 539 MLXSW_REG_SFD_REC_LEN, 0x08, false); 540 541 /* reg_sfd_mc_mid 542 * 543 * Multicast identifier - global identifier that represents the multicast 544 * group across all devices. 545 * Access: RW 546 */ 547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 548 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 549 550 static inline void 551 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 552 const char *mac, u16 fid_vid, 553 enum mlxsw_reg_sfd_rec_action action, u16 mid) 554 { 555 mlxsw_reg_sfd_rec_pack(payload, rec_index, 556 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 557 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 558 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 559 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 560 } 561 562 /* SFN - Switch FDB Notification Register 563 * ------------------------------------------- 564 * The switch provides notifications on newly learned FDB entries and 565 * aged out entries. The notifications can be polled by software. 566 */ 567 #define MLXSW_REG_SFN_ID 0x200B 568 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 569 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 570 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 571 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 572 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 573 574 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 575 576 /* reg_sfn_swid 577 * Switch partition ID. 578 * Access: Index 579 */ 580 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 581 582 /* reg_sfn_end 583 * Forces the current session to end. 584 * Access: OP 585 */ 586 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 587 588 /* reg_sfn_num_rec 589 * Request: Number of learned notifications and aged-out notification 590 * records requested. 591 * Response: Number of notification records returned (must be smaller 592 * than or equal to the value requested) 593 * Ranges 0..64 594 * Access: OP 595 */ 596 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 597 598 static inline void mlxsw_reg_sfn_pack(char *payload) 599 { 600 MLXSW_REG_ZERO(sfn, payload); 601 mlxsw_reg_sfn_swid_set(payload, 0); 602 mlxsw_reg_sfn_end_set(payload, 1); 603 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 604 } 605 606 /* reg_sfn_rec_swid 607 * Switch partition ID. 608 * Access: RO 609 */ 610 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 611 MLXSW_REG_SFN_REC_LEN, 0x00, false); 612 613 enum mlxsw_reg_sfn_rec_type { 614 /* MAC addresses learned on a regular port. */ 615 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 616 /* MAC addresses learned on a LAG port. */ 617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 618 /* Aged-out MAC address on a regular port. */ 619 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 620 /* Aged-out MAC address on a LAG port. */ 621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 622 }; 623 624 /* reg_sfn_rec_type 625 * Notification record type. 626 * Access: RO 627 */ 628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 629 MLXSW_REG_SFN_REC_LEN, 0x00, false); 630 631 /* reg_sfn_rec_mac 632 * MAC address. 633 * Access: RO 634 */ 635 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 636 MLXSW_REG_SFN_REC_LEN, 0x02); 637 638 /* reg_sfn_mac_sub_port 639 * VEPA channel on the local port. 640 * 0 if multichannel VEPA is not enabled. 641 * Access: RO 642 */ 643 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 644 MLXSW_REG_SFN_REC_LEN, 0x08, false); 645 646 /* reg_sfn_mac_fid 647 * Filtering identifier. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 651 MLXSW_REG_SFN_REC_LEN, 0x08, false); 652 653 /* reg_sfn_mac_system_port 654 * Unique port identifier for the final destination of the packet. 655 * Access: RO 656 */ 657 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 658 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 659 660 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 661 char *mac, u16 *p_vid, 662 u8 *p_local_port) 663 { 664 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 665 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 666 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 667 } 668 669 /* reg_sfn_mac_lag_lag_id 670 * LAG ID (pointer into the LAG descriptor table). 671 * Access: RO 672 */ 673 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 674 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 675 676 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 677 char *mac, u16 *p_vid, 678 u16 *p_lag_id) 679 { 680 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 681 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 682 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 683 } 684 685 /* SPMS - Switch Port MSTP/RSTP State Register 686 * ------------------------------------------- 687 * Configures the spanning tree state of a physical port. 688 */ 689 #define MLXSW_REG_SPMS_ID 0x200D 690 #define MLXSW_REG_SPMS_LEN 0x404 691 692 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 693 694 /* reg_spms_local_port 695 * Local port number. 696 * Access: Index 697 */ 698 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 699 700 enum mlxsw_reg_spms_state { 701 MLXSW_REG_SPMS_STATE_NO_CHANGE, 702 MLXSW_REG_SPMS_STATE_DISCARDING, 703 MLXSW_REG_SPMS_STATE_LEARNING, 704 MLXSW_REG_SPMS_STATE_FORWARDING, 705 }; 706 707 /* reg_spms_state 708 * Spanning tree state of each VLAN ID (VID) of the local port. 709 * 0 - Do not change spanning tree state (used only when writing). 710 * 1 - Discarding. No learning or forwarding to/from this port (default). 711 * 2 - Learning. Port is learning, but not forwarding. 712 * 3 - Forwarding. Port is learning and forwarding. 713 * Access: RW 714 */ 715 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 716 717 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 718 { 719 MLXSW_REG_ZERO(spms, payload); 720 mlxsw_reg_spms_local_port_set(payload, local_port); 721 } 722 723 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 724 enum mlxsw_reg_spms_state state) 725 { 726 mlxsw_reg_spms_state_set(payload, vid, state); 727 } 728 729 /* SPVID - Switch Port VID 730 * ----------------------- 731 * The switch port VID configures the default VID for a port. 732 */ 733 #define MLXSW_REG_SPVID_ID 0x200E 734 #define MLXSW_REG_SPVID_LEN 0x08 735 736 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 737 738 /* reg_spvid_local_port 739 * Local port number. 740 * Access: Index 741 */ 742 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 743 744 /* reg_spvid_sub_port 745 * Virtual port within the physical port. 746 * Should be set to 0 when virtual ports are not enabled on the port. 747 * Access: Index 748 */ 749 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 750 751 /* reg_spvid_pvid 752 * Port default VID 753 * Access: RW 754 */ 755 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 756 757 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 758 { 759 MLXSW_REG_ZERO(spvid, payload); 760 mlxsw_reg_spvid_local_port_set(payload, local_port); 761 mlxsw_reg_spvid_pvid_set(payload, pvid); 762 } 763 764 /* SPVM - Switch Port VLAN Membership 765 * ---------------------------------- 766 * The Switch Port VLAN Membership register configures the VLAN membership 767 * of a port in a VLAN denoted by VID. VLAN membership is managed per 768 * virtual port. The register can be used to add and remove VID(s) from a port. 769 */ 770 #define MLXSW_REG_SPVM_ID 0x200F 771 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 772 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 773 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 774 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 775 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 776 777 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 778 779 /* reg_spvm_pt 780 * Priority tagged. If this bit is set, packets forwarded to the port with 781 * untagged VLAN membership (u bit is set) will be tagged with priority tag 782 * (VID=0) 783 * Access: RW 784 */ 785 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 786 787 /* reg_spvm_pte 788 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 789 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 790 * Access: WO 791 */ 792 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 793 794 /* reg_spvm_local_port 795 * Local port number. 796 * Access: Index 797 */ 798 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 799 800 /* reg_spvm_sub_port 801 * Virtual port within the physical port. 802 * Should be set to 0 when virtual ports are not enabled on the port. 803 * Access: Index 804 */ 805 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 806 807 /* reg_spvm_num_rec 808 * Number of records to update. Each record contains: i, e, u, vid. 809 * Access: OP 810 */ 811 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 812 813 /* reg_spvm_rec_i 814 * Ingress membership in VLAN ID. 815 * Access: Index 816 */ 817 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 818 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 819 MLXSW_REG_SPVM_REC_LEN, 0, false); 820 821 /* reg_spvm_rec_e 822 * Egress membership in VLAN ID. 823 * Access: Index 824 */ 825 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 826 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 827 MLXSW_REG_SPVM_REC_LEN, 0, false); 828 829 /* reg_spvm_rec_u 830 * Untagged - port is an untagged member - egress transmission uses untagged 831 * frames on VID<n> 832 * Access: Index 833 */ 834 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 835 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 836 MLXSW_REG_SPVM_REC_LEN, 0, false); 837 838 /* reg_spvm_rec_vid 839 * Egress membership in VLAN ID. 840 * Access: Index 841 */ 842 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 843 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 844 MLXSW_REG_SPVM_REC_LEN, 0, false); 845 846 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 847 u16 vid_begin, u16 vid_end, 848 bool is_member, bool untagged) 849 { 850 int size = vid_end - vid_begin + 1; 851 int i; 852 853 MLXSW_REG_ZERO(spvm, payload); 854 mlxsw_reg_spvm_local_port_set(payload, local_port); 855 mlxsw_reg_spvm_num_rec_set(payload, size); 856 857 for (i = 0; i < size; i++) { 858 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 859 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 860 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 861 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 862 } 863 } 864 865 /* SPAFT - Switch Port Acceptable Frame Types 866 * ------------------------------------------ 867 * The Switch Port Acceptable Frame Types register configures the frame 868 * admittance of the port. 869 */ 870 #define MLXSW_REG_SPAFT_ID 0x2010 871 #define MLXSW_REG_SPAFT_LEN 0x08 872 873 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 874 875 /* reg_spaft_local_port 876 * Local port number. 877 * Access: Index 878 * 879 * Note: CPU port is not supported (all tag types are allowed). 880 */ 881 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 882 883 /* reg_spaft_sub_port 884 * Virtual port within the physical port. 885 * Should be set to 0 when virtual ports are not enabled on the port. 886 * Access: RW 887 */ 888 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 889 890 /* reg_spaft_allow_untagged 891 * When set, untagged frames on the ingress are allowed (default). 892 * Access: RW 893 */ 894 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 895 896 /* reg_spaft_allow_prio_tagged 897 * When set, priority tagged frames on the ingress are allowed (default). 898 * Access: RW 899 */ 900 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 901 902 /* reg_spaft_allow_tagged 903 * When set, tagged frames on the ingress are allowed (default). 904 * Access: RW 905 */ 906 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 907 908 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 909 bool allow_untagged) 910 { 911 MLXSW_REG_ZERO(spaft, payload); 912 mlxsw_reg_spaft_local_port_set(payload, local_port); 913 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 914 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 915 mlxsw_reg_spaft_allow_tagged_set(payload, true); 916 } 917 918 /* SFGC - Switch Flooding Group Configuration 919 * ------------------------------------------ 920 * The following register controls the association of flooding tables and MIDs 921 * to packet types used for flooding. 922 */ 923 #define MLXSW_REG_SFGC_ID 0x2011 924 #define MLXSW_REG_SFGC_LEN 0x10 925 926 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 927 928 enum mlxsw_reg_sfgc_type { 929 MLXSW_REG_SFGC_TYPE_BROADCAST, 930 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 931 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 932 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 933 MLXSW_REG_SFGC_TYPE_RESERVED, 934 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 935 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 936 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 937 MLXSW_REG_SFGC_TYPE_MAX, 938 }; 939 940 /* reg_sfgc_type 941 * The traffic type to reach the flooding table. 942 * Access: Index 943 */ 944 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 945 946 enum mlxsw_reg_sfgc_bridge_type { 947 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 948 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 949 }; 950 951 /* reg_sfgc_bridge_type 952 * Access: Index 953 * 954 * Note: SwitchX-2 only supports 802.1Q mode. 955 */ 956 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 957 958 enum mlxsw_flood_table_type { 959 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 960 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 961 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 962 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 963 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 964 }; 965 966 /* reg_sfgc_table_type 967 * See mlxsw_flood_table_type 968 * Access: RW 969 * 970 * Note: FID offset and FID types are not supported in SwitchX-2. 971 */ 972 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 973 974 /* reg_sfgc_flood_table 975 * Flooding table index to associate with the specific type on the specific 976 * switch partition. 977 * Access: RW 978 */ 979 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 980 981 /* reg_sfgc_mid 982 * The multicast ID for the swid. Not supported for Spectrum 983 * Access: RW 984 */ 985 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 986 987 /* reg_sfgc_counter_set_type 988 * Counter Set Type for flow counters. 989 * Access: RW 990 */ 991 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 992 993 /* reg_sfgc_counter_index 994 * Counter Index for flow counters. 995 * Access: RW 996 */ 997 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 998 999 static inline void 1000 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1001 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1002 enum mlxsw_flood_table_type table_type, 1003 unsigned int flood_table) 1004 { 1005 MLXSW_REG_ZERO(sfgc, payload); 1006 mlxsw_reg_sfgc_type_set(payload, type); 1007 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1008 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1009 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1010 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1011 } 1012 1013 /* SFTR - Switch Flooding Table Register 1014 * ------------------------------------- 1015 * The switch flooding table is used for flooding packet replication. The table 1016 * defines a bit mask of ports for packet replication. 1017 */ 1018 #define MLXSW_REG_SFTR_ID 0x2012 1019 #define MLXSW_REG_SFTR_LEN 0x420 1020 1021 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1022 1023 /* reg_sftr_swid 1024 * Switch partition ID with which to associate the port. 1025 * Access: Index 1026 */ 1027 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1028 1029 /* reg_sftr_flood_table 1030 * Flooding table index to associate with the specific type on the specific 1031 * switch partition. 1032 * Access: Index 1033 */ 1034 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1035 1036 /* reg_sftr_index 1037 * Index. Used as an index into the Flooding Table in case the table is 1038 * configured to use VID / FID or FID Offset. 1039 * Access: Index 1040 */ 1041 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1042 1043 /* reg_sftr_table_type 1044 * See mlxsw_flood_table_type 1045 * Access: RW 1046 */ 1047 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1048 1049 /* reg_sftr_range 1050 * Range of entries to update 1051 * Access: Index 1052 */ 1053 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1054 1055 /* reg_sftr_port 1056 * Local port membership (1 bit per port). 1057 * Access: RW 1058 */ 1059 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1060 1061 /* reg_sftr_cpu_port_mask 1062 * CPU port mask (1 bit per port). 1063 * Access: W 1064 */ 1065 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1066 1067 static inline void mlxsw_reg_sftr_pack(char *payload, 1068 unsigned int flood_table, 1069 unsigned int index, 1070 enum mlxsw_flood_table_type table_type, 1071 unsigned int range, u8 port, bool set) 1072 { 1073 MLXSW_REG_ZERO(sftr, payload); 1074 mlxsw_reg_sftr_swid_set(payload, 0); 1075 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1076 mlxsw_reg_sftr_index_set(payload, index); 1077 mlxsw_reg_sftr_table_type_set(payload, table_type); 1078 mlxsw_reg_sftr_range_set(payload, range); 1079 mlxsw_reg_sftr_port_set(payload, port, set); 1080 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1081 } 1082 1083 /* SFDF - Switch Filtering DB Flush 1084 * -------------------------------- 1085 * The switch filtering DB flush register is used to flush the FDB. 1086 * Note that FDB notifications are flushed as well. 1087 */ 1088 #define MLXSW_REG_SFDF_ID 0x2013 1089 #define MLXSW_REG_SFDF_LEN 0x14 1090 1091 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1092 1093 /* reg_sfdf_swid 1094 * Switch partition ID. 1095 * Access: Index 1096 */ 1097 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1098 1099 enum mlxsw_reg_sfdf_flush_type { 1100 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1101 MLXSW_REG_SFDF_FLUSH_PER_FID, 1102 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1103 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1104 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1105 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1106 }; 1107 1108 /* reg_sfdf_flush_type 1109 * Flush type. 1110 * 0 - All SWID dynamic entries are flushed. 1111 * 1 - All FID dynamic entries are flushed. 1112 * 2 - All dynamic entries pointing to port are flushed. 1113 * 3 - All FID dynamic entries pointing to port are flushed. 1114 * 4 - All dynamic entries pointing to LAG are flushed. 1115 * 5 - All FID dynamic entries pointing to LAG are flushed. 1116 * Access: RW 1117 */ 1118 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1119 1120 /* reg_sfdf_flush_static 1121 * Static. 1122 * 0 - Flush only dynamic entries. 1123 * 1 - Flush both dynamic and static entries. 1124 * Access: RW 1125 */ 1126 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1127 1128 static inline void mlxsw_reg_sfdf_pack(char *payload, 1129 enum mlxsw_reg_sfdf_flush_type type) 1130 { 1131 MLXSW_REG_ZERO(sfdf, payload); 1132 mlxsw_reg_sfdf_flush_type_set(payload, type); 1133 mlxsw_reg_sfdf_flush_static_set(payload, true); 1134 } 1135 1136 /* reg_sfdf_fid 1137 * FID to flush. 1138 * Access: RW 1139 */ 1140 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1141 1142 /* reg_sfdf_system_port 1143 * Port to flush. 1144 * Access: RW 1145 */ 1146 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1147 1148 /* reg_sfdf_port_fid_system_port 1149 * Port to flush, pointed to by FID. 1150 * Access: RW 1151 */ 1152 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1153 1154 /* reg_sfdf_lag_id 1155 * LAG ID to flush. 1156 * Access: RW 1157 */ 1158 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1159 1160 /* reg_sfdf_lag_fid_lag_id 1161 * LAG ID to flush, pointed to by FID. 1162 * Access: RW 1163 */ 1164 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1165 1166 /* SLDR - Switch LAG Descriptor Register 1167 * ----------------------------------------- 1168 * The switch LAG descriptor register is populated by LAG descriptors. 1169 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1170 * max_lag-1. 1171 */ 1172 #define MLXSW_REG_SLDR_ID 0x2014 1173 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1174 1175 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1176 1177 enum mlxsw_reg_sldr_op { 1178 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1179 MLXSW_REG_SLDR_OP_LAG_CREATE, 1180 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1181 /* Ports that appear in the list have the Distributor enabled */ 1182 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1183 /* Removes ports from the disributor list */ 1184 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1185 }; 1186 1187 /* reg_sldr_op 1188 * Operation. 1189 * Access: RW 1190 */ 1191 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1192 1193 /* reg_sldr_lag_id 1194 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1195 * Access: Index 1196 */ 1197 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1198 1199 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1200 { 1201 MLXSW_REG_ZERO(sldr, payload); 1202 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1203 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1204 } 1205 1206 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1207 { 1208 MLXSW_REG_ZERO(sldr, payload); 1209 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1210 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1211 } 1212 1213 /* reg_sldr_num_ports 1214 * The number of member ports of the LAG. 1215 * Reserved for Create / Destroy operations 1216 * For Add / Remove operations - indicates the number of ports in the list. 1217 * Access: RW 1218 */ 1219 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1220 1221 /* reg_sldr_system_port 1222 * System port. 1223 * Access: RW 1224 */ 1225 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1226 1227 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1228 u8 local_port) 1229 { 1230 MLXSW_REG_ZERO(sldr, payload); 1231 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1232 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1233 mlxsw_reg_sldr_num_ports_set(payload, 1); 1234 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1235 } 1236 1237 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1238 u8 local_port) 1239 { 1240 MLXSW_REG_ZERO(sldr, payload); 1241 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1242 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1243 mlxsw_reg_sldr_num_ports_set(payload, 1); 1244 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1245 } 1246 1247 /* SLCR - Switch LAG Configuration 2 Register 1248 * ------------------------------------------- 1249 * The Switch LAG Configuration register is used for configuring the 1250 * LAG properties of the switch. 1251 */ 1252 #define MLXSW_REG_SLCR_ID 0x2015 1253 #define MLXSW_REG_SLCR_LEN 0x10 1254 1255 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1256 1257 enum mlxsw_reg_slcr_pp { 1258 /* Global Configuration (for all ports) */ 1259 MLXSW_REG_SLCR_PP_GLOBAL, 1260 /* Per port configuration, based on local_port field */ 1261 MLXSW_REG_SLCR_PP_PER_PORT, 1262 }; 1263 1264 /* reg_slcr_pp 1265 * Per Port Configuration 1266 * Note: Reading at Global mode results in reading port 1 configuration. 1267 * Access: Index 1268 */ 1269 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1270 1271 /* reg_slcr_local_port 1272 * Local port number 1273 * Supported from CPU port 1274 * Not supported from router port 1275 * Reserved when pp = Global Configuration 1276 * Access: Index 1277 */ 1278 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1279 1280 enum mlxsw_reg_slcr_type { 1281 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1282 MLXSW_REG_SLCR_TYPE_XOR, 1283 MLXSW_REG_SLCR_TYPE_RANDOM, 1284 }; 1285 1286 /* reg_slcr_type 1287 * Hash type 1288 * Access: RW 1289 */ 1290 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1291 1292 /* Ingress port */ 1293 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1294 /* SMAC - for IPv4 and IPv6 packets */ 1295 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1296 /* SMAC - for non-IP packets */ 1297 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1298 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1299 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1300 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1301 /* DMAC - for IPv4 and IPv6 packets */ 1302 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1303 /* DMAC - for non-IP packets */ 1304 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1305 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1306 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1307 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1308 /* Ethertype - for IPv4 and IPv6 packets */ 1309 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1310 /* Ethertype - for non-IP packets */ 1311 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1312 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1313 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1314 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1315 /* VLAN ID - for IPv4 and IPv6 packets */ 1316 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1317 /* VLAN ID - for non-IP packets */ 1318 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1319 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1320 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1321 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1322 /* Source IP address (can be IPv4 or IPv6) */ 1323 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1324 /* Destination IP address (can be IPv4 or IPv6) */ 1325 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1326 /* TCP/UDP source port */ 1327 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1328 /* TCP/UDP destination port*/ 1329 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1330 /* IPv4 Protocol/IPv6 Next Header */ 1331 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1332 /* IPv6 Flow label */ 1333 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1334 /* SID - FCoE source ID */ 1335 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1336 /* DID - FCoE destination ID */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1338 /* OXID - FCoE originator exchange ID */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1340 /* Destination QP number - for RoCE packets */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1342 1343 /* reg_slcr_lag_hash 1344 * LAG hashing configuration. This is a bitmask, in which each set 1345 * bit includes the corresponding item in the LAG hash calculation. 1346 * The default lag_hash contains SMAC, DMAC, VLANID and 1347 * Ethertype (for all packet types). 1348 * Access: RW 1349 */ 1350 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1351 1352 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1353 { 1354 MLXSW_REG_ZERO(slcr, payload); 1355 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1356 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1357 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1358 } 1359 1360 /* SLCOR - Switch LAG Collector Register 1361 * ------------------------------------- 1362 * The Switch LAG Collector register controls the Local Port membership 1363 * in a LAG and enablement of the collector. 1364 */ 1365 #define MLXSW_REG_SLCOR_ID 0x2016 1366 #define MLXSW_REG_SLCOR_LEN 0x10 1367 1368 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1369 1370 enum mlxsw_reg_slcor_col { 1371 /* Port is added with collector disabled */ 1372 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1373 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1374 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1375 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1376 }; 1377 1378 /* reg_slcor_col 1379 * Collector configuration 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1383 1384 /* reg_slcor_local_port 1385 * Local port number 1386 * Not supported for CPU port 1387 * Access: Index 1388 */ 1389 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1390 1391 /* reg_slcor_lag_id 1392 * LAG Identifier. Index into the LAG descriptor table. 1393 * Access: Index 1394 */ 1395 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1396 1397 /* reg_slcor_port_index 1398 * Port index in the LAG list. Only valid on Add Port to LAG col. 1399 * Valid range is from 0 to cap_max_lag_members-1 1400 * Access: RW 1401 */ 1402 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1403 1404 static inline void mlxsw_reg_slcor_pack(char *payload, 1405 u8 local_port, u16 lag_id, 1406 enum mlxsw_reg_slcor_col col) 1407 { 1408 MLXSW_REG_ZERO(slcor, payload); 1409 mlxsw_reg_slcor_col_set(payload, col); 1410 mlxsw_reg_slcor_local_port_set(payload, local_port); 1411 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1412 } 1413 1414 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1415 u8 local_port, u16 lag_id, 1416 u8 port_index) 1417 { 1418 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1419 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1420 mlxsw_reg_slcor_port_index_set(payload, port_index); 1421 } 1422 1423 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1424 u8 local_port, u16 lag_id) 1425 { 1426 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1427 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1428 } 1429 1430 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1431 u8 local_port, u16 lag_id) 1432 { 1433 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1435 } 1436 1437 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1438 u8 local_port, u16 lag_id) 1439 { 1440 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1441 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1442 } 1443 1444 /* SPMLR - Switch Port MAC Learning Register 1445 * ----------------------------------------- 1446 * Controls the Switch MAC learning policy per port. 1447 */ 1448 #define MLXSW_REG_SPMLR_ID 0x2018 1449 #define MLXSW_REG_SPMLR_LEN 0x8 1450 1451 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1452 1453 /* reg_spmlr_local_port 1454 * Local port number. 1455 * Access: Index 1456 */ 1457 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1458 1459 /* reg_spmlr_sub_port 1460 * Virtual port within the physical port. 1461 * Should be set to 0 when virtual ports are not enabled on the port. 1462 * Access: Index 1463 */ 1464 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1465 1466 enum mlxsw_reg_spmlr_learn_mode { 1467 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1468 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1469 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1470 }; 1471 1472 /* reg_spmlr_learn_mode 1473 * Learning mode on the port. 1474 * 0 - Learning disabled. 1475 * 2 - Learning enabled. 1476 * 3 - Security mode. 1477 * 1478 * In security mode the switch does not learn MACs on the port, but uses the 1479 * SMAC to see if it exists on another ingress port. If so, the packet is 1480 * classified as a bad packet and is discarded unless the software registers 1481 * to receive port security error packets usign HPKT. 1482 */ 1483 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1484 1485 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1486 enum mlxsw_reg_spmlr_learn_mode mode) 1487 { 1488 MLXSW_REG_ZERO(spmlr, payload); 1489 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1490 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1491 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1492 } 1493 1494 /* SVFA - Switch VID to FID Allocation Register 1495 * -------------------------------------------- 1496 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1497 * virtualized ports. 1498 */ 1499 #define MLXSW_REG_SVFA_ID 0x201C 1500 #define MLXSW_REG_SVFA_LEN 0x10 1501 1502 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1503 1504 /* reg_svfa_swid 1505 * Switch partition ID. 1506 * Access: Index 1507 */ 1508 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1509 1510 /* reg_svfa_local_port 1511 * Local port number. 1512 * Access: Index 1513 * 1514 * Note: Reserved for 802.1Q FIDs. 1515 */ 1516 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1517 1518 enum mlxsw_reg_svfa_mt { 1519 MLXSW_REG_SVFA_MT_VID_TO_FID, 1520 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1521 }; 1522 1523 /* reg_svfa_mapping_table 1524 * Mapping table: 1525 * 0 - VID to FID 1526 * 1 - {Port, VID} to FID 1527 * Access: Index 1528 * 1529 * Note: Reserved for SwitchX-2. 1530 */ 1531 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1532 1533 /* reg_svfa_v 1534 * Valid. 1535 * Valid if set. 1536 * Access: RW 1537 * 1538 * Note: Reserved for SwitchX-2. 1539 */ 1540 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1541 1542 /* reg_svfa_fid 1543 * Filtering ID. 1544 * Access: RW 1545 */ 1546 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1547 1548 /* reg_svfa_vid 1549 * VLAN ID. 1550 * Access: Index 1551 */ 1552 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1553 1554 /* reg_svfa_counter_set_type 1555 * Counter set type for flow counters. 1556 * Access: RW 1557 * 1558 * Note: Reserved for SwitchX-2. 1559 */ 1560 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1561 1562 /* reg_svfa_counter_index 1563 * Counter index for flow counters. 1564 * Access: RW 1565 * 1566 * Note: Reserved for SwitchX-2. 1567 */ 1568 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1569 1570 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1571 enum mlxsw_reg_svfa_mt mt, bool valid, 1572 u16 fid, u16 vid) 1573 { 1574 MLXSW_REG_ZERO(svfa, payload); 1575 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1576 mlxsw_reg_svfa_swid_set(payload, 0); 1577 mlxsw_reg_svfa_local_port_set(payload, local_port); 1578 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1579 mlxsw_reg_svfa_v_set(payload, valid); 1580 mlxsw_reg_svfa_fid_set(payload, fid); 1581 mlxsw_reg_svfa_vid_set(payload, vid); 1582 } 1583 1584 /* SVPE - Switch Virtual-Port Enabling Register 1585 * -------------------------------------------- 1586 * Enables port virtualization. 1587 */ 1588 #define MLXSW_REG_SVPE_ID 0x201E 1589 #define MLXSW_REG_SVPE_LEN 0x4 1590 1591 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1592 1593 /* reg_svpe_local_port 1594 * Local port number 1595 * Access: Index 1596 * 1597 * Note: CPU port is not supported (uses VLAN mode only). 1598 */ 1599 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1600 1601 /* reg_svpe_vp_en 1602 * Virtual port enable. 1603 * 0 - Disable, VLAN mode (VID to FID). 1604 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1608 1609 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1610 bool enable) 1611 { 1612 MLXSW_REG_ZERO(svpe, payload); 1613 mlxsw_reg_svpe_local_port_set(payload, local_port); 1614 mlxsw_reg_svpe_vp_en_set(payload, enable); 1615 } 1616 1617 /* SFMR - Switch FID Management Register 1618 * ------------------------------------- 1619 * Creates and configures FIDs. 1620 */ 1621 #define MLXSW_REG_SFMR_ID 0x201F 1622 #define MLXSW_REG_SFMR_LEN 0x18 1623 1624 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1625 1626 enum mlxsw_reg_sfmr_op { 1627 MLXSW_REG_SFMR_OP_CREATE_FID, 1628 MLXSW_REG_SFMR_OP_DESTROY_FID, 1629 }; 1630 1631 /* reg_sfmr_op 1632 * Operation. 1633 * 0 - Create or edit FID. 1634 * 1 - Destroy FID. 1635 * Access: WO 1636 */ 1637 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1638 1639 /* reg_sfmr_fid 1640 * Filtering ID. 1641 * Access: Index 1642 */ 1643 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1644 1645 /* reg_sfmr_fid_offset 1646 * FID offset. 1647 * Used to point into the flooding table selected by SFGC register if 1648 * the table is of type FID-Offset. Otherwise, this field is reserved. 1649 * Access: RW 1650 */ 1651 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1652 1653 /* reg_sfmr_vtfp 1654 * Valid Tunnel Flood Pointer. 1655 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1656 * Access: RW 1657 * 1658 * Note: Reserved for 802.1Q FIDs. 1659 */ 1660 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1661 1662 /* reg_sfmr_nve_tunnel_flood_ptr 1663 * Underlay Flooding and BC Pointer. 1664 * Used as a pointer to the first entry of the group based link lists of 1665 * flooding or BC entries (for NVE tunnels). 1666 * Access: RW 1667 */ 1668 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1669 1670 /* reg_sfmr_vv 1671 * VNI Valid. 1672 * If not set, then vni is reserved. 1673 * Access: RW 1674 * 1675 * Note: Reserved for 802.1Q FIDs. 1676 */ 1677 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1678 1679 /* reg_sfmr_vni 1680 * Virtual Network Identifier. 1681 * Access: RW 1682 * 1683 * Note: A given VNI can only be assigned to one FID. 1684 */ 1685 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1686 1687 static inline void mlxsw_reg_sfmr_pack(char *payload, 1688 enum mlxsw_reg_sfmr_op op, u16 fid, 1689 u16 fid_offset) 1690 { 1691 MLXSW_REG_ZERO(sfmr, payload); 1692 mlxsw_reg_sfmr_op_set(payload, op); 1693 mlxsw_reg_sfmr_fid_set(payload, fid); 1694 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1695 mlxsw_reg_sfmr_vtfp_set(payload, false); 1696 mlxsw_reg_sfmr_vv_set(payload, false); 1697 } 1698 1699 /* SPVMLR - Switch Port VLAN MAC Learning Register 1700 * ----------------------------------------------- 1701 * Controls the switch MAC learning policy per {Port, VID}. 1702 */ 1703 #define MLXSW_REG_SPVMLR_ID 0x2020 1704 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1705 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1706 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1707 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1708 MLXSW_REG_SPVMLR_REC_LEN * \ 1709 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1710 1711 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1712 1713 /* reg_spvmlr_local_port 1714 * Local ingress port. 1715 * Access: Index 1716 * 1717 * Note: CPU port is not supported. 1718 */ 1719 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1720 1721 /* reg_spvmlr_num_rec 1722 * Number of records to update. 1723 * Access: OP 1724 */ 1725 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1726 1727 /* reg_spvmlr_rec_learn_enable 1728 * 0 - Disable learning for {Port, VID}. 1729 * 1 - Enable learning for {Port, VID}. 1730 * Access: RW 1731 */ 1732 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1733 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1734 1735 /* reg_spvmlr_rec_vid 1736 * VLAN ID to be added/removed from port or for querying. 1737 * Access: Index 1738 */ 1739 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1740 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1741 1742 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1743 u16 vid_begin, u16 vid_end, 1744 bool learn_enable) 1745 { 1746 int num_rec = vid_end - vid_begin + 1; 1747 int i; 1748 1749 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1750 1751 MLXSW_REG_ZERO(spvmlr, payload); 1752 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1753 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1754 1755 for (i = 0; i < num_rec; i++) { 1756 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1757 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1758 } 1759 } 1760 1761 /* CWTP - Congetion WRED ECN TClass Profile 1762 * ---------------------------------------- 1763 * Configures the profiles for queues of egress port and traffic class 1764 */ 1765 #define MLXSW_REG_CWTP_ID 0x2802 1766 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1767 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1768 #define MLXSW_REG_CWTP_LEN 0x40 1769 1770 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1771 1772 /* reg_cwtp_local_port 1773 * Local port number 1774 * Not supported for CPU port 1775 * Access: Index 1776 */ 1777 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1778 1779 /* reg_cwtp_traffic_class 1780 * Traffic Class to configure 1781 * Access: Index 1782 */ 1783 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1784 1785 /* reg_cwtp_profile_min 1786 * Minimum Average Queue Size of the profile in cells. 1787 * Access: RW 1788 */ 1789 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1790 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1791 1792 /* reg_cwtp_profile_percent 1793 * Percentage of WRED and ECN marking for maximum Average Queue size 1794 * Range is 0 to 100, units of integer percentage 1795 * Access: RW 1796 */ 1797 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1798 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1799 1800 /* reg_cwtp_profile_max 1801 * Maximum Average Queue size of the profile in cells 1802 * Access: RW 1803 */ 1804 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1805 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1806 1807 #define MLXSW_REG_CWTP_MIN_VALUE 64 1808 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1809 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1810 1811 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1812 u8 traffic_class) 1813 { 1814 int i; 1815 1816 MLXSW_REG_ZERO(cwtp, payload); 1817 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1818 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1819 1820 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1821 mlxsw_reg_cwtp_profile_min_set(payload, i, 1822 MLXSW_REG_CWTP_MIN_VALUE); 1823 mlxsw_reg_cwtp_profile_max_set(payload, i, 1824 MLXSW_REG_CWTP_MIN_VALUE); 1825 } 1826 } 1827 1828 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1829 1830 static inline void 1831 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1832 u32 probability) 1833 { 1834 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1835 1836 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1837 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1838 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1839 } 1840 1841 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1842 * --------------------------------------------------- 1843 * The CWTPM register maps each egress port and traffic class to profile num. 1844 */ 1845 #define MLXSW_REG_CWTPM_ID 0x2803 1846 #define MLXSW_REG_CWTPM_LEN 0x44 1847 1848 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1849 1850 /* reg_cwtpm_local_port 1851 * Local port number 1852 * Not supported for CPU port 1853 * Access: Index 1854 */ 1855 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1856 1857 /* reg_cwtpm_traffic_class 1858 * Traffic Class to configure 1859 * Access: Index 1860 */ 1861 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1862 1863 /* reg_cwtpm_ew 1864 * Control enablement of WRED for traffic class: 1865 * 0 - Disable 1866 * 1 - Enable 1867 * Access: RW 1868 */ 1869 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1870 1871 /* reg_cwtpm_ee 1872 * Control enablement of ECN for traffic class: 1873 * 0 - Disable 1874 * 1 - Enable 1875 * Access: RW 1876 */ 1877 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1878 1879 /* reg_cwtpm_tcp_g 1880 * TCP Green Profile. 1881 * Index of the profile within {port, traffic class} to use. 1882 * 0 for disabling both WRED and ECN for this type of traffic. 1883 * Access: RW 1884 */ 1885 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1886 1887 /* reg_cwtpm_tcp_y 1888 * TCP Yellow Profile. 1889 * Index of the profile within {port, traffic class} to use. 1890 * 0 for disabling both WRED and ECN for this type of traffic. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1894 1895 /* reg_cwtpm_tcp_r 1896 * TCP Red Profile. 1897 * Index of the profile within {port, traffic class} to use. 1898 * 0 for disabling both WRED and ECN for this type of traffic. 1899 * Access: RW 1900 */ 1901 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 1902 1903 /* reg_cwtpm_ntcp_g 1904 * Non-TCP Green Profile. 1905 * Index of the profile within {port, traffic class} to use. 1906 * 0 for disabling both WRED and ECN for this type of traffic. 1907 * Access: RW 1908 */ 1909 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 1910 1911 /* reg_cwtpm_ntcp_y 1912 * Non-TCP Yellow Profile. 1913 * Index of the profile within {port, traffic class} to use. 1914 * 0 for disabling both WRED and ECN for this type of traffic. 1915 * Access: RW 1916 */ 1917 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 1918 1919 /* reg_cwtpm_ntcp_r 1920 * Non-TCP Red Profile. 1921 * Index of the profile within {port, traffic class} to use. 1922 * 0 for disabling both WRED and ECN for this type of traffic. 1923 * Access: RW 1924 */ 1925 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 1926 1927 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 1928 1929 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 1930 u8 traffic_class, u8 profile, 1931 bool wred, bool ecn) 1932 { 1933 MLXSW_REG_ZERO(cwtpm, payload); 1934 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 1935 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 1936 mlxsw_reg_cwtpm_ew_set(payload, wred); 1937 mlxsw_reg_cwtpm_ee_set(payload, ecn); 1938 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 1939 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 1940 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 1941 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 1942 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 1943 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 1944 } 1945 1946 /* PPBT - Policy-Engine Port Binding Table 1947 * --------------------------------------- 1948 * This register is used for configuration of the Port Binding Table. 1949 */ 1950 #define MLXSW_REG_PPBT_ID 0x3002 1951 #define MLXSW_REG_PPBT_LEN 0x14 1952 1953 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 1954 1955 enum mlxsw_reg_pxbt_e { 1956 MLXSW_REG_PXBT_E_IACL, 1957 MLXSW_REG_PXBT_E_EACL, 1958 }; 1959 1960 /* reg_ppbt_e 1961 * Access: Index 1962 */ 1963 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 1964 1965 enum mlxsw_reg_pxbt_op { 1966 MLXSW_REG_PXBT_OP_BIND, 1967 MLXSW_REG_PXBT_OP_UNBIND, 1968 }; 1969 1970 /* reg_ppbt_op 1971 * Access: RW 1972 */ 1973 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 1974 1975 /* reg_ppbt_local_port 1976 * Local port. Not including CPU port. 1977 * Access: Index 1978 */ 1979 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 1980 1981 /* reg_ppbt_g 1982 * group - When set, the binding is of an ACL group. When cleared, 1983 * the binding is of an ACL. 1984 * Must be set to 1 for Spectrum. 1985 * Access: RW 1986 */ 1987 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 1988 1989 /* reg_ppbt_acl_info 1990 * ACL/ACL group identifier. If the g bit is set, this field should hold 1991 * the acl_group_id, else it should hold the acl_id. 1992 * Access: RW 1993 */ 1994 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 1995 1996 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 1997 enum mlxsw_reg_pxbt_op op, 1998 u8 local_port, u16 acl_info) 1999 { 2000 MLXSW_REG_ZERO(ppbt, payload); 2001 mlxsw_reg_ppbt_e_set(payload, e); 2002 mlxsw_reg_ppbt_op_set(payload, op); 2003 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2004 mlxsw_reg_ppbt_g_set(payload, true); 2005 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2006 } 2007 2008 /* PACL - Policy-Engine ACL Register 2009 * --------------------------------- 2010 * This register is used for configuration of the ACL. 2011 */ 2012 #define MLXSW_REG_PACL_ID 0x3004 2013 #define MLXSW_REG_PACL_LEN 0x70 2014 2015 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2016 2017 /* reg_pacl_v 2018 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2019 * while the ACL is bounded to either a port, VLAN or ACL rule. 2020 * Access: RW 2021 */ 2022 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2023 2024 /* reg_pacl_acl_id 2025 * An identifier representing the ACL (managed by software) 2026 * Range 0 .. cap_max_acl_regions - 1 2027 * Access: Index 2028 */ 2029 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2030 2031 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2032 2033 /* reg_pacl_tcam_region_info 2034 * Opaque object that represents a TCAM region. 2035 * Obtained through PTAR register. 2036 * Access: RW 2037 */ 2038 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2039 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2040 2041 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2042 bool valid, const char *tcam_region_info) 2043 { 2044 MLXSW_REG_ZERO(pacl, payload); 2045 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2046 mlxsw_reg_pacl_v_set(payload, valid); 2047 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2048 } 2049 2050 /* PAGT - Policy-Engine ACL Group Table 2051 * ------------------------------------ 2052 * This register is used for configuration of the ACL Group Table. 2053 */ 2054 #define MLXSW_REG_PAGT_ID 0x3005 2055 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2056 #define MLXSW_REG_PAGT_ACL_LEN 4 2057 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2058 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2059 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2060 2061 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2062 2063 /* reg_pagt_size 2064 * Number of ACLs in the group. 2065 * Size 0 invalidates a group. 2066 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2067 * Total number of ACLs in all groups must be lower or equal 2068 * to cap_max_acl_tot_groups 2069 * Note: a group which is binded must not be invalidated 2070 * Access: Index 2071 */ 2072 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2073 2074 /* reg_pagt_acl_group_id 2075 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2076 * the ACL Group identifier (managed by software). 2077 * Access: Index 2078 */ 2079 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2080 2081 /* reg_pagt_acl_id 2082 * ACL identifier 2083 * Access: RW 2084 */ 2085 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2086 2087 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2088 { 2089 MLXSW_REG_ZERO(pagt, payload); 2090 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2091 } 2092 2093 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2094 u16 acl_id) 2095 { 2096 u8 size = mlxsw_reg_pagt_size_get(payload); 2097 2098 if (index >= size) 2099 mlxsw_reg_pagt_size_set(payload, index + 1); 2100 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2101 } 2102 2103 /* PTAR - Policy-Engine TCAM Allocation Register 2104 * --------------------------------------------- 2105 * This register is used for allocation of regions in the TCAM. 2106 * Note: Query method is not supported on this register. 2107 */ 2108 #define MLXSW_REG_PTAR_ID 0x3006 2109 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2110 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2111 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2112 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2113 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2114 2115 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2116 2117 enum mlxsw_reg_ptar_op { 2118 /* allocate a TCAM region */ 2119 MLXSW_REG_PTAR_OP_ALLOC, 2120 /* resize a TCAM region */ 2121 MLXSW_REG_PTAR_OP_RESIZE, 2122 /* deallocate TCAM region */ 2123 MLXSW_REG_PTAR_OP_FREE, 2124 /* test allocation */ 2125 MLXSW_REG_PTAR_OP_TEST, 2126 }; 2127 2128 /* reg_ptar_op 2129 * Access: OP 2130 */ 2131 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2132 2133 /* reg_ptar_action_set_type 2134 * Type of action set to be used on this region. 2135 * For Spectrum, this is always type 2 - "flexible" 2136 * Access: WO 2137 */ 2138 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2139 2140 /* reg_ptar_key_type 2141 * TCAM key type for the region. 2142 * For Spectrum, this is always type 0x50 - "FLEX_KEY" 2143 * Access: WO 2144 */ 2145 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2146 2147 /* reg_ptar_region_size 2148 * TCAM region size. When allocating/resizing this is the requested size, 2149 * the response is the actual size. Note that actual size may be 2150 * larger than requested. 2151 * Allowed range 1 .. cap_max_rules-1 2152 * Reserved during op deallocate. 2153 * Access: WO 2154 */ 2155 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2156 2157 /* reg_ptar_region_id 2158 * Region identifier 2159 * Range 0 .. cap_max_regions-1 2160 * Access: Index 2161 */ 2162 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2163 2164 /* reg_ptar_tcam_region_info 2165 * Opaque object that represents the TCAM region. 2166 * Returned when allocating a region. 2167 * Provided by software for ACL generation and region deallocation and resize. 2168 * Access: RW 2169 */ 2170 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2171 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2172 2173 /* reg_ptar_flexible_key_id 2174 * Identifier of the Flexible Key. 2175 * Only valid if key_type == "FLEX_KEY" 2176 * The key size will be rounded up to one of the following values: 2177 * 9B, 18B, 36B, 54B. 2178 * This field is reserved for in resize operation. 2179 * Access: WO 2180 */ 2181 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2182 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2183 2184 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2185 u16 region_size, u16 region_id, 2186 const char *tcam_region_info) 2187 { 2188 MLXSW_REG_ZERO(ptar, payload); 2189 mlxsw_reg_ptar_op_set(payload, op); 2190 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2191 mlxsw_reg_ptar_key_type_set(payload, 0x50); /* "FLEX_KEY" */ 2192 mlxsw_reg_ptar_region_size_set(payload, region_size); 2193 mlxsw_reg_ptar_region_id_set(payload, region_id); 2194 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2195 } 2196 2197 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2198 u16 key_id) 2199 { 2200 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2201 } 2202 2203 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2204 { 2205 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2206 } 2207 2208 /* PPBS - Policy-Engine Policy Based Switching Register 2209 * ---------------------------------------------------- 2210 * This register retrieves and sets Policy Based Switching Table entries. 2211 */ 2212 #define MLXSW_REG_PPBS_ID 0x300C 2213 #define MLXSW_REG_PPBS_LEN 0x14 2214 2215 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2216 2217 /* reg_ppbs_pbs_ptr 2218 * Index into the PBS table. 2219 * For Spectrum, the index points to the KVD Linear. 2220 * Access: Index 2221 */ 2222 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2223 2224 /* reg_ppbs_system_port 2225 * Unique port identifier for the final destination of the packet. 2226 * Access: RW 2227 */ 2228 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2229 2230 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2231 u16 system_port) 2232 { 2233 MLXSW_REG_ZERO(ppbs, payload); 2234 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2235 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2236 } 2237 2238 /* PRCR - Policy-Engine Rules Copy Register 2239 * ---------------------------------------- 2240 * This register is used for accessing rules within a TCAM region. 2241 */ 2242 #define MLXSW_REG_PRCR_ID 0x300D 2243 #define MLXSW_REG_PRCR_LEN 0x40 2244 2245 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2246 2247 enum mlxsw_reg_prcr_op { 2248 /* Move rules. Moves the rules from "tcam_region_info" starting 2249 * at offset "offset" to "dest_tcam_region_info" 2250 * at offset "dest_offset." 2251 */ 2252 MLXSW_REG_PRCR_OP_MOVE, 2253 /* Copy rules. Copies the rules from "tcam_region_info" starting 2254 * at offset "offset" to "dest_tcam_region_info" 2255 * at offset "dest_offset." 2256 */ 2257 MLXSW_REG_PRCR_OP_COPY, 2258 }; 2259 2260 /* reg_prcr_op 2261 * Access: OP 2262 */ 2263 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2264 2265 /* reg_prcr_offset 2266 * Offset within the source region to copy/move from. 2267 * Access: Index 2268 */ 2269 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2270 2271 /* reg_prcr_size 2272 * The number of rules to copy/move. 2273 * Access: WO 2274 */ 2275 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2276 2277 /* reg_prcr_tcam_region_info 2278 * Opaque object that represents the source TCAM region. 2279 * Access: Index 2280 */ 2281 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2282 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2283 2284 /* reg_prcr_dest_offset 2285 * Offset within the source region to copy/move to. 2286 * Access: Index 2287 */ 2288 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2289 2290 /* reg_prcr_dest_tcam_region_info 2291 * Opaque object that represents the destination TCAM region. 2292 * Access: Index 2293 */ 2294 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2295 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2296 2297 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2298 const char *src_tcam_region_info, 2299 u16 src_offset, 2300 const char *dest_tcam_region_info, 2301 u16 dest_offset, u16 size) 2302 { 2303 MLXSW_REG_ZERO(prcr, payload); 2304 mlxsw_reg_prcr_op_set(payload, op); 2305 mlxsw_reg_prcr_offset_set(payload, src_offset); 2306 mlxsw_reg_prcr_size_set(payload, size); 2307 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2308 src_tcam_region_info); 2309 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2310 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2311 dest_tcam_region_info); 2312 } 2313 2314 /* PEFA - Policy-Engine Extended Flexible Action Register 2315 * ------------------------------------------------------ 2316 * This register is used for accessing an extended flexible action entry 2317 * in the central KVD Linear Database. 2318 */ 2319 #define MLXSW_REG_PEFA_ID 0x300F 2320 #define MLXSW_REG_PEFA_LEN 0xB0 2321 2322 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2323 2324 /* reg_pefa_index 2325 * Index in the KVD Linear Centralized Database. 2326 * Access: Index 2327 */ 2328 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2329 2330 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2331 2332 /* reg_pefa_flex_action_set 2333 * Action-set to perform when rule is matched. 2334 * Must be zero padded if action set is shorter. 2335 * Access: RW 2336 */ 2337 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2338 2339 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, 2340 const char *flex_action_set) 2341 { 2342 MLXSW_REG_ZERO(pefa, payload); 2343 mlxsw_reg_pefa_index_set(payload, index); 2344 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, flex_action_set); 2345 } 2346 2347 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2348 * ----------------------------------------------------- 2349 * This register is used for accessing rules within a TCAM region. 2350 * It is a new version of PTCE in order to support wider key, 2351 * mask and action within a TCAM region. This register is not supported 2352 * by SwitchX and SwitchX-2. 2353 */ 2354 #define MLXSW_REG_PTCE2_ID 0x3017 2355 #define MLXSW_REG_PTCE2_LEN 0x1D8 2356 2357 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2358 2359 /* reg_ptce2_v 2360 * Valid. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2364 2365 /* reg_ptce2_a 2366 * Activity. Set if a packet lookup has hit on the specific entry. 2367 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2368 * Access: RO 2369 */ 2370 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2371 2372 enum mlxsw_reg_ptce2_op { 2373 /* Read operation. */ 2374 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2375 /* clear on read operation. Used to read entry 2376 * and clear Activity bit. 2377 */ 2378 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2379 /* Write operation. Used to write a new entry to the table. 2380 * All R/W fields are relevant for new entry. Activity bit is set 2381 * for new entries - Note write with v = 0 will delete the entry. 2382 */ 2383 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2384 /* Update action. Only action set will be updated. */ 2385 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2386 /* Clear activity. A bit is cleared for the entry. */ 2387 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2388 }; 2389 2390 /* reg_ptce2_op 2391 * Access: OP 2392 */ 2393 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2394 2395 /* reg_ptce2_offset 2396 * Access: Index 2397 */ 2398 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2399 2400 /* reg_ptce2_tcam_region_info 2401 * Opaque object that represents the TCAM region. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2405 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2406 2407 #define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96 2408 2409 /* reg_ptce2_flex_key_blocks 2410 * ACL Key. 2411 * Access: RW 2412 */ 2413 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2414 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2415 2416 /* reg_ptce2_mask 2417 * mask- in the same size as key. A bit that is set directs the TCAM 2418 * to compare the corresponding bit in key. A bit that is clear directs 2419 * the TCAM to ignore the corresponding bit in key. 2420 * Access: RW 2421 */ 2422 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2423 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2424 2425 /* reg_ptce2_flex_action_set 2426 * ACL action set. 2427 * Access: RW 2428 */ 2429 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2430 MLXSW_REG_FLEX_ACTION_SET_LEN); 2431 2432 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2433 enum mlxsw_reg_ptce2_op op, 2434 const char *tcam_region_info, 2435 u16 offset) 2436 { 2437 MLXSW_REG_ZERO(ptce2, payload); 2438 mlxsw_reg_ptce2_v_set(payload, valid); 2439 mlxsw_reg_ptce2_op_set(payload, op); 2440 mlxsw_reg_ptce2_offset_set(payload, offset); 2441 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2442 } 2443 2444 /* QPCR - QoS Policer Configuration Register 2445 * ----------------------------------------- 2446 * The QPCR register is used to create policers - that limit 2447 * the rate of bytes or packets via some trap group. 2448 */ 2449 #define MLXSW_REG_QPCR_ID 0x4004 2450 #define MLXSW_REG_QPCR_LEN 0x28 2451 2452 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 2453 2454 enum mlxsw_reg_qpcr_g { 2455 MLXSW_REG_QPCR_G_GLOBAL = 2, 2456 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 2457 }; 2458 2459 /* reg_qpcr_g 2460 * The policer type. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 2464 2465 /* reg_qpcr_pid 2466 * Policer ID. 2467 * Access: Index 2468 */ 2469 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 2470 2471 /* reg_qpcr_color_aware 2472 * Is the policer aware of colors. 2473 * Must be 0 (unaware) for cpu port. 2474 * Access: RW for unbounded policer. RO for bounded policer. 2475 */ 2476 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 2477 2478 /* reg_qpcr_bytes 2479 * Is policer limit is for bytes per sec or packets per sec. 2480 * 0 - packets 2481 * 1 - bytes 2482 * Access: RW for unbounded policer. RO for bounded policer. 2483 */ 2484 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 2485 2486 enum mlxsw_reg_qpcr_ir_units { 2487 MLXSW_REG_QPCR_IR_UNITS_M, 2488 MLXSW_REG_QPCR_IR_UNITS_K, 2489 }; 2490 2491 /* reg_qpcr_ir_units 2492 * Policer's units for cir and eir fields (for bytes limits only) 2493 * 1 - 10^3 2494 * 0 - 10^6 2495 * Access: OP 2496 */ 2497 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 2498 2499 enum mlxsw_reg_qpcr_rate_type { 2500 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 2501 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 2502 }; 2503 2504 /* reg_qpcr_rate_type 2505 * Policer can have one limit (single rate) or 2 limits with specific operation 2506 * for packets that exceed the lower rate but not the upper one. 2507 * (For cpu port must be single rate) 2508 * Access: RW for unbounded policer. RO for bounded policer. 2509 */ 2510 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 2511 2512 /* reg_qpc_cbs 2513 * Policer's committed burst size. 2514 * The policer is working with time slices of 50 nano sec. By default every 2515 * slice is granted the proportionate share of the committed rate. If we want to 2516 * allow a slice to exceed that share (while still keeping the rate per sec) we 2517 * can allow burst. The burst size is between the default proportionate share 2518 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 2519 * committed rate will result in exceeding the rate). The burst size must be a 2520 * log of 2 and will be determined by 2^cbs. 2521 * Access: RW 2522 */ 2523 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 2524 2525 /* reg_qpcr_cir 2526 * Policer's committed rate. 2527 * The rate used for sungle rate, the lower rate for double rate. 2528 * For bytes limits, the rate will be this value * the unit from ir_units. 2529 * (Resolution error is up to 1%). 2530 * Access: RW 2531 */ 2532 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 2533 2534 /* reg_qpcr_eir 2535 * Policer's exceed rate. 2536 * The higher rate for double rate, reserved for single rate. 2537 * Lower rate for double rate policer. 2538 * For bytes limits, the rate will be this value * the unit from ir_units. 2539 * (Resolution error is up to 1%). 2540 * Access: RW 2541 */ 2542 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 2543 2544 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 2545 2546 /* reg_qpcr_exceed_action. 2547 * What to do with packets between the 2 limits for double rate. 2548 * Access: RW for unbounded policer. RO for bounded policer. 2549 */ 2550 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 2551 2552 enum mlxsw_reg_qpcr_action { 2553 /* Discard */ 2554 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 2555 /* Forward and set color to red. 2556 * If the packet is intended to cpu port, it will be dropped. 2557 */ 2558 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 2559 }; 2560 2561 /* reg_qpcr_violate_action 2562 * What to do with packets that cross the cir limit (for single rate) or the eir 2563 * limit (for double rate). 2564 * Access: RW for unbounded policer. RO for bounded policer. 2565 */ 2566 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 2567 2568 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 2569 enum mlxsw_reg_qpcr_ir_units ir_units, 2570 bool bytes, u32 cir, u16 cbs) 2571 { 2572 MLXSW_REG_ZERO(qpcr, payload); 2573 mlxsw_reg_qpcr_pid_set(payload, pid); 2574 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 2575 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 2576 mlxsw_reg_qpcr_violate_action_set(payload, 2577 MLXSW_REG_QPCR_ACTION_DISCARD); 2578 mlxsw_reg_qpcr_cir_set(payload, cir); 2579 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 2580 mlxsw_reg_qpcr_bytes_set(payload, bytes); 2581 mlxsw_reg_qpcr_cbs_set(payload, cbs); 2582 } 2583 2584 /* QTCT - QoS Switch Traffic Class Table 2585 * ------------------------------------- 2586 * Configures the mapping between the packet switch priority and the 2587 * traffic class on the transmit port. 2588 */ 2589 #define MLXSW_REG_QTCT_ID 0x400A 2590 #define MLXSW_REG_QTCT_LEN 0x08 2591 2592 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 2593 2594 /* reg_qtct_local_port 2595 * Local port number. 2596 * Access: Index 2597 * 2598 * Note: CPU port is not supported. 2599 */ 2600 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 2601 2602 /* reg_qtct_sub_port 2603 * Virtual port within the physical port. 2604 * Should be set to 0 when virtual ports are not enabled on the port. 2605 * Access: Index 2606 */ 2607 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 2608 2609 /* reg_qtct_switch_prio 2610 * Switch priority. 2611 * Access: Index 2612 */ 2613 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 2614 2615 /* reg_qtct_tclass 2616 * Traffic class. 2617 * Default values: 2618 * switch_prio 0 : tclass 1 2619 * switch_prio 1 : tclass 0 2620 * switch_prio i : tclass i, for i > 1 2621 * Access: RW 2622 */ 2623 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 2624 2625 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 2626 u8 switch_prio, u8 tclass) 2627 { 2628 MLXSW_REG_ZERO(qtct, payload); 2629 mlxsw_reg_qtct_local_port_set(payload, local_port); 2630 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 2631 mlxsw_reg_qtct_tclass_set(payload, tclass); 2632 } 2633 2634 /* QEEC - QoS ETS Element Configuration Register 2635 * --------------------------------------------- 2636 * Configures the ETS elements. 2637 */ 2638 #define MLXSW_REG_QEEC_ID 0x400D 2639 #define MLXSW_REG_QEEC_LEN 0x1C 2640 2641 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 2642 2643 /* reg_qeec_local_port 2644 * Local port number. 2645 * Access: Index 2646 * 2647 * Note: CPU port is supported. 2648 */ 2649 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 2650 2651 enum mlxsw_reg_qeec_hr { 2652 MLXSW_REG_QEEC_HIERARCY_PORT, 2653 MLXSW_REG_QEEC_HIERARCY_GROUP, 2654 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2655 MLXSW_REG_QEEC_HIERARCY_TC, 2656 }; 2657 2658 /* reg_qeec_element_hierarchy 2659 * 0 - Port 2660 * 1 - Group 2661 * 2 - Subgroup 2662 * 3 - Traffic Class 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 2666 2667 /* reg_qeec_element_index 2668 * The index of the element in the hierarchy. 2669 * Access: Index 2670 */ 2671 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 2672 2673 /* reg_qeec_next_element_index 2674 * The index of the next (lower) element in the hierarchy. 2675 * Access: RW 2676 * 2677 * Note: Reserved for element_hierarchy 0. 2678 */ 2679 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 2680 2681 enum { 2682 MLXSW_REG_QEEC_BYTES_MODE, 2683 MLXSW_REG_QEEC_PACKETS_MODE, 2684 }; 2685 2686 /* reg_qeec_pb 2687 * Packets or bytes mode. 2688 * 0 - Bytes mode 2689 * 1 - Packets mode 2690 * Access: RW 2691 * 2692 * Note: Used for max shaper configuration. For Spectrum, packets mode 2693 * is supported only for traffic classes of CPU port. 2694 */ 2695 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 2696 2697 /* reg_qeec_mase 2698 * Max shaper configuration enable. Enables configuration of the max 2699 * shaper on this ETS element. 2700 * 0 - Disable 2701 * 1 - Enable 2702 * Access: RW 2703 */ 2704 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 2705 2706 /* A large max rate will disable the max shaper. */ 2707 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 2708 2709 /* reg_qeec_max_shaper_rate 2710 * Max shaper information rate. 2711 * For CPU port, can only be configured for port hierarchy. 2712 * When in bytes mode, value is specified in units of 1000bps. 2713 * Access: RW 2714 */ 2715 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 2716 2717 /* reg_qeec_de 2718 * DWRR configuration enable. Enables configuration of the dwrr and 2719 * dwrr_weight. 2720 * 0 - Disable 2721 * 1 - Enable 2722 * Access: RW 2723 */ 2724 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 2725 2726 /* reg_qeec_dwrr 2727 * Transmission selection algorithm to use on the link going down from 2728 * the ETS element. 2729 * 0 - Strict priority 2730 * 1 - DWRR 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 2734 2735 /* reg_qeec_dwrr_weight 2736 * DWRR weight on the link going down from the ETS element. The 2737 * percentage of bandwidth guaranteed to an ETS element within 2738 * its hierarchy. The sum of all weights across all ETS elements 2739 * within one hierarchy should be equal to 100. Reserved when 2740 * transmission selection algorithm is strict priority. 2741 * Access: RW 2742 */ 2743 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 2744 2745 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 2746 enum mlxsw_reg_qeec_hr hr, u8 index, 2747 u8 next_index) 2748 { 2749 MLXSW_REG_ZERO(qeec, payload); 2750 mlxsw_reg_qeec_local_port_set(payload, local_port); 2751 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 2752 mlxsw_reg_qeec_element_index_set(payload, index); 2753 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 2754 } 2755 2756 /* PMLP - Ports Module to Local Port Register 2757 * ------------------------------------------ 2758 * Configures the assignment of modules to local ports. 2759 */ 2760 #define MLXSW_REG_PMLP_ID 0x5002 2761 #define MLXSW_REG_PMLP_LEN 0x40 2762 2763 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 2764 2765 /* reg_pmlp_rxtx 2766 * 0 - Tx value is used for both Tx and Rx. 2767 * 1 - Rx value is taken from a separte field. 2768 * Access: RW 2769 */ 2770 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 2771 2772 /* reg_pmlp_local_port 2773 * Local port number. 2774 * Access: Index 2775 */ 2776 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 2777 2778 /* reg_pmlp_width 2779 * 0 - Unmap local port. 2780 * 1 - Lane 0 is used. 2781 * 2 - Lanes 0 and 1 are used. 2782 * 4 - Lanes 0, 1, 2 and 3 are used. 2783 * Access: RW 2784 */ 2785 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 2786 2787 /* reg_pmlp_module 2788 * Module number. 2789 * Access: RW 2790 */ 2791 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 2792 2793 /* reg_pmlp_tx_lane 2794 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 2795 * Access: RW 2796 */ 2797 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 2798 2799 /* reg_pmlp_rx_lane 2800 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 2801 * equal to Tx lane. 2802 * Access: RW 2803 */ 2804 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 2805 2806 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 2807 { 2808 MLXSW_REG_ZERO(pmlp, payload); 2809 mlxsw_reg_pmlp_local_port_set(payload, local_port); 2810 } 2811 2812 /* PMTU - Port MTU Register 2813 * ------------------------ 2814 * Configures and reports the port MTU. 2815 */ 2816 #define MLXSW_REG_PMTU_ID 0x5003 2817 #define MLXSW_REG_PMTU_LEN 0x10 2818 2819 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 2820 2821 /* reg_pmtu_local_port 2822 * Local port number. 2823 * Access: Index 2824 */ 2825 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 2826 2827 /* reg_pmtu_max_mtu 2828 * Maximum MTU. 2829 * When port type (e.g. Ethernet) is configured, the relevant MTU is 2830 * reported, otherwise the minimum between the max_mtu of the different 2831 * types is reported. 2832 * Access: RO 2833 */ 2834 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 2835 2836 /* reg_pmtu_admin_mtu 2837 * MTU value to set port to. Must be smaller or equal to max_mtu. 2838 * Note: If port type is Infiniband, then port must be disabled, when its 2839 * MTU is set. 2840 * Access: RW 2841 */ 2842 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 2843 2844 /* reg_pmtu_oper_mtu 2845 * The actual MTU configured on the port. Packets exceeding this size 2846 * will be dropped. 2847 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 2848 * oper_mtu might be smaller than admin_mtu. 2849 * Access: RO 2850 */ 2851 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 2852 2853 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 2854 u16 new_mtu) 2855 { 2856 MLXSW_REG_ZERO(pmtu, payload); 2857 mlxsw_reg_pmtu_local_port_set(payload, local_port); 2858 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 2859 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 2860 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 2861 } 2862 2863 /* PTYS - Port Type and Speed Register 2864 * ----------------------------------- 2865 * Configures and reports the port speed type. 2866 * 2867 * Note: When set while the link is up, the changes will not take effect 2868 * until the port transitions from down to up state. 2869 */ 2870 #define MLXSW_REG_PTYS_ID 0x5004 2871 #define MLXSW_REG_PTYS_LEN 0x40 2872 2873 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 2874 2875 /* reg_ptys_local_port 2876 * Local port number. 2877 * Access: Index 2878 */ 2879 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 2880 2881 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 2882 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 2883 2884 /* reg_ptys_proto_mask 2885 * Protocol mask. Indicates which protocol is used. 2886 * 0 - Infiniband. 2887 * 1 - Fibre Channel. 2888 * 2 - Ethernet. 2889 * Access: Index 2890 */ 2891 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 2892 2893 enum { 2894 MLXSW_REG_PTYS_AN_STATUS_NA, 2895 MLXSW_REG_PTYS_AN_STATUS_OK, 2896 MLXSW_REG_PTYS_AN_STATUS_FAIL, 2897 }; 2898 2899 /* reg_ptys_an_status 2900 * Autonegotiation status. 2901 * Access: RO 2902 */ 2903 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 2904 2905 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 2906 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 2907 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 2908 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 2909 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 2910 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 2911 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 2912 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 2913 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 2914 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 2915 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 2916 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 2917 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 2918 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 2919 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 2920 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 2921 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 2922 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 2923 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 2924 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 2925 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 2926 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 2927 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 2928 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 2929 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 2930 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 2931 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 2932 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 2933 2934 /* reg_ptys_eth_proto_cap 2935 * Ethernet port supported speeds and protocols. 2936 * Access: RO 2937 */ 2938 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 2939 2940 /* reg_ptys_ib_link_width_cap 2941 * IB port supported widths. 2942 * Access: RO 2943 */ 2944 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 2945 2946 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 2947 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 2948 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 2949 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 2950 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 2951 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 2952 2953 /* reg_ptys_ib_proto_cap 2954 * IB port supported speeds and protocols. 2955 * Access: RO 2956 */ 2957 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 2958 2959 /* reg_ptys_eth_proto_admin 2960 * Speed and protocol to set port to. 2961 * Access: RW 2962 */ 2963 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 2964 2965 /* reg_ptys_ib_link_width_admin 2966 * IB width to set port to. 2967 * Access: RW 2968 */ 2969 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 2970 2971 /* reg_ptys_ib_proto_admin 2972 * IB speeds and protocols to set port to. 2973 * Access: RW 2974 */ 2975 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 2976 2977 /* reg_ptys_eth_proto_oper 2978 * The current speed and protocol configured for the port. 2979 * Access: RO 2980 */ 2981 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 2982 2983 /* reg_ptys_ib_link_width_oper 2984 * The current IB width to set port to. 2985 * Access: RO 2986 */ 2987 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 2988 2989 /* reg_ptys_ib_proto_oper 2990 * The current IB speed and protocol. 2991 * Access: RO 2992 */ 2993 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 2994 2995 /* reg_ptys_eth_proto_lp_advertise 2996 * The protocols that were advertised by the link partner during 2997 * autonegotiation. 2998 * Access: RO 2999 */ 3000 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3001 3002 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3003 u32 proto_admin) 3004 { 3005 MLXSW_REG_ZERO(ptys, payload); 3006 mlxsw_reg_ptys_local_port_set(payload, local_port); 3007 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 3008 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 3009 } 3010 3011 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 3012 u32 *p_eth_proto_cap, 3013 u32 *p_eth_proto_adm, 3014 u32 *p_eth_proto_oper) 3015 { 3016 if (p_eth_proto_cap) 3017 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 3018 if (p_eth_proto_adm) 3019 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 3020 if (p_eth_proto_oper) 3021 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 3022 } 3023 3024 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 3025 u16 proto_admin, u16 link_width) 3026 { 3027 MLXSW_REG_ZERO(ptys, payload); 3028 mlxsw_reg_ptys_local_port_set(payload, local_port); 3029 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 3030 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 3031 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 3032 } 3033 3034 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 3035 u16 *p_ib_link_width_cap, 3036 u16 *p_ib_proto_oper, 3037 u16 *p_ib_link_width_oper) 3038 { 3039 if (p_ib_proto_cap) 3040 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 3041 if (p_ib_link_width_cap) 3042 *p_ib_link_width_cap = 3043 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 3044 if (p_ib_proto_oper) 3045 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 3046 if (p_ib_link_width_oper) 3047 *p_ib_link_width_oper = 3048 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 3049 } 3050 3051 /* PPAD - Port Physical Address Register 3052 * ------------------------------------- 3053 * The PPAD register configures the per port physical MAC address. 3054 */ 3055 #define MLXSW_REG_PPAD_ID 0x5005 3056 #define MLXSW_REG_PPAD_LEN 0x10 3057 3058 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 3059 3060 /* reg_ppad_single_base_mac 3061 * 0: base_mac, local port should be 0 and mac[7:0] is 3062 * reserved. HW will set incremental 3063 * 1: single_mac - mac of the local_port 3064 * Access: RW 3065 */ 3066 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 3067 3068 /* reg_ppad_local_port 3069 * port number, if single_base_mac = 0 then local_port is reserved 3070 * Access: RW 3071 */ 3072 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 3073 3074 /* reg_ppad_mac 3075 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 3076 * If single_base_mac = 1 - the per port MAC address 3077 * Access: RW 3078 */ 3079 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 3080 3081 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 3082 u8 local_port) 3083 { 3084 MLXSW_REG_ZERO(ppad, payload); 3085 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 3086 mlxsw_reg_ppad_local_port_set(payload, local_port); 3087 } 3088 3089 /* PAOS - Ports Administrative and Operational Status Register 3090 * ----------------------------------------------------------- 3091 * Configures and retrieves per port administrative and operational status. 3092 */ 3093 #define MLXSW_REG_PAOS_ID 0x5006 3094 #define MLXSW_REG_PAOS_LEN 0x10 3095 3096 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 3097 3098 /* reg_paos_swid 3099 * Switch partition ID with which to associate the port. 3100 * Note: while external ports uses unique local port numbers (and thus swid is 3101 * redundant), router ports use the same local port number where swid is the 3102 * only indication for the relevant port. 3103 * Access: Index 3104 */ 3105 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 3106 3107 /* reg_paos_local_port 3108 * Local port number. 3109 * Access: Index 3110 */ 3111 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 3112 3113 /* reg_paos_admin_status 3114 * Port administrative state (the desired state of the port): 3115 * 1 - Up. 3116 * 2 - Down. 3117 * 3 - Up once. This means that in case of link failure, the port won't go 3118 * into polling mode, but will wait to be re-enabled by software. 3119 * 4 - Disabled by system. Can only be set by hardware. 3120 * Access: RW 3121 */ 3122 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 3123 3124 /* reg_paos_oper_status 3125 * Port operational state (the current state): 3126 * 1 - Up. 3127 * 2 - Down. 3128 * 3 - Down by port failure. This means that the device will not let the 3129 * port up again until explicitly specified by software. 3130 * Access: RO 3131 */ 3132 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 3133 3134 /* reg_paos_ase 3135 * Admin state update enabled. 3136 * Access: WO 3137 */ 3138 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 3139 3140 /* reg_paos_ee 3141 * Event update enable. If this bit is set, event generation will be 3142 * updated based on the e field. 3143 * Access: WO 3144 */ 3145 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 3146 3147 /* reg_paos_e 3148 * Event generation on operational state change: 3149 * 0 - Do not generate event. 3150 * 1 - Generate Event. 3151 * 2 - Generate Single Event. 3152 * Access: RW 3153 */ 3154 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 3155 3156 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 3157 enum mlxsw_port_admin_status status) 3158 { 3159 MLXSW_REG_ZERO(paos, payload); 3160 mlxsw_reg_paos_swid_set(payload, 0); 3161 mlxsw_reg_paos_local_port_set(payload, local_port); 3162 mlxsw_reg_paos_admin_status_set(payload, status); 3163 mlxsw_reg_paos_oper_status_set(payload, 0); 3164 mlxsw_reg_paos_ase_set(payload, 1); 3165 mlxsw_reg_paos_ee_set(payload, 1); 3166 mlxsw_reg_paos_e_set(payload, 1); 3167 } 3168 3169 /* PFCC - Ports Flow Control Configuration Register 3170 * ------------------------------------------------ 3171 * Configures and retrieves the per port flow control configuration. 3172 */ 3173 #define MLXSW_REG_PFCC_ID 0x5007 3174 #define MLXSW_REG_PFCC_LEN 0x20 3175 3176 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 3177 3178 /* reg_pfcc_local_port 3179 * Local port number. 3180 * Access: Index 3181 */ 3182 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 3183 3184 /* reg_pfcc_pnat 3185 * Port number access type. Determines the way local_port is interpreted: 3186 * 0 - Local port number. 3187 * 1 - IB / label port number. 3188 * Access: Index 3189 */ 3190 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 3191 3192 /* reg_pfcc_shl_cap 3193 * Send to higher layers capabilities: 3194 * 0 - No capability of sending Pause and PFC frames to higher layers. 3195 * 1 - Device has capability of sending Pause and PFC frames to higher 3196 * layers. 3197 * Access: RO 3198 */ 3199 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 3200 3201 /* reg_pfcc_shl_opr 3202 * Send to higher layers operation: 3203 * 0 - Pause and PFC frames are handled by the port (default). 3204 * 1 - Pause and PFC frames are handled by the port and also sent to 3205 * higher layers. Only valid if shl_cap = 1. 3206 * Access: RW 3207 */ 3208 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 3209 3210 /* reg_pfcc_ppan 3211 * Pause policy auto negotiation. 3212 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 3213 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 3214 * based on the auto-negotiation resolution. 3215 * Access: RW 3216 * 3217 * Note: The auto-negotiation advertisement is set according to pptx and 3218 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 3219 */ 3220 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 3221 3222 /* reg_pfcc_prio_mask_tx 3223 * Bit per priority indicating if Tx flow control policy should be 3224 * updated based on bit pfctx. 3225 * Access: WO 3226 */ 3227 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 3228 3229 /* reg_pfcc_prio_mask_rx 3230 * Bit per priority indicating if Rx flow control policy should be 3231 * updated based on bit pfcrx. 3232 * Access: WO 3233 */ 3234 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 3235 3236 /* reg_pfcc_pptx 3237 * Admin Pause policy on Tx. 3238 * 0 - Never generate Pause frames (default). 3239 * 1 - Generate Pause frames according to Rx buffer threshold. 3240 * Access: RW 3241 */ 3242 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 3243 3244 /* reg_pfcc_aptx 3245 * Active (operational) Pause policy on Tx. 3246 * 0 - Never generate Pause frames. 3247 * 1 - Generate Pause frames according to Rx buffer threshold. 3248 * Access: RO 3249 */ 3250 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 3251 3252 /* reg_pfcc_pfctx 3253 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 3254 * 0 - Never generate priority Pause frames on the specified priority 3255 * (default). 3256 * 1 - Generate priority Pause frames according to Rx buffer threshold on 3257 * the specified priority. 3258 * Access: RW 3259 * 3260 * Note: pfctx and pptx must be mutually exclusive. 3261 */ 3262 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 3263 3264 /* reg_pfcc_pprx 3265 * Admin Pause policy on Rx. 3266 * 0 - Ignore received Pause frames (default). 3267 * 1 - Respect received Pause frames. 3268 * Access: RW 3269 */ 3270 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 3271 3272 /* reg_pfcc_aprx 3273 * Active (operational) Pause policy on Rx. 3274 * 0 - Ignore received Pause frames. 3275 * 1 - Respect received Pause frames. 3276 * Access: RO 3277 */ 3278 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 3279 3280 /* reg_pfcc_pfcrx 3281 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 3282 * 0 - Ignore incoming priority Pause frames on the specified priority 3283 * (default). 3284 * 1 - Respect incoming priority Pause frames on the specified priority. 3285 * Access: RW 3286 */ 3287 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 3288 3289 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 3290 3291 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 3292 { 3293 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3294 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3295 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 3296 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 3297 } 3298 3299 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 3300 { 3301 MLXSW_REG_ZERO(pfcc, payload); 3302 mlxsw_reg_pfcc_local_port_set(payload, local_port); 3303 } 3304 3305 /* PPCNT - Ports Performance Counters Register 3306 * ------------------------------------------- 3307 * The PPCNT register retrieves per port performance counters. 3308 */ 3309 #define MLXSW_REG_PPCNT_ID 0x5008 3310 #define MLXSW_REG_PPCNT_LEN 0x100 3311 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 3312 3313 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 3314 3315 /* reg_ppcnt_swid 3316 * For HCA: must be always 0. 3317 * Switch partition ID to associate port with. 3318 * Switch partitions are numbered from 0 to 7 inclusively. 3319 * Switch partition 254 indicates stacking ports. 3320 * Switch partition 255 indicates all switch partitions. 3321 * Only valid on Set() operation with local_port=255. 3322 * Access: Index 3323 */ 3324 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 3325 3326 /* reg_ppcnt_local_port 3327 * Local port number. 3328 * 255 indicates all ports on the device, and is only allowed 3329 * for Set() operation. 3330 * Access: Index 3331 */ 3332 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 3333 3334 /* reg_ppcnt_pnat 3335 * Port number access type: 3336 * 0 - Local port number 3337 * 1 - IB port number 3338 * Access: Index 3339 */ 3340 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 3341 3342 enum mlxsw_reg_ppcnt_grp { 3343 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 3344 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 3345 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 3346 MLXSW_REG_PPCNT_TC_CNT = 0x11, 3347 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 3348 }; 3349 3350 /* reg_ppcnt_grp 3351 * Performance counter group. 3352 * Group 63 indicates all groups. Only valid on Set() operation with 3353 * clr bit set. 3354 * 0x0: IEEE 802.3 Counters 3355 * 0x1: RFC 2863 Counters 3356 * 0x2: RFC 2819 Counters 3357 * 0x3: RFC 3635 Counters 3358 * 0x5: Ethernet Extended Counters 3359 * 0x8: Link Level Retransmission Counters 3360 * 0x10: Per Priority Counters 3361 * 0x11: Per Traffic Class Counters 3362 * 0x12: Physical Layer Counters 3363 * 0x13: Per Traffic Class Congestion Counters 3364 * Access: Index 3365 */ 3366 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 3367 3368 /* reg_ppcnt_clr 3369 * Clear counters. Setting the clr bit will reset the counter value 3370 * for all counters in the counter group. This bit can be set 3371 * for both Set() and Get() operation. 3372 * Access: OP 3373 */ 3374 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 3375 3376 /* reg_ppcnt_prio_tc 3377 * Priority for counter set that support per priority, valid values: 0-7. 3378 * Traffic class for counter set that support per traffic class, 3379 * valid values: 0- cap_max_tclass-1 . 3380 * For HCA: cap_max_tclass is always 8. 3381 * Otherwise must be 0. 3382 * Access: Index 3383 */ 3384 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 3385 3386 /* Ethernet IEEE 802.3 Counter Group */ 3387 3388 /* reg_ppcnt_a_frames_transmitted_ok 3389 * Access: RO 3390 */ 3391 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 3392 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3393 3394 /* reg_ppcnt_a_frames_received_ok 3395 * Access: RO 3396 */ 3397 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 3398 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3399 3400 /* reg_ppcnt_a_frame_check_sequence_errors 3401 * Access: RO 3402 */ 3403 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 3404 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 3405 3406 /* reg_ppcnt_a_alignment_errors 3407 * Access: RO 3408 */ 3409 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 3410 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 3411 3412 /* reg_ppcnt_a_octets_transmitted_ok 3413 * Access: RO 3414 */ 3415 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 3416 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3417 3418 /* reg_ppcnt_a_octets_received_ok 3419 * Access: RO 3420 */ 3421 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 3422 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3423 3424 /* reg_ppcnt_a_multicast_frames_xmitted_ok 3425 * Access: RO 3426 */ 3427 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 3428 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 3429 3430 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 3431 * Access: RO 3432 */ 3433 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 3434 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 3435 3436 /* reg_ppcnt_a_multicast_frames_received_ok 3437 * Access: RO 3438 */ 3439 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 3440 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 3441 3442 /* reg_ppcnt_a_broadcast_frames_received_ok 3443 * Access: RO 3444 */ 3445 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 3446 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3447 3448 /* reg_ppcnt_a_in_range_length_errors 3449 * Access: RO 3450 */ 3451 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 3452 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3453 3454 /* reg_ppcnt_a_out_of_range_length_field 3455 * Access: RO 3456 */ 3457 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 3458 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3459 3460 /* reg_ppcnt_a_frame_too_long_errors 3461 * Access: RO 3462 */ 3463 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 3464 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3465 3466 /* reg_ppcnt_a_symbol_error_during_carrier 3467 * Access: RO 3468 */ 3469 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 3470 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3471 3472 /* reg_ppcnt_a_mac_control_frames_transmitted 3473 * Access: RO 3474 */ 3475 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 3476 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3477 3478 /* reg_ppcnt_a_mac_control_frames_received 3479 * Access: RO 3480 */ 3481 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 3482 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 3483 3484 /* reg_ppcnt_a_unsupported_opcodes_received 3485 * Access: RO 3486 */ 3487 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 3488 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 3489 3490 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 3491 * Access: RO 3492 */ 3493 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 3494 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 3495 3496 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 3497 * Access: RO 3498 */ 3499 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 3500 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 3501 3502 /* Ethernet Extended Counter Group Counters */ 3503 3504 /* reg_ppcnt_ecn_marked 3505 * Access: RO 3506 */ 3507 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 3508 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3509 3510 /* Ethernet Per Priority Group Counters */ 3511 3512 /* reg_ppcnt_rx_octets 3513 * Access: RO 3514 */ 3515 MLXSW_ITEM64(reg, ppcnt, rx_octets, 3516 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3517 3518 /* reg_ppcnt_rx_frames 3519 * Access: RO 3520 */ 3521 MLXSW_ITEM64(reg, ppcnt, rx_frames, 3522 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 3523 3524 /* reg_ppcnt_tx_octets 3525 * Access: RO 3526 */ 3527 MLXSW_ITEM64(reg, ppcnt, tx_octets, 3528 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 3529 3530 /* reg_ppcnt_tx_frames 3531 * Access: RO 3532 */ 3533 MLXSW_ITEM64(reg, ppcnt, tx_frames, 3534 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 3535 3536 /* reg_ppcnt_rx_pause 3537 * Access: RO 3538 */ 3539 MLXSW_ITEM64(reg, ppcnt, rx_pause, 3540 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 3541 3542 /* reg_ppcnt_rx_pause_duration 3543 * Access: RO 3544 */ 3545 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 3546 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 3547 3548 /* reg_ppcnt_tx_pause 3549 * Access: RO 3550 */ 3551 MLXSW_ITEM64(reg, ppcnt, tx_pause, 3552 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 3553 3554 /* reg_ppcnt_tx_pause_duration 3555 * Access: RO 3556 */ 3557 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 3558 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 3559 3560 /* reg_ppcnt_rx_pause_transition 3561 * Access: RO 3562 */ 3563 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 3564 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 3565 3566 /* Ethernet Per Traffic Group Counters */ 3567 3568 /* reg_ppcnt_tc_transmit_queue 3569 * Contains the transmit queue depth in cells of traffic class 3570 * selected by prio_tc and the port selected by local_port. 3571 * The field cannot be cleared. 3572 * Access: RO 3573 */ 3574 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 3575 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3576 3577 /* reg_ppcnt_tc_no_buffer_discard_uc 3578 * The number of unicast packets dropped due to lack of shared 3579 * buffer resources. 3580 * Access: RO 3581 */ 3582 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 3583 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 3584 3585 /* Ethernet Per Traffic Class Congestion Group Counters */ 3586 3587 /* reg_ppcnt_wred_discard 3588 * Access: RO 3589 */ 3590 MLXSW_ITEM64(reg, ppcnt, wred_discard, 3591 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 3592 3593 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 3594 enum mlxsw_reg_ppcnt_grp grp, 3595 u8 prio_tc) 3596 { 3597 MLXSW_REG_ZERO(ppcnt, payload); 3598 mlxsw_reg_ppcnt_swid_set(payload, 0); 3599 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 3600 mlxsw_reg_ppcnt_pnat_set(payload, 0); 3601 mlxsw_reg_ppcnt_grp_set(payload, grp); 3602 mlxsw_reg_ppcnt_clr_set(payload, 0); 3603 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 3604 } 3605 3606 /* PLIB - Port Local to InfiniBand Port 3607 * ------------------------------------ 3608 * The PLIB register performs mapping from Local Port into InfiniBand Port. 3609 */ 3610 #define MLXSW_REG_PLIB_ID 0x500A 3611 #define MLXSW_REG_PLIB_LEN 0x10 3612 3613 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 3614 3615 /* reg_plib_local_port 3616 * Local port number. 3617 * Access: Index 3618 */ 3619 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 3620 3621 /* reg_plib_ib_port 3622 * InfiniBand port remapping for local_port. 3623 * Access: RW 3624 */ 3625 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 3626 3627 /* PPTB - Port Prio To Buffer Register 3628 * ----------------------------------- 3629 * Configures the switch priority to buffer table. 3630 */ 3631 #define MLXSW_REG_PPTB_ID 0x500B 3632 #define MLXSW_REG_PPTB_LEN 0x10 3633 3634 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 3635 3636 enum { 3637 MLXSW_REG_PPTB_MM_UM, 3638 MLXSW_REG_PPTB_MM_UNICAST, 3639 MLXSW_REG_PPTB_MM_MULTICAST, 3640 }; 3641 3642 /* reg_pptb_mm 3643 * Mapping mode. 3644 * 0 - Map both unicast and multicast packets to the same buffer. 3645 * 1 - Map only unicast packets. 3646 * 2 - Map only multicast packets. 3647 * Access: Index 3648 * 3649 * Note: SwitchX-2 only supports the first option. 3650 */ 3651 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 3652 3653 /* reg_pptb_local_port 3654 * Local port number. 3655 * Access: Index 3656 */ 3657 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 3658 3659 /* reg_pptb_um 3660 * Enables the update of the untagged_buf field. 3661 * Access: RW 3662 */ 3663 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 3664 3665 /* reg_pptb_pm 3666 * Enables the update of the prio_to_buff field. 3667 * Bit <i> is a flag for updating the mapping for switch priority <i>. 3668 * Access: RW 3669 */ 3670 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 3671 3672 /* reg_pptb_prio_to_buff 3673 * Mapping of switch priority <i> to one of the allocated receive port 3674 * buffers. 3675 * Access: RW 3676 */ 3677 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 3678 3679 /* reg_pptb_pm_msb 3680 * Enables the update of the prio_to_buff field. 3681 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 3682 * Access: RW 3683 */ 3684 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 3685 3686 /* reg_pptb_untagged_buff 3687 * Mapping of untagged frames to one of the allocated receive port buffers. 3688 * Access: RW 3689 * 3690 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 3691 * Spectrum, as it maps untagged packets based on the default switch priority. 3692 */ 3693 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 3694 3695 /* reg_pptb_prio_to_buff_msb 3696 * Mapping of switch priority <i+8> to one of the allocated receive port 3697 * buffers. 3698 * Access: RW 3699 */ 3700 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 3701 3702 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 3703 3704 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 3705 { 3706 MLXSW_REG_ZERO(pptb, payload); 3707 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 3708 mlxsw_reg_pptb_local_port_set(payload, local_port); 3709 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3710 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3711 } 3712 3713 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 3714 u8 buff) 3715 { 3716 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 3717 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 3718 } 3719 3720 /* PBMC - Port Buffer Management Control Register 3721 * ---------------------------------------------- 3722 * The PBMC register configures and retrieves the port packet buffer 3723 * allocation for different Prios, and the Pause threshold management. 3724 */ 3725 #define MLXSW_REG_PBMC_ID 0x500C 3726 #define MLXSW_REG_PBMC_LEN 0x6C 3727 3728 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 3729 3730 /* reg_pbmc_local_port 3731 * Local port number. 3732 * Access: Index 3733 */ 3734 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 3735 3736 /* reg_pbmc_xoff_timer_value 3737 * When device generates a pause frame, it uses this value as the pause 3738 * timer (time for the peer port to pause in quota-512 bit time). 3739 * Access: RW 3740 */ 3741 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 3742 3743 /* reg_pbmc_xoff_refresh 3744 * The time before a new pause frame should be sent to refresh the pause RW 3745 * state. Using the same units as xoff_timer_value above (in quota-512 bit 3746 * time). 3747 * Access: RW 3748 */ 3749 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 3750 3751 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 3752 3753 /* reg_pbmc_buf_lossy 3754 * The field indicates if the buffer is lossy. 3755 * 0 - Lossless 3756 * 1 - Lossy 3757 * Access: RW 3758 */ 3759 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 3760 3761 /* reg_pbmc_buf_epsb 3762 * Eligible for Port Shared buffer. 3763 * If epsb is set, packets assigned to buffer are allowed to insert the port 3764 * shared buffer. 3765 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 3766 * Access: RW 3767 */ 3768 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 3769 3770 /* reg_pbmc_buf_size 3771 * The part of the packet buffer array is allocated for the specific buffer. 3772 * Units are represented in cells. 3773 * Access: RW 3774 */ 3775 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 3776 3777 /* reg_pbmc_buf_xoff_threshold 3778 * Once the amount of data in the buffer goes above this value, device 3779 * starts sending PFC frames for all priorities associated with the 3780 * buffer. Units are represented in cells. Reserved in case of lossy 3781 * buffer. 3782 * Access: RW 3783 * 3784 * Note: In Spectrum, reserved for buffer[9]. 3785 */ 3786 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 3787 0x08, 0x04, false); 3788 3789 /* reg_pbmc_buf_xon_threshold 3790 * When the amount of data in the buffer goes below this value, device 3791 * stops sending PFC frames for the priorities associated with the 3792 * buffer. Units are represented in cells. Reserved in case of lossy 3793 * buffer. 3794 * Access: RW 3795 * 3796 * Note: In Spectrum, reserved for buffer[9]. 3797 */ 3798 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 3799 0x08, 0x04, false); 3800 3801 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 3802 u16 xoff_timer_value, u16 xoff_refresh) 3803 { 3804 MLXSW_REG_ZERO(pbmc, payload); 3805 mlxsw_reg_pbmc_local_port_set(payload, local_port); 3806 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 3807 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 3808 } 3809 3810 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 3811 int buf_index, 3812 u16 size) 3813 { 3814 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 3815 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3816 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3817 } 3818 3819 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 3820 int buf_index, u16 size, 3821 u16 threshold) 3822 { 3823 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 3824 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3825 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3826 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 3827 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 3828 } 3829 3830 /* PSPA - Port Switch Partition Allocation 3831 * --------------------------------------- 3832 * Controls the association of a port with a switch partition and enables 3833 * configuring ports as stacking ports. 3834 */ 3835 #define MLXSW_REG_PSPA_ID 0x500D 3836 #define MLXSW_REG_PSPA_LEN 0x8 3837 3838 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 3839 3840 /* reg_pspa_swid 3841 * Switch partition ID. 3842 * Access: RW 3843 */ 3844 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 3845 3846 /* reg_pspa_local_port 3847 * Local port number. 3848 * Access: Index 3849 */ 3850 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 3851 3852 /* reg_pspa_sub_port 3853 * Virtual port within the local port. Set to 0 when virtual ports are 3854 * disabled on the local port. 3855 * Access: Index 3856 */ 3857 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 3858 3859 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 3860 { 3861 MLXSW_REG_ZERO(pspa, payload); 3862 mlxsw_reg_pspa_swid_set(payload, swid); 3863 mlxsw_reg_pspa_local_port_set(payload, local_port); 3864 mlxsw_reg_pspa_sub_port_set(payload, 0); 3865 } 3866 3867 /* HTGT - Host Trap Group Table 3868 * ---------------------------- 3869 * Configures the properties for forwarding to CPU. 3870 */ 3871 #define MLXSW_REG_HTGT_ID 0x7002 3872 #define MLXSW_REG_HTGT_LEN 0x20 3873 3874 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 3875 3876 /* reg_htgt_swid 3877 * Switch partition ID. 3878 * Access: Index 3879 */ 3880 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 3881 3882 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 3883 3884 /* reg_htgt_type 3885 * CPU path type. 3886 * Access: RW 3887 */ 3888 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 3889 3890 enum mlxsw_reg_htgt_trap_group { 3891 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3892 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 3893 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 3894 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 3895 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 3896 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 3897 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 3898 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 3899 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 3900 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 3901 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 3902 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 3903 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 3904 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 3905 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 3906 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 3907 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 3908 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 3909 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 3910 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 3911 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 3912 }; 3913 3914 /* reg_htgt_trap_group 3915 * Trap group number. User defined number specifying which trap groups 3916 * should be forwarded to the CPU. The mapping between trap IDs and trap 3917 * groups is configured using HPKT register. 3918 * Access: Index 3919 */ 3920 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 3921 3922 enum { 3923 MLXSW_REG_HTGT_POLICER_DISABLE, 3924 MLXSW_REG_HTGT_POLICER_ENABLE, 3925 }; 3926 3927 /* reg_htgt_pide 3928 * Enable policer ID specified using 'pid' field. 3929 * Access: RW 3930 */ 3931 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 3932 3933 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 3934 3935 /* reg_htgt_pid 3936 * Policer ID for the trap group. 3937 * Access: RW 3938 */ 3939 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 3940 3941 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 3942 3943 /* reg_htgt_mirror_action 3944 * Mirror action to use. 3945 * 0 - Trap to CPU. 3946 * 1 - Trap to CPU and mirror to a mirroring agent. 3947 * 2 - Mirror to a mirroring agent and do not trap to CPU. 3948 * Access: RW 3949 * 3950 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 3951 */ 3952 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 3953 3954 /* reg_htgt_mirroring_agent 3955 * Mirroring agent. 3956 * Access: RW 3957 */ 3958 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 3959 3960 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 3961 3962 /* reg_htgt_priority 3963 * Trap group priority. 3964 * In case a packet matches multiple classification rules, the packet will 3965 * only be trapped once, based on the trap ID associated with the group (via 3966 * register HPKT) with the highest priority. 3967 * Supported values are 0-7, with 7 represnting the highest priority. 3968 * Access: RW 3969 * 3970 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 3971 * by the 'trap_group' field. 3972 */ 3973 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 3974 3975 #define MLXSW_REG_HTGT_DEFAULT_TC 7 3976 3977 /* reg_htgt_local_path_cpu_tclass 3978 * CPU ingress traffic class for the trap group. 3979 * Access: RW 3980 */ 3981 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 3982 3983 enum mlxsw_reg_htgt_local_path_rdq { 3984 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 3985 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 3986 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 3987 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 3988 }; 3989 /* reg_htgt_local_path_rdq 3990 * Receive descriptor queue (RDQ) to use for the trap group. 3991 * Access: RW 3992 */ 3993 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 3994 3995 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 3996 u8 priority, u8 tc) 3997 { 3998 MLXSW_REG_ZERO(htgt, payload); 3999 4000 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 4001 mlxsw_reg_htgt_pide_set(payload, 4002 MLXSW_REG_HTGT_POLICER_DISABLE); 4003 } else { 4004 mlxsw_reg_htgt_pide_set(payload, 4005 MLXSW_REG_HTGT_POLICER_ENABLE); 4006 mlxsw_reg_htgt_pid_set(payload, policer_id); 4007 } 4008 4009 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 4010 mlxsw_reg_htgt_trap_group_set(payload, group); 4011 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 4012 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 4013 mlxsw_reg_htgt_priority_set(payload, priority); 4014 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 4015 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 4016 } 4017 4018 /* HPKT - Host Packet Trap 4019 * ----------------------- 4020 * Configures trap IDs inside trap groups. 4021 */ 4022 #define MLXSW_REG_HPKT_ID 0x7003 4023 #define MLXSW_REG_HPKT_LEN 0x10 4024 4025 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 4026 4027 enum { 4028 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 4029 MLXSW_REG_HPKT_ACK_REQUIRED, 4030 }; 4031 4032 /* reg_hpkt_ack 4033 * Require acknowledgements from the host for events. 4034 * If set, then the device will wait for the event it sent to be acknowledged 4035 * by the host. This option is only relevant for event trap IDs. 4036 * Access: RW 4037 * 4038 * Note: Currently not supported by firmware. 4039 */ 4040 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 4041 4042 enum mlxsw_reg_hpkt_action { 4043 MLXSW_REG_HPKT_ACTION_FORWARD, 4044 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 4045 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 4046 MLXSW_REG_HPKT_ACTION_DISCARD, 4047 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 4048 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 4049 }; 4050 4051 /* reg_hpkt_action 4052 * Action to perform on packet when trapped. 4053 * 0 - No action. Forward to CPU based on switching rules. 4054 * 1 - Trap to CPU (CPU receives sole copy). 4055 * 2 - Mirror to CPU (CPU receives a replica of the packet). 4056 * 3 - Discard. 4057 * 4 - Soft discard (allow other traps to act on the packet). 4058 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 4059 * Access: RW 4060 * 4061 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 4062 * addressed to the CPU. 4063 */ 4064 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 4065 4066 /* reg_hpkt_trap_group 4067 * Trap group to associate the trap with. 4068 * Access: RW 4069 */ 4070 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 4071 4072 /* reg_hpkt_trap_id 4073 * Trap ID. 4074 * Access: Index 4075 * 4076 * Note: A trap ID can only be associated with a single trap group. The device 4077 * will associate the trap ID with the last trap group configured. 4078 */ 4079 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 4080 4081 enum { 4082 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 4083 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 4084 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 4085 }; 4086 4087 /* reg_hpkt_ctrl 4088 * Configure dedicated buffer resources for control packets. 4089 * Ignored by SwitchX-2. 4090 * 0 - Keep factory defaults. 4091 * 1 - Do not use control buffer for this trap ID. 4092 * 2 - Use control buffer for this trap ID. 4093 * Access: RW 4094 */ 4095 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 4096 4097 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 4098 enum mlxsw_reg_htgt_trap_group trap_group, 4099 bool is_ctrl) 4100 { 4101 MLXSW_REG_ZERO(hpkt, payload); 4102 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 4103 mlxsw_reg_hpkt_action_set(payload, action); 4104 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 4105 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 4106 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 4107 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 4108 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 4109 } 4110 4111 /* RGCR - Router General Configuration Register 4112 * -------------------------------------------- 4113 * The register is used for setting up the router configuration. 4114 */ 4115 #define MLXSW_REG_RGCR_ID 0x8001 4116 #define MLXSW_REG_RGCR_LEN 0x28 4117 4118 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 4119 4120 /* reg_rgcr_ipv4_en 4121 * IPv4 router enable. 4122 * Access: RW 4123 */ 4124 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 4125 4126 /* reg_rgcr_ipv6_en 4127 * IPv6 router enable. 4128 * Access: RW 4129 */ 4130 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 4131 4132 /* reg_rgcr_max_router_interfaces 4133 * Defines the maximum number of active router interfaces for all virtual 4134 * routers. 4135 * Access: RW 4136 */ 4137 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 4138 4139 /* reg_rgcr_usp 4140 * Update switch priority and packet color. 4141 * 0 - Preserve the value of Switch Priority and packet color. 4142 * 1 - Recalculate the value of Switch Priority and packet color. 4143 * Access: RW 4144 * 4145 * Note: Not supported by SwitchX and SwitchX-2. 4146 */ 4147 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 4148 4149 /* reg_rgcr_pcp_rw 4150 * Indicates how to handle the pcp_rewrite_en value: 4151 * 0 - Preserve the value of pcp_rewrite_en. 4152 * 2 - Disable PCP rewrite. 4153 * 3 - Enable PCP rewrite. 4154 * Access: RW 4155 * 4156 * Note: Not supported by SwitchX and SwitchX-2. 4157 */ 4158 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 4159 4160 /* reg_rgcr_activity_dis 4161 * Activity disable: 4162 * 0 - Activity will be set when an entry is hit (default). 4163 * 1 - Activity will not be set when an entry is hit. 4164 * 4165 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 4166 * (RALUE). 4167 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 4168 * Entry (RAUHT). 4169 * Bits 2:7 are reserved. 4170 * Access: RW 4171 * 4172 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 4173 */ 4174 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 4175 4176 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 4177 bool ipv6_en) 4178 { 4179 MLXSW_REG_ZERO(rgcr, payload); 4180 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 4181 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 4182 } 4183 4184 /* RITR - Router Interface Table Register 4185 * -------------------------------------- 4186 * The register is used to configure the router interface table. 4187 */ 4188 #define MLXSW_REG_RITR_ID 0x8002 4189 #define MLXSW_REG_RITR_LEN 0x40 4190 4191 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 4192 4193 /* reg_ritr_enable 4194 * Enables routing on the router interface. 4195 * Access: RW 4196 */ 4197 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 4198 4199 /* reg_ritr_ipv4 4200 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 4201 * interface. 4202 * Access: RW 4203 */ 4204 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 4205 4206 /* reg_ritr_ipv6 4207 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 4208 * interface. 4209 * Access: RW 4210 */ 4211 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 4212 4213 /* reg_ritr_ipv4_mc 4214 * IPv4 multicast routing enable. 4215 * Access: RW 4216 */ 4217 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 4218 4219 enum mlxsw_reg_ritr_if_type { 4220 /* VLAN interface. */ 4221 MLXSW_REG_RITR_VLAN_IF, 4222 /* FID interface. */ 4223 MLXSW_REG_RITR_FID_IF, 4224 /* Sub-port interface. */ 4225 MLXSW_REG_RITR_SP_IF, 4226 /* Loopback Interface. */ 4227 MLXSW_REG_RITR_LOOPBACK_IF, 4228 }; 4229 4230 /* reg_ritr_type 4231 * Router interface type as per enum mlxsw_reg_ritr_if_type. 4232 * Access: RW 4233 */ 4234 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 4235 4236 enum { 4237 MLXSW_REG_RITR_RIF_CREATE, 4238 MLXSW_REG_RITR_RIF_DEL, 4239 }; 4240 4241 /* reg_ritr_op 4242 * Opcode: 4243 * 0 - Create or edit RIF. 4244 * 1 - Delete RIF. 4245 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 4246 * is not supported. An interface must be deleted and re-created in order 4247 * to update properties. 4248 * Access: WO 4249 */ 4250 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 4251 4252 /* reg_ritr_rif 4253 * Router interface index. A pointer to the Router Interface Table. 4254 * Access: Index 4255 */ 4256 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 4257 4258 /* reg_ritr_ipv4_fe 4259 * IPv4 Forwarding Enable. 4260 * Enables routing of IPv4 traffic on the router interface. When disabled, 4261 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4262 * Not supported in SwitchX-2. 4263 * Access: RW 4264 */ 4265 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 4266 4267 /* reg_ritr_ipv6_fe 4268 * IPv6 Forwarding Enable. 4269 * Enables routing of IPv6 traffic on the router interface. When disabled, 4270 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4271 * Not supported in SwitchX-2. 4272 * Access: RW 4273 */ 4274 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 4275 4276 /* reg_ritr_ipv4_mc_fe 4277 * IPv4 Multicast Forwarding Enable. 4278 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4279 * will be enabled. 4280 * Access: RW 4281 */ 4282 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 4283 4284 /* reg_ritr_lb_en 4285 * Loop-back filter enable for unicast packets. 4286 * If the flag is set then loop-back filter for unicast packets is 4287 * implemented on the RIF. Multicast packets are always subject to 4288 * loop-back filtering. 4289 * Access: RW 4290 */ 4291 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 4292 4293 /* reg_ritr_virtual_router 4294 * Virtual router ID associated with the router interface. 4295 * Access: RW 4296 */ 4297 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 4298 4299 /* reg_ritr_mtu 4300 * Router interface MTU. 4301 * Access: RW 4302 */ 4303 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 4304 4305 /* reg_ritr_if_swid 4306 * Switch partition ID. 4307 * Access: RW 4308 */ 4309 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 4310 4311 /* reg_ritr_if_mac 4312 * Router interface MAC address. 4313 * In Spectrum, all MAC addresses must have the same 38 MSBits. 4314 * Access: RW 4315 */ 4316 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 4317 4318 /* VLAN Interface */ 4319 4320 /* reg_ritr_vlan_if_vid 4321 * VLAN ID. 4322 * Access: RW 4323 */ 4324 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 4325 4326 /* FID Interface */ 4327 4328 /* reg_ritr_fid_if_fid 4329 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 4330 * the vFID range are supported. 4331 * Access: RW 4332 */ 4333 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 4334 4335 static inline void mlxsw_reg_ritr_fid_set(char *payload, 4336 enum mlxsw_reg_ritr_if_type rif_type, 4337 u16 fid) 4338 { 4339 if (rif_type == MLXSW_REG_RITR_FID_IF) 4340 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 4341 else 4342 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 4343 } 4344 4345 /* Sub-port Interface */ 4346 4347 /* reg_ritr_sp_if_lag 4348 * LAG indication. When this bit is set the system_port field holds the 4349 * LAG identifier. 4350 * Access: RW 4351 */ 4352 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 4353 4354 /* reg_ritr_sp_system_port 4355 * Port unique indentifier. When lag bit is set, this field holds the 4356 * lag_id in bits 0:9. 4357 * Access: RW 4358 */ 4359 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 4360 4361 /* reg_ritr_sp_if_vid 4362 * VLAN ID. 4363 * Access: RW 4364 */ 4365 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 4366 4367 /* Loopback Interface */ 4368 4369 enum mlxsw_reg_ritr_loopback_protocol { 4370 /* IPinIP IPv4 underlay Unicast */ 4371 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 4372 /* IPinIP IPv6 underlay Unicast */ 4373 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 4374 }; 4375 4376 /* reg_ritr_loopback_protocol 4377 * Access: RW 4378 */ 4379 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 4380 4381 enum mlxsw_reg_ritr_loopback_ipip_type { 4382 /* Tunnel is IPinIP. */ 4383 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 4384 /* Tunnel is GRE, no key. */ 4385 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 4386 /* Tunnel is GRE, with a key. */ 4387 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 4388 }; 4389 4390 /* reg_ritr_loopback_ipip_type 4391 * Encapsulation type. 4392 * Access: RW 4393 */ 4394 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 4395 4396 enum mlxsw_reg_ritr_loopback_ipip_options { 4397 /* The key is defined by gre_key. */ 4398 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 4399 }; 4400 4401 /* reg_ritr_loopback_ipip_options 4402 * Access: RW 4403 */ 4404 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 4405 4406 /* reg_ritr_loopback_ipip_uvr 4407 * Underlay Virtual Router ID. 4408 * Range is 0..cap_max_virtual_routers-1. 4409 * Reserved for Spectrum-2. 4410 * Access: RW 4411 */ 4412 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 4413 4414 /* reg_ritr_loopback_ipip_usip* 4415 * Encapsulation Underlay source IP. 4416 * Access: RW 4417 */ 4418 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 4419 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 4420 4421 /* reg_ritr_loopback_ipip_gre_key 4422 * GRE Key. 4423 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 4424 * Access: RW 4425 */ 4426 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 4427 4428 /* Shared between ingress/egress */ 4429 enum mlxsw_reg_ritr_counter_set_type { 4430 /* No Count. */ 4431 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 4432 /* Basic. Used for router interfaces, counting the following: 4433 * - Error and Discard counters. 4434 * - Unicast, Multicast and Broadcast counters. Sharing the 4435 * same set of counters for the different type of traffic 4436 * (IPv4, IPv6 and mpls). 4437 */ 4438 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 4439 }; 4440 4441 /* reg_ritr_ingress_counter_index 4442 * Counter Index for flow counter. 4443 * Access: RW 4444 */ 4445 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 4446 4447 /* reg_ritr_ingress_counter_set_type 4448 * Igress Counter Set Type for router interface counter. 4449 * Access: RW 4450 */ 4451 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 4452 4453 /* reg_ritr_egress_counter_index 4454 * Counter Index for flow counter. 4455 * Access: RW 4456 */ 4457 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 4458 4459 /* reg_ritr_egress_counter_set_type 4460 * Egress Counter Set Type for router interface counter. 4461 * Access: RW 4462 */ 4463 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 4464 4465 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 4466 bool enable, bool egress) 4467 { 4468 enum mlxsw_reg_ritr_counter_set_type set_type; 4469 4470 if (enable) 4471 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 4472 else 4473 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 4474 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 4475 4476 if (egress) 4477 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 4478 else 4479 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 4480 } 4481 4482 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 4483 { 4484 MLXSW_REG_ZERO(ritr, payload); 4485 mlxsw_reg_ritr_rif_set(payload, rif); 4486 } 4487 4488 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 4489 u16 system_port, u16 vid) 4490 { 4491 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 4492 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 4493 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 4494 } 4495 4496 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 4497 enum mlxsw_reg_ritr_if_type type, 4498 u16 rif, u16 vr_id, u16 mtu) 4499 { 4500 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 4501 4502 MLXSW_REG_ZERO(ritr, payload); 4503 mlxsw_reg_ritr_enable_set(payload, enable); 4504 mlxsw_reg_ritr_ipv4_set(payload, 1); 4505 mlxsw_reg_ritr_ipv6_set(payload, 1); 4506 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 4507 mlxsw_reg_ritr_type_set(payload, type); 4508 mlxsw_reg_ritr_op_set(payload, op); 4509 mlxsw_reg_ritr_rif_set(payload, rif); 4510 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 4511 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 4512 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 4513 mlxsw_reg_ritr_lb_en_set(payload, 1); 4514 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 4515 mlxsw_reg_ritr_mtu_set(payload, mtu); 4516 } 4517 4518 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 4519 { 4520 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 4521 } 4522 4523 static inline void 4524 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 4525 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4526 enum mlxsw_reg_ritr_loopback_ipip_options options, 4527 u16 uvr_id, u32 gre_key) 4528 { 4529 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 4530 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 4531 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 4532 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 4533 } 4534 4535 static inline void 4536 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 4537 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4538 enum mlxsw_reg_ritr_loopback_ipip_options options, 4539 u16 uvr_id, u32 usip, u32 gre_key) 4540 { 4541 mlxsw_reg_ritr_loopback_protocol_set(payload, 4542 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 4543 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 4544 uvr_id, gre_key); 4545 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 4546 } 4547 4548 /* RTAR - Router TCAM Allocation Register 4549 * -------------------------------------- 4550 * This register is used for allocation of regions in the TCAM table. 4551 */ 4552 #define MLXSW_REG_RTAR_ID 0x8004 4553 #define MLXSW_REG_RTAR_LEN 0x20 4554 4555 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 4556 4557 enum mlxsw_reg_rtar_op { 4558 MLXSW_REG_RTAR_OP_ALLOCATE, 4559 MLXSW_REG_RTAR_OP_RESIZE, 4560 MLXSW_REG_RTAR_OP_DEALLOCATE, 4561 }; 4562 4563 /* reg_rtar_op 4564 * Access: WO 4565 */ 4566 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 4567 4568 enum mlxsw_reg_rtar_key_type { 4569 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 4570 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 4571 }; 4572 4573 /* reg_rtar_key_type 4574 * TCAM key type for the region. 4575 * Access: WO 4576 */ 4577 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 4578 4579 /* reg_rtar_region_size 4580 * TCAM region size. When allocating/resizing this is the requested 4581 * size, the response is the actual size. 4582 * Note: Actual size may be larger than requested. 4583 * Reserved for op = Deallocate 4584 * Access: WO 4585 */ 4586 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 4587 4588 static inline void mlxsw_reg_rtar_pack(char *payload, 4589 enum mlxsw_reg_rtar_op op, 4590 enum mlxsw_reg_rtar_key_type key_type, 4591 u16 region_size) 4592 { 4593 MLXSW_REG_ZERO(rtar, payload); 4594 mlxsw_reg_rtar_op_set(payload, op); 4595 mlxsw_reg_rtar_key_type_set(payload, key_type); 4596 mlxsw_reg_rtar_region_size_set(payload, region_size); 4597 } 4598 4599 /* RATR - Router Adjacency Table Register 4600 * -------------------------------------- 4601 * The RATR register is used to configure the Router Adjacency (next-hop) 4602 * Table. 4603 */ 4604 #define MLXSW_REG_RATR_ID 0x8008 4605 #define MLXSW_REG_RATR_LEN 0x2C 4606 4607 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 4608 4609 enum mlxsw_reg_ratr_op { 4610 /* Read */ 4611 MLXSW_REG_RATR_OP_QUERY_READ = 0, 4612 /* Read and clear activity */ 4613 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 4614 /* Write Adjacency entry */ 4615 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 4616 /* Write Adjacency entry only if the activity is cleared. 4617 * The write may not succeed if the activity is set. There is not 4618 * direct feedback if the write has succeeded or not, however 4619 * the get will reveal the actual entry (SW can compare the get 4620 * response to the set command). 4621 */ 4622 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 4623 }; 4624 4625 /* reg_ratr_op 4626 * Note that Write operation may also be used for updating 4627 * counter_set_type and counter_index. In this case all other 4628 * fields must not be updated. 4629 * Access: OP 4630 */ 4631 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 4632 4633 /* reg_ratr_v 4634 * Valid bit. Indicates if the adjacency entry is valid. 4635 * Note: the device may need some time before reusing an invalidated 4636 * entry. During this time the entry can not be reused. It is 4637 * recommended to use another entry before reusing an invalidated 4638 * entry (e.g. software can put it at the end of the list for 4639 * reusing). Trying to access an invalidated entry not yet cleared 4640 * by the device results with failure indicating "Try Again" status. 4641 * When valid is '0' then egress_router_interface,trap_action, 4642 * adjacency_parameters and counters are reserved 4643 * Access: RW 4644 */ 4645 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 4646 4647 /* reg_ratr_a 4648 * Activity. Set for new entries. Set if a packet lookup has hit on 4649 * the specific entry. To clear the a bit, use "clear activity". 4650 * Access: RO 4651 */ 4652 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 4653 4654 enum mlxsw_reg_ratr_type { 4655 /* Ethernet */ 4656 MLXSW_REG_RATR_TYPE_ETHERNET, 4657 /* IPoIB Unicast without GRH. 4658 * Reserved for Spectrum. 4659 */ 4660 MLXSW_REG_RATR_TYPE_IPOIB_UC, 4661 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 4662 * adjacency). 4663 * Reserved for Spectrum. 4664 */ 4665 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 4666 /* IPoIB Multicast. 4667 * Reserved for Spectrum. 4668 */ 4669 MLXSW_REG_RATR_TYPE_IPOIB_MC, 4670 /* MPLS. 4671 * Reserved for SwitchX/-2. 4672 */ 4673 MLXSW_REG_RATR_TYPE_MPLS, 4674 /* IPinIP Encap. 4675 * Reserved for SwitchX/-2. 4676 */ 4677 MLXSW_REG_RATR_TYPE_IPIP, 4678 }; 4679 4680 /* reg_ratr_type 4681 * Adjacency entry type. 4682 * Access: RW 4683 */ 4684 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 4685 4686 /* reg_ratr_adjacency_index_low 4687 * Bits 15:0 of index into the adjacency table. 4688 * For SwitchX and SwitchX-2, the adjacency table is linear and 4689 * used for adjacency entries only. 4690 * For Spectrum, the index is to the KVD linear. 4691 * Access: Index 4692 */ 4693 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 4694 4695 /* reg_ratr_egress_router_interface 4696 * Range is 0 .. cap_max_router_interfaces - 1 4697 * Access: RW 4698 */ 4699 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 4700 4701 enum mlxsw_reg_ratr_trap_action { 4702 MLXSW_REG_RATR_TRAP_ACTION_NOP, 4703 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 4704 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 4705 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 4706 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 4707 }; 4708 4709 /* reg_ratr_trap_action 4710 * see mlxsw_reg_ratr_trap_action 4711 * Access: RW 4712 */ 4713 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 4714 4715 /* reg_ratr_adjacency_index_high 4716 * Bits 23:16 of the adjacency_index. 4717 * Access: Index 4718 */ 4719 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 4720 4721 enum mlxsw_reg_ratr_trap_id { 4722 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 4723 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 4724 }; 4725 4726 /* reg_ratr_trap_id 4727 * Trap ID to be reported to CPU. 4728 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 4729 * For trap_action of NOP, MIRROR and DISCARD_ERROR 4730 * Access: RW 4731 */ 4732 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 4733 4734 /* reg_ratr_eth_destination_mac 4735 * MAC address of the destination next-hop. 4736 * Access: RW 4737 */ 4738 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 4739 4740 enum mlxsw_reg_ratr_ipip_type { 4741 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 4742 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 4743 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 4744 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 4745 }; 4746 4747 /* reg_ratr_ipip_type 4748 * Underlay destination ip type. 4749 * Note: the type field must match the protocol of the router interface. 4750 * Access: RW 4751 */ 4752 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 4753 4754 /* reg_ratr_ipip_ipv4_udip 4755 * Underlay ipv4 dip. 4756 * Reserved when ipip_type is IPv6. 4757 * Access: RW 4758 */ 4759 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 4760 4761 /* reg_ratr_ipip_ipv6_ptr 4762 * Pointer to IPv6 underlay destination ip address. 4763 * For Spectrum: Pointer to KVD linear space. 4764 * Access: RW 4765 */ 4766 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 4767 4768 enum mlxsw_reg_flow_counter_set_type { 4769 /* No count */ 4770 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4771 /* Count packets and bytes */ 4772 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 4773 /* Count only packets */ 4774 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 4775 }; 4776 4777 /* reg_ratr_counter_set_type 4778 * Counter set type for flow counters 4779 * Access: RW 4780 */ 4781 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 4782 4783 /* reg_ratr_counter_index 4784 * Counter index for flow counters 4785 * Access: RW 4786 */ 4787 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 4788 4789 static inline void 4790 mlxsw_reg_ratr_pack(char *payload, 4791 enum mlxsw_reg_ratr_op op, bool valid, 4792 enum mlxsw_reg_ratr_type type, 4793 u32 adjacency_index, u16 egress_rif) 4794 { 4795 MLXSW_REG_ZERO(ratr, payload); 4796 mlxsw_reg_ratr_op_set(payload, op); 4797 mlxsw_reg_ratr_v_set(payload, valid); 4798 mlxsw_reg_ratr_type_set(payload, type); 4799 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 4800 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 4801 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 4802 } 4803 4804 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 4805 const char *dest_mac) 4806 { 4807 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 4808 } 4809 4810 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 4811 { 4812 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 4813 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 4814 } 4815 4816 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 4817 bool counter_enable) 4818 { 4819 enum mlxsw_reg_flow_counter_set_type set_type; 4820 4821 if (counter_enable) 4822 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 4823 else 4824 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 4825 4826 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 4827 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 4828 } 4829 4830 /* RICNT - Router Interface Counter Register 4831 * ----------------------------------------- 4832 * The RICNT register retrieves per port performance counters 4833 */ 4834 #define MLXSW_REG_RICNT_ID 0x800B 4835 #define MLXSW_REG_RICNT_LEN 0x100 4836 4837 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 4838 4839 /* reg_ricnt_counter_index 4840 * Counter index 4841 * Access: RW 4842 */ 4843 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 4844 4845 enum mlxsw_reg_ricnt_counter_set_type { 4846 /* No Count. */ 4847 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4848 /* Basic. Used for router interfaces, counting the following: 4849 * - Error and Discard counters. 4850 * - Unicast, Multicast and Broadcast counters. Sharing the 4851 * same set of counters for the different type of traffic 4852 * (IPv4, IPv6 and mpls). 4853 */ 4854 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 4855 }; 4856 4857 /* reg_ricnt_counter_set_type 4858 * Counter Set Type for router interface counter 4859 * Access: RW 4860 */ 4861 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 4862 4863 enum mlxsw_reg_ricnt_opcode { 4864 /* Nop. Supported only for read access*/ 4865 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 4866 /* Clear. Setting the clr bit will reset the counter value for 4867 * all counters of the specified Router Interface. 4868 */ 4869 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 4870 }; 4871 4872 /* reg_ricnt_opcode 4873 * Opcode 4874 * Access: RW 4875 */ 4876 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 4877 4878 /* reg_ricnt_good_unicast_packets 4879 * good unicast packets. 4880 * Access: RW 4881 */ 4882 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 4883 4884 /* reg_ricnt_good_multicast_packets 4885 * good multicast packets. 4886 * Access: RW 4887 */ 4888 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 4889 4890 /* reg_ricnt_good_broadcast_packets 4891 * good broadcast packets 4892 * Access: RW 4893 */ 4894 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 4895 4896 /* reg_ricnt_good_unicast_bytes 4897 * A count of L3 data and padding octets not including L2 headers 4898 * for good unicast frames. 4899 * Access: RW 4900 */ 4901 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 4902 4903 /* reg_ricnt_good_multicast_bytes 4904 * A count of L3 data and padding octets not including L2 headers 4905 * for good multicast frames. 4906 * Access: RW 4907 */ 4908 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 4909 4910 /* reg_ritr_good_broadcast_bytes 4911 * A count of L3 data and padding octets not including L2 headers 4912 * for good broadcast frames. 4913 * Access: RW 4914 */ 4915 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 4916 4917 /* reg_ricnt_error_packets 4918 * A count of errored frames that do not pass the router checks. 4919 * Access: RW 4920 */ 4921 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 4922 4923 /* reg_ricnt_discrad_packets 4924 * A count of non-errored frames that do not pass the router checks. 4925 * Access: RW 4926 */ 4927 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 4928 4929 /* reg_ricnt_error_bytes 4930 * A count of L3 data and padding octets not including L2 headers 4931 * for errored frames. 4932 * Access: RW 4933 */ 4934 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 4935 4936 /* reg_ricnt_discard_bytes 4937 * A count of L3 data and padding octets not including L2 headers 4938 * for non-errored frames that do not pass the router checks. 4939 * Access: RW 4940 */ 4941 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 4942 4943 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 4944 enum mlxsw_reg_ricnt_opcode op) 4945 { 4946 MLXSW_REG_ZERO(ricnt, payload); 4947 mlxsw_reg_ricnt_op_set(payload, op); 4948 mlxsw_reg_ricnt_counter_index_set(payload, index); 4949 mlxsw_reg_ricnt_counter_set_type_set(payload, 4950 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 4951 } 4952 4953 /* RRCR - Router Rules Copy Register Layout 4954 * ---------------------------------------- 4955 * This register is used for moving and copying route entry rules. 4956 */ 4957 #define MLXSW_REG_RRCR_ID 0x800F 4958 #define MLXSW_REG_RRCR_LEN 0x24 4959 4960 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 4961 4962 enum mlxsw_reg_rrcr_op { 4963 /* Move rules */ 4964 MLXSW_REG_RRCR_OP_MOVE, 4965 /* Copy rules */ 4966 MLXSW_REG_RRCR_OP_COPY, 4967 }; 4968 4969 /* reg_rrcr_op 4970 * Access: WO 4971 */ 4972 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 4973 4974 /* reg_rrcr_offset 4975 * Offset within the region from which to copy/move. 4976 * Access: Index 4977 */ 4978 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 4979 4980 /* reg_rrcr_size 4981 * The number of rules to copy/move. 4982 * Access: WO 4983 */ 4984 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 4985 4986 /* reg_rrcr_table_id 4987 * Identifier of the table on which to perform the operation. Encoding is the 4988 * same as in RTAR.key_type 4989 * Access: Index 4990 */ 4991 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 4992 4993 /* reg_rrcr_dest_offset 4994 * Offset within the region to which to copy/move 4995 * Access: Index 4996 */ 4997 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 4998 4999 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 5000 u16 offset, u16 size, 5001 enum mlxsw_reg_rtar_key_type table_id, 5002 u16 dest_offset) 5003 { 5004 MLXSW_REG_ZERO(rrcr, payload); 5005 mlxsw_reg_rrcr_op_set(payload, op); 5006 mlxsw_reg_rrcr_offset_set(payload, offset); 5007 mlxsw_reg_rrcr_size_set(payload, size); 5008 mlxsw_reg_rrcr_table_id_set(payload, table_id); 5009 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 5010 } 5011 5012 /* RALTA - Router Algorithmic LPM Tree Allocation Register 5013 * ------------------------------------------------------- 5014 * RALTA is used to allocate the LPM trees of the SHSPM method. 5015 */ 5016 #define MLXSW_REG_RALTA_ID 0x8010 5017 #define MLXSW_REG_RALTA_LEN 0x04 5018 5019 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 5020 5021 /* reg_ralta_op 5022 * opcode (valid for Write, must be 0 on Read) 5023 * 0 - allocate a tree 5024 * 1 - deallocate a tree 5025 * Access: OP 5026 */ 5027 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 5028 5029 enum mlxsw_reg_ralxx_protocol { 5030 MLXSW_REG_RALXX_PROTOCOL_IPV4, 5031 MLXSW_REG_RALXX_PROTOCOL_IPV6, 5032 }; 5033 5034 /* reg_ralta_protocol 5035 * Protocol. 5036 * Deallocation opcode: Reserved. 5037 * Access: RW 5038 */ 5039 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 5040 5041 /* reg_ralta_tree_id 5042 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 5043 * the tree identifier (managed by software). 5044 * Note that tree_id 0 is allocated for a default-route tree. 5045 * Access: Index 5046 */ 5047 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 5048 5049 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 5050 enum mlxsw_reg_ralxx_protocol protocol, 5051 u8 tree_id) 5052 { 5053 MLXSW_REG_ZERO(ralta, payload); 5054 mlxsw_reg_ralta_op_set(payload, !alloc); 5055 mlxsw_reg_ralta_protocol_set(payload, protocol); 5056 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 5057 } 5058 5059 /* RALST - Router Algorithmic LPM Structure Tree Register 5060 * ------------------------------------------------------ 5061 * RALST is used to set and query the structure of an LPM tree. 5062 * The structure of the tree must be sorted as a sorted binary tree, while 5063 * each node is a bin that is tagged as the length of the prefixes the lookup 5064 * will refer to. Therefore, bin X refers to a set of entries with prefixes 5065 * of X bits to match with the destination address. The bin 0 indicates 5066 * the default action, when there is no match of any prefix. 5067 */ 5068 #define MLXSW_REG_RALST_ID 0x8011 5069 #define MLXSW_REG_RALST_LEN 0x104 5070 5071 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 5072 5073 /* reg_ralst_root_bin 5074 * The bin number of the root bin. 5075 * 0<root_bin=<(length of IP address) 5076 * For a default-route tree configure 0xff 5077 * Access: RW 5078 */ 5079 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 5080 5081 /* reg_ralst_tree_id 5082 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5083 * Access: Index 5084 */ 5085 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 5086 5087 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 5088 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 5089 #define MLXSW_REG_RALST_BIN_COUNT 128 5090 5091 /* reg_ralst_left_child_bin 5092 * Holding the children of the bin according to the stored tree's structure. 5093 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5094 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5095 * Access: RW 5096 */ 5097 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 5098 5099 /* reg_ralst_right_child_bin 5100 * Holding the children of the bin according to the stored tree's structure. 5101 * For trees composed of less than 4 blocks, the bins in excess are reserved. 5102 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 5103 * Access: RW 5104 */ 5105 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 5106 false); 5107 5108 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 5109 { 5110 MLXSW_REG_ZERO(ralst, payload); 5111 5112 /* Initialize all bins to have no left or right child */ 5113 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 5114 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 5115 5116 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 5117 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 5118 } 5119 5120 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 5121 u8 left_child_bin, 5122 u8 right_child_bin) 5123 { 5124 int bin_index = bin_number - 1; 5125 5126 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 5127 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 5128 right_child_bin); 5129 } 5130 5131 /* RALTB - Router Algorithmic LPM Tree Binding Register 5132 * ---------------------------------------------------- 5133 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 5134 */ 5135 #define MLXSW_REG_RALTB_ID 0x8012 5136 #define MLXSW_REG_RALTB_LEN 0x04 5137 5138 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 5139 5140 /* reg_raltb_virtual_router 5141 * Virtual Router ID 5142 * Range is 0..cap_max_virtual_routers-1 5143 * Access: Index 5144 */ 5145 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 5146 5147 /* reg_raltb_protocol 5148 * Protocol. 5149 * Access: Index 5150 */ 5151 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 5152 5153 /* reg_raltb_tree_id 5154 * Tree to be used for the {virtual_router, protocol} 5155 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 5156 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 5157 * Access: RW 5158 */ 5159 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 5160 5161 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 5162 enum mlxsw_reg_ralxx_protocol protocol, 5163 u8 tree_id) 5164 { 5165 MLXSW_REG_ZERO(raltb, payload); 5166 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 5167 mlxsw_reg_raltb_protocol_set(payload, protocol); 5168 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 5169 } 5170 5171 /* RALUE - Router Algorithmic LPM Unicast Entry Register 5172 * ----------------------------------------------------- 5173 * RALUE is used to configure and query LPM entries that serve 5174 * the Unicast protocols. 5175 */ 5176 #define MLXSW_REG_RALUE_ID 0x8013 5177 #define MLXSW_REG_RALUE_LEN 0x38 5178 5179 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 5180 5181 /* reg_ralue_protocol 5182 * Protocol. 5183 * Access: Index 5184 */ 5185 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 5186 5187 enum mlxsw_reg_ralue_op { 5188 /* Read operation. If entry doesn't exist, the operation fails. */ 5189 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 5190 /* Clear on read operation. Used to read entry and 5191 * clear Activity bit. 5192 */ 5193 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 5194 /* Write operation. Used to write a new entry to the table. All RW 5195 * fields are written for new entry. Activity bit is set 5196 * for new entries. 5197 */ 5198 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 5199 /* Update operation. Used to update an existing route entry and 5200 * only update the RW fields that are detailed in the field 5201 * op_u_mask. If entry doesn't exist, the operation fails. 5202 */ 5203 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 5204 /* Clear activity. The Activity bit (the field a) is cleared 5205 * for the entry. 5206 */ 5207 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 5208 /* Delete operation. Used to delete an existing entry. If entry 5209 * doesn't exist, the operation fails. 5210 */ 5211 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 5212 }; 5213 5214 /* reg_ralue_op 5215 * Operation. 5216 * Access: OP 5217 */ 5218 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 5219 5220 /* reg_ralue_a 5221 * Activity. Set for new entries. Set if a packet lookup has hit on the 5222 * specific entry, only if the entry is a route. To clear the a bit, use 5223 * "clear activity" op. 5224 * Enabled by activity_dis in RGCR 5225 * Access: RO 5226 */ 5227 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 5228 5229 /* reg_ralue_virtual_router 5230 * Virtual Router ID 5231 * Range is 0..cap_max_virtual_routers-1 5232 * Access: Index 5233 */ 5234 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 5235 5236 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 5237 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 5238 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 5239 5240 /* reg_ralue_op_u_mask 5241 * opcode update mask. 5242 * On read operation, this field is reserved. 5243 * This field is valid for update opcode, otherwise - reserved. 5244 * This field is a bitmask of the fields that should be updated. 5245 * Access: WO 5246 */ 5247 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 5248 5249 /* reg_ralue_prefix_len 5250 * Number of bits in the prefix of the LPM route. 5251 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 5252 * two entries in the physical HW table. 5253 * Access: Index 5254 */ 5255 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 5256 5257 /* reg_ralue_dip* 5258 * The prefix of the route or of the marker that the object of the LPM 5259 * is compared with. The most significant bits of the dip are the prefix. 5260 * The least significant bits must be '0' if the prefix_len is smaller 5261 * than 128 for IPv6 or smaller than 32 for IPv4. 5262 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 5263 * Access: Index 5264 */ 5265 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 5266 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 5267 5268 enum mlxsw_reg_ralue_entry_type { 5269 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 5270 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 5271 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 5272 }; 5273 5274 /* reg_ralue_entry_type 5275 * Entry type. 5276 * Note - for Marker entries, the action_type and action fields are reserved. 5277 * Access: RW 5278 */ 5279 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 5280 5281 /* reg_ralue_bmp_len 5282 * The best match prefix length in the case that there is no match for 5283 * longer prefixes. 5284 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 5285 * Note for any update operation with entry_type modification this 5286 * field must be set. 5287 * Access: RW 5288 */ 5289 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 5290 5291 enum mlxsw_reg_ralue_action_type { 5292 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 5293 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 5294 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 5295 }; 5296 5297 /* reg_ralue_action_type 5298 * Action Type 5299 * Indicates how the IP address is connected. 5300 * It can be connected to a local subnet through local_erif or can be 5301 * on a remote subnet connected through a next-hop router, 5302 * or transmitted to the CPU. 5303 * Reserved when entry_type = MARKER_ENTRY 5304 * Access: RW 5305 */ 5306 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 5307 5308 enum mlxsw_reg_ralue_trap_action { 5309 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 5310 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 5311 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 5312 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 5313 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 5314 }; 5315 5316 /* reg_ralue_trap_action 5317 * Trap action. 5318 * For IP2ME action, only NOP and MIRROR are possible. 5319 * Access: RW 5320 */ 5321 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 5322 5323 /* reg_ralue_trap_id 5324 * Trap ID to be reported to CPU. 5325 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 5326 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 5327 * Access: RW 5328 */ 5329 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 5330 5331 /* reg_ralue_adjacency_index 5332 * Points to the first entry of the group-based ECMP. 5333 * Only relevant in case of REMOTE action. 5334 * Access: RW 5335 */ 5336 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 5337 5338 /* reg_ralue_ecmp_size 5339 * Amount of sequential entries starting 5340 * from the adjacency_index (the number of ECMPs). 5341 * The valid range is 1-64, 512, 1024, 2048 and 4096. 5342 * Reserved when trap_action is TRAP or DISCARD_ERROR. 5343 * Only relevant in case of REMOTE action. 5344 * Access: RW 5345 */ 5346 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 5347 5348 /* reg_ralue_local_erif 5349 * Egress Router Interface. 5350 * Only relevant in case of LOCAL action. 5351 * Access: RW 5352 */ 5353 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 5354 5355 /* reg_ralue_ip2me_v 5356 * Valid bit for the tunnel_ptr field. 5357 * If valid = 0 then trap to CPU as IP2ME trap ID. 5358 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 5359 * decapsulation then tunnel decapsulation is done. 5360 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 5361 * decapsulation then trap as IP2ME trap ID. 5362 * Only relevant in case of IP2ME action. 5363 * Access: RW 5364 */ 5365 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 5366 5367 /* reg_ralue_ip2me_tunnel_ptr 5368 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 5369 * For Spectrum, pointer to KVD Linear. 5370 * Only relevant in case of IP2ME action. 5371 * Access: RW 5372 */ 5373 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 5374 5375 static inline void mlxsw_reg_ralue_pack(char *payload, 5376 enum mlxsw_reg_ralxx_protocol protocol, 5377 enum mlxsw_reg_ralue_op op, 5378 u16 virtual_router, u8 prefix_len) 5379 { 5380 MLXSW_REG_ZERO(ralue, payload); 5381 mlxsw_reg_ralue_protocol_set(payload, protocol); 5382 mlxsw_reg_ralue_op_set(payload, op); 5383 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 5384 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 5385 mlxsw_reg_ralue_entry_type_set(payload, 5386 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 5387 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 5388 } 5389 5390 static inline void mlxsw_reg_ralue_pack4(char *payload, 5391 enum mlxsw_reg_ralxx_protocol protocol, 5392 enum mlxsw_reg_ralue_op op, 5393 u16 virtual_router, u8 prefix_len, 5394 u32 dip) 5395 { 5396 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5397 mlxsw_reg_ralue_dip4_set(payload, dip); 5398 } 5399 5400 static inline void mlxsw_reg_ralue_pack6(char *payload, 5401 enum mlxsw_reg_ralxx_protocol protocol, 5402 enum mlxsw_reg_ralue_op op, 5403 u16 virtual_router, u8 prefix_len, 5404 const void *dip) 5405 { 5406 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5407 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 5408 } 5409 5410 static inline void 5411 mlxsw_reg_ralue_act_remote_pack(char *payload, 5412 enum mlxsw_reg_ralue_trap_action trap_action, 5413 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 5414 { 5415 mlxsw_reg_ralue_action_type_set(payload, 5416 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 5417 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5418 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5419 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 5420 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 5421 } 5422 5423 static inline void 5424 mlxsw_reg_ralue_act_local_pack(char *payload, 5425 enum mlxsw_reg_ralue_trap_action trap_action, 5426 u16 trap_id, u16 local_erif) 5427 { 5428 mlxsw_reg_ralue_action_type_set(payload, 5429 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 5430 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5431 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5432 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 5433 } 5434 5435 static inline void 5436 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 5437 { 5438 mlxsw_reg_ralue_action_type_set(payload, 5439 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5440 } 5441 5442 static inline void 5443 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 5444 { 5445 mlxsw_reg_ralue_action_type_set(payload, 5446 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5447 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 5448 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 5449 } 5450 5451 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 5452 * ---------------------------------------------------------- 5453 * The RAUHT register is used to configure and query the Unicast Host table in 5454 * devices that implement the Algorithmic LPM. 5455 */ 5456 #define MLXSW_REG_RAUHT_ID 0x8014 5457 #define MLXSW_REG_RAUHT_LEN 0x74 5458 5459 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 5460 5461 enum mlxsw_reg_rauht_type { 5462 MLXSW_REG_RAUHT_TYPE_IPV4, 5463 MLXSW_REG_RAUHT_TYPE_IPV6, 5464 }; 5465 5466 /* reg_rauht_type 5467 * Access: Index 5468 */ 5469 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 5470 5471 enum mlxsw_reg_rauht_op { 5472 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 5473 /* Read operation */ 5474 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 5475 /* Clear on read operation. Used to read entry and clear 5476 * activity bit. 5477 */ 5478 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 5479 /* Add. Used to write a new entry to the table. All R/W fields are 5480 * relevant for new entry. Activity bit is set for new entries. 5481 */ 5482 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 5483 /* Update action. Used to update an existing route entry and 5484 * only update the following fields: 5485 * trap_action, trap_id, mac, counter_set_type, counter_index 5486 */ 5487 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 5488 /* Clear activity. A bit is cleared for the entry. */ 5489 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 5490 /* Delete entry */ 5491 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 5492 /* Delete all host entries on a RIF. In this command, dip 5493 * field is reserved. 5494 */ 5495 }; 5496 5497 /* reg_rauht_op 5498 * Access: OP 5499 */ 5500 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 5501 5502 /* reg_rauht_a 5503 * Activity. Set for new entries. Set if a packet lookup has hit on 5504 * the specific entry. 5505 * To clear the a bit, use "clear activity" op. 5506 * Enabled by activity_dis in RGCR 5507 * Access: RO 5508 */ 5509 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 5510 5511 /* reg_rauht_rif 5512 * Router Interface 5513 * Access: Index 5514 */ 5515 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 5516 5517 /* reg_rauht_dip* 5518 * Destination address. 5519 * Access: Index 5520 */ 5521 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 5522 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 5523 5524 enum mlxsw_reg_rauht_trap_action { 5525 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 5526 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 5527 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 5528 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 5529 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 5530 }; 5531 5532 /* reg_rauht_trap_action 5533 * Access: RW 5534 */ 5535 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 5536 5537 enum mlxsw_reg_rauht_trap_id { 5538 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 5539 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 5540 }; 5541 5542 /* reg_rauht_trap_id 5543 * Trap ID to be reported to CPU. 5544 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5545 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 5546 * trap_id is reserved. 5547 * Access: RW 5548 */ 5549 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 5550 5551 /* reg_rauht_counter_set_type 5552 * Counter set type for flow counters 5553 * Access: RW 5554 */ 5555 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 5556 5557 /* reg_rauht_counter_index 5558 * Counter index for flow counters 5559 * Access: RW 5560 */ 5561 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 5562 5563 /* reg_rauht_mac 5564 * MAC address. 5565 * Access: RW 5566 */ 5567 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 5568 5569 static inline void mlxsw_reg_rauht_pack(char *payload, 5570 enum mlxsw_reg_rauht_op op, u16 rif, 5571 const char *mac) 5572 { 5573 MLXSW_REG_ZERO(rauht, payload); 5574 mlxsw_reg_rauht_op_set(payload, op); 5575 mlxsw_reg_rauht_rif_set(payload, rif); 5576 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 5577 } 5578 5579 static inline void mlxsw_reg_rauht_pack4(char *payload, 5580 enum mlxsw_reg_rauht_op op, u16 rif, 5581 const char *mac, u32 dip) 5582 { 5583 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5584 mlxsw_reg_rauht_dip4_set(payload, dip); 5585 } 5586 5587 static inline void mlxsw_reg_rauht_pack6(char *payload, 5588 enum mlxsw_reg_rauht_op op, u16 rif, 5589 const char *mac, const char *dip) 5590 { 5591 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5592 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 5593 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 5594 } 5595 5596 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 5597 u64 counter_index) 5598 { 5599 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 5600 mlxsw_reg_rauht_counter_set_type_set(payload, 5601 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 5602 } 5603 5604 /* RALEU - Router Algorithmic LPM ECMP Update Register 5605 * --------------------------------------------------- 5606 * The register enables updating the ECMP section in the action for multiple 5607 * LPM Unicast entries in a single operation. The update is executed to 5608 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 5609 */ 5610 #define MLXSW_REG_RALEU_ID 0x8015 5611 #define MLXSW_REG_RALEU_LEN 0x28 5612 5613 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 5614 5615 /* reg_raleu_protocol 5616 * Protocol. 5617 * Access: Index 5618 */ 5619 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 5620 5621 /* reg_raleu_virtual_router 5622 * Virtual Router ID 5623 * Range is 0..cap_max_virtual_routers-1 5624 * Access: Index 5625 */ 5626 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 5627 5628 /* reg_raleu_adjacency_index 5629 * Adjacency Index used for matching on the existing entries. 5630 * Access: Index 5631 */ 5632 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 5633 5634 /* reg_raleu_ecmp_size 5635 * ECMP Size used for matching on the existing entries. 5636 * Access: Index 5637 */ 5638 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 5639 5640 /* reg_raleu_new_adjacency_index 5641 * New Adjacency Index. 5642 * Access: WO 5643 */ 5644 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 5645 5646 /* reg_raleu_new_ecmp_size 5647 * New ECMP Size. 5648 * Access: WO 5649 */ 5650 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 5651 5652 static inline void mlxsw_reg_raleu_pack(char *payload, 5653 enum mlxsw_reg_ralxx_protocol protocol, 5654 u16 virtual_router, 5655 u32 adjacency_index, u16 ecmp_size, 5656 u32 new_adjacency_index, 5657 u16 new_ecmp_size) 5658 { 5659 MLXSW_REG_ZERO(raleu, payload); 5660 mlxsw_reg_raleu_protocol_set(payload, protocol); 5661 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 5662 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 5663 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 5664 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 5665 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 5666 } 5667 5668 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 5669 * ---------------------------------------------------------------- 5670 * The RAUHTD register allows dumping entries from the Router Unicast Host 5671 * Table. For a given session an entry is dumped no more than one time. The 5672 * first RAUHTD access after reset is a new session. A session ends when the 5673 * num_rec response is smaller than num_rec request or for IPv4 when the 5674 * num_entries is smaller than 4. The clear activity affect the current session 5675 * or the last session if a new session has not started. 5676 */ 5677 #define MLXSW_REG_RAUHTD_ID 0x8018 5678 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 5679 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 5680 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 5681 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 5682 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 5683 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 5684 5685 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 5686 5687 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 5688 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 5689 5690 /* reg_rauhtd_filter_fields 5691 * if a bit is '0' then the relevant field is ignored and dump is done 5692 * regardless of the field value 5693 * Bit0 - filter by activity: entry_a 5694 * Bit3 - filter by entry rip: entry_rif 5695 * Access: Index 5696 */ 5697 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 5698 5699 enum mlxsw_reg_rauhtd_op { 5700 MLXSW_REG_RAUHTD_OP_DUMP, 5701 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 5702 }; 5703 5704 /* reg_rauhtd_op 5705 * Access: OP 5706 */ 5707 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 5708 5709 /* reg_rauhtd_num_rec 5710 * At request: number of records requested 5711 * At response: number of records dumped 5712 * For IPv4, each record has 4 entries at request and up to 4 entries 5713 * at response 5714 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 5715 * Access: Index 5716 */ 5717 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 5718 5719 /* reg_rauhtd_entry_a 5720 * Dump only if activity has value of entry_a 5721 * Reserved if filter_fields bit0 is '0' 5722 * Access: Index 5723 */ 5724 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 5725 5726 enum mlxsw_reg_rauhtd_type { 5727 MLXSW_REG_RAUHTD_TYPE_IPV4, 5728 MLXSW_REG_RAUHTD_TYPE_IPV6, 5729 }; 5730 5731 /* reg_rauhtd_type 5732 * Dump only if record type is: 5733 * 0 - IPv4 5734 * 1 - IPv6 5735 * Access: Index 5736 */ 5737 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 5738 5739 /* reg_rauhtd_entry_rif 5740 * Dump only if RIF has value of entry_rif 5741 * Reserved if filter_fields bit3 is '0' 5742 * Access: Index 5743 */ 5744 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 5745 5746 static inline void mlxsw_reg_rauhtd_pack(char *payload, 5747 enum mlxsw_reg_rauhtd_type type) 5748 { 5749 MLXSW_REG_ZERO(rauhtd, payload); 5750 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 5751 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 5752 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 5753 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 5754 mlxsw_reg_rauhtd_type_set(payload, type); 5755 } 5756 5757 /* reg_rauhtd_ipv4_rec_num_entries 5758 * Number of valid entries in this record: 5759 * 0 - 1 valid entry 5760 * 1 - 2 valid entries 5761 * 2 - 3 valid entries 5762 * 3 - 4 valid entries 5763 * Access: RO 5764 */ 5765 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 5766 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 5767 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5768 5769 /* reg_rauhtd_rec_type 5770 * Record type. 5771 * 0 - IPv4 5772 * 1 - IPv6 5773 * Access: RO 5774 */ 5775 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 5776 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5777 5778 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 5779 5780 /* reg_rauhtd_ipv4_ent_a 5781 * Activity. Set for new entries. Set if a packet lookup has hit on the 5782 * specific entry. 5783 * Access: RO 5784 */ 5785 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5786 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5787 5788 /* reg_rauhtd_ipv4_ent_rif 5789 * Router interface. 5790 * Access: RO 5791 */ 5792 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5793 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5794 5795 /* reg_rauhtd_ipv4_ent_dip 5796 * Destination IPv4 address. 5797 * Access: RO 5798 */ 5799 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5800 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 5801 5802 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 5803 5804 /* reg_rauhtd_ipv6_ent_a 5805 * Activity. Set for new entries. Set if a packet lookup has hit on the 5806 * specific entry. 5807 * Access: RO 5808 */ 5809 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5810 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5811 5812 /* reg_rauhtd_ipv6_ent_rif 5813 * Router interface. 5814 * Access: RO 5815 */ 5816 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5817 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5818 5819 /* reg_rauhtd_ipv6_ent_dip 5820 * Destination IPv6 address. 5821 * Access: RO 5822 */ 5823 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 5824 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 5825 5826 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 5827 int ent_index, u16 *p_rif, 5828 u32 *p_dip) 5829 { 5830 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 5831 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 5832 } 5833 5834 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 5835 int rec_index, u16 *p_rif, 5836 char *p_dip) 5837 { 5838 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 5839 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 5840 } 5841 5842 /* RTDP - Routing Tunnel Decap Properties Register 5843 * ----------------------------------------------- 5844 * The RTDP register is used for configuring the tunnel decap properties of NVE 5845 * and IPinIP. 5846 */ 5847 #define MLXSW_REG_RTDP_ID 0x8020 5848 #define MLXSW_REG_RTDP_LEN 0x44 5849 5850 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 5851 5852 enum mlxsw_reg_rtdp_type { 5853 MLXSW_REG_RTDP_TYPE_NVE, 5854 MLXSW_REG_RTDP_TYPE_IPIP, 5855 }; 5856 5857 /* reg_rtdp_type 5858 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 5859 * Access: RW 5860 */ 5861 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 5862 5863 /* reg_rtdp_tunnel_index 5864 * Index to the Decap entry. 5865 * For Spectrum, Index to KVD Linear. 5866 * Access: Index 5867 */ 5868 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 5869 5870 /* IPinIP */ 5871 5872 /* reg_rtdp_ipip_irif 5873 * Ingress Router Interface for the overlay router 5874 * Access: RW 5875 */ 5876 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 5877 5878 enum mlxsw_reg_rtdp_ipip_sip_check { 5879 /* No sip checks. */ 5880 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 5881 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 5882 * equal ipv4_usip. 5883 */ 5884 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 5885 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 5886 * equal ipv6_usip. 5887 */ 5888 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 5889 }; 5890 5891 /* reg_rtdp_ipip_sip_check 5892 * SIP check to perform. If decapsulation failed due to these configurations 5893 * then trap_id is IPIP_DECAP_ERROR. 5894 * Access: RW 5895 */ 5896 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 5897 5898 /* If set, allow decapsulation of IPinIP (without GRE). */ 5899 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 5900 /* If set, allow decapsulation of IPinGREinIP without a key. */ 5901 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 5902 /* If set, allow decapsulation of IPinGREinIP with a key. */ 5903 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 5904 5905 /* reg_rtdp_ipip_type_check 5906 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 5907 * these configurations then trap_id is IPIP_DECAP_ERROR. 5908 * Access: RW 5909 */ 5910 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 5911 5912 /* reg_rtdp_ipip_gre_key_check 5913 * Whether GRE key should be checked. When check is enabled: 5914 * - A packet received as IPinIP (without GRE) will always pass. 5915 * - A packet received as IPinGREinIP without a key will not pass the check. 5916 * - A packet received as IPinGREinIP with a key will pass the check only if the 5917 * key in the packet is equal to expected_gre_key. 5918 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 5919 * Access: RW 5920 */ 5921 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 5922 5923 /* reg_rtdp_ipip_ipv4_usip 5924 * Underlay IPv4 address for ipv4 source address check. 5925 * Reserved when sip_check is not '1'. 5926 * Access: RW 5927 */ 5928 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 5929 5930 /* reg_rtdp_ipip_ipv6_usip_ptr 5931 * This field is valid when sip_check is "sipv6 check explicitly". This is a 5932 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 5933 * is to the KVD linear. 5934 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 5935 * Access: RW 5936 */ 5937 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 5938 5939 /* reg_rtdp_ipip_expected_gre_key 5940 * GRE key for checking. 5941 * Reserved when gre_key_check is '0'. 5942 * Access: RW 5943 */ 5944 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 5945 5946 static inline void mlxsw_reg_rtdp_pack(char *payload, 5947 enum mlxsw_reg_rtdp_type type, 5948 u32 tunnel_index) 5949 { 5950 MLXSW_REG_ZERO(rtdp, payload); 5951 mlxsw_reg_rtdp_type_set(payload, type); 5952 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 5953 } 5954 5955 static inline void 5956 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 5957 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 5958 unsigned int type_check, bool gre_key_check, 5959 u32 ipv4_usip, u32 expected_gre_key) 5960 { 5961 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 5962 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 5963 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 5964 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 5965 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 5966 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 5967 } 5968 5969 /* RIGR-V2 - Router Interface Group Register Version 2 5970 * --------------------------------------------------- 5971 * The RIGR_V2 register is used to add, remove and query egress interface list 5972 * of a multicast forwarding entry. 5973 */ 5974 #define MLXSW_REG_RIGR2_ID 0x8023 5975 #define MLXSW_REG_RIGR2_LEN 0xB0 5976 5977 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 5978 5979 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 5980 5981 /* reg_rigr2_rigr_index 5982 * KVD Linear index. 5983 * Access: Index 5984 */ 5985 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 5986 5987 /* reg_rigr2_vnext 5988 * Next RIGR Index is valid. 5989 * Access: RW 5990 */ 5991 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 5992 5993 /* reg_rigr2_next_rigr_index 5994 * Next RIGR Index. The index is to the KVD linear. 5995 * Reserved when vnxet = '0'. 5996 * Access: RW 5997 */ 5998 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 5999 6000 /* reg_rigr2_vrmid 6001 * RMID Index is valid. 6002 * Access: RW 6003 */ 6004 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 6005 6006 /* reg_rigr2_rmid_index 6007 * RMID Index. 6008 * Range 0 .. max_mid - 1 6009 * Reserved when vrmid = '0'. 6010 * The index is to the Port Group Table (PGT) 6011 * Access: RW 6012 */ 6013 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 6014 6015 /* reg_rigr2_erif_entry_v 6016 * Egress Router Interface is valid. 6017 * Note that low-entries must be set if high-entries are set. For 6018 * example: if erif_entry[2].v is set then erif_entry[1].v and 6019 * erif_entry[0].v must be set. 6020 * Index can be from 0 to cap_mc_erif_list_entries-1 6021 * Access: RW 6022 */ 6023 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 6024 6025 /* reg_rigr2_erif_entry_erif 6026 * Egress Router Interface. 6027 * Valid range is from 0 to cap_max_router_interfaces - 1 6028 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 6029 * Access: RW 6030 */ 6031 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 6032 6033 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 6034 bool vnext, u32 next_rigr_index) 6035 { 6036 MLXSW_REG_ZERO(rigr2, payload); 6037 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 6038 mlxsw_reg_rigr2_vnext_set(payload, vnext); 6039 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 6040 mlxsw_reg_rigr2_vrmid_set(payload, 0); 6041 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 6042 } 6043 6044 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 6045 bool v, u16 erif) 6046 { 6047 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 6048 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 6049 } 6050 6051 /* RECR-V2 - Router ECMP Configuration Version 2 Register 6052 * ------------------------------------------------------ 6053 */ 6054 #define MLXSW_REG_RECR2_ID 0x8025 6055 #define MLXSW_REG_RECR2_LEN 0x38 6056 6057 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 6058 6059 /* reg_recr2_pp 6060 * Per-port configuration 6061 * Access: Index 6062 */ 6063 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 6064 6065 /* reg_recr2_sh 6066 * Symmetric hash 6067 * Access: RW 6068 */ 6069 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 6070 6071 /* reg_recr2_seed 6072 * Seed 6073 * Access: RW 6074 */ 6075 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 6076 6077 enum { 6078 /* Enable IPv4 fields if packet is not TCP and not UDP */ 6079 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 6080 /* Enable IPv4 fields if packet is TCP or UDP */ 6081 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 6082 /* Enable IPv6 fields if packet is not TCP and not UDP */ 6083 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 6084 /* Enable IPv6 fields if packet is TCP or UDP */ 6085 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 6086 /* Enable TCP/UDP header fields if packet is IPv4 */ 6087 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 6088 /* Enable TCP/UDP header fields if packet is IPv6 */ 6089 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 6090 }; 6091 6092 /* reg_recr2_outer_header_enables 6093 * Bit mask where each bit enables a specific layer to be included in 6094 * the hash calculation. 6095 * Access: RW 6096 */ 6097 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 6098 6099 enum { 6100 /* IPv4 Source IP */ 6101 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 6102 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 6103 /* IPv4 Destination IP */ 6104 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 6105 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 6106 /* IP Protocol */ 6107 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 6108 /* IPv6 Source IP */ 6109 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 6110 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 6111 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 6112 /* IPv6 Destination IP */ 6113 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 6114 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 6115 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 6116 /* IPv6 Next Header */ 6117 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 6118 /* IPv6 Flow Label */ 6119 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 6120 /* TCP/UDP Source Port */ 6121 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 6122 /* TCP/UDP Destination Port */ 6123 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 6124 }; 6125 6126 /* reg_recr2_outer_header_fields_enable 6127 * Packet fields to enable for ECMP hash subject to outer_header_enable. 6128 * Access: RW 6129 */ 6130 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 6131 6132 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 6133 { 6134 int i; 6135 6136 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 6137 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6138 true); 6139 } 6140 6141 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 6142 { 6143 int i; 6144 6145 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 6146 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6147 true); 6148 } 6149 6150 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 6151 { 6152 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 6153 6154 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6155 6156 i = MLXSW_REG_RECR2_IPV6_SIP8; 6157 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 6158 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6159 true); 6160 } 6161 6162 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 6163 { 6164 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 6165 6166 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 6167 6168 i = MLXSW_REG_RECR2_IPV6_DIP8; 6169 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 6170 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 6171 true); 6172 } 6173 6174 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 6175 { 6176 MLXSW_REG_ZERO(recr2, payload); 6177 mlxsw_reg_recr2_pp_set(payload, false); 6178 mlxsw_reg_recr2_sh_set(payload, true); 6179 mlxsw_reg_recr2_seed_set(payload, seed); 6180 } 6181 6182 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 6183 * -------------------------------------------------------------- 6184 * The RMFT_V2 register is used to configure and query the multicast table. 6185 */ 6186 #define MLXSW_REG_RMFT2_ID 0x8027 6187 #define MLXSW_REG_RMFT2_LEN 0x174 6188 6189 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 6190 6191 /* reg_rmft2_v 6192 * Valid 6193 * Access: RW 6194 */ 6195 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 6196 6197 enum mlxsw_reg_rmft2_type { 6198 MLXSW_REG_RMFT2_TYPE_IPV4, 6199 MLXSW_REG_RMFT2_TYPE_IPV6 6200 }; 6201 6202 /* reg_rmft2_type 6203 * Access: Index 6204 */ 6205 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 6206 6207 enum mlxsw_sp_reg_rmft2_op { 6208 /* For Write: 6209 * Write operation. Used to write a new entry to the table. All RW 6210 * fields are relevant for new entry. Activity bit is set for new 6211 * entries - Note write with v (Valid) 0 will delete the entry. 6212 * For Query: 6213 * Read operation 6214 */ 6215 MLXSW_REG_RMFT2_OP_READ_WRITE, 6216 }; 6217 6218 /* reg_rmft2_op 6219 * Operation. 6220 * Access: OP 6221 */ 6222 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 6223 6224 /* reg_rmft2_a 6225 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 6226 * entry. 6227 * Access: RO 6228 */ 6229 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 6230 6231 /* reg_rmft2_offset 6232 * Offset within the multicast forwarding table to write to. 6233 * Access: Index 6234 */ 6235 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 6236 6237 /* reg_rmft2_virtual_router 6238 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 6239 * Access: RW 6240 */ 6241 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 6242 6243 enum mlxsw_reg_rmft2_irif_mask { 6244 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 6245 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 6246 }; 6247 6248 /* reg_rmft2_irif_mask 6249 * Ingress RIF mask. 6250 * Access: RW 6251 */ 6252 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 6253 6254 /* reg_rmft2_irif 6255 * Ingress RIF index. 6256 * Access: RW 6257 */ 6258 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 6259 6260 /* reg_rmft2_dip4 6261 * Destination IPv4 address 6262 * Access: RW 6263 */ 6264 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 6265 6266 /* reg_rmft2_dip4_mask 6267 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6268 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6269 * Access: RW 6270 */ 6271 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 6272 6273 /* reg_rmft2_sip4 6274 * Source IPv4 address 6275 * Access: RW 6276 */ 6277 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 6278 6279 /* reg_rmft2_sip4_mask 6280 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 6281 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 6282 * Access: RW 6283 */ 6284 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 6285 6286 /* reg_rmft2_flexible_action_set 6287 * ACL action set. The only supported action types in this field and in any 6288 * action-set pointed from here are as follows: 6289 * 00h: ACTION_NULL 6290 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 6291 * 03h: ACTION_TRAP 6292 * 06h: ACTION_QOS 6293 * 08h: ACTION_POLICING_MONITORING 6294 * 10h: ACTION_ROUTER_MC 6295 * Access: RW 6296 */ 6297 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 6298 MLXSW_REG_FLEX_ACTION_SET_LEN); 6299 6300 static inline void 6301 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 6302 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 6303 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 6304 const char *flexible_action_set) 6305 { 6306 MLXSW_REG_ZERO(rmft2, payload); 6307 mlxsw_reg_rmft2_v_set(payload, v); 6308 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 6309 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 6310 mlxsw_reg_rmft2_offset_set(payload, offset); 6311 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 6312 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 6313 mlxsw_reg_rmft2_irif_set(payload, irif); 6314 mlxsw_reg_rmft2_dip4_set(payload, dip4); 6315 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 6316 mlxsw_reg_rmft2_sip4_set(payload, sip4); 6317 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 6318 if (flexible_action_set) 6319 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 6320 flexible_action_set); 6321 } 6322 6323 /* MFCR - Management Fan Control Register 6324 * -------------------------------------- 6325 * This register controls the settings of the Fan Speed PWM mechanism. 6326 */ 6327 #define MLXSW_REG_MFCR_ID 0x9001 6328 #define MLXSW_REG_MFCR_LEN 0x08 6329 6330 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 6331 6332 enum mlxsw_reg_mfcr_pwm_frequency { 6333 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 6334 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 6335 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 6336 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 6337 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 6338 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 6339 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 6340 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 6341 }; 6342 6343 /* reg_mfcr_pwm_frequency 6344 * Controls the frequency of the PWM signal. 6345 * Access: RW 6346 */ 6347 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 6348 6349 #define MLXSW_MFCR_TACHOS_MAX 10 6350 6351 /* reg_mfcr_tacho_active 6352 * Indicates which of the tachometer is active (bit per tachometer). 6353 * Access: RO 6354 */ 6355 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 6356 6357 #define MLXSW_MFCR_PWMS_MAX 5 6358 6359 /* reg_mfcr_pwm_active 6360 * Indicates which of the PWM control is active (bit per PWM). 6361 * Access: RO 6362 */ 6363 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 6364 6365 static inline void 6366 mlxsw_reg_mfcr_pack(char *payload, 6367 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 6368 { 6369 MLXSW_REG_ZERO(mfcr, payload); 6370 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 6371 } 6372 6373 static inline void 6374 mlxsw_reg_mfcr_unpack(char *payload, 6375 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 6376 u16 *p_tacho_active, u8 *p_pwm_active) 6377 { 6378 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 6379 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 6380 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 6381 } 6382 6383 /* MFSC - Management Fan Speed Control Register 6384 * -------------------------------------------- 6385 * This register controls the settings of the Fan Speed PWM mechanism. 6386 */ 6387 #define MLXSW_REG_MFSC_ID 0x9002 6388 #define MLXSW_REG_MFSC_LEN 0x08 6389 6390 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 6391 6392 /* reg_mfsc_pwm 6393 * Fan pwm to control / monitor. 6394 * Access: Index 6395 */ 6396 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 6397 6398 /* reg_mfsc_pwm_duty_cycle 6399 * Controls the duty cycle of the PWM. Value range from 0..255 to 6400 * represent duty cycle of 0%...100%. 6401 * Access: RW 6402 */ 6403 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 6404 6405 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 6406 u8 pwm_duty_cycle) 6407 { 6408 MLXSW_REG_ZERO(mfsc, payload); 6409 mlxsw_reg_mfsc_pwm_set(payload, pwm); 6410 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 6411 } 6412 6413 /* MFSM - Management Fan Speed Measurement 6414 * --------------------------------------- 6415 * This register controls the settings of the Tacho measurements and 6416 * enables reading the Tachometer measurements. 6417 */ 6418 #define MLXSW_REG_MFSM_ID 0x9003 6419 #define MLXSW_REG_MFSM_LEN 0x08 6420 6421 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 6422 6423 /* reg_mfsm_tacho 6424 * Fan tachometer index. 6425 * Access: Index 6426 */ 6427 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 6428 6429 /* reg_mfsm_rpm 6430 * Fan speed (round per minute). 6431 * Access: RO 6432 */ 6433 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 6434 6435 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 6436 { 6437 MLXSW_REG_ZERO(mfsm, payload); 6438 mlxsw_reg_mfsm_tacho_set(payload, tacho); 6439 } 6440 6441 /* MFSL - Management Fan Speed Limit Register 6442 * ------------------------------------------ 6443 * The Fan Speed Limit register is used to configure the fan speed 6444 * event / interrupt notification mechanism. Fan speed threshold are 6445 * defined for both under-speed and over-speed. 6446 */ 6447 #define MLXSW_REG_MFSL_ID 0x9004 6448 #define MLXSW_REG_MFSL_LEN 0x0C 6449 6450 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 6451 6452 /* reg_mfsl_tacho 6453 * Fan tachometer index. 6454 * Access: Index 6455 */ 6456 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 6457 6458 /* reg_mfsl_tach_min 6459 * Tachometer minimum value (minimum RPM). 6460 * Access: RW 6461 */ 6462 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 6463 6464 /* reg_mfsl_tach_max 6465 * Tachometer maximum value (maximum RPM). 6466 * Access: RW 6467 */ 6468 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 6469 6470 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 6471 u16 tach_min, u16 tach_max) 6472 { 6473 MLXSW_REG_ZERO(mfsl, payload); 6474 mlxsw_reg_mfsl_tacho_set(payload, tacho); 6475 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 6476 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 6477 } 6478 6479 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 6480 u16 *p_tach_min, u16 *p_tach_max) 6481 { 6482 if (p_tach_min) 6483 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 6484 6485 if (p_tach_max) 6486 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 6487 } 6488 6489 /* MTCAP - Management Temperature Capabilities 6490 * ------------------------------------------- 6491 * This register exposes the capabilities of the device and 6492 * system temperature sensing. 6493 */ 6494 #define MLXSW_REG_MTCAP_ID 0x9009 6495 #define MLXSW_REG_MTCAP_LEN 0x08 6496 6497 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 6498 6499 /* reg_mtcap_sensor_count 6500 * Number of sensors supported by the device. 6501 * This includes the QSFP module sensors (if exists in the QSFP module). 6502 * Access: RO 6503 */ 6504 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 6505 6506 /* MTMP - Management Temperature 6507 * ----------------------------- 6508 * This register controls the settings of the temperature measurements 6509 * and enables reading the temperature measurements. Note that temperature 6510 * is in 0.125 degrees Celsius. 6511 */ 6512 #define MLXSW_REG_MTMP_ID 0x900A 6513 #define MLXSW_REG_MTMP_LEN 0x20 6514 6515 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 6516 6517 /* reg_mtmp_sensor_index 6518 * Sensors index to access. 6519 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 6520 * (module 0 is mapped to sensor_index 64). 6521 * Access: Index 6522 */ 6523 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 6524 6525 /* Convert to milli degrees Celsius */ 6526 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 6527 6528 /* reg_mtmp_temperature 6529 * Temperature reading from the sensor. Reading is in 0.125 Celsius 6530 * degrees units. 6531 * Access: RO 6532 */ 6533 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 6534 6535 /* reg_mtmp_mte 6536 * Max Temperature Enable - enables measuring the max temperature on a sensor. 6537 * Access: RW 6538 */ 6539 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 6540 6541 /* reg_mtmp_mtr 6542 * Max Temperature Reset - clears the value of the max temperature register. 6543 * Access: WO 6544 */ 6545 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 6546 6547 /* reg_mtmp_max_temperature 6548 * The highest measured temperature from the sensor. 6549 * When the bit mte is cleared, the field max_temperature is reserved. 6550 * Access: RO 6551 */ 6552 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 6553 6554 /* reg_mtmp_tee 6555 * Temperature Event Enable. 6556 * 0 - Do not generate event 6557 * 1 - Generate event 6558 * 2 - Generate single event 6559 * Access: RW 6560 */ 6561 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 6562 6563 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 6564 6565 /* reg_mtmp_temperature_threshold_hi 6566 * High threshold for Temperature Warning Event. In 0.125 Celsius. 6567 * Access: RW 6568 */ 6569 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 6570 6571 /* reg_mtmp_temperature_threshold_lo 6572 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 6573 * Access: RW 6574 */ 6575 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 6576 6577 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 6578 6579 /* reg_mtmp_sensor_name 6580 * Sensor Name 6581 * Access: RO 6582 */ 6583 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 6584 6585 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 6586 bool max_temp_enable, 6587 bool max_temp_reset) 6588 { 6589 MLXSW_REG_ZERO(mtmp, payload); 6590 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 6591 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 6592 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 6593 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 6594 MLXSW_REG_MTMP_THRESH_HI); 6595 } 6596 6597 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 6598 unsigned int *p_max_temp, 6599 char *sensor_name) 6600 { 6601 u16 temp; 6602 6603 if (p_temp) { 6604 temp = mlxsw_reg_mtmp_temperature_get(payload); 6605 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6606 } 6607 if (p_max_temp) { 6608 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 6609 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6610 } 6611 if (sensor_name) 6612 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 6613 } 6614 6615 /* MCIA - Management Cable Info Access 6616 * ----------------------------------- 6617 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 6618 */ 6619 6620 #define MLXSW_REG_MCIA_ID 0x9014 6621 #define MLXSW_REG_MCIA_LEN 0x40 6622 6623 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 6624 6625 /* reg_mcia_l 6626 * Lock bit. Setting this bit will lock the access to the specific 6627 * cable. Used for updating a full page in a cable EPROM. Any access 6628 * other then subsequence writes will fail while the port is locked. 6629 * Access: RW 6630 */ 6631 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 6632 6633 /* reg_mcia_module 6634 * Module number. 6635 * Access: Index 6636 */ 6637 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 6638 6639 /* reg_mcia_status 6640 * Module status. 6641 * Access: RO 6642 */ 6643 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 6644 6645 /* reg_mcia_i2c_device_address 6646 * I2C device address. 6647 * Access: RW 6648 */ 6649 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 6650 6651 /* reg_mcia_page_number 6652 * Page number. 6653 * Access: RW 6654 */ 6655 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 6656 6657 /* reg_mcia_device_address 6658 * Device address. 6659 * Access: RW 6660 */ 6661 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 6662 6663 /* reg_mcia_size 6664 * Number of bytes to read/write (up to 48 bytes). 6665 * Access: RW 6666 */ 6667 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 6668 6669 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 6670 6671 /* reg_mcia_eeprom 6672 * Bytes to read/write. 6673 * Access: RW 6674 */ 6675 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 6676 6677 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 6678 u8 page_number, u16 device_addr, 6679 u8 size, u8 i2c_device_addr) 6680 { 6681 MLXSW_REG_ZERO(mcia, payload); 6682 mlxsw_reg_mcia_module_set(payload, module); 6683 mlxsw_reg_mcia_l_set(payload, lock); 6684 mlxsw_reg_mcia_page_number_set(payload, page_number); 6685 mlxsw_reg_mcia_device_address_set(payload, device_addr); 6686 mlxsw_reg_mcia_size_set(payload, size); 6687 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 6688 } 6689 6690 /* MPAT - Monitoring Port Analyzer Table 6691 * ------------------------------------- 6692 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 6693 * For an enabled analyzer, all fields except e (enable) cannot be modified. 6694 */ 6695 #define MLXSW_REG_MPAT_ID 0x901A 6696 #define MLXSW_REG_MPAT_LEN 0x78 6697 6698 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 6699 6700 /* reg_mpat_pa_id 6701 * Port Analyzer ID. 6702 * Access: Index 6703 */ 6704 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 6705 6706 /* reg_mpat_system_port 6707 * A unique port identifier for the final destination of the packet. 6708 * Access: RW 6709 */ 6710 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 6711 6712 /* reg_mpat_e 6713 * Enable. Indicating the Port Analyzer is enabled. 6714 * Access: RW 6715 */ 6716 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 6717 6718 /* reg_mpat_qos 6719 * Quality Of Service Mode. 6720 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 6721 * PCP, DEI, DSCP or VL) are configured. 6722 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 6723 * same as in the original packet that has triggered the mirroring. For 6724 * SPAN also the pcp,dei are maintained. 6725 * Access: RW 6726 */ 6727 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 6728 6729 /* reg_mpat_be 6730 * Best effort mode. Indicates mirroring traffic should not cause packet 6731 * drop or back pressure, but will discard the mirrored packets. Mirrored 6732 * packets will be forwarded on a best effort manner. 6733 * 0: Do not discard mirrored packets 6734 * 1: Discard mirrored packets if causing congestion 6735 * Access: RW 6736 */ 6737 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 6738 6739 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 6740 u16 system_port, bool e) 6741 { 6742 MLXSW_REG_ZERO(mpat, payload); 6743 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 6744 mlxsw_reg_mpat_system_port_set(payload, system_port); 6745 mlxsw_reg_mpat_e_set(payload, e); 6746 mlxsw_reg_mpat_qos_set(payload, 1); 6747 mlxsw_reg_mpat_be_set(payload, 1); 6748 } 6749 6750 /* MPAR - Monitoring Port Analyzer Register 6751 * ---------------------------------------- 6752 * MPAR register is used to query and configure the port analyzer port mirroring 6753 * properties. 6754 */ 6755 #define MLXSW_REG_MPAR_ID 0x901B 6756 #define MLXSW_REG_MPAR_LEN 0x08 6757 6758 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 6759 6760 /* reg_mpar_local_port 6761 * The local port to mirror the packets from. 6762 * Access: Index 6763 */ 6764 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 6765 6766 enum mlxsw_reg_mpar_i_e { 6767 MLXSW_REG_MPAR_TYPE_EGRESS, 6768 MLXSW_REG_MPAR_TYPE_INGRESS, 6769 }; 6770 6771 /* reg_mpar_i_e 6772 * Ingress/Egress 6773 * Access: Index 6774 */ 6775 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 6776 6777 /* reg_mpar_enable 6778 * Enable mirroring 6779 * By default, port mirroring is disabled for all ports. 6780 * Access: RW 6781 */ 6782 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 6783 6784 /* reg_mpar_pa_id 6785 * Port Analyzer ID. 6786 * Access: RW 6787 */ 6788 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 6789 6790 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 6791 enum mlxsw_reg_mpar_i_e i_e, 6792 bool enable, u8 pa_id) 6793 { 6794 MLXSW_REG_ZERO(mpar, payload); 6795 mlxsw_reg_mpar_local_port_set(payload, local_port); 6796 mlxsw_reg_mpar_enable_set(payload, enable); 6797 mlxsw_reg_mpar_i_e_set(payload, i_e); 6798 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 6799 } 6800 6801 /* MLCR - Management LED Control Register 6802 * -------------------------------------- 6803 * Controls the system LEDs. 6804 */ 6805 #define MLXSW_REG_MLCR_ID 0x902B 6806 #define MLXSW_REG_MLCR_LEN 0x0C 6807 6808 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 6809 6810 /* reg_mlcr_local_port 6811 * Local port number. 6812 * Access: RW 6813 */ 6814 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 6815 6816 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 6817 6818 /* reg_mlcr_beacon_duration 6819 * Duration of the beacon to be active, in seconds. 6820 * 0x0 - Will turn off the beacon. 6821 * 0xFFFF - Will turn on the beacon until explicitly turned off. 6822 * Access: RW 6823 */ 6824 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 6825 6826 /* reg_mlcr_beacon_remain 6827 * Remaining duration of the beacon, in seconds. 6828 * 0xFFFF indicates an infinite amount of time. 6829 * Access: RO 6830 */ 6831 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 6832 6833 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 6834 bool active) 6835 { 6836 MLXSW_REG_ZERO(mlcr, payload); 6837 mlxsw_reg_mlcr_local_port_set(payload, local_port); 6838 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 6839 MLXSW_REG_MLCR_DURATION_MAX : 0); 6840 } 6841 6842 /* MCQI - Management Component Query Information 6843 * --------------------------------------------- 6844 * This register allows querying information about firmware components. 6845 */ 6846 #define MLXSW_REG_MCQI_ID 0x9061 6847 #define MLXSW_REG_MCQI_BASE_LEN 0x18 6848 #define MLXSW_REG_MCQI_CAP_LEN 0x14 6849 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 6850 6851 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 6852 6853 /* reg_mcqi_component_index 6854 * Index of the accessed component. 6855 * Access: Index 6856 */ 6857 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 6858 6859 enum mlxfw_reg_mcqi_info_type { 6860 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 6861 }; 6862 6863 /* reg_mcqi_info_type 6864 * Component properties set. 6865 * Access: RW 6866 */ 6867 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 6868 6869 /* reg_mcqi_offset 6870 * The requested/returned data offset from the section start, given in bytes. 6871 * Must be DWORD aligned. 6872 * Access: RW 6873 */ 6874 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 6875 6876 /* reg_mcqi_data_size 6877 * The requested/returned data size, given in bytes. If data_size is not DWORD 6878 * aligned, the last bytes are zero padded. 6879 * Access: RW 6880 */ 6881 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 6882 6883 /* reg_mcqi_cap_max_component_size 6884 * Maximum size for this component, given in bytes. 6885 * Access: RO 6886 */ 6887 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 6888 6889 /* reg_mcqi_cap_log_mcda_word_size 6890 * Log 2 of the access word size in bytes. Read and write access must be aligned 6891 * to the word size. Write access must be done for an integer number of words. 6892 * Access: RO 6893 */ 6894 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 6895 6896 /* reg_mcqi_cap_mcda_max_write_size 6897 * Maximal write size for MCDA register 6898 * Access: RO 6899 */ 6900 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 6901 6902 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 6903 { 6904 MLXSW_REG_ZERO(mcqi, payload); 6905 mlxsw_reg_mcqi_component_index_set(payload, component_index); 6906 mlxsw_reg_mcqi_info_type_set(payload, 6907 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 6908 mlxsw_reg_mcqi_offset_set(payload, 0); 6909 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 6910 } 6911 6912 static inline void mlxsw_reg_mcqi_unpack(char *payload, 6913 u32 *p_cap_max_component_size, 6914 u8 *p_cap_log_mcda_word_size, 6915 u16 *p_cap_mcda_max_write_size) 6916 { 6917 *p_cap_max_component_size = 6918 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 6919 *p_cap_log_mcda_word_size = 6920 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 6921 *p_cap_mcda_max_write_size = 6922 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 6923 } 6924 6925 /* MCC - Management Component Control 6926 * ---------------------------------- 6927 * Controls the firmware component and updates the FSM. 6928 */ 6929 #define MLXSW_REG_MCC_ID 0x9062 6930 #define MLXSW_REG_MCC_LEN 0x1C 6931 6932 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 6933 6934 enum mlxsw_reg_mcc_instruction { 6935 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 6936 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 6937 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 6938 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 6939 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 6940 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 6941 }; 6942 6943 /* reg_mcc_instruction 6944 * Command to be executed by the FSM. 6945 * Applicable for write operation only. 6946 * Access: RW 6947 */ 6948 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 6949 6950 /* reg_mcc_component_index 6951 * Index of the accessed component. Applicable only for commands that 6952 * refer to components. Otherwise, this field is reserved. 6953 * Access: Index 6954 */ 6955 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 6956 6957 /* reg_mcc_update_handle 6958 * Token representing the current flow executed by the FSM. 6959 * Access: WO 6960 */ 6961 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 6962 6963 /* reg_mcc_error_code 6964 * Indicates the successful completion of the instruction, or the reason it 6965 * failed 6966 * Access: RO 6967 */ 6968 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 6969 6970 /* reg_mcc_control_state 6971 * Current FSM state 6972 * Access: RO 6973 */ 6974 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 6975 6976 /* reg_mcc_component_size 6977 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 6978 * the size may shorten the update time. Value 0x0 means that size is 6979 * unspecified. 6980 * Access: WO 6981 */ 6982 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 6983 6984 static inline void mlxsw_reg_mcc_pack(char *payload, 6985 enum mlxsw_reg_mcc_instruction instr, 6986 u16 component_index, u32 update_handle, 6987 u32 component_size) 6988 { 6989 MLXSW_REG_ZERO(mcc, payload); 6990 mlxsw_reg_mcc_instruction_set(payload, instr); 6991 mlxsw_reg_mcc_component_index_set(payload, component_index); 6992 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 6993 mlxsw_reg_mcc_component_size_set(payload, component_size); 6994 } 6995 6996 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 6997 u8 *p_error_code, u8 *p_control_state) 6998 { 6999 if (p_update_handle) 7000 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 7001 if (p_error_code) 7002 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 7003 if (p_control_state) 7004 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 7005 } 7006 7007 /* MCDA - Management Component Data Access 7008 * --------------------------------------- 7009 * This register allows reading and writing a firmware component. 7010 */ 7011 #define MLXSW_REG_MCDA_ID 0x9063 7012 #define MLXSW_REG_MCDA_BASE_LEN 0x10 7013 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 7014 #define MLXSW_REG_MCDA_LEN \ 7015 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 7016 7017 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 7018 7019 /* reg_mcda_update_handle 7020 * Token representing the current flow executed by the FSM. 7021 * Access: RW 7022 */ 7023 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 7024 7025 /* reg_mcda_offset 7026 * Offset of accessed address relative to component start. Accesses must be in 7027 * accordance to log_mcda_word_size in MCQI reg. 7028 * Access: RW 7029 */ 7030 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 7031 7032 /* reg_mcda_size 7033 * Size of the data accessed, given in bytes. 7034 * Access: RW 7035 */ 7036 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 7037 7038 /* reg_mcda_data 7039 * Data block accessed. 7040 * Access: RW 7041 */ 7042 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 7043 7044 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 7045 u32 offset, u16 size, u8 *data) 7046 { 7047 int i; 7048 7049 MLXSW_REG_ZERO(mcda, payload); 7050 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 7051 mlxsw_reg_mcda_offset_set(payload, offset); 7052 mlxsw_reg_mcda_size_set(payload, size); 7053 7054 for (i = 0; i < size / 4; i++) 7055 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 7056 } 7057 7058 /* MPSC - Monitoring Packet Sampling Configuration Register 7059 * -------------------------------------------------------- 7060 * MPSC Register is used to configure the Packet Sampling mechanism. 7061 */ 7062 #define MLXSW_REG_MPSC_ID 0x9080 7063 #define MLXSW_REG_MPSC_LEN 0x1C 7064 7065 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 7066 7067 /* reg_mpsc_local_port 7068 * Local port number 7069 * Not supported for CPU port 7070 * Access: Index 7071 */ 7072 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 7073 7074 /* reg_mpsc_e 7075 * Enable sampling on port local_port 7076 * Access: RW 7077 */ 7078 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 7079 7080 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 7081 7082 /* reg_mpsc_rate 7083 * Sampling rate = 1 out of rate packets (with randomization around 7084 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 7085 * Access: RW 7086 */ 7087 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 7088 7089 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 7090 u32 rate) 7091 { 7092 MLXSW_REG_ZERO(mpsc, payload); 7093 mlxsw_reg_mpsc_local_port_set(payload, local_port); 7094 mlxsw_reg_mpsc_e_set(payload, e); 7095 mlxsw_reg_mpsc_rate_set(payload, rate); 7096 } 7097 7098 /* MGPC - Monitoring General Purpose Counter Set Register 7099 * The MGPC register retrieves and sets the General Purpose Counter Set. 7100 */ 7101 #define MLXSW_REG_MGPC_ID 0x9081 7102 #define MLXSW_REG_MGPC_LEN 0x18 7103 7104 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 7105 7106 /* reg_mgpc_counter_set_type 7107 * Counter set type. 7108 * Access: OP 7109 */ 7110 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 7111 7112 /* reg_mgpc_counter_index 7113 * Counter index. 7114 * Access: Index 7115 */ 7116 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 7117 7118 enum mlxsw_reg_mgpc_opcode { 7119 /* Nop */ 7120 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 7121 /* Clear counters */ 7122 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 7123 }; 7124 7125 /* reg_mgpc_opcode 7126 * Opcode. 7127 * Access: OP 7128 */ 7129 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 7130 7131 /* reg_mgpc_byte_counter 7132 * Byte counter value. 7133 * Access: RW 7134 */ 7135 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 7136 7137 /* reg_mgpc_packet_counter 7138 * Packet counter value. 7139 * Access: RW 7140 */ 7141 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 7142 7143 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 7144 enum mlxsw_reg_mgpc_opcode opcode, 7145 enum mlxsw_reg_flow_counter_set_type set_type) 7146 { 7147 MLXSW_REG_ZERO(mgpc, payload); 7148 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 7149 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 7150 mlxsw_reg_mgpc_opcode_set(payload, opcode); 7151 } 7152 7153 /* TIGCR - Tunneling IPinIP General Configuration Register 7154 * ------------------------------------------------------- 7155 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 7156 */ 7157 #define MLXSW_REG_TIGCR_ID 0xA801 7158 #define MLXSW_REG_TIGCR_LEN 0x10 7159 7160 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 7161 7162 /* reg_tigcr_ipip_ttlc 7163 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 7164 * header. 7165 * Access: RW 7166 */ 7167 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 7168 7169 /* reg_tigcr_ipip_ttl_uc 7170 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 7171 * reg_tigcr_ipip_ttlc is unset. 7172 * Access: RW 7173 */ 7174 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 7175 7176 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 7177 { 7178 MLXSW_REG_ZERO(tigcr, payload); 7179 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 7180 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 7181 } 7182 7183 /* SBPR - Shared Buffer Pools Register 7184 * ----------------------------------- 7185 * The SBPR configures and retrieves the shared buffer pools and configuration. 7186 */ 7187 #define MLXSW_REG_SBPR_ID 0xB001 7188 #define MLXSW_REG_SBPR_LEN 0x14 7189 7190 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 7191 7192 /* shared direstion enum for SBPR, SBCM, SBPM */ 7193 enum mlxsw_reg_sbxx_dir { 7194 MLXSW_REG_SBXX_DIR_INGRESS, 7195 MLXSW_REG_SBXX_DIR_EGRESS, 7196 }; 7197 7198 /* reg_sbpr_dir 7199 * Direction. 7200 * Access: Index 7201 */ 7202 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 7203 7204 /* reg_sbpr_pool 7205 * Pool index. 7206 * Access: Index 7207 */ 7208 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 7209 7210 /* reg_sbpr_size 7211 * Pool size in buffer cells. 7212 * Access: RW 7213 */ 7214 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 7215 7216 enum mlxsw_reg_sbpr_mode { 7217 MLXSW_REG_SBPR_MODE_STATIC, 7218 MLXSW_REG_SBPR_MODE_DYNAMIC, 7219 }; 7220 7221 /* reg_sbpr_mode 7222 * Pool quota calculation mode. 7223 * Access: RW 7224 */ 7225 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 7226 7227 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 7228 enum mlxsw_reg_sbxx_dir dir, 7229 enum mlxsw_reg_sbpr_mode mode, u32 size) 7230 { 7231 MLXSW_REG_ZERO(sbpr, payload); 7232 mlxsw_reg_sbpr_pool_set(payload, pool); 7233 mlxsw_reg_sbpr_dir_set(payload, dir); 7234 mlxsw_reg_sbpr_mode_set(payload, mode); 7235 mlxsw_reg_sbpr_size_set(payload, size); 7236 } 7237 7238 /* SBCM - Shared Buffer Class Management Register 7239 * ---------------------------------------------- 7240 * The SBCM register configures and retrieves the shared buffer allocation 7241 * and configuration according to Port-PG, including the binding to pool 7242 * and definition of the associated quota. 7243 */ 7244 #define MLXSW_REG_SBCM_ID 0xB002 7245 #define MLXSW_REG_SBCM_LEN 0x28 7246 7247 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 7248 7249 /* reg_sbcm_local_port 7250 * Local port number. 7251 * For Ingress: excludes CPU port and Router port 7252 * For Egress: excludes IP Router 7253 * Access: Index 7254 */ 7255 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 7256 7257 /* reg_sbcm_pg_buff 7258 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 7259 * For PG buffer: range is 0..cap_max_pg_buffers - 1 7260 * For traffic class: range is 0..cap_max_tclass - 1 7261 * Note that when traffic class is in MC aware mode then the traffic 7262 * classes which are MC aware cannot be configured. 7263 * Access: Index 7264 */ 7265 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 7266 7267 /* reg_sbcm_dir 7268 * Direction. 7269 * Access: Index 7270 */ 7271 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 7272 7273 /* reg_sbcm_min_buff 7274 * Minimum buffer size for the limiter, in cells. 7275 * Access: RW 7276 */ 7277 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 7278 7279 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 7280 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 7281 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 7282 7283 /* reg_sbcm_max_buff 7284 * When the pool associated to the port-pg/tclass is configured to 7285 * static, Maximum buffer size for the limiter configured in cells. 7286 * When the pool associated to the port-pg/tclass is configured to 7287 * dynamic, the max_buff holds the "alpha" parameter, supporting 7288 * the following values: 7289 * 0: 0 7290 * i: (1/128)*2^(i-1), for i=1..14 7291 * 0xFF: Infinity 7292 * Access: RW 7293 */ 7294 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 7295 7296 /* reg_sbcm_pool 7297 * Association of the port-priority to a pool. 7298 * Access: RW 7299 */ 7300 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 7301 7302 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 7303 enum mlxsw_reg_sbxx_dir dir, 7304 u32 min_buff, u32 max_buff, u8 pool) 7305 { 7306 MLXSW_REG_ZERO(sbcm, payload); 7307 mlxsw_reg_sbcm_local_port_set(payload, local_port); 7308 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 7309 mlxsw_reg_sbcm_dir_set(payload, dir); 7310 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 7311 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 7312 mlxsw_reg_sbcm_pool_set(payload, pool); 7313 } 7314 7315 /* SBPM - Shared Buffer Port Management Register 7316 * --------------------------------------------- 7317 * The SBPM register configures and retrieves the shared buffer allocation 7318 * and configuration according to Port-Pool, including the definition 7319 * of the associated quota. 7320 */ 7321 #define MLXSW_REG_SBPM_ID 0xB003 7322 #define MLXSW_REG_SBPM_LEN 0x28 7323 7324 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 7325 7326 /* reg_sbpm_local_port 7327 * Local port number. 7328 * For Ingress: excludes CPU port and Router port 7329 * For Egress: excludes IP Router 7330 * Access: Index 7331 */ 7332 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 7333 7334 /* reg_sbpm_pool 7335 * The pool associated to quota counting on the local_port. 7336 * Access: Index 7337 */ 7338 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 7339 7340 /* reg_sbpm_dir 7341 * Direction. 7342 * Access: Index 7343 */ 7344 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 7345 7346 /* reg_sbpm_buff_occupancy 7347 * Current buffer occupancy in cells. 7348 * Access: RO 7349 */ 7350 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 7351 7352 /* reg_sbpm_clr 7353 * Clear Max Buffer Occupancy 7354 * When this bit is set, max_buff_occupancy field is cleared (and a 7355 * new max value is tracked from the time the clear was performed). 7356 * Access: OP 7357 */ 7358 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 7359 7360 /* reg_sbpm_max_buff_occupancy 7361 * Maximum value of buffer occupancy in cells monitored. Cleared by 7362 * writing to the clr field. 7363 * Access: RO 7364 */ 7365 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 7366 7367 /* reg_sbpm_min_buff 7368 * Minimum buffer size for the limiter, in cells. 7369 * Access: RW 7370 */ 7371 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 7372 7373 /* reg_sbpm_max_buff 7374 * When the pool associated to the port-pg/tclass is configured to 7375 * static, Maximum buffer size for the limiter configured in cells. 7376 * When the pool associated to the port-pg/tclass is configured to 7377 * dynamic, the max_buff holds the "alpha" parameter, supporting 7378 * the following values: 7379 * 0: 0 7380 * i: (1/128)*2^(i-1), for i=1..14 7381 * 0xFF: Infinity 7382 * Access: RW 7383 */ 7384 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 7385 7386 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 7387 enum mlxsw_reg_sbxx_dir dir, bool clr, 7388 u32 min_buff, u32 max_buff) 7389 { 7390 MLXSW_REG_ZERO(sbpm, payload); 7391 mlxsw_reg_sbpm_local_port_set(payload, local_port); 7392 mlxsw_reg_sbpm_pool_set(payload, pool); 7393 mlxsw_reg_sbpm_dir_set(payload, dir); 7394 mlxsw_reg_sbpm_clr_set(payload, clr); 7395 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 7396 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 7397 } 7398 7399 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 7400 u32 *p_max_buff_occupancy) 7401 { 7402 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 7403 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 7404 } 7405 7406 /* SBMM - Shared Buffer Multicast Management Register 7407 * -------------------------------------------------- 7408 * The SBMM register configures and retrieves the shared buffer allocation 7409 * and configuration for MC packets according to Switch-Priority, including 7410 * the binding to pool and definition of the associated quota. 7411 */ 7412 #define MLXSW_REG_SBMM_ID 0xB004 7413 #define MLXSW_REG_SBMM_LEN 0x28 7414 7415 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 7416 7417 /* reg_sbmm_prio 7418 * Switch Priority. 7419 * Access: Index 7420 */ 7421 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 7422 7423 /* reg_sbmm_min_buff 7424 * Minimum buffer size for the limiter, in cells. 7425 * Access: RW 7426 */ 7427 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 7428 7429 /* reg_sbmm_max_buff 7430 * When the pool associated to the port-pg/tclass is configured to 7431 * static, Maximum buffer size for the limiter configured in cells. 7432 * When the pool associated to the port-pg/tclass is configured to 7433 * dynamic, the max_buff holds the "alpha" parameter, supporting 7434 * the following values: 7435 * 0: 0 7436 * i: (1/128)*2^(i-1), for i=1..14 7437 * 0xFF: Infinity 7438 * Access: RW 7439 */ 7440 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 7441 7442 /* reg_sbmm_pool 7443 * Association of the port-priority to a pool. 7444 * Access: RW 7445 */ 7446 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 7447 7448 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 7449 u32 max_buff, u8 pool) 7450 { 7451 MLXSW_REG_ZERO(sbmm, payload); 7452 mlxsw_reg_sbmm_prio_set(payload, prio); 7453 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 7454 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 7455 mlxsw_reg_sbmm_pool_set(payload, pool); 7456 } 7457 7458 /* SBSR - Shared Buffer Status Register 7459 * ------------------------------------ 7460 * The SBSR register retrieves the shared buffer occupancy according to 7461 * Port-Pool. Note that this register enables reading a large amount of data. 7462 * It is the user's responsibility to limit the amount of data to ensure the 7463 * response can match the maximum transfer unit. In case the response exceeds 7464 * the maximum transport unit, it will be truncated with no special notice. 7465 */ 7466 #define MLXSW_REG_SBSR_ID 0xB005 7467 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 7468 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 7469 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 7470 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 7471 MLXSW_REG_SBSR_REC_LEN * \ 7472 MLXSW_REG_SBSR_REC_MAX_COUNT) 7473 7474 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 7475 7476 /* reg_sbsr_clr 7477 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 7478 * field is cleared (and a new max value is tracked from the time the clear 7479 * was performed). 7480 * Access: OP 7481 */ 7482 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 7483 7484 /* reg_sbsr_ingress_port_mask 7485 * Bit vector for all ingress network ports. 7486 * Indicates which of the ports (for which the relevant bit is set) 7487 * are affected by the set operation. Configuration of any other port 7488 * does not change. 7489 * Access: Index 7490 */ 7491 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 7492 7493 /* reg_sbsr_pg_buff_mask 7494 * Bit vector for all switch priority groups. 7495 * Indicates which of the priorities (for which the relevant bit is set) 7496 * are affected by the set operation. Configuration of any other priority 7497 * does not change. 7498 * Range is 0..cap_max_pg_buffers - 1 7499 * Access: Index 7500 */ 7501 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 7502 7503 /* reg_sbsr_egress_port_mask 7504 * Bit vector for all egress network ports. 7505 * Indicates which of the ports (for which the relevant bit is set) 7506 * are affected by the set operation. Configuration of any other port 7507 * does not change. 7508 * Access: Index 7509 */ 7510 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 7511 7512 /* reg_sbsr_tclass_mask 7513 * Bit vector for all traffic classes. 7514 * Indicates which of the traffic classes (for which the relevant bit is 7515 * set) are affected by the set operation. Configuration of any other 7516 * traffic class does not change. 7517 * Range is 0..cap_max_tclass - 1 7518 * Access: Index 7519 */ 7520 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 7521 7522 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 7523 { 7524 MLXSW_REG_ZERO(sbsr, payload); 7525 mlxsw_reg_sbsr_clr_set(payload, clr); 7526 } 7527 7528 /* reg_sbsr_rec_buff_occupancy 7529 * Current buffer occupancy in cells. 7530 * Access: RO 7531 */ 7532 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7533 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 7534 7535 /* reg_sbsr_rec_max_buff_occupancy 7536 * Maximum value of buffer occupancy in cells monitored. Cleared by 7537 * writing to the clr field. 7538 * Access: RO 7539 */ 7540 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7541 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 7542 7543 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 7544 u32 *p_buff_occupancy, 7545 u32 *p_max_buff_occupancy) 7546 { 7547 *p_buff_occupancy = 7548 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 7549 *p_max_buff_occupancy = 7550 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 7551 } 7552 7553 /* SBIB - Shared Buffer Internal Buffer Register 7554 * --------------------------------------------- 7555 * The SBIB register configures per port buffers for internal use. The internal 7556 * buffers consume memory on the port buffers (note that the port buffers are 7557 * used also by PBMC). 7558 * 7559 * For Spectrum this is used for egress mirroring. 7560 */ 7561 #define MLXSW_REG_SBIB_ID 0xB006 7562 #define MLXSW_REG_SBIB_LEN 0x10 7563 7564 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 7565 7566 /* reg_sbib_local_port 7567 * Local port number 7568 * Not supported for CPU port and router port 7569 * Access: Index 7570 */ 7571 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 7572 7573 /* reg_sbib_buff_size 7574 * Units represented in cells 7575 * Allowed range is 0 to (cap_max_headroom_size - 1) 7576 * Default is 0 7577 * Access: RW 7578 */ 7579 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 7580 7581 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 7582 u32 buff_size) 7583 { 7584 MLXSW_REG_ZERO(sbib, payload); 7585 mlxsw_reg_sbib_local_port_set(payload, local_port); 7586 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 7587 } 7588 7589 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 7590 MLXSW_REG(sgcr), 7591 MLXSW_REG(spad), 7592 MLXSW_REG(smid), 7593 MLXSW_REG(sspr), 7594 MLXSW_REG(sfdat), 7595 MLXSW_REG(sfd), 7596 MLXSW_REG(sfn), 7597 MLXSW_REG(spms), 7598 MLXSW_REG(spvid), 7599 MLXSW_REG(spvm), 7600 MLXSW_REG(spaft), 7601 MLXSW_REG(sfgc), 7602 MLXSW_REG(sftr), 7603 MLXSW_REG(sfdf), 7604 MLXSW_REG(sldr), 7605 MLXSW_REG(slcr), 7606 MLXSW_REG(slcor), 7607 MLXSW_REG(spmlr), 7608 MLXSW_REG(svfa), 7609 MLXSW_REG(svpe), 7610 MLXSW_REG(sfmr), 7611 MLXSW_REG(spvmlr), 7612 MLXSW_REG(cwtp), 7613 MLXSW_REG(cwtpm), 7614 MLXSW_REG(ppbt), 7615 MLXSW_REG(pacl), 7616 MLXSW_REG(pagt), 7617 MLXSW_REG(ptar), 7618 MLXSW_REG(ppbs), 7619 MLXSW_REG(prcr), 7620 MLXSW_REG(pefa), 7621 MLXSW_REG(ptce2), 7622 MLXSW_REG(qpcr), 7623 MLXSW_REG(qtct), 7624 MLXSW_REG(qeec), 7625 MLXSW_REG(pmlp), 7626 MLXSW_REG(pmtu), 7627 MLXSW_REG(ptys), 7628 MLXSW_REG(ppad), 7629 MLXSW_REG(paos), 7630 MLXSW_REG(pfcc), 7631 MLXSW_REG(ppcnt), 7632 MLXSW_REG(plib), 7633 MLXSW_REG(pptb), 7634 MLXSW_REG(pbmc), 7635 MLXSW_REG(pspa), 7636 MLXSW_REG(htgt), 7637 MLXSW_REG(hpkt), 7638 MLXSW_REG(rgcr), 7639 MLXSW_REG(ritr), 7640 MLXSW_REG(rtar), 7641 MLXSW_REG(ratr), 7642 MLXSW_REG(rtdp), 7643 MLXSW_REG(ricnt), 7644 MLXSW_REG(rrcr), 7645 MLXSW_REG(ralta), 7646 MLXSW_REG(ralst), 7647 MLXSW_REG(raltb), 7648 MLXSW_REG(ralue), 7649 MLXSW_REG(rauht), 7650 MLXSW_REG(raleu), 7651 MLXSW_REG(rauhtd), 7652 MLXSW_REG(rigr2), 7653 MLXSW_REG(recr2), 7654 MLXSW_REG(rmft2), 7655 MLXSW_REG(mfcr), 7656 MLXSW_REG(mfsc), 7657 MLXSW_REG(mfsm), 7658 MLXSW_REG(mfsl), 7659 MLXSW_REG(mtcap), 7660 MLXSW_REG(mtmp), 7661 MLXSW_REG(mcia), 7662 MLXSW_REG(mpat), 7663 MLXSW_REG(mpar), 7664 MLXSW_REG(mlcr), 7665 MLXSW_REG(mpsc), 7666 MLXSW_REG(mcqi), 7667 MLXSW_REG(mcc), 7668 MLXSW_REG(mcda), 7669 MLXSW_REG(mgpc), 7670 MLXSW_REG(tigcr), 7671 MLXSW_REG(sbpr), 7672 MLXSW_REG(sbcm), 7673 MLXSW_REG(sbpm), 7674 MLXSW_REG(sbmm), 7675 MLXSW_REG(sbsr), 7676 MLXSW_REG(sbib), 7677 }; 7678 7679 static inline const char *mlxsw_reg_id_str(u16 reg_id) 7680 { 7681 const struct mlxsw_reg_info *reg_info; 7682 int i; 7683 7684 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 7685 reg_info = mlxsw_reg_infos[i]; 7686 if (reg_info->id == reg_id) 7687 return reg_info->name; 7688 } 7689 return "*UNKNOWN*"; 7690 } 7691 7692 /* PUDE - Port Up / Down Event 7693 * --------------------------- 7694 * Reports the operational state change of a port. 7695 */ 7696 #define MLXSW_REG_PUDE_LEN 0x10 7697 7698 /* reg_pude_swid 7699 * Switch partition ID with which to associate the port. 7700 * Access: Index 7701 */ 7702 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 7703 7704 /* reg_pude_local_port 7705 * Local port number. 7706 * Access: Index 7707 */ 7708 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 7709 7710 /* reg_pude_admin_status 7711 * Port administrative state (the desired state). 7712 * 1 - Up. 7713 * 2 - Down. 7714 * 3 - Up once. This means that in case of link failure, the port won't go 7715 * into polling mode, but will wait to be re-enabled by software. 7716 * 4 - Disabled by system. Can only be set by hardware. 7717 * Access: RO 7718 */ 7719 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 7720 7721 /* reg_pude_oper_status 7722 * Port operatioanl state. 7723 * 1 - Up. 7724 * 2 - Down. 7725 * 3 - Down by port failure. This means that the device will not let the 7726 * port up again until explicitly specified by software. 7727 * Access: RO 7728 */ 7729 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 7730 7731 #endif 7732