1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_set_vid 326 * Set VID. 327 * 0 - Do not update VID. 328 * 1 - Set VID. 329 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 330 * Access: RW 331 * 332 * Note: Reserved when legacy bridge model is used. 333 */ 334 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 335 MLXSW_REG_SFD_REC_LEN, 0x08, false); 336 337 /* reg_sfd_uc_fid_vid 338 * Filtering ID or VLAN ID 339 * For SwitchX and SwitchX-2: 340 * - Dynamic entries (policy 2,3) use FID 341 * - Static entries (policy 0) use VID 342 * - When independent learning is configured, VID=FID 343 * For Spectrum: use FID for both Dynamic and Static entries. 344 * VID should not be used. 345 * Access: Index 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 348 MLXSW_REG_SFD_REC_LEN, 0x08, false); 349 350 /* reg_sfd_uc_vid 351 * New VID when set_vid=1. 352 * Access: RW 353 * 354 * Note: Reserved when legacy bridge model is used and when set_vid=0. 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 357 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 358 359 /* reg_sfd_uc_system_port 360 * Unique port identifier for the final destination of the packet. 361 * Access: RW 362 */ 363 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 364 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 365 366 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 367 enum mlxsw_reg_sfd_rec_type rec_type, 368 const char *mac, 369 enum mlxsw_reg_sfd_rec_action action) 370 { 371 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 372 373 if (rec_index >= num_rec) 374 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 375 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 376 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 377 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 378 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 379 } 380 381 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 382 enum mlxsw_reg_sfd_rec_policy policy, 383 const char *mac, u16 fid_vid, u16 vid, 384 enum mlxsw_reg_sfd_rec_action action, 385 u16 local_port) 386 { 387 mlxsw_reg_sfd_rec_pack(payload, rec_index, 388 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 389 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 390 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 391 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 392 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 393 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 394 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 395 } 396 397 /* reg_sfd_uc_lag_sub_port 398 * LAG sub port. 399 * Must be 0 if multichannel VEPA is not enabled. 400 * Access: RW 401 */ 402 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 403 MLXSW_REG_SFD_REC_LEN, 0x08, false); 404 405 /* reg_sfd_uc_lag_set_vid 406 * Set VID. 407 * 0 - Do not update VID. 408 * 1 - Set VID. 409 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 410 * Access: RW 411 * 412 * Note: Reserved when legacy bridge model is used. 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_lag_fid_vid 418 * Filtering ID or VLAN ID 419 * For SwitchX and SwitchX-2: 420 * - Dynamic entries (policy 2,3) use FID 421 * - Static entries (policy 0) use VID 422 * - When independent learning is configured, VID=FID 423 * For Spectrum: use FID for both Dynamic and Static entries. 424 * VID should not be used. 425 * Access: Index 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 428 MLXSW_REG_SFD_REC_LEN, 0x08, false); 429 430 /* reg_sfd_uc_lag_lag_vid 431 * New vlan ID. 432 * Access: RW 433 * 434 * Note: Reserved when legacy bridge model is used and set_vid=0. 435 */ 436 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 437 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 438 439 /* reg_sfd_uc_lag_lag_id 440 * LAG Identifier - pointer into the LAG descriptor table. 441 * Access: RW 442 */ 443 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 444 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 445 446 static inline void 447 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 448 enum mlxsw_reg_sfd_rec_policy policy, 449 const char *mac, u16 fid_vid, 450 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 451 u16 lag_id) 452 { 453 mlxsw_reg_sfd_rec_pack(payload, rec_index, 454 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 455 mac, action); 456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 457 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 458 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 459 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 460 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 461 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 462 } 463 464 /* reg_sfd_mc_pgi 465 * 466 * Multicast port group index - index into the port group table. 467 * Value 0x1FFF indicates the pgi should point to the MID entry. 468 * For Spectrum this value must be set to 0x1FFF 469 * Access: RW 470 */ 471 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 472 MLXSW_REG_SFD_REC_LEN, 0x08, false); 473 474 /* reg_sfd_mc_fid_vid 475 * 476 * Filtering ID or VLAN ID 477 * Access: Index 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x08, false); 481 482 /* reg_sfd_mc_mid 483 * 484 * Multicast identifier - global identifier that represents the multicast 485 * group across all devices. 486 * Access: RW 487 */ 488 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 489 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 490 491 static inline void 492 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 493 const char *mac, u16 fid_vid, 494 enum mlxsw_reg_sfd_rec_action action, u16 mid) 495 { 496 mlxsw_reg_sfd_rec_pack(payload, rec_index, 497 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 498 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 499 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 500 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 501 } 502 503 /* reg_sfd_uc_tunnel_uip_msb 504 * When protocol is IPv4, the most significant byte of the underlay IPv4 505 * destination IP. 506 * When protocol is IPv6, reserved. 507 * Access: RW 508 */ 509 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 510 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 511 512 /* reg_sfd_uc_tunnel_fid 513 * Filtering ID. 514 * Access: Index 515 */ 516 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 517 MLXSW_REG_SFD_REC_LEN, 0x08, false); 518 519 enum mlxsw_reg_sfd_uc_tunnel_protocol { 520 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 521 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 522 }; 523 524 /* reg_sfd_uc_tunnel_protocol 525 * IP protocol. 526 * Access: RW 527 */ 528 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 529 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 530 531 /* reg_sfd_uc_tunnel_uip_lsb 532 * When protocol is IPv4, the least significant bytes of the underlay 533 * IPv4 destination IP. 534 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 535 * which is configured by RIPS. 536 * Access: RW 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 539 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 540 541 static inline void 542 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 543 enum mlxsw_reg_sfd_rec_policy policy, 544 const char *mac, u16 fid, 545 enum mlxsw_reg_sfd_rec_action action, 546 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 547 { 548 mlxsw_reg_sfd_rec_pack(payload, rec_index, 549 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 550 action); 551 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 552 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 553 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 554 } 555 556 static inline void 557 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 558 enum mlxsw_reg_sfd_rec_policy policy, 559 const char *mac, u16 fid, 560 enum mlxsw_reg_sfd_rec_action action, u32 uip) 561 { 562 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 563 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 564 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 565 action, 566 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 567 } 568 569 static inline void 570 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 571 u16 fid, enum mlxsw_reg_sfd_rec_action action, 572 u32 uip_ptr) 573 { 574 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 575 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 576 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 577 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 578 mac, fid, action, 579 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 580 } 581 582 enum mlxsw_reg_tunnel_port { 583 MLXSW_REG_TUNNEL_PORT_NVE, 584 MLXSW_REG_TUNNEL_PORT_VPLS, 585 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 586 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 587 }; 588 589 /* SFN - Switch FDB Notification Register 590 * ------------------------------------------- 591 * The switch provides notifications on newly learned FDB entries and 592 * aged out entries. The notifications can be polled by software. 593 */ 594 #define MLXSW_REG_SFN_ID 0x200B 595 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 596 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 597 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 598 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 599 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 600 601 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 602 603 /* reg_sfn_swid 604 * Switch partition ID. 605 * Access: Index 606 */ 607 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 608 609 /* reg_sfn_end 610 * Forces the current session to end. 611 * Access: OP 612 */ 613 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 614 615 /* reg_sfn_num_rec 616 * Request: Number of learned notifications and aged-out notification 617 * records requested. 618 * Response: Number of notification records returned (must be smaller 619 * than or equal to the value requested) 620 * Ranges 0..64 621 * Access: OP 622 */ 623 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 624 625 static inline void mlxsw_reg_sfn_pack(char *payload) 626 { 627 MLXSW_REG_ZERO(sfn, payload); 628 mlxsw_reg_sfn_swid_set(payload, 0); 629 mlxsw_reg_sfn_end_set(payload, 0); 630 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 631 } 632 633 /* reg_sfn_rec_swid 634 * Switch partition ID. 635 * Access: RO 636 */ 637 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 638 MLXSW_REG_SFN_REC_LEN, 0x00, false); 639 640 enum mlxsw_reg_sfn_rec_type { 641 /* MAC addresses learned on a regular port. */ 642 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 643 /* MAC addresses learned on a LAG port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 645 /* Aged-out MAC address on a regular port. */ 646 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 647 /* Aged-out MAC address on a LAG port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 649 /* Learned unicast tunnel record. */ 650 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 651 /* Aged-out unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 653 }; 654 655 /* reg_sfn_rec_type 656 * Notification record type. 657 * Access: RO 658 */ 659 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 660 MLXSW_REG_SFN_REC_LEN, 0x00, false); 661 662 /* reg_sfn_rec_mac 663 * MAC address. 664 * Access: RO 665 */ 666 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 667 MLXSW_REG_SFN_REC_LEN, 0x02); 668 669 /* reg_sfn_mac_sub_port 670 * VEPA channel on the local port. 671 * 0 if multichannel VEPA is not enabled. 672 * Access: RO 673 */ 674 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 675 MLXSW_REG_SFN_REC_LEN, 0x08, false); 676 677 /* reg_sfn_mac_fid 678 * Filtering identifier. 679 * Access: RO 680 */ 681 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 682 MLXSW_REG_SFN_REC_LEN, 0x08, false); 683 684 /* reg_sfn_mac_system_port 685 * Unique port identifier for the final destination of the packet. 686 * Access: RO 687 */ 688 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 689 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 690 691 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 692 char *mac, u16 *p_vid, 693 u16 *p_local_port) 694 { 695 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 696 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 697 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 698 } 699 700 /* reg_sfn_mac_lag_lag_id 701 * LAG ID (pointer into the LAG descriptor table). 702 * Access: RO 703 */ 704 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 705 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 706 707 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 708 char *mac, u16 *p_vid, 709 u16 *p_lag_id) 710 { 711 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 712 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 713 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 714 } 715 716 /* reg_sfn_uc_tunnel_uip_msb 717 * When protocol is IPv4, the most significant byte of the underlay IPv4 718 * address of the remote VTEP. 719 * When protocol is IPv6, reserved. 720 * Access: RO 721 */ 722 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 723 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 724 725 enum mlxsw_reg_sfn_uc_tunnel_protocol { 726 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 727 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 728 }; 729 730 /* reg_sfn_uc_tunnel_protocol 731 * IP protocol. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 735 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_uip_lsb 738 * When protocol is IPv4, the least significant bytes of the underlay 739 * IPv4 address of the remote VTEP. 740 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 741 * Access: RO 742 */ 743 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 744 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 745 746 /* reg_sfn_uc_tunnel_port 747 * Tunnel port. 748 * Reserved on Spectrum. 749 * Access: RO 750 */ 751 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 752 MLXSW_REG_SFN_REC_LEN, 0x10, false); 753 754 static inline void 755 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 756 u16 *p_fid, u32 *p_uip, 757 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 758 { 759 u32 uip_msb, uip_lsb; 760 761 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 762 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 763 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 764 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 765 *p_uip = uip_msb << 24 | uip_lsb; 766 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 767 } 768 769 /* SPMS - Switch Port MSTP/RSTP State Register 770 * ------------------------------------------- 771 * Configures the spanning tree state of a physical port. 772 */ 773 #define MLXSW_REG_SPMS_ID 0x200D 774 #define MLXSW_REG_SPMS_LEN 0x404 775 776 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 777 778 /* reg_spms_local_port 779 * Local port number. 780 * Access: Index 781 */ 782 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 783 784 enum mlxsw_reg_spms_state { 785 MLXSW_REG_SPMS_STATE_NO_CHANGE, 786 MLXSW_REG_SPMS_STATE_DISCARDING, 787 MLXSW_REG_SPMS_STATE_LEARNING, 788 MLXSW_REG_SPMS_STATE_FORWARDING, 789 }; 790 791 /* reg_spms_state 792 * Spanning tree state of each VLAN ID (VID) of the local port. 793 * 0 - Do not change spanning tree state (used only when writing). 794 * 1 - Discarding. No learning or forwarding to/from this port (default). 795 * 2 - Learning. Port is learning, but not forwarding. 796 * 3 - Forwarding. Port is learning and forwarding. 797 * Access: RW 798 */ 799 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 800 801 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 802 { 803 MLXSW_REG_ZERO(spms, payload); 804 mlxsw_reg_spms_local_port_set(payload, local_port); 805 } 806 807 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 808 enum mlxsw_reg_spms_state state) 809 { 810 mlxsw_reg_spms_state_set(payload, vid, state); 811 } 812 813 /* SPVID - Switch Port VID 814 * ----------------------- 815 * The switch port VID configures the default VID for a port. 816 */ 817 #define MLXSW_REG_SPVID_ID 0x200E 818 #define MLXSW_REG_SPVID_LEN 0x08 819 820 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 821 822 /* reg_spvid_tport 823 * Port is tunnel port. 824 * Reserved when SwitchX/-2 or Spectrum-1. 825 * Access: Index 826 */ 827 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 828 829 /* reg_spvid_local_port 830 * When tport = 0: Local port number. Not supported for CPU port. 831 * When tport = 1: Tunnel port. 832 * Access: Index 833 */ 834 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 835 836 /* reg_spvid_sub_port 837 * Virtual port within the physical port. 838 * Should be set to 0 when virtual ports are not enabled on the port. 839 * Access: Index 840 */ 841 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 842 843 /* reg_spvid_egr_et_set 844 * When VLAN is pushed at ingress (for untagged packets or for 845 * QinQ push mode) then the EtherType is decided at the egress port. 846 * Reserved when Spectrum-1. 847 * Access: RW 848 */ 849 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 850 851 /* reg_spvid_et_vlan 852 * EtherType used for when VLAN is pushed at ingress (for untagged 853 * packets or for QinQ push mode). 854 * 0: ether_type0 - (default) 855 * 1: ether_type1 856 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 857 * Ethertype IDs are configured by SVER. 858 * Reserved when egr_et_set = 1. 859 * Access: RW 860 */ 861 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 862 863 /* reg_spvid_pvid 864 * Port default VID 865 * Access: RW 866 */ 867 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 868 869 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 870 u8 et_vlan) 871 { 872 MLXSW_REG_ZERO(spvid, payload); 873 mlxsw_reg_spvid_local_port_set(payload, local_port); 874 mlxsw_reg_spvid_pvid_set(payload, pvid); 875 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 876 } 877 878 /* SPVM - Switch Port VLAN Membership 879 * ---------------------------------- 880 * The Switch Port VLAN Membership register configures the VLAN membership 881 * of a port in a VLAN denoted by VID. VLAN membership is managed per 882 * virtual port. The register can be used to add and remove VID(s) from a port. 883 */ 884 #define MLXSW_REG_SPVM_ID 0x200F 885 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 886 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 887 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 888 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 889 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 890 891 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 892 893 /* reg_spvm_pt 894 * Priority tagged. If this bit is set, packets forwarded to the port with 895 * untagged VLAN membership (u bit is set) will be tagged with priority tag 896 * (VID=0) 897 * Access: RW 898 */ 899 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 900 901 /* reg_spvm_pte 902 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 903 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 904 * Access: WO 905 */ 906 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 907 908 /* reg_spvm_local_port 909 * Local port number. 910 * Access: Index 911 */ 912 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 913 914 /* reg_spvm_sub_port 915 * Virtual port within the physical port. 916 * Should be set to 0 when virtual ports are not enabled on the port. 917 * Access: Index 918 */ 919 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 920 921 /* reg_spvm_num_rec 922 * Number of records to update. Each record contains: i, e, u, vid. 923 * Access: OP 924 */ 925 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 926 927 /* reg_spvm_rec_i 928 * Ingress membership in VLAN ID. 929 * Access: Index 930 */ 931 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 932 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 933 MLXSW_REG_SPVM_REC_LEN, 0, false); 934 935 /* reg_spvm_rec_e 936 * Egress membership in VLAN ID. 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 940 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_u 944 * Untagged - port is an untagged member - egress transmission uses untagged 945 * frames on VID<n> 946 * Access: Index 947 */ 948 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 949 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 950 MLXSW_REG_SPVM_REC_LEN, 0, false); 951 952 /* reg_spvm_rec_vid 953 * Egress membership in VLAN ID. 954 * Access: Index 955 */ 956 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 957 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 958 MLXSW_REG_SPVM_REC_LEN, 0, false); 959 960 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 961 u16 vid_begin, u16 vid_end, 962 bool is_member, bool untagged) 963 { 964 int size = vid_end - vid_begin + 1; 965 int i; 966 967 MLXSW_REG_ZERO(spvm, payload); 968 mlxsw_reg_spvm_local_port_set(payload, local_port); 969 mlxsw_reg_spvm_num_rec_set(payload, size); 970 971 for (i = 0; i < size; i++) { 972 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 973 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 974 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 975 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 976 } 977 } 978 979 /* SPAFT - Switch Port Acceptable Frame Types 980 * ------------------------------------------ 981 * The Switch Port Acceptable Frame Types register configures the frame 982 * admittance of the port. 983 */ 984 #define MLXSW_REG_SPAFT_ID 0x2010 985 #define MLXSW_REG_SPAFT_LEN 0x08 986 987 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 988 989 /* reg_spaft_local_port 990 * Local port number. 991 * Access: Index 992 * 993 * Note: CPU port is not supported (all tag types are allowed). 994 */ 995 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 996 997 /* reg_spaft_sub_port 998 * Virtual port within the physical port. 999 * Should be set to 0 when virtual ports are not enabled on the port. 1000 * Access: RW 1001 */ 1002 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1003 1004 /* reg_spaft_allow_untagged 1005 * When set, untagged frames on the ingress are allowed (default). 1006 * Access: RW 1007 */ 1008 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1009 1010 /* reg_spaft_allow_prio_tagged 1011 * When set, priority tagged frames on the ingress are allowed (default). 1012 * Access: RW 1013 */ 1014 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1015 1016 /* reg_spaft_allow_tagged 1017 * When set, tagged frames on the ingress are allowed (default). 1018 * Access: RW 1019 */ 1020 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1021 1022 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1023 bool allow_untagged) 1024 { 1025 MLXSW_REG_ZERO(spaft, payload); 1026 mlxsw_reg_spaft_local_port_set(payload, local_port); 1027 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1028 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1029 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1030 } 1031 1032 /* SFGC - Switch Flooding Group Configuration 1033 * ------------------------------------------ 1034 * The following register controls the association of flooding tables and MIDs 1035 * to packet types used for flooding. 1036 */ 1037 #define MLXSW_REG_SFGC_ID 0x2011 1038 #define MLXSW_REG_SFGC_LEN 0x14 1039 1040 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1041 1042 enum mlxsw_reg_sfgc_type { 1043 MLXSW_REG_SFGC_TYPE_BROADCAST, 1044 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1045 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1046 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1047 MLXSW_REG_SFGC_TYPE_RESERVED, 1048 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1049 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1050 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1051 MLXSW_REG_SFGC_TYPE_MAX, 1052 }; 1053 1054 /* reg_sfgc_type 1055 * The traffic type to reach the flooding table. 1056 * Access: Index 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1059 1060 /* bridge_type is used in SFGC and SFMR. */ 1061 enum mlxsw_reg_bridge_type { 1062 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1063 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1064 }; 1065 1066 /* reg_sfgc_bridge_type 1067 * Access: Index 1068 * 1069 * Note: SwitchX-2 only supports 802.1Q mode. 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1072 1073 enum mlxsw_flood_table_type { 1074 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1075 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1076 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1077 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1078 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1079 }; 1080 1081 /* reg_sfgc_table_type 1082 * See mlxsw_flood_table_type 1083 * Access: RW 1084 * 1085 * Note: FID offset and FID types are not supported in SwitchX-2. 1086 */ 1087 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1088 1089 /* reg_sfgc_flood_table 1090 * Flooding table index to associate with the specific type on the specific 1091 * switch partition. 1092 * Access: RW 1093 */ 1094 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1095 1096 /* reg_sfgc_counter_set_type 1097 * Counter Set Type for flow counters. 1098 * Access: RW 1099 */ 1100 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1101 1102 /* reg_sfgc_counter_index 1103 * Counter Index for flow counters. 1104 * Access: RW 1105 */ 1106 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1107 1108 /* reg_sfgc_mid_base 1109 * MID Base. 1110 * Access: RW 1111 * 1112 * Note: Reserved when legacy bridge model is used. 1113 */ 1114 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1115 1116 static inline void 1117 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1118 enum mlxsw_reg_bridge_type bridge_type, 1119 enum mlxsw_flood_table_type table_type, 1120 unsigned int flood_table, u16 mid_base) 1121 { 1122 MLXSW_REG_ZERO(sfgc, payload); 1123 mlxsw_reg_sfgc_type_set(payload, type); 1124 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1125 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1126 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1127 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1128 } 1129 1130 /* SFDF - Switch Filtering DB Flush 1131 * -------------------------------- 1132 * The switch filtering DB flush register is used to flush the FDB. 1133 * Note that FDB notifications are flushed as well. 1134 */ 1135 #define MLXSW_REG_SFDF_ID 0x2013 1136 #define MLXSW_REG_SFDF_LEN 0x14 1137 1138 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1139 1140 /* reg_sfdf_swid 1141 * Switch partition ID. 1142 * Access: Index 1143 */ 1144 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1145 1146 enum mlxsw_reg_sfdf_flush_type { 1147 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1148 MLXSW_REG_SFDF_FLUSH_PER_FID, 1149 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1150 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1151 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1152 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1153 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1154 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1155 }; 1156 1157 /* reg_sfdf_flush_type 1158 * Flush type. 1159 * 0 - All SWID dynamic entries are flushed. 1160 * 1 - All FID dynamic entries are flushed. 1161 * 2 - All dynamic entries pointing to port are flushed. 1162 * 3 - All FID dynamic entries pointing to port are flushed. 1163 * 4 - All dynamic entries pointing to LAG are flushed. 1164 * 5 - All FID dynamic entries pointing to LAG are flushed. 1165 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1166 * flushed. 1167 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1168 * flushed, per FID. 1169 * Access: RW 1170 */ 1171 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1172 1173 /* reg_sfdf_flush_static 1174 * Static. 1175 * 0 - Flush only dynamic entries. 1176 * 1 - Flush both dynamic and static entries. 1177 * Access: RW 1178 */ 1179 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1180 1181 static inline void mlxsw_reg_sfdf_pack(char *payload, 1182 enum mlxsw_reg_sfdf_flush_type type) 1183 { 1184 MLXSW_REG_ZERO(sfdf, payload); 1185 mlxsw_reg_sfdf_flush_type_set(payload, type); 1186 mlxsw_reg_sfdf_flush_static_set(payload, true); 1187 } 1188 1189 /* reg_sfdf_fid 1190 * FID to flush. 1191 * Access: RW 1192 */ 1193 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1194 1195 /* reg_sfdf_system_port 1196 * Port to flush. 1197 * Access: RW 1198 */ 1199 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1200 1201 /* reg_sfdf_port_fid_system_port 1202 * Port to flush, pointed to by FID. 1203 * Access: RW 1204 */ 1205 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1206 1207 /* reg_sfdf_lag_id 1208 * LAG ID to flush. 1209 * Access: RW 1210 */ 1211 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1212 1213 /* reg_sfdf_lag_fid_lag_id 1214 * LAG ID to flush, pointed to by FID. 1215 * Access: RW 1216 */ 1217 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1218 1219 /* SLDR - Switch LAG Descriptor Register 1220 * ----------------------------------------- 1221 * The switch LAG descriptor register is populated by LAG descriptors. 1222 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1223 * max_lag-1. 1224 */ 1225 #define MLXSW_REG_SLDR_ID 0x2014 1226 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1227 1228 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1229 1230 enum mlxsw_reg_sldr_op { 1231 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1232 MLXSW_REG_SLDR_OP_LAG_CREATE, 1233 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1234 /* Ports that appear in the list have the Distributor enabled */ 1235 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1236 /* Removes ports from the disributor list */ 1237 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1238 }; 1239 1240 /* reg_sldr_op 1241 * Operation. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1245 1246 /* reg_sldr_lag_id 1247 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1248 * Access: Index 1249 */ 1250 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1251 1252 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1253 { 1254 MLXSW_REG_ZERO(sldr, payload); 1255 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1256 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1257 } 1258 1259 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1260 { 1261 MLXSW_REG_ZERO(sldr, payload); 1262 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1263 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1264 } 1265 1266 /* reg_sldr_num_ports 1267 * The number of member ports of the LAG. 1268 * Reserved for Create / Destroy operations 1269 * For Add / Remove operations - indicates the number of ports in the list. 1270 * Access: RW 1271 */ 1272 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1273 1274 /* reg_sldr_system_port 1275 * System port. 1276 * Access: RW 1277 */ 1278 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1279 1280 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1281 u16 local_port) 1282 { 1283 MLXSW_REG_ZERO(sldr, payload); 1284 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1285 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1286 mlxsw_reg_sldr_num_ports_set(payload, 1); 1287 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1288 } 1289 1290 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1291 u16 local_port) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 mlxsw_reg_sldr_num_ports_set(payload, 1); 1297 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1298 } 1299 1300 /* SLCR - Switch LAG Configuration 2 Register 1301 * ------------------------------------------- 1302 * The Switch LAG Configuration register is used for configuring the 1303 * LAG properties of the switch. 1304 */ 1305 #define MLXSW_REG_SLCR_ID 0x2015 1306 #define MLXSW_REG_SLCR_LEN 0x10 1307 1308 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1309 1310 enum mlxsw_reg_slcr_pp { 1311 /* Global Configuration (for all ports) */ 1312 MLXSW_REG_SLCR_PP_GLOBAL, 1313 /* Per port configuration, based on local_port field */ 1314 MLXSW_REG_SLCR_PP_PER_PORT, 1315 }; 1316 1317 /* reg_slcr_pp 1318 * Per Port Configuration 1319 * Note: Reading at Global mode results in reading port 1 configuration. 1320 * Access: Index 1321 */ 1322 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1323 1324 /* reg_slcr_local_port 1325 * Local port number 1326 * Supported from CPU port 1327 * Not supported from router port 1328 * Reserved when pp = Global Configuration 1329 * Access: Index 1330 */ 1331 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1332 1333 enum mlxsw_reg_slcr_type { 1334 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1335 MLXSW_REG_SLCR_TYPE_XOR, 1336 MLXSW_REG_SLCR_TYPE_RANDOM, 1337 }; 1338 1339 /* reg_slcr_type 1340 * Hash type 1341 * Access: RW 1342 */ 1343 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1344 1345 /* Ingress port */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1347 /* SMAC - for IPv4 and IPv6 packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1349 /* SMAC - for non-IP packets */ 1350 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1351 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1352 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1353 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1354 /* DMAC - for IPv4 and IPv6 packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1356 /* DMAC - for non-IP packets */ 1357 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1358 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1359 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1360 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1361 /* Ethertype - for IPv4 and IPv6 packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1363 /* Ethertype - for non-IP packets */ 1364 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1365 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1366 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1367 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1368 /* VLAN ID - for IPv4 and IPv6 packets */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1370 /* VLAN ID - for non-IP packets */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1372 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1373 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1374 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1375 /* Source IP address (can be IPv4 or IPv6) */ 1376 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1377 /* Destination IP address (can be IPv4 or IPv6) */ 1378 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1379 /* TCP/UDP source port */ 1380 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1381 /* TCP/UDP destination port*/ 1382 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1383 /* IPv4 Protocol/IPv6 Next Header */ 1384 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1385 /* IPv6 Flow label */ 1386 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1387 /* SID - FCoE source ID */ 1388 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1389 /* DID - FCoE destination ID */ 1390 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1391 /* OXID - FCoE originator exchange ID */ 1392 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1393 /* Destination QP number - for RoCE packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1395 1396 /* reg_slcr_lag_hash 1397 * LAG hashing configuration. This is a bitmask, in which each set 1398 * bit includes the corresponding item in the LAG hash calculation. 1399 * The default lag_hash contains SMAC, DMAC, VLANID and 1400 * Ethertype (for all packet types). 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1404 1405 /* reg_slcr_seed 1406 * LAG seed value. The seed is the same for all ports. 1407 * Access: RW 1408 */ 1409 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1410 1411 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1412 { 1413 MLXSW_REG_ZERO(slcr, payload); 1414 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1415 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1416 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1417 mlxsw_reg_slcr_seed_set(payload, seed); 1418 } 1419 1420 /* SLCOR - Switch LAG Collector Register 1421 * ------------------------------------- 1422 * The Switch LAG Collector register controls the Local Port membership 1423 * in a LAG and enablement of the collector. 1424 */ 1425 #define MLXSW_REG_SLCOR_ID 0x2016 1426 #define MLXSW_REG_SLCOR_LEN 0x10 1427 1428 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1429 1430 enum mlxsw_reg_slcor_col { 1431 /* Port is added with collector disabled */ 1432 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1433 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1435 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1436 }; 1437 1438 /* reg_slcor_col 1439 * Collector configuration 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1443 1444 /* reg_slcor_local_port 1445 * Local port number 1446 * Not supported for CPU port 1447 * Access: Index 1448 */ 1449 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1450 1451 /* reg_slcor_lag_id 1452 * LAG Identifier. Index into the LAG descriptor table. 1453 * Access: Index 1454 */ 1455 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1456 1457 /* reg_slcor_port_index 1458 * Port index in the LAG list. Only valid on Add Port to LAG col. 1459 * Valid range is from 0 to cap_max_lag_members-1 1460 * Access: RW 1461 */ 1462 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1463 1464 static inline void mlxsw_reg_slcor_pack(char *payload, 1465 u16 local_port, u16 lag_id, 1466 enum mlxsw_reg_slcor_col col) 1467 { 1468 MLXSW_REG_ZERO(slcor, payload); 1469 mlxsw_reg_slcor_col_set(payload, col); 1470 mlxsw_reg_slcor_local_port_set(payload, local_port); 1471 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1472 } 1473 1474 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1475 u16 local_port, u16 lag_id, 1476 u8 port_index) 1477 { 1478 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1479 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1480 mlxsw_reg_slcor_port_index_set(payload, port_index); 1481 } 1482 1483 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1484 u16 local_port, u16 lag_id) 1485 { 1486 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1487 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1488 } 1489 1490 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1491 u16 local_port, u16 lag_id) 1492 { 1493 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1495 } 1496 1497 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1498 u16 local_port, u16 lag_id) 1499 { 1500 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1501 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1502 } 1503 1504 /* SPMLR - Switch Port MAC Learning Register 1505 * ----------------------------------------- 1506 * Controls the Switch MAC learning policy per port. 1507 */ 1508 #define MLXSW_REG_SPMLR_ID 0x2018 1509 #define MLXSW_REG_SPMLR_LEN 0x8 1510 1511 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1512 1513 /* reg_spmlr_local_port 1514 * Local port number. 1515 * Access: Index 1516 */ 1517 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1518 1519 /* reg_spmlr_sub_port 1520 * Virtual port within the physical port. 1521 * Should be set to 0 when virtual ports are not enabled on the port. 1522 * Access: Index 1523 */ 1524 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1525 1526 enum mlxsw_reg_spmlr_learn_mode { 1527 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1528 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1529 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1530 }; 1531 1532 /* reg_spmlr_learn_mode 1533 * Learning mode on the port. 1534 * 0 - Learning disabled. 1535 * 2 - Learning enabled. 1536 * 3 - Security mode. 1537 * 1538 * In security mode the switch does not learn MACs on the port, but uses the 1539 * SMAC to see if it exists on another ingress port. If so, the packet is 1540 * classified as a bad packet and is discarded unless the software registers 1541 * to receive port security error packets usign HPKT. 1542 */ 1543 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1544 1545 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1546 enum mlxsw_reg_spmlr_learn_mode mode) 1547 { 1548 MLXSW_REG_ZERO(spmlr, payload); 1549 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1550 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1551 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1552 } 1553 1554 /* SVFA - Switch VID to FID Allocation Register 1555 * -------------------------------------------- 1556 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1557 * virtualized ports. 1558 */ 1559 #define MLXSW_REG_SVFA_ID 0x201C 1560 #define MLXSW_REG_SVFA_LEN 0x18 1561 1562 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1563 1564 /* reg_svfa_swid 1565 * Switch partition ID. 1566 * Access: Index 1567 */ 1568 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1569 1570 /* reg_svfa_local_port 1571 * Local port number. 1572 * Access: Index 1573 * 1574 * Note: Reserved for 802.1Q FIDs. 1575 */ 1576 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1577 1578 enum mlxsw_reg_svfa_mt { 1579 MLXSW_REG_SVFA_MT_VID_TO_FID, 1580 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1581 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1582 }; 1583 1584 /* reg_svfa_mapping_table 1585 * Mapping table: 1586 * 0 - VID to FID 1587 * 1 - {Port, VID} to FID 1588 * Access: Index 1589 * 1590 * Note: Reserved for SwitchX-2. 1591 */ 1592 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1593 1594 /* reg_svfa_v 1595 * Valid. 1596 * Valid if set. 1597 * Access: RW 1598 * 1599 * Note: Reserved for SwitchX-2. 1600 */ 1601 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1602 1603 /* reg_svfa_fid 1604 * Filtering ID. 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1608 1609 /* reg_svfa_vid 1610 * VLAN ID. 1611 * Access: Index 1612 */ 1613 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1614 1615 /* reg_svfa_counter_set_type 1616 * Counter set type for flow counters. 1617 * Access: RW 1618 * 1619 * Note: Reserved for SwitchX-2. 1620 */ 1621 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1622 1623 /* reg_svfa_counter_index 1624 * Counter index for flow counters. 1625 * Access: RW 1626 * 1627 * Note: Reserved for SwitchX-2. 1628 */ 1629 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1630 1631 /* reg_svfa_vni 1632 * Virtual Network Identifier. 1633 * Access: Index 1634 * 1635 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1636 */ 1637 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1638 1639 /* reg_svfa_irif_v 1640 * Ingress RIF valid. 1641 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1642 * 1 - Ingress RIF valid. 1643 * Must not be set for a non enabled RIF. 1644 * Access: RW 1645 * 1646 * Note: Reserved when legacy bridge model is used. 1647 */ 1648 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1649 1650 /* reg_svfa_irif 1651 * Ingress RIF (Router Interface). 1652 * Range is 0..cap_max_router_interfaces-1. 1653 * Access: RW 1654 * 1655 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1656 */ 1657 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1658 1659 static inline void __mlxsw_reg_svfa_pack(char *payload, 1660 enum mlxsw_reg_svfa_mt mt, bool valid, 1661 u16 fid, bool irif_v, u16 irif) 1662 { 1663 MLXSW_REG_ZERO(svfa, payload); 1664 mlxsw_reg_svfa_swid_set(payload, 0); 1665 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1666 mlxsw_reg_svfa_v_set(payload, valid); 1667 mlxsw_reg_svfa_fid_set(payload, fid); 1668 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1669 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1670 } 1671 1672 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1673 bool valid, u16 fid, u16 vid, 1674 bool irif_v, u16 irif) 1675 { 1676 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1677 1678 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1679 mlxsw_reg_svfa_local_port_set(payload, local_port); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1684 u16 vid, bool irif_v, u16 irif) 1685 { 1686 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1687 1688 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1689 mlxsw_reg_svfa_vid_set(payload, vid); 1690 } 1691 1692 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1693 u32 vni, bool irif_v, u16 irif) 1694 { 1695 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1696 1697 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1698 mlxsw_reg_svfa_vni_set(payload, vni); 1699 } 1700 1701 /* SPVTR - Switch Port VLAN Stacking Register 1702 * ------------------------------------------ 1703 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1704 * to enable VLAN stacking. 1705 */ 1706 #define MLXSW_REG_SPVTR_ID 0x201D 1707 #define MLXSW_REG_SPVTR_LEN 0x10 1708 1709 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1710 1711 /* reg_spvtr_tport 1712 * Port is tunnel port. 1713 * Access: Index 1714 * 1715 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1716 */ 1717 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1718 1719 /* reg_spvtr_local_port 1720 * When tport = 0: local port number (Not supported from/to CPU). 1721 * When tport = 1: tunnel port. 1722 * Access: Index 1723 */ 1724 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1725 1726 /* reg_spvtr_ippe 1727 * Ingress Port Prio Mode Update Enable. 1728 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1729 * Reserved on Get operations. 1730 * Access: OP 1731 */ 1732 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1733 1734 /* reg_spvtr_ipve 1735 * Ingress Port VID Mode Update Enable. 1736 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1737 * field. 1738 * Reserved on Get operations. 1739 * Access: OP 1740 */ 1741 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1742 1743 /* reg_spvtr_epve 1744 * Egress Port VID Mode Update Enable. 1745 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1746 * field. 1747 * Access: OP 1748 */ 1749 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1750 1751 /* reg_spvtr_ipprio_mode 1752 * Ingress Port Priority Mode. 1753 * This controls the PCP and DEI of the new outer VLAN 1754 * Note: for SwitchX/-2 the DEI is not affected. 1755 * 0: use port default PCP and DEI (configured by QPDPC). 1756 * 1: use C-VLAN PCP and DEI. 1757 * Has no effect when ipvid_mode = 0. 1758 * Reserved when tport = 1. 1759 * Access: RW 1760 */ 1761 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1762 1763 enum mlxsw_reg_spvtr_ipvid_mode { 1764 /* IEEE Compliant PVID (default) */ 1765 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1766 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1767 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1768 /* Always push VLAN (also for prio tagged packets) */ 1769 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1770 }; 1771 1772 /* reg_spvtr_ipvid_mode 1773 * Ingress Port VLAN-ID Mode. 1774 * For Spectrum family, this affects the values of SPVM.i 1775 * Access: RW 1776 */ 1777 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1778 1779 enum mlxsw_reg_spvtr_epvid_mode { 1780 /* IEEE Compliant VLAN membership */ 1781 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1782 /* Pop VLAN (for VLAN stacking) */ 1783 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1784 }; 1785 1786 /* reg_spvtr_epvid_mode 1787 * Egress Port VLAN-ID Mode. 1788 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1789 * Access: WO 1790 */ 1791 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1792 1793 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1794 u16 local_port, 1795 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1796 { 1797 MLXSW_REG_ZERO(spvtr, payload); 1798 mlxsw_reg_spvtr_tport_set(payload, tport); 1799 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1800 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1801 mlxsw_reg_spvtr_ipve_set(payload, true); 1802 } 1803 1804 /* SVPE - Switch Virtual-Port Enabling Register 1805 * -------------------------------------------- 1806 * Enables port virtualization. 1807 */ 1808 #define MLXSW_REG_SVPE_ID 0x201E 1809 #define MLXSW_REG_SVPE_LEN 0x4 1810 1811 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1812 1813 /* reg_svpe_local_port 1814 * Local port number 1815 * Access: Index 1816 * 1817 * Note: CPU port is not supported (uses VLAN mode only). 1818 */ 1819 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1820 1821 /* reg_svpe_vp_en 1822 * Virtual port enable. 1823 * 0 - Disable, VLAN mode (VID to FID). 1824 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1825 * Access: RW 1826 */ 1827 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1828 1829 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1830 bool enable) 1831 { 1832 MLXSW_REG_ZERO(svpe, payload); 1833 mlxsw_reg_svpe_local_port_set(payload, local_port); 1834 mlxsw_reg_svpe_vp_en_set(payload, enable); 1835 } 1836 1837 /* SFMR - Switch FID Management Register 1838 * ------------------------------------- 1839 * Creates and configures FIDs. 1840 */ 1841 #define MLXSW_REG_SFMR_ID 0x201F 1842 #define MLXSW_REG_SFMR_LEN 0x30 1843 1844 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1845 1846 enum mlxsw_reg_sfmr_op { 1847 MLXSW_REG_SFMR_OP_CREATE_FID, 1848 MLXSW_REG_SFMR_OP_DESTROY_FID, 1849 }; 1850 1851 /* reg_sfmr_op 1852 * Operation. 1853 * 0 - Create or edit FID. 1854 * 1 - Destroy FID. 1855 * Access: WO 1856 */ 1857 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1858 1859 /* reg_sfmr_fid 1860 * Filtering ID. 1861 * Access: Index 1862 */ 1863 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1864 1865 /* reg_sfmr_flood_rsp 1866 * Router sub-port flooding table. 1867 * 0 - Regular flooding table. 1868 * 1 - Router sub-port flooding table. For this FID the flooding is per 1869 * router-sub-port local_port. Must not be set for a FID which is not a 1870 * router-sub-port and must be set prior to enabling the relevant RIF. 1871 * Access: RW 1872 * 1873 * Note: Reserved when legacy bridge model is used. 1874 */ 1875 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1876 1877 /* reg_sfmr_flood_bridge_type 1878 * Flood bridge type (see SFGC.bridge_type). 1879 * 0 - type_0. 1880 * 1 - type_1. 1881 * Access: RW 1882 * 1883 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1884 */ 1885 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1886 1887 /* reg_sfmr_fid_offset 1888 * FID offset. 1889 * Used to point into the flooding table selected by SFGC register if 1890 * the table is of type FID-Offset. Otherwise, this field is reserved. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1894 1895 /* reg_sfmr_vtfp 1896 * Valid Tunnel Flood Pointer. 1897 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1898 * Access: RW 1899 * 1900 * Note: Reserved for 802.1Q FIDs. 1901 */ 1902 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1903 1904 /* reg_sfmr_nve_tunnel_flood_ptr 1905 * Underlay Flooding and BC Pointer. 1906 * Used as a pointer to the first entry of the group based link lists of 1907 * flooding or BC entries (for NVE tunnels). 1908 * Access: RW 1909 */ 1910 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1911 1912 /* reg_sfmr_vv 1913 * VNI Valid. 1914 * If not set, then vni is reserved. 1915 * Access: RW 1916 * 1917 * Note: Reserved for 802.1Q FIDs. 1918 */ 1919 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1920 1921 /* reg_sfmr_vni 1922 * Virtual Network Identifier. 1923 * When legacy bridge model is used, a given VNI can only be assigned to one 1924 * FID. When unified bridge model is used, it configures only the FID->VNI, 1925 * the VNI->FID is done by SVFA. 1926 * Access: RW 1927 */ 1928 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1929 1930 /* reg_sfmr_irif_v 1931 * Ingress RIF valid. 1932 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1933 * 1 - Ingress RIF valid. 1934 * Must not be set for a non valid RIF. 1935 * Access: RW 1936 * 1937 * Note: Reserved when legacy bridge model is used. 1938 */ 1939 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1940 1941 /* reg_sfmr_irif 1942 * Ingress RIF (Router Interface). 1943 * Range is 0..cap_max_router_interfaces-1. 1944 * Access: RW 1945 * 1946 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1947 */ 1948 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1949 1950 /* reg_sfmr_smpe_valid 1951 * SMPE is valid. 1952 * Access: RW 1953 * 1954 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1955 * Spectrum-1. 1956 */ 1957 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1958 1959 /* reg_sfmr_smpe 1960 * Switch multicast port to egress VID. 1961 * Range is 0..cap_max_rmpe-1 1962 * Access: RW 1963 * 1964 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1965 * Spectrum-1. 1966 */ 1967 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1968 1969 static inline void mlxsw_reg_sfmr_pack(char *payload, 1970 enum mlxsw_reg_sfmr_op op, u16 fid, 1971 u16 fid_offset, bool flood_rsp, 1972 enum mlxsw_reg_bridge_type bridge_type, 1973 bool smpe_valid, u16 smpe) 1974 { 1975 MLXSW_REG_ZERO(sfmr, payload); 1976 mlxsw_reg_sfmr_op_set(payload, op); 1977 mlxsw_reg_sfmr_fid_set(payload, fid); 1978 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1979 mlxsw_reg_sfmr_vtfp_set(payload, false); 1980 mlxsw_reg_sfmr_vv_set(payload, false); 1981 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1982 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1983 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 1984 mlxsw_reg_sfmr_smpe_set(payload, smpe); 1985 } 1986 1987 /* SPVMLR - Switch Port VLAN MAC Learning Register 1988 * ----------------------------------------------- 1989 * Controls the switch MAC learning policy per {Port, VID}. 1990 */ 1991 #define MLXSW_REG_SPVMLR_ID 0x2020 1992 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1993 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1994 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1995 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1996 MLXSW_REG_SPVMLR_REC_LEN * \ 1997 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1998 1999 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 2000 2001 /* reg_spvmlr_local_port 2002 * Local ingress port. 2003 * Access: Index 2004 * 2005 * Note: CPU port is not supported. 2006 */ 2007 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 2008 2009 /* reg_spvmlr_num_rec 2010 * Number of records to update. 2011 * Access: OP 2012 */ 2013 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2014 2015 /* reg_spvmlr_rec_learn_enable 2016 * 0 - Disable learning for {Port, VID}. 2017 * 1 - Enable learning for {Port, VID}. 2018 * Access: RW 2019 */ 2020 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2021 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2022 2023 /* reg_spvmlr_rec_vid 2024 * VLAN ID to be added/removed from port or for querying. 2025 * Access: Index 2026 */ 2027 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2028 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2029 2030 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2031 u16 vid_begin, u16 vid_end, 2032 bool learn_enable) 2033 { 2034 int num_rec = vid_end - vid_begin + 1; 2035 int i; 2036 2037 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2038 2039 MLXSW_REG_ZERO(spvmlr, payload); 2040 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2041 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2042 2043 for (i = 0; i < num_rec; i++) { 2044 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2045 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2046 } 2047 } 2048 2049 /* SPVC - Switch Port VLAN Classification Register 2050 * ----------------------------------------------- 2051 * Configures the port to identify packets as untagged / single tagged / 2052 * double packets based on the packet EtherTypes. 2053 * Ethertype IDs are configured by SVER. 2054 */ 2055 #define MLXSW_REG_SPVC_ID 0x2026 2056 #define MLXSW_REG_SPVC_LEN 0x0C 2057 2058 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2059 2060 /* reg_spvc_local_port 2061 * Local port. 2062 * Access: Index 2063 * 2064 * Note: applies both to Rx port and Tx port, so if a packet traverses 2065 * through Rx port i and a Tx port j then port i and port j must have the 2066 * same configuration. 2067 */ 2068 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2069 2070 /* reg_spvc_inner_et2 2071 * Vlan Tag1 EtherType2 enable. 2072 * Packet is initially classified as double VLAN Tag if in addition to 2073 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2074 * equal to ether_type2. 2075 * 0: disable (default) 2076 * 1: enable 2077 * Access: RW 2078 */ 2079 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2080 2081 /* reg_spvc_et2 2082 * Vlan Tag0 EtherType2 enable. 2083 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2084 * equal to ether_type2. 2085 * 0: disable (default) 2086 * 1: enable 2087 * Access: RW 2088 */ 2089 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2090 2091 /* reg_spvc_inner_et1 2092 * Vlan Tag1 EtherType1 enable. 2093 * Packet is initially classified as double VLAN Tag if in addition to 2094 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2095 * equal to ether_type1. 2096 * 0: disable 2097 * 1: enable (default) 2098 * Access: RW 2099 */ 2100 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2101 2102 /* reg_spvc_et1 2103 * Vlan Tag0 EtherType1 enable. 2104 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2105 * equal to ether_type1. 2106 * 0: disable 2107 * 1: enable (default) 2108 * Access: RW 2109 */ 2110 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2111 2112 /* reg_inner_et0 2113 * Vlan Tag1 EtherType0 enable. 2114 * Packet is initially classified as double VLAN Tag if in addition to 2115 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2116 * equal to ether_type0. 2117 * 0: disable 2118 * 1: enable (default) 2119 * Access: RW 2120 */ 2121 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2122 2123 /* reg_et0 2124 * Vlan Tag0 EtherType0 enable. 2125 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2126 * equal to ether_type0. 2127 * 0: disable 2128 * 1: enable (default) 2129 * Access: RW 2130 */ 2131 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2132 2133 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2134 bool et0) 2135 { 2136 MLXSW_REG_ZERO(spvc, payload); 2137 mlxsw_reg_spvc_local_port_set(payload, local_port); 2138 /* Enable inner_et1 and inner_et0 to enable identification of double 2139 * tagged packets. 2140 */ 2141 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2142 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2143 mlxsw_reg_spvc_et1_set(payload, et1); 2144 mlxsw_reg_spvc_et0_set(payload, et0); 2145 } 2146 2147 /* SPEVET - Switch Port Egress VLAN EtherType 2148 * ------------------------------------------ 2149 * The switch port egress VLAN EtherType configures which EtherType to push at 2150 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2151 * is set. 2152 */ 2153 #define MLXSW_REG_SPEVET_ID 0x202A 2154 #define MLXSW_REG_SPEVET_LEN 0x08 2155 2156 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2157 2158 /* reg_spevet_local_port 2159 * Egress Local port number. 2160 * Not supported to CPU port. 2161 * Access: Index 2162 */ 2163 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2164 2165 /* reg_spevet_et_vlan 2166 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2167 * 0: ether_type0 - (default) 2168 * 1: ether_type1 2169 * 2: ether_type2 2170 * Access: RW 2171 */ 2172 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2173 2174 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2175 u8 et_vlan) 2176 { 2177 MLXSW_REG_ZERO(spevet, payload); 2178 mlxsw_reg_spevet_local_port_set(payload, local_port); 2179 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2180 } 2181 2182 /* SMPE - Switch Multicast Port to Egress VID 2183 * ------------------------------------------ 2184 * The switch multicast port to egress VID maps 2185 * {egress_port, SMPE index} -> {VID}. 2186 */ 2187 #define MLXSW_REG_SMPE_ID 0x202B 2188 #define MLXSW_REG_SMPE_LEN 0x0C 2189 2190 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2191 2192 /* reg_smpe_local_port 2193 * Local port number. 2194 * CPU port is not supported. 2195 * Access: Index 2196 */ 2197 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2198 2199 /* reg_smpe_smpe_index 2200 * Switch multicast port to egress VID. 2201 * Range is 0..cap_max_rmpe-1. 2202 * Access: Index 2203 */ 2204 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2205 2206 /* reg_smpe_evid 2207 * Egress VID. 2208 * Access: RW 2209 */ 2210 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2211 2212 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2213 u16 smpe_index, u16 evid) 2214 { 2215 MLXSW_REG_ZERO(smpe, payload); 2216 mlxsw_reg_smpe_local_port_set(payload, local_port); 2217 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2218 mlxsw_reg_smpe_evid_set(payload, evid); 2219 } 2220 2221 /* SFTR-V2 - Switch Flooding Table Version 2 Register 2222 * -------------------------------------------------- 2223 * The switch flooding table is used for flooding packet replication. The table 2224 * defines a bit mask of ports for packet replication. 2225 */ 2226 #define MLXSW_REG_SFTR2_ID 0x202F 2227 #define MLXSW_REG_SFTR2_LEN 0x120 2228 2229 MLXSW_REG_DEFINE(sftr2, MLXSW_REG_SFTR2_ID, MLXSW_REG_SFTR2_LEN); 2230 2231 /* reg_sftr2_swid 2232 * Switch partition ID with which to associate the port. 2233 * Access: Index 2234 */ 2235 MLXSW_ITEM32(reg, sftr2, swid, 0x00, 24, 8); 2236 2237 /* reg_sftr2_flood_table 2238 * Flooding table index to associate with the specific type on the specific 2239 * switch partition. 2240 * Access: Index 2241 */ 2242 MLXSW_ITEM32(reg, sftr2, flood_table, 0x00, 16, 6); 2243 2244 /* reg_sftr2_index 2245 * Index. Used as an index into the Flooding Table in case the table is 2246 * configured to use VID / FID or FID Offset. 2247 * Access: Index 2248 */ 2249 MLXSW_ITEM32(reg, sftr2, index, 0x00, 0, 16); 2250 2251 /* reg_sftr2_table_type 2252 * See mlxsw_flood_table_type 2253 * Access: RW 2254 */ 2255 MLXSW_ITEM32(reg, sftr2, table_type, 0x04, 16, 3); 2256 2257 /* reg_sftr2_range 2258 * Range of entries to update 2259 * Access: Index 2260 */ 2261 MLXSW_ITEM32(reg, sftr2, range, 0x04, 0, 16); 2262 2263 /* reg_sftr2_port 2264 * Local port membership (1 bit per port). 2265 * Access: RW 2266 */ 2267 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port, 0x20, 0x80, 1); 2268 2269 /* reg_sftr2_port_mask 2270 * Local port mask (1 bit per port). 2271 * Access: WO 2272 */ 2273 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port_mask, 0xA0, 0x80, 1); 2274 2275 static inline void mlxsw_reg_sftr2_pack(char *payload, 2276 unsigned int flood_table, 2277 unsigned int index, 2278 enum mlxsw_flood_table_type table_type, 2279 unsigned int range, u16 port, bool set) 2280 { 2281 MLXSW_REG_ZERO(sftr2, payload); 2282 mlxsw_reg_sftr2_swid_set(payload, 0); 2283 mlxsw_reg_sftr2_flood_table_set(payload, flood_table); 2284 mlxsw_reg_sftr2_index_set(payload, index); 2285 mlxsw_reg_sftr2_table_type_set(payload, table_type); 2286 mlxsw_reg_sftr2_range_set(payload, range); 2287 mlxsw_reg_sftr2_port_set(payload, port, set); 2288 mlxsw_reg_sftr2_port_mask_set(payload, port, 1); 2289 } 2290 2291 /* SMID-V2 - Switch Multicast ID Version 2 Register 2292 * ------------------------------------------------ 2293 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2294 * of the multicast group within the stacking domain, into a list of local 2295 * ports into which the packet is replicated. 2296 */ 2297 #define MLXSW_REG_SMID2_ID 0x2034 2298 #define MLXSW_REG_SMID2_LEN 0x120 2299 2300 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2301 2302 /* reg_smid2_swid 2303 * Switch partition ID. 2304 * Access: Index 2305 */ 2306 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2307 2308 /* reg_smid2_mid 2309 * Multicast identifier - global identifier that represents the multicast group 2310 * across all devices. 2311 * Access: Index 2312 */ 2313 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2314 2315 /* reg_smid2_smpe_valid 2316 * SMPE is valid. 2317 * When not valid, the egress VID will not be modified by the SMPE table. 2318 * Access: RW 2319 * 2320 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2321 */ 2322 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2323 2324 /* reg_smid2_smpe 2325 * Switch multicast port to egress VID. 2326 * Access: RW 2327 * 2328 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2329 */ 2330 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2331 2332 /* reg_smid2_port 2333 * Local port memebership (1 bit per port). 2334 * Access: RW 2335 */ 2336 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2337 2338 /* reg_smid2_port_mask 2339 * Local port mask (1 bit per port). 2340 * Access: WO 2341 */ 2342 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2343 2344 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2345 bool set, bool smpe_valid, u16 smpe) 2346 { 2347 MLXSW_REG_ZERO(smid2, payload); 2348 mlxsw_reg_smid2_swid_set(payload, 0); 2349 mlxsw_reg_smid2_mid_set(payload, mid); 2350 mlxsw_reg_smid2_port_set(payload, port, set); 2351 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2352 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2353 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2354 } 2355 2356 /* CWTP - Congetion WRED ECN TClass Profile 2357 * ---------------------------------------- 2358 * Configures the profiles for queues of egress port and traffic class 2359 */ 2360 #define MLXSW_REG_CWTP_ID 0x2802 2361 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2362 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2363 #define MLXSW_REG_CWTP_LEN 0x40 2364 2365 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2366 2367 /* reg_cwtp_local_port 2368 * Local port number 2369 * Not supported for CPU port 2370 * Access: Index 2371 */ 2372 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2373 2374 /* reg_cwtp_traffic_class 2375 * Traffic Class to configure 2376 * Access: Index 2377 */ 2378 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2379 2380 /* reg_cwtp_profile_min 2381 * Minimum Average Queue Size of the profile in cells. 2382 * Access: RW 2383 */ 2384 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2385 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2386 2387 /* reg_cwtp_profile_percent 2388 * Percentage of WRED and ECN marking for maximum Average Queue size 2389 * Range is 0 to 100, units of integer percentage 2390 * Access: RW 2391 */ 2392 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2393 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2394 2395 /* reg_cwtp_profile_max 2396 * Maximum Average Queue size of the profile in cells 2397 * Access: RW 2398 */ 2399 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2400 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2401 2402 #define MLXSW_REG_CWTP_MIN_VALUE 64 2403 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2404 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2405 2406 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2407 u8 traffic_class) 2408 { 2409 int i; 2410 2411 MLXSW_REG_ZERO(cwtp, payload); 2412 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2413 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2414 2415 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2416 mlxsw_reg_cwtp_profile_min_set(payload, i, 2417 MLXSW_REG_CWTP_MIN_VALUE); 2418 mlxsw_reg_cwtp_profile_max_set(payload, i, 2419 MLXSW_REG_CWTP_MIN_VALUE); 2420 } 2421 } 2422 2423 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2424 2425 static inline void 2426 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2427 u32 probability) 2428 { 2429 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2430 2431 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2432 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2433 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2434 } 2435 2436 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2437 * --------------------------------------------------- 2438 * The CWTPM register maps each egress port and traffic class to profile num. 2439 */ 2440 #define MLXSW_REG_CWTPM_ID 0x2803 2441 #define MLXSW_REG_CWTPM_LEN 0x44 2442 2443 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2444 2445 /* reg_cwtpm_local_port 2446 * Local port number 2447 * Not supported for CPU port 2448 * Access: Index 2449 */ 2450 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2451 2452 /* reg_cwtpm_traffic_class 2453 * Traffic Class to configure 2454 * Access: Index 2455 */ 2456 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2457 2458 /* reg_cwtpm_ew 2459 * Control enablement of WRED for traffic class: 2460 * 0 - Disable 2461 * 1 - Enable 2462 * Access: RW 2463 */ 2464 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2465 2466 /* reg_cwtpm_ee 2467 * Control enablement of ECN for traffic class: 2468 * 0 - Disable 2469 * 1 - Enable 2470 * Access: RW 2471 */ 2472 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2473 2474 /* reg_cwtpm_tcp_g 2475 * TCP Green Profile. 2476 * Index of the profile within {port, traffic class} to use. 2477 * 0 for disabling both WRED and ECN for this type of traffic. 2478 * Access: RW 2479 */ 2480 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2481 2482 /* reg_cwtpm_tcp_y 2483 * TCP Yellow Profile. 2484 * Index of the profile within {port, traffic class} to use. 2485 * 0 for disabling both WRED and ECN for this type of traffic. 2486 * Access: RW 2487 */ 2488 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2489 2490 /* reg_cwtpm_tcp_r 2491 * TCP Red Profile. 2492 * Index of the profile within {port, traffic class} to use. 2493 * 0 for disabling both WRED and ECN for this type of traffic. 2494 * Access: RW 2495 */ 2496 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2497 2498 /* reg_cwtpm_ntcp_g 2499 * Non-TCP Green Profile. 2500 * Index of the profile within {port, traffic class} to use. 2501 * 0 for disabling both WRED and ECN for this type of traffic. 2502 * Access: RW 2503 */ 2504 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2505 2506 /* reg_cwtpm_ntcp_y 2507 * Non-TCP Yellow Profile. 2508 * Index of the profile within {port, traffic class} to use. 2509 * 0 for disabling both WRED and ECN for this type of traffic. 2510 * Access: RW 2511 */ 2512 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2513 2514 /* reg_cwtpm_ntcp_r 2515 * Non-TCP Red Profile. 2516 * Index of the profile within {port, traffic class} to use. 2517 * 0 for disabling both WRED and ECN for this type of traffic. 2518 * Access: RW 2519 */ 2520 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2521 2522 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2523 2524 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2525 u8 traffic_class, u8 profile, 2526 bool wred, bool ecn) 2527 { 2528 MLXSW_REG_ZERO(cwtpm, payload); 2529 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2530 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2531 mlxsw_reg_cwtpm_ew_set(payload, wred); 2532 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2533 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2534 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2535 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2536 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2537 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2538 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2539 } 2540 2541 /* PGCR - Policy-Engine General Configuration Register 2542 * --------------------------------------------------- 2543 * This register configures general Policy-Engine settings. 2544 */ 2545 #define MLXSW_REG_PGCR_ID 0x3001 2546 #define MLXSW_REG_PGCR_LEN 0x20 2547 2548 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2549 2550 /* reg_pgcr_default_action_pointer_base 2551 * Default action pointer base. Each region has a default action pointer 2552 * which is equal to default_action_pointer_base + region_id. 2553 * Access: RW 2554 */ 2555 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2556 2557 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2558 { 2559 MLXSW_REG_ZERO(pgcr, payload); 2560 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2561 } 2562 2563 /* PPBT - Policy-Engine Port Binding Table 2564 * --------------------------------------- 2565 * This register is used for configuration of the Port Binding Table. 2566 */ 2567 #define MLXSW_REG_PPBT_ID 0x3002 2568 #define MLXSW_REG_PPBT_LEN 0x14 2569 2570 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2571 2572 enum mlxsw_reg_pxbt_e { 2573 MLXSW_REG_PXBT_E_IACL, 2574 MLXSW_REG_PXBT_E_EACL, 2575 }; 2576 2577 /* reg_ppbt_e 2578 * Access: Index 2579 */ 2580 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2581 2582 enum mlxsw_reg_pxbt_op { 2583 MLXSW_REG_PXBT_OP_BIND, 2584 MLXSW_REG_PXBT_OP_UNBIND, 2585 }; 2586 2587 /* reg_ppbt_op 2588 * Access: RW 2589 */ 2590 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2591 2592 /* reg_ppbt_local_port 2593 * Local port. Not including CPU port. 2594 * Access: Index 2595 */ 2596 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2597 2598 /* reg_ppbt_g 2599 * group - When set, the binding is of an ACL group. When cleared, 2600 * the binding is of an ACL. 2601 * Must be set to 1 for Spectrum. 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2605 2606 /* reg_ppbt_acl_info 2607 * ACL/ACL group identifier. If the g bit is set, this field should hold 2608 * the acl_group_id, else it should hold the acl_id. 2609 * Access: RW 2610 */ 2611 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2612 2613 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2614 enum mlxsw_reg_pxbt_op op, 2615 u16 local_port, u16 acl_info) 2616 { 2617 MLXSW_REG_ZERO(ppbt, payload); 2618 mlxsw_reg_ppbt_e_set(payload, e); 2619 mlxsw_reg_ppbt_op_set(payload, op); 2620 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2621 mlxsw_reg_ppbt_g_set(payload, true); 2622 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2623 } 2624 2625 /* PACL - Policy-Engine ACL Register 2626 * --------------------------------- 2627 * This register is used for configuration of the ACL. 2628 */ 2629 #define MLXSW_REG_PACL_ID 0x3004 2630 #define MLXSW_REG_PACL_LEN 0x70 2631 2632 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2633 2634 /* reg_pacl_v 2635 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2636 * while the ACL is bounded to either a port, VLAN or ACL rule. 2637 * Access: RW 2638 */ 2639 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2640 2641 /* reg_pacl_acl_id 2642 * An identifier representing the ACL (managed by software) 2643 * Range 0 .. cap_max_acl_regions - 1 2644 * Access: Index 2645 */ 2646 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2647 2648 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2649 2650 /* reg_pacl_tcam_region_info 2651 * Opaque object that represents a TCAM region. 2652 * Obtained through PTAR register. 2653 * Access: RW 2654 */ 2655 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2656 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2657 2658 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2659 bool valid, const char *tcam_region_info) 2660 { 2661 MLXSW_REG_ZERO(pacl, payload); 2662 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2663 mlxsw_reg_pacl_v_set(payload, valid); 2664 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2665 } 2666 2667 /* PAGT - Policy-Engine ACL Group Table 2668 * ------------------------------------ 2669 * This register is used for configuration of the ACL Group Table. 2670 */ 2671 #define MLXSW_REG_PAGT_ID 0x3005 2672 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2673 #define MLXSW_REG_PAGT_ACL_LEN 4 2674 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2675 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2676 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2677 2678 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2679 2680 /* reg_pagt_size 2681 * Number of ACLs in the group. 2682 * Size 0 invalidates a group. 2683 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2684 * Total number of ACLs in all groups must be lower or equal 2685 * to cap_max_acl_tot_groups 2686 * Note: a group which is binded must not be invalidated 2687 * Access: Index 2688 */ 2689 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2690 2691 /* reg_pagt_acl_group_id 2692 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2693 * the ACL Group identifier (managed by software). 2694 * Access: Index 2695 */ 2696 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2697 2698 /* reg_pagt_multi 2699 * Multi-ACL 2700 * 0 - This ACL is the last ACL in the multi-ACL 2701 * 1 - This ACL is part of a multi-ACL 2702 * Access: RW 2703 */ 2704 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2705 2706 /* reg_pagt_acl_id 2707 * ACL identifier 2708 * Access: RW 2709 */ 2710 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2711 2712 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2713 { 2714 MLXSW_REG_ZERO(pagt, payload); 2715 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2716 } 2717 2718 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2719 u16 acl_id, bool multi) 2720 { 2721 u8 size = mlxsw_reg_pagt_size_get(payload); 2722 2723 if (index >= size) 2724 mlxsw_reg_pagt_size_set(payload, index + 1); 2725 mlxsw_reg_pagt_multi_set(payload, index, multi); 2726 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2727 } 2728 2729 /* PTAR - Policy-Engine TCAM Allocation Register 2730 * --------------------------------------------- 2731 * This register is used for allocation of regions in the TCAM. 2732 * Note: Query method is not supported on this register. 2733 */ 2734 #define MLXSW_REG_PTAR_ID 0x3006 2735 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2736 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2737 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2738 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2739 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2740 2741 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2742 2743 enum mlxsw_reg_ptar_op { 2744 /* allocate a TCAM region */ 2745 MLXSW_REG_PTAR_OP_ALLOC, 2746 /* resize a TCAM region */ 2747 MLXSW_REG_PTAR_OP_RESIZE, 2748 /* deallocate TCAM region */ 2749 MLXSW_REG_PTAR_OP_FREE, 2750 /* test allocation */ 2751 MLXSW_REG_PTAR_OP_TEST, 2752 }; 2753 2754 /* reg_ptar_op 2755 * Access: OP 2756 */ 2757 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2758 2759 /* reg_ptar_action_set_type 2760 * Type of action set to be used on this region. 2761 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2762 * Access: WO 2763 */ 2764 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2765 2766 enum mlxsw_reg_ptar_key_type { 2767 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2768 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2769 }; 2770 2771 /* reg_ptar_key_type 2772 * TCAM key type for the region. 2773 * Access: WO 2774 */ 2775 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2776 2777 /* reg_ptar_region_size 2778 * TCAM region size. When allocating/resizing this is the requested size, 2779 * the response is the actual size. Note that actual size may be 2780 * larger than requested. 2781 * Allowed range 1 .. cap_max_rules-1 2782 * Reserved during op deallocate. 2783 * Access: WO 2784 */ 2785 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2786 2787 /* reg_ptar_region_id 2788 * Region identifier 2789 * Range 0 .. cap_max_regions-1 2790 * Access: Index 2791 */ 2792 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2793 2794 /* reg_ptar_tcam_region_info 2795 * Opaque object that represents the TCAM region. 2796 * Returned when allocating a region. 2797 * Provided by software for ACL generation and region deallocation and resize. 2798 * Access: RW 2799 */ 2800 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2801 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2802 2803 /* reg_ptar_flexible_key_id 2804 * Identifier of the Flexible Key. 2805 * Only valid if key_type == "FLEX_KEY" 2806 * The key size will be rounded up to one of the following values: 2807 * 9B, 18B, 36B, 54B. 2808 * This field is reserved for in resize operation. 2809 * Access: WO 2810 */ 2811 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2812 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2813 2814 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2815 enum mlxsw_reg_ptar_key_type key_type, 2816 u16 region_size, u16 region_id, 2817 const char *tcam_region_info) 2818 { 2819 MLXSW_REG_ZERO(ptar, payload); 2820 mlxsw_reg_ptar_op_set(payload, op); 2821 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2822 mlxsw_reg_ptar_key_type_set(payload, key_type); 2823 mlxsw_reg_ptar_region_size_set(payload, region_size); 2824 mlxsw_reg_ptar_region_id_set(payload, region_id); 2825 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2826 } 2827 2828 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2829 u16 key_id) 2830 { 2831 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2832 } 2833 2834 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2835 { 2836 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2837 } 2838 2839 /* PPBS - Policy-Engine Policy Based Switching Register 2840 * ---------------------------------------------------- 2841 * This register retrieves and sets Policy Based Switching Table entries. 2842 */ 2843 #define MLXSW_REG_PPBS_ID 0x300C 2844 #define MLXSW_REG_PPBS_LEN 0x14 2845 2846 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2847 2848 /* reg_ppbs_pbs_ptr 2849 * Index into the PBS table. 2850 * For Spectrum, the index points to the KVD Linear. 2851 * Access: Index 2852 */ 2853 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2854 2855 /* reg_ppbs_system_port 2856 * Unique port identifier for the final destination of the packet. 2857 * Access: RW 2858 */ 2859 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2860 2861 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2862 u16 system_port) 2863 { 2864 MLXSW_REG_ZERO(ppbs, payload); 2865 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2866 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2867 } 2868 2869 /* PRCR - Policy-Engine Rules Copy Register 2870 * ---------------------------------------- 2871 * This register is used for accessing rules within a TCAM region. 2872 */ 2873 #define MLXSW_REG_PRCR_ID 0x300D 2874 #define MLXSW_REG_PRCR_LEN 0x40 2875 2876 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2877 2878 enum mlxsw_reg_prcr_op { 2879 /* Move rules. Moves the rules from "tcam_region_info" starting 2880 * at offset "offset" to "dest_tcam_region_info" 2881 * at offset "dest_offset." 2882 */ 2883 MLXSW_REG_PRCR_OP_MOVE, 2884 /* Copy rules. Copies the rules from "tcam_region_info" starting 2885 * at offset "offset" to "dest_tcam_region_info" 2886 * at offset "dest_offset." 2887 */ 2888 MLXSW_REG_PRCR_OP_COPY, 2889 }; 2890 2891 /* reg_prcr_op 2892 * Access: OP 2893 */ 2894 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2895 2896 /* reg_prcr_offset 2897 * Offset within the source region to copy/move from. 2898 * Access: Index 2899 */ 2900 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2901 2902 /* reg_prcr_size 2903 * The number of rules to copy/move. 2904 * Access: WO 2905 */ 2906 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2907 2908 /* reg_prcr_tcam_region_info 2909 * Opaque object that represents the source TCAM region. 2910 * Access: Index 2911 */ 2912 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2913 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2914 2915 /* reg_prcr_dest_offset 2916 * Offset within the source region to copy/move to. 2917 * Access: Index 2918 */ 2919 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2920 2921 /* reg_prcr_dest_tcam_region_info 2922 * Opaque object that represents the destination TCAM region. 2923 * Access: Index 2924 */ 2925 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2926 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2927 2928 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2929 const char *src_tcam_region_info, 2930 u16 src_offset, 2931 const char *dest_tcam_region_info, 2932 u16 dest_offset, u16 size) 2933 { 2934 MLXSW_REG_ZERO(prcr, payload); 2935 mlxsw_reg_prcr_op_set(payload, op); 2936 mlxsw_reg_prcr_offset_set(payload, src_offset); 2937 mlxsw_reg_prcr_size_set(payload, size); 2938 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2939 src_tcam_region_info); 2940 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2941 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2942 dest_tcam_region_info); 2943 } 2944 2945 /* PEFA - Policy-Engine Extended Flexible Action Register 2946 * ------------------------------------------------------ 2947 * This register is used for accessing an extended flexible action entry 2948 * in the central KVD Linear Database. 2949 */ 2950 #define MLXSW_REG_PEFA_ID 0x300F 2951 #define MLXSW_REG_PEFA_LEN 0xB0 2952 2953 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2954 2955 /* reg_pefa_index 2956 * Index in the KVD Linear Centralized Database. 2957 * Access: Index 2958 */ 2959 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2960 2961 /* reg_pefa_a 2962 * Index in the KVD Linear Centralized Database. 2963 * Activity 2964 * For a new entry: set if ca=0, clear if ca=1 2965 * Set if a packet lookup has hit on the specific entry 2966 * Access: RO 2967 */ 2968 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2969 2970 /* reg_pefa_ca 2971 * Clear activity 2972 * When write: activity is according to this field 2973 * When read: after reading the activity is cleared according to ca 2974 * Access: OP 2975 */ 2976 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2977 2978 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2979 2980 /* reg_pefa_flex_action_set 2981 * Action-set to perform when rule is matched. 2982 * Must be zero padded if action set is shorter. 2983 * Access: RW 2984 */ 2985 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2986 2987 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2988 const char *flex_action_set) 2989 { 2990 MLXSW_REG_ZERO(pefa, payload); 2991 mlxsw_reg_pefa_index_set(payload, index); 2992 mlxsw_reg_pefa_ca_set(payload, ca); 2993 if (flex_action_set) 2994 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2995 flex_action_set); 2996 } 2997 2998 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2999 { 3000 *p_a = mlxsw_reg_pefa_a_get(payload); 3001 } 3002 3003 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 3004 * -------------------------------------------------------------- 3005 * This register is used for binding Multicast router to an ACL group 3006 * that serves the MC router. 3007 * This register is not supported by SwitchX/-2 and Spectrum. 3008 */ 3009 #define MLXSW_REG_PEMRBT_ID 0x3014 3010 #define MLXSW_REG_PEMRBT_LEN 0x14 3011 3012 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 3013 3014 enum mlxsw_reg_pemrbt_protocol { 3015 MLXSW_REG_PEMRBT_PROTO_IPV4, 3016 MLXSW_REG_PEMRBT_PROTO_IPV6, 3017 }; 3018 3019 /* reg_pemrbt_protocol 3020 * Access: Index 3021 */ 3022 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 3023 3024 /* reg_pemrbt_group_id 3025 * ACL group identifier. 3026 * Range 0..cap_max_acl_groups-1 3027 * Access: RW 3028 */ 3029 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 3030 3031 static inline void 3032 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 3033 u16 group_id) 3034 { 3035 MLXSW_REG_ZERO(pemrbt, payload); 3036 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 3037 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 3038 } 3039 3040 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 3041 * ----------------------------------------------------- 3042 * This register is used for accessing rules within a TCAM region. 3043 * It is a new version of PTCE in order to support wider key, 3044 * mask and action within a TCAM region. This register is not supported 3045 * by SwitchX and SwitchX-2. 3046 */ 3047 #define MLXSW_REG_PTCE2_ID 0x3017 3048 #define MLXSW_REG_PTCE2_LEN 0x1D8 3049 3050 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3051 3052 /* reg_ptce2_v 3053 * Valid. 3054 * Access: RW 3055 */ 3056 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3057 3058 /* reg_ptce2_a 3059 * Activity. Set if a packet lookup has hit on the specific entry. 3060 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3061 * Access: RO 3062 */ 3063 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3064 3065 enum mlxsw_reg_ptce2_op { 3066 /* Read operation. */ 3067 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3068 /* clear on read operation. Used to read entry 3069 * and clear Activity bit. 3070 */ 3071 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3072 /* Write operation. Used to write a new entry to the table. 3073 * All R/W fields are relevant for new entry. Activity bit is set 3074 * for new entries - Note write with v = 0 will delete the entry. 3075 */ 3076 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3077 /* Update action. Only action set will be updated. */ 3078 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3079 /* Clear activity. A bit is cleared for the entry. */ 3080 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3081 }; 3082 3083 /* reg_ptce2_op 3084 * Access: OP 3085 */ 3086 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3087 3088 /* reg_ptce2_offset 3089 * Access: Index 3090 */ 3091 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3092 3093 /* reg_ptce2_priority 3094 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3095 * Note: priority does not have to be unique per rule. 3096 * Within a region, higher priority should have lower offset (no limitation 3097 * between regions in a multi-region). 3098 * Access: RW 3099 */ 3100 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3101 3102 /* reg_ptce2_tcam_region_info 3103 * Opaque object that represents the TCAM region. 3104 * Access: Index 3105 */ 3106 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3107 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3108 3109 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3110 3111 /* reg_ptce2_flex_key_blocks 3112 * ACL Key. 3113 * Access: RW 3114 */ 3115 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3116 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3117 3118 /* reg_ptce2_mask 3119 * mask- in the same size as key. A bit that is set directs the TCAM 3120 * to compare the corresponding bit in key. A bit that is clear directs 3121 * the TCAM to ignore the corresponding bit in key. 3122 * Access: RW 3123 */ 3124 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3125 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3126 3127 /* reg_ptce2_flex_action_set 3128 * ACL action set. 3129 * Access: RW 3130 */ 3131 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3132 MLXSW_REG_FLEX_ACTION_SET_LEN); 3133 3134 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3135 enum mlxsw_reg_ptce2_op op, 3136 const char *tcam_region_info, 3137 u16 offset, u32 priority) 3138 { 3139 MLXSW_REG_ZERO(ptce2, payload); 3140 mlxsw_reg_ptce2_v_set(payload, valid); 3141 mlxsw_reg_ptce2_op_set(payload, op); 3142 mlxsw_reg_ptce2_offset_set(payload, offset); 3143 mlxsw_reg_ptce2_priority_set(payload, priority); 3144 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3145 } 3146 3147 /* PERPT - Policy-Engine ERP Table Register 3148 * ---------------------------------------- 3149 * This register adds and removes eRPs from the eRP table. 3150 */ 3151 #define MLXSW_REG_PERPT_ID 0x3021 3152 #define MLXSW_REG_PERPT_LEN 0x80 3153 3154 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3155 3156 /* reg_perpt_erpt_bank 3157 * eRP table bank. 3158 * Range 0 .. cap_max_erp_table_banks - 1 3159 * Access: Index 3160 */ 3161 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3162 3163 /* reg_perpt_erpt_index 3164 * Index to eRP table within the eRP bank. 3165 * Range is 0 .. cap_max_erp_table_bank_size - 1 3166 * Access: Index 3167 */ 3168 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3169 3170 enum mlxsw_reg_perpt_key_size { 3171 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3172 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3173 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3174 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3175 }; 3176 3177 /* reg_perpt_key_size 3178 * Access: OP 3179 */ 3180 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3181 3182 /* reg_perpt_bf_bypass 3183 * 0 - The eRP is used only if bloom filter state is set for the given 3184 * rule. 3185 * 1 - The eRP is used regardless of bloom filter state. 3186 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3187 * Access: RW 3188 */ 3189 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3190 3191 /* reg_perpt_erp_id 3192 * eRP ID for use by the rules. 3193 * Access: RW 3194 */ 3195 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3196 3197 /* reg_perpt_erpt_base_bank 3198 * Base eRP table bank, points to head of erp_vector 3199 * Range is 0 .. cap_max_erp_table_banks - 1 3200 * Access: OP 3201 */ 3202 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3203 3204 /* reg_perpt_erpt_base_index 3205 * Base index to eRP table within the eRP bank 3206 * Range is 0 .. cap_max_erp_table_bank_size - 1 3207 * Access: OP 3208 */ 3209 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3210 3211 /* reg_perpt_erp_index_in_vector 3212 * eRP index in the vector. 3213 * Access: OP 3214 */ 3215 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3216 3217 /* reg_perpt_erp_vector 3218 * eRP vector. 3219 * Access: OP 3220 */ 3221 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3222 3223 /* reg_perpt_mask 3224 * Mask 3225 * 0 - A-TCAM will ignore the bit in key 3226 * 1 - A-TCAM will compare the bit in key 3227 * Access: RW 3228 */ 3229 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3230 3231 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3232 unsigned long *erp_vector, 3233 unsigned long size) 3234 { 3235 unsigned long bit; 3236 3237 for_each_set_bit(bit, erp_vector, size) 3238 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3239 } 3240 3241 static inline void 3242 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3243 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3244 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3245 char *mask) 3246 { 3247 MLXSW_REG_ZERO(perpt, payload); 3248 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3249 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3250 mlxsw_reg_perpt_key_size_set(payload, key_size); 3251 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3252 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3253 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3254 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3255 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3256 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3257 } 3258 3259 /* PERAR - Policy-Engine Region Association Register 3260 * ------------------------------------------------- 3261 * This register associates a hw region for region_id's. Changing on the fly 3262 * is supported by the device. 3263 */ 3264 #define MLXSW_REG_PERAR_ID 0x3026 3265 #define MLXSW_REG_PERAR_LEN 0x08 3266 3267 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3268 3269 /* reg_perar_region_id 3270 * Region identifier 3271 * Range 0 .. cap_max_regions-1 3272 * Access: Index 3273 */ 3274 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3275 3276 static inline unsigned int 3277 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3278 { 3279 return DIV_ROUND_UP(block_num, 4); 3280 } 3281 3282 /* reg_perar_hw_region 3283 * HW Region 3284 * Range 0 .. cap_max_regions-1 3285 * Default: hw_region = region_id 3286 * For a 8 key block region, 2 consecutive regions are used 3287 * For a 12 key block region, 3 consecutive regions are used 3288 * Access: RW 3289 */ 3290 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3291 3292 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3293 u16 hw_region) 3294 { 3295 MLXSW_REG_ZERO(perar, payload); 3296 mlxsw_reg_perar_region_id_set(payload, region_id); 3297 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3298 } 3299 3300 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3301 * ----------------------------------------------------- 3302 * This register is a new version of PTCE-V2 in order to support the 3303 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3304 */ 3305 #define MLXSW_REG_PTCE3_ID 0x3027 3306 #define MLXSW_REG_PTCE3_LEN 0xF0 3307 3308 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3309 3310 /* reg_ptce3_v 3311 * Valid. 3312 * Access: RW 3313 */ 3314 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3315 3316 enum mlxsw_reg_ptce3_op { 3317 /* Write operation. Used to write a new entry to the table. 3318 * All R/W fields are relevant for new entry. Activity bit is set 3319 * for new entries. Write with v = 0 will delete the entry. Must 3320 * not be used if an entry exists. 3321 */ 3322 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3323 /* Update operation */ 3324 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3325 /* Read operation */ 3326 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3327 }; 3328 3329 /* reg_ptce3_op 3330 * Access: OP 3331 */ 3332 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3333 3334 /* reg_ptce3_priority 3335 * Priority of the rule. Higher values win. 3336 * For Spectrum-2 range is 1..cap_kvd_size - 1 3337 * Note: Priority does not have to be unique per rule. 3338 * Access: RW 3339 */ 3340 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3341 3342 /* reg_ptce3_tcam_region_info 3343 * Opaque object that represents the TCAM region. 3344 * Access: Index 3345 */ 3346 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3347 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3348 3349 /* reg_ptce3_flex2_key_blocks 3350 * ACL key. The key must be masked according to eRP (if exists) or 3351 * according to master mask. 3352 * Access: Index 3353 */ 3354 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3355 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3356 3357 /* reg_ptce3_erp_id 3358 * eRP ID. 3359 * Access: Index 3360 */ 3361 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3362 3363 /* reg_ptce3_delta_start 3364 * Start point of delta_value and delta_mask, in bits. Must not exceed 3365 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3366 * Access: Index 3367 */ 3368 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3369 3370 /* reg_ptce3_delta_mask 3371 * Delta mask. 3372 * 0 - Ignore relevant bit in delta_value 3373 * 1 - Compare relevant bit in delta_value 3374 * Delta mask must not be set for reserved fields in the key blocks. 3375 * Note: No delta when no eRPs. Thus, for regions with 3376 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3377 * Access: Index 3378 */ 3379 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3380 3381 /* reg_ptce3_delta_value 3382 * Delta value. 3383 * Bits which are masked by delta_mask must be 0. 3384 * Access: Index 3385 */ 3386 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3387 3388 /* reg_ptce3_prune_vector 3389 * Pruning vector relative to the PERPT.erp_id. 3390 * Used for reducing lookups. 3391 * 0 - NEED: Do a lookup using the eRP. 3392 * 1 - PRUNE: Do not perform a lookup using the eRP. 3393 * Maybe be modified by PEAPBL and PEAPBM. 3394 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3395 * all 1's or all 0's. 3396 * Access: RW 3397 */ 3398 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3399 3400 /* reg_ptce3_prune_ctcam 3401 * Pruning on C-TCAM. Used for reducing lookups. 3402 * 0 - NEED: Do a lookup in the C-TCAM. 3403 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3404 * Access: RW 3405 */ 3406 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3407 3408 /* reg_ptce3_large_exists 3409 * Large entry key ID exists. 3410 * Within the region: 3411 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3412 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3413 * For rule delete: The MSB of the key will be removed. 3414 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3415 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3416 * For rule delete: The MSB of the key will not be removed. 3417 * Access: WO 3418 */ 3419 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3420 3421 /* reg_ptce3_large_entry_key_id 3422 * Large entry key ID. 3423 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3424 * blocks. Must be different for different keys which have the same common 3425 * 6 key blocks (MSB, blocks 6..11) key within a region. 3426 * Range is 0..cap_max_pe_large_key_id - 1 3427 * Access: RW 3428 */ 3429 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3430 3431 /* reg_ptce3_action_pointer 3432 * Pointer to action. 3433 * Range is 0..cap_max_kvd_action_sets - 1 3434 * Access: RW 3435 */ 3436 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3437 3438 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3439 enum mlxsw_reg_ptce3_op op, 3440 u32 priority, 3441 const char *tcam_region_info, 3442 const char *key, u8 erp_id, 3443 u16 delta_start, u8 delta_mask, 3444 u8 delta_value, bool large_exists, 3445 u32 lkey_id, u32 action_pointer) 3446 { 3447 MLXSW_REG_ZERO(ptce3, payload); 3448 mlxsw_reg_ptce3_v_set(payload, valid); 3449 mlxsw_reg_ptce3_op_set(payload, op); 3450 mlxsw_reg_ptce3_priority_set(payload, priority); 3451 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3452 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3453 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3454 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3455 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3456 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3457 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3458 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3459 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3460 } 3461 3462 /* PERCR - Policy-Engine Region Configuration Register 3463 * --------------------------------------------------- 3464 * This register configures the region parameters. The region_id must be 3465 * allocated. 3466 */ 3467 #define MLXSW_REG_PERCR_ID 0x302A 3468 #define MLXSW_REG_PERCR_LEN 0x80 3469 3470 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3471 3472 /* reg_percr_region_id 3473 * Region identifier. 3474 * Range 0..cap_max_regions-1 3475 * Access: Index 3476 */ 3477 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3478 3479 /* reg_percr_atcam_ignore_prune 3480 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3481 * Access: RW 3482 */ 3483 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3484 3485 /* reg_percr_ctcam_ignore_prune 3486 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3487 * Access: RW 3488 */ 3489 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3490 3491 /* reg_percr_bf_bypass 3492 * Bloom filter bypass. 3493 * 0 - Bloom filter is used (default) 3494 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3495 * region_id or eRP. See PERPT.bf_bypass 3496 * Access: RW 3497 */ 3498 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3499 3500 /* reg_percr_master_mask 3501 * Master mask. Logical OR mask of all masks of all rules of a region 3502 * (both A-TCAM and C-TCAM). When there are no eRPs 3503 * (erpt_pointer_valid = 0), then this provides the mask. 3504 * Access: RW 3505 */ 3506 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3507 3508 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3509 { 3510 MLXSW_REG_ZERO(percr, payload); 3511 mlxsw_reg_percr_region_id_set(payload, region_id); 3512 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3513 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3514 mlxsw_reg_percr_bf_bypass_set(payload, false); 3515 } 3516 3517 /* PERERP - Policy-Engine Region eRP Register 3518 * ------------------------------------------ 3519 * This register configures the region eRP. The region_id must be 3520 * allocated. 3521 */ 3522 #define MLXSW_REG_PERERP_ID 0x302B 3523 #define MLXSW_REG_PERERP_LEN 0x1C 3524 3525 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3526 3527 /* reg_pererp_region_id 3528 * Region identifier. 3529 * Range 0..cap_max_regions-1 3530 * Access: Index 3531 */ 3532 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3533 3534 /* reg_pererp_ctcam_le 3535 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3536 * Access: RW 3537 */ 3538 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3539 3540 /* reg_pererp_erpt_pointer_valid 3541 * erpt_pointer is valid. 3542 * Access: RW 3543 */ 3544 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3545 3546 /* reg_pererp_erpt_bank_pointer 3547 * Pointer to eRP table bank. May be modified at any time. 3548 * Range 0..cap_max_erp_table_banks-1 3549 * Reserved when erpt_pointer_valid = 0 3550 */ 3551 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3552 3553 /* reg_pererp_erpt_pointer 3554 * Pointer to eRP table within the eRP bank. Can be changed for an 3555 * existing region. 3556 * Range 0..cap_max_erp_table_size-1 3557 * Reserved when erpt_pointer_valid = 0 3558 * Access: RW 3559 */ 3560 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3561 3562 /* reg_pererp_erpt_vector 3563 * Vector of allowed eRP indexes starting from erpt_pointer within the 3564 * erpt_bank_pointer. Next entries will be in next bank. 3565 * Note that eRP index is used and not eRP ID. 3566 * Reserved when erpt_pointer_valid = 0 3567 * Access: RW 3568 */ 3569 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3570 3571 /* reg_pererp_master_rp_id 3572 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3573 * for the lookup. Can be changed for an existing region. 3574 * Reserved when erpt_pointer_valid = 1 3575 * Access: RW 3576 */ 3577 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3578 3579 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3580 unsigned long *erp_vector, 3581 unsigned long size) 3582 { 3583 unsigned long bit; 3584 3585 for_each_set_bit(bit, erp_vector, size) 3586 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3587 } 3588 3589 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3590 bool ctcam_le, bool erpt_pointer_valid, 3591 u8 erpt_bank_pointer, u8 erpt_pointer, 3592 u8 master_rp_id) 3593 { 3594 MLXSW_REG_ZERO(pererp, payload); 3595 mlxsw_reg_pererp_region_id_set(payload, region_id); 3596 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3597 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3598 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3599 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3600 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3601 } 3602 3603 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3604 * ---------------------------------------------------------------- 3605 * This register configures the Bloom filter entries. 3606 */ 3607 #define MLXSW_REG_PEABFE_ID 0x3022 3608 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3609 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3610 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3611 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3612 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3613 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3614 3615 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3616 3617 /* reg_peabfe_size 3618 * Number of BF entries to be updated. 3619 * Range 1..256 3620 * Access: Op 3621 */ 3622 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3623 3624 /* reg_peabfe_bf_entry_state 3625 * Bloom filter state 3626 * 0 - Clear 3627 * 1 - Set 3628 * Access: RW 3629 */ 3630 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3631 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3632 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3633 3634 /* reg_peabfe_bf_entry_bank 3635 * Bloom filter bank ID 3636 * Range 0..cap_max_erp_table_banks-1 3637 * Access: Index 3638 */ 3639 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3640 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3641 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3642 3643 /* reg_peabfe_bf_entry_index 3644 * Bloom filter entry index 3645 * Range 0..2^cap_max_bf_log-1 3646 * Access: Index 3647 */ 3648 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3649 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3650 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3651 3652 static inline void mlxsw_reg_peabfe_pack(char *payload) 3653 { 3654 MLXSW_REG_ZERO(peabfe, payload); 3655 } 3656 3657 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3658 u8 state, u8 bank, u32 bf_index) 3659 { 3660 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3661 3662 if (rec_index >= num_rec) 3663 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3664 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3665 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3666 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3667 } 3668 3669 /* IEDR - Infrastructure Entry Delete Register 3670 * ---------------------------------------------------- 3671 * This register is used for deleting entries from the entry tables. 3672 * It is legitimate to attempt to delete a nonexisting entry (the device will 3673 * respond as a good flow). 3674 */ 3675 #define MLXSW_REG_IEDR_ID 0x3804 3676 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3677 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3678 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3679 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3680 MLXSW_REG_IEDR_REC_LEN * \ 3681 MLXSW_REG_IEDR_REC_MAX_COUNT) 3682 3683 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3684 3685 /* reg_iedr_num_rec 3686 * Number of records. 3687 * Access: OP 3688 */ 3689 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3690 3691 /* reg_iedr_rec_type 3692 * Resource type. 3693 * Access: OP 3694 */ 3695 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3696 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3697 3698 /* reg_iedr_rec_size 3699 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3700 * Access: OP 3701 */ 3702 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3703 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3704 3705 /* reg_iedr_rec_index_start 3706 * Resource index start. 3707 * Access: OP 3708 */ 3709 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3710 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3711 3712 static inline void mlxsw_reg_iedr_pack(char *payload) 3713 { 3714 MLXSW_REG_ZERO(iedr, payload); 3715 } 3716 3717 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3718 u8 rec_type, u16 rec_size, 3719 u32 rec_index_start) 3720 { 3721 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3722 3723 if (rec_index >= num_rec) 3724 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3725 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3726 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3727 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3728 } 3729 3730 /* QPTS - QoS Priority Trust State Register 3731 * ---------------------------------------- 3732 * This register controls the port policy to calculate the switch priority and 3733 * packet color based on incoming packet fields. 3734 */ 3735 #define MLXSW_REG_QPTS_ID 0x4002 3736 #define MLXSW_REG_QPTS_LEN 0x8 3737 3738 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3739 3740 /* reg_qpts_local_port 3741 * Local port number. 3742 * Access: Index 3743 * 3744 * Note: CPU port is supported. 3745 */ 3746 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3747 3748 enum mlxsw_reg_qpts_trust_state { 3749 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3750 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3751 }; 3752 3753 /* reg_qpts_trust_state 3754 * Trust state for a given port. 3755 * Access: RW 3756 */ 3757 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3758 3759 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3760 enum mlxsw_reg_qpts_trust_state ts) 3761 { 3762 MLXSW_REG_ZERO(qpts, payload); 3763 3764 mlxsw_reg_qpts_local_port_set(payload, local_port); 3765 mlxsw_reg_qpts_trust_state_set(payload, ts); 3766 } 3767 3768 /* QPCR - QoS Policer Configuration Register 3769 * ----------------------------------------- 3770 * The QPCR register is used to create policers - that limit 3771 * the rate of bytes or packets via some trap group. 3772 */ 3773 #define MLXSW_REG_QPCR_ID 0x4004 3774 #define MLXSW_REG_QPCR_LEN 0x28 3775 3776 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3777 3778 enum mlxsw_reg_qpcr_g { 3779 MLXSW_REG_QPCR_G_GLOBAL = 2, 3780 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3781 }; 3782 3783 /* reg_qpcr_g 3784 * The policer type. 3785 * Access: Index 3786 */ 3787 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3788 3789 /* reg_qpcr_pid 3790 * Policer ID. 3791 * Access: Index 3792 */ 3793 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3794 3795 /* reg_qpcr_clear_counter 3796 * Clear counters. 3797 * Access: OP 3798 */ 3799 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3800 3801 /* reg_qpcr_color_aware 3802 * Is the policer aware of colors. 3803 * Must be 0 (unaware) for cpu port. 3804 * Access: RW for unbounded policer. RO for bounded policer. 3805 */ 3806 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3807 3808 /* reg_qpcr_bytes 3809 * Is policer limit is for bytes per sec or packets per sec. 3810 * 0 - packets 3811 * 1 - bytes 3812 * Access: RW for unbounded policer. RO for bounded policer. 3813 */ 3814 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3815 3816 enum mlxsw_reg_qpcr_ir_units { 3817 MLXSW_REG_QPCR_IR_UNITS_M, 3818 MLXSW_REG_QPCR_IR_UNITS_K, 3819 }; 3820 3821 /* reg_qpcr_ir_units 3822 * Policer's units for cir and eir fields (for bytes limits only) 3823 * 1 - 10^3 3824 * 0 - 10^6 3825 * Access: OP 3826 */ 3827 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3828 3829 enum mlxsw_reg_qpcr_rate_type { 3830 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3831 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3832 }; 3833 3834 /* reg_qpcr_rate_type 3835 * Policer can have one limit (single rate) or 2 limits with specific operation 3836 * for packets that exceed the lower rate but not the upper one. 3837 * (For cpu port must be single rate) 3838 * Access: RW for unbounded policer. RO for bounded policer. 3839 */ 3840 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3841 3842 /* reg_qpc_cbs 3843 * Policer's committed burst size. 3844 * The policer is working with time slices of 50 nano sec. By default every 3845 * slice is granted the proportionate share of the committed rate. If we want to 3846 * allow a slice to exceed that share (while still keeping the rate per sec) we 3847 * can allow burst. The burst size is between the default proportionate share 3848 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3849 * committed rate will result in exceeding the rate). The burst size must be a 3850 * log of 2 and will be determined by 2^cbs. 3851 * Access: RW 3852 */ 3853 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3854 3855 /* reg_qpcr_cir 3856 * Policer's committed rate. 3857 * The rate used for sungle rate, the lower rate for double rate. 3858 * For bytes limits, the rate will be this value * the unit from ir_units. 3859 * (Resolution error is up to 1%). 3860 * Access: RW 3861 */ 3862 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3863 3864 /* reg_qpcr_eir 3865 * Policer's exceed rate. 3866 * The higher rate for double rate, reserved for single rate. 3867 * Lower rate for double rate policer. 3868 * For bytes limits, the rate will be this value * the unit from ir_units. 3869 * (Resolution error is up to 1%). 3870 * Access: RW 3871 */ 3872 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3873 3874 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3875 3876 /* reg_qpcr_exceed_action. 3877 * What to do with packets between the 2 limits for double rate. 3878 * Access: RW for unbounded policer. RO for bounded policer. 3879 */ 3880 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3881 3882 enum mlxsw_reg_qpcr_action { 3883 /* Discard */ 3884 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3885 /* Forward and set color to red. 3886 * If the packet is intended to cpu port, it will be dropped. 3887 */ 3888 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3889 }; 3890 3891 /* reg_qpcr_violate_action 3892 * What to do with packets that cross the cir limit (for single rate) or the eir 3893 * limit (for double rate). 3894 * Access: RW for unbounded policer. RO for bounded policer. 3895 */ 3896 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3897 3898 /* reg_qpcr_violate_count 3899 * Counts the number of times violate_action happened on this PID. 3900 * Access: RW 3901 */ 3902 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3903 3904 /* Packets */ 3905 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3906 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3907 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3908 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3909 3910 /* Bandwidth */ 3911 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3912 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3913 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3914 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3915 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3916 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3917 3918 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3919 enum mlxsw_reg_qpcr_ir_units ir_units, 3920 bool bytes, u32 cir, u16 cbs) 3921 { 3922 MLXSW_REG_ZERO(qpcr, payload); 3923 mlxsw_reg_qpcr_pid_set(payload, pid); 3924 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3925 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3926 mlxsw_reg_qpcr_violate_action_set(payload, 3927 MLXSW_REG_QPCR_ACTION_DISCARD); 3928 mlxsw_reg_qpcr_cir_set(payload, cir); 3929 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3930 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3931 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3932 } 3933 3934 /* QTCT - QoS Switch Traffic Class Table 3935 * ------------------------------------- 3936 * Configures the mapping between the packet switch priority and the 3937 * traffic class on the transmit port. 3938 */ 3939 #define MLXSW_REG_QTCT_ID 0x400A 3940 #define MLXSW_REG_QTCT_LEN 0x08 3941 3942 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3943 3944 /* reg_qtct_local_port 3945 * Local port number. 3946 * Access: Index 3947 * 3948 * Note: CPU port is not supported. 3949 */ 3950 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3951 3952 /* reg_qtct_sub_port 3953 * Virtual port within the physical port. 3954 * Should be set to 0 when virtual ports are not enabled on the port. 3955 * Access: Index 3956 */ 3957 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3958 3959 /* reg_qtct_switch_prio 3960 * Switch priority. 3961 * Access: Index 3962 */ 3963 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3964 3965 /* reg_qtct_tclass 3966 * Traffic class. 3967 * Default values: 3968 * switch_prio 0 : tclass 1 3969 * switch_prio 1 : tclass 0 3970 * switch_prio i : tclass i, for i > 1 3971 * Access: RW 3972 */ 3973 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3974 3975 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3976 u8 switch_prio, u8 tclass) 3977 { 3978 MLXSW_REG_ZERO(qtct, payload); 3979 mlxsw_reg_qtct_local_port_set(payload, local_port); 3980 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3981 mlxsw_reg_qtct_tclass_set(payload, tclass); 3982 } 3983 3984 /* QEEC - QoS ETS Element Configuration Register 3985 * --------------------------------------------- 3986 * Configures the ETS elements. 3987 */ 3988 #define MLXSW_REG_QEEC_ID 0x400D 3989 #define MLXSW_REG_QEEC_LEN 0x20 3990 3991 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3992 3993 /* reg_qeec_local_port 3994 * Local port number. 3995 * Access: Index 3996 * 3997 * Note: CPU port is supported. 3998 */ 3999 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 4000 4001 enum mlxsw_reg_qeec_hr { 4002 MLXSW_REG_QEEC_HR_PORT, 4003 MLXSW_REG_QEEC_HR_GROUP, 4004 MLXSW_REG_QEEC_HR_SUBGROUP, 4005 MLXSW_REG_QEEC_HR_TC, 4006 }; 4007 4008 /* reg_qeec_element_hierarchy 4009 * 0 - Port 4010 * 1 - Group 4011 * 2 - Subgroup 4012 * 3 - Traffic Class 4013 * Access: Index 4014 */ 4015 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 4016 4017 /* reg_qeec_element_index 4018 * The index of the element in the hierarchy. 4019 * Access: Index 4020 */ 4021 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 4022 4023 /* reg_qeec_next_element_index 4024 * The index of the next (lower) element in the hierarchy. 4025 * Access: RW 4026 * 4027 * Note: Reserved for element_hierarchy 0. 4028 */ 4029 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 4030 4031 /* reg_qeec_mise 4032 * Min shaper configuration enable. Enables configuration of the min 4033 * shaper on this ETS element 4034 * 0 - Disable 4035 * 1 - Enable 4036 * Access: RW 4037 */ 4038 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 4039 4040 /* reg_qeec_ptps 4041 * PTP shaper 4042 * 0: regular shaper mode 4043 * 1: PTP oriented shaper 4044 * Allowed only for hierarchy 0 4045 * Not supported for CPU port 4046 * Note that ptps mode may affect the shaper rates of all hierarchies 4047 * Supported only on Spectrum-1 4048 * Access: RW 4049 */ 4050 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4051 4052 enum { 4053 MLXSW_REG_QEEC_BYTES_MODE, 4054 MLXSW_REG_QEEC_PACKETS_MODE, 4055 }; 4056 4057 /* reg_qeec_pb 4058 * Packets or bytes mode. 4059 * 0 - Bytes mode 4060 * 1 - Packets mode 4061 * Access: RW 4062 * 4063 * Note: Used for max shaper configuration. For Spectrum, packets mode 4064 * is supported only for traffic classes of CPU port. 4065 */ 4066 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4067 4068 /* The smallest permitted min shaper rate. */ 4069 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4070 4071 /* reg_qeec_min_shaper_rate 4072 * Min shaper information rate. 4073 * For CPU port, can only be configured for port hierarchy. 4074 * When in bytes mode, value is specified in units of 1000bps. 4075 * Access: RW 4076 */ 4077 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4078 4079 /* reg_qeec_mase 4080 * Max shaper configuration enable. Enables configuration of the max 4081 * shaper on this ETS element. 4082 * 0 - Disable 4083 * 1 - Enable 4084 * Access: RW 4085 */ 4086 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4087 4088 /* The largest max shaper value possible to disable the shaper. */ 4089 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4090 4091 /* reg_qeec_max_shaper_rate 4092 * Max shaper information rate. 4093 * For CPU port, can only be configured for port hierarchy. 4094 * When in bytes mode, value is specified in units of 1000bps. 4095 * Access: RW 4096 */ 4097 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4098 4099 /* reg_qeec_de 4100 * DWRR configuration enable. Enables configuration of the dwrr and 4101 * dwrr_weight. 4102 * 0 - Disable 4103 * 1 - Enable 4104 * Access: RW 4105 */ 4106 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4107 4108 /* reg_qeec_dwrr 4109 * Transmission selection algorithm to use on the link going down from 4110 * the ETS element. 4111 * 0 - Strict priority 4112 * 1 - DWRR 4113 * Access: RW 4114 */ 4115 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4116 4117 /* reg_qeec_dwrr_weight 4118 * DWRR weight on the link going down from the ETS element. The 4119 * percentage of bandwidth guaranteed to an ETS element within 4120 * its hierarchy. The sum of all weights across all ETS elements 4121 * within one hierarchy should be equal to 100. Reserved when 4122 * transmission selection algorithm is strict priority. 4123 * Access: RW 4124 */ 4125 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4126 4127 /* reg_qeec_max_shaper_bs 4128 * Max shaper burst size 4129 * Burst size is 2^max_shaper_bs * 512 bits 4130 * For Spectrum-1: Range is: 5..25 4131 * For Spectrum-2: Range is: 11..25 4132 * Reserved when ptps = 1 4133 * Access: RW 4134 */ 4135 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4136 4137 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4138 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4139 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4140 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4141 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4142 4143 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4144 enum mlxsw_reg_qeec_hr hr, u8 index, 4145 u8 next_index) 4146 { 4147 MLXSW_REG_ZERO(qeec, payload); 4148 mlxsw_reg_qeec_local_port_set(payload, local_port); 4149 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4150 mlxsw_reg_qeec_element_index_set(payload, index); 4151 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4152 } 4153 4154 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4155 bool ptps) 4156 { 4157 MLXSW_REG_ZERO(qeec, payload); 4158 mlxsw_reg_qeec_local_port_set(payload, local_port); 4159 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4160 mlxsw_reg_qeec_ptps_set(payload, ptps); 4161 } 4162 4163 /* QRWE - QoS ReWrite Enable 4164 * ------------------------- 4165 * This register configures the rewrite enable per receive port. 4166 */ 4167 #define MLXSW_REG_QRWE_ID 0x400F 4168 #define MLXSW_REG_QRWE_LEN 0x08 4169 4170 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4171 4172 /* reg_qrwe_local_port 4173 * Local port number. 4174 * Access: Index 4175 * 4176 * Note: CPU port is supported. No support for router port. 4177 */ 4178 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4179 4180 /* reg_qrwe_dscp 4181 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4182 * Access: RW 4183 */ 4184 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4185 4186 /* reg_qrwe_pcp 4187 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4188 * Access: RW 4189 */ 4190 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4191 4192 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4193 bool rewrite_pcp, bool rewrite_dscp) 4194 { 4195 MLXSW_REG_ZERO(qrwe, payload); 4196 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4197 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4198 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4199 } 4200 4201 /* QPDSM - QoS Priority to DSCP Mapping 4202 * ------------------------------------ 4203 * QoS Priority to DSCP Mapping Register 4204 */ 4205 #define MLXSW_REG_QPDSM_ID 0x4011 4206 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4207 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4208 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4209 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4210 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4211 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4212 4213 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4214 4215 /* reg_qpdsm_local_port 4216 * Local Port. Supported for data packets from CPU port. 4217 * Access: Index 4218 */ 4219 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4220 4221 /* reg_qpdsm_prio_entry_color0_e 4222 * Enable update of the entry for color 0 and a given port. 4223 * Access: WO 4224 */ 4225 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4226 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4227 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4228 4229 /* reg_qpdsm_prio_entry_color0_dscp 4230 * DSCP field in the outer label of the packet for color 0 and a given port. 4231 * Reserved when e=0. 4232 * Access: RW 4233 */ 4234 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4235 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4236 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4237 4238 /* reg_qpdsm_prio_entry_color1_e 4239 * Enable update of the entry for color 1 and a given port. 4240 * Access: WO 4241 */ 4242 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4243 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4244 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4245 4246 /* reg_qpdsm_prio_entry_color1_dscp 4247 * DSCP field in the outer label of the packet for color 1 and a given port. 4248 * Reserved when e=0. 4249 * Access: RW 4250 */ 4251 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4252 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4253 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4254 4255 /* reg_qpdsm_prio_entry_color2_e 4256 * Enable update of the entry for color 2 and a given port. 4257 * Access: WO 4258 */ 4259 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4260 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4261 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4262 4263 /* reg_qpdsm_prio_entry_color2_dscp 4264 * DSCP field in the outer label of the packet for color 2 and a given port. 4265 * Reserved when e=0. 4266 * Access: RW 4267 */ 4268 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4269 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4270 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4271 4272 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4273 { 4274 MLXSW_REG_ZERO(qpdsm, payload); 4275 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4276 } 4277 4278 static inline void 4279 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4280 { 4281 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4282 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4283 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4284 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4285 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4286 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4287 } 4288 4289 /* QPDP - QoS Port DSCP to Priority Mapping Register 4290 * ------------------------------------------------- 4291 * This register controls the port default Switch Priority and Color. The 4292 * default Switch Priority and Color are used for frames where the trust state 4293 * uses default values. All member ports of a LAG should be configured with the 4294 * same default values. 4295 */ 4296 #define MLXSW_REG_QPDP_ID 0x4007 4297 #define MLXSW_REG_QPDP_LEN 0x8 4298 4299 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4300 4301 /* reg_qpdp_local_port 4302 * Local Port. Supported for data packets from CPU port. 4303 * Access: Index 4304 */ 4305 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4306 4307 /* reg_qpdp_switch_prio 4308 * Default port Switch Priority (default 0) 4309 * Access: RW 4310 */ 4311 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4312 4313 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4314 u8 switch_prio) 4315 { 4316 MLXSW_REG_ZERO(qpdp, payload); 4317 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4318 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4319 } 4320 4321 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4322 * -------------------------------------------------- 4323 * This register controls the mapping from DSCP field to 4324 * Switch Priority for IP packets. 4325 */ 4326 #define MLXSW_REG_QPDPM_ID 0x4013 4327 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4328 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4329 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4330 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4331 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4332 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4333 4334 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4335 4336 /* reg_qpdpm_local_port 4337 * Local Port. Supported for data packets from CPU port. 4338 * Access: Index 4339 */ 4340 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4341 4342 /* reg_qpdpm_dscp_e 4343 * Enable update of the specific entry. When cleared, the switch_prio and color 4344 * fields are ignored and the previous switch_prio and color values are 4345 * preserved. 4346 * Access: WO 4347 */ 4348 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4349 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4350 4351 /* reg_qpdpm_dscp_prio 4352 * The new Switch Priority value for the relevant DSCP value. 4353 * Access: RW 4354 */ 4355 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4356 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4357 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4358 4359 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4360 { 4361 MLXSW_REG_ZERO(qpdpm, payload); 4362 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4363 } 4364 4365 static inline void 4366 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4367 { 4368 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4369 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4370 } 4371 4372 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4373 * ------------------------------------------------------------------ 4374 * This register configures if the Switch Priority to Traffic Class mapping is 4375 * based on Multicast packet indication. If so, then multicast packets will get 4376 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4377 * QTCT. 4378 * By default, Switch Priority to Traffic Class mapping is not based on 4379 * Multicast packet indication. 4380 */ 4381 #define MLXSW_REG_QTCTM_ID 0x401A 4382 #define MLXSW_REG_QTCTM_LEN 0x08 4383 4384 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4385 4386 /* reg_qtctm_local_port 4387 * Local port number. 4388 * No support for CPU port. 4389 * Access: Index 4390 */ 4391 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4392 4393 /* reg_qtctm_mc 4394 * Multicast Mode 4395 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4396 * indication (default is 0, not based on Multicast packet indication). 4397 */ 4398 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4399 4400 static inline void 4401 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4402 { 4403 MLXSW_REG_ZERO(qtctm, payload); 4404 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4405 mlxsw_reg_qtctm_mc_set(payload, mc); 4406 } 4407 4408 /* QPSC - QoS PTP Shaper Configuration Register 4409 * -------------------------------------------- 4410 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4411 * Supported only on Spectrum-1. 4412 */ 4413 #define MLXSW_REG_QPSC_ID 0x401B 4414 #define MLXSW_REG_QPSC_LEN 0x28 4415 4416 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4417 4418 enum mlxsw_reg_qpsc_port_speed { 4419 MLXSW_REG_QPSC_PORT_SPEED_100M, 4420 MLXSW_REG_QPSC_PORT_SPEED_1G, 4421 MLXSW_REG_QPSC_PORT_SPEED_10G, 4422 MLXSW_REG_QPSC_PORT_SPEED_25G, 4423 }; 4424 4425 /* reg_qpsc_port_speed 4426 * Port speed. 4427 * Access: Index 4428 */ 4429 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4430 4431 /* reg_qpsc_shaper_time_exp 4432 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4433 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4434 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4435 * Access: RW 4436 */ 4437 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4438 4439 /* reg_qpsc_shaper_time_mantissa 4440 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4441 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4442 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4443 * Access: RW 4444 */ 4445 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4446 4447 /* reg_qpsc_shaper_inc 4448 * Number of tokens added to shaper on each update. 4449 * Units of 8B. 4450 * Access: RW 4451 */ 4452 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4453 4454 /* reg_qpsc_shaper_bs 4455 * Max shaper Burst size. 4456 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4457 * Range is: 5..25 (from 2KB..2GB) 4458 * Access: RW 4459 */ 4460 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4461 4462 /* reg_qpsc_ptsc_we 4463 * Write enable to port_to_shaper_credits. 4464 * Access: WO 4465 */ 4466 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4467 4468 /* reg_qpsc_port_to_shaper_credits 4469 * For split ports: range 1..57 4470 * For non-split ports: range 1..112 4471 * Written only when ptsc_we is set. 4472 * Access: RW 4473 */ 4474 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4475 4476 /* reg_qpsc_ing_timestamp_inc 4477 * Ingress timestamp increment. 4478 * 2's complement. 4479 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4480 * value for all ports. 4481 * Same units as used by MTPPTR. 4482 * Access: RW 4483 */ 4484 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4485 4486 /* reg_qpsc_egr_timestamp_inc 4487 * Egress timestamp increment. 4488 * 2's complement. 4489 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4490 * value for all ports. 4491 * Same units as used by MTPPTR. 4492 * Access: RW 4493 */ 4494 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4495 4496 static inline void 4497 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4498 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4499 u8 shaper_bs, u8 port_to_shaper_credits, 4500 int ing_timestamp_inc, int egr_timestamp_inc) 4501 { 4502 MLXSW_REG_ZERO(qpsc, payload); 4503 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4504 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4505 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4506 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4507 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4508 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4509 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4510 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4511 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4512 } 4513 4514 /* PMLP - Ports Module to Local Port Register 4515 * ------------------------------------------ 4516 * Configures the assignment of modules to local ports. 4517 */ 4518 #define MLXSW_REG_PMLP_ID 0x5002 4519 #define MLXSW_REG_PMLP_LEN 0x40 4520 4521 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4522 4523 /* reg_pmlp_rxtx 4524 * 0 - Tx value is used for both Tx and Rx. 4525 * 1 - Rx value is taken from a separte field. 4526 * Access: RW 4527 */ 4528 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4529 4530 /* reg_pmlp_local_port 4531 * Local port number. 4532 * Access: Index 4533 */ 4534 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4535 4536 /* reg_pmlp_width 4537 * 0 - Unmap local port. 4538 * 1 - Lane 0 is used. 4539 * 2 - Lanes 0 and 1 are used. 4540 * 4 - Lanes 0, 1, 2 and 3 are used. 4541 * 8 - Lanes 0-7 are used. 4542 * Access: RW 4543 */ 4544 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4545 4546 /* reg_pmlp_module 4547 * Module number. 4548 * Access: RW 4549 */ 4550 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4551 4552 /* reg_pmlp_slot_index 4553 * Module number. 4554 * Slot_index 4555 * Slot_index = 0 represent the onboard (motherboard). 4556 * In case of non-modular system only slot_index = 0 is available. 4557 * Access: RW 4558 */ 4559 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4560 4561 /* reg_pmlp_tx_lane 4562 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4563 * Access: RW 4564 */ 4565 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4566 4567 /* reg_pmlp_rx_lane 4568 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4569 * equal to Tx lane. 4570 * Access: RW 4571 */ 4572 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4573 4574 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4575 { 4576 MLXSW_REG_ZERO(pmlp, payload); 4577 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4578 } 4579 4580 /* PMTU - Port MTU Register 4581 * ------------------------ 4582 * Configures and reports the port MTU. 4583 */ 4584 #define MLXSW_REG_PMTU_ID 0x5003 4585 #define MLXSW_REG_PMTU_LEN 0x10 4586 4587 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4588 4589 /* reg_pmtu_local_port 4590 * Local port number. 4591 * Access: Index 4592 */ 4593 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4594 4595 /* reg_pmtu_max_mtu 4596 * Maximum MTU. 4597 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4598 * reported, otherwise the minimum between the max_mtu of the different 4599 * types is reported. 4600 * Access: RO 4601 */ 4602 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4603 4604 /* reg_pmtu_admin_mtu 4605 * MTU value to set port to. Must be smaller or equal to max_mtu. 4606 * Note: If port type is Infiniband, then port must be disabled, when its 4607 * MTU is set. 4608 * Access: RW 4609 */ 4610 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4611 4612 /* reg_pmtu_oper_mtu 4613 * The actual MTU configured on the port. Packets exceeding this size 4614 * will be dropped. 4615 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4616 * oper_mtu might be smaller than admin_mtu. 4617 * Access: RO 4618 */ 4619 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4620 4621 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4622 u16 new_mtu) 4623 { 4624 MLXSW_REG_ZERO(pmtu, payload); 4625 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4626 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4627 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4628 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4629 } 4630 4631 /* PTYS - Port Type and Speed Register 4632 * ----------------------------------- 4633 * Configures and reports the port speed type. 4634 * 4635 * Note: When set while the link is up, the changes will not take effect 4636 * until the port transitions from down to up state. 4637 */ 4638 #define MLXSW_REG_PTYS_ID 0x5004 4639 #define MLXSW_REG_PTYS_LEN 0x40 4640 4641 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4642 4643 /* an_disable_admin 4644 * Auto negotiation disable administrative configuration 4645 * 0 - Device doesn't support AN disable. 4646 * 1 - Device supports AN disable. 4647 * Access: RW 4648 */ 4649 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4650 4651 /* reg_ptys_local_port 4652 * Local port number. 4653 * Access: Index 4654 */ 4655 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4656 4657 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4658 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4659 4660 /* reg_ptys_proto_mask 4661 * Protocol mask. Indicates which protocol is used. 4662 * 0 - Infiniband. 4663 * 1 - Fibre Channel. 4664 * 2 - Ethernet. 4665 * Access: Index 4666 */ 4667 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4668 4669 enum { 4670 MLXSW_REG_PTYS_AN_STATUS_NA, 4671 MLXSW_REG_PTYS_AN_STATUS_OK, 4672 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4673 }; 4674 4675 /* reg_ptys_an_status 4676 * Autonegotiation status. 4677 * Access: RO 4678 */ 4679 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4680 4681 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4682 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4683 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4684 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4685 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4686 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4687 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4688 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4689 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4690 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4691 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4692 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4693 4694 /* reg_ptys_ext_eth_proto_cap 4695 * Extended Ethernet port supported speeds and protocols. 4696 * Access: RO 4697 */ 4698 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4699 4700 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4701 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4702 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4703 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4704 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4705 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4706 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4707 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4708 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4709 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4710 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4711 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4712 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4713 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4714 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4715 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4716 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4717 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4718 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4719 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4720 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4721 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4722 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4723 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4724 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4725 4726 /* reg_ptys_eth_proto_cap 4727 * Ethernet port supported speeds and protocols. 4728 * Access: RO 4729 */ 4730 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4731 4732 /* reg_ptys_ib_link_width_cap 4733 * IB port supported widths. 4734 * Access: RO 4735 */ 4736 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4737 4738 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4739 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4740 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4741 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4742 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4743 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4744 4745 /* reg_ptys_ib_proto_cap 4746 * IB port supported speeds and protocols. 4747 * Access: RO 4748 */ 4749 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4750 4751 /* reg_ptys_ext_eth_proto_admin 4752 * Extended speed and protocol to set port to. 4753 * Access: RW 4754 */ 4755 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4756 4757 /* reg_ptys_eth_proto_admin 4758 * Speed and protocol to set port to. 4759 * Access: RW 4760 */ 4761 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4762 4763 /* reg_ptys_ib_link_width_admin 4764 * IB width to set port to. 4765 * Access: RW 4766 */ 4767 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4768 4769 /* reg_ptys_ib_proto_admin 4770 * IB speeds and protocols to set port to. 4771 * Access: RW 4772 */ 4773 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4774 4775 /* reg_ptys_ext_eth_proto_oper 4776 * The extended current speed and protocol configured for the port. 4777 * Access: RO 4778 */ 4779 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4780 4781 /* reg_ptys_eth_proto_oper 4782 * The current speed and protocol configured for the port. 4783 * Access: RO 4784 */ 4785 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4786 4787 /* reg_ptys_ib_link_width_oper 4788 * The current IB width to set port to. 4789 * Access: RO 4790 */ 4791 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4792 4793 /* reg_ptys_ib_proto_oper 4794 * The current IB speed and protocol. 4795 * Access: RO 4796 */ 4797 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4798 4799 enum mlxsw_reg_ptys_connector_type { 4800 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4801 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4802 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4803 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4804 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4805 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4806 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4807 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4808 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4809 }; 4810 4811 /* reg_ptys_connector_type 4812 * Connector type indication. 4813 * Access: RO 4814 */ 4815 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4816 4817 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4818 u32 proto_admin, bool autoneg) 4819 { 4820 MLXSW_REG_ZERO(ptys, payload); 4821 mlxsw_reg_ptys_local_port_set(payload, local_port); 4822 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4823 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4824 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4825 } 4826 4827 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4828 u32 proto_admin, bool autoneg) 4829 { 4830 MLXSW_REG_ZERO(ptys, payload); 4831 mlxsw_reg_ptys_local_port_set(payload, local_port); 4832 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4833 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4834 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4835 } 4836 4837 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4838 u32 *p_eth_proto_cap, 4839 u32 *p_eth_proto_admin, 4840 u32 *p_eth_proto_oper) 4841 { 4842 if (p_eth_proto_cap) 4843 *p_eth_proto_cap = 4844 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4845 if (p_eth_proto_admin) 4846 *p_eth_proto_admin = 4847 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4848 if (p_eth_proto_oper) 4849 *p_eth_proto_oper = 4850 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4851 } 4852 4853 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4854 u32 *p_eth_proto_cap, 4855 u32 *p_eth_proto_admin, 4856 u32 *p_eth_proto_oper) 4857 { 4858 if (p_eth_proto_cap) 4859 *p_eth_proto_cap = 4860 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4861 if (p_eth_proto_admin) 4862 *p_eth_proto_admin = 4863 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4864 if (p_eth_proto_oper) 4865 *p_eth_proto_oper = 4866 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4867 } 4868 4869 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port, 4870 u16 proto_admin, u16 link_width) 4871 { 4872 MLXSW_REG_ZERO(ptys, payload); 4873 mlxsw_reg_ptys_local_port_set(payload, local_port); 4874 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4875 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4876 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4877 } 4878 4879 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4880 u16 *p_ib_link_width_cap, 4881 u16 *p_ib_proto_oper, 4882 u16 *p_ib_link_width_oper) 4883 { 4884 if (p_ib_proto_cap) 4885 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4886 if (p_ib_link_width_cap) 4887 *p_ib_link_width_cap = 4888 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4889 if (p_ib_proto_oper) 4890 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4891 if (p_ib_link_width_oper) 4892 *p_ib_link_width_oper = 4893 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4894 } 4895 4896 /* PPAD - Port Physical Address Register 4897 * ------------------------------------- 4898 * The PPAD register configures the per port physical MAC address. 4899 */ 4900 #define MLXSW_REG_PPAD_ID 0x5005 4901 #define MLXSW_REG_PPAD_LEN 0x10 4902 4903 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4904 4905 /* reg_ppad_single_base_mac 4906 * 0: base_mac, local port should be 0 and mac[7:0] is 4907 * reserved. HW will set incremental 4908 * 1: single_mac - mac of the local_port 4909 * Access: RW 4910 */ 4911 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4912 4913 /* reg_ppad_local_port 4914 * port number, if single_base_mac = 0 then local_port is reserved 4915 * Access: RW 4916 */ 4917 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4918 4919 /* reg_ppad_mac 4920 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4921 * If single_base_mac = 1 - the per port MAC address 4922 * Access: RW 4923 */ 4924 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4925 4926 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4927 u16 local_port) 4928 { 4929 MLXSW_REG_ZERO(ppad, payload); 4930 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4931 mlxsw_reg_ppad_local_port_set(payload, local_port); 4932 } 4933 4934 /* PAOS - Ports Administrative and Operational Status Register 4935 * ----------------------------------------------------------- 4936 * Configures and retrieves per port administrative and operational status. 4937 */ 4938 #define MLXSW_REG_PAOS_ID 0x5006 4939 #define MLXSW_REG_PAOS_LEN 0x10 4940 4941 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4942 4943 /* reg_paos_swid 4944 * Switch partition ID with which to associate the port. 4945 * Note: while external ports uses unique local port numbers (and thus swid is 4946 * redundant), router ports use the same local port number where swid is the 4947 * only indication for the relevant port. 4948 * Access: Index 4949 */ 4950 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4951 4952 /* reg_paos_local_port 4953 * Local port number. 4954 * Access: Index 4955 */ 4956 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4957 4958 /* reg_paos_admin_status 4959 * Port administrative state (the desired state of the port): 4960 * 1 - Up. 4961 * 2 - Down. 4962 * 3 - Up once. This means that in case of link failure, the port won't go 4963 * into polling mode, but will wait to be re-enabled by software. 4964 * 4 - Disabled by system. Can only be set by hardware. 4965 * Access: RW 4966 */ 4967 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4968 4969 /* reg_paos_oper_status 4970 * Port operational state (the current state): 4971 * 1 - Up. 4972 * 2 - Down. 4973 * 3 - Down by port failure. This means that the device will not let the 4974 * port up again until explicitly specified by software. 4975 * Access: RO 4976 */ 4977 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4978 4979 /* reg_paos_ase 4980 * Admin state update enabled. 4981 * Access: WO 4982 */ 4983 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4984 4985 /* reg_paos_ee 4986 * Event update enable. If this bit is set, event generation will be 4987 * updated based on the e field. 4988 * Access: WO 4989 */ 4990 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4991 4992 /* reg_paos_e 4993 * Event generation on operational state change: 4994 * 0 - Do not generate event. 4995 * 1 - Generate Event. 4996 * 2 - Generate Single Event. 4997 * Access: RW 4998 */ 4999 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 5000 5001 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 5002 enum mlxsw_port_admin_status status) 5003 { 5004 MLXSW_REG_ZERO(paos, payload); 5005 mlxsw_reg_paos_swid_set(payload, 0); 5006 mlxsw_reg_paos_local_port_set(payload, local_port); 5007 mlxsw_reg_paos_admin_status_set(payload, status); 5008 mlxsw_reg_paos_oper_status_set(payload, 0); 5009 mlxsw_reg_paos_ase_set(payload, 1); 5010 mlxsw_reg_paos_ee_set(payload, 1); 5011 mlxsw_reg_paos_e_set(payload, 1); 5012 } 5013 5014 /* PFCC - Ports Flow Control Configuration Register 5015 * ------------------------------------------------ 5016 * Configures and retrieves the per port flow control configuration. 5017 */ 5018 #define MLXSW_REG_PFCC_ID 0x5007 5019 #define MLXSW_REG_PFCC_LEN 0x20 5020 5021 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 5022 5023 /* reg_pfcc_local_port 5024 * Local port number. 5025 * Access: Index 5026 */ 5027 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 5028 5029 /* reg_pfcc_pnat 5030 * Port number access type. Determines the way local_port is interpreted: 5031 * 0 - Local port number. 5032 * 1 - IB / label port number. 5033 * Access: Index 5034 */ 5035 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 5036 5037 /* reg_pfcc_shl_cap 5038 * Send to higher layers capabilities: 5039 * 0 - No capability of sending Pause and PFC frames to higher layers. 5040 * 1 - Device has capability of sending Pause and PFC frames to higher 5041 * layers. 5042 * Access: RO 5043 */ 5044 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 5045 5046 /* reg_pfcc_shl_opr 5047 * Send to higher layers operation: 5048 * 0 - Pause and PFC frames are handled by the port (default). 5049 * 1 - Pause and PFC frames are handled by the port and also sent to 5050 * higher layers. Only valid if shl_cap = 1. 5051 * Access: RW 5052 */ 5053 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 5054 5055 /* reg_pfcc_ppan 5056 * Pause policy auto negotiation. 5057 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 5058 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 5059 * based on the auto-negotiation resolution. 5060 * Access: RW 5061 * 5062 * Note: The auto-negotiation advertisement is set according to pptx and 5063 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 5064 */ 5065 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 5066 5067 /* reg_pfcc_prio_mask_tx 5068 * Bit per priority indicating if Tx flow control policy should be 5069 * updated based on bit pfctx. 5070 * Access: WO 5071 */ 5072 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 5073 5074 /* reg_pfcc_prio_mask_rx 5075 * Bit per priority indicating if Rx flow control policy should be 5076 * updated based on bit pfcrx. 5077 * Access: WO 5078 */ 5079 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 5080 5081 /* reg_pfcc_pptx 5082 * Admin Pause policy on Tx. 5083 * 0 - Never generate Pause frames (default). 5084 * 1 - Generate Pause frames according to Rx buffer threshold. 5085 * Access: RW 5086 */ 5087 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 5088 5089 /* reg_pfcc_aptx 5090 * Active (operational) Pause policy on Tx. 5091 * 0 - Never generate Pause frames. 5092 * 1 - Generate Pause frames according to Rx buffer threshold. 5093 * Access: RO 5094 */ 5095 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 5096 5097 /* reg_pfcc_pfctx 5098 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 5099 * 0 - Never generate priority Pause frames on the specified priority 5100 * (default). 5101 * 1 - Generate priority Pause frames according to Rx buffer threshold on 5102 * the specified priority. 5103 * Access: RW 5104 * 5105 * Note: pfctx and pptx must be mutually exclusive. 5106 */ 5107 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 5108 5109 /* reg_pfcc_pprx 5110 * Admin Pause policy on Rx. 5111 * 0 - Ignore received Pause frames (default). 5112 * 1 - Respect received Pause frames. 5113 * Access: RW 5114 */ 5115 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5116 5117 /* reg_pfcc_aprx 5118 * Active (operational) Pause policy on Rx. 5119 * 0 - Ignore received Pause frames. 5120 * 1 - Respect received Pause frames. 5121 * Access: RO 5122 */ 5123 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5124 5125 /* reg_pfcc_pfcrx 5126 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5127 * 0 - Ignore incoming priority Pause frames on the specified priority 5128 * (default). 5129 * 1 - Respect incoming priority Pause frames on the specified priority. 5130 * Access: RW 5131 */ 5132 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5133 5134 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5135 5136 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5137 { 5138 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5139 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5140 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5141 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5142 } 5143 5144 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5145 { 5146 MLXSW_REG_ZERO(pfcc, payload); 5147 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5148 } 5149 5150 /* PPCNT - Ports Performance Counters Register 5151 * ------------------------------------------- 5152 * The PPCNT register retrieves per port performance counters. 5153 */ 5154 #define MLXSW_REG_PPCNT_ID 0x5008 5155 #define MLXSW_REG_PPCNT_LEN 0x100 5156 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5157 5158 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5159 5160 /* reg_ppcnt_swid 5161 * For HCA: must be always 0. 5162 * Switch partition ID to associate port with. 5163 * Switch partitions are numbered from 0 to 7 inclusively. 5164 * Switch partition 254 indicates stacking ports. 5165 * Switch partition 255 indicates all switch partitions. 5166 * Only valid on Set() operation with local_port=255. 5167 * Access: Index 5168 */ 5169 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5170 5171 /* reg_ppcnt_local_port 5172 * Local port number. 5173 * Access: Index 5174 */ 5175 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5176 5177 /* reg_ppcnt_pnat 5178 * Port number access type: 5179 * 0 - Local port number 5180 * 1 - IB port number 5181 * Access: Index 5182 */ 5183 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5184 5185 enum mlxsw_reg_ppcnt_grp { 5186 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5187 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5188 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5189 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5190 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5191 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5192 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5193 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5194 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5195 }; 5196 5197 /* reg_ppcnt_grp 5198 * Performance counter group. 5199 * Group 63 indicates all groups. Only valid on Set() operation with 5200 * clr bit set. 5201 * 0x0: IEEE 802.3 Counters 5202 * 0x1: RFC 2863 Counters 5203 * 0x2: RFC 2819 Counters 5204 * 0x3: RFC 3635 Counters 5205 * 0x5: Ethernet Extended Counters 5206 * 0x6: Ethernet Discard Counters 5207 * 0x8: Link Level Retransmission Counters 5208 * 0x10: Per Priority Counters 5209 * 0x11: Per Traffic Class Counters 5210 * 0x12: Physical Layer Counters 5211 * 0x13: Per Traffic Class Congestion Counters 5212 * Access: Index 5213 */ 5214 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5215 5216 /* reg_ppcnt_clr 5217 * Clear counters. Setting the clr bit will reset the counter value 5218 * for all counters in the counter group. This bit can be set 5219 * for both Set() and Get() operation. 5220 * Access: OP 5221 */ 5222 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5223 5224 /* reg_ppcnt_lp_gl 5225 * Local port global variable. 5226 * 0: local_port 255 = all ports of the device. 5227 * 1: local_port indicates local port number for all ports. 5228 * Access: OP 5229 */ 5230 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5231 5232 /* reg_ppcnt_prio_tc 5233 * Priority for counter set that support per priority, valid values: 0-7. 5234 * Traffic class for counter set that support per traffic class, 5235 * valid values: 0- cap_max_tclass-1 . 5236 * For HCA: cap_max_tclass is always 8. 5237 * Otherwise must be 0. 5238 * Access: Index 5239 */ 5240 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5241 5242 /* Ethernet IEEE 802.3 Counter Group */ 5243 5244 /* reg_ppcnt_a_frames_transmitted_ok 5245 * Access: RO 5246 */ 5247 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5248 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5249 5250 /* reg_ppcnt_a_frames_received_ok 5251 * Access: RO 5252 */ 5253 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5254 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5255 5256 /* reg_ppcnt_a_frame_check_sequence_errors 5257 * Access: RO 5258 */ 5259 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5260 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5261 5262 /* reg_ppcnt_a_alignment_errors 5263 * Access: RO 5264 */ 5265 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5266 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5267 5268 /* reg_ppcnt_a_octets_transmitted_ok 5269 * Access: RO 5270 */ 5271 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5272 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5273 5274 /* reg_ppcnt_a_octets_received_ok 5275 * Access: RO 5276 */ 5277 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5278 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5279 5280 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5281 * Access: RO 5282 */ 5283 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5284 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5285 5286 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5287 * Access: RO 5288 */ 5289 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5290 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5291 5292 /* reg_ppcnt_a_multicast_frames_received_ok 5293 * Access: RO 5294 */ 5295 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5296 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5297 5298 /* reg_ppcnt_a_broadcast_frames_received_ok 5299 * Access: RO 5300 */ 5301 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5302 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5303 5304 /* reg_ppcnt_a_in_range_length_errors 5305 * Access: RO 5306 */ 5307 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5308 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5309 5310 /* reg_ppcnt_a_out_of_range_length_field 5311 * Access: RO 5312 */ 5313 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5314 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5315 5316 /* reg_ppcnt_a_frame_too_long_errors 5317 * Access: RO 5318 */ 5319 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5320 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5321 5322 /* reg_ppcnt_a_symbol_error_during_carrier 5323 * Access: RO 5324 */ 5325 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5326 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5327 5328 /* reg_ppcnt_a_mac_control_frames_transmitted 5329 * Access: RO 5330 */ 5331 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5332 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5333 5334 /* reg_ppcnt_a_mac_control_frames_received 5335 * Access: RO 5336 */ 5337 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5338 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5339 5340 /* reg_ppcnt_a_unsupported_opcodes_received 5341 * Access: RO 5342 */ 5343 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5344 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5345 5346 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5347 * Access: RO 5348 */ 5349 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5350 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5351 5352 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5353 * Access: RO 5354 */ 5355 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5356 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5357 5358 /* Ethernet RFC 2863 Counter Group */ 5359 5360 /* reg_ppcnt_if_in_discards 5361 * Access: RO 5362 */ 5363 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5364 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5365 5366 /* reg_ppcnt_if_out_discards 5367 * Access: RO 5368 */ 5369 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5370 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5371 5372 /* reg_ppcnt_if_out_errors 5373 * Access: RO 5374 */ 5375 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5376 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5377 5378 /* Ethernet RFC 2819 Counter Group */ 5379 5380 /* reg_ppcnt_ether_stats_undersize_pkts 5381 * Access: RO 5382 */ 5383 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5384 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5385 5386 /* reg_ppcnt_ether_stats_oversize_pkts 5387 * Access: RO 5388 */ 5389 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5390 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5391 5392 /* reg_ppcnt_ether_stats_fragments 5393 * Access: RO 5394 */ 5395 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5396 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5397 5398 /* reg_ppcnt_ether_stats_pkts64octets 5399 * Access: RO 5400 */ 5401 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5402 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5403 5404 /* reg_ppcnt_ether_stats_pkts65to127octets 5405 * Access: RO 5406 */ 5407 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5408 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5409 5410 /* reg_ppcnt_ether_stats_pkts128to255octets 5411 * Access: RO 5412 */ 5413 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5414 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5415 5416 /* reg_ppcnt_ether_stats_pkts256to511octets 5417 * Access: RO 5418 */ 5419 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5420 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5421 5422 /* reg_ppcnt_ether_stats_pkts512to1023octets 5423 * Access: RO 5424 */ 5425 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5426 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5427 5428 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5429 * Access: RO 5430 */ 5431 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5432 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5433 5434 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5435 * Access: RO 5436 */ 5437 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5438 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5439 5440 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5441 * Access: RO 5442 */ 5443 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5444 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5445 5446 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5447 * Access: RO 5448 */ 5449 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5450 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5451 5452 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5453 * Access: RO 5454 */ 5455 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5456 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5457 5458 /* Ethernet RFC 3635 Counter Group */ 5459 5460 /* reg_ppcnt_dot3stats_fcs_errors 5461 * Access: RO 5462 */ 5463 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5464 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5465 5466 /* reg_ppcnt_dot3stats_symbol_errors 5467 * Access: RO 5468 */ 5469 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5470 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5471 5472 /* reg_ppcnt_dot3control_in_unknown_opcodes 5473 * Access: RO 5474 */ 5475 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5476 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5477 5478 /* reg_ppcnt_dot3in_pause_frames 5479 * Access: RO 5480 */ 5481 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5482 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5483 5484 /* Ethernet Extended Counter Group Counters */ 5485 5486 /* reg_ppcnt_ecn_marked 5487 * Access: RO 5488 */ 5489 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5490 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5491 5492 /* Ethernet Discard Counter Group Counters */ 5493 5494 /* reg_ppcnt_ingress_general 5495 * Access: RO 5496 */ 5497 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5498 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5499 5500 /* reg_ppcnt_ingress_policy_engine 5501 * Access: RO 5502 */ 5503 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5504 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5505 5506 /* reg_ppcnt_ingress_vlan_membership 5507 * Access: RO 5508 */ 5509 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5510 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5511 5512 /* reg_ppcnt_ingress_tag_frame_type 5513 * Access: RO 5514 */ 5515 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5516 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5517 5518 /* reg_ppcnt_egress_vlan_membership 5519 * Access: RO 5520 */ 5521 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5522 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5523 5524 /* reg_ppcnt_loopback_filter 5525 * Access: RO 5526 */ 5527 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5528 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5529 5530 /* reg_ppcnt_egress_general 5531 * Access: RO 5532 */ 5533 MLXSW_ITEM64(reg, ppcnt, egress_general, 5534 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5535 5536 /* reg_ppcnt_egress_hoq 5537 * Access: RO 5538 */ 5539 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5540 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5541 5542 /* reg_ppcnt_egress_policy_engine 5543 * Access: RO 5544 */ 5545 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5546 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5547 5548 /* reg_ppcnt_ingress_tx_link_down 5549 * Access: RO 5550 */ 5551 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5552 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5553 5554 /* reg_ppcnt_egress_stp_filter 5555 * Access: RO 5556 */ 5557 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5558 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5559 5560 /* reg_ppcnt_egress_sll 5561 * Access: RO 5562 */ 5563 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5564 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5565 5566 /* Ethernet Per Priority Group Counters */ 5567 5568 /* reg_ppcnt_rx_octets 5569 * Access: RO 5570 */ 5571 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5572 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5573 5574 /* reg_ppcnt_rx_frames 5575 * Access: RO 5576 */ 5577 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5578 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5579 5580 /* reg_ppcnt_tx_octets 5581 * Access: RO 5582 */ 5583 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5584 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5585 5586 /* reg_ppcnt_tx_frames 5587 * Access: RO 5588 */ 5589 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5590 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5591 5592 /* reg_ppcnt_rx_pause 5593 * Access: RO 5594 */ 5595 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5596 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5597 5598 /* reg_ppcnt_rx_pause_duration 5599 * Access: RO 5600 */ 5601 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5602 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5603 5604 /* reg_ppcnt_tx_pause 5605 * Access: RO 5606 */ 5607 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5608 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5609 5610 /* reg_ppcnt_tx_pause_duration 5611 * Access: RO 5612 */ 5613 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5614 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5615 5616 /* reg_ppcnt_rx_pause_transition 5617 * Access: RO 5618 */ 5619 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5620 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5621 5622 /* Ethernet Per Traffic Class Counters */ 5623 5624 /* reg_ppcnt_tc_transmit_queue 5625 * Contains the transmit queue depth in cells of traffic class 5626 * selected by prio_tc and the port selected by local_port. 5627 * The field cannot be cleared. 5628 * Access: RO 5629 */ 5630 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5631 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5632 5633 /* reg_ppcnt_tc_no_buffer_discard_uc 5634 * The number of unicast packets dropped due to lack of shared 5635 * buffer resources. 5636 * Access: RO 5637 */ 5638 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5639 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5640 5641 /* Ethernet Per Traffic Class Congestion Group Counters */ 5642 5643 /* reg_ppcnt_wred_discard 5644 * Access: RO 5645 */ 5646 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5647 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5648 5649 /* reg_ppcnt_ecn_marked_tc 5650 * Access: RO 5651 */ 5652 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5653 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5654 5655 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5656 enum mlxsw_reg_ppcnt_grp grp, 5657 u8 prio_tc) 5658 { 5659 MLXSW_REG_ZERO(ppcnt, payload); 5660 mlxsw_reg_ppcnt_swid_set(payload, 0); 5661 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5662 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5663 mlxsw_reg_ppcnt_grp_set(payload, grp); 5664 mlxsw_reg_ppcnt_clr_set(payload, 0); 5665 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5666 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5667 } 5668 5669 /* PLIB - Port Local to InfiniBand Port 5670 * ------------------------------------ 5671 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5672 */ 5673 #define MLXSW_REG_PLIB_ID 0x500A 5674 #define MLXSW_REG_PLIB_LEN 0x10 5675 5676 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5677 5678 /* reg_plib_local_port 5679 * Local port number. 5680 * Access: Index 5681 */ 5682 MLXSW_ITEM32_LP(reg, plib, 0x00, 16, 0x00, 12); 5683 5684 /* reg_plib_ib_port 5685 * InfiniBand port remapping for local_port. 5686 * Access: RW 5687 */ 5688 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5689 5690 /* PPTB - Port Prio To Buffer Register 5691 * ----------------------------------- 5692 * Configures the switch priority to buffer table. 5693 */ 5694 #define MLXSW_REG_PPTB_ID 0x500B 5695 #define MLXSW_REG_PPTB_LEN 0x10 5696 5697 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5698 5699 enum { 5700 MLXSW_REG_PPTB_MM_UM, 5701 MLXSW_REG_PPTB_MM_UNICAST, 5702 MLXSW_REG_PPTB_MM_MULTICAST, 5703 }; 5704 5705 /* reg_pptb_mm 5706 * Mapping mode. 5707 * 0 - Map both unicast and multicast packets to the same buffer. 5708 * 1 - Map only unicast packets. 5709 * 2 - Map only multicast packets. 5710 * Access: Index 5711 * 5712 * Note: SwitchX-2 only supports the first option. 5713 */ 5714 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5715 5716 /* reg_pptb_local_port 5717 * Local port number. 5718 * Access: Index 5719 */ 5720 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5721 5722 /* reg_pptb_um 5723 * Enables the update of the untagged_buf field. 5724 * Access: RW 5725 */ 5726 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5727 5728 /* reg_pptb_pm 5729 * Enables the update of the prio_to_buff field. 5730 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5731 * Access: RW 5732 */ 5733 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5734 5735 /* reg_pptb_prio_to_buff 5736 * Mapping of switch priority <i> to one of the allocated receive port 5737 * buffers. 5738 * Access: RW 5739 */ 5740 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5741 5742 /* reg_pptb_pm_msb 5743 * Enables the update of the prio_to_buff field. 5744 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5745 * Access: RW 5746 */ 5747 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5748 5749 /* reg_pptb_untagged_buff 5750 * Mapping of untagged frames to one of the allocated receive port buffers. 5751 * Access: RW 5752 * 5753 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5754 * Spectrum, as it maps untagged packets based on the default switch priority. 5755 */ 5756 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5757 5758 /* reg_pptb_prio_to_buff_msb 5759 * Mapping of switch priority <i+8> to one of the allocated receive port 5760 * buffers. 5761 * Access: RW 5762 */ 5763 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5764 5765 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5766 5767 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5768 { 5769 MLXSW_REG_ZERO(pptb, payload); 5770 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5771 mlxsw_reg_pptb_local_port_set(payload, local_port); 5772 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5773 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5774 } 5775 5776 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5777 u8 buff) 5778 { 5779 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5780 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5781 } 5782 5783 /* PBMC - Port Buffer Management Control Register 5784 * ---------------------------------------------- 5785 * The PBMC register configures and retrieves the port packet buffer 5786 * allocation for different Prios, and the Pause threshold management. 5787 */ 5788 #define MLXSW_REG_PBMC_ID 0x500C 5789 #define MLXSW_REG_PBMC_LEN 0x6C 5790 5791 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5792 5793 /* reg_pbmc_local_port 5794 * Local port number. 5795 * Access: Index 5796 */ 5797 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5798 5799 /* reg_pbmc_xoff_timer_value 5800 * When device generates a pause frame, it uses this value as the pause 5801 * timer (time for the peer port to pause in quota-512 bit time). 5802 * Access: RW 5803 */ 5804 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5805 5806 /* reg_pbmc_xoff_refresh 5807 * The time before a new pause frame should be sent to refresh the pause RW 5808 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5809 * time). 5810 * Access: RW 5811 */ 5812 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5813 5814 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5815 5816 /* reg_pbmc_buf_lossy 5817 * The field indicates if the buffer is lossy. 5818 * 0 - Lossless 5819 * 1 - Lossy 5820 * Access: RW 5821 */ 5822 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5823 5824 /* reg_pbmc_buf_epsb 5825 * Eligible for Port Shared buffer. 5826 * If epsb is set, packets assigned to buffer are allowed to insert the port 5827 * shared buffer. 5828 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5829 * Access: RW 5830 */ 5831 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5832 5833 /* reg_pbmc_buf_size 5834 * The part of the packet buffer array is allocated for the specific buffer. 5835 * Units are represented in cells. 5836 * Access: RW 5837 */ 5838 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5839 5840 /* reg_pbmc_buf_xoff_threshold 5841 * Once the amount of data in the buffer goes above this value, device 5842 * starts sending PFC frames for all priorities associated with the 5843 * buffer. Units are represented in cells. Reserved in case of lossy 5844 * buffer. 5845 * Access: RW 5846 * 5847 * Note: In Spectrum, reserved for buffer[9]. 5848 */ 5849 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5850 0x08, 0x04, false); 5851 5852 /* reg_pbmc_buf_xon_threshold 5853 * When the amount of data in the buffer goes below this value, device 5854 * stops sending PFC frames for the priorities associated with the 5855 * buffer. Units are represented in cells. Reserved in case of lossy 5856 * buffer. 5857 * Access: RW 5858 * 5859 * Note: In Spectrum, reserved for buffer[9]. 5860 */ 5861 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5862 0x08, 0x04, false); 5863 5864 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5865 u16 xoff_timer_value, u16 xoff_refresh) 5866 { 5867 MLXSW_REG_ZERO(pbmc, payload); 5868 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5869 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5870 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5871 } 5872 5873 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5874 int buf_index, 5875 u16 size) 5876 { 5877 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5878 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5879 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5880 } 5881 5882 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5883 int buf_index, u16 size, 5884 u16 threshold) 5885 { 5886 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5887 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5888 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5889 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5890 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5891 } 5892 5893 /* PSPA - Port Switch Partition Allocation 5894 * --------------------------------------- 5895 * Controls the association of a port with a switch partition and enables 5896 * configuring ports as stacking ports. 5897 */ 5898 #define MLXSW_REG_PSPA_ID 0x500D 5899 #define MLXSW_REG_PSPA_LEN 0x8 5900 5901 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5902 5903 /* reg_pspa_swid 5904 * Switch partition ID. 5905 * Access: RW 5906 */ 5907 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5908 5909 /* reg_pspa_local_port 5910 * Local port number. 5911 * Access: Index 5912 */ 5913 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5914 5915 /* reg_pspa_sub_port 5916 * Virtual port within the local port. Set to 0 when virtual ports are 5917 * disabled on the local port. 5918 * Access: Index 5919 */ 5920 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5921 5922 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5923 { 5924 MLXSW_REG_ZERO(pspa, payload); 5925 mlxsw_reg_pspa_swid_set(payload, swid); 5926 mlxsw_reg_pspa_local_port_set(payload, local_port); 5927 mlxsw_reg_pspa_sub_port_set(payload, 0); 5928 } 5929 5930 /* PMAOS - Ports Module Administrative and Operational Status 5931 * ---------------------------------------------------------- 5932 * This register configures and retrieves the per module status. 5933 */ 5934 #define MLXSW_REG_PMAOS_ID 0x5012 5935 #define MLXSW_REG_PMAOS_LEN 0x10 5936 5937 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5938 5939 /* reg_pmaos_rst 5940 * Module reset toggle. 5941 * Note: Setting reset while module is plugged-in will result in transition to 5942 * "initializing" operational state. 5943 * Access: OP 5944 */ 5945 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5946 5947 /* reg_pmaos_slot_index 5948 * Slot index. 5949 * Access: Index 5950 */ 5951 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5952 5953 /* reg_pmaos_module 5954 * Module number. 5955 * Access: Index 5956 */ 5957 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5958 5959 enum mlxsw_reg_pmaos_admin_status { 5960 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5961 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5962 /* If the module is active and then unplugged, or experienced an error 5963 * event, the operational status should go to "disabled" and can only 5964 * be enabled upon explicit enable command. 5965 */ 5966 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5967 }; 5968 5969 /* reg_pmaos_admin_status 5970 * Module administrative state (the desired state of the module). 5971 * Note: To disable a module, all ports associated with the port must be 5972 * administatively down first. 5973 * Access: RW 5974 */ 5975 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5976 5977 /* reg_pmaos_ase 5978 * Admin state update enable. 5979 * If this bit is set, admin state will be updated based on admin_state field. 5980 * Only relevant on Set() operations. 5981 * Access: WO 5982 */ 5983 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5984 5985 /* reg_pmaos_ee 5986 * Event update enable. 5987 * If this bit is set, event generation will be updated based on the e field. 5988 * Only relevant on Set operations. 5989 * Access: WO 5990 */ 5991 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5992 5993 enum mlxsw_reg_pmaos_e { 5994 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5995 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5996 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5997 }; 5998 5999 /* reg_pmaos_e 6000 * Event Generation on operational state change. 6001 * Access: RW 6002 */ 6003 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 6004 6005 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 6006 { 6007 MLXSW_REG_ZERO(pmaos, payload); 6008 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 6009 mlxsw_reg_pmaos_module_set(payload, module); 6010 } 6011 6012 /* PPLR - Port Physical Loopback Register 6013 * -------------------------------------- 6014 * This register allows configuration of the port's loopback mode. 6015 */ 6016 #define MLXSW_REG_PPLR_ID 0x5018 6017 #define MLXSW_REG_PPLR_LEN 0x8 6018 6019 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 6020 6021 /* reg_pplr_local_port 6022 * Local port number. 6023 * Access: Index 6024 */ 6025 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 6026 6027 /* Phy local loopback. When set the port's egress traffic is looped back 6028 * to the receiver and the port transmitter is disabled. 6029 */ 6030 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 6031 6032 /* reg_pplr_lb_en 6033 * Loopback enable. 6034 * Access: RW 6035 */ 6036 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 6037 6038 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 6039 bool phy_local) 6040 { 6041 MLXSW_REG_ZERO(pplr, payload); 6042 mlxsw_reg_pplr_local_port_set(payload, local_port); 6043 mlxsw_reg_pplr_lb_en_set(payload, 6044 phy_local ? 6045 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 6046 } 6047 6048 /* PMTDB - Port Module To local DataBase Register 6049 * ---------------------------------------------- 6050 * The PMTDB register allows to query the possible module<->local port 6051 * mapping than can be used in PMLP. It does not represent the actual/current 6052 * mapping of the local to module. Actual mapping is only defined by PMLP. 6053 */ 6054 #define MLXSW_REG_PMTDB_ID 0x501A 6055 #define MLXSW_REG_PMTDB_LEN 0x40 6056 6057 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 6058 6059 /* reg_pmtdb_slot_index 6060 * Slot index (0: Main board). 6061 * Access: Index 6062 */ 6063 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 6064 6065 /* reg_pmtdb_module 6066 * Module number. 6067 * Access: Index 6068 */ 6069 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 6070 6071 /* reg_pmtdb_ports_width 6072 * Port's width 6073 * Access: Index 6074 */ 6075 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 6076 6077 /* reg_pmtdb_num_ports 6078 * Number of ports in a single module (split/breakout) 6079 * Access: Index 6080 */ 6081 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 6082 6083 enum mlxsw_reg_pmtdb_status { 6084 MLXSW_REG_PMTDB_STATUS_SUCCESS, 6085 }; 6086 6087 /* reg_pmtdb_status 6088 * Status 6089 * Access: RO 6090 */ 6091 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 6092 6093 /* reg_pmtdb_port_num 6094 * The local_port value which can be assigned to the module. 6095 * In case of more than one port, port<x> represent the /<x> port of 6096 * the module. 6097 * Access: RO 6098 */ 6099 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 6100 6101 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 6102 u8 ports_width, u8 num_ports) 6103 { 6104 MLXSW_REG_ZERO(pmtdb, payload); 6105 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 6106 mlxsw_reg_pmtdb_module_set(payload, module); 6107 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 6108 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 6109 } 6110 6111 /* PMECR - Ports Mapping Event Configuration Register 6112 * -------------------------------------------------- 6113 * The PMECR register is used to enable/disable event triggering 6114 * in case of local port mapping change. 6115 */ 6116 #define MLXSW_REG_PMECR_ID 0x501B 6117 #define MLXSW_REG_PMECR_LEN 0x20 6118 6119 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 6120 6121 /* reg_pmecr_local_port 6122 * Local port number. 6123 * Access: Index 6124 */ 6125 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 6126 6127 /* reg_pmecr_ee 6128 * Event update enable. If this bit is set, event generation will be updated 6129 * based on the e field. Only relevant on Set operations. 6130 * Access: WO 6131 */ 6132 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 6133 6134 /* reg_pmecr_eswi 6135 * Software ignore enable bit. If this bit is set, the value of swi is used. 6136 * If this bit is clear, the value of swi is ignored. 6137 * Only relevant on Set operations. 6138 * Access: WO 6139 */ 6140 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6141 6142 /* reg_pmecr_swi 6143 * Software ignore. If this bit is set, the device shouldn't generate events 6144 * in case of PMLP SET operation but only upon self local port mapping change 6145 * (if applicable according to e configuration). This is supplementary 6146 * configuration on top of e value. 6147 * Access: RW 6148 */ 6149 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6150 6151 enum mlxsw_reg_pmecr_e { 6152 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6153 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6154 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6155 }; 6156 6157 /* reg_pmecr_e 6158 * Event generation on local port mapping change. 6159 * Access: RW 6160 */ 6161 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6162 6163 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6164 enum mlxsw_reg_pmecr_e e) 6165 { 6166 MLXSW_REG_ZERO(pmecr, payload); 6167 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6168 mlxsw_reg_pmecr_e_set(payload, e); 6169 mlxsw_reg_pmecr_ee_set(payload, true); 6170 mlxsw_reg_pmecr_swi_set(payload, true); 6171 mlxsw_reg_pmecr_eswi_set(payload, true); 6172 } 6173 6174 /* PMPE - Port Module Plug/Unplug Event Register 6175 * --------------------------------------------- 6176 * This register reports any operational status change of a module. 6177 * A change in the module’s state will generate an event only if the change 6178 * happens after arming the event mechanism. Any changes to the module state 6179 * while the event mechanism is not armed will not be reported. Software can 6180 * query the PMPE register for module status. 6181 */ 6182 #define MLXSW_REG_PMPE_ID 0x5024 6183 #define MLXSW_REG_PMPE_LEN 0x10 6184 6185 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6186 6187 /* reg_pmpe_slot_index 6188 * Slot index. 6189 * Access: Index 6190 */ 6191 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6192 6193 /* reg_pmpe_module 6194 * Module number. 6195 * Access: Index 6196 */ 6197 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6198 6199 enum mlxsw_reg_pmpe_module_status { 6200 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6201 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6202 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6203 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6204 }; 6205 6206 /* reg_pmpe_module_status 6207 * Module status. 6208 * Access: RO 6209 */ 6210 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6211 6212 /* reg_pmpe_error_type 6213 * Module error details. 6214 * Access: RO 6215 */ 6216 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6217 6218 /* PDDR - Port Diagnostics Database Register 6219 * ----------------------------------------- 6220 * The PDDR enables to read the Phy debug database 6221 */ 6222 #define MLXSW_REG_PDDR_ID 0x5031 6223 #define MLXSW_REG_PDDR_LEN 0x100 6224 6225 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6226 6227 /* reg_pddr_local_port 6228 * Local port number. 6229 * Access: Index 6230 */ 6231 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6232 6233 enum mlxsw_reg_pddr_page_select { 6234 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6235 }; 6236 6237 /* reg_pddr_page_select 6238 * Page select index. 6239 * Access: Index 6240 */ 6241 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6242 6243 enum mlxsw_reg_pddr_trblsh_group_opcode { 6244 /* Monitor opcodes */ 6245 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6246 }; 6247 6248 /* reg_pddr_group_opcode 6249 * Group selector. 6250 * Access: Index 6251 */ 6252 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6253 6254 /* reg_pddr_status_opcode 6255 * Group selector. 6256 * Access: RO 6257 */ 6258 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6259 6260 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6261 u8 page_select) 6262 { 6263 MLXSW_REG_ZERO(pddr, payload); 6264 mlxsw_reg_pddr_local_port_set(payload, local_port); 6265 mlxsw_reg_pddr_page_select_set(payload, page_select); 6266 } 6267 6268 /* PMMP - Port Module Memory Map Properties Register 6269 * ------------------------------------------------- 6270 * The PMMP register allows to override the module memory map advertisement. 6271 * The register can only be set when the module is disabled by PMAOS register. 6272 */ 6273 #define MLXSW_REG_PMMP_ID 0x5044 6274 #define MLXSW_REG_PMMP_LEN 0x2C 6275 6276 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6277 6278 /* reg_pmmp_module 6279 * Module number. 6280 * Access: Index 6281 */ 6282 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6283 6284 /* reg_pmmp_slot_index 6285 * Slot index. 6286 * Access: Index 6287 */ 6288 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6289 6290 /* reg_pmmp_sticky 6291 * When set, will keep eeprom_override values after plug-out event. 6292 * Access: OP 6293 */ 6294 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6295 6296 /* reg_pmmp_eeprom_override_mask 6297 * Write mask bit (negative polarity). 6298 * 0 - Allow write 6299 * 1 - Ignore write 6300 * On write, indicates which of the bits from eeprom_override field are 6301 * updated. 6302 * Access: WO 6303 */ 6304 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6305 6306 enum { 6307 /* Set module to low power mode */ 6308 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6309 }; 6310 6311 /* reg_pmmp_eeprom_override 6312 * Override / ignore EEPROM advertisement properties bitmask 6313 * Access: RW 6314 */ 6315 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6316 6317 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6318 { 6319 MLXSW_REG_ZERO(pmmp, payload); 6320 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6321 mlxsw_reg_pmmp_module_set(payload, module); 6322 } 6323 6324 /* PLLP - Port Local port to Label Port mapping Register 6325 * ----------------------------------------------------- 6326 * The PLLP register returns the mapping from Local Port into Label Port. 6327 */ 6328 #define MLXSW_REG_PLLP_ID 0x504A 6329 #define MLXSW_REG_PLLP_LEN 0x10 6330 6331 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6332 6333 /* reg_pllp_local_port 6334 * Local port number. 6335 * Access: Index 6336 */ 6337 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6338 6339 /* reg_pllp_label_port 6340 * Front panel label of the port. 6341 * Access: RO 6342 */ 6343 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6344 6345 /* reg_pllp_split_num 6346 * Label split mapping for local_port. 6347 * Access: RO 6348 */ 6349 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6350 6351 /* reg_pllp_slot_index 6352 * Slot index (0: Main board). 6353 * Access: RO 6354 */ 6355 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6356 6357 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6358 { 6359 MLXSW_REG_ZERO(pllp, payload); 6360 mlxsw_reg_pllp_local_port_set(payload, local_port); 6361 } 6362 6363 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6364 u8 *split_num, u8 *slot_index) 6365 { 6366 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6367 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6368 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6369 } 6370 6371 /* PMTM - Port Module Type Mapping Register 6372 * ---------------------------------------- 6373 * The PMTM register allows query or configuration of module types. 6374 * The register can only be set when the module is disabled by PMAOS register 6375 */ 6376 #define MLXSW_REG_PMTM_ID 0x5067 6377 #define MLXSW_REG_PMTM_LEN 0x10 6378 6379 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6380 6381 /* reg_pmtm_slot_index 6382 * Slot index. 6383 * Access: Index 6384 */ 6385 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6386 6387 /* reg_pmtm_module 6388 * Module number. 6389 * Access: Index 6390 */ 6391 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6392 6393 enum mlxsw_reg_pmtm_module_type { 6394 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6395 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6396 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6397 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6398 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6399 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6400 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6401 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6402 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6403 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6404 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6405 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6406 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6407 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6408 }; 6409 6410 /* reg_pmtm_module_type 6411 * Module type. 6412 * Access: RW 6413 */ 6414 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6415 6416 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6417 { 6418 MLXSW_REG_ZERO(pmtm, payload); 6419 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6420 mlxsw_reg_pmtm_module_set(payload, module); 6421 } 6422 6423 /* HTGT - Host Trap Group Table 6424 * ---------------------------- 6425 * Configures the properties for forwarding to CPU. 6426 */ 6427 #define MLXSW_REG_HTGT_ID 0x7002 6428 #define MLXSW_REG_HTGT_LEN 0x20 6429 6430 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6431 6432 /* reg_htgt_swid 6433 * Switch partition ID. 6434 * Access: Index 6435 */ 6436 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6437 6438 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6439 6440 /* reg_htgt_type 6441 * CPU path type. 6442 * Access: RW 6443 */ 6444 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6445 6446 enum mlxsw_reg_htgt_trap_group { 6447 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6448 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6449 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6450 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6451 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6452 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6453 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6454 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6455 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6456 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6457 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6458 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6459 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6460 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6461 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6462 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6463 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6464 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6465 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6466 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6467 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6468 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6469 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6470 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6471 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6472 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6473 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6474 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6475 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6476 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6477 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6478 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6479 6480 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6481 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6482 }; 6483 6484 /* reg_htgt_trap_group 6485 * Trap group number. User defined number specifying which trap groups 6486 * should be forwarded to the CPU. The mapping between trap IDs and trap 6487 * groups is configured using HPKT register. 6488 * Access: Index 6489 */ 6490 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6491 6492 enum { 6493 MLXSW_REG_HTGT_POLICER_DISABLE, 6494 MLXSW_REG_HTGT_POLICER_ENABLE, 6495 }; 6496 6497 /* reg_htgt_pide 6498 * Enable policer ID specified using 'pid' field. 6499 * Access: RW 6500 */ 6501 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6502 6503 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6504 6505 /* reg_htgt_pid 6506 * Policer ID for the trap group. 6507 * Access: RW 6508 */ 6509 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6510 6511 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6512 6513 /* reg_htgt_mirror_action 6514 * Mirror action to use. 6515 * 0 - Trap to CPU. 6516 * 1 - Trap to CPU and mirror to a mirroring agent. 6517 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6518 * Access: RW 6519 * 6520 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6521 */ 6522 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6523 6524 /* reg_htgt_mirroring_agent 6525 * Mirroring agent. 6526 * Access: RW 6527 */ 6528 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6529 6530 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6531 6532 /* reg_htgt_priority 6533 * Trap group priority. 6534 * In case a packet matches multiple classification rules, the packet will 6535 * only be trapped once, based on the trap ID associated with the group (via 6536 * register HPKT) with the highest priority. 6537 * Supported values are 0-7, with 7 represnting the highest priority. 6538 * Access: RW 6539 * 6540 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6541 * by the 'trap_group' field. 6542 */ 6543 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6544 6545 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6546 6547 /* reg_htgt_local_path_cpu_tclass 6548 * CPU ingress traffic class for the trap group. 6549 * Access: RW 6550 */ 6551 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6552 6553 enum mlxsw_reg_htgt_local_path_rdq { 6554 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6555 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6556 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6557 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6558 }; 6559 /* reg_htgt_local_path_rdq 6560 * Receive descriptor queue (RDQ) to use for the trap group. 6561 * Access: RW 6562 */ 6563 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6564 6565 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6566 u8 priority, u8 tc) 6567 { 6568 MLXSW_REG_ZERO(htgt, payload); 6569 6570 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6571 mlxsw_reg_htgt_pide_set(payload, 6572 MLXSW_REG_HTGT_POLICER_DISABLE); 6573 } else { 6574 mlxsw_reg_htgt_pide_set(payload, 6575 MLXSW_REG_HTGT_POLICER_ENABLE); 6576 mlxsw_reg_htgt_pid_set(payload, policer_id); 6577 } 6578 6579 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6580 mlxsw_reg_htgt_trap_group_set(payload, group); 6581 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6582 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6583 mlxsw_reg_htgt_priority_set(payload, priority); 6584 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6585 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6586 } 6587 6588 /* HPKT - Host Packet Trap 6589 * ----------------------- 6590 * Configures trap IDs inside trap groups. 6591 */ 6592 #define MLXSW_REG_HPKT_ID 0x7003 6593 #define MLXSW_REG_HPKT_LEN 0x10 6594 6595 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6596 6597 enum { 6598 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6599 MLXSW_REG_HPKT_ACK_REQUIRED, 6600 }; 6601 6602 /* reg_hpkt_ack 6603 * Require acknowledgements from the host for events. 6604 * If set, then the device will wait for the event it sent to be acknowledged 6605 * by the host. This option is only relevant for event trap IDs. 6606 * Access: RW 6607 * 6608 * Note: Currently not supported by firmware. 6609 */ 6610 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6611 6612 enum mlxsw_reg_hpkt_action { 6613 MLXSW_REG_HPKT_ACTION_FORWARD, 6614 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6615 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6616 MLXSW_REG_HPKT_ACTION_DISCARD, 6617 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6618 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6619 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6620 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6621 }; 6622 6623 /* reg_hpkt_action 6624 * Action to perform on packet when trapped. 6625 * 0 - No action. Forward to CPU based on switching rules. 6626 * 1 - Trap to CPU (CPU receives sole copy). 6627 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6628 * 3 - Discard. 6629 * 4 - Soft discard (allow other traps to act on the packet). 6630 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6631 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6632 * 15 - Restore the firmware's default action. 6633 * Access: RW 6634 * 6635 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6636 * addressed to the CPU. 6637 */ 6638 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6639 6640 /* reg_hpkt_trap_group 6641 * Trap group to associate the trap with. 6642 * Access: RW 6643 */ 6644 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6645 6646 /* reg_hpkt_trap_id 6647 * Trap ID. 6648 * Access: Index 6649 * 6650 * Note: A trap ID can only be associated with a single trap group. The device 6651 * will associate the trap ID with the last trap group configured. 6652 */ 6653 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6654 6655 enum { 6656 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6657 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6658 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6659 }; 6660 6661 /* reg_hpkt_ctrl 6662 * Configure dedicated buffer resources for control packets. 6663 * Ignored by SwitchX-2. 6664 * 0 - Keep factory defaults. 6665 * 1 - Do not use control buffer for this trap ID. 6666 * 2 - Use control buffer for this trap ID. 6667 * Access: RW 6668 */ 6669 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6670 6671 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6672 enum mlxsw_reg_htgt_trap_group trap_group, 6673 bool is_ctrl) 6674 { 6675 MLXSW_REG_ZERO(hpkt, payload); 6676 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6677 mlxsw_reg_hpkt_action_set(payload, action); 6678 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6679 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6680 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6681 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6682 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6683 } 6684 6685 /* RGCR - Router General Configuration Register 6686 * -------------------------------------------- 6687 * The register is used for setting up the router configuration. 6688 */ 6689 #define MLXSW_REG_RGCR_ID 0x8001 6690 #define MLXSW_REG_RGCR_LEN 0x28 6691 6692 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6693 6694 /* reg_rgcr_ipv4_en 6695 * IPv4 router enable. 6696 * Access: RW 6697 */ 6698 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6699 6700 /* reg_rgcr_ipv6_en 6701 * IPv6 router enable. 6702 * Access: RW 6703 */ 6704 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6705 6706 /* reg_rgcr_max_router_interfaces 6707 * Defines the maximum number of active router interfaces for all virtual 6708 * routers. 6709 * Access: RW 6710 */ 6711 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6712 6713 /* reg_rgcr_usp 6714 * Update switch priority and packet color. 6715 * 0 - Preserve the value of Switch Priority and packet color. 6716 * 1 - Recalculate the value of Switch Priority and packet color. 6717 * Access: RW 6718 * 6719 * Note: Not supported by SwitchX and SwitchX-2. 6720 */ 6721 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6722 6723 /* reg_rgcr_pcp_rw 6724 * Indicates how to handle the pcp_rewrite_en value: 6725 * 0 - Preserve the value of pcp_rewrite_en. 6726 * 2 - Disable PCP rewrite. 6727 * 3 - Enable PCP rewrite. 6728 * Access: RW 6729 * 6730 * Note: Not supported by SwitchX and SwitchX-2. 6731 */ 6732 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6733 6734 /* reg_rgcr_activity_dis 6735 * Activity disable: 6736 * 0 - Activity will be set when an entry is hit (default). 6737 * 1 - Activity will not be set when an entry is hit. 6738 * 6739 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6740 * (RALUE). 6741 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6742 * Entry (RAUHT). 6743 * Bits 2:7 are reserved. 6744 * Access: RW 6745 * 6746 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6747 */ 6748 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6749 6750 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6751 bool ipv6_en) 6752 { 6753 MLXSW_REG_ZERO(rgcr, payload); 6754 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6755 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6756 } 6757 6758 /* RITR - Router Interface Table Register 6759 * -------------------------------------- 6760 * The register is used to configure the router interface table. 6761 */ 6762 #define MLXSW_REG_RITR_ID 0x8002 6763 #define MLXSW_REG_RITR_LEN 0x40 6764 6765 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6766 6767 /* reg_ritr_enable 6768 * Enables routing on the router interface. 6769 * Access: RW 6770 */ 6771 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6772 6773 /* reg_ritr_ipv4 6774 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6775 * interface. 6776 * Access: RW 6777 */ 6778 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6779 6780 /* reg_ritr_ipv6 6781 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6782 * interface. 6783 * Access: RW 6784 */ 6785 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6786 6787 /* reg_ritr_ipv4_mc 6788 * IPv4 multicast routing enable. 6789 * Access: RW 6790 */ 6791 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6792 6793 /* reg_ritr_ipv6_mc 6794 * IPv6 multicast routing enable. 6795 * Access: RW 6796 */ 6797 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6798 6799 enum mlxsw_reg_ritr_if_type { 6800 /* VLAN interface. */ 6801 MLXSW_REG_RITR_VLAN_IF, 6802 /* FID interface. */ 6803 MLXSW_REG_RITR_FID_IF, 6804 /* Sub-port interface. */ 6805 MLXSW_REG_RITR_SP_IF, 6806 /* Loopback Interface. */ 6807 MLXSW_REG_RITR_LOOPBACK_IF, 6808 }; 6809 6810 /* reg_ritr_type 6811 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6812 * Access: RW 6813 */ 6814 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6815 6816 enum { 6817 MLXSW_REG_RITR_RIF_CREATE, 6818 MLXSW_REG_RITR_RIF_DEL, 6819 }; 6820 6821 /* reg_ritr_op 6822 * Opcode: 6823 * 0 - Create or edit RIF. 6824 * 1 - Delete RIF. 6825 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6826 * is not supported. An interface must be deleted and re-created in order 6827 * to update properties. 6828 * Access: WO 6829 */ 6830 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6831 6832 /* reg_ritr_rif 6833 * Router interface index. A pointer to the Router Interface Table. 6834 * Access: Index 6835 */ 6836 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6837 6838 /* reg_ritr_ipv4_fe 6839 * IPv4 Forwarding Enable. 6840 * Enables routing of IPv4 traffic on the router interface. When disabled, 6841 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6842 * Not supported in SwitchX-2. 6843 * Access: RW 6844 */ 6845 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6846 6847 /* reg_ritr_ipv6_fe 6848 * IPv6 Forwarding Enable. 6849 * Enables routing of IPv6 traffic on the router interface. When disabled, 6850 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6851 * Not supported in SwitchX-2. 6852 * Access: RW 6853 */ 6854 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6855 6856 /* reg_ritr_ipv4_mc_fe 6857 * IPv4 Multicast Forwarding Enable. 6858 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6859 * will be enabled. 6860 * Access: RW 6861 */ 6862 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6863 6864 /* reg_ritr_ipv6_mc_fe 6865 * IPv6 Multicast Forwarding Enable. 6866 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6867 * will be enabled. 6868 * Access: RW 6869 */ 6870 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6871 6872 /* reg_ritr_lb_en 6873 * Loop-back filter enable for unicast packets. 6874 * If the flag is set then loop-back filter for unicast packets is 6875 * implemented on the RIF. Multicast packets are always subject to 6876 * loop-back filtering. 6877 * Access: RW 6878 */ 6879 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6880 6881 /* reg_ritr_virtual_router 6882 * Virtual router ID associated with the router interface. 6883 * Access: RW 6884 */ 6885 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6886 6887 /* reg_ritr_mtu 6888 * Router interface MTU. 6889 * Access: RW 6890 */ 6891 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6892 6893 /* reg_ritr_if_swid 6894 * Switch partition ID. 6895 * Access: RW 6896 */ 6897 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6898 6899 /* reg_ritr_if_mac_profile_id 6900 * MAC msb profile ID. 6901 * Access: RW 6902 */ 6903 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6904 6905 /* reg_ritr_if_mac 6906 * Router interface MAC address. 6907 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6908 * Access: RW 6909 */ 6910 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6911 6912 /* reg_ritr_if_vrrp_id_ipv6 6913 * VRRP ID for IPv6 6914 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6915 * Access: RW 6916 */ 6917 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6918 6919 /* reg_ritr_if_vrrp_id_ipv4 6920 * VRRP ID for IPv4 6921 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6922 * Access: RW 6923 */ 6924 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6925 6926 /* VLAN Interface */ 6927 6928 /* reg_ritr_vlan_if_vlan_id 6929 * VLAN ID. 6930 * Access: RW 6931 */ 6932 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6933 6934 /* reg_ritr_vlan_if_efid 6935 * Egress FID. 6936 * Used to connect the RIF to a bridge. 6937 * Access: RW 6938 * 6939 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6940 */ 6941 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6942 6943 /* FID Interface */ 6944 6945 /* reg_ritr_fid_if_fid 6946 * Filtering ID. Used to connect a bridge to the router. 6947 * When legacy bridge model is used, only FIDs from the vFID range are 6948 * supported. When unified bridge model is used, this is the egress FID for 6949 * router to bridge. 6950 * Access: RW 6951 */ 6952 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6953 6954 /* Sub-port Interface */ 6955 6956 /* reg_ritr_sp_if_lag 6957 * LAG indication. When this bit is set the system_port field holds the 6958 * LAG identifier. 6959 * Access: RW 6960 */ 6961 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6962 6963 /* reg_ritr_sp_system_port 6964 * Port unique indentifier. When lag bit is set, this field holds the 6965 * lag_id in bits 0:9. 6966 * Access: RW 6967 */ 6968 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6969 6970 /* reg_ritr_sp_if_efid 6971 * Egress filtering ID. 6972 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6973 * the VID. 6974 * Access: RW 6975 * 6976 * Note: Reserved when legacy bridge model is used. 6977 */ 6978 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6979 6980 /* reg_ritr_sp_if_vid 6981 * VLAN ID. 6982 * Access: RW 6983 */ 6984 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6985 6986 /* Loopback Interface */ 6987 6988 enum mlxsw_reg_ritr_loopback_protocol { 6989 /* IPinIP IPv4 underlay Unicast */ 6990 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6991 /* IPinIP IPv6 underlay Unicast */ 6992 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6993 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6994 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6995 }; 6996 6997 /* reg_ritr_loopback_protocol 6998 * Access: RW 6999 */ 7000 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 7001 7002 enum mlxsw_reg_ritr_loopback_ipip_type { 7003 /* Tunnel is IPinIP. */ 7004 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 7005 /* Tunnel is GRE, no key. */ 7006 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 7007 /* Tunnel is GRE, with a key. */ 7008 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 7009 }; 7010 7011 /* reg_ritr_loopback_ipip_type 7012 * Encapsulation type. 7013 * Access: RW 7014 */ 7015 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 7016 7017 enum mlxsw_reg_ritr_loopback_ipip_options { 7018 /* The key is defined by gre_key. */ 7019 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 7020 }; 7021 7022 /* reg_ritr_loopback_ipip_options 7023 * Access: RW 7024 */ 7025 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 7026 7027 /* reg_ritr_loopback_ipip_uvr 7028 * Underlay Virtual Router ID. 7029 * Range is 0..cap_max_virtual_routers-1. 7030 * Reserved for Spectrum-2. 7031 * Access: RW 7032 */ 7033 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 7034 7035 /* reg_ritr_loopback_ipip_underlay_rif 7036 * Underlay ingress router interface. 7037 * Reserved for Spectrum. 7038 * Access: RW 7039 */ 7040 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 7041 7042 /* reg_ritr_loopback_ipip_usip* 7043 * Encapsulation Underlay source IP. 7044 * Access: RW 7045 */ 7046 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 7047 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 7048 7049 /* reg_ritr_loopback_ipip_gre_key 7050 * GRE Key. 7051 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 7052 * Access: RW 7053 */ 7054 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 7055 7056 /* Shared between ingress/egress */ 7057 enum mlxsw_reg_ritr_counter_set_type { 7058 /* No Count. */ 7059 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 7060 /* Basic. Used for router interfaces, counting the following: 7061 * - Error and Discard counters. 7062 * - Unicast, Multicast and Broadcast counters. Sharing the 7063 * same set of counters for the different type of traffic 7064 * (IPv4, IPv6 and mpls). 7065 */ 7066 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 7067 }; 7068 7069 /* reg_ritr_ingress_counter_index 7070 * Counter Index for flow counter. 7071 * Access: RW 7072 */ 7073 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 7074 7075 /* reg_ritr_ingress_counter_set_type 7076 * Igress Counter Set Type for router interface counter. 7077 * Access: RW 7078 */ 7079 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 7080 7081 /* reg_ritr_egress_counter_index 7082 * Counter Index for flow counter. 7083 * Access: RW 7084 */ 7085 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 7086 7087 /* reg_ritr_egress_counter_set_type 7088 * Egress Counter Set Type for router interface counter. 7089 * Access: RW 7090 */ 7091 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 7092 7093 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 7094 bool enable, bool egress) 7095 { 7096 enum mlxsw_reg_ritr_counter_set_type set_type; 7097 7098 if (enable) 7099 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 7100 else 7101 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 7102 7103 if (egress) { 7104 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 7105 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 7106 } else { 7107 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 7108 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 7109 } 7110 } 7111 7112 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 7113 { 7114 MLXSW_REG_ZERO(ritr, payload); 7115 mlxsw_reg_ritr_rif_set(payload, rif); 7116 } 7117 7118 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 7119 u16 system_port, u16 efid, u16 vid) 7120 { 7121 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 7122 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 7123 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 7124 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 7125 } 7126 7127 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 7128 enum mlxsw_reg_ritr_if_type type, 7129 u16 rif, u16 vr_id, u16 mtu) 7130 { 7131 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 7132 7133 MLXSW_REG_ZERO(ritr, payload); 7134 mlxsw_reg_ritr_enable_set(payload, enable); 7135 mlxsw_reg_ritr_ipv4_set(payload, 1); 7136 mlxsw_reg_ritr_ipv6_set(payload, 1); 7137 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7138 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7139 mlxsw_reg_ritr_type_set(payload, type); 7140 mlxsw_reg_ritr_op_set(payload, op); 7141 mlxsw_reg_ritr_rif_set(payload, rif); 7142 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7143 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7144 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7145 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7146 mlxsw_reg_ritr_lb_en_set(payload, 1); 7147 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7148 mlxsw_reg_ritr_mtu_set(payload, mtu); 7149 } 7150 7151 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7152 { 7153 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7154 } 7155 7156 static inline void 7157 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7158 u16 mtu, const char *mac, u8 mac_profile_id, 7159 u16 vlan_id, u16 efid) 7160 { 7161 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7162 7163 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7164 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7165 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7166 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7167 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7168 } 7169 7170 static inline void 7171 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7172 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7173 enum mlxsw_reg_ritr_loopback_ipip_options options, 7174 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7175 { 7176 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7177 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7178 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7179 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7180 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7181 } 7182 7183 static inline void 7184 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7185 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7186 enum mlxsw_reg_ritr_loopback_ipip_options options, 7187 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7188 { 7189 mlxsw_reg_ritr_loopback_protocol_set(payload, 7190 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7191 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7192 uvr_id, underlay_rif, gre_key); 7193 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7194 } 7195 7196 static inline void 7197 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7198 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7199 enum mlxsw_reg_ritr_loopback_ipip_options options, 7200 u16 uvr_id, u16 underlay_rif, 7201 const struct in6_addr *usip, u32 gre_key) 7202 { 7203 enum mlxsw_reg_ritr_loopback_protocol protocol = 7204 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7205 7206 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7207 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7208 uvr_id, underlay_rif, gre_key); 7209 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7210 (const char *)usip); 7211 } 7212 7213 /* RTAR - Router TCAM Allocation Register 7214 * -------------------------------------- 7215 * This register is used for allocation of regions in the TCAM table. 7216 */ 7217 #define MLXSW_REG_RTAR_ID 0x8004 7218 #define MLXSW_REG_RTAR_LEN 0x20 7219 7220 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7221 7222 enum mlxsw_reg_rtar_op { 7223 MLXSW_REG_RTAR_OP_ALLOCATE, 7224 MLXSW_REG_RTAR_OP_RESIZE, 7225 MLXSW_REG_RTAR_OP_DEALLOCATE, 7226 }; 7227 7228 /* reg_rtar_op 7229 * Access: WO 7230 */ 7231 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7232 7233 enum mlxsw_reg_rtar_key_type { 7234 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7235 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7236 }; 7237 7238 /* reg_rtar_key_type 7239 * TCAM key type for the region. 7240 * Access: WO 7241 */ 7242 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7243 7244 /* reg_rtar_region_size 7245 * TCAM region size. When allocating/resizing this is the requested 7246 * size, the response is the actual size. 7247 * Note: Actual size may be larger than requested. 7248 * Reserved for op = Deallocate 7249 * Access: WO 7250 */ 7251 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7252 7253 static inline void mlxsw_reg_rtar_pack(char *payload, 7254 enum mlxsw_reg_rtar_op op, 7255 enum mlxsw_reg_rtar_key_type key_type, 7256 u16 region_size) 7257 { 7258 MLXSW_REG_ZERO(rtar, payload); 7259 mlxsw_reg_rtar_op_set(payload, op); 7260 mlxsw_reg_rtar_key_type_set(payload, key_type); 7261 mlxsw_reg_rtar_region_size_set(payload, region_size); 7262 } 7263 7264 /* RATR - Router Adjacency Table Register 7265 * -------------------------------------- 7266 * The RATR register is used to configure the Router Adjacency (next-hop) 7267 * Table. 7268 */ 7269 #define MLXSW_REG_RATR_ID 0x8008 7270 #define MLXSW_REG_RATR_LEN 0x2C 7271 7272 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7273 7274 enum mlxsw_reg_ratr_op { 7275 /* Read */ 7276 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7277 /* Read and clear activity */ 7278 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7279 /* Write Adjacency entry */ 7280 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7281 /* Write Adjacency entry only if the activity is cleared. 7282 * The write may not succeed if the activity is set. There is not 7283 * direct feedback if the write has succeeded or not, however 7284 * the get will reveal the actual entry (SW can compare the get 7285 * response to the set command). 7286 */ 7287 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7288 }; 7289 7290 /* reg_ratr_op 7291 * Note that Write operation may also be used for updating 7292 * counter_set_type and counter_index. In this case all other 7293 * fields must not be updated. 7294 * Access: OP 7295 */ 7296 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7297 7298 /* reg_ratr_v 7299 * Valid bit. Indicates if the adjacency entry is valid. 7300 * Note: the device may need some time before reusing an invalidated 7301 * entry. During this time the entry can not be reused. It is 7302 * recommended to use another entry before reusing an invalidated 7303 * entry (e.g. software can put it at the end of the list for 7304 * reusing). Trying to access an invalidated entry not yet cleared 7305 * by the device results with failure indicating "Try Again" status. 7306 * When valid is '0' then egress_router_interface,trap_action, 7307 * adjacency_parameters and counters are reserved 7308 * Access: RW 7309 */ 7310 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7311 7312 /* reg_ratr_a 7313 * Activity. Set for new entries. Set if a packet lookup has hit on 7314 * the specific entry. To clear the a bit, use "clear activity". 7315 * Access: RO 7316 */ 7317 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7318 7319 enum mlxsw_reg_ratr_type { 7320 /* Ethernet */ 7321 MLXSW_REG_RATR_TYPE_ETHERNET, 7322 /* IPoIB Unicast without GRH. 7323 * Reserved for Spectrum. 7324 */ 7325 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7326 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7327 * adjacency). 7328 * Reserved for Spectrum. 7329 */ 7330 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7331 /* IPoIB Multicast. 7332 * Reserved for Spectrum. 7333 */ 7334 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7335 /* MPLS. 7336 * Reserved for SwitchX/-2. 7337 */ 7338 MLXSW_REG_RATR_TYPE_MPLS, 7339 /* IPinIP Encap. 7340 * Reserved for SwitchX/-2. 7341 */ 7342 MLXSW_REG_RATR_TYPE_IPIP, 7343 }; 7344 7345 /* reg_ratr_type 7346 * Adjacency entry type. 7347 * Access: RW 7348 */ 7349 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7350 7351 /* reg_ratr_adjacency_index_low 7352 * Bits 15:0 of index into the adjacency table. 7353 * For SwitchX and SwitchX-2, the adjacency table is linear and 7354 * used for adjacency entries only. 7355 * For Spectrum, the index is to the KVD linear. 7356 * Access: Index 7357 */ 7358 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7359 7360 /* reg_ratr_egress_router_interface 7361 * Range is 0 .. cap_max_router_interfaces - 1 7362 * Access: RW 7363 */ 7364 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7365 7366 enum mlxsw_reg_ratr_trap_action { 7367 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7368 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7369 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7370 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7371 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7372 }; 7373 7374 /* reg_ratr_trap_action 7375 * see mlxsw_reg_ratr_trap_action 7376 * Access: RW 7377 */ 7378 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7379 7380 /* reg_ratr_adjacency_index_high 7381 * Bits 23:16 of the adjacency_index. 7382 * Access: Index 7383 */ 7384 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7385 7386 enum mlxsw_reg_ratr_trap_id { 7387 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7388 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7389 }; 7390 7391 /* reg_ratr_trap_id 7392 * Trap ID to be reported to CPU. 7393 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7394 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7395 * Access: RW 7396 */ 7397 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7398 7399 /* reg_ratr_eth_destination_mac 7400 * MAC address of the destination next-hop. 7401 * Access: RW 7402 */ 7403 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7404 7405 enum mlxsw_reg_ratr_ipip_type { 7406 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7407 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7408 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7409 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7410 }; 7411 7412 /* reg_ratr_ipip_type 7413 * Underlay destination ip type. 7414 * Note: the type field must match the protocol of the router interface. 7415 * Access: RW 7416 */ 7417 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7418 7419 /* reg_ratr_ipip_ipv4_udip 7420 * Underlay ipv4 dip. 7421 * Reserved when ipip_type is IPv6. 7422 * Access: RW 7423 */ 7424 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7425 7426 /* reg_ratr_ipip_ipv6_ptr 7427 * Pointer to IPv6 underlay destination ip address. 7428 * For Spectrum: Pointer to KVD linear space. 7429 * Access: RW 7430 */ 7431 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7432 7433 enum mlxsw_reg_flow_counter_set_type { 7434 /* No count */ 7435 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7436 /* Count packets and bytes */ 7437 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7438 /* Count only packets */ 7439 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7440 }; 7441 7442 /* reg_ratr_counter_set_type 7443 * Counter set type for flow counters 7444 * Access: RW 7445 */ 7446 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7447 7448 /* reg_ratr_counter_index 7449 * Counter index for flow counters 7450 * Access: RW 7451 */ 7452 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7453 7454 static inline void 7455 mlxsw_reg_ratr_pack(char *payload, 7456 enum mlxsw_reg_ratr_op op, bool valid, 7457 enum mlxsw_reg_ratr_type type, 7458 u32 adjacency_index, u16 egress_rif) 7459 { 7460 MLXSW_REG_ZERO(ratr, payload); 7461 mlxsw_reg_ratr_op_set(payload, op); 7462 mlxsw_reg_ratr_v_set(payload, valid); 7463 mlxsw_reg_ratr_type_set(payload, type); 7464 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7465 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7466 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7467 } 7468 7469 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7470 const char *dest_mac) 7471 { 7472 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7473 } 7474 7475 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7476 { 7477 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7478 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7479 } 7480 7481 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7482 { 7483 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7484 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7485 } 7486 7487 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7488 bool counter_enable) 7489 { 7490 enum mlxsw_reg_flow_counter_set_type set_type; 7491 7492 if (counter_enable) 7493 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7494 else 7495 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7496 7497 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7498 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7499 } 7500 7501 /* RDPM - Router DSCP to Priority Mapping 7502 * -------------------------------------- 7503 * Controls the mapping from DSCP field to switch priority on routed packets 7504 */ 7505 #define MLXSW_REG_RDPM_ID 0x8009 7506 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7507 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7508 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7509 #define MLXSW_REG_RDPM_LEN 0x40 7510 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7511 MLXSW_REG_RDPM_LEN - \ 7512 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7513 7514 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7515 7516 /* reg_dscp_entry_e 7517 * Enable update of the specific entry 7518 * Access: Index 7519 */ 7520 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7521 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7522 7523 /* reg_dscp_entry_prio 7524 * Switch Priority 7525 * Access: RW 7526 */ 7527 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7528 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7529 7530 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7531 u8 prio) 7532 { 7533 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7534 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7535 } 7536 7537 /* RICNT - Router Interface Counter Register 7538 * ----------------------------------------- 7539 * The RICNT register retrieves per port performance counters 7540 */ 7541 #define MLXSW_REG_RICNT_ID 0x800B 7542 #define MLXSW_REG_RICNT_LEN 0x100 7543 7544 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7545 7546 /* reg_ricnt_counter_index 7547 * Counter index 7548 * Access: RW 7549 */ 7550 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7551 7552 enum mlxsw_reg_ricnt_counter_set_type { 7553 /* No Count. */ 7554 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7555 /* Basic. Used for router interfaces, counting the following: 7556 * - Error and Discard counters. 7557 * - Unicast, Multicast and Broadcast counters. Sharing the 7558 * same set of counters for the different type of traffic 7559 * (IPv4, IPv6 and mpls). 7560 */ 7561 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7562 }; 7563 7564 /* reg_ricnt_counter_set_type 7565 * Counter Set Type for router interface counter 7566 * Access: RW 7567 */ 7568 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7569 7570 enum mlxsw_reg_ricnt_opcode { 7571 /* Nop. Supported only for read access*/ 7572 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7573 /* Clear. Setting the clr bit will reset the counter value for 7574 * all counters of the specified Router Interface. 7575 */ 7576 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7577 }; 7578 7579 /* reg_ricnt_opcode 7580 * Opcode 7581 * Access: RW 7582 */ 7583 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7584 7585 /* reg_ricnt_good_unicast_packets 7586 * good unicast packets. 7587 * Access: RW 7588 */ 7589 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7590 7591 /* reg_ricnt_good_multicast_packets 7592 * good multicast packets. 7593 * Access: RW 7594 */ 7595 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7596 7597 /* reg_ricnt_good_broadcast_packets 7598 * good broadcast packets 7599 * Access: RW 7600 */ 7601 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7602 7603 /* reg_ricnt_good_unicast_bytes 7604 * A count of L3 data and padding octets not including L2 headers 7605 * for good unicast frames. 7606 * Access: RW 7607 */ 7608 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7609 7610 /* reg_ricnt_good_multicast_bytes 7611 * A count of L3 data and padding octets not including L2 headers 7612 * for good multicast frames. 7613 * Access: RW 7614 */ 7615 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7616 7617 /* reg_ritr_good_broadcast_bytes 7618 * A count of L3 data and padding octets not including L2 headers 7619 * for good broadcast frames. 7620 * Access: RW 7621 */ 7622 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7623 7624 /* reg_ricnt_error_packets 7625 * A count of errored frames that do not pass the router checks. 7626 * Access: RW 7627 */ 7628 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7629 7630 /* reg_ricnt_discrad_packets 7631 * A count of non-errored frames that do not pass the router checks. 7632 * Access: RW 7633 */ 7634 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7635 7636 /* reg_ricnt_error_bytes 7637 * A count of L3 data and padding octets not including L2 headers 7638 * for errored frames. 7639 * Access: RW 7640 */ 7641 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7642 7643 /* reg_ricnt_discard_bytes 7644 * A count of L3 data and padding octets not including L2 headers 7645 * for non-errored frames that do not pass the router checks. 7646 * Access: RW 7647 */ 7648 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7649 7650 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7651 enum mlxsw_reg_ricnt_opcode op) 7652 { 7653 MLXSW_REG_ZERO(ricnt, payload); 7654 mlxsw_reg_ricnt_op_set(payload, op); 7655 mlxsw_reg_ricnt_counter_index_set(payload, index); 7656 mlxsw_reg_ricnt_counter_set_type_set(payload, 7657 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7658 } 7659 7660 /* RRCR - Router Rules Copy Register Layout 7661 * ---------------------------------------- 7662 * This register is used for moving and copying route entry rules. 7663 */ 7664 #define MLXSW_REG_RRCR_ID 0x800F 7665 #define MLXSW_REG_RRCR_LEN 0x24 7666 7667 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7668 7669 enum mlxsw_reg_rrcr_op { 7670 /* Move rules */ 7671 MLXSW_REG_RRCR_OP_MOVE, 7672 /* Copy rules */ 7673 MLXSW_REG_RRCR_OP_COPY, 7674 }; 7675 7676 /* reg_rrcr_op 7677 * Access: WO 7678 */ 7679 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7680 7681 /* reg_rrcr_offset 7682 * Offset within the region from which to copy/move. 7683 * Access: Index 7684 */ 7685 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7686 7687 /* reg_rrcr_size 7688 * The number of rules to copy/move. 7689 * Access: WO 7690 */ 7691 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7692 7693 /* reg_rrcr_table_id 7694 * Identifier of the table on which to perform the operation. Encoding is the 7695 * same as in RTAR.key_type 7696 * Access: Index 7697 */ 7698 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7699 7700 /* reg_rrcr_dest_offset 7701 * Offset within the region to which to copy/move 7702 * Access: Index 7703 */ 7704 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7705 7706 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7707 u16 offset, u16 size, 7708 enum mlxsw_reg_rtar_key_type table_id, 7709 u16 dest_offset) 7710 { 7711 MLXSW_REG_ZERO(rrcr, payload); 7712 mlxsw_reg_rrcr_op_set(payload, op); 7713 mlxsw_reg_rrcr_offset_set(payload, offset); 7714 mlxsw_reg_rrcr_size_set(payload, size); 7715 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7716 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7717 } 7718 7719 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7720 * ------------------------------------------------------- 7721 * RALTA is used to allocate the LPM trees of the SHSPM method. 7722 */ 7723 #define MLXSW_REG_RALTA_ID 0x8010 7724 #define MLXSW_REG_RALTA_LEN 0x04 7725 7726 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7727 7728 /* reg_ralta_op 7729 * opcode (valid for Write, must be 0 on Read) 7730 * 0 - allocate a tree 7731 * 1 - deallocate a tree 7732 * Access: OP 7733 */ 7734 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7735 7736 enum mlxsw_reg_ralxx_protocol { 7737 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7738 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7739 }; 7740 7741 /* reg_ralta_protocol 7742 * Protocol. 7743 * Deallocation opcode: Reserved. 7744 * Access: RW 7745 */ 7746 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7747 7748 /* reg_ralta_tree_id 7749 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7750 * the tree identifier (managed by software). 7751 * Note that tree_id 0 is allocated for a default-route tree. 7752 * Access: Index 7753 */ 7754 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7755 7756 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7757 enum mlxsw_reg_ralxx_protocol protocol, 7758 u8 tree_id) 7759 { 7760 MLXSW_REG_ZERO(ralta, payload); 7761 mlxsw_reg_ralta_op_set(payload, !alloc); 7762 mlxsw_reg_ralta_protocol_set(payload, protocol); 7763 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7764 } 7765 7766 /* RALST - Router Algorithmic LPM Structure Tree Register 7767 * ------------------------------------------------------ 7768 * RALST is used to set and query the structure of an LPM tree. 7769 * The structure of the tree must be sorted as a sorted binary tree, while 7770 * each node is a bin that is tagged as the length of the prefixes the lookup 7771 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7772 * of X bits to match with the destination address. The bin 0 indicates 7773 * the default action, when there is no match of any prefix. 7774 */ 7775 #define MLXSW_REG_RALST_ID 0x8011 7776 #define MLXSW_REG_RALST_LEN 0x104 7777 7778 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7779 7780 /* reg_ralst_root_bin 7781 * The bin number of the root bin. 7782 * 0<root_bin=<(length of IP address) 7783 * For a default-route tree configure 0xff 7784 * Access: RW 7785 */ 7786 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7787 7788 /* reg_ralst_tree_id 7789 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7790 * Access: Index 7791 */ 7792 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7793 7794 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7795 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7796 #define MLXSW_REG_RALST_BIN_COUNT 128 7797 7798 /* reg_ralst_left_child_bin 7799 * Holding the children of the bin according to the stored tree's structure. 7800 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7801 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7802 * Access: RW 7803 */ 7804 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7805 7806 /* reg_ralst_right_child_bin 7807 * Holding the children of the bin according to the stored tree's structure. 7808 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7809 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7810 * Access: RW 7811 */ 7812 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7813 false); 7814 7815 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7816 { 7817 MLXSW_REG_ZERO(ralst, payload); 7818 7819 /* Initialize all bins to have no left or right child */ 7820 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7821 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7822 7823 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7824 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7825 } 7826 7827 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7828 u8 left_child_bin, 7829 u8 right_child_bin) 7830 { 7831 int bin_index = bin_number - 1; 7832 7833 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7834 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7835 right_child_bin); 7836 } 7837 7838 /* RALTB - Router Algorithmic LPM Tree Binding Register 7839 * ---------------------------------------------------- 7840 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7841 */ 7842 #define MLXSW_REG_RALTB_ID 0x8012 7843 #define MLXSW_REG_RALTB_LEN 0x04 7844 7845 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7846 7847 /* reg_raltb_virtual_router 7848 * Virtual Router ID 7849 * Range is 0..cap_max_virtual_routers-1 7850 * Access: Index 7851 */ 7852 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7853 7854 /* reg_raltb_protocol 7855 * Protocol. 7856 * Access: Index 7857 */ 7858 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7859 7860 /* reg_raltb_tree_id 7861 * Tree to be used for the {virtual_router, protocol} 7862 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7863 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7864 * Access: RW 7865 */ 7866 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7867 7868 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7869 enum mlxsw_reg_ralxx_protocol protocol, 7870 u8 tree_id) 7871 { 7872 MLXSW_REG_ZERO(raltb, payload); 7873 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7874 mlxsw_reg_raltb_protocol_set(payload, protocol); 7875 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7876 } 7877 7878 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7879 * ----------------------------------------------------- 7880 * RALUE is used to configure and query LPM entries that serve 7881 * the Unicast protocols. 7882 */ 7883 #define MLXSW_REG_RALUE_ID 0x8013 7884 #define MLXSW_REG_RALUE_LEN 0x38 7885 7886 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7887 7888 /* reg_ralue_protocol 7889 * Protocol. 7890 * Access: Index 7891 */ 7892 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7893 7894 enum mlxsw_reg_ralue_op { 7895 /* Read operation. If entry doesn't exist, the operation fails. */ 7896 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7897 /* Clear on read operation. Used to read entry and 7898 * clear Activity bit. 7899 */ 7900 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7901 /* Write operation. Used to write a new entry to the table. All RW 7902 * fields are written for new entry. Activity bit is set 7903 * for new entries. 7904 */ 7905 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7906 /* Update operation. Used to update an existing route entry and 7907 * only update the RW fields that are detailed in the field 7908 * op_u_mask. If entry doesn't exist, the operation fails. 7909 */ 7910 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7911 /* Clear activity. The Activity bit (the field a) is cleared 7912 * for the entry. 7913 */ 7914 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7915 /* Delete operation. Used to delete an existing entry. If entry 7916 * doesn't exist, the operation fails. 7917 */ 7918 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7919 }; 7920 7921 /* reg_ralue_op 7922 * Operation. 7923 * Access: OP 7924 */ 7925 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7926 7927 /* reg_ralue_a 7928 * Activity. Set for new entries. Set if a packet lookup has hit on the 7929 * specific entry, only if the entry is a route. To clear the a bit, use 7930 * "clear activity" op. 7931 * Enabled by activity_dis in RGCR 7932 * Access: RO 7933 */ 7934 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7935 7936 /* reg_ralue_virtual_router 7937 * Virtual Router ID 7938 * Range is 0..cap_max_virtual_routers-1 7939 * Access: Index 7940 */ 7941 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7942 7943 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7944 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7945 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7946 7947 /* reg_ralue_op_u_mask 7948 * opcode update mask. 7949 * On read operation, this field is reserved. 7950 * This field is valid for update opcode, otherwise - reserved. 7951 * This field is a bitmask of the fields that should be updated. 7952 * Access: WO 7953 */ 7954 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7955 7956 /* reg_ralue_prefix_len 7957 * Number of bits in the prefix of the LPM route. 7958 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7959 * two entries in the physical HW table. 7960 * Access: Index 7961 */ 7962 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7963 7964 /* reg_ralue_dip* 7965 * The prefix of the route or of the marker that the object of the LPM 7966 * is compared with. The most significant bits of the dip are the prefix. 7967 * The least significant bits must be '0' if the prefix_len is smaller 7968 * than 128 for IPv6 or smaller than 32 for IPv4. 7969 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7970 * Access: Index 7971 */ 7972 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7973 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7974 7975 enum mlxsw_reg_ralue_entry_type { 7976 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7977 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7978 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7979 }; 7980 7981 /* reg_ralue_entry_type 7982 * Entry type. 7983 * Note - for Marker entries, the action_type and action fields are reserved. 7984 * Access: RW 7985 */ 7986 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7987 7988 /* reg_ralue_bmp_len 7989 * The best match prefix length in the case that there is no match for 7990 * longer prefixes. 7991 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7992 * Note for any update operation with entry_type modification this 7993 * field must be set. 7994 * Access: RW 7995 */ 7996 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7997 7998 enum mlxsw_reg_ralue_action_type { 7999 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 8000 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 8001 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 8002 }; 8003 8004 /* reg_ralue_action_type 8005 * Action Type 8006 * Indicates how the IP address is connected. 8007 * It can be connected to a local subnet through local_erif or can be 8008 * on a remote subnet connected through a next-hop router, 8009 * or transmitted to the CPU. 8010 * Reserved when entry_type = MARKER_ENTRY 8011 * Access: RW 8012 */ 8013 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 8014 8015 enum mlxsw_reg_ralue_trap_action { 8016 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 8017 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 8018 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 8019 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 8020 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 8021 }; 8022 8023 /* reg_ralue_trap_action 8024 * Trap action. 8025 * For IP2ME action, only NOP and MIRROR are possible. 8026 * Access: RW 8027 */ 8028 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 8029 8030 /* reg_ralue_trap_id 8031 * Trap ID to be reported to CPU. 8032 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 8033 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 8034 * Access: RW 8035 */ 8036 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 8037 8038 /* reg_ralue_adjacency_index 8039 * Points to the first entry of the group-based ECMP. 8040 * Only relevant in case of REMOTE action. 8041 * Access: RW 8042 */ 8043 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 8044 8045 /* reg_ralue_ecmp_size 8046 * Amount of sequential entries starting 8047 * from the adjacency_index (the number of ECMPs). 8048 * The valid range is 1-64, 512, 1024, 2048 and 4096. 8049 * Reserved when trap_action is TRAP or DISCARD_ERROR. 8050 * Only relevant in case of REMOTE action. 8051 * Access: RW 8052 */ 8053 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 8054 8055 /* reg_ralue_local_erif 8056 * Egress Router Interface. 8057 * Only relevant in case of LOCAL action. 8058 * Access: RW 8059 */ 8060 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 8061 8062 /* reg_ralue_ip2me_v 8063 * Valid bit for the tunnel_ptr field. 8064 * If valid = 0 then trap to CPU as IP2ME trap ID. 8065 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 8066 * decapsulation then tunnel decapsulation is done. 8067 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 8068 * decapsulation then trap as IP2ME trap ID. 8069 * Only relevant in case of IP2ME action. 8070 * Access: RW 8071 */ 8072 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 8073 8074 /* reg_ralue_ip2me_tunnel_ptr 8075 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 8076 * For Spectrum, pointer to KVD Linear. 8077 * Only relevant in case of IP2ME action. 8078 * Access: RW 8079 */ 8080 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 8081 8082 static inline void mlxsw_reg_ralue_pack(char *payload, 8083 enum mlxsw_reg_ralxx_protocol protocol, 8084 enum mlxsw_reg_ralue_op op, 8085 u16 virtual_router, u8 prefix_len) 8086 { 8087 MLXSW_REG_ZERO(ralue, payload); 8088 mlxsw_reg_ralue_protocol_set(payload, protocol); 8089 mlxsw_reg_ralue_op_set(payload, op); 8090 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 8091 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 8092 mlxsw_reg_ralue_entry_type_set(payload, 8093 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 8094 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 8095 } 8096 8097 static inline void mlxsw_reg_ralue_pack4(char *payload, 8098 enum mlxsw_reg_ralxx_protocol protocol, 8099 enum mlxsw_reg_ralue_op op, 8100 u16 virtual_router, u8 prefix_len, 8101 u32 dip) 8102 { 8103 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8104 mlxsw_reg_ralue_dip4_set(payload, dip); 8105 } 8106 8107 static inline void mlxsw_reg_ralue_pack6(char *payload, 8108 enum mlxsw_reg_ralxx_protocol protocol, 8109 enum mlxsw_reg_ralue_op op, 8110 u16 virtual_router, u8 prefix_len, 8111 const void *dip) 8112 { 8113 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8114 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 8115 } 8116 8117 static inline void 8118 mlxsw_reg_ralue_act_remote_pack(char *payload, 8119 enum mlxsw_reg_ralue_trap_action trap_action, 8120 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 8121 { 8122 mlxsw_reg_ralue_action_type_set(payload, 8123 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 8124 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8125 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8126 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 8127 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 8128 } 8129 8130 static inline void 8131 mlxsw_reg_ralue_act_local_pack(char *payload, 8132 enum mlxsw_reg_ralue_trap_action trap_action, 8133 u16 trap_id, u16 local_erif) 8134 { 8135 mlxsw_reg_ralue_action_type_set(payload, 8136 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8137 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8138 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8139 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8140 } 8141 8142 static inline void 8143 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8144 { 8145 mlxsw_reg_ralue_action_type_set(payload, 8146 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8147 } 8148 8149 static inline void 8150 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8151 { 8152 mlxsw_reg_ralue_action_type_set(payload, 8153 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8154 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8155 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8156 } 8157 8158 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8159 * ---------------------------------------------------------- 8160 * The RAUHT register is used to configure and query the Unicast Host table in 8161 * devices that implement the Algorithmic LPM. 8162 */ 8163 #define MLXSW_REG_RAUHT_ID 0x8014 8164 #define MLXSW_REG_RAUHT_LEN 0x74 8165 8166 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8167 8168 enum mlxsw_reg_rauht_type { 8169 MLXSW_REG_RAUHT_TYPE_IPV4, 8170 MLXSW_REG_RAUHT_TYPE_IPV6, 8171 }; 8172 8173 /* reg_rauht_type 8174 * Access: Index 8175 */ 8176 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8177 8178 enum mlxsw_reg_rauht_op { 8179 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8180 /* Read operation */ 8181 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8182 /* Clear on read operation. Used to read entry and clear 8183 * activity bit. 8184 */ 8185 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8186 /* Add. Used to write a new entry to the table. All R/W fields are 8187 * relevant for new entry. Activity bit is set for new entries. 8188 */ 8189 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8190 /* Update action. Used to update an existing route entry and 8191 * only update the following fields: 8192 * trap_action, trap_id, mac, counter_set_type, counter_index 8193 */ 8194 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8195 /* Clear activity. A bit is cleared for the entry. */ 8196 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8197 /* Delete entry */ 8198 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8199 /* Delete all host entries on a RIF. In this command, dip 8200 * field is reserved. 8201 */ 8202 }; 8203 8204 /* reg_rauht_op 8205 * Access: OP 8206 */ 8207 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8208 8209 /* reg_rauht_a 8210 * Activity. Set for new entries. Set if a packet lookup has hit on 8211 * the specific entry. 8212 * To clear the a bit, use "clear activity" op. 8213 * Enabled by activity_dis in RGCR 8214 * Access: RO 8215 */ 8216 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8217 8218 /* reg_rauht_rif 8219 * Router Interface 8220 * Access: Index 8221 */ 8222 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8223 8224 /* reg_rauht_dip* 8225 * Destination address. 8226 * Access: Index 8227 */ 8228 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8229 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8230 8231 enum mlxsw_reg_rauht_trap_action { 8232 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8233 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8234 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8235 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8236 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8237 }; 8238 8239 /* reg_rauht_trap_action 8240 * Access: RW 8241 */ 8242 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8243 8244 enum mlxsw_reg_rauht_trap_id { 8245 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8246 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8247 }; 8248 8249 /* reg_rauht_trap_id 8250 * Trap ID to be reported to CPU. 8251 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8252 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8253 * trap_id is reserved. 8254 * Access: RW 8255 */ 8256 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8257 8258 /* reg_rauht_counter_set_type 8259 * Counter set type for flow counters 8260 * Access: RW 8261 */ 8262 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8263 8264 /* reg_rauht_counter_index 8265 * Counter index for flow counters 8266 * Access: RW 8267 */ 8268 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8269 8270 /* reg_rauht_mac 8271 * MAC address. 8272 * Access: RW 8273 */ 8274 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8275 8276 static inline void mlxsw_reg_rauht_pack(char *payload, 8277 enum mlxsw_reg_rauht_op op, u16 rif, 8278 const char *mac) 8279 { 8280 MLXSW_REG_ZERO(rauht, payload); 8281 mlxsw_reg_rauht_op_set(payload, op); 8282 mlxsw_reg_rauht_rif_set(payload, rif); 8283 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8284 } 8285 8286 static inline void mlxsw_reg_rauht_pack4(char *payload, 8287 enum mlxsw_reg_rauht_op op, u16 rif, 8288 const char *mac, u32 dip) 8289 { 8290 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8291 mlxsw_reg_rauht_dip4_set(payload, dip); 8292 } 8293 8294 static inline void mlxsw_reg_rauht_pack6(char *payload, 8295 enum mlxsw_reg_rauht_op op, u16 rif, 8296 const char *mac, const char *dip) 8297 { 8298 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8299 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8300 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8301 } 8302 8303 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8304 u64 counter_index) 8305 { 8306 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8307 mlxsw_reg_rauht_counter_set_type_set(payload, 8308 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8309 } 8310 8311 /* RALEU - Router Algorithmic LPM ECMP Update Register 8312 * --------------------------------------------------- 8313 * The register enables updating the ECMP section in the action for multiple 8314 * LPM Unicast entries in a single operation. The update is executed to 8315 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8316 */ 8317 #define MLXSW_REG_RALEU_ID 0x8015 8318 #define MLXSW_REG_RALEU_LEN 0x28 8319 8320 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8321 8322 /* reg_raleu_protocol 8323 * Protocol. 8324 * Access: Index 8325 */ 8326 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8327 8328 /* reg_raleu_virtual_router 8329 * Virtual Router ID 8330 * Range is 0..cap_max_virtual_routers-1 8331 * Access: Index 8332 */ 8333 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8334 8335 /* reg_raleu_adjacency_index 8336 * Adjacency Index used for matching on the existing entries. 8337 * Access: Index 8338 */ 8339 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8340 8341 /* reg_raleu_ecmp_size 8342 * ECMP Size used for matching on the existing entries. 8343 * Access: Index 8344 */ 8345 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8346 8347 /* reg_raleu_new_adjacency_index 8348 * New Adjacency Index. 8349 * Access: WO 8350 */ 8351 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8352 8353 /* reg_raleu_new_ecmp_size 8354 * New ECMP Size. 8355 * Access: WO 8356 */ 8357 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8358 8359 static inline void mlxsw_reg_raleu_pack(char *payload, 8360 enum mlxsw_reg_ralxx_protocol protocol, 8361 u16 virtual_router, 8362 u32 adjacency_index, u16 ecmp_size, 8363 u32 new_adjacency_index, 8364 u16 new_ecmp_size) 8365 { 8366 MLXSW_REG_ZERO(raleu, payload); 8367 mlxsw_reg_raleu_protocol_set(payload, protocol); 8368 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8369 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8370 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8371 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8372 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8373 } 8374 8375 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8376 * ---------------------------------------------------------------- 8377 * The RAUHTD register allows dumping entries from the Router Unicast Host 8378 * Table. For a given session an entry is dumped no more than one time. The 8379 * first RAUHTD access after reset is a new session. A session ends when the 8380 * num_rec response is smaller than num_rec request or for IPv4 when the 8381 * num_entries is smaller than 4. The clear activity affect the current session 8382 * or the last session if a new session has not started. 8383 */ 8384 #define MLXSW_REG_RAUHTD_ID 0x8018 8385 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8386 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8387 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8388 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8389 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8390 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8391 8392 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8393 8394 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8395 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8396 8397 /* reg_rauhtd_filter_fields 8398 * if a bit is '0' then the relevant field is ignored and dump is done 8399 * regardless of the field value 8400 * Bit0 - filter by activity: entry_a 8401 * Bit3 - filter by entry rip: entry_rif 8402 * Access: Index 8403 */ 8404 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8405 8406 enum mlxsw_reg_rauhtd_op { 8407 MLXSW_REG_RAUHTD_OP_DUMP, 8408 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8409 }; 8410 8411 /* reg_rauhtd_op 8412 * Access: OP 8413 */ 8414 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8415 8416 /* reg_rauhtd_num_rec 8417 * At request: number of records requested 8418 * At response: number of records dumped 8419 * For IPv4, each record has 4 entries at request and up to 4 entries 8420 * at response 8421 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8422 * Access: Index 8423 */ 8424 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8425 8426 /* reg_rauhtd_entry_a 8427 * Dump only if activity has value of entry_a 8428 * Reserved if filter_fields bit0 is '0' 8429 * Access: Index 8430 */ 8431 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8432 8433 enum mlxsw_reg_rauhtd_type { 8434 MLXSW_REG_RAUHTD_TYPE_IPV4, 8435 MLXSW_REG_RAUHTD_TYPE_IPV6, 8436 }; 8437 8438 /* reg_rauhtd_type 8439 * Dump only if record type is: 8440 * 0 - IPv4 8441 * 1 - IPv6 8442 * Access: Index 8443 */ 8444 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8445 8446 /* reg_rauhtd_entry_rif 8447 * Dump only if RIF has value of entry_rif 8448 * Reserved if filter_fields bit3 is '0' 8449 * Access: Index 8450 */ 8451 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8452 8453 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8454 enum mlxsw_reg_rauhtd_type type) 8455 { 8456 MLXSW_REG_ZERO(rauhtd, payload); 8457 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8458 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8459 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8460 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8461 mlxsw_reg_rauhtd_type_set(payload, type); 8462 } 8463 8464 /* reg_rauhtd_ipv4_rec_num_entries 8465 * Number of valid entries in this record: 8466 * 0 - 1 valid entry 8467 * 1 - 2 valid entries 8468 * 2 - 3 valid entries 8469 * 3 - 4 valid entries 8470 * Access: RO 8471 */ 8472 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8473 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8474 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8475 8476 /* reg_rauhtd_rec_type 8477 * Record type. 8478 * 0 - IPv4 8479 * 1 - IPv6 8480 * Access: RO 8481 */ 8482 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8483 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8484 8485 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8486 8487 /* reg_rauhtd_ipv4_ent_a 8488 * Activity. Set for new entries. Set if a packet lookup has hit on the 8489 * specific entry. 8490 * Access: RO 8491 */ 8492 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8493 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8494 8495 /* reg_rauhtd_ipv4_ent_rif 8496 * Router interface. 8497 * Access: RO 8498 */ 8499 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8500 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8501 8502 /* reg_rauhtd_ipv4_ent_dip 8503 * Destination IPv4 address. 8504 * Access: RO 8505 */ 8506 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8507 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8508 8509 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8510 8511 /* reg_rauhtd_ipv6_ent_a 8512 * Activity. Set for new entries. Set if a packet lookup has hit on the 8513 * specific entry. 8514 * Access: RO 8515 */ 8516 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8517 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8518 8519 /* reg_rauhtd_ipv6_ent_rif 8520 * Router interface. 8521 * Access: RO 8522 */ 8523 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8524 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8525 8526 /* reg_rauhtd_ipv6_ent_dip 8527 * Destination IPv6 address. 8528 * Access: RO 8529 */ 8530 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8531 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8532 8533 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8534 int ent_index, u16 *p_rif, 8535 u32 *p_dip) 8536 { 8537 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8538 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8539 } 8540 8541 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8542 int rec_index, u16 *p_rif, 8543 char *p_dip) 8544 { 8545 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8546 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8547 } 8548 8549 /* RTDP - Routing Tunnel Decap Properties Register 8550 * ----------------------------------------------- 8551 * The RTDP register is used for configuring the tunnel decap properties of NVE 8552 * and IPinIP. 8553 */ 8554 #define MLXSW_REG_RTDP_ID 0x8020 8555 #define MLXSW_REG_RTDP_LEN 0x44 8556 8557 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8558 8559 enum mlxsw_reg_rtdp_type { 8560 MLXSW_REG_RTDP_TYPE_NVE, 8561 MLXSW_REG_RTDP_TYPE_IPIP, 8562 }; 8563 8564 /* reg_rtdp_type 8565 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8566 * Access: RW 8567 */ 8568 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8569 8570 /* reg_rtdp_tunnel_index 8571 * Index to the Decap entry. 8572 * For Spectrum, Index to KVD Linear. 8573 * Access: Index 8574 */ 8575 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8576 8577 /* reg_rtdp_egress_router_interface 8578 * Underlay egress router interface. 8579 * Valid range is from 0 to cap_max_router_interfaces - 1 8580 * Access: RW 8581 */ 8582 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8583 8584 /* IPinIP */ 8585 8586 /* reg_rtdp_ipip_irif 8587 * Ingress Router Interface for the overlay router 8588 * Access: RW 8589 */ 8590 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8591 8592 enum mlxsw_reg_rtdp_ipip_sip_check { 8593 /* No sip checks. */ 8594 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8595 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8596 * equal ipv4_usip. 8597 */ 8598 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8599 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8600 * equal ipv6_usip. 8601 */ 8602 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8603 }; 8604 8605 /* reg_rtdp_ipip_sip_check 8606 * SIP check to perform. If decapsulation failed due to these configurations 8607 * then trap_id is IPIP_DECAP_ERROR. 8608 * Access: RW 8609 */ 8610 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8611 8612 /* If set, allow decapsulation of IPinIP (without GRE). */ 8613 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8614 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8615 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8616 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8617 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8618 8619 /* reg_rtdp_ipip_type_check 8620 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8621 * these configurations then trap_id is IPIP_DECAP_ERROR. 8622 * Access: RW 8623 */ 8624 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8625 8626 /* reg_rtdp_ipip_gre_key_check 8627 * Whether GRE key should be checked. When check is enabled: 8628 * - A packet received as IPinIP (without GRE) will always pass. 8629 * - A packet received as IPinGREinIP without a key will not pass the check. 8630 * - A packet received as IPinGREinIP with a key will pass the check only if the 8631 * key in the packet is equal to expected_gre_key. 8632 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8633 * Access: RW 8634 */ 8635 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8636 8637 /* reg_rtdp_ipip_ipv4_usip 8638 * Underlay IPv4 address for ipv4 source address check. 8639 * Reserved when sip_check is not '1'. 8640 * Access: RW 8641 */ 8642 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8643 8644 /* reg_rtdp_ipip_ipv6_usip_ptr 8645 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8646 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8647 * is to the KVD linear. 8648 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8649 * Access: RW 8650 */ 8651 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8652 8653 /* reg_rtdp_ipip_expected_gre_key 8654 * GRE key for checking. 8655 * Reserved when gre_key_check is '0'. 8656 * Access: RW 8657 */ 8658 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8659 8660 static inline void mlxsw_reg_rtdp_pack(char *payload, 8661 enum mlxsw_reg_rtdp_type type, 8662 u32 tunnel_index) 8663 { 8664 MLXSW_REG_ZERO(rtdp, payload); 8665 mlxsw_reg_rtdp_type_set(payload, type); 8666 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8667 } 8668 8669 static inline void 8670 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8671 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8672 unsigned int type_check, bool gre_key_check, 8673 u32 expected_gre_key) 8674 { 8675 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8676 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8677 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8678 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8679 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8680 } 8681 8682 static inline void 8683 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8684 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8685 unsigned int type_check, bool gre_key_check, 8686 u32 ipv4_usip, u32 expected_gre_key) 8687 { 8688 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8689 gre_key_check, expected_gre_key); 8690 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8691 } 8692 8693 static inline void 8694 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8695 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8696 unsigned int type_check, bool gre_key_check, 8697 u32 ipv6_usip_ptr, u32 expected_gre_key) 8698 { 8699 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8700 gre_key_check, expected_gre_key); 8701 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8702 } 8703 8704 /* RIPS - Router IP version Six Register 8705 * ------------------------------------- 8706 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8707 * IPinIP 8708 */ 8709 #define MLXSW_REG_RIPS_ID 0x8021 8710 #define MLXSW_REG_RIPS_LEN 0x14 8711 8712 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8713 8714 /* reg_rips_index 8715 * Index to IPv6 address. 8716 * For Spectrum, the index is to the KVD linear. 8717 * Access: Index 8718 */ 8719 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8720 8721 /* reg_rips_ipv6 8722 * IPv6 address 8723 * Access: RW 8724 */ 8725 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8726 8727 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8728 const struct in6_addr *ipv6) 8729 { 8730 MLXSW_REG_ZERO(rips, payload); 8731 mlxsw_reg_rips_index_set(payload, index); 8732 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8733 } 8734 8735 /* RATRAD - Router Adjacency Table Activity Dump Register 8736 * ------------------------------------------------------ 8737 * The RATRAD register is used to dump and optionally clear activity bits of 8738 * router adjacency table entries. 8739 */ 8740 #define MLXSW_REG_RATRAD_ID 0x8022 8741 #define MLXSW_REG_RATRAD_LEN 0x210 8742 8743 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8744 8745 enum { 8746 /* Read activity */ 8747 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8748 /* Read and clear activity */ 8749 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8750 }; 8751 8752 /* reg_ratrad_op 8753 * Access: Operation 8754 */ 8755 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8756 8757 /* reg_ratrad_ecmp_size 8758 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8759 * ranges: 8760 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8761 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8762 * Access: Index 8763 */ 8764 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8765 8766 /* reg_ratrad_adjacency_index 8767 * Index into the adjacency table. 8768 * Access: Index 8769 */ 8770 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8771 8772 /* reg_ratrad_activity_vector 8773 * Activity bit per adjacency index. 8774 * Bits higher than ecmp_size are reserved. 8775 * Access: RO 8776 */ 8777 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8778 8779 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8780 u16 ecmp_size) 8781 { 8782 MLXSW_REG_ZERO(ratrad, payload); 8783 mlxsw_reg_ratrad_op_set(payload, 8784 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8785 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8786 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8787 } 8788 8789 /* RIGR-V2 - Router Interface Group Register Version 2 8790 * --------------------------------------------------- 8791 * The RIGR_V2 register is used to add, remove and query egress interface list 8792 * of a multicast forwarding entry. 8793 */ 8794 #define MLXSW_REG_RIGR2_ID 0x8023 8795 #define MLXSW_REG_RIGR2_LEN 0xB0 8796 8797 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8798 8799 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8800 8801 /* reg_rigr2_rigr_index 8802 * KVD Linear index. 8803 * Access: Index 8804 */ 8805 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8806 8807 /* reg_rigr2_vnext 8808 * Next RIGR Index is valid. 8809 * Access: RW 8810 */ 8811 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8812 8813 /* reg_rigr2_next_rigr_index 8814 * Next RIGR Index. The index is to the KVD linear. 8815 * Reserved when vnxet = '0'. 8816 * Access: RW 8817 */ 8818 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8819 8820 /* reg_rigr2_vrmid 8821 * RMID Index is valid. 8822 * Access: RW 8823 */ 8824 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8825 8826 /* reg_rigr2_rmid_index 8827 * RMID Index. 8828 * Range 0 .. max_mid - 1 8829 * Reserved when vrmid = '0'. 8830 * The index is to the Port Group Table (PGT) 8831 * Access: RW 8832 */ 8833 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8834 8835 /* reg_rigr2_erif_entry_v 8836 * Egress Router Interface is valid. 8837 * Note that low-entries must be set if high-entries are set. For 8838 * example: if erif_entry[2].v is set then erif_entry[1].v and 8839 * erif_entry[0].v must be set. 8840 * Index can be from 0 to cap_mc_erif_list_entries-1 8841 * Access: RW 8842 */ 8843 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8844 8845 /* reg_rigr2_erif_entry_erif 8846 * Egress Router Interface. 8847 * Valid range is from 0 to cap_max_router_interfaces - 1 8848 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8849 * Access: RW 8850 */ 8851 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8852 8853 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8854 bool vnext, u32 next_rigr_index) 8855 { 8856 MLXSW_REG_ZERO(rigr2, payload); 8857 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8858 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8859 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8860 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8861 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8862 } 8863 8864 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8865 bool v, u16 erif) 8866 { 8867 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8868 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8869 } 8870 8871 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8872 * ------------------------------------------------------ 8873 */ 8874 #define MLXSW_REG_RECR2_ID 0x8025 8875 #define MLXSW_REG_RECR2_LEN 0x38 8876 8877 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8878 8879 /* reg_recr2_pp 8880 * Per-port configuration 8881 * Access: Index 8882 */ 8883 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8884 8885 /* reg_recr2_sh 8886 * Symmetric hash 8887 * Access: RW 8888 */ 8889 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8890 8891 /* reg_recr2_seed 8892 * Seed 8893 * Access: RW 8894 */ 8895 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8896 8897 enum { 8898 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8899 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8900 /* Enable IPv4 fields if packet is TCP or UDP */ 8901 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8902 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8903 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8904 /* Enable IPv6 fields if packet is TCP or UDP */ 8905 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8906 /* Enable TCP/UDP header fields if packet is IPv4 */ 8907 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8908 /* Enable TCP/UDP header fields if packet is IPv6 */ 8909 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8910 8911 __MLXSW_REG_RECR2_HEADER_CNT, 8912 }; 8913 8914 /* reg_recr2_outer_header_enables 8915 * Bit mask where each bit enables a specific layer to be included in 8916 * the hash calculation. 8917 * Access: RW 8918 */ 8919 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8920 8921 enum { 8922 /* IPv4 Source IP */ 8923 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8924 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8925 /* IPv4 Destination IP */ 8926 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8927 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8928 /* IP Protocol */ 8929 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8930 /* IPv6 Source IP */ 8931 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8932 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8933 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8934 /* IPv6 Destination IP */ 8935 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8936 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8937 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8938 /* IPv6 Next Header */ 8939 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8940 /* IPv6 Flow Label */ 8941 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8942 /* TCP/UDP Source Port */ 8943 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8944 /* TCP/UDP Destination Port */ 8945 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8946 8947 __MLXSW_REG_RECR2_FIELD_CNT, 8948 }; 8949 8950 /* reg_recr2_outer_header_fields_enable 8951 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8952 * Access: RW 8953 */ 8954 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8955 8956 /* reg_recr2_inner_header_enables 8957 * Bit mask where each bit enables a specific inner layer to be included in the 8958 * hash calculation. Same values as reg_recr2_outer_header_enables. 8959 * Access: RW 8960 */ 8961 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8962 8963 enum { 8964 /* Inner IPv4 Source IP */ 8965 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8966 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8967 /* Inner IPv4 Destination IP */ 8968 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8969 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8970 /* Inner IP Protocol */ 8971 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8972 /* Inner IPv6 Source IP */ 8973 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8974 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8975 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8976 /* Inner IPv6 Destination IP */ 8977 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8978 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8979 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8980 /* Inner IPv6 Next Header */ 8981 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8982 /* Inner IPv6 Flow Label */ 8983 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8984 /* Inner TCP/UDP Source Port */ 8985 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8986 /* Inner TCP/UDP Destination Port */ 8987 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8988 8989 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8990 }; 8991 8992 /* reg_recr2_inner_header_fields_enable 8993 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8994 * Access: RW 8995 */ 8996 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8997 8998 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8999 { 9000 MLXSW_REG_ZERO(recr2, payload); 9001 mlxsw_reg_recr2_pp_set(payload, false); 9002 mlxsw_reg_recr2_sh_set(payload, true); 9003 mlxsw_reg_recr2_seed_set(payload, seed); 9004 } 9005 9006 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 9007 * -------------------------------------------------------------- 9008 * The RMFT_V2 register is used to configure and query the multicast table. 9009 */ 9010 #define MLXSW_REG_RMFT2_ID 0x8027 9011 #define MLXSW_REG_RMFT2_LEN 0x174 9012 9013 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 9014 9015 /* reg_rmft2_v 9016 * Valid 9017 * Access: RW 9018 */ 9019 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 9020 9021 enum mlxsw_reg_rmft2_type { 9022 MLXSW_REG_RMFT2_TYPE_IPV4, 9023 MLXSW_REG_RMFT2_TYPE_IPV6 9024 }; 9025 9026 /* reg_rmft2_type 9027 * Access: Index 9028 */ 9029 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 9030 9031 enum mlxsw_sp_reg_rmft2_op { 9032 /* For Write: 9033 * Write operation. Used to write a new entry to the table. All RW 9034 * fields are relevant for new entry. Activity bit is set for new 9035 * entries - Note write with v (Valid) 0 will delete the entry. 9036 * For Query: 9037 * Read operation 9038 */ 9039 MLXSW_REG_RMFT2_OP_READ_WRITE, 9040 }; 9041 9042 /* reg_rmft2_op 9043 * Operation. 9044 * Access: OP 9045 */ 9046 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 9047 9048 /* reg_rmft2_a 9049 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 9050 * entry. 9051 * Access: RO 9052 */ 9053 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 9054 9055 /* reg_rmft2_offset 9056 * Offset within the multicast forwarding table to write to. 9057 * Access: Index 9058 */ 9059 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 9060 9061 /* reg_rmft2_virtual_router 9062 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 9063 * Access: RW 9064 */ 9065 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 9066 9067 enum mlxsw_reg_rmft2_irif_mask { 9068 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 9069 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 9070 }; 9071 9072 /* reg_rmft2_irif_mask 9073 * Ingress RIF mask. 9074 * Access: RW 9075 */ 9076 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 9077 9078 /* reg_rmft2_irif 9079 * Ingress RIF index. 9080 * Access: RW 9081 */ 9082 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 9083 9084 /* reg_rmft2_dip{4,6} 9085 * Destination IPv4/6 address 9086 * Access: RW 9087 */ 9088 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 9089 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 9090 9091 /* reg_rmft2_dip{4,6}_mask 9092 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9093 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9094 * Access: RW 9095 */ 9096 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 9097 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 9098 9099 /* reg_rmft2_sip{4,6} 9100 * Source IPv4/6 address 9101 * Access: RW 9102 */ 9103 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 9104 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 9105 9106 /* reg_rmft2_sip{4,6}_mask 9107 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9108 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9109 * Access: RW 9110 */ 9111 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 9112 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 9113 9114 /* reg_rmft2_flexible_action_set 9115 * ACL action set. The only supported action types in this field and in any 9116 * action-set pointed from here are as follows: 9117 * 00h: ACTION_NULL 9118 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 9119 * 03h: ACTION_TRAP 9120 * 06h: ACTION_QOS 9121 * 08h: ACTION_POLICING_MONITORING 9122 * 10h: ACTION_ROUTER_MC 9123 * Access: RW 9124 */ 9125 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 9126 MLXSW_REG_FLEX_ACTION_SET_LEN); 9127 9128 static inline void 9129 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 9130 u16 virtual_router, 9131 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9132 const char *flex_action_set) 9133 { 9134 MLXSW_REG_ZERO(rmft2, payload); 9135 mlxsw_reg_rmft2_v_set(payload, v); 9136 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9137 mlxsw_reg_rmft2_offset_set(payload, offset); 9138 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9139 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9140 mlxsw_reg_rmft2_irif_set(payload, irif); 9141 if (flex_action_set) 9142 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9143 flex_action_set); 9144 } 9145 9146 static inline void 9147 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9148 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9149 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9150 const char *flexible_action_set) 9151 { 9152 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9153 irif_mask, irif, flexible_action_set); 9154 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9155 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9156 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9157 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9158 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9159 } 9160 9161 static inline void 9162 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9163 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9164 struct in6_addr dip6, struct in6_addr dip6_mask, 9165 struct in6_addr sip6, struct in6_addr sip6_mask, 9166 const char *flexible_action_set) 9167 { 9168 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9169 irif_mask, irif, flexible_action_set); 9170 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9171 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9172 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9173 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9174 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9175 } 9176 9177 /* REIV - Router Egress Interface to VID Register 9178 * ---------------------------------------------- 9179 * The REIV register maps {eRIF, egress_port} -> VID. 9180 * This mapping is done at the egress, after the ACLs. 9181 * This mapping always takes effect after router, regardless of cast 9182 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9183 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9184 * Reserved when the RIF is a loopback RIF. 9185 * 9186 * Note: Reserved when legacy bridge model is used. 9187 */ 9188 #define MLXSW_REG_REIV_ID 0x8034 9189 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9190 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9191 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9192 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9193 MLXSW_REG_REIV_REC_LEN * \ 9194 MLXSW_REG_REIV_REC_MAX_COUNT) 9195 9196 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9197 9198 /* reg_reiv_port_page 9199 * Port page - elport_record[0] is 256*port_page. 9200 * Access: Index 9201 */ 9202 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9203 9204 /* reg_reiv_erif 9205 * Egress RIF. 9206 * Range is 0..cap_max_router_interfaces-1. 9207 * Access: Index 9208 */ 9209 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9210 9211 /* reg_reiv_rec_update 9212 * Update enable (when write): 9213 * 0 - Do not update the entry. 9214 * 1 - Update the entry. 9215 * Access: OP 9216 */ 9217 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9218 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9219 9220 /* reg_reiv_rec_evid 9221 * Egress VID. 9222 * Range is 0..4095. 9223 * Access: RW 9224 */ 9225 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9226 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9227 9228 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9229 { 9230 MLXSW_REG_ZERO(reiv, payload); 9231 mlxsw_reg_reiv_port_page_set(payload, port_page); 9232 mlxsw_reg_reiv_erif_set(payload, erif); 9233 } 9234 9235 /* MFCR - Management Fan Control Register 9236 * -------------------------------------- 9237 * This register controls the settings of the Fan Speed PWM mechanism. 9238 */ 9239 #define MLXSW_REG_MFCR_ID 0x9001 9240 #define MLXSW_REG_MFCR_LEN 0x08 9241 9242 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9243 9244 enum mlxsw_reg_mfcr_pwm_frequency { 9245 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9246 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9247 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9248 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9249 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9250 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9251 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9252 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9253 }; 9254 9255 /* reg_mfcr_pwm_frequency 9256 * Controls the frequency of the PWM signal. 9257 * Access: RW 9258 */ 9259 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9260 9261 #define MLXSW_MFCR_TACHOS_MAX 10 9262 9263 /* reg_mfcr_tacho_active 9264 * Indicates which of the tachometer is active (bit per tachometer). 9265 * Access: RO 9266 */ 9267 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9268 9269 #define MLXSW_MFCR_PWMS_MAX 5 9270 9271 /* reg_mfcr_pwm_active 9272 * Indicates which of the PWM control is active (bit per PWM). 9273 * Access: RO 9274 */ 9275 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9276 9277 static inline void 9278 mlxsw_reg_mfcr_pack(char *payload, 9279 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9280 { 9281 MLXSW_REG_ZERO(mfcr, payload); 9282 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9283 } 9284 9285 static inline void 9286 mlxsw_reg_mfcr_unpack(char *payload, 9287 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9288 u16 *p_tacho_active, u8 *p_pwm_active) 9289 { 9290 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9291 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9292 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9293 } 9294 9295 /* MFSC - Management Fan Speed Control Register 9296 * -------------------------------------------- 9297 * This register controls the settings of the Fan Speed PWM mechanism. 9298 */ 9299 #define MLXSW_REG_MFSC_ID 0x9002 9300 #define MLXSW_REG_MFSC_LEN 0x08 9301 9302 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9303 9304 /* reg_mfsc_pwm 9305 * Fan pwm to control / monitor. 9306 * Access: Index 9307 */ 9308 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9309 9310 /* reg_mfsc_pwm_duty_cycle 9311 * Controls the duty cycle of the PWM. Value range from 0..255 to 9312 * represent duty cycle of 0%...100%. 9313 * Access: RW 9314 */ 9315 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9316 9317 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9318 u8 pwm_duty_cycle) 9319 { 9320 MLXSW_REG_ZERO(mfsc, payload); 9321 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9322 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9323 } 9324 9325 /* MFSM - Management Fan Speed Measurement 9326 * --------------------------------------- 9327 * This register controls the settings of the Tacho measurements and 9328 * enables reading the Tachometer measurements. 9329 */ 9330 #define MLXSW_REG_MFSM_ID 0x9003 9331 #define MLXSW_REG_MFSM_LEN 0x08 9332 9333 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9334 9335 /* reg_mfsm_tacho 9336 * Fan tachometer index. 9337 * Access: Index 9338 */ 9339 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9340 9341 /* reg_mfsm_rpm 9342 * Fan speed (round per minute). 9343 * Access: RO 9344 */ 9345 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9346 9347 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9348 { 9349 MLXSW_REG_ZERO(mfsm, payload); 9350 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9351 } 9352 9353 /* MFSL - Management Fan Speed Limit Register 9354 * ------------------------------------------ 9355 * The Fan Speed Limit register is used to configure the fan speed 9356 * event / interrupt notification mechanism. Fan speed threshold are 9357 * defined for both under-speed and over-speed. 9358 */ 9359 #define MLXSW_REG_MFSL_ID 0x9004 9360 #define MLXSW_REG_MFSL_LEN 0x0C 9361 9362 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9363 9364 /* reg_mfsl_tacho 9365 * Fan tachometer index. 9366 * Access: Index 9367 */ 9368 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9369 9370 /* reg_mfsl_tach_min 9371 * Tachometer minimum value (minimum RPM). 9372 * Access: RW 9373 */ 9374 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9375 9376 /* reg_mfsl_tach_max 9377 * Tachometer maximum value (maximum RPM). 9378 * Access: RW 9379 */ 9380 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9381 9382 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9383 u16 tach_min, u16 tach_max) 9384 { 9385 MLXSW_REG_ZERO(mfsl, payload); 9386 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9387 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9388 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9389 } 9390 9391 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9392 u16 *p_tach_min, u16 *p_tach_max) 9393 { 9394 if (p_tach_min) 9395 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9396 9397 if (p_tach_max) 9398 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9399 } 9400 9401 /* FORE - Fan Out of Range Event Register 9402 * -------------------------------------- 9403 * This register reports the status of the controlled fans compared to the 9404 * range defined by the MFSL register. 9405 */ 9406 #define MLXSW_REG_FORE_ID 0x9007 9407 #define MLXSW_REG_FORE_LEN 0x0C 9408 9409 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9410 9411 /* fan_under_limit 9412 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9413 * to a single tachometer and indicates the specific tachometer reading is 9414 * below the threshold. 9415 * Access: RO 9416 */ 9417 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9418 9419 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9420 bool *fault) 9421 { 9422 u16 limit; 9423 9424 if (fault) { 9425 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9426 *fault = limit & BIT(tacho); 9427 } 9428 } 9429 9430 /* MTCAP - Management Temperature Capabilities 9431 * ------------------------------------------- 9432 * This register exposes the capabilities of the device and 9433 * system temperature sensing. 9434 */ 9435 #define MLXSW_REG_MTCAP_ID 0x9009 9436 #define MLXSW_REG_MTCAP_LEN 0x08 9437 9438 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9439 9440 /* reg_mtcap_sensor_count 9441 * Number of sensors supported by the device. 9442 * This includes the QSFP module sensors (if exists in the QSFP module). 9443 * Access: RO 9444 */ 9445 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9446 9447 /* MTMP - Management Temperature 9448 * ----------------------------- 9449 * This register controls the settings of the temperature measurements 9450 * and enables reading the temperature measurements. Note that temperature 9451 * is in 0.125 degrees Celsius. 9452 */ 9453 #define MLXSW_REG_MTMP_ID 0x900A 9454 #define MLXSW_REG_MTMP_LEN 0x20 9455 9456 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9457 9458 /* reg_mtmp_slot_index 9459 * Slot index (0: Main board). 9460 * Access: Index 9461 */ 9462 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9463 9464 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9465 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9466 /* reg_mtmp_sensor_index 9467 * Sensors index to access. 9468 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9469 * (module 0 is mapped to sensor_index 64). 9470 * Access: Index 9471 */ 9472 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9473 9474 /* Convert to milli degrees Celsius */ 9475 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9476 ((v_) >= 0) ? ((v_) * 125) : \ 9477 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9478 * 125)); }) 9479 9480 /* reg_mtmp_max_operational_temperature 9481 * The highest temperature in the nominal operational range. Reading is in 9482 * 0.125 Celsius degrees units. 9483 * In case of module this is SFF critical temperature threshold. 9484 * Access: RO 9485 */ 9486 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9487 9488 /* reg_mtmp_temperature 9489 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9490 * degrees units. 9491 * Access: RO 9492 */ 9493 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9494 9495 /* reg_mtmp_mte 9496 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9497 * Access: RW 9498 */ 9499 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9500 9501 /* reg_mtmp_mtr 9502 * Max Temperature Reset - clears the value of the max temperature register. 9503 * Access: WO 9504 */ 9505 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9506 9507 /* reg_mtmp_max_temperature 9508 * The highest measured temperature from the sensor. 9509 * When the bit mte is cleared, the field max_temperature is reserved. 9510 * Access: RO 9511 */ 9512 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9513 9514 /* reg_mtmp_tee 9515 * Temperature Event Enable. 9516 * 0 - Do not generate event 9517 * 1 - Generate event 9518 * 2 - Generate single event 9519 * Access: RW 9520 */ 9521 9522 enum mlxsw_reg_mtmp_tee { 9523 MLXSW_REG_MTMP_TEE_NO_EVENT, 9524 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9525 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9526 }; 9527 9528 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9529 9530 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9531 9532 /* reg_mtmp_temperature_threshold_hi 9533 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9534 * Access: RW 9535 */ 9536 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9537 9538 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9539 /* reg_mtmp_temperature_threshold_lo 9540 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9541 * Access: RW 9542 */ 9543 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9544 9545 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9546 9547 /* reg_mtmp_sensor_name 9548 * Sensor Name 9549 * Access: RO 9550 */ 9551 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9552 9553 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9554 u16 sensor_index, bool max_temp_enable, 9555 bool max_temp_reset) 9556 { 9557 MLXSW_REG_ZERO(mtmp, payload); 9558 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9559 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9560 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9561 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9562 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9563 MLXSW_REG_MTMP_THRESH_HI); 9564 } 9565 9566 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9567 int *p_max_temp, int *p_temp_hi, 9568 int *p_max_oper_temp, 9569 char *sensor_name) 9570 { 9571 s16 temp; 9572 9573 if (p_temp) { 9574 temp = mlxsw_reg_mtmp_temperature_get(payload); 9575 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9576 } 9577 if (p_max_temp) { 9578 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9579 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9580 } 9581 if (p_temp_hi) { 9582 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9583 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9584 } 9585 if (p_max_oper_temp) { 9586 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9587 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9588 } 9589 if (sensor_name) 9590 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9591 } 9592 9593 /* MTWE - Management Temperature Warning Event 9594 * ------------------------------------------- 9595 * This register is used for over temperature warning. 9596 */ 9597 #define MLXSW_REG_MTWE_ID 0x900B 9598 #define MLXSW_REG_MTWE_LEN 0x10 9599 9600 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9601 9602 /* reg_mtwe_sensor_warning 9603 * Bit vector indicating which of the sensor reading is above threshold. 9604 * Address 00h bit31 is sensor_warning[127]. 9605 * Address 0Ch bit0 is sensor_warning[0]. 9606 * Access: RO 9607 */ 9608 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9609 9610 /* MTBR - Management Temperature Bulk Register 9611 * ------------------------------------------- 9612 * This register is used for bulk temperature reading. 9613 */ 9614 #define MLXSW_REG_MTBR_ID 0x900F 9615 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9616 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9617 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9618 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9619 MLXSW_REG_MTBR_REC_LEN * \ 9620 MLXSW_REG_MTBR_REC_MAX_COUNT) 9621 9622 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9623 9624 /* reg_mtbr_slot_index 9625 * Slot index (0: Main board). 9626 * Access: Index 9627 */ 9628 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9629 9630 /* reg_mtbr_base_sensor_index 9631 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9632 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9633 * Access: Index 9634 */ 9635 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9636 9637 /* reg_mtbr_num_rec 9638 * Request: Number of records to read 9639 * Response: Number of records read 9640 * See above description for more details. 9641 * Range 1..255 9642 * Access: RW 9643 */ 9644 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9645 9646 /* reg_mtbr_rec_max_temp 9647 * The highest measured temperature from the sensor. 9648 * When the bit mte is cleared, the field max_temperature is reserved. 9649 * Access: RO 9650 */ 9651 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9652 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9653 9654 /* reg_mtbr_rec_temp 9655 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9656 * degrees units. 9657 * Access: RO 9658 */ 9659 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9660 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9661 9662 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9663 u16 base_sensor_index, u8 num_rec) 9664 { 9665 MLXSW_REG_ZERO(mtbr, payload); 9666 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9667 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9668 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9669 } 9670 9671 /* Error codes from temperatute reading */ 9672 enum mlxsw_reg_mtbr_temp_status { 9673 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9674 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9675 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9676 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9677 }; 9678 9679 /* Base index for reading modules temperature */ 9680 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9681 9682 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9683 u16 *p_temp, u16 *p_max_temp) 9684 { 9685 if (p_temp) 9686 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9687 if (p_max_temp) 9688 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9689 } 9690 9691 /* MCIA - Management Cable Info Access 9692 * ----------------------------------- 9693 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9694 */ 9695 9696 #define MLXSW_REG_MCIA_ID 0x9014 9697 #define MLXSW_REG_MCIA_LEN 0x40 9698 9699 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9700 9701 /* reg_mcia_l 9702 * Lock bit. Setting this bit will lock the access to the specific 9703 * cable. Used for updating a full page in a cable EPROM. Any access 9704 * other then subsequence writes will fail while the port is locked. 9705 * Access: RW 9706 */ 9707 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9708 9709 /* reg_mcia_module 9710 * Module number. 9711 * Access: Index 9712 */ 9713 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9714 9715 /* reg_mcia_slot_index 9716 * Slot index (0: Main board) 9717 * Access: Index 9718 */ 9719 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9720 9721 enum { 9722 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9723 /* No response from module's EEPROM. */ 9724 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9725 /* Module type not supported by the device. */ 9726 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9727 /* No module present indication. */ 9728 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9729 /* Error occurred while trying to access module's EEPROM using I2C. */ 9730 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9731 /* Module is disabled. */ 9732 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9733 }; 9734 9735 /* reg_mcia_status 9736 * Module status. 9737 * Access: RO 9738 */ 9739 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9740 9741 /* reg_mcia_i2c_device_address 9742 * I2C device address. 9743 * Access: RW 9744 */ 9745 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9746 9747 /* reg_mcia_page_number 9748 * Page number. 9749 * Access: RW 9750 */ 9751 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9752 9753 /* reg_mcia_device_address 9754 * Device address. 9755 * Access: RW 9756 */ 9757 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9758 9759 /* reg_mcia_bank_number 9760 * Bank number. 9761 * Access: Index 9762 */ 9763 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9764 9765 /* reg_mcia_size 9766 * Number of bytes to read/write (up to 48 bytes). 9767 * Access: RW 9768 */ 9769 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9770 9771 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9772 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9773 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9774 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9775 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9776 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9777 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9778 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9779 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9780 #define MLXSW_REG_MCIA_PAGE0_LO 0 9781 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9782 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9783 9784 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9785 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9786 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9787 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9788 }; 9789 9790 enum mlxsw_reg_mcia_eeprom_module_info_id { 9791 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9792 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9793 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9794 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9795 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9796 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9797 }; 9798 9799 enum mlxsw_reg_mcia_eeprom_module_info { 9800 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9801 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9802 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9803 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9804 }; 9805 9806 /* reg_mcia_eeprom 9807 * Bytes to read/write. 9808 * Access: RW 9809 */ 9810 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9811 9812 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9813 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9814 * on offset 384 through 511, page 3 - on offset 512 through 639. 9815 */ 9816 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9817 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9818 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9819 9820 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9821 u8 lock, u8 page_number, 9822 u16 device_addr, u8 size, 9823 u8 i2c_device_addr) 9824 { 9825 MLXSW_REG_ZERO(mcia, payload); 9826 mlxsw_reg_mcia_slot_set(payload, slot_index); 9827 mlxsw_reg_mcia_module_set(payload, module); 9828 mlxsw_reg_mcia_l_set(payload, lock); 9829 mlxsw_reg_mcia_page_number_set(payload, page_number); 9830 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9831 mlxsw_reg_mcia_size_set(payload, size); 9832 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9833 } 9834 9835 /* MPAT - Monitoring Port Analyzer Table 9836 * ------------------------------------- 9837 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9838 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9839 */ 9840 #define MLXSW_REG_MPAT_ID 0x901A 9841 #define MLXSW_REG_MPAT_LEN 0x78 9842 9843 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9844 9845 /* reg_mpat_pa_id 9846 * Port Analyzer ID. 9847 * Access: Index 9848 */ 9849 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9850 9851 /* reg_mpat_session_id 9852 * Mirror Session ID. 9853 * Used for MIRROR_SESSION<i> trap. 9854 * Access: RW 9855 */ 9856 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9857 9858 /* reg_mpat_system_port 9859 * A unique port identifier for the final destination of the packet. 9860 * Access: RW 9861 */ 9862 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9863 9864 /* reg_mpat_e 9865 * Enable. Indicating the Port Analyzer is enabled. 9866 * Access: RW 9867 */ 9868 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9869 9870 /* reg_mpat_qos 9871 * Quality Of Service Mode. 9872 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9873 * PCP, DEI, DSCP or VL) are configured. 9874 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9875 * same as in the original packet that has triggered the mirroring. For 9876 * SPAN also the pcp,dei are maintained. 9877 * Access: RW 9878 */ 9879 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9880 9881 /* reg_mpat_be 9882 * Best effort mode. Indicates mirroring traffic should not cause packet 9883 * drop or back pressure, but will discard the mirrored packets. Mirrored 9884 * packets will be forwarded on a best effort manner. 9885 * 0: Do not discard mirrored packets 9886 * 1: Discard mirrored packets if causing congestion 9887 * Access: RW 9888 */ 9889 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9890 9891 enum mlxsw_reg_mpat_span_type { 9892 /* Local SPAN Ethernet. 9893 * The original packet is not encapsulated. 9894 */ 9895 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9896 9897 /* Remote SPAN Ethernet VLAN. 9898 * The packet is forwarded to the monitoring port on the monitoring 9899 * VLAN. 9900 */ 9901 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9902 9903 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9904 * The packet is encapsulated with GRE header. 9905 */ 9906 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9907 }; 9908 9909 /* reg_mpat_span_type 9910 * SPAN type. 9911 * Access: RW 9912 */ 9913 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9914 9915 /* reg_mpat_pide 9916 * Policer enable. 9917 * Access: RW 9918 */ 9919 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9920 9921 /* reg_mpat_pid 9922 * Policer ID. 9923 * Access: RW 9924 */ 9925 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9926 9927 /* Remote SPAN - Ethernet VLAN 9928 * - - - - - - - - - - - - - - 9929 */ 9930 9931 /* reg_mpat_eth_rspan_vid 9932 * Encapsulation header VLAN ID. 9933 * Access: RW 9934 */ 9935 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9936 9937 /* Encapsulated Remote SPAN - Ethernet L2 9938 * - - - - - - - - - - - - - - - - - - - 9939 */ 9940 9941 enum mlxsw_reg_mpat_eth_rspan_version { 9942 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9943 }; 9944 9945 /* reg_mpat_eth_rspan_version 9946 * RSPAN mirror header version. 9947 * Access: RW 9948 */ 9949 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9950 9951 /* reg_mpat_eth_rspan_mac 9952 * Destination MAC address. 9953 * Access: RW 9954 */ 9955 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9956 9957 /* reg_mpat_eth_rspan_tp 9958 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9959 * Access: RW 9960 */ 9961 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9962 9963 /* Encapsulated Remote SPAN - Ethernet L3 9964 * - - - - - - - - - - - - - - - - - - - 9965 */ 9966 9967 enum mlxsw_reg_mpat_eth_rspan_protocol { 9968 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9969 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9970 }; 9971 9972 /* reg_mpat_eth_rspan_protocol 9973 * SPAN encapsulation protocol. 9974 * Access: RW 9975 */ 9976 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9977 9978 /* reg_mpat_eth_rspan_ttl 9979 * Encapsulation header Time-to-Live/HopLimit. 9980 * Access: RW 9981 */ 9982 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9983 9984 /* reg_mpat_eth_rspan_smac 9985 * Source MAC address 9986 * Access: RW 9987 */ 9988 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9989 9990 /* reg_mpat_eth_rspan_dip* 9991 * Destination IP address. The IP version is configured by protocol. 9992 * Access: RW 9993 */ 9994 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9995 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9996 9997 /* reg_mpat_eth_rspan_sip* 9998 * Source IP address. The IP version is configured by protocol. 9999 * Access: RW 10000 */ 10001 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 10002 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 10003 10004 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 10005 u16 system_port, bool e, 10006 enum mlxsw_reg_mpat_span_type span_type) 10007 { 10008 MLXSW_REG_ZERO(mpat, payload); 10009 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 10010 mlxsw_reg_mpat_system_port_set(payload, system_port); 10011 mlxsw_reg_mpat_e_set(payload, e); 10012 mlxsw_reg_mpat_qos_set(payload, 1); 10013 mlxsw_reg_mpat_be_set(payload, 1); 10014 mlxsw_reg_mpat_span_type_set(payload, span_type); 10015 } 10016 10017 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 10018 { 10019 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 10020 } 10021 10022 static inline void 10023 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 10024 enum mlxsw_reg_mpat_eth_rspan_version version, 10025 const char *mac, 10026 bool tp) 10027 { 10028 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 10029 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 10030 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 10031 } 10032 10033 static inline void 10034 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 10035 const char *smac, 10036 u32 sip, u32 dip) 10037 { 10038 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10039 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10040 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10041 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 10042 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 10043 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 10044 } 10045 10046 static inline void 10047 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 10048 const char *smac, 10049 struct in6_addr sip, struct in6_addr dip) 10050 { 10051 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10052 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10053 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10054 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 10055 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 10056 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 10057 } 10058 10059 /* MPAR - Monitoring Port Analyzer Register 10060 * ---------------------------------------- 10061 * MPAR register is used to query and configure the port analyzer port mirroring 10062 * properties. 10063 */ 10064 #define MLXSW_REG_MPAR_ID 0x901B 10065 #define MLXSW_REG_MPAR_LEN 0x0C 10066 10067 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 10068 10069 /* reg_mpar_local_port 10070 * The local port to mirror the packets from. 10071 * Access: Index 10072 */ 10073 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 10074 10075 enum mlxsw_reg_mpar_i_e { 10076 MLXSW_REG_MPAR_TYPE_EGRESS, 10077 MLXSW_REG_MPAR_TYPE_INGRESS, 10078 }; 10079 10080 /* reg_mpar_i_e 10081 * Ingress/Egress 10082 * Access: Index 10083 */ 10084 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10085 10086 /* reg_mpar_enable 10087 * Enable mirroring 10088 * By default, port mirroring is disabled for all ports. 10089 * Access: RW 10090 */ 10091 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10092 10093 /* reg_mpar_pa_id 10094 * Port Analyzer ID. 10095 * Access: RW 10096 */ 10097 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10098 10099 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10100 10101 /* reg_mpar_probability_rate 10102 * Sampling rate. 10103 * Valid values are: 1 to 3.5*10^9 10104 * Value of 1 means "sample all". Default is 1. 10105 * Reserved when Spectrum-1. 10106 * Access: RW 10107 */ 10108 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10109 10110 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 10111 enum mlxsw_reg_mpar_i_e i_e, 10112 bool enable, u8 pa_id, 10113 u32 probability_rate) 10114 { 10115 MLXSW_REG_ZERO(mpar, payload); 10116 mlxsw_reg_mpar_local_port_set(payload, local_port); 10117 mlxsw_reg_mpar_enable_set(payload, enable); 10118 mlxsw_reg_mpar_i_e_set(payload, i_e); 10119 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10120 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10121 } 10122 10123 /* MGIR - Management General Information Register 10124 * ---------------------------------------------- 10125 * MGIR register allows software to query the hardware and firmware general 10126 * information. 10127 */ 10128 #define MLXSW_REG_MGIR_ID 0x9020 10129 #define MLXSW_REG_MGIR_LEN 0x9C 10130 10131 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10132 10133 /* reg_mgir_hw_info_device_hw_revision 10134 * Access: RO 10135 */ 10136 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10137 10138 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10139 10140 /* reg_mgir_fw_info_psid 10141 * PSID (ASCII string). 10142 * Access: RO 10143 */ 10144 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10145 10146 /* reg_mgir_fw_info_extended_major 10147 * Access: RO 10148 */ 10149 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10150 10151 /* reg_mgir_fw_info_extended_minor 10152 * Access: RO 10153 */ 10154 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10155 10156 /* reg_mgir_fw_info_extended_sub_minor 10157 * Access: RO 10158 */ 10159 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10160 10161 static inline void mlxsw_reg_mgir_pack(char *payload) 10162 { 10163 MLXSW_REG_ZERO(mgir, payload); 10164 } 10165 10166 static inline void 10167 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10168 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10169 { 10170 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10171 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10172 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10173 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10174 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10175 } 10176 10177 /* MRSR - Management Reset and Shutdown Register 10178 * --------------------------------------------- 10179 * MRSR register is used to reset or shutdown the switch or 10180 * the entire system (when applicable). 10181 */ 10182 #define MLXSW_REG_MRSR_ID 0x9023 10183 #define MLXSW_REG_MRSR_LEN 0x08 10184 10185 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10186 10187 /* reg_mrsr_command 10188 * Reset/shutdown command 10189 * 0 - do nothing 10190 * 1 - software reset 10191 * Access: WO 10192 */ 10193 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10194 10195 static inline void mlxsw_reg_mrsr_pack(char *payload) 10196 { 10197 MLXSW_REG_ZERO(mrsr, payload); 10198 mlxsw_reg_mrsr_command_set(payload, 1); 10199 } 10200 10201 /* MLCR - Management LED Control Register 10202 * -------------------------------------- 10203 * Controls the system LEDs. 10204 */ 10205 #define MLXSW_REG_MLCR_ID 0x902B 10206 #define MLXSW_REG_MLCR_LEN 0x0C 10207 10208 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10209 10210 /* reg_mlcr_local_port 10211 * Local port number. 10212 * Access: RW 10213 */ 10214 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10215 10216 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10217 10218 /* reg_mlcr_beacon_duration 10219 * Duration of the beacon to be active, in seconds. 10220 * 0x0 - Will turn off the beacon. 10221 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10222 * Access: RW 10223 */ 10224 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10225 10226 /* reg_mlcr_beacon_remain 10227 * Remaining duration of the beacon, in seconds. 10228 * 0xFFFF indicates an infinite amount of time. 10229 * Access: RO 10230 */ 10231 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10232 10233 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10234 bool active) 10235 { 10236 MLXSW_REG_ZERO(mlcr, payload); 10237 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10238 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10239 MLXSW_REG_MLCR_DURATION_MAX : 0); 10240 } 10241 10242 /* MCION - Management Cable IO and Notifications Register 10243 * ------------------------------------------------------ 10244 * The MCION register is used to query transceiver modules' IO pins and other 10245 * notifications. 10246 */ 10247 #define MLXSW_REG_MCION_ID 0x9052 10248 #define MLXSW_REG_MCION_LEN 0x18 10249 10250 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10251 10252 /* reg_mcion_module 10253 * Module number. 10254 * Access: Index 10255 */ 10256 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10257 10258 /* reg_mcion_slot_index 10259 * Slot index. 10260 * Access: Index 10261 */ 10262 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10263 10264 enum { 10265 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10266 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10267 }; 10268 10269 /* reg_mcion_module_status_bits 10270 * Module IO status as defined by SFF. 10271 * Access: RO 10272 */ 10273 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10274 10275 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10276 { 10277 MLXSW_REG_ZERO(mcion, payload); 10278 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10279 mlxsw_reg_mcion_module_set(payload, module); 10280 } 10281 10282 /* MTPPS - Management Pulse Per Second Register 10283 * -------------------------------------------- 10284 * This register provides the device PPS capabilities, configure the PPS in and 10285 * out modules and holds the PPS in time stamp. 10286 */ 10287 #define MLXSW_REG_MTPPS_ID 0x9053 10288 #define MLXSW_REG_MTPPS_LEN 0x3C 10289 10290 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10291 10292 /* reg_mtpps_enable 10293 * Enables the PPS functionality the specific pin. 10294 * A boolean variable. 10295 * Access: RW 10296 */ 10297 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10298 10299 enum mlxsw_reg_mtpps_pin_mode { 10300 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10301 }; 10302 10303 /* reg_mtpps_pin_mode 10304 * Pin mode to be used. The mode must comply with the supported modes of the 10305 * requested pin. 10306 * Access: RW 10307 */ 10308 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10309 10310 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10311 10312 /* reg_mtpps_pin 10313 * Pin to be configured or queried out of the supported pins. 10314 * Access: Index 10315 */ 10316 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10317 10318 /* reg_mtpps_time_stamp 10319 * When pin_mode = pps_in, the latched device time when it was triggered from 10320 * the external GPIO pin. 10321 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10322 * time to generate next output signal. 10323 * Time is in units of device clock. 10324 * Access: RW 10325 */ 10326 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10327 10328 static inline void 10329 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10330 { 10331 MLXSW_REG_ZERO(mtpps, payload); 10332 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10333 mlxsw_reg_mtpps_pin_mode_set(payload, 10334 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10335 mlxsw_reg_mtpps_enable_set(payload, true); 10336 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10337 } 10338 10339 /* MTUTC - Management UTC Register 10340 * ------------------------------- 10341 * Configures the HW UTC counter. 10342 */ 10343 #define MLXSW_REG_MTUTC_ID 0x9055 10344 #define MLXSW_REG_MTUTC_LEN 0x1C 10345 10346 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10347 10348 enum mlxsw_reg_mtutc_operation { 10349 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10350 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10351 }; 10352 10353 /* reg_mtutc_operation 10354 * Operation. 10355 * Access: OP 10356 */ 10357 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10358 10359 /* reg_mtutc_freq_adjustment 10360 * Frequency adjustment: Every PPS the HW frequency will be 10361 * adjusted by this value. Units of HW clock, where HW counts 10362 * 10^9 HW clocks for 1 HW second. 10363 * Access: RW 10364 */ 10365 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10366 10367 /* reg_mtutc_utc_sec 10368 * UTC seconds. 10369 * Access: WO 10370 */ 10371 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10372 10373 static inline void 10374 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10375 u32 freq_adj, u32 utc_sec) 10376 { 10377 MLXSW_REG_ZERO(mtutc, payload); 10378 mlxsw_reg_mtutc_operation_set(payload, oper); 10379 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10380 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10381 } 10382 10383 /* MCQI - Management Component Query Information 10384 * --------------------------------------------- 10385 * This register allows querying information about firmware components. 10386 */ 10387 #define MLXSW_REG_MCQI_ID 0x9061 10388 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10389 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10390 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10391 10392 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10393 10394 /* reg_mcqi_component_index 10395 * Index of the accessed component. 10396 * Access: Index 10397 */ 10398 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10399 10400 enum mlxfw_reg_mcqi_info_type { 10401 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10402 }; 10403 10404 /* reg_mcqi_info_type 10405 * Component properties set. 10406 * Access: RW 10407 */ 10408 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10409 10410 /* reg_mcqi_offset 10411 * The requested/returned data offset from the section start, given in bytes. 10412 * Must be DWORD aligned. 10413 * Access: RW 10414 */ 10415 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10416 10417 /* reg_mcqi_data_size 10418 * The requested/returned data size, given in bytes. If data_size is not DWORD 10419 * aligned, the last bytes are zero padded. 10420 * Access: RW 10421 */ 10422 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10423 10424 /* reg_mcqi_cap_max_component_size 10425 * Maximum size for this component, given in bytes. 10426 * Access: RO 10427 */ 10428 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10429 10430 /* reg_mcqi_cap_log_mcda_word_size 10431 * Log 2 of the access word size in bytes. Read and write access must be aligned 10432 * to the word size. Write access must be done for an integer number of words. 10433 * Access: RO 10434 */ 10435 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10436 10437 /* reg_mcqi_cap_mcda_max_write_size 10438 * Maximal write size for MCDA register 10439 * Access: RO 10440 */ 10441 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10442 10443 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10444 { 10445 MLXSW_REG_ZERO(mcqi, payload); 10446 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10447 mlxsw_reg_mcqi_info_type_set(payload, 10448 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10449 mlxsw_reg_mcqi_offset_set(payload, 0); 10450 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10451 } 10452 10453 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10454 u32 *p_cap_max_component_size, 10455 u8 *p_cap_log_mcda_word_size, 10456 u16 *p_cap_mcda_max_write_size) 10457 { 10458 *p_cap_max_component_size = 10459 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10460 *p_cap_log_mcda_word_size = 10461 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10462 *p_cap_mcda_max_write_size = 10463 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10464 } 10465 10466 /* MCC - Management Component Control 10467 * ---------------------------------- 10468 * Controls the firmware component and updates the FSM. 10469 */ 10470 #define MLXSW_REG_MCC_ID 0x9062 10471 #define MLXSW_REG_MCC_LEN 0x1C 10472 10473 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10474 10475 enum mlxsw_reg_mcc_instruction { 10476 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10477 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10478 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10479 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10480 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10481 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10482 }; 10483 10484 /* reg_mcc_instruction 10485 * Command to be executed by the FSM. 10486 * Applicable for write operation only. 10487 * Access: RW 10488 */ 10489 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10490 10491 /* reg_mcc_component_index 10492 * Index of the accessed component. Applicable only for commands that 10493 * refer to components. Otherwise, this field is reserved. 10494 * Access: Index 10495 */ 10496 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10497 10498 /* reg_mcc_update_handle 10499 * Token representing the current flow executed by the FSM. 10500 * Access: WO 10501 */ 10502 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10503 10504 /* reg_mcc_error_code 10505 * Indicates the successful completion of the instruction, or the reason it 10506 * failed 10507 * Access: RO 10508 */ 10509 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10510 10511 /* reg_mcc_control_state 10512 * Current FSM state 10513 * Access: RO 10514 */ 10515 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10516 10517 /* reg_mcc_component_size 10518 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10519 * the size may shorten the update time. Value 0x0 means that size is 10520 * unspecified. 10521 * Access: WO 10522 */ 10523 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10524 10525 static inline void mlxsw_reg_mcc_pack(char *payload, 10526 enum mlxsw_reg_mcc_instruction instr, 10527 u16 component_index, u32 update_handle, 10528 u32 component_size) 10529 { 10530 MLXSW_REG_ZERO(mcc, payload); 10531 mlxsw_reg_mcc_instruction_set(payload, instr); 10532 mlxsw_reg_mcc_component_index_set(payload, component_index); 10533 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10534 mlxsw_reg_mcc_component_size_set(payload, component_size); 10535 } 10536 10537 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10538 u8 *p_error_code, u8 *p_control_state) 10539 { 10540 if (p_update_handle) 10541 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10542 if (p_error_code) 10543 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10544 if (p_control_state) 10545 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10546 } 10547 10548 /* MCDA - Management Component Data Access 10549 * --------------------------------------- 10550 * This register allows reading and writing a firmware component. 10551 */ 10552 #define MLXSW_REG_MCDA_ID 0x9063 10553 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10554 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10555 #define MLXSW_REG_MCDA_LEN \ 10556 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10557 10558 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10559 10560 /* reg_mcda_update_handle 10561 * Token representing the current flow executed by the FSM. 10562 * Access: RW 10563 */ 10564 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10565 10566 /* reg_mcda_offset 10567 * Offset of accessed address relative to component start. Accesses must be in 10568 * accordance to log_mcda_word_size in MCQI reg. 10569 * Access: RW 10570 */ 10571 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10572 10573 /* reg_mcda_size 10574 * Size of the data accessed, given in bytes. 10575 * Access: RW 10576 */ 10577 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10578 10579 /* reg_mcda_data 10580 * Data block accessed. 10581 * Access: RW 10582 */ 10583 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10584 10585 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10586 u32 offset, u16 size, u8 *data) 10587 { 10588 int i; 10589 10590 MLXSW_REG_ZERO(mcda, payload); 10591 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10592 mlxsw_reg_mcda_offset_set(payload, offset); 10593 mlxsw_reg_mcda_size_set(payload, size); 10594 10595 for (i = 0; i < size / 4; i++) 10596 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10597 } 10598 10599 /* MPSC - Monitoring Packet Sampling Configuration Register 10600 * -------------------------------------------------------- 10601 * MPSC Register is used to configure the Packet Sampling mechanism. 10602 */ 10603 #define MLXSW_REG_MPSC_ID 0x9080 10604 #define MLXSW_REG_MPSC_LEN 0x1C 10605 10606 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10607 10608 /* reg_mpsc_local_port 10609 * Local port number 10610 * Not supported for CPU port 10611 * Access: Index 10612 */ 10613 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10614 10615 /* reg_mpsc_e 10616 * Enable sampling on port local_port 10617 * Access: RW 10618 */ 10619 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10620 10621 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10622 10623 /* reg_mpsc_rate 10624 * Sampling rate = 1 out of rate packets (with randomization around 10625 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10626 * Access: RW 10627 */ 10628 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10629 10630 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10631 u32 rate) 10632 { 10633 MLXSW_REG_ZERO(mpsc, payload); 10634 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10635 mlxsw_reg_mpsc_e_set(payload, e); 10636 mlxsw_reg_mpsc_rate_set(payload, rate); 10637 } 10638 10639 /* MGPC - Monitoring General Purpose Counter Set Register 10640 * The MGPC register retrieves and sets the General Purpose Counter Set. 10641 */ 10642 #define MLXSW_REG_MGPC_ID 0x9081 10643 #define MLXSW_REG_MGPC_LEN 0x18 10644 10645 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10646 10647 /* reg_mgpc_counter_set_type 10648 * Counter set type. 10649 * Access: OP 10650 */ 10651 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10652 10653 /* reg_mgpc_counter_index 10654 * Counter index. 10655 * Access: Index 10656 */ 10657 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10658 10659 enum mlxsw_reg_mgpc_opcode { 10660 /* Nop */ 10661 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10662 /* Clear counters */ 10663 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10664 }; 10665 10666 /* reg_mgpc_opcode 10667 * Opcode. 10668 * Access: OP 10669 */ 10670 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10671 10672 /* reg_mgpc_byte_counter 10673 * Byte counter value. 10674 * Access: RW 10675 */ 10676 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10677 10678 /* reg_mgpc_packet_counter 10679 * Packet counter value. 10680 * Access: RW 10681 */ 10682 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10683 10684 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10685 enum mlxsw_reg_mgpc_opcode opcode, 10686 enum mlxsw_reg_flow_counter_set_type set_type) 10687 { 10688 MLXSW_REG_ZERO(mgpc, payload); 10689 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10690 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10691 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10692 } 10693 10694 /* MPRS - Monitoring Parsing State Register 10695 * ---------------------------------------- 10696 * The MPRS register is used for setting up the parsing for hash, 10697 * policy-engine and routing. 10698 */ 10699 #define MLXSW_REG_MPRS_ID 0x9083 10700 #define MLXSW_REG_MPRS_LEN 0x14 10701 10702 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10703 10704 /* reg_mprs_parsing_depth 10705 * Minimum parsing depth. 10706 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10707 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10708 * Access: RW 10709 */ 10710 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10711 10712 /* reg_mprs_parsing_en 10713 * Parsing enable. 10714 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10715 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10716 * Access: RW 10717 */ 10718 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10719 10720 /* reg_mprs_vxlan_udp_dport 10721 * VxLAN UDP destination port. 10722 * Used for identifying VxLAN packets and for dport field in 10723 * encapsulation. Default is 4789. 10724 * Access: RW 10725 */ 10726 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10727 10728 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10729 u16 vxlan_udp_dport) 10730 { 10731 MLXSW_REG_ZERO(mprs, payload); 10732 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10733 mlxsw_reg_mprs_parsing_en_set(payload, true); 10734 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10735 } 10736 10737 /* MOGCR - Monitoring Global Configuration Register 10738 * ------------------------------------------------ 10739 */ 10740 #define MLXSW_REG_MOGCR_ID 0x9086 10741 #define MLXSW_REG_MOGCR_LEN 0x20 10742 10743 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10744 10745 /* reg_mogcr_ptp_iftc 10746 * PTP Ingress FIFO Trap Clear 10747 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10748 * to this value. Default 0. 10749 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10750 * Access: RW 10751 */ 10752 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10753 10754 /* reg_mogcr_ptp_eftc 10755 * PTP Egress FIFO Trap Clear 10756 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10757 * to this value. Default 0. 10758 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10759 * Access: RW 10760 */ 10761 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10762 10763 /* reg_mogcr_mirroring_pid_base 10764 * Base policer id for mirroring policers. 10765 * Must have an even value (e.g. 1000, not 1001). 10766 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10767 * Access: RW 10768 */ 10769 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10770 10771 /* MPAGR - Monitoring Port Analyzer Global Register 10772 * ------------------------------------------------ 10773 * This register is used for global port analyzer configurations. 10774 * Note: This register is not supported by current FW versions for Spectrum-1. 10775 */ 10776 #define MLXSW_REG_MPAGR_ID 0x9089 10777 #define MLXSW_REG_MPAGR_LEN 0x0C 10778 10779 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10780 10781 enum mlxsw_reg_mpagr_trigger { 10782 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10783 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10784 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10785 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10786 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10787 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10788 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10789 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10790 }; 10791 10792 /* reg_mpagr_trigger 10793 * Mirror trigger. 10794 * Access: Index 10795 */ 10796 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10797 10798 /* reg_mpagr_pa_id 10799 * Port analyzer ID. 10800 * Access: RW 10801 */ 10802 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10803 10804 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10805 10806 /* reg_mpagr_probability_rate 10807 * Sampling rate. 10808 * Valid values are: 1 to 3.5*10^9 10809 * Value of 1 means "sample all". Default is 1. 10810 * Access: RW 10811 */ 10812 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10813 10814 static inline void mlxsw_reg_mpagr_pack(char *payload, 10815 enum mlxsw_reg_mpagr_trigger trigger, 10816 u8 pa_id, u32 probability_rate) 10817 { 10818 MLXSW_REG_ZERO(mpagr, payload); 10819 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10820 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10821 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10822 } 10823 10824 /* MOMTE - Monitoring Mirror Trigger Enable Register 10825 * ------------------------------------------------- 10826 * This register is used to configure the mirror enable for different mirror 10827 * reasons. 10828 */ 10829 #define MLXSW_REG_MOMTE_ID 0x908D 10830 #define MLXSW_REG_MOMTE_LEN 0x10 10831 10832 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10833 10834 /* reg_momte_local_port 10835 * Local port number. 10836 * Access: Index 10837 */ 10838 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10839 10840 enum mlxsw_reg_momte_type { 10841 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10842 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10843 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10844 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10845 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10846 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10847 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10848 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10849 }; 10850 10851 /* reg_momte_type 10852 * Type of mirroring. 10853 * Access: Index 10854 */ 10855 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10856 10857 /* reg_momte_tclass_en 10858 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10859 * 0: disable (default) 10860 * 1: enable 10861 * Access: RW 10862 */ 10863 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10864 10865 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10866 enum mlxsw_reg_momte_type type) 10867 { 10868 MLXSW_REG_ZERO(momte, payload); 10869 mlxsw_reg_momte_local_port_set(payload, local_port); 10870 mlxsw_reg_momte_type_set(payload, type); 10871 } 10872 10873 /* MTPPPC - Time Precision Packet Port Configuration 10874 * ------------------------------------------------- 10875 * This register serves for configuration of which PTP messages should be 10876 * timestamped. This is a global configuration, despite the register name. 10877 * 10878 * Reserved when Spectrum-2. 10879 */ 10880 #define MLXSW_REG_MTPPPC_ID 0x9090 10881 #define MLXSW_REG_MTPPPC_LEN 0x28 10882 10883 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10884 10885 /* reg_mtpppc_ing_timestamp_message_type 10886 * Bitwise vector of PTP message types to timestamp at ingress. 10887 * MessageType field as defined by IEEE 1588 10888 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10889 * Default all 0 10890 * Access: RW 10891 */ 10892 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10893 10894 /* reg_mtpppc_egr_timestamp_message_type 10895 * Bitwise vector of PTP message types to timestamp at egress. 10896 * MessageType field as defined by IEEE 1588 10897 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10898 * Default all 0 10899 * Access: RW 10900 */ 10901 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10902 10903 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10904 { 10905 MLXSW_REG_ZERO(mtpppc, payload); 10906 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10907 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10908 } 10909 10910 /* MTPPTR - Time Precision Packet Timestamping Reading 10911 * --------------------------------------------------- 10912 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10913 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10914 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10915 * trapped. The sequence number is used to synchronize the timestamp FIFO 10916 * entries and the trapped packets. 10917 * Reserved when Spectrum-2. 10918 */ 10919 10920 #define MLXSW_REG_MTPPTR_ID 0x9091 10921 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10922 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10923 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10924 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10925 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10926 10927 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10928 10929 /* reg_mtpptr_local_port 10930 * Not supported for CPU port. 10931 * Access: Index 10932 */ 10933 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10934 10935 enum mlxsw_reg_mtpptr_dir { 10936 MLXSW_REG_MTPPTR_DIR_INGRESS, 10937 MLXSW_REG_MTPPTR_DIR_EGRESS, 10938 }; 10939 10940 /* reg_mtpptr_dir 10941 * Direction. 10942 * Access: Index 10943 */ 10944 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10945 10946 /* reg_mtpptr_clr 10947 * Clear the records. 10948 * Access: OP 10949 */ 10950 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10951 10952 /* reg_mtpptr_num_rec 10953 * Number of valid records in the response 10954 * Range 0.. cap_ptp_timestamp_fifo 10955 * Access: RO 10956 */ 10957 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10958 10959 /* reg_mtpptr_rec_message_type 10960 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10961 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10962 * Access: RO 10963 */ 10964 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10965 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10966 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10967 10968 /* reg_mtpptr_rec_domain_number 10969 * DomainNumber field as defined by IEEE 1588 10970 * Access: RO 10971 */ 10972 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10973 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10974 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10975 10976 /* reg_mtpptr_rec_sequence_id 10977 * SequenceId field as defined by IEEE 1588 10978 * Access: RO 10979 */ 10980 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10981 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10982 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10983 10984 /* reg_mtpptr_rec_timestamp_high 10985 * Timestamp of when the PTP packet has passed through the port Units of PLL 10986 * clock time. 10987 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10988 * Access: RO 10989 */ 10990 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10991 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10992 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10993 10994 /* reg_mtpptr_rec_timestamp_low 10995 * See rec_timestamp_high. 10996 * Access: RO 10997 */ 10998 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10999 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11000 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 11001 11002 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 11003 unsigned int rec, 11004 u8 *p_message_type, 11005 u8 *p_domain_number, 11006 u16 *p_sequence_id, 11007 u64 *p_timestamp) 11008 { 11009 u32 timestamp_high, timestamp_low; 11010 11011 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 11012 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 11013 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 11014 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 11015 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 11016 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 11017 } 11018 11019 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 11020 * --------------------------------------------------------- 11021 * This register is used for configuring under which trap to deliver PTP 11022 * packets depending on type of the packet. 11023 */ 11024 #define MLXSW_REG_MTPTPT_ID 0x9092 11025 #define MLXSW_REG_MTPTPT_LEN 0x08 11026 11027 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 11028 11029 enum mlxsw_reg_mtptpt_trap_id { 11030 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 11031 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 11032 }; 11033 11034 /* reg_mtptpt_trap_id 11035 * Trap id. 11036 * Access: Index 11037 */ 11038 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 11039 11040 /* reg_mtptpt_message_type 11041 * Bitwise vector of PTP message types to trap. This is a necessary but 11042 * non-sufficient condition since need to enable also per port. See MTPPPC. 11043 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 11044 * Bit0: Sync, Bit1: Delay_Req) 11045 */ 11046 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 11047 11048 static inline void mlxsw_reg_mtptptp_pack(char *payload, 11049 enum mlxsw_reg_mtptpt_trap_id trap_id, 11050 u16 message_type) 11051 { 11052 MLXSW_REG_ZERO(mtptpt, payload); 11053 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 11054 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 11055 } 11056 11057 /* MFGD - Monitoring FW General Debug Register 11058 * ------------------------------------------- 11059 */ 11060 #define MLXSW_REG_MFGD_ID 0x90F0 11061 #define MLXSW_REG_MFGD_LEN 0x0C 11062 11063 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11064 11065 /* reg_mfgd_fw_fatal_event_mode 11066 * 0 - don't check FW fatal (default) 11067 * 1 - check FW fatal - enable MFDE trap 11068 * Access: RW 11069 */ 11070 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11071 11072 /* reg_mfgd_trigger_test 11073 * Access: WO 11074 */ 11075 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11076 11077 /* MGPIR - Management General Peripheral Information Register 11078 * ---------------------------------------------------------- 11079 * MGPIR register allows software to query the hardware and 11080 * firmware general information of peripheral entities. 11081 */ 11082 #define MLXSW_REG_MGPIR_ID 0x9100 11083 #define MLXSW_REG_MGPIR_LEN 0xA0 11084 11085 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11086 11087 enum mlxsw_reg_mgpir_device_type { 11088 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11089 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11090 }; 11091 11092 /* mgpir_slot_index 11093 * Slot index (0: Main board). 11094 * Access: Index 11095 */ 11096 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11097 11098 /* mgpir_device_type 11099 * Access: RO 11100 */ 11101 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11102 11103 /* mgpir_devices_per_flash 11104 * Number of devices of device_type per flash (can be shared by few devices). 11105 * Access: RO 11106 */ 11107 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11108 11109 /* mgpir_num_of_devices 11110 * Number of devices of device_type. 11111 * Access: RO 11112 */ 11113 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11114 11115 /* max_modules_per_slot 11116 * Maximum number of modules that can be connected per slot. 11117 * Access: RO 11118 */ 11119 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11120 11121 /* mgpir_num_of_slots 11122 * Number of slots in the system. 11123 * Access: RO 11124 */ 11125 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11126 11127 /* mgpir_num_of_modules 11128 * Number of modules. 11129 * Access: RO 11130 */ 11131 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11132 11133 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11134 { 11135 MLXSW_REG_ZERO(mgpir, payload); 11136 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11137 } 11138 11139 static inline void 11140 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11141 enum mlxsw_reg_mgpir_device_type *device_type, 11142 u8 *devices_per_flash, u8 *num_of_modules, 11143 u8 *num_of_slots) 11144 { 11145 if (num_of_devices) 11146 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11147 if (device_type) 11148 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11149 if (devices_per_flash) 11150 *devices_per_flash = 11151 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11152 if (num_of_modules) 11153 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11154 if (num_of_slots) 11155 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11156 } 11157 11158 /* MBCT - Management Binary Code Transfer Register 11159 * ----------------------------------------------- 11160 * This register allows to transfer binary codes from the host to 11161 * the management FW by transferring it by chunks of maximum 1KB. 11162 */ 11163 #define MLXSW_REG_MBCT_ID 0x9120 11164 #define MLXSW_REG_MBCT_LEN 0x420 11165 11166 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11167 11168 /* reg_mbct_slot_index 11169 * Slot index. 0 is reserved. 11170 * Access: Index 11171 */ 11172 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11173 11174 /* reg_mbct_data_size 11175 * Actual data field size in bytes for the current data transfer. 11176 * Access: WO 11177 */ 11178 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11179 11180 enum mlxsw_reg_mbct_op { 11181 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11182 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11183 MLXSW_REG_MBCT_OP_ACTIVATE, 11184 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11185 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11186 }; 11187 11188 /* reg_mbct_op 11189 * Access: WO 11190 */ 11191 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11192 11193 /* reg_mbct_last 11194 * Indicates that the current data field is the last chunk of the INI. 11195 * Access: WO 11196 */ 11197 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11198 11199 /* reg_mbct_oee 11200 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11201 * was executed and the fsm_state has changed. 11202 * Access: WO 11203 */ 11204 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11205 11206 enum mlxsw_reg_mbct_status { 11207 /* Partial data transfer completed successfully and ready for next 11208 * data transfer. 11209 */ 11210 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11211 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11212 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11213 /* Error - trying to erase INI while it being used. */ 11214 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11215 /* Last data transfer completed, applying magic pattern. */ 11216 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11217 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11218 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11219 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11220 }; 11221 11222 /* reg_mbct_status 11223 * Status. 11224 * Access: RO 11225 */ 11226 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11227 11228 enum mlxsw_reg_mbct_fsm_state { 11229 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11230 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11231 }; 11232 11233 /* reg_mbct_fsm_state 11234 * FSM state. 11235 * Access: RO 11236 */ 11237 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11238 11239 #define MLXSW_REG_MBCT_DATA_LEN 1024 11240 11241 /* reg_mbct_data 11242 * Up to 1KB of data. 11243 * Access: WO 11244 */ 11245 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11246 11247 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11248 enum mlxsw_reg_mbct_op op, bool oee) 11249 { 11250 MLXSW_REG_ZERO(mbct, payload); 11251 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11252 mlxsw_reg_mbct_op_set(payload, op); 11253 mlxsw_reg_mbct_oee_set(payload, oee); 11254 } 11255 11256 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11257 u16 data_size, bool last, 11258 const char *data) 11259 { 11260 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11261 return; 11262 mlxsw_reg_mbct_data_size_set(payload, data_size); 11263 mlxsw_reg_mbct_last_set(payload, last); 11264 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11265 } 11266 11267 static inline void 11268 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11269 enum mlxsw_reg_mbct_status *p_status, 11270 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11271 { 11272 if (p_slot_index) 11273 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11274 *p_status = mlxsw_reg_mbct_status_get(payload); 11275 if (p_fsm_state) 11276 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11277 } 11278 11279 /* MDDQ - Management DownStream Device Query Register 11280 * -------------------------------------------------- 11281 * This register allows to query the DownStream device properties. The desired 11282 * information is chosen upon the query_type field and is delivered by 32B 11283 * of data blocks. 11284 */ 11285 #define MLXSW_REG_MDDQ_ID 0x9161 11286 #define MLXSW_REG_MDDQ_LEN 0x30 11287 11288 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11289 11290 /* reg_mddq_sie 11291 * Slot info event enable. 11292 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11293 * active / ready will generate a DSDSC event. 11294 * Access: RW 11295 */ 11296 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11297 11298 enum mlxsw_reg_mddq_query_type { 11299 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11300 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME = 3, 11301 }; 11302 11303 /* reg_mddq_query_type 11304 * Access: Index 11305 */ 11306 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11307 11308 /* reg_mddq_slot_index 11309 * Slot index. 0 is reserved. 11310 * Access: Index 11311 */ 11312 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11313 11314 /* reg_mddq_slot_info_provisioned 11315 * If set, the INI file is applied and the card is provisioned. 11316 * Access: RO 11317 */ 11318 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11319 11320 /* reg_mddq_slot_info_sr_valid 11321 * If set, Shift Register is valid (after being provisioned) and data 11322 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11323 * Access: RO 11324 */ 11325 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11326 11327 enum mlxsw_reg_mddq_slot_info_ready { 11328 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11329 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11330 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11331 }; 11332 11333 /* reg_mddq_slot_info_lc_ready 11334 * If set, the LC is powered on, matching the INI version and a new FW 11335 * version can be burnt (if necessary). 11336 * Access: RO 11337 */ 11338 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11339 11340 /* reg_mddq_slot_info_active 11341 * If set, the FW has completed the MDDC.device_enable command. 11342 * Access: RO 11343 */ 11344 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11345 11346 /* reg_mddq_slot_info_hw_revision 11347 * Major user-configured version number of the current INI file. 11348 * Valid only when active or ready are '1'. 11349 * Access: RO 11350 */ 11351 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11352 11353 /* reg_mddq_slot_info_ini_file_version 11354 * User-configured version number of the current INI file. 11355 * Valid only when active or lc_ready are '1'. 11356 * Access: RO 11357 */ 11358 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11359 11360 /* reg_mddq_slot_info_card_type 11361 * Access: RO 11362 */ 11363 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11364 11365 static inline void 11366 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11367 enum mlxsw_reg_mddq_query_type query_type) 11368 { 11369 MLXSW_REG_ZERO(mddq, payload); 11370 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11371 mlxsw_reg_mddq_query_type_set(payload, query_type); 11372 } 11373 11374 static inline void 11375 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11376 { 11377 __mlxsw_reg_mddq_pack(payload, slot_index, 11378 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11379 mlxsw_reg_mddq_sie_set(payload, sie); 11380 } 11381 11382 static inline void 11383 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11384 bool *p_provisioned, bool *p_sr_valid, 11385 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11386 bool *p_active, u16 *p_hw_revision, 11387 u16 *p_ini_file_version, 11388 u8 *p_card_type) 11389 { 11390 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11391 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11392 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11393 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11394 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11395 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11396 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11397 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11398 } 11399 11400 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11401 11402 /* reg_mddq_slot_ascii_name 11403 * Slot's ASCII name. 11404 * Access: RO 11405 */ 11406 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11407 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11408 11409 static inline void 11410 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11411 { 11412 __mlxsw_reg_mddq_pack(payload, slot_index, 11413 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11414 } 11415 11416 static inline void 11417 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11418 { 11419 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11420 } 11421 11422 /* MDDC - Management DownStream Device Control Register 11423 * ---------------------------------------------------- 11424 * This register allows to control downstream devices and line cards. 11425 */ 11426 #define MLXSW_REG_MDDC_ID 0x9163 11427 #define MLXSW_REG_MDDC_LEN 0x30 11428 11429 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11430 11431 /* reg_mddc_slot_index 11432 * Slot index. 0 is reserved. 11433 * Access: Index 11434 */ 11435 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11436 11437 /* reg_mddc_rst 11438 * Reset request. 11439 * Access: OP 11440 */ 11441 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11442 11443 /* reg_mddc_device_enable 11444 * When set, FW is the manager and allowed to program the downstream device. 11445 * Access: RW 11446 */ 11447 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11448 11449 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11450 bool device_enable) 11451 { 11452 MLXSW_REG_ZERO(mddc, payload); 11453 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11454 mlxsw_reg_mddc_rst_set(payload, rst); 11455 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11456 } 11457 11458 /* MFDE - Monitoring FW Debug Register 11459 * ----------------------------------- 11460 */ 11461 #define MLXSW_REG_MFDE_ID 0x9200 11462 #define MLXSW_REG_MFDE_LEN 0x30 11463 11464 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11465 11466 /* reg_mfde_irisc_id 11467 * Which irisc triggered the event 11468 * Access: RO 11469 */ 11470 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11471 11472 enum mlxsw_reg_mfde_severity { 11473 /* Unrecoverable switch behavior */ 11474 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11475 /* Unexpected state with possible systemic failure */ 11476 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11477 /* Unexpected state without systemic failure */ 11478 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11479 }; 11480 11481 /* reg_mfde_severity 11482 * The severity of the event. 11483 * Access: RO 11484 */ 11485 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11486 11487 enum mlxsw_reg_mfde_event_id { 11488 /* CRspace timeout */ 11489 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11490 /* KVD insertion machine stopped */ 11491 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11492 /* Triggered by MFGD.trigger_test */ 11493 MLXSW_REG_MFDE_EVENT_ID_TEST, 11494 /* Triggered when firmware hits an assert */ 11495 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11496 /* Fatal error interrupt from hardware */ 11497 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11498 }; 11499 11500 /* reg_mfde_event_id 11501 * Access: RO 11502 */ 11503 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11504 11505 enum mlxsw_reg_mfde_method { 11506 MLXSW_REG_MFDE_METHOD_QUERY, 11507 MLXSW_REG_MFDE_METHOD_WRITE, 11508 }; 11509 11510 /* reg_mfde_method 11511 * Access: RO 11512 */ 11513 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11514 11515 /* reg_mfde_long_process 11516 * Indicates if the command is in long_process mode. 11517 * Access: RO 11518 */ 11519 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11520 11521 enum mlxsw_reg_mfde_command_type { 11522 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11523 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11524 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11525 }; 11526 11527 /* reg_mfde_command_type 11528 * Access: RO 11529 */ 11530 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11531 11532 /* reg_mfde_reg_attr_id 11533 * EMAD - register id, MAD - attibute id 11534 * Access: RO 11535 */ 11536 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11537 11538 /* reg_mfde_crspace_to_log_address 11539 * crspace address accessed, which resulted in timeout. 11540 * Access: RO 11541 */ 11542 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11543 11544 /* reg_mfde_crspace_to_oe 11545 * 0 - New event 11546 * 1 - Old event, occurred before MFGD activation. 11547 * Access: RO 11548 */ 11549 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11550 11551 /* reg_mfde_crspace_to_log_id 11552 * Which irisc triggered the timeout. 11553 * Access: RO 11554 */ 11555 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11556 11557 /* reg_mfde_crspace_to_log_ip 11558 * IP (instruction pointer) that triggered the timeout. 11559 * Access: RO 11560 */ 11561 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11562 11563 /* reg_mfde_kvd_im_stop_oe 11564 * 0 - New event 11565 * 1 - Old event, occurred before MFGD activation. 11566 * Access: RO 11567 */ 11568 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11569 11570 /* reg_mfde_kvd_im_stop_pipes_mask 11571 * Bit per kvh pipe. 11572 * Access: RO 11573 */ 11574 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11575 11576 /* reg_mfde_fw_assert_var0-4 11577 * Variables passed to assert. 11578 * Access: RO 11579 */ 11580 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11581 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11582 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11583 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11584 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11585 11586 /* reg_mfde_fw_assert_existptr 11587 * The instruction pointer when assert was triggered. 11588 * Access: RO 11589 */ 11590 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11591 11592 /* reg_mfde_fw_assert_callra 11593 * The return address after triggering assert. 11594 * Access: RO 11595 */ 11596 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11597 11598 /* reg_mfde_fw_assert_oe 11599 * 0 - New event 11600 * 1 - Old event, occurred before MFGD activation. 11601 * Access: RO 11602 */ 11603 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11604 11605 /* reg_mfde_fw_assert_tile_v 11606 * 0: The assert was from main 11607 * 1: The assert was from a tile 11608 * Access: RO 11609 */ 11610 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11611 11612 /* reg_mfde_fw_assert_tile_index 11613 * When tile_v=1, the tile_index that caused the assert. 11614 * Access: RO 11615 */ 11616 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11617 11618 /* reg_mfde_fw_assert_ext_synd 11619 * A generated one-to-one identifier which is specific per-assert. 11620 * Access: RO 11621 */ 11622 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11623 11624 /* reg_mfde_fatal_cause_id 11625 * HW interrupt cause id. 11626 * Access: RO 11627 */ 11628 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11629 11630 /* reg_mfde_fatal_cause_tile_v 11631 * 0: The assert was from main 11632 * 1: The assert was from a tile 11633 * Access: RO 11634 */ 11635 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11636 11637 /* reg_mfde_fatal_cause_tile_index 11638 * When tile_v=1, the tile_index that caused the assert. 11639 * Access: RO 11640 */ 11641 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11642 11643 /* TNGCR - Tunneling NVE General Configuration Register 11644 * ---------------------------------------------------- 11645 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11646 */ 11647 #define MLXSW_REG_TNGCR_ID 0xA001 11648 #define MLXSW_REG_TNGCR_LEN 0x44 11649 11650 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11651 11652 enum mlxsw_reg_tngcr_type { 11653 MLXSW_REG_TNGCR_TYPE_VXLAN, 11654 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11655 MLXSW_REG_TNGCR_TYPE_GENEVE, 11656 MLXSW_REG_TNGCR_TYPE_NVGRE, 11657 }; 11658 11659 /* reg_tngcr_type 11660 * Tunnel type for encapsulation and decapsulation. The types are mutually 11661 * exclusive. 11662 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11663 * Access: RW 11664 */ 11665 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11666 11667 /* reg_tngcr_nve_valid 11668 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11669 * Access: RW 11670 */ 11671 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11672 11673 /* reg_tngcr_nve_ttl_uc 11674 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11675 * Access: RW 11676 */ 11677 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11678 11679 /* reg_tngcr_nve_ttl_mc 11680 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11681 * Access: RW 11682 */ 11683 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11684 11685 enum { 11686 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11687 MLXSW_REG_TNGCR_FL_NO_COPY, 11688 /* Copy flow label from inner packet if packet is IPv6 and 11689 * encapsulation is by IPv6. Otherwise, calculate flow label using 11690 * nve_flh. 11691 */ 11692 MLXSW_REG_TNGCR_FL_COPY, 11693 }; 11694 11695 /* reg_tngcr_nve_flc 11696 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11697 * Access: RW 11698 */ 11699 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11700 11701 enum { 11702 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11703 * uses {nve_fl_prefix, nve_fl_suffix}. 11704 */ 11705 MLXSW_REG_TNGCR_FL_NO_HASH, 11706 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11707 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11708 */ 11709 MLXSW_REG_TNGCR_FL_HASH, 11710 }; 11711 11712 /* reg_tngcr_nve_flh 11713 * NVE flow label hash. 11714 * Access: RW 11715 */ 11716 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11717 11718 /* reg_tngcr_nve_fl_prefix 11719 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11720 * Access: RW 11721 */ 11722 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11723 11724 /* reg_tngcr_nve_fl_suffix 11725 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11726 * Reserved when nve_flh=1 and for Spectrum. 11727 * Access: RW 11728 */ 11729 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11730 11731 enum { 11732 /* Source UDP port is fixed (default '0') */ 11733 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11734 /* Source UDP port is calculated based on hash */ 11735 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11736 }; 11737 11738 /* reg_tngcr_nve_udp_sport_type 11739 * NVE UDP source port type. 11740 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11741 * When the source UDP port is calculated based on hash, then the 8 LSBs 11742 * are calculated from hash the 8 MSBs are configured by 11743 * nve_udp_sport_prefix. 11744 * Access: RW 11745 */ 11746 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11747 11748 /* reg_tngcr_nve_udp_sport_prefix 11749 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11750 * Reserved when NVE type is NVGRE. 11751 * Access: RW 11752 */ 11753 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11754 11755 /* reg_tngcr_nve_group_size_mc 11756 * The amount of sequential linked lists of MC entries. The first linked 11757 * list is configured by SFD.underlay_mc_ptr. 11758 * Valid values: 1, 2, 4, 8, 16, 32, 64 11759 * The linked list are configured by TNUMT. 11760 * The hash is set by LAG hash. 11761 * Access: RW 11762 */ 11763 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11764 11765 /* reg_tngcr_nve_group_size_flood 11766 * The amount of sequential linked lists of flooding entries. The first 11767 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11768 * Valid values: 1, 2, 4, 8, 16, 32, 64 11769 * The linked list are configured by TNUMT. 11770 * The hash is set by LAG hash. 11771 * Access: RW 11772 */ 11773 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11774 11775 /* reg_tngcr_learn_enable 11776 * During decapsulation, whether to learn from NVE port. 11777 * Reserved when Spectrum-2. See TNPC. 11778 * Access: RW 11779 */ 11780 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11781 11782 /* reg_tngcr_underlay_virtual_router 11783 * Underlay virtual router. 11784 * Reserved when Spectrum-2. 11785 * Access: RW 11786 */ 11787 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11788 11789 /* reg_tngcr_underlay_rif 11790 * Underlay ingress router interface. RIF type should be loopback generic. 11791 * Reserved when Spectrum. 11792 * Access: RW 11793 */ 11794 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11795 11796 /* reg_tngcr_usipv4 11797 * Underlay source IPv4 address of the NVE. 11798 * Access: RW 11799 */ 11800 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11801 11802 /* reg_tngcr_usipv6 11803 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11804 * modified under traffic of NVE tunneling encapsulation. 11805 * Access: RW 11806 */ 11807 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11808 11809 static inline void mlxsw_reg_tngcr_pack(char *payload, 11810 enum mlxsw_reg_tngcr_type type, 11811 bool valid, u8 ttl) 11812 { 11813 MLXSW_REG_ZERO(tngcr, payload); 11814 mlxsw_reg_tngcr_type_set(payload, type); 11815 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11816 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11817 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11818 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11819 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11820 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11821 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11822 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11823 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11824 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11825 } 11826 11827 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11828 * ------------------------------------------------------- 11829 * The TNUMT register is for building the underlay MC table. It is used 11830 * for MC, flooding and BC traffic into the NVE tunnel. 11831 */ 11832 #define MLXSW_REG_TNUMT_ID 0xA003 11833 #define MLXSW_REG_TNUMT_LEN 0x20 11834 11835 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11836 11837 enum mlxsw_reg_tnumt_record_type { 11838 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11839 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11840 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11841 }; 11842 11843 /* reg_tnumt_record_type 11844 * Record type. 11845 * Access: RW 11846 */ 11847 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11848 11849 /* reg_tnumt_tunnel_port 11850 * Tunnel port. 11851 * Access: RW 11852 */ 11853 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11854 11855 /* reg_tnumt_underlay_mc_ptr 11856 * Index to the underlay multicast table. 11857 * For Spectrum the index is to the KVD linear. 11858 * Access: Index 11859 */ 11860 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11861 11862 /* reg_tnumt_vnext 11863 * The next_underlay_mc_ptr is valid. 11864 * Access: RW 11865 */ 11866 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11867 11868 /* reg_tnumt_next_underlay_mc_ptr 11869 * The next index to the underlay multicast table. 11870 * Access: RW 11871 */ 11872 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11873 11874 /* reg_tnumt_record_size 11875 * Number of IP addresses in the record. 11876 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11877 * Access: RW 11878 */ 11879 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11880 11881 /* reg_tnumt_udip 11882 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11883 * Access: RW 11884 */ 11885 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11886 11887 /* reg_tnumt_udip_ptr 11888 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11889 * i >= size. The IPv6 addresses are configured by RIPS. 11890 * Access: RW 11891 */ 11892 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11893 11894 static inline void mlxsw_reg_tnumt_pack(char *payload, 11895 enum mlxsw_reg_tnumt_record_type type, 11896 enum mlxsw_reg_tunnel_port tport, 11897 u32 underlay_mc_ptr, bool vnext, 11898 u32 next_underlay_mc_ptr, 11899 u8 record_size) 11900 { 11901 MLXSW_REG_ZERO(tnumt, payload); 11902 mlxsw_reg_tnumt_record_type_set(payload, type); 11903 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 11904 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 11905 mlxsw_reg_tnumt_vnext_set(payload, vnext); 11906 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 11907 mlxsw_reg_tnumt_record_size_set(payload, record_size); 11908 } 11909 11910 /* TNQCR - Tunneling NVE QoS Configuration Register 11911 * ------------------------------------------------ 11912 * The TNQCR register configures how QoS is set in encapsulation into the 11913 * underlay network. 11914 */ 11915 #define MLXSW_REG_TNQCR_ID 0xA010 11916 #define MLXSW_REG_TNQCR_LEN 0x0C 11917 11918 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 11919 11920 /* reg_tnqcr_enc_set_dscp 11921 * For encapsulation: How to set DSCP field: 11922 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 11923 * (outer) IP header. If there is no IP header, use TNQDR.dscp 11924 * 1 - Set the DSCP field as TNQDR.dscp 11925 * Access: RW 11926 */ 11927 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 11928 11929 static inline void mlxsw_reg_tnqcr_pack(char *payload) 11930 { 11931 MLXSW_REG_ZERO(tnqcr, payload); 11932 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 11933 } 11934 11935 /* TNQDR - Tunneling NVE QoS Default Register 11936 * ------------------------------------------ 11937 * The TNQDR register configures the default QoS settings for NVE 11938 * encapsulation. 11939 */ 11940 #define MLXSW_REG_TNQDR_ID 0xA011 11941 #define MLXSW_REG_TNQDR_LEN 0x08 11942 11943 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 11944 11945 /* reg_tnqdr_local_port 11946 * Local port number (receive port). CPU port is supported. 11947 * Access: Index 11948 */ 11949 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 11950 11951 /* reg_tnqdr_dscp 11952 * For encapsulation, the default DSCP. 11953 * Access: RW 11954 */ 11955 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 11956 11957 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 11958 { 11959 MLXSW_REG_ZERO(tnqdr, payload); 11960 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 11961 mlxsw_reg_tnqdr_dscp_set(payload, 0); 11962 } 11963 11964 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 11965 * -------------------------------------------------------- 11966 * The TNEEM register maps ECN of the IP header at the ingress to the 11967 * encapsulation to the ECN of the underlay network. 11968 */ 11969 #define MLXSW_REG_TNEEM_ID 0xA012 11970 #define MLXSW_REG_TNEEM_LEN 0x0C 11971 11972 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 11973 11974 /* reg_tneem_overlay_ecn 11975 * ECN of the IP header in the overlay network. 11976 * Access: Index 11977 */ 11978 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 11979 11980 /* reg_tneem_underlay_ecn 11981 * ECN of the IP header in the underlay network. 11982 * Access: RW 11983 */ 11984 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 11985 11986 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 11987 u8 underlay_ecn) 11988 { 11989 MLXSW_REG_ZERO(tneem, payload); 11990 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 11991 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 11992 } 11993 11994 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 11995 * -------------------------------------------------------- 11996 * The TNDEM register configures the actions that are done in the 11997 * decapsulation. 11998 */ 11999 #define MLXSW_REG_TNDEM_ID 0xA013 12000 #define MLXSW_REG_TNDEM_LEN 0x0C 12001 12002 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12003 12004 /* reg_tndem_underlay_ecn 12005 * ECN field of the IP header in the underlay network. 12006 * Access: Index 12007 */ 12008 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12009 12010 /* reg_tndem_overlay_ecn 12011 * ECN field of the IP header in the overlay network. 12012 * Access: Index 12013 */ 12014 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12015 12016 /* reg_tndem_eip_ecn 12017 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12018 * from the decapsulation. 12019 * Access: RW 12020 */ 12021 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12022 12023 /* reg_tndem_trap_en 12024 * Trap enable: 12025 * 0 - No trap due to decap ECN 12026 * 1 - Trap enable with trap_id 12027 * Access: RW 12028 */ 12029 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12030 12031 /* reg_tndem_trap_id 12032 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12033 * Reserved when trap_en is '0'. 12034 * Access: RW 12035 */ 12036 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12037 12038 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12039 u8 overlay_ecn, u8 ecn, bool trap_en, 12040 u16 trap_id) 12041 { 12042 MLXSW_REG_ZERO(tndem, payload); 12043 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12044 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12045 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12046 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12047 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12048 } 12049 12050 /* TNPC - Tunnel Port Configuration Register 12051 * ----------------------------------------- 12052 * The TNPC register is used for tunnel port configuration. 12053 * Reserved when Spectrum. 12054 */ 12055 #define MLXSW_REG_TNPC_ID 0xA020 12056 #define MLXSW_REG_TNPC_LEN 0x18 12057 12058 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12059 12060 /* reg_tnpc_tunnel_port 12061 * Tunnel port. 12062 * Access: Index 12063 */ 12064 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12065 12066 /* reg_tnpc_learn_enable_v6 12067 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12068 * Access: RW 12069 */ 12070 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12071 12072 /* reg_tnpc_learn_enable_v4 12073 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12074 * Access: RW 12075 */ 12076 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12077 12078 static inline void mlxsw_reg_tnpc_pack(char *payload, 12079 enum mlxsw_reg_tunnel_port tport, 12080 bool learn_enable) 12081 { 12082 MLXSW_REG_ZERO(tnpc, payload); 12083 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12084 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12085 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12086 } 12087 12088 /* TIGCR - Tunneling IPinIP General Configuration Register 12089 * ------------------------------------------------------- 12090 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12091 */ 12092 #define MLXSW_REG_TIGCR_ID 0xA801 12093 #define MLXSW_REG_TIGCR_LEN 0x10 12094 12095 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12096 12097 /* reg_tigcr_ipip_ttlc 12098 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12099 * header. 12100 * Access: RW 12101 */ 12102 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12103 12104 /* reg_tigcr_ipip_ttl_uc 12105 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12106 * reg_tigcr_ipip_ttlc is unset. 12107 * Access: RW 12108 */ 12109 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12110 12111 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12112 { 12113 MLXSW_REG_ZERO(tigcr, payload); 12114 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12115 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12116 } 12117 12118 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12119 * ----------------------------------------------------------- 12120 * The TIEEM register maps ECN of the IP header at the ingress to the 12121 * encapsulation to the ECN of the underlay network. 12122 */ 12123 #define MLXSW_REG_TIEEM_ID 0xA812 12124 #define MLXSW_REG_TIEEM_LEN 0x0C 12125 12126 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12127 12128 /* reg_tieem_overlay_ecn 12129 * ECN of the IP header in the overlay network. 12130 * Access: Index 12131 */ 12132 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12133 12134 /* reg_tineem_underlay_ecn 12135 * ECN of the IP header in the underlay network. 12136 * Access: RW 12137 */ 12138 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12139 12140 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12141 u8 underlay_ecn) 12142 { 12143 MLXSW_REG_ZERO(tieem, payload); 12144 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12145 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12146 } 12147 12148 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12149 * ----------------------------------------------------------- 12150 * The TIDEM register configures the actions that are done in the 12151 * decapsulation. 12152 */ 12153 #define MLXSW_REG_TIDEM_ID 0xA813 12154 #define MLXSW_REG_TIDEM_LEN 0x0C 12155 12156 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12157 12158 /* reg_tidem_underlay_ecn 12159 * ECN field of the IP header in the underlay network. 12160 * Access: Index 12161 */ 12162 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12163 12164 /* reg_tidem_overlay_ecn 12165 * ECN field of the IP header in the overlay network. 12166 * Access: Index 12167 */ 12168 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12169 12170 /* reg_tidem_eip_ecn 12171 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12172 * from the decapsulation. 12173 * Access: RW 12174 */ 12175 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12176 12177 /* reg_tidem_trap_en 12178 * Trap enable: 12179 * 0 - No trap due to decap ECN 12180 * 1 - Trap enable with trap_id 12181 * Access: RW 12182 */ 12183 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12184 12185 /* reg_tidem_trap_id 12186 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12187 * Reserved when trap_en is '0'. 12188 * Access: RW 12189 */ 12190 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12191 12192 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12193 u8 overlay_ecn, u8 eip_ecn, 12194 bool trap_en, u16 trap_id) 12195 { 12196 MLXSW_REG_ZERO(tidem, payload); 12197 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12198 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12199 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12200 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12201 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12202 } 12203 12204 /* SBPR - Shared Buffer Pools Register 12205 * ----------------------------------- 12206 * The SBPR configures and retrieves the shared buffer pools and configuration. 12207 */ 12208 #define MLXSW_REG_SBPR_ID 0xB001 12209 #define MLXSW_REG_SBPR_LEN 0x14 12210 12211 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12212 12213 /* reg_sbpr_desc 12214 * When set, configures descriptor buffer. 12215 * Access: Index 12216 */ 12217 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12218 12219 /* shared direstion enum for SBPR, SBCM, SBPM */ 12220 enum mlxsw_reg_sbxx_dir { 12221 MLXSW_REG_SBXX_DIR_INGRESS, 12222 MLXSW_REG_SBXX_DIR_EGRESS, 12223 }; 12224 12225 /* reg_sbpr_dir 12226 * Direction. 12227 * Access: Index 12228 */ 12229 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12230 12231 /* reg_sbpr_pool 12232 * Pool index. 12233 * Access: Index 12234 */ 12235 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12236 12237 /* reg_sbpr_infi_size 12238 * Size is infinite. 12239 * Access: RW 12240 */ 12241 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12242 12243 /* reg_sbpr_size 12244 * Pool size in buffer cells. 12245 * Reserved when infi_size = 1. 12246 * Access: RW 12247 */ 12248 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12249 12250 enum mlxsw_reg_sbpr_mode { 12251 MLXSW_REG_SBPR_MODE_STATIC, 12252 MLXSW_REG_SBPR_MODE_DYNAMIC, 12253 }; 12254 12255 /* reg_sbpr_mode 12256 * Pool quota calculation mode. 12257 * Access: RW 12258 */ 12259 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12260 12261 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12262 enum mlxsw_reg_sbxx_dir dir, 12263 enum mlxsw_reg_sbpr_mode mode, u32 size, 12264 bool infi_size) 12265 { 12266 MLXSW_REG_ZERO(sbpr, payload); 12267 mlxsw_reg_sbpr_pool_set(payload, pool); 12268 mlxsw_reg_sbpr_dir_set(payload, dir); 12269 mlxsw_reg_sbpr_mode_set(payload, mode); 12270 mlxsw_reg_sbpr_size_set(payload, size); 12271 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12272 } 12273 12274 /* SBCM - Shared Buffer Class Management Register 12275 * ---------------------------------------------- 12276 * The SBCM register configures and retrieves the shared buffer allocation 12277 * and configuration according to Port-PG, including the binding to pool 12278 * and definition of the associated quota. 12279 */ 12280 #define MLXSW_REG_SBCM_ID 0xB002 12281 #define MLXSW_REG_SBCM_LEN 0x28 12282 12283 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12284 12285 /* reg_sbcm_local_port 12286 * Local port number. 12287 * For Ingress: excludes CPU port and Router port 12288 * For Egress: excludes IP Router 12289 * Access: Index 12290 */ 12291 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12292 12293 /* reg_sbcm_pg_buff 12294 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12295 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12296 * For traffic class: range is 0..cap_max_tclass - 1 12297 * Note that when traffic class is in MC aware mode then the traffic 12298 * classes which are MC aware cannot be configured. 12299 * Access: Index 12300 */ 12301 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12302 12303 /* reg_sbcm_dir 12304 * Direction. 12305 * Access: Index 12306 */ 12307 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12308 12309 /* reg_sbcm_min_buff 12310 * Minimum buffer size for the limiter, in cells. 12311 * Access: RW 12312 */ 12313 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12314 12315 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12316 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12317 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12318 12319 /* reg_sbcm_infi_max 12320 * Max buffer is infinite. 12321 * Access: RW 12322 */ 12323 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12324 12325 /* reg_sbcm_max_buff 12326 * When the pool associated to the port-pg/tclass is configured to 12327 * static, Maximum buffer size for the limiter configured in cells. 12328 * When the pool associated to the port-pg/tclass is configured to 12329 * dynamic, the max_buff holds the "alpha" parameter, supporting 12330 * the following values: 12331 * 0: 0 12332 * i: (1/128)*2^(i-1), for i=1..14 12333 * 0xFF: Infinity 12334 * Reserved when infi_max = 1. 12335 * Access: RW 12336 */ 12337 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12338 12339 /* reg_sbcm_pool 12340 * Association of the port-priority to a pool. 12341 * Access: RW 12342 */ 12343 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12344 12345 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12346 enum mlxsw_reg_sbxx_dir dir, 12347 u32 min_buff, u32 max_buff, 12348 bool infi_max, u8 pool) 12349 { 12350 MLXSW_REG_ZERO(sbcm, payload); 12351 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12352 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12353 mlxsw_reg_sbcm_dir_set(payload, dir); 12354 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12355 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12356 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12357 mlxsw_reg_sbcm_pool_set(payload, pool); 12358 } 12359 12360 /* SBPM - Shared Buffer Port Management Register 12361 * --------------------------------------------- 12362 * The SBPM register configures and retrieves the shared buffer allocation 12363 * and configuration according to Port-Pool, including the definition 12364 * of the associated quota. 12365 */ 12366 #define MLXSW_REG_SBPM_ID 0xB003 12367 #define MLXSW_REG_SBPM_LEN 0x28 12368 12369 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12370 12371 /* reg_sbpm_local_port 12372 * Local port number. 12373 * For Ingress: excludes CPU port and Router port 12374 * For Egress: excludes IP Router 12375 * Access: Index 12376 */ 12377 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12378 12379 /* reg_sbpm_pool 12380 * The pool associated to quota counting on the local_port. 12381 * Access: Index 12382 */ 12383 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12384 12385 /* reg_sbpm_dir 12386 * Direction. 12387 * Access: Index 12388 */ 12389 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12390 12391 /* reg_sbpm_buff_occupancy 12392 * Current buffer occupancy in cells. 12393 * Access: RO 12394 */ 12395 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12396 12397 /* reg_sbpm_clr 12398 * Clear Max Buffer Occupancy 12399 * When this bit is set, max_buff_occupancy field is cleared (and a 12400 * new max value is tracked from the time the clear was performed). 12401 * Access: OP 12402 */ 12403 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12404 12405 /* reg_sbpm_max_buff_occupancy 12406 * Maximum value of buffer occupancy in cells monitored. Cleared by 12407 * writing to the clr field. 12408 * Access: RO 12409 */ 12410 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12411 12412 /* reg_sbpm_min_buff 12413 * Minimum buffer size for the limiter, in cells. 12414 * Access: RW 12415 */ 12416 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12417 12418 /* reg_sbpm_max_buff 12419 * When the pool associated to the port-pg/tclass is configured to 12420 * static, Maximum buffer size for the limiter configured in cells. 12421 * When the pool associated to the port-pg/tclass is configured to 12422 * dynamic, the max_buff holds the "alpha" parameter, supporting 12423 * the following values: 12424 * 0: 0 12425 * i: (1/128)*2^(i-1), for i=1..14 12426 * 0xFF: Infinity 12427 * Access: RW 12428 */ 12429 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12430 12431 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12432 enum mlxsw_reg_sbxx_dir dir, bool clr, 12433 u32 min_buff, u32 max_buff) 12434 { 12435 MLXSW_REG_ZERO(sbpm, payload); 12436 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12437 mlxsw_reg_sbpm_pool_set(payload, pool); 12438 mlxsw_reg_sbpm_dir_set(payload, dir); 12439 mlxsw_reg_sbpm_clr_set(payload, clr); 12440 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12441 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12442 } 12443 12444 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12445 u32 *p_max_buff_occupancy) 12446 { 12447 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12448 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12449 } 12450 12451 /* SBMM - Shared Buffer Multicast Management Register 12452 * -------------------------------------------------- 12453 * The SBMM register configures and retrieves the shared buffer allocation 12454 * and configuration for MC packets according to Switch-Priority, including 12455 * the binding to pool and definition of the associated quota. 12456 */ 12457 #define MLXSW_REG_SBMM_ID 0xB004 12458 #define MLXSW_REG_SBMM_LEN 0x28 12459 12460 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12461 12462 /* reg_sbmm_prio 12463 * Switch Priority. 12464 * Access: Index 12465 */ 12466 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12467 12468 /* reg_sbmm_min_buff 12469 * Minimum buffer size for the limiter, in cells. 12470 * Access: RW 12471 */ 12472 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12473 12474 /* reg_sbmm_max_buff 12475 * When the pool associated to the port-pg/tclass is configured to 12476 * static, Maximum buffer size for the limiter configured in cells. 12477 * When the pool associated to the port-pg/tclass is configured to 12478 * dynamic, the max_buff holds the "alpha" parameter, supporting 12479 * the following values: 12480 * 0: 0 12481 * i: (1/128)*2^(i-1), for i=1..14 12482 * 0xFF: Infinity 12483 * Access: RW 12484 */ 12485 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12486 12487 /* reg_sbmm_pool 12488 * Association of the port-priority to a pool. 12489 * Access: RW 12490 */ 12491 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12492 12493 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12494 u32 max_buff, u8 pool) 12495 { 12496 MLXSW_REG_ZERO(sbmm, payload); 12497 mlxsw_reg_sbmm_prio_set(payload, prio); 12498 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12499 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12500 mlxsw_reg_sbmm_pool_set(payload, pool); 12501 } 12502 12503 /* SBSR - Shared Buffer Status Register 12504 * ------------------------------------ 12505 * The SBSR register retrieves the shared buffer occupancy according to 12506 * Port-Pool. Note that this register enables reading a large amount of data. 12507 * It is the user's responsibility to limit the amount of data to ensure the 12508 * response can match the maximum transfer unit. In case the response exceeds 12509 * the maximum transport unit, it will be truncated with no special notice. 12510 */ 12511 #define MLXSW_REG_SBSR_ID 0xB005 12512 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12513 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12514 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12515 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12516 MLXSW_REG_SBSR_REC_LEN * \ 12517 MLXSW_REG_SBSR_REC_MAX_COUNT) 12518 12519 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12520 12521 /* reg_sbsr_clr 12522 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12523 * field is cleared (and a new max value is tracked from the time the clear 12524 * was performed). 12525 * Access: OP 12526 */ 12527 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12528 12529 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12530 12531 /* reg_sbsr_port_page 12532 * Determines the range of the ports specified in the 'ingress_port_mask' 12533 * and 'egress_port_mask' bit masks. 12534 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12535 * Access: Index 12536 */ 12537 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12538 12539 /* reg_sbsr_ingress_port_mask 12540 * Bit vector for all ingress network ports. 12541 * Indicates which of the ports (for which the relevant bit is set) 12542 * are affected by the set operation. Configuration of any other port 12543 * does not change. 12544 * Access: Index 12545 */ 12546 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12547 12548 /* reg_sbsr_pg_buff_mask 12549 * Bit vector for all switch priority groups. 12550 * Indicates which of the priorities (for which the relevant bit is set) 12551 * are affected by the set operation. Configuration of any other priority 12552 * does not change. 12553 * Range is 0..cap_max_pg_buffers - 1 12554 * Access: Index 12555 */ 12556 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12557 12558 /* reg_sbsr_egress_port_mask 12559 * Bit vector for all egress network ports. 12560 * Indicates which of the ports (for which the relevant bit is set) 12561 * are affected by the set operation. Configuration of any other port 12562 * does not change. 12563 * Access: Index 12564 */ 12565 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12566 12567 /* reg_sbsr_tclass_mask 12568 * Bit vector for all traffic classes. 12569 * Indicates which of the traffic classes (for which the relevant bit is 12570 * set) are affected by the set operation. Configuration of any other 12571 * traffic class does not change. 12572 * Range is 0..cap_max_tclass - 1 12573 * Access: Index 12574 */ 12575 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12576 12577 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12578 { 12579 MLXSW_REG_ZERO(sbsr, payload); 12580 mlxsw_reg_sbsr_clr_set(payload, clr); 12581 } 12582 12583 /* reg_sbsr_rec_buff_occupancy 12584 * Current buffer occupancy in cells. 12585 * Access: RO 12586 */ 12587 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12588 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12589 12590 /* reg_sbsr_rec_max_buff_occupancy 12591 * Maximum value of buffer occupancy in cells monitored. Cleared by 12592 * writing to the clr field. 12593 * Access: RO 12594 */ 12595 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12596 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12597 12598 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12599 u32 *p_buff_occupancy, 12600 u32 *p_max_buff_occupancy) 12601 { 12602 *p_buff_occupancy = 12603 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12604 *p_max_buff_occupancy = 12605 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12606 } 12607 12608 /* SBIB - Shared Buffer Internal Buffer Register 12609 * --------------------------------------------- 12610 * The SBIB register configures per port buffers for internal use. The internal 12611 * buffers consume memory on the port buffers (note that the port buffers are 12612 * used also by PBMC). 12613 * 12614 * For Spectrum this is used for egress mirroring. 12615 */ 12616 #define MLXSW_REG_SBIB_ID 0xB006 12617 #define MLXSW_REG_SBIB_LEN 0x10 12618 12619 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12620 12621 /* reg_sbib_local_port 12622 * Local port number 12623 * Not supported for CPU port and router port 12624 * Access: Index 12625 */ 12626 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12627 12628 /* reg_sbib_buff_size 12629 * Units represented in cells 12630 * Allowed range is 0 to (cap_max_headroom_size - 1) 12631 * Default is 0 12632 * Access: RW 12633 */ 12634 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12635 12636 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12637 u32 buff_size) 12638 { 12639 MLXSW_REG_ZERO(sbib, payload); 12640 mlxsw_reg_sbib_local_port_set(payload, local_port); 12641 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12642 } 12643 12644 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12645 MLXSW_REG(sgcr), 12646 MLXSW_REG(spad), 12647 MLXSW_REG(sspr), 12648 MLXSW_REG(sfdat), 12649 MLXSW_REG(sfd), 12650 MLXSW_REG(sfn), 12651 MLXSW_REG(spms), 12652 MLXSW_REG(spvid), 12653 MLXSW_REG(spvm), 12654 MLXSW_REG(spaft), 12655 MLXSW_REG(sfgc), 12656 MLXSW_REG(sfdf), 12657 MLXSW_REG(sldr), 12658 MLXSW_REG(slcr), 12659 MLXSW_REG(slcor), 12660 MLXSW_REG(spmlr), 12661 MLXSW_REG(svfa), 12662 MLXSW_REG(spvtr), 12663 MLXSW_REG(svpe), 12664 MLXSW_REG(sfmr), 12665 MLXSW_REG(spvmlr), 12666 MLXSW_REG(spvc), 12667 MLXSW_REG(spevet), 12668 MLXSW_REG(smpe), 12669 MLXSW_REG(sftr2), 12670 MLXSW_REG(smid2), 12671 MLXSW_REG(cwtp), 12672 MLXSW_REG(cwtpm), 12673 MLXSW_REG(pgcr), 12674 MLXSW_REG(ppbt), 12675 MLXSW_REG(pacl), 12676 MLXSW_REG(pagt), 12677 MLXSW_REG(ptar), 12678 MLXSW_REG(ppbs), 12679 MLXSW_REG(prcr), 12680 MLXSW_REG(pefa), 12681 MLXSW_REG(pemrbt), 12682 MLXSW_REG(ptce2), 12683 MLXSW_REG(perpt), 12684 MLXSW_REG(peabfe), 12685 MLXSW_REG(perar), 12686 MLXSW_REG(ptce3), 12687 MLXSW_REG(percr), 12688 MLXSW_REG(pererp), 12689 MLXSW_REG(iedr), 12690 MLXSW_REG(qpts), 12691 MLXSW_REG(qpcr), 12692 MLXSW_REG(qtct), 12693 MLXSW_REG(qeec), 12694 MLXSW_REG(qrwe), 12695 MLXSW_REG(qpdsm), 12696 MLXSW_REG(qpdp), 12697 MLXSW_REG(qpdpm), 12698 MLXSW_REG(qtctm), 12699 MLXSW_REG(qpsc), 12700 MLXSW_REG(pmlp), 12701 MLXSW_REG(pmtu), 12702 MLXSW_REG(ptys), 12703 MLXSW_REG(ppad), 12704 MLXSW_REG(paos), 12705 MLXSW_REG(pfcc), 12706 MLXSW_REG(ppcnt), 12707 MLXSW_REG(plib), 12708 MLXSW_REG(pptb), 12709 MLXSW_REG(pbmc), 12710 MLXSW_REG(pspa), 12711 MLXSW_REG(pmaos), 12712 MLXSW_REG(pplr), 12713 MLXSW_REG(pmtdb), 12714 MLXSW_REG(pmecr), 12715 MLXSW_REG(pmpe), 12716 MLXSW_REG(pddr), 12717 MLXSW_REG(pmmp), 12718 MLXSW_REG(pllp), 12719 MLXSW_REG(pmtm), 12720 MLXSW_REG(htgt), 12721 MLXSW_REG(hpkt), 12722 MLXSW_REG(rgcr), 12723 MLXSW_REG(ritr), 12724 MLXSW_REG(rtar), 12725 MLXSW_REG(ratr), 12726 MLXSW_REG(rtdp), 12727 MLXSW_REG(rips), 12728 MLXSW_REG(ratrad), 12729 MLXSW_REG(rdpm), 12730 MLXSW_REG(ricnt), 12731 MLXSW_REG(rrcr), 12732 MLXSW_REG(ralta), 12733 MLXSW_REG(ralst), 12734 MLXSW_REG(raltb), 12735 MLXSW_REG(ralue), 12736 MLXSW_REG(rauht), 12737 MLXSW_REG(raleu), 12738 MLXSW_REG(rauhtd), 12739 MLXSW_REG(rigr2), 12740 MLXSW_REG(recr2), 12741 MLXSW_REG(rmft2), 12742 MLXSW_REG(reiv), 12743 MLXSW_REG(mfcr), 12744 MLXSW_REG(mfsc), 12745 MLXSW_REG(mfsm), 12746 MLXSW_REG(mfsl), 12747 MLXSW_REG(fore), 12748 MLXSW_REG(mtcap), 12749 MLXSW_REG(mtmp), 12750 MLXSW_REG(mtwe), 12751 MLXSW_REG(mtbr), 12752 MLXSW_REG(mcia), 12753 MLXSW_REG(mpat), 12754 MLXSW_REG(mpar), 12755 MLXSW_REG(mgir), 12756 MLXSW_REG(mrsr), 12757 MLXSW_REG(mlcr), 12758 MLXSW_REG(mcion), 12759 MLXSW_REG(mtpps), 12760 MLXSW_REG(mtutc), 12761 MLXSW_REG(mpsc), 12762 MLXSW_REG(mcqi), 12763 MLXSW_REG(mcc), 12764 MLXSW_REG(mcda), 12765 MLXSW_REG(mgpc), 12766 MLXSW_REG(mprs), 12767 MLXSW_REG(mogcr), 12768 MLXSW_REG(mpagr), 12769 MLXSW_REG(momte), 12770 MLXSW_REG(mtpppc), 12771 MLXSW_REG(mtpptr), 12772 MLXSW_REG(mtptpt), 12773 MLXSW_REG(mfgd), 12774 MLXSW_REG(mgpir), 12775 MLXSW_REG(mbct), 12776 MLXSW_REG(mddq), 12777 MLXSW_REG(mddc), 12778 MLXSW_REG(mfde), 12779 MLXSW_REG(tngcr), 12780 MLXSW_REG(tnumt), 12781 MLXSW_REG(tnqcr), 12782 MLXSW_REG(tnqdr), 12783 MLXSW_REG(tneem), 12784 MLXSW_REG(tndem), 12785 MLXSW_REG(tnpc), 12786 MLXSW_REG(tigcr), 12787 MLXSW_REG(tieem), 12788 MLXSW_REG(tidem), 12789 MLXSW_REG(sbpr), 12790 MLXSW_REG(sbcm), 12791 MLXSW_REG(sbpm), 12792 MLXSW_REG(sbmm), 12793 MLXSW_REG(sbsr), 12794 MLXSW_REG(sbib), 12795 }; 12796 12797 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12798 { 12799 const struct mlxsw_reg_info *reg_info; 12800 int i; 12801 12802 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12803 reg_info = mlxsw_reg_infos[i]; 12804 if (reg_info->id == reg_id) 12805 return reg_info->name; 12806 } 12807 return "*UNKNOWN*"; 12808 } 12809 12810 /* PUDE - Port Up / Down Event 12811 * --------------------------- 12812 * Reports the operational state change of a port. 12813 */ 12814 #define MLXSW_REG_PUDE_LEN 0x10 12815 12816 /* reg_pude_swid 12817 * Switch partition ID with which to associate the port. 12818 * Access: Index 12819 */ 12820 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12821 12822 /* reg_pude_local_port 12823 * Local port number. 12824 * Access: Index 12825 */ 12826 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12827 12828 /* reg_pude_admin_status 12829 * Port administrative state (the desired state). 12830 * 1 - Up. 12831 * 2 - Down. 12832 * 3 - Up once. This means that in case of link failure, the port won't go 12833 * into polling mode, but will wait to be re-enabled by software. 12834 * 4 - Disabled by system. Can only be set by hardware. 12835 * Access: RO 12836 */ 12837 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12838 12839 /* reg_pude_oper_status 12840 * Port operatioanl state. 12841 * 1 - Up. 12842 * 2 - Down. 12843 * 3 - Down by port failure. This means that the device will not let the 12844 * port up again until explicitly specified by software. 12845 * Access: RO 12846 */ 12847 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12848 12849 #endif 12850