1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #ifndef _MLXSW_REG_H
5 #define _MLXSW_REG_H
6 
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
11 
12 #include "item.h"
13 #include "port.h"
14 
15 struct mlxsw_reg_info {
16 	u16 id;
17 	u16 len; /* In u8 */
18 	const char *name;
19 };
20 
21 #define MLXSW_REG_DEFINE(_name, _id, _len)				\
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = {		\
23 	.id = _id,							\
24 	.len = _len,							\
25 	.name = #_name,							\
26 }
27 
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31 
32 /* SGCR - Switch General Configuration Register
33  * --------------------------------------------
34  * This register is used for configuration of the switch capabilities.
35  */
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
38 
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40 
41 /* reg_sgcr_llb
42  * Link Local Broadcast (Default=0)
43  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44  * packets and ignore the IGMP snooping entries.
45  * Access: RW
46  */
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48 
49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50 {
51 	MLXSW_REG_ZERO(sgcr, payload);
52 	mlxsw_reg_sgcr_llb_set(payload, !!llb);
53 }
54 
55 /* SPAD - Switch Physical Address Register
56  * ---------------------------------------
57  * The SPAD register configures the switch physical MAC address.
58  */
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
61 
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63 
64 /* reg_spad_base_mac
65  * Base MAC address for the switch partitions.
66  * Per switch partition MAC address is equal to:
67  * base_mac + swid
68  * Access: RW
69  */
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71 
72 /* SMID - Switch Multicast ID
73  * --------------------------
74  * The MID record maps from a MID (Multicast ID), which is a unique identifier
75  * of the multicast group within the stacking domain, into a list of local
76  * ports into which the packet is replicated.
77  */
78 #define MLXSW_REG_SMID_ID 0x2007
79 #define MLXSW_REG_SMID_LEN 0x240
80 
81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
82 
83 /* reg_smid_swid
84  * Switch partition ID.
85  * Access: Index
86  */
87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
88 
89 /* reg_smid_mid
90  * Multicast identifier - global identifier that represents the multicast group
91  * across all devices.
92  * Access: Index
93  */
94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
95 
96 /* reg_smid_port
97  * Local port memebership (1 bit per port).
98  * Access: RW
99  */
100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
101 
102 /* reg_smid_port_mask
103  * Local port mask (1 bit per port).
104  * Access: W
105  */
106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
107 
108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
109 				       u8 port, bool set)
110 {
111 	MLXSW_REG_ZERO(smid, payload);
112 	mlxsw_reg_smid_swid_set(payload, 0);
113 	mlxsw_reg_smid_mid_set(payload, mid);
114 	mlxsw_reg_smid_port_set(payload, port, set);
115 	mlxsw_reg_smid_port_mask_set(payload, port, 1);
116 }
117 
118 /* SSPR - Switch System Port Record Register
119  * -----------------------------------------
120  * Configures the system port to local port mapping.
121  */
122 #define MLXSW_REG_SSPR_ID 0x2008
123 #define MLXSW_REG_SSPR_LEN 0x8
124 
125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
126 
127 /* reg_sspr_m
128  * Master - if set, then the record describes the master system port.
129  * This is needed in case a local port is mapped into several system ports
130  * (for multipathing). That number will be reported as the source system
131  * port when packets are forwarded to the CPU. Only one master port is allowed
132  * per local port.
133  *
134  * Note: Must be set for Spectrum.
135  * Access: RW
136  */
137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
138 
139 /* reg_sspr_local_port
140  * Local port number.
141  *
142  * Access: RW
143  */
144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
145 
146 /* reg_sspr_sub_port
147  * Virtual port within the physical port.
148  * Should be set to 0 when virtual ports are not enabled on the port.
149  *
150  * Access: RW
151  */
152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
153 
154 /* reg_sspr_system_port
155  * Unique identifier within the stacking domain that represents all the ports
156  * that are available in the system (external ports).
157  *
158  * Currently, only single-ASIC configurations are supported, so we default to
159  * 1:1 mapping between system ports and local ports.
160  * Access: Index
161  */
162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163 
164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
165 {
166 	MLXSW_REG_ZERO(sspr, payload);
167 	mlxsw_reg_sspr_m_set(payload, 1);
168 	mlxsw_reg_sspr_local_port_set(payload, local_port);
169 	mlxsw_reg_sspr_sub_port_set(payload, 0);
170 	mlxsw_reg_sspr_system_port_set(payload, local_port);
171 }
172 
173 /* SFDAT - Switch Filtering Database Aging Time
174  * --------------------------------------------
175  * Controls the Switch aging time. Aging time is able to be set per Switch
176  * Partition.
177  */
178 #define MLXSW_REG_SFDAT_ID 0x2009
179 #define MLXSW_REG_SFDAT_LEN 0x8
180 
181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
182 
183 /* reg_sfdat_swid
184  * Switch partition ID.
185  * Access: Index
186  */
187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
188 
189 /* reg_sfdat_age_time
190  * Aging time in seconds
191  * Min - 10 seconds
192  * Max - 1,000,000 seconds
193  * Default is 300 seconds.
194  * Access: RW
195  */
196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
197 
198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
199 {
200 	MLXSW_REG_ZERO(sfdat, payload);
201 	mlxsw_reg_sfdat_swid_set(payload, 0);
202 	mlxsw_reg_sfdat_age_time_set(payload, age_time);
203 }
204 
205 /* SFD - Switch Filtering Database
206  * -------------------------------
207  * The following register defines the access to the filtering database.
208  * The register supports querying, adding, removing and modifying the database.
209  * The access is optimized for bulk updates in which case more than one
210  * FDB record is present in the same command.
211  */
212 #define MLXSW_REG_SFD_ID 0x200A
213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +	\
217 			   MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
218 
219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
220 
221 /* reg_sfd_swid
222  * Switch partition ID for queries. Reserved on Write.
223  * Access: Index
224  */
225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
226 
227 enum mlxsw_reg_sfd_op {
228 	/* Dump entire FDB a (process according to record_locator) */
229 	MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230 	/* Query records by {MAC, VID/FID} value */
231 	MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232 	/* Query and clear activity. Query records by {MAC, VID/FID} value */
233 	MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234 	/* Test. Response indicates if each of the records could be
235 	 * added to the FDB.
236 	 */
237 	MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238 	/* Add/modify. Aged-out records cannot be added. This command removes
239 	 * the learning notification of the {MAC, VID/FID}. Response includes
240 	 * the entries that were added to the FDB.
241 	 */
242 	MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243 	/* Remove record by {MAC, VID/FID}. This command also removes
244 	 * the learning notification and aged-out notifications
245 	 * of the {MAC, VID/FID}. The response provides current (pre-removal)
246 	 * entries as non-aged-out.
247 	 */
248 	MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249 	/* Remove learned notification by {MAC, VID/FID}. The response provides
250 	 * the removed learning notification.
251 	 */
252 	MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
253 };
254 
255 /* reg_sfd_op
256  * Operation.
257  * Access: OP
258  */
259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
260 
261 /* reg_sfd_record_locator
262  * Used for querying the FDB. Use record_locator=0 to initiate the
263  * query. When a record is returned, a new record_locator is
264  * returned to be used in the subsequent query.
265  * Reserved for database update.
266  * Access: Index
267  */
268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
269 
270 /* reg_sfd_num_rec
271  * Request: Number of records to read/add/modify/remove
272  * Response: Number of records read/added/replaced/removed
273  * See above description for more details.
274  * Ranges 0..64
275  * Access: RW
276  */
277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
278 
279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
280 				      u32 record_locator)
281 {
282 	MLXSW_REG_ZERO(sfd, payload);
283 	mlxsw_reg_sfd_op_set(payload, op);
284 	mlxsw_reg_sfd_record_locator_set(payload, record_locator);
285 }
286 
287 /* reg_sfd_rec_swid
288  * Switch partition ID.
289  * Access: Index
290  */
291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
293 
294 enum mlxsw_reg_sfd_rec_type {
295 	MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 	MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 	MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 	MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
299 };
300 
301 /* reg_sfd_rec_type
302  * FDB record type.
303  * Access: RW
304  */
305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
307 
308 enum mlxsw_reg_sfd_rec_policy {
309 	/* Replacement disabled, aging disabled. */
310 	MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311 	/* (mlag remote): Replacement enabled, aging disabled,
312 	 * learning notification enabled on this port.
313 	 */
314 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315 	/* (ingress device): Replacement enabled, aging enabled. */
316 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
317 };
318 
319 /* reg_sfd_rec_policy
320  * Policy.
321  * Access: RW
322  */
323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
325 
326 /* reg_sfd_rec_a
327  * Activity. Set for new static entries. Set for static entries if a frame SMAC
328  * lookup hits on the entry.
329  * To clear the a bit, use "query and clear activity" op.
330  * Access: RO
331  */
332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
334 
335 /* reg_sfd_rec_mac
336  * MAC address.
337  * Access: Index
338  */
339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 		       MLXSW_REG_SFD_REC_LEN, 0x02);
341 
342 enum mlxsw_reg_sfd_rec_action {
343 	/* forward */
344 	MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345 	/* forward and trap, trap_id is FDB_TRAP */
346 	MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347 	/* trap and do not forward, trap_id is FDB_TRAP */
348 	MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349 	/* forward to IP router */
350 	MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 	MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
352 };
353 
354 /* reg_sfd_rec_action
355  * Action to apply on the packet.
356  * Note: Dynamic entries can only be configured with NOP action.
357  * Access: RW
358  */
359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
361 
362 /* reg_sfd_uc_sub_port
363  * VEPA channel on local port.
364  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
365  * VEPA is not enabled.
366  * Access: RW
367  */
368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
370 
371 /* reg_sfd_uc_fid_vid
372  * Filtering ID or VLAN ID
373  * For SwitchX and SwitchX-2:
374  * - Dynamic entries (policy 2,3) use FID
375  * - Static entries (policy 0) use VID
376  * - When independent learning is configured, VID=FID
377  * For Spectrum: use FID for both Dynamic and Static entries.
378  * VID should not be used.
379  * Access: Index
380  */
381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
383 
384 /* reg_sfd_uc_system_port
385  * Unique port identifier for the final destination of the packet.
386  * Access: RW
387  */
388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
390 
391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 					  enum mlxsw_reg_sfd_rec_type rec_type,
393 					  const char *mac,
394 					  enum mlxsw_reg_sfd_rec_action action)
395 {
396 	u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
397 
398 	if (rec_index >= num_rec)
399 		mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 	mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 	mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 	mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 	mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404 }
405 
406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 					 enum mlxsw_reg_sfd_rec_policy policy,
408 					 const char *mac, u16 fid_vid,
409 					 enum mlxsw_reg_sfd_rec_action action,
410 					 u8 local_port)
411 {
412 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 			       MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 	mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 	mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 	mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418 }
419 
420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 					   char *mac, u16 *p_fid_vid,
422 					   u8 *p_local_port)
423 {
424 	mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 	*p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 	*p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
427 }
428 
429 /* reg_sfd_uc_lag_sub_port
430  * LAG sub port.
431  * Must be 0 if multichannel VEPA is not enabled.
432  * Access: RW
433  */
434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
436 
437 /* reg_sfd_uc_lag_fid_vid
438  * Filtering ID or VLAN ID
439  * For SwitchX and SwitchX-2:
440  * - Dynamic entries (policy 2,3) use FID
441  * - Static entries (policy 0) use VID
442  * - When independent learning is configured, VID=FID
443  * For Spectrum: use FID for both Dynamic and Static entries.
444  * VID should not be used.
445  * Access: Index
446  */
447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
449 
450 /* reg_sfd_uc_lag_lag_vid
451  * Indicates VID in case of vFIDs. Reserved for FIDs.
452  * Access: RW
453  */
454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
456 
457 /* reg_sfd_uc_lag_lag_id
458  * LAG Identifier - pointer into the LAG descriptor table.
459  * Access: RW
460  */
461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
463 
464 static inline void
465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 			  enum mlxsw_reg_sfd_rec_policy policy,
467 			  const char *mac, u16 fid_vid,
468 			  enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
469 			  u16 lag_id)
470 {
471 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
473 			       mac, action);
474 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 	mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 	mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 	mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 	mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
479 }
480 
481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 					       char *mac, u16 *p_vid,
483 					       u16 *p_lag_id)
484 {
485 	mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 	*p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 	*p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
488 }
489 
490 /* reg_sfd_mc_pgi
491  *
492  * Multicast port group index - index into the port group table.
493  * Value 0x1FFF indicates the pgi should point to the MID entry.
494  * For Spectrum this value must be set to 0x1FFF
495  * Access: RW
496  */
497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
499 
500 /* reg_sfd_mc_fid_vid
501  *
502  * Filtering ID or VLAN ID
503  * Access: Index
504  */
505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
507 
508 /* reg_sfd_mc_mid
509  *
510  * Multicast identifier - global identifier that represents the multicast
511  * group across all devices.
512  * Access: RW
513  */
514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
516 
517 static inline void
518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 		      const char *mac, u16 fid_vid,
520 		      enum mlxsw_reg_sfd_rec_action action, u16 mid)
521 {
522 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 			       MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 	mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 	mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 	mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
527 }
528 
529 /* reg_sfd_uc_tunnel_uip_msb
530  * When protocol is IPv4, the most significant byte of the underlay IPv4
531  * destination IP.
532  * When protocol is IPv6, reserved.
533  * Access: RW
534  */
535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 		     8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
537 
538 /* reg_sfd_uc_tunnel_fid
539  * Filtering ID.
540  * Access: Index
541  */
542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
544 
545 enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
548 };
549 
550 /* reg_sfd_uc_tunnel_protocol
551  * IP protocol.
552  * Access: RW
553  */
554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 		     1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
556 
557 /* reg_sfd_uc_tunnel_uip_lsb
558  * When protocol is IPv4, the least significant bytes of the underlay
559  * IPv4 destination IP.
560  * When protocol is IPv6, pointer to the underlay IPv6 destination IP
561  * which is configured by RIPS.
562  * Access: RW
563  */
564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 		     24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
566 
567 static inline void
568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 			     enum mlxsw_reg_sfd_rec_policy policy,
570 			     const char *mac, u16 fid,
571 			     enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 			     enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
573 {
574 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
576 			       action);
577 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 	mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 	mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 	mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
582 }
583 
584 /* SFN - Switch FDB Notification Register
585  * -------------------------------------------
586  * The switch provides notifications on newly learned FDB entries and
587  * aged out entries. The notifications can be polled by software.
588  */
589 #define MLXSW_REG_SFN_ID 0x200B
590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +	\
594 			   MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
595 
596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
597 
598 /* reg_sfn_swid
599  * Switch partition ID.
600  * Access: Index
601  */
602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
603 
604 /* reg_sfn_end
605  * Forces the current session to end.
606  * Access: OP
607  */
608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
609 
610 /* reg_sfn_num_rec
611  * Request: Number of learned notifications and aged-out notification
612  * records requested.
613  * Response: Number of notification records returned (must be smaller
614  * than or equal to the value requested)
615  * Ranges 0..64
616  * Access: OP
617  */
618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
619 
620 static inline void mlxsw_reg_sfn_pack(char *payload)
621 {
622 	MLXSW_REG_ZERO(sfn, payload);
623 	mlxsw_reg_sfn_swid_set(payload, 0);
624 	mlxsw_reg_sfn_end_set(payload, 1);
625 	mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
626 }
627 
628 /* reg_sfn_rec_swid
629  * Switch partition ID.
630  * Access: RO
631  */
632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
633 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
634 
635 enum mlxsw_reg_sfn_rec_type {
636 	/* MAC addresses learned on a regular port. */
637 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
638 	/* MAC addresses learned on a LAG port. */
639 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
640 	/* Aged-out MAC address on a regular port. */
641 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
642 	/* Aged-out MAC address on a LAG port. */
643 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
644 	/* Learned unicast tunnel record. */
645 	MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
646 	/* Aged-out unicast tunnel record. */
647 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
648 };
649 
650 /* reg_sfn_rec_type
651  * Notification record type.
652  * Access: RO
653  */
654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
655 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
656 
657 /* reg_sfn_rec_mac
658  * MAC address.
659  * Access: RO
660  */
661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
662 		       MLXSW_REG_SFN_REC_LEN, 0x02);
663 
664 /* reg_sfn_mac_sub_port
665  * VEPA channel on the local port.
666  * 0 if multichannel VEPA is not enabled.
667  * Access: RO
668  */
669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
670 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
671 
672 /* reg_sfn_mac_fid
673  * Filtering identifier.
674  * Access: RO
675  */
676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
677 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
678 
679 /* reg_sfn_mac_system_port
680  * Unique port identifier for the final destination of the packet.
681  * Access: RO
682  */
683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
684 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
685 
686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
687 					    char *mac, u16 *p_vid,
688 					    u8 *p_local_port)
689 {
690 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
691 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
692 	*p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
693 }
694 
695 /* reg_sfn_mac_lag_lag_id
696  * LAG ID (pointer into the LAG descriptor table).
697  * Access: RO
698  */
699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
700 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
701 
702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
703 						char *mac, u16 *p_vid,
704 						u16 *p_lag_id)
705 {
706 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
707 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
708 	*p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
709 }
710 
711 /* reg_sfn_uc_tunnel_uip_msb
712  * When protocol is IPv4, the most significant byte of the underlay IPv4
713  * address of the remote VTEP.
714  * When protocol is IPv6, reserved.
715  * Access: RO
716  */
717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
718 		     8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
719 
720 enum mlxsw_reg_sfn_uc_tunnel_protocol {
721 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
722 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
723 };
724 
725 /* reg_sfn_uc_tunnel_protocol
726  * IP protocol.
727  * Access: RO
728  */
729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
730 		     1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
731 
732 /* reg_sfn_uc_tunnel_uip_lsb
733  * When protocol is IPv4, the least significant bytes of the underlay
734  * IPv4 address of the remote VTEP.
735  * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
736  * Access: RO
737  */
738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
739 		     24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
740 
741 enum mlxsw_reg_sfn_tunnel_port {
742 	MLXSW_REG_SFN_TUNNEL_PORT_NVE,
743 	MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
744 	MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
745 	MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
746 };
747 
748 /* reg_sfn_uc_tunnel_port
749  * Tunnel port.
750  * Reserved on Spectrum.
751  * Access: RO
752  */
753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
754 		     MLXSW_REG_SFN_REC_LEN, 0x10, false);
755 
756 static inline void
757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
758 			       u16 *p_fid, u32 *p_uip,
759 			       enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
760 {
761 	u32 uip_msb, uip_lsb;
762 
763 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
764 	*p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
765 	uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
766 	uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
767 	*p_uip = uip_msb << 24 | uip_lsb;
768 	*p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
769 }
770 
771 /* SPMS - Switch Port MSTP/RSTP State Register
772  * -------------------------------------------
773  * Configures the spanning tree state of a physical port.
774  */
775 #define MLXSW_REG_SPMS_ID 0x200D
776 #define MLXSW_REG_SPMS_LEN 0x404
777 
778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
779 
780 /* reg_spms_local_port
781  * Local port number.
782  * Access: Index
783  */
784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
785 
786 enum mlxsw_reg_spms_state {
787 	MLXSW_REG_SPMS_STATE_NO_CHANGE,
788 	MLXSW_REG_SPMS_STATE_DISCARDING,
789 	MLXSW_REG_SPMS_STATE_LEARNING,
790 	MLXSW_REG_SPMS_STATE_FORWARDING,
791 };
792 
793 /* reg_spms_state
794  * Spanning tree state of each VLAN ID (VID) of the local port.
795  * 0 - Do not change spanning tree state (used only when writing).
796  * 1 - Discarding. No learning or forwarding to/from this port (default).
797  * 2 - Learning. Port is learning, but not forwarding.
798  * 3 - Forwarding. Port is learning and forwarding.
799  * Access: RW
800  */
801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
802 
803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
804 {
805 	MLXSW_REG_ZERO(spms, payload);
806 	mlxsw_reg_spms_local_port_set(payload, local_port);
807 }
808 
809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
810 					   enum mlxsw_reg_spms_state state)
811 {
812 	mlxsw_reg_spms_state_set(payload, vid, state);
813 }
814 
815 /* SPVID - Switch Port VID
816  * -----------------------
817  * The switch port VID configures the default VID for a port.
818  */
819 #define MLXSW_REG_SPVID_ID 0x200E
820 #define MLXSW_REG_SPVID_LEN 0x08
821 
822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
823 
824 /* reg_spvid_local_port
825  * Local port number.
826  * Access: Index
827  */
828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
829 
830 /* reg_spvid_sub_port
831  * Virtual port within the physical port.
832  * Should be set to 0 when virtual ports are not enabled on the port.
833  * Access: Index
834  */
835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
836 
837 /* reg_spvid_pvid
838  * Port default VID
839  * Access: RW
840  */
841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
842 
843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
844 {
845 	MLXSW_REG_ZERO(spvid, payload);
846 	mlxsw_reg_spvid_local_port_set(payload, local_port);
847 	mlxsw_reg_spvid_pvid_set(payload, pvid);
848 }
849 
850 /* SPVM - Switch Port VLAN Membership
851  * ----------------------------------
852  * The Switch Port VLAN Membership register configures the VLAN membership
853  * of a port in a VLAN denoted by VID. VLAN membership is managed per
854  * virtual port. The register can be used to add and remove VID(s) from a port.
855  */
856 #define MLXSW_REG_SPVM_ID 0x200F
857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +	\
861 		    MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
862 
863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
864 
865 /* reg_spvm_pt
866  * Priority tagged. If this bit is set, packets forwarded to the port with
867  * untagged VLAN membership (u bit is set) will be tagged with priority tag
868  * (VID=0)
869  * Access: RW
870  */
871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
872 
873 /* reg_spvm_pte
874  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
875  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
876  * Access: WO
877  */
878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
879 
880 /* reg_spvm_local_port
881  * Local port number.
882  * Access: Index
883  */
884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
885 
886 /* reg_spvm_sub_port
887  * Virtual port within the physical port.
888  * Should be set to 0 when virtual ports are not enabled on the port.
889  * Access: Index
890  */
891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
892 
893 /* reg_spvm_num_rec
894  * Number of records to update. Each record contains: i, e, u, vid.
895  * Access: OP
896  */
897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
898 
899 /* reg_spvm_rec_i
900  * Ingress membership in VLAN ID.
901  * Access: Index
902  */
903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
904 		     MLXSW_REG_SPVM_BASE_LEN, 14, 1,
905 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
906 
907 /* reg_spvm_rec_e
908  * Egress membership in VLAN ID.
909  * Access: Index
910  */
911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
912 		     MLXSW_REG_SPVM_BASE_LEN, 13, 1,
913 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
914 
915 /* reg_spvm_rec_u
916  * Untagged - port is an untagged member - egress transmission uses untagged
917  * frames on VID<n>
918  * Access: Index
919  */
920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
921 		     MLXSW_REG_SPVM_BASE_LEN, 12, 1,
922 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
923 
924 /* reg_spvm_rec_vid
925  * Egress membership in VLAN ID.
926  * Access: Index
927  */
928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
929 		     MLXSW_REG_SPVM_BASE_LEN, 0, 12,
930 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
931 
932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
933 				       u16 vid_begin, u16 vid_end,
934 				       bool is_member, bool untagged)
935 {
936 	int size = vid_end - vid_begin + 1;
937 	int i;
938 
939 	MLXSW_REG_ZERO(spvm, payload);
940 	mlxsw_reg_spvm_local_port_set(payload, local_port);
941 	mlxsw_reg_spvm_num_rec_set(payload, size);
942 
943 	for (i = 0; i < size; i++) {
944 		mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
945 		mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
946 		mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
947 		mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
948 	}
949 }
950 
951 /* SPAFT - Switch Port Acceptable Frame Types
952  * ------------------------------------------
953  * The Switch Port Acceptable Frame Types register configures the frame
954  * admittance of the port.
955  */
956 #define MLXSW_REG_SPAFT_ID 0x2010
957 #define MLXSW_REG_SPAFT_LEN 0x08
958 
959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
960 
961 /* reg_spaft_local_port
962  * Local port number.
963  * Access: Index
964  *
965  * Note: CPU port is not supported (all tag types are allowed).
966  */
967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
968 
969 /* reg_spaft_sub_port
970  * Virtual port within the physical port.
971  * Should be set to 0 when virtual ports are not enabled on the port.
972  * Access: RW
973  */
974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
975 
976 /* reg_spaft_allow_untagged
977  * When set, untagged frames on the ingress are allowed (default).
978  * Access: RW
979  */
980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
981 
982 /* reg_spaft_allow_prio_tagged
983  * When set, priority tagged frames on the ingress are allowed (default).
984  * Access: RW
985  */
986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
987 
988 /* reg_spaft_allow_tagged
989  * When set, tagged frames on the ingress are allowed (default).
990  * Access: RW
991  */
992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
993 
994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
995 					bool allow_untagged)
996 {
997 	MLXSW_REG_ZERO(spaft, payload);
998 	mlxsw_reg_spaft_local_port_set(payload, local_port);
999 	mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000 	mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1001 	mlxsw_reg_spaft_allow_tagged_set(payload, true);
1002 }
1003 
1004 /* SFGC - Switch Flooding Group Configuration
1005  * ------------------------------------------
1006  * The following register controls the association of flooding tables and MIDs
1007  * to packet types used for flooding.
1008  */
1009 #define MLXSW_REG_SFGC_ID 0x2011
1010 #define MLXSW_REG_SFGC_LEN 0x10
1011 
1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1013 
1014 enum mlxsw_reg_sfgc_type {
1015 	MLXSW_REG_SFGC_TYPE_BROADCAST,
1016 	MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019 	MLXSW_REG_SFGC_TYPE_RESERVED,
1020 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021 	MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022 	MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023 	MLXSW_REG_SFGC_TYPE_MAX,
1024 };
1025 
1026 /* reg_sfgc_type
1027  * The traffic type to reach the flooding table.
1028  * Access: Index
1029  */
1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1031 
1032 enum mlxsw_reg_sfgc_bridge_type {
1033 	MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034 	MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1035 };
1036 
1037 /* reg_sfgc_bridge_type
1038  * Access: Index
1039  *
1040  * Note: SwitchX-2 only supports 802.1Q mode.
1041  */
1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1043 
1044 enum mlxsw_flood_table_type {
1045 	MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046 	MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047 	MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048 	MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049 	MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1050 };
1051 
1052 /* reg_sfgc_table_type
1053  * See mlxsw_flood_table_type
1054  * Access: RW
1055  *
1056  * Note: FID offset and FID types are not supported in SwitchX-2.
1057  */
1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1059 
1060 /* reg_sfgc_flood_table
1061  * Flooding table index to associate with the specific type on the specific
1062  * switch partition.
1063  * Access: RW
1064  */
1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1066 
1067 /* reg_sfgc_mid
1068  * The multicast ID for the swid. Not supported for Spectrum
1069  * Access: RW
1070  */
1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1072 
1073 /* reg_sfgc_counter_set_type
1074  * Counter Set Type for flow counters.
1075  * Access: RW
1076  */
1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1078 
1079 /* reg_sfgc_counter_index
1080  * Counter Index for flow counters.
1081  * Access: RW
1082  */
1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1084 
1085 static inline void
1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087 		    enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088 		    enum mlxsw_flood_table_type table_type,
1089 		    unsigned int flood_table)
1090 {
1091 	MLXSW_REG_ZERO(sfgc, payload);
1092 	mlxsw_reg_sfgc_type_set(payload, type);
1093 	mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094 	mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095 	mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096 	mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1097 }
1098 
1099 /* SFTR - Switch Flooding Table Register
1100  * -------------------------------------
1101  * The switch flooding table is used for flooding packet replication. The table
1102  * defines a bit mask of ports for packet replication.
1103  */
1104 #define MLXSW_REG_SFTR_ID 0x2012
1105 #define MLXSW_REG_SFTR_LEN 0x420
1106 
1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1108 
1109 /* reg_sftr_swid
1110  * Switch partition ID with which to associate the port.
1111  * Access: Index
1112  */
1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1114 
1115 /* reg_sftr_flood_table
1116  * Flooding table index to associate with the specific type on the specific
1117  * switch partition.
1118  * Access: Index
1119  */
1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1121 
1122 /* reg_sftr_index
1123  * Index. Used as an index into the Flooding Table in case the table is
1124  * configured to use VID / FID or FID Offset.
1125  * Access: Index
1126  */
1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1128 
1129 /* reg_sftr_table_type
1130  * See mlxsw_flood_table_type
1131  * Access: RW
1132  */
1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1134 
1135 /* reg_sftr_range
1136  * Range of entries to update
1137  * Access: Index
1138  */
1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1140 
1141 /* reg_sftr_port
1142  * Local port membership (1 bit per port).
1143  * Access: RW
1144  */
1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1146 
1147 /* reg_sftr_cpu_port_mask
1148  * CPU port mask (1 bit per port).
1149  * Access: W
1150  */
1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1152 
1153 static inline void mlxsw_reg_sftr_pack(char *payload,
1154 				       unsigned int flood_table,
1155 				       unsigned int index,
1156 				       enum mlxsw_flood_table_type table_type,
1157 				       unsigned int range, u8 port, bool set)
1158 {
1159 	MLXSW_REG_ZERO(sftr, payload);
1160 	mlxsw_reg_sftr_swid_set(payload, 0);
1161 	mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162 	mlxsw_reg_sftr_index_set(payload, index);
1163 	mlxsw_reg_sftr_table_type_set(payload, table_type);
1164 	mlxsw_reg_sftr_range_set(payload, range);
1165 	mlxsw_reg_sftr_port_set(payload, port, set);
1166 	mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1167 }
1168 
1169 /* SFDF - Switch Filtering DB Flush
1170  * --------------------------------
1171  * The switch filtering DB flush register is used to flush the FDB.
1172  * Note that FDB notifications are flushed as well.
1173  */
1174 #define MLXSW_REG_SFDF_ID 0x2013
1175 #define MLXSW_REG_SFDF_LEN 0x14
1176 
1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1178 
1179 /* reg_sfdf_swid
1180  * Switch partition ID.
1181  * Access: Index
1182  */
1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1184 
1185 enum mlxsw_reg_sfdf_flush_type {
1186 	MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187 	MLXSW_REG_SFDF_FLUSH_PER_FID,
1188 	MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189 	MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190 	MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191 	MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192 	MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193 	MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1194 };
1195 
1196 /* reg_sfdf_flush_type
1197  * Flush type.
1198  * 0 - All SWID dynamic entries are flushed.
1199  * 1 - All FID dynamic entries are flushed.
1200  * 2 - All dynamic entries pointing to port are flushed.
1201  * 3 - All FID dynamic entries pointing to port are flushed.
1202  * 4 - All dynamic entries pointing to LAG are flushed.
1203  * 5 - All FID dynamic entries pointing to LAG are flushed.
1204  * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1205  *     flushed.
1206  * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1207  *     flushed, per FID.
1208  * Access: RW
1209  */
1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1211 
1212 /* reg_sfdf_flush_static
1213  * Static.
1214  * 0 - Flush only dynamic entries.
1215  * 1 - Flush both dynamic and static entries.
1216  * Access: RW
1217  */
1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1219 
1220 static inline void mlxsw_reg_sfdf_pack(char *payload,
1221 				       enum mlxsw_reg_sfdf_flush_type type)
1222 {
1223 	MLXSW_REG_ZERO(sfdf, payload);
1224 	mlxsw_reg_sfdf_flush_type_set(payload, type);
1225 	mlxsw_reg_sfdf_flush_static_set(payload, true);
1226 }
1227 
1228 /* reg_sfdf_fid
1229  * FID to flush.
1230  * Access: RW
1231  */
1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1233 
1234 /* reg_sfdf_system_port
1235  * Port to flush.
1236  * Access: RW
1237  */
1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1239 
1240 /* reg_sfdf_port_fid_system_port
1241  * Port to flush, pointed to by FID.
1242  * Access: RW
1243  */
1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1245 
1246 /* reg_sfdf_lag_id
1247  * LAG ID to flush.
1248  * Access: RW
1249  */
1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1251 
1252 /* reg_sfdf_lag_fid_lag_id
1253  * LAG ID to flush, pointed to by FID.
1254  * Access: RW
1255  */
1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1257 
1258 /* SLDR - Switch LAG Descriptor Register
1259  * -----------------------------------------
1260  * The switch LAG descriptor register is populated by LAG descriptors.
1261  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1262  * max_lag-1.
1263  */
1264 #define MLXSW_REG_SLDR_ID 0x2014
1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1266 
1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1268 
1269 enum mlxsw_reg_sldr_op {
1270 	/* Indicates a creation of a new LAG-ID, lag_id must be valid */
1271 	MLXSW_REG_SLDR_OP_LAG_CREATE,
1272 	MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273 	/* Ports that appear in the list have the Distributor enabled */
1274 	MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275 	/* Removes ports from the disributor list */
1276 	MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1277 };
1278 
1279 /* reg_sldr_op
1280  * Operation.
1281  * Access: RW
1282  */
1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1284 
1285 /* reg_sldr_lag_id
1286  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1287  * Access: Index
1288  */
1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1290 
1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1292 {
1293 	MLXSW_REG_ZERO(sldr, payload);
1294 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1296 }
1297 
1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1299 {
1300 	MLXSW_REG_ZERO(sldr, payload);
1301 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1303 }
1304 
1305 /* reg_sldr_num_ports
1306  * The number of member ports of the LAG.
1307  * Reserved for Create / Destroy operations
1308  * For Add / Remove operations - indicates the number of ports in the list.
1309  * Access: RW
1310  */
1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1312 
1313 /* reg_sldr_system_port
1314  * System port.
1315  * Access: RW
1316  */
1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1318 
1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1320 						    u8 local_port)
1321 {
1322 	MLXSW_REG_ZERO(sldr, payload);
1323 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1326 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1327 }
1328 
1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1330 						       u8 local_port)
1331 {
1332 	MLXSW_REG_ZERO(sldr, payload);
1333 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1336 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1337 }
1338 
1339 /* SLCR - Switch LAG Configuration 2 Register
1340  * -------------------------------------------
1341  * The Switch LAG Configuration register is used for configuring the
1342  * LAG properties of the switch.
1343  */
1344 #define MLXSW_REG_SLCR_ID 0x2015
1345 #define MLXSW_REG_SLCR_LEN 0x10
1346 
1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1348 
1349 enum mlxsw_reg_slcr_pp {
1350 	/* Global Configuration (for all ports) */
1351 	MLXSW_REG_SLCR_PP_GLOBAL,
1352 	/* Per port configuration, based on local_port field */
1353 	MLXSW_REG_SLCR_PP_PER_PORT,
1354 };
1355 
1356 /* reg_slcr_pp
1357  * Per Port Configuration
1358  * Note: Reading at Global mode results in reading port 1 configuration.
1359  * Access: Index
1360  */
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1362 
1363 /* reg_slcr_local_port
1364  * Local port number
1365  * Supported from CPU port
1366  * Not supported from router port
1367  * Reserved when pp = Global Configuration
1368  * Access: Index
1369  */
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1371 
1372 enum mlxsw_reg_slcr_type {
1373 	MLXSW_REG_SLCR_TYPE_CRC, /* default */
1374 	MLXSW_REG_SLCR_TYPE_XOR,
1375 	MLXSW_REG_SLCR_TYPE_RANDOM,
1376 };
1377 
1378 /* reg_slcr_type
1379  * Hash type
1380  * Access: RW
1381  */
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1383 
1384 /* Ingress port */
1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT		BIT(0)
1386 /* SMAC - for IPv4 and IPv6 packets */
1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP		BIT(1)
1388 /* SMAC - for non-IP packets */
1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP	BIT(2)
1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391 	(MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392 	 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393 /* DMAC - for IPv4 and IPv6 packets */
1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP		BIT(3)
1395 /* DMAC - for non-IP packets */
1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP	BIT(4)
1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398 	(MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399 	 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400 /* Ethertype - for IPv4 and IPv6 packets */
1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP	BIT(5)
1402 /* Ethertype - for non-IP packets */
1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP	BIT(6)
1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405 	(MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406 	 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407 /* VLAN ID - for IPv4 and IPv6 packets */
1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP	BIT(7)
1409 /* VLAN ID - for non-IP packets */
1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP	BIT(8)
1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412 	(MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413 	 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414 /* Source IP address (can be IPv4 or IPv6) */
1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP		BIT(9)
1416 /* Destination IP address (can be IPv4 or IPv6) */
1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP		BIT(10)
1418 /* TCP/UDP source port */
1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT		BIT(11)
1420 /* TCP/UDP destination port*/
1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT		BIT(12)
1422 /* IPv4 Protocol/IPv6 Next Header */
1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO		BIT(13)
1424 /* IPv6 Flow label */
1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL	BIT(14)
1426 /* SID - FCoE source ID */
1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID	BIT(15)
1428 /* DID - FCoE destination ID */
1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID	BIT(16)
1430 /* OXID - FCoE originator exchange ID */
1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID	BIT(17)
1432 /* Destination QP number - for RoCE packets */
1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP	BIT(19)
1434 
1435 /* reg_slcr_lag_hash
1436  * LAG hashing configuration. This is a bitmask, in which each set
1437  * bit includes the corresponding item in the LAG hash calculation.
1438  * The default lag_hash contains SMAC, DMAC, VLANID and
1439  * Ethertype (for all packet types).
1440  * Access: RW
1441  */
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1443 
1444 /* reg_slcr_seed
1445  * LAG seed value. The seed is the same for all ports.
1446  * Access: RW
1447  */
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1449 
1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1451 {
1452 	MLXSW_REG_ZERO(slcr, payload);
1453 	mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454 	mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455 	mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456 	mlxsw_reg_slcr_seed_set(payload, seed);
1457 }
1458 
1459 /* SLCOR - Switch LAG Collector Register
1460  * -------------------------------------
1461  * The Switch LAG Collector register controls the Local Port membership
1462  * in a LAG and enablement of the collector.
1463  */
1464 #define MLXSW_REG_SLCOR_ID 0x2016
1465 #define MLXSW_REG_SLCOR_LEN 0x10
1466 
1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1468 
1469 enum mlxsw_reg_slcor_col {
1470 	/* Port is added with collector disabled */
1471 	MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474 	MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1475 };
1476 
1477 /* reg_slcor_col
1478  * Collector configuration
1479  * Access: RW
1480  */
1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1482 
1483 /* reg_slcor_local_port
1484  * Local port number
1485  * Not supported for CPU port
1486  * Access: Index
1487  */
1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1489 
1490 /* reg_slcor_lag_id
1491  * LAG Identifier. Index into the LAG descriptor table.
1492  * Access: Index
1493  */
1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1495 
1496 /* reg_slcor_port_index
1497  * Port index in the LAG list. Only valid on Add Port to LAG col.
1498  * Valid range is from 0 to cap_max_lag_members-1
1499  * Access: RW
1500  */
1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1502 
1503 static inline void mlxsw_reg_slcor_pack(char *payload,
1504 					u8 local_port, u16 lag_id,
1505 					enum mlxsw_reg_slcor_col col)
1506 {
1507 	MLXSW_REG_ZERO(slcor, payload);
1508 	mlxsw_reg_slcor_col_set(payload, col);
1509 	mlxsw_reg_slcor_local_port_set(payload, local_port);
1510 	mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1511 }
1512 
1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514 						 u8 local_port, u16 lag_id,
1515 						 u8 port_index)
1516 {
1517 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518 			     MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519 	mlxsw_reg_slcor_port_index_set(payload, port_index);
1520 }
1521 
1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523 						    u8 local_port, u16 lag_id)
1524 {
1525 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526 			     MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1527 }
1528 
1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530 						   u8 local_port, u16 lag_id)
1531 {
1532 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1534 }
1535 
1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537 						    u8 local_port, u16 lag_id)
1538 {
1539 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1541 }
1542 
1543 /* SPMLR - Switch Port MAC Learning Register
1544  * -----------------------------------------
1545  * Controls the Switch MAC learning policy per port.
1546  */
1547 #define MLXSW_REG_SPMLR_ID 0x2018
1548 #define MLXSW_REG_SPMLR_LEN 0x8
1549 
1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1551 
1552 /* reg_spmlr_local_port
1553  * Local port number.
1554  * Access: Index
1555  */
1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1557 
1558 /* reg_spmlr_sub_port
1559  * Virtual port within the physical port.
1560  * Should be set to 0 when virtual ports are not enabled on the port.
1561  * Access: Index
1562  */
1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1564 
1565 enum mlxsw_reg_spmlr_learn_mode {
1566 	MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567 	MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568 	MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1569 };
1570 
1571 /* reg_spmlr_learn_mode
1572  * Learning mode on the port.
1573  * 0 - Learning disabled.
1574  * 2 - Learning enabled.
1575  * 3 - Security mode.
1576  *
1577  * In security mode the switch does not learn MACs on the port, but uses the
1578  * SMAC to see if it exists on another ingress port. If so, the packet is
1579  * classified as a bad packet and is discarded unless the software registers
1580  * to receive port security error packets usign HPKT.
1581  */
1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1583 
1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585 					enum mlxsw_reg_spmlr_learn_mode mode)
1586 {
1587 	MLXSW_REG_ZERO(spmlr, payload);
1588 	mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589 	mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590 	mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1591 }
1592 
1593 /* SVFA - Switch VID to FID Allocation Register
1594  * --------------------------------------------
1595  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1596  * virtualized ports.
1597  */
1598 #define MLXSW_REG_SVFA_ID 0x201C
1599 #define MLXSW_REG_SVFA_LEN 0x10
1600 
1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1602 
1603 /* reg_svfa_swid
1604  * Switch partition ID.
1605  * Access: Index
1606  */
1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1608 
1609 /* reg_svfa_local_port
1610  * Local port number.
1611  * Access: Index
1612  *
1613  * Note: Reserved for 802.1Q FIDs.
1614  */
1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1616 
1617 enum mlxsw_reg_svfa_mt {
1618 	MLXSW_REG_SVFA_MT_VID_TO_FID,
1619 	MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1620 };
1621 
1622 /* reg_svfa_mapping_table
1623  * Mapping table:
1624  * 0 - VID to FID
1625  * 1 - {Port, VID} to FID
1626  * Access: Index
1627  *
1628  * Note: Reserved for SwitchX-2.
1629  */
1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1631 
1632 /* reg_svfa_v
1633  * Valid.
1634  * Valid if set.
1635  * Access: RW
1636  *
1637  * Note: Reserved for SwitchX-2.
1638  */
1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1640 
1641 /* reg_svfa_fid
1642  * Filtering ID.
1643  * Access: RW
1644  */
1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1646 
1647 /* reg_svfa_vid
1648  * VLAN ID.
1649  * Access: Index
1650  */
1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1652 
1653 /* reg_svfa_counter_set_type
1654  * Counter set type for flow counters.
1655  * Access: RW
1656  *
1657  * Note: Reserved for SwitchX-2.
1658  */
1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1660 
1661 /* reg_svfa_counter_index
1662  * Counter index for flow counters.
1663  * Access: RW
1664  *
1665  * Note: Reserved for SwitchX-2.
1666  */
1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1668 
1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670 				       enum mlxsw_reg_svfa_mt mt, bool valid,
1671 				       u16 fid, u16 vid)
1672 {
1673 	MLXSW_REG_ZERO(svfa, payload);
1674 	local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675 	mlxsw_reg_svfa_swid_set(payload, 0);
1676 	mlxsw_reg_svfa_local_port_set(payload, local_port);
1677 	mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678 	mlxsw_reg_svfa_v_set(payload, valid);
1679 	mlxsw_reg_svfa_fid_set(payload, fid);
1680 	mlxsw_reg_svfa_vid_set(payload, vid);
1681 }
1682 
1683 /* SVPE - Switch Virtual-Port Enabling Register
1684  * --------------------------------------------
1685  * Enables port virtualization.
1686  */
1687 #define MLXSW_REG_SVPE_ID 0x201E
1688 #define MLXSW_REG_SVPE_LEN 0x4
1689 
1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1691 
1692 /* reg_svpe_local_port
1693  * Local port number
1694  * Access: Index
1695  *
1696  * Note: CPU port is not supported (uses VLAN mode only).
1697  */
1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1699 
1700 /* reg_svpe_vp_en
1701  * Virtual port enable.
1702  * 0 - Disable, VLAN mode (VID to FID).
1703  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1704  * Access: RW
1705  */
1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1707 
1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1709 				       bool enable)
1710 {
1711 	MLXSW_REG_ZERO(svpe, payload);
1712 	mlxsw_reg_svpe_local_port_set(payload, local_port);
1713 	mlxsw_reg_svpe_vp_en_set(payload, enable);
1714 }
1715 
1716 /* SFMR - Switch FID Management Register
1717  * -------------------------------------
1718  * Creates and configures FIDs.
1719  */
1720 #define MLXSW_REG_SFMR_ID 0x201F
1721 #define MLXSW_REG_SFMR_LEN 0x18
1722 
1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1724 
1725 enum mlxsw_reg_sfmr_op {
1726 	MLXSW_REG_SFMR_OP_CREATE_FID,
1727 	MLXSW_REG_SFMR_OP_DESTROY_FID,
1728 };
1729 
1730 /* reg_sfmr_op
1731  * Operation.
1732  * 0 - Create or edit FID.
1733  * 1 - Destroy FID.
1734  * Access: WO
1735  */
1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1737 
1738 /* reg_sfmr_fid
1739  * Filtering ID.
1740  * Access: Index
1741  */
1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1743 
1744 /* reg_sfmr_fid_offset
1745  * FID offset.
1746  * Used to point into the flooding table selected by SFGC register if
1747  * the table is of type FID-Offset. Otherwise, this field is reserved.
1748  * Access: RW
1749  */
1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1751 
1752 /* reg_sfmr_vtfp
1753  * Valid Tunnel Flood Pointer.
1754  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1755  * Access: RW
1756  *
1757  * Note: Reserved for 802.1Q FIDs.
1758  */
1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1760 
1761 /* reg_sfmr_nve_tunnel_flood_ptr
1762  * Underlay Flooding and BC Pointer.
1763  * Used as a pointer to the first entry of the group based link lists of
1764  * flooding or BC entries (for NVE tunnels).
1765  * Access: RW
1766  */
1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1768 
1769 /* reg_sfmr_vv
1770  * VNI Valid.
1771  * If not set, then vni is reserved.
1772  * Access: RW
1773  *
1774  * Note: Reserved for 802.1Q FIDs.
1775  */
1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1777 
1778 /* reg_sfmr_vni
1779  * Virtual Network Identifier.
1780  * Access: RW
1781  *
1782  * Note: A given VNI can only be assigned to one FID.
1783  */
1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1785 
1786 static inline void mlxsw_reg_sfmr_pack(char *payload,
1787 				       enum mlxsw_reg_sfmr_op op, u16 fid,
1788 				       u16 fid_offset)
1789 {
1790 	MLXSW_REG_ZERO(sfmr, payload);
1791 	mlxsw_reg_sfmr_op_set(payload, op);
1792 	mlxsw_reg_sfmr_fid_set(payload, fid);
1793 	mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794 	mlxsw_reg_sfmr_vtfp_set(payload, false);
1795 	mlxsw_reg_sfmr_vv_set(payload, false);
1796 }
1797 
1798 /* SPVMLR - Switch Port VLAN MAC Learning Register
1799  * -----------------------------------------------
1800  * Controls the switch MAC learning policy per {Port, VID}.
1801  */
1802 #define MLXSW_REG_SPVMLR_ID 0x2020
1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807 			      MLXSW_REG_SPVMLR_REC_LEN * \
1808 			      MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1809 
1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1811 
1812 /* reg_spvmlr_local_port
1813  * Local ingress port.
1814  * Access: Index
1815  *
1816  * Note: CPU port is not supported.
1817  */
1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1819 
1820 /* reg_spvmlr_num_rec
1821  * Number of records to update.
1822  * Access: OP
1823  */
1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1825 
1826 /* reg_spvmlr_rec_learn_enable
1827  * 0 - Disable learning for {Port, VID}.
1828  * 1 - Enable learning for {Port, VID}.
1829  * Access: RW
1830  */
1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832 		     31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1833 
1834 /* reg_spvmlr_rec_vid
1835  * VLAN ID to be added/removed from port or for querying.
1836  * Access: Index
1837  */
1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839 		     MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1840 
1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842 					 u16 vid_begin, u16 vid_end,
1843 					 bool learn_enable)
1844 {
1845 	int num_rec = vid_end - vid_begin + 1;
1846 	int i;
1847 
1848 	WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1849 
1850 	MLXSW_REG_ZERO(spvmlr, payload);
1851 	mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852 	mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1853 
1854 	for (i = 0; i < num_rec; i++) {
1855 		mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856 		mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1857 	}
1858 }
1859 
1860 /* CWTP - Congetion WRED ECN TClass Profile
1861  * ----------------------------------------
1862  * Configures the profiles for queues of egress port and traffic class
1863  */
1864 #define MLXSW_REG_CWTP_ID 0x2802
1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867 #define MLXSW_REG_CWTP_LEN 0x40
1868 
1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1870 
1871 /* reg_cwtp_local_port
1872  * Local port number
1873  * Not supported for CPU port
1874  * Access: Index
1875  */
1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1877 
1878 /* reg_cwtp_traffic_class
1879  * Traffic Class to configure
1880  * Access: Index
1881  */
1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1883 
1884 /* reg_cwtp_profile_min
1885  * Minimum Average Queue Size of the profile in cells.
1886  * Access: RW
1887  */
1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1890 
1891 /* reg_cwtp_profile_percent
1892  * Percentage of WRED and ECN marking for maximum Average Queue size
1893  * Range is 0 to 100, units of integer percentage
1894  * Access: RW
1895  */
1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897 		     24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1898 
1899 /* reg_cwtp_profile_max
1900  * Maximum Average Queue size of the profile in cells
1901  * Access: RW
1902  */
1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1905 
1906 #define MLXSW_REG_CWTP_MIN_VALUE 64
1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1909 
1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1911 				       u8 traffic_class)
1912 {
1913 	int i;
1914 
1915 	MLXSW_REG_ZERO(cwtp, payload);
1916 	mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917 	mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1918 
1919 	for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920 		mlxsw_reg_cwtp_profile_min_set(payload, i,
1921 					       MLXSW_REG_CWTP_MIN_VALUE);
1922 		mlxsw_reg_cwtp_profile_max_set(payload, i,
1923 					       MLXSW_REG_CWTP_MIN_VALUE);
1924 	}
1925 }
1926 
1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1928 
1929 static inline void
1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1931 			    u32 probability)
1932 {
1933 	u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1934 
1935 	mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936 	mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937 	mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1938 }
1939 
1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1941  * ---------------------------------------------------
1942  * The CWTPM register maps each egress port and traffic class to profile num.
1943  */
1944 #define MLXSW_REG_CWTPM_ID 0x2803
1945 #define MLXSW_REG_CWTPM_LEN 0x44
1946 
1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1948 
1949 /* reg_cwtpm_local_port
1950  * Local port number
1951  * Not supported for CPU port
1952  * Access: Index
1953  */
1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1955 
1956 /* reg_cwtpm_traffic_class
1957  * Traffic Class to configure
1958  * Access: Index
1959  */
1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1961 
1962 /* reg_cwtpm_ew
1963  * Control enablement of WRED for traffic class:
1964  * 0 - Disable
1965  * 1 - Enable
1966  * Access: RW
1967  */
1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1969 
1970 /* reg_cwtpm_ee
1971  * Control enablement of ECN for traffic class:
1972  * 0 - Disable
1973  * 1 - Enable
1974  * Access: RW
1975  */
1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1977 
1978 /* reg_cwtpm_tcp_g
1979  * TCP Green Profile.
1980  * Index of the profile within {port, traffic class} to use.
1981  * 0 for disabling both WRED and ECN for this type of traffic.
1982  * Access: RW
1983  */
1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1985 
1986 /* reg_cwtpm_tcp_y
1987  * TCP Yellow Profile.
1988  * Index of the profile within {port, traffic class} to use.
1989  * 0 for disabling both WRED and ECN for this type of traffic.
1990  * Access: RW
1991  */
1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1993 
1994 /* reg_cwtpm_tcp_r
1995  * TCP Red Profile.
1996  * Index of the profile within {port, traffic class} to use.
1997  * 0 for disabling both WRED and ECN for this type of traffic.
1998  * Access: RW
1999  */
2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2001 
2002 /* reg_cwtpm_ntcp_g
2003  * Non-TCP Green Profile.
2004  * Index of the profile within {port, traffic class} to use.
2005  * 0 for disabling both WRED and ECN for this type of traffic.
2006  * Access: RW
2007  */
2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2009 
2010 /* reg_cwtpm_ntcp_y
2011  * Non-TCP Yellow Profile.
2012  * Index of the profile within {port, traffic class} to use.
2013  * 0 for disabling both WRED and ECN for this type of traffic.
2014  * Access: RW
2015  */
2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2017 
2018 /* reg_cwtpm_ntcp_r
2019  * Non-TCP Red Profile.
2020  * Index of the profile within {port, traffic class} to use.
2021  * 0 for disabling both WRED and ECN for this type of traffic.
2022  * Access: RW
2023  */
2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2025 
2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2027 
2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029 					u8 traffic_class, u8 profile,
2030 					bool wred, bool ecn)
2031 {
2032 	MLXSW_REG_ZERO(cwtpm, payload);
2033 	mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034 	mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035 	mlxsw_reg_cwtpm_ew_set(payload, wred);
2036 	mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037 	mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038 	mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039 	mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040 	mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041 	mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042 	mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2043 }
2044 
2045 /* PGCR - Policy-Engine General Configuration Register
2046  * ---------------------------------------------------
2047  * This register configures general Policy-Engine settings.
2048  */
2049 #define MLXSW_REG_PGCR_ID 0x3001
2050 #define MLXSW_REG_PGCR_LEN 0x20
2051 
2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2053 
2054 /* reg_pgcr_default_action_pointer_base
2055  * Default action pointer base. Each region has a default action pointer
2056  * which is equal to default_action_pointer_base + region_id.
2057  * Access: RW
2058  */
2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2060 
2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2062 {
2063 	MLXSW_REG_ZERO(pgcr, payload);
2064 	mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2065 }
2066 
2067 /* PPBT - Policy-Engine Port Binding Table
2068  * ---------------------------------------
2069  * This register is used for configuration of the Port Binding Table.
2070  */
2071 #define MLXSW_REG_PPBT_ID 0x3002
2072 #define MLXSW_REG_PPBT_LEN 0x14
2073 
2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2075 
2076 enum mlxsw_reg_pxbt_e {
2077 	MLXSW_REG_PXBT_E_IACL,
2078 	MLXSW_REG_PXBT_E_EACL,
2079 };
2080 
2081 /* reg_ppbt_e
2082  * Access: Index
2083  */
2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2085 
2086 enum mlxsw_reg_pxbt_op {
2087 	MLXSW_REG_PXBT_OP_BIND,
2088 	MLXSW_REG_PXBT_OP_UNBIND,
2089 };
2090 
2091 /* reg_ppbt_op
2092  * Access: RW
2093  */
2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2095 
2096 /* reg_ppbt_local_port
2097  * Local port. Not including CPU port.
2098  * Access: Index
2099  */
2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2101 
2102 /* reg_ppbt_g
2103  * group - When set, the binding is of an ACL group. When cleared,
2104  * the binding is of an ACL.
2105  * Must be set to 1 for Spectrum.
2106  * Access: RW
2107  */
2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2109 
2110 /* reg_ppbt_acl_info
2111  * ACL/ACL group identifier. If the g bit is set, this field should hold
2112  * the acl_group_id, else it should hold the acl_id.
2113  * Access: RW
2114  */
2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2116 
2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118 				       enum mlxsw_reg_pxbt_op op,
2119 				       u8 local_port, u16 acl_info)
2120 {
2121 	MLXSW_REG_ZERO(ppbt, payload);
2122 	mlxsw_reg_ppbt_e_set(payload, e);
2123 	mlxsw_reg_ppbt_op_set(payload, op);
2124 	mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125 	mlxsw_reg_ppbt_g_set(payload, true);
2126 	mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2127 }
2128 
2129 /* PACL - Policy-Engine ACL Register
2130  * ---------------------------------
2131  * This register is used for configuration of the ACL.
2132  */
2133 #define MLXSW_REG_PACL_ID 0x3004
2134 #define MLXSW_REG_PACL_LEN 0x70
2135 
2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2137 
2138 /* reg_pacl_v
2139  * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2140  * while the ACL is bounded to either a port, VLAN or ACL rule.
2141  * Access: RW
2142  */
2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2144 
2145 /* reg_pacl_acl_id
2146  * An identifier representing the ACL (managed by software)
2147  * Range 0 .. cap_max_acl_regions - 1
2148  * Access: Index
2149  */
2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2151 
2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2153 
2154 /* reg_pacl_tcam_region_info
2155  * Opaque object that represents a TCAM region.
2156  * Obtained through PTAR register.
2157  * Access: RW
2158  */
2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2161 
2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163 				       bool valid, const char *tcam_region_info)
2164 {
2165 	MLXSW_REG_ZERO(pacl, payload);
2166 	mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167 	mlxsw_reg_pacl_v_set(payload, valid);
2168 	mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2169 }
2170 
2171 /* PAGT - Policy-Engine ACL Group Table
2172  * ------------------------------------
2173  * This register is used for configuration of the ACL Group Table.
2174  */
2175 #define MLXSW_REG_PAGT_ID 0x3005
2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2177 #define MLXSW_REG_PAGT_ACL_LEN 4
2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180 		MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2181 
2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2183 
2184 /* reg_pagt_size
2185  * Number of ACLs in the group.
2186  * Size 0 invalidates a group.
2187  * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2188  * Total number of ACLs in all groups must be lower or equal
2189  * to cap_max_acl_tot_groups
2190  * Note: a group which is binded must not be invalidated
2191  * Access: Index
2192  */
2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2194 
2195 /* reg_pagt_acl_group_id
2196  * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2197  * the ACL Group identifier (managed by software).
2198  * Access: Index
2199  */
2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2201 
2202 /* reg_pagt_multi
2203  * Multi-ACL
2204  * 0 - This ACL is the last ACL in the multi-ACL
2205  * 1 - This ACL is part of a multi-ACL
2206  * Access: RW
2207  */
2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2209 
2210 /* reg_pagt_acl_id
2211  * ACL identifier
2212  * Access: RW
2213  */
2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2215 
2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2217 {
2218 	MLXSW_REG_ZERO(pagt, payload);
2219 	mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2220 }
2221 
2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223 					      u16 acl_id, bool multi)
2224 {
2225 	u8 size = mlxsw_reg_pagt_size_get(payload);
2226 
2227 	if (index >= size)
2228 		mlxsw_reg_pagt_size_set(payload, index + 1);
2229 	mlxsw_reg_pagt_multi_set(payload, index, multi);
2230 	mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2231 }
2232 
2233 /* PTAR - Policy-Engine TCAM Allocation Register
2234  * ---------------------------------------------
2235  * This register is used for allocation of regions in the TCAM.
2236  * Note: Query method is not supported on this register.
2237  */
2238 #define MLXSW_REG_PTAR_ID 0x3006
2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243 		MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2244 
2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2246 
2247 enum mlxsw_reg_ptar_op {
2248 	/* allocate a TCAM region */
2249 	MLXSW_REG_PTAR_OP_ALLOC,
2250 	/* resize a TCAM region */
2251 	MLXSW_REG_PTAR_OP_RESIZE,
2252 	/* deallocate TCAM region */
2253 	MLXSW_REG_PTAR_OP_FREE,
2254 	/* test allocation */
2255 	MLXSW_REG_PTAR_OP_TEST,
2256 };
2257 
2258 /* reg_ptar_op
2259  * Access: OP
2260  */
2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2262 
2263 /* reg_ptar_action_set_type
2264  * Type of action set to be used on this region.
2265  * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2266  * Access: WO
2267  */
2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2269 
2270 enum mlxsw_reg_ptar_key_type {
2271 	MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2272 	MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2273 };
2274 
2275 /* reg_ptar_key_type
2276  * TCAM key type for the region.
2277  * Access: WO
2278  */
2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2280 
2281 /* reg_ptar_region_size
2282  * TCAM region size. When allocating/resizing this is the requested size,
2283  * the response is the actual size. Note that actual size may be
2284  * larger than requested.
2285  * Allowed range 1 .. cap_max_rules-1
2286  * Reserved during op deallocate.
2287  * Access: WO
2288  */
2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2290 
2291 /* reg_ptar_region_id
2292  * Region identifier
2293  * Range 0 .. cap_max_regions-1
2294  * Access: Index
2295  */
2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2297 
2298 /* reg_ptar_tcam_region_info
2299  * Opaque object that represents the TCAM region.
2300  * Returned when allocating a region.
2301  * Provided by software for ACL generation and region deallocation and resize.
2302  * Access: RW
2303  */
2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2306 
2307 /* reg_ptar_flexible_key_id
2308  * Identifier of the Flexible Key.
2309  * Only valid if key_type == "FLEX_KEY"
2310  * The key size will be rounded up to one of the following values:
2311  * 9B, 18B, 36B, 54B.
2312  * This field is reserved for in resize operation.
2313  * Access: WO
2314  */
2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316 		    MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2317 
2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319 				       enum mlxsw_reg_ptar_key_type key_type,
2320 				       u16 region_size, u16 region_id,
2321 				       const char *tcam_region_info)
2322 {
2323 	MLXSW_REG_ZERO(ptar, payload);
2324 	mlxsw_reg_ptar_op_set(payload, op);
2325 	mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2326 	mlxsw_reg_ptar_key_type_set(payload, key_type);
2327 	mlxsw_reg_ptar_region_size_set(payload, region_size);
2328 	mlxsw_reg_ptar_region_id_set(payload, region_id);
2329 	mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2330 }
2331 
2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2333 					      u16 key_id)
2334 {
2335 	mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2336 }
2337 
2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2339 {
2340 	mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2341 }
2342 
2343 /* PPBS - Policy-Engine Policy Based Switching Register
2344  * ----------------------------------------------------
2345  * This register retrieves and sets Policy Based Switching Table entries.
2346  */
2347 #define MLXSW_REG_PPBS_ID 0x300C
2348 #define MLXSW_REG_PPBS_LEN 0x14
2349 
2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2351 
2352 /* reg_ppbs_pbs_ptr
2353  * Index into the PBS table.
2354  * For Spectrum, the index points to the KVD Linear.
2355  * Access: Index
2356  */
2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2358 
2359 /* reg_ppbs_system_port
2360  * Unique port identifier for the final destination of the packet.
2361  * Access: RW
2362  */
2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2364 
2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2366 				       u16 system_port)
2367 {
2368 	MLXSW_REG_ZERO(ppbs, payload);
2369 	mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370 	mlxsw_reg_ppbs_system_port_set(payload, system_port);
2371 }
2372 
2373 /* PRCR - Policy-Engine Rules Copy Register
2374  * ----------------------------------------
2375  * This register is used for accessing rules within a TCAM region.
2376  */
2377 #define MLXSW_REG_PRCR_ID 0x300D
2378 #define MLXSW_REG_PRCR_LEN 0x40
2379 
2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2381 
2382 enum mlxsw_reg_prcr_op {
2383 	/* Move rules. Moves the rules from "tcam_region_info" starting
2384 	 * at offset "offset" to "dest_tcam_region_info"
2385 	 * at offset "dest_offset."
2386 	 */
2387 	MLXSW_REG_PRCR_OP_MOVE,
2388 	/* Copy rules. Copies the rules from "tcam_region_info" starting
2389 	 * at offset "offset" to "dest_tcam_region_info"
2390 	 * at offset "dest_offset."
2391 	 */
2392 	MLXSW_REG_PRCR_OP_COPY,
2393 };
2394 
2395 /* reg_prcr_op
2396  * Access: OP
2397  */
2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2399 
2400 /* reg_prcr_offset
2401  * Offset within the source region to copy/move from.
2402  * Access: Index
2403  */
2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2405 
2406 /* reg_prcr_size
2407  * The number of rules to copy/move.
2408  * Access: WO
2409  */
2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2411 
2412 /* reg_prcr_tcam_region_info
2413  * Opaque object that represents the source TCAM region.
2414  * Access: Index
2415  */
2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2418 
2419 /* reg_prcr_dest_offset
2420  * Offset within the source region to copy/move to.
2421  * Access: Index
2422  */
2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2424 
2425 /* reg_prcr_dest_tcam_region_info
2426  * Opaque object that represents the destination TCAM region.
2427  * Access: Index
2428  */
2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2431 
2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433 				       const char *src_tcam_region_info,
2434 				       u16 src_offset,
2435 				       const char *dest_tcam_region_info,
2436 				       u16 dest_offset, u16 size)
2437 {
2438 	MLXSW_REG_ZERO(prcr, payload);
2439 	mlxsw_reg_prcr_op_set(payload, op);
2440 	mlxsw_reg_prcr_offset_set(payload, src_offset);
2441 	mlxsw_reg_prcr_size_set(payload, size);
2442 	mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443 						  src_tcam_region_info);
2444 	mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445 	mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446 						       dest_tcam_region_info);
2447 }
2448 
2449 /* PEFA - Policy-Engine Extended Flexible Action Register
2450  * ------------------------------------------------------
2451  * This register is used for accessing an extended flexible action entry
2452  * in the central KVD Linear Database.
2453  */
2454 #define MLXSW_REG_PEFA_ID 0x300F
2455 #define MLXSW_REG_PEFA_LEN 0xB0
2456 
2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2458 
2459 /* reg_pefa_index
2460  * Index in the KVD Linear Centralized Database.
2461  * Access: Index
2462  */
2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2464 
2465 /* reg_pefa_a
2466  * Index in the KVD Linear Centralized Database.
2467  * Activity
2468  * For a new entry: set if ca=0, clear if ca=1
2469  * Set if a packet lookup has hit on the specific entry
2470  * Access: RO
2471  */
2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2473 
2474 /* reg_pefa_ca
2475  * Clear activity
2476  * When write: activity is according to this field
2477  * When read: after reading the activity is cleared according to ca
2478  * Access: OP
2479  */
2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2481 
2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2483 
2484 /* reg_pefa_flex_action_set
2485  * Action-set to perform when rule is matched.
2486  * Must be zero padded if action set is shorter.
2487  * Access: RW
2488  */
2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2490 
2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492 				       const char *flex_action_set)
2493 {
2494 	MLXSW_REG_ZERO(pefa, payload);
2495 	mlxsw_reg_pefa_index_set(payload, index);
2496 	mlxsw_reg_pefa_ca_set(payload, ca);
2497 	if (flex_action_set)
2498 		mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2499 							 flex_action_set);
2500 }
2501 
2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2503 {
2504 	*p_a = mlxsw_reg_pefa_a_get(payload);
2505 }
2506 
2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2508  * --------------------------------------------------------------
2509  * This register is used for binding Multicast router to an ACL group
2510  * that serves the MC router.
2511  * This register is not supported by SwitchX/-2 and Spectrum.
2512  */
2513 #define MLXSW_REG_PEMRBT_ID 0x3014
2514 #define MLXSW_REG_PEMRBT_LEN 0x14
2515 
2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2517 
2518 enum mlxsw_reg_pemrbt_protocol {
2519 	MLXSW_REG_PEMRBT_PROTO_IPV4,
2520 	MLXSW_REG_PEMRBT_PROTO_IPV6,
2521 };
2522 
2523 /* reg_pemrbt_protocol
2524  * Access: Index
2525  */
2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2527 
2528 /* reg_pemrbt_group_id
2529  * ACL group identifier.
2530  * Range 0..cap_max_acl_groups-1
2531  * Access: RW
2532  */
2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2534 
2535 static inline void
2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2537 		      u16 group_id)
2538 {
2539 	MLXSW_REG_ZERO(pemrbt, payload);
2540 	mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541 	mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2542 }
2543 
2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2545  * -----------------------------------------------------
2546  * This register is used for accessing rules within a TCAM region.
2547  * It is a new version of PTCE in order to support wider key,
2548  * mask and action within a TCAM region. This register is not supported
2549  * by SwitchX and SwitchX-2.
2550  */
2551 #define MLXSW_REG_PTCE2_ID 0x3017
2552 #define MLXSW_REG_PTCE2_LEN 0x1D8
2553 
2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2555 
2556 /* reg_ptce2_v
2557  * Valid.
2558  * Access: RW
2559  */
2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2561 
2562 /* reg_ptce2_a
2563  * Activity. Set if a packet lookup has hit on the specific entry.
2564  * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2565  * Access: RO
2566  */
2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2568 
2569 enum mlxsw_reg_ptce2_op {
2570 	/* Read operation. */
2571 	MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572 	/* clear on read operation. Used to read entry
2573 	 * and clear Activity bit.
2574 	 */
2575 	MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576 	/* Write operation. Used to write a new entry to the table.
2577 	 * All R/W fields are relevant for new entry. Activity bit is set
2578 	 * for new entries - Note write with v = 0 will delete the entry.
2579 	 */
2580 	MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581 	/* Update action. Only action set will be updated. */
2582 	MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583 	/* Clear activity. A bit is cleared for the entry. */
2584 	MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2585 };
2586 
2587 /* reg_ptce2_op
2588  * Access: OP
2589  */
2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2591 
2592 /* reg_ptce2_offset
2593  * Access: Index
2594  */
2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2596 
2597 /* reg_ptce2_priority
2598  * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2599  * Note: priority does not have to be unique per rule.
2600  * Within a region, higher priority should have lower offset (no limitation
2601  * between regions in a multi-region).
2602  * Access: RW
2603  */
2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2605 
2606 /* reg_ptce2_tcam_region_info
2607  * Opaque object that represents the TCAM region.
2608  * Access: Index
2609  */
2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2612 
2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2614 
2615 /* reg_ptce2_flex_key_blocks
2616  * ACL Key.
2617  * Access: RW
2618  */
2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2621 
2622 /* reg_ptce2_mask
2623  * mask- in the same size as key. A bit that is set directs the TCAM
2624  * to compare the corresponding bit in key. A bit that is clear directs
2625  * the TCAM to ignore the corresponding bit in key.
2626  * Access: RW
2627  */
2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2630 
2631 /* reg_ptce2_flex_action_set
2632  * ACL action set.
2633  * Access: RW
2634  */
2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
2637 
2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639 					enum mlxsw_reg_ptce2_op op,
2640 					const char *tcam_region_info,
2641 					u16 offset, u32 priority)
2642 {
2643 	MLXSW_REG_ZERO(ptce2, payload);
2644 	mlxsw_reg_ptce2_v_set(payload, valid);
2645 	mlxsw_reg_ptce2_op_set(payload, op);
2646 	mlxsw_reg_ptce2_offset_set(payload, offset);
2647 	mlxsw_reg_ptce2_priority_set(payload, priority);
2648 	mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2649 }
2650 
2651 /* PERPT - Policy-Engine ERP Table Register
2652  * ----------------------------------------
2653  * This register adds and removes eRPs from the eRP table.
2654  */
2655 #define MLXSW_REG_PERPT_ID 0x3021
2656 #define MLXSW_REG_PERPT_LEN 0x80
2657 
2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2659 
2660 /* reg_perpt_erpt_bank
2661  * eRP table bank.
2662  * Range 0 .. cap_max_erp_table_banks - 1
2663  * Access: Index
2664  */
2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2666 
2667 /* reg_perpt_erpt_index
2668  * Index to eRP table within the eRP bank.
2669  * Range is 0 .. cap_max_erp_table_bank_size - 1
2670  * Access: Index
2671  */
2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2673 
2674 enum mlxsw_reg_perpt_key_size {
2675 	MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676 	MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677 	MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678 	MLXSW_REG_PERPT_KEY_SIZE_12KB,
2679 };
2680 
2681 /* reg_perpt_key_size
2682  * Access: OP
2683  */
2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2685 
2686 /* reg_perpt_bf_bypass
2687  * 0 - The eRP is used only if bloom filter state is set for the given
2688  * rule.
2689  * 1 - The eRP is used regardless of bloom filter state.
2690  * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2691  * Access: RW
2692  */
2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2694 
2695 /* reg_perpt_erp_id
2696  * eRP ID for use by the rules.
2697  * Access: RW
2698  */
2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2700 
2701 /* reg_perpt_erpt_base_bank
2702  * Base eRP table bank, points to head of erp_vector
2703  * Range is 0 .. cap_max_erp_table_banks - 1
2704  * Access: OP
2705  */
2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2707 
2708 /* reg_perpt_erpt_base_index
2709  * Base index to eRP table within the eRP bank
2710  * Range is 0 .. cap_max_erp_table_bank_size - 1
2711  * Access: OP
2712  */
2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2714 
2715 /* reg_perpt_erp_index_in_vector
2716  * eRP index in the vector.
2717  * Access: OP
2718  */
2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2720 
2721 /* reg_perpt_erp_vector
2722  * eRP vector.
2723  * Access: OP
2724  */
2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2726 
2727 /* reg_perpt_mask
2728  * Mask
2729  * 0 - A-TCAM will ignore the bit in key
2730  * 1 - A-TCAM will compare the bit in key
2731  * Access: RW
2732  */
2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2734 
2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736 						   unsigned long *erp_vector,
2737 						   unsigned long size)
2738 {
2739 	unsigned long bit;
2740 
2741 	for_each_set_bit(bit, erp_vector, size)
2742 		mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2743 }
2744 
2745 static inline void
2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747 		     enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748 		     u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2749 		     char *mask)
2750 {
2751 	MLXSW_REG_ZERO(perpt, payload);
2752 	mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753 	mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754 	mlxsw_reg_perpt_key_size_set(payload, key_size);
2755 	mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756 	mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757 	mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758 	mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759 	mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760 	mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2761 }
2762 
2763 /* PERAR - Policy-Engine Region Association Register
2764  * -------------------------------------------------
2765  * This register associates a hw region for region_id's. Changing on the fly
2766  * is supported by the device.
2767  */
2768 #define MLXSW_REG_PERAR_ID 0x3026
2769 #define MLXSW_REG_PERAR_LEN 0x08
2770 
2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2772 
2773 /* reg_perar_region_id
2774  * Region identifier
2775  * Range 0 .. cap_max_regions-1
2776  * Access: Index
2777  */
2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2779 
2780 static inline unsigned int
2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2782 {
2783 	return DIV_ROUND_UP(block_num, 4);
2784 }
2785 
2786 /* reg_perar_hw_region
2787  * HW Region
2788  * Range 0 .. cap_max_regions-1
2789  * Default: hw_region = region_id
2790  * For a 8 key block region, 2 consecutive regions are used
2791  * For a 12 key block region, 3 consecutive regions are used
2792  * Access: RW
2793  */
2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2795 
2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2797 					u16 hw_region)
2798 {
2799 	MLXSW_REG_ZERO(perar, payload);
2800 	mlxsw_reg_perar_region_id_set(payload, region_id);
2801 	mlxsw_reg_perar_hw_region_set(payload, hw_region);
2802 }
2803 
2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2805  * -----------------------------------------------------
2806  * This register is a new version of PTCE-V2 in order to support the
2807  * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2808  */
2809 #define MLXSW_REG_PTCE3_ID 0x3027
2810 #define MLXSW_REG_PTCE3_LEN 0xF0
2811 
2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2813 
2814 /* reg_ptce3_v
2815  * Valid.
2816  * Access: RW
2817  */
2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2819 
2820 enum mlxsw_reg_ptce3_op {
2821 	/* Write operation. Used to write a new entry to the table.
2822 	 * All R/W fields are relevant for new entry. Activity bit is set
2823 	 * for new entries. Write with v = 0 will delete the entry. Must
2824 	 * not be used if an entry exists.
2825 	 */
2826 	 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827 	 /* Update operation */
2828 	 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829 	 /* Read operation */
2830 	 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2831 };
2832 
2833 /* reg_ptce3_op
2834  * Access: OP
2835  */
2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2837 
2838 /* reg_ptce3_priority
2839  * Priority of the rule. Higher values win.
2840  * For Spectrum-2 range is 1..cap_kvd_size - 1
2841  * Note: Priority does not have to be unique per rule.
2842  * Access: RW
2843  */
2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2845 
2846 /* reg_ptce3_tcam_region_info
2847  * Opaque object that represents the TCAM region.
2848  * Access: Index
2849  */
2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2852 
2853 /* reg_ptce3_flex2_key_blocks
2854  * ACL key. The key must be masked according to eRP (if exists) or
2855  * according to master mask.
2856  * Access: Index
2857  */
2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2860 
2861 /* reg_ptce3_erp_id
2862  * eRP ID.
2863  * Access: Index
2864  */
2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2866 
2867 /* reg_ptce3_delta_start
2868  * Start point of delta_value and delta_mask, in bits. Must not exceed
2869  * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2870  * Access: Index
2871  */
2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2873 
2874 /* reg_ptce3_delta_mask
2875  * Delta mask.
2876  * 0 - Ignore relevant bit in delta_value
2877  * 1 - Compare relevant bit in delta_value
2878  * Delta mask must not be set for reserved fields in the key blocks.
2879  * Note: No delta when no eRPs. Thus, for regions with
2880  * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2881  * Access: Index
2882  */
2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2884 
2885 /* reg_ptce3_delta_value
2886  * Delta value.
2887  * Bits which are masked by delta_mask must be 0.
2888  * Access: Index
2889  */
2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2891 
2892 /* reg_ptce3_prune_vector
2893  * Pruning vector relative to the PERPT.erp_id.
2894  * Used for reducing lookups.
2895  * 0 - NEED: Do a lookup using the eRP.
2896  * 1 - PRUNE: Do not perform a lookup using the eRP.
2897  * Maybe be modified by PEAPBL and PEAPBM.
2898  * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2899  * all 1's or all 0's.
2900  * Access: RW
2901  */
2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2903 
2904 /* reg_ptce3_prune_ctcam
2905  * Pruning on C-TCAM. Used for reducing lookups.
2906  * 0 - NEED: Do a lookup in the C-TCAM.
2907  * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2908  * Access: RW
2909  */
2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2911 
2912 /* reg_ptce3_large_exists
2913  * Large entry key ID exists.
2914  * Within the region:
2915  * 0 - SINGLE: The large_entry_key_id is not currently in use.
2916  * For rule insert: The MSB of the key (blocks 6..11) will be added.
2917  * For rule delete: The MSB of the key will be removed.
2918  * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2919  * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2920  * For rule delete: The MSB of the key will not be removed.
2921  * Access: WO
2922  */
2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2924 
2925 /* reg_ptce3_large_entry_key_id
2926  * Large entry key ID.
2927  * A key for 12 key blocks rules. Reserved when region has less than 12 key
2928  * blocks. Must be different for different keys which have the same common
2929  * 6 key blocks (MSB, blocks 6..11) key within a region.
2930  * Range is 0..cap_max_pe_large_key_id - 1
2931  * Access: RW
2932  */
2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2934 
2935 /* reg_ptce3_action_pointer
2936  * Pointer to action.
2937  * Range is 0..cap_max_kvd_action_sets - 1
2938  * Access: RW
2939  */
2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2941 
2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943 					enum mlxsw_reg_ptce3_op op,
2944 					u32 priority,
2945 					const char *tcam_region_info,
2946 					const char *key, u8 erp_id,
2947 					u16 delta_start, u8 delta_mask,
2948 					u8 delta_value, bool large_exists,
2949 					u32 lkey_id, u32 action_pointer)
2950 {
2951 	MLXSW_REG_ZERO(ptce3, payload);
2952 	mlxsw_reg_ptce3_v_set(payload, valid);
2953 	mlxsw_reg_ptce3_op_set(payload, op);
2954 	mlxsw_reg_ptce3_priority_set(payload, priority);
2955 	mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956 	mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957 	mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958 	mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959 	mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960 	mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961 	mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962 	mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963 	mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2964 }
2965 
2966 /* PERCR - Policy-Engine Region Configuration Register
2967  * ---------------------------------------------------
2968  * This register configures the region parameters. The region_id must be
2969  * allocated.
2970  */
2971 #define MLXSW_REG_PERCR_ID 0x302A
2972 #define MLXSW_REG_PERCR_LEN 0x80
2973 
2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2975 
2976 /* reg_percr_region_id
2977  * Region identifier.
2978  * Range 0..cap_max_regions-1
2979  * Access: Index
2980  */
2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2982 
2983 /* reg_percr_atcam_ignore_prune
2984  * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2985  * Access: RW
2986  */
2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2988 
2989 /* reg_percr_ctcam_ignore_prune
2990  * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2991  * Access: RW
2992  */
2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2994 
2995 /* reg_percr_bf_bypass
2996  * Bloom filter bypass.
2997  * 0 - Bloom filter is used (default)
2998  * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2999  * region_id or eRP. See PERPT.bf_bypass
3000  * Access: RW
3001  */
3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3003 
3004 /* reg_percr_master_mask
3005  * Master mask. Logical OR mask of all masks of all rules of a region
3006  * (both A-TCAM and C-TCAM). When there are no eRPs
3007  * (erpt_pointer_valid = 0), then this provides the mask.
3008  * Access: RW
3009  */
3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3011 
3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3013 {
3014 	MLXSW_REG_ZERO(percr, payload);
3015 	mlxsw_reg_percr_region_id_set(payload, region_id);
3016 	mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017 	mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018 	mlxsw_reg_percr_bf_bypass_set(payload, false);
3019 }
3020 
3021 /* PERERP - Policy-Engine Region eRP Register
3022  * ------------------------------------------
3023  * This register configures the region eRP. The region_id must be
3024  * allocated.
3025  */
3026 #define MLXSW_REG_PERERP_ID 0x302B
3027 #define MLXSW_REG_PERERP_LEN 0x1C
3028 
3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3030 
3031 /* reg_pererp_region_id
3032  * Region identifier.
3033  * Range 0..cap_max_regions-1
3034  * Access: Index
3035  */
3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3037 
3038 /* reg_pererp_ctcam_le
3039  * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3040  * Access: RW
3041  */
3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3043 
3044 /* reg_pererp_erpt_pointer_valid
3045  * erpt_pointer is valid.
3046  * Access: RW
3047  */
3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3049 
3050 /* reg_pererp_erpt_bank_pointer
3051  * Pointer to eRP table bank. May be modified at any time.
3052  * Range 0..cap_max_erp_table_banks-1
3053  * Reserved when erpt_pointer_valid = 0
3054  */
3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3056 
3057 /* reg_pererp_erpt_pointer
3058  * Pointer to eRP table within the eRP bank. Can be changed for an
3059  * existing region.
3060  * Range 0..cap_max_erp_table_size-1
3061  * Reserved when erpt_pointer_valid = 0
3062  * Access: RW
3063  */
3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3065 
3066 /* reg_pererp_erpt_vector
3067  * Vector of allowed eRP indexes starting from erpt_pointer within the
3068  * erpt_bank_pointer. Next entries will be in next bank.
3069  * Note that eRP index is used and not eRP ID.
3070  * Reserved when erpt_pointer_valid = 0
3071  * Access: RW
3072  */
3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3074 
3075 /* reg_pererp_master_rp_id
3076  * Master RP ID. When there are no eRPs, then this provides the eRP ID
3077  * for the lookup. Can be changed for an existing region.
3078  * Reserved when erpt_pointer_valid = 1
3079  * Access: RW
3080  */
3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3082 
3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084 						    unsigned long *erp_vector,
3085 						    unsigned long size)
3086 {
3087 	unsigned long bit;
3088 
3089 	for_each_set_bit(bit, erp_vector, size)
3090 		mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3091 }
3092 
3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094 					 bool ctcam_le, bool erpt_pointer_valid,
3095 					 u8 erpt_bank_pointer, u8 erpt_pointer,
3096 					 u8 master_rp_id)
3097 {
3098 	MLXSW_REG_ZERO(pererp, payload);
3099 	mlxsw_reg_pererp_region_id_set(payload, region_id);
3100 	mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101 	mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102 	mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103 	mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104 	mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3105 }
3106 
3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3108  * ----------------------------------------------------------------
3109  * This register configures the Bloom filter entries.
3110  */
3111 #define MLXSW_REG_PEABFE_ID 0x3022
3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116 			      MLXSW_REG_PEABFE_BF_REC_LEN * \
3117 			      MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3118 
3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3120 
3121 /* reg_peabfe_size
3122  * Number of BF entries to be updated.
3123  * Range 1..256
3124  * Access: Op
3125  */
3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3127 
3128 /* reg_peabfe_bf_entry_state
3129  * Bloom filter state
3130  * 0 - Clear
3131  * 1 - Set
3132  * Access: RW
3133  */
3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135 		     MLXSW_REG_PEABFE_BASE_LEN,	31, 1,
3136 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3137 
3138 /* reg_peabfe_bf_entry_bank
3139  * Bloom filter bank ID
3140  * Range 0..cap_max_erp_table_banks-1
3141  * Access: Index
3142  */
3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144 		     MLXSW_REG_PEABFE_BASE_LEN,	24, 4,
3145 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3146 
3147 /* reg_peabfe_bf_entry_index
3148  * Bloom filter entry index
3149  * Range 0..2^cap_max_bf_log-1
3150  * Access: Index
3151  */
3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153 		     MLXSW_REG_PEABFE_BASE_LEN,	0, 24,
3154 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3155 
3156 static inline void mlxsw_reg_peabfe_pack(char *payload)
3157 {
3158 	MLXSW_REG_ZERO(peabfe, payload);
3159 }
3160 
3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162 					     u8 state, u8 bank, u32 bf_index)
3163 {
3164 	u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3165 
3166 	if (rec_index >= num_rec)
3167 		mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168 	mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169 	mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170 	mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3171 }
3172 
3173 /* IEDR - Infrastructure Entry Delete Register
3174  * ----------------------------------------------------
3175  * This register is used for deleting entries from the entry tables.
3176  * It is legitimate to attempt to delete a nonexisting entry (the device will
3177  * respond as a good flow).
3178  */
3179 #define MLXSW_REG_IEDR_ID 0x3804
3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +	\
3184 			    MLXSW_REG_IEDR_REC_LEN *	\
3185 			    MLXSW_REG_IEDR_REC_MAX_COUNT)
3186 
3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3188 
3189 /* reg_iedr_num_rec
3190  * Number of records.
3191  * Access: OP
3192  */
3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3194 
3195 /* reg_iedr_rec_type
3196  * Resource type.
3197  * Access: OP
3198  */
3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3201 
3202 /* reg_iedr_rec_size
3203  * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3204  * Access: OP
3205  */
3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3208 
3209 /* reg_iedr_rec_index_start
3210  * Resource index start.
3211  * Access: OP
3212  */
3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214 		     MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3215 
3216 static inline void mlxsw_reg_iedr_pack(char *payload)
3217 {
3218 	MLXSW_REG_ZERO(iedr, payload);
3219 }
3220 
3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222 					   u8 rec_type, u16 rec_size,
3223 					   u32 rec_index_start)
3224 {
3225 	u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3226 
3227 	if (rec_index >= num_rec)
3228 		mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229 	mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230 	mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231 	mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3232 }
3233 
3234 /* QPTS - QoS Priority Trust State Register
3235  * ----------------------------------------
3236  * This register controls the port policy to calculate the switch priority and
3237  * packet color based on incoming packet fields.
3238  */
3239 #define MLXSW_REG_QPTS_ID 0x4002
3240 #define MLXSW_REG_QPTS_LEN 0x8
3241 
3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3243 
3244 /* reg_qpts_local_port
3245  * Local port number.
3246  * Access: Index
3247  *
3248  * Note: CPU port is supported.
3249  */
3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3251 
3252 enum mlxsw_reg_qpts_trust_state {
3253 	MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254 	MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3255 };
3256 
3257 /* reg_qpts_trust_state
3258  * Trust state for a given port.
3259  * Access: RW
3260  */
3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3262 
3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264 				       enum mlxsw_reg_qpts_trust_state ts)
3265 {
3266 	MLXSW_REG_ZERO(qpts, payload);
3267 
3268 	mlxsw_reg_qpts_local_port_set(payload, local_port);
3269 	mlxsw_reg_qpts_trust_state_set(payload, ts);
3270 }
3271 
3272 /* QPCR - QoS Policer Configuration Register
3273  * -----------------------------------------
3274  * The QPCR register is used to create policers - that limit
3275  * the rate of bytes or packets via some trap group.
3276  */
3277 #define MLXSW_REG_QPCR_ID 0x4004
3278 #define MLXSW_REG_QPCR_LEN 0x28
3279 
3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3281 
3282 enum mlxsw_reg_qpcr_g {
3283 	MLXSW_REG_QPCR_G_GLOBAL = 2,
3284 	MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3285 };
3286 
3287 /* reg_qpcr_g
3288  * The policer type.
3289  * Access: Index
3290  */
3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3292 
3293 /* reg_qpcr_pid
3294  * Policer ID.
3295  * Access: Index
3296  */
3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3298 
3299 /* reg_qpcr_color_aware
3300  * Is the policer aware of colors.
3301  * Must be 0 (unaware) for cpu port.
3302  * Access: RW for unbounded policer. RO for bounded policer.
3303  */
3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3305 
3306 /* reg_qpcr_bytes
3307  * Is policer limit is for bytes per sec or packets per sec.
3308  * 0 - packets
3309  * 1 - bytes
3310  * Access: RW for unbounded policer. RO for bounded policer.
3311  */
3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3313 
3314 enum mlxsw_reg_qpcr_ir_units {
3315 	MLXSW_REG_QPCR_IR_UNITS_M,
3316 	MLXSW_REG_QPCR_IR_UNITS_K,
3317 };
3318 
3319 /* reg_qpcr_ir_units
3320  * Policer's units for cir and eir fields (for bytes limits only)
3321  * 1 - 10^3
3322  * 0 - 10^6
3323  * Access: OP
3324  */
3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3326 
3327 enum mlxsw_reg_qpcr_rate_type {
3328 	MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329 	MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3330 };
3331 
3332 /* reg_qpcr_rate_type
3333  * Policer can have one limit (single rate) or 2 limits with specific operation
3334  * for packets that exceed the lower rate but not the upper one.
3335  * (For cpu port must be single rate)
3336  * Access: RW for unbounded policer. RO for bounded policer.
3337  */
3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3339 
3340 /* reg_qpc_cbs
3341  * Policer's committed burst size.
3342  * The policer is working with time slices of 50 nano sec. By default every
3343  * slice is granted the proportionate share of the committed rate. If we want to
3344  * allow a slice to exceed that share (while still keeping the rate per sec) we
3345  * can allow burst. The burst size is between the default proportionate share
3346  * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3347  * committed rate will result in exceeding the rate). The burst size must be a
3348  * log of 2 and will be determined by 2^cbs.
3349  * Access: RW
3350  */
3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3352 
3353 /* reg_qpcr_cir
3354  * Policer's committed rate.
3355  * The rate used for sungle rate, the lower rate for double rate.
3356  * For bytes limits, the rate will be this value * the unit from ir_units.
3357  * (Resolution error is up to 1%).
3358  * Access: RW
3359  */
3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3361 
3362 /* reg_qpcr_eir
3363  * Policer's exceed rate.
3364  * The higher rate for double rate, reserved for single rate.
3365  * Lower rate for double rate policer.
3366  * For bytes limits, the rate will be this value * the unit from ir_units.
3367  * (Resolution error is up to 1%).
3368  * Access: RW
3369  */
3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3371 
3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3373 
3374 /* reg_qpcr_exceed_action.
3375  * What to do with packets between the 2 limits for double rate.
3376  * Access: RW for unbounded policer. RO for bounded policer.
3377  */
3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3379 
3380 enum mlxsw_reg_qpcr_action {
3381 	/* Discard */
3382 	MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383 	/* Forward and set color to red.
3384 	 * If the packet is intended to cpu port, it will be dropped.
3385 	 */
3386 	MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3387 };
3388 
3389 /* reg_qpcr_violate_action
3390  * What to do with packets that cross the cir limit (for single rate) or the eir
3391  * limit (for double rate).
3392  * Access: RW for unbounded policer. RO for bounded policer.
3393  */
3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3395 
3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397 				       enum mlxsw_reg_qpcr_ir_units ir_units,
3398 				       bool bytes, u32 cir, u16 cbs)
3399 {
3400 	MLXSW_REG_ZERO(qpcr, payload);
3401 	mlxsw_reg_qpcr_pid_set(payload, pid);
3402 	mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403 	mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404 	mlxsw_reg_qpcr_violate_action_set(payload,
3405 					  MLXSW_REG_QPCR_ACTION_DISCARD);
3406 	mlxsw_reg_qpcr_cir_set(payload, cir);
3407 	mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408 	mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409 	mlxsw_reg_qpcr_cbs_set(payload, cbs);
3410 }
3411 
3412 /* QTCT - QoS Switch Traffic Class Table
3413  * -------------------------------------
3414  * Configures the mapping between the packet switch priority and the
3415  * traffic class on the transmit port.
3416  */
3417 #define MLXSW_REG_QTCT_ID 0x400A
3418 #define MLXSW_REG_QTCT_LEN 0x08
3419 
3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3421 
3422 /* reg_qtct_local_port
3423  * Local port number.
3424  * Access: Index
3425  *
3426  * Note: CPU port is not supported.
3427  */
3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3429 
3430 /* reg_qtct_sub_port
3431  * Virtual port within the physical port.
3432  * Should be set to 0 when virtual ports are not enabled on the port.
3433  * Access: Index
3434  */
3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3436 
3437 /* reg_qtct_switch_prio
3438  * Switch priority.
3439  * Access: Index
3440  */
3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3442 
3443 /* reg_qtct_tclass
3444  * Traffic class.
3445  * Default values:
3446  * switch_prio 0 : tclass 1
3447  * switch_prio 1 : tclass 0
3448  * switch_prio i : tclass i, for i > 1
3449  * Access: RW
3450  */
3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3452 
3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454 				       u8 switch_prio, u8 tclass)
3455 {
3456 	MLXSW_REG_ZERO(qtct, payload);
3457 	mlxsw_reg_qtct_local_port_set(payload, local_port);
3458 	mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459 	mlxsw_reg_qtct_tclass_set(payload, tclass);
3460 }
3461 
3462 /* QEEC - QoS ETS Element Configuration Register
3463  * ---------------------------------------------
3464  * Configures the ETS elements.
3465  */
3466 #define MLXSW_REG_QEEC_ID 0x400D
3467 #define MLXSW_REG_QEEC_LEN 0x20
3468 
3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3470 
3471 /* reg_qeec_local_port
3472  * Local port number.
3473  * Access: Index
3474  *
3475  * Note: CPU port is supported.
3476  */
3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3478 
3479 enum mlxsw_reg_qeec_hr {
3480 	MLXSW_REG_QEEC_HR_PORT,
3481 	MLXSW_REG_QEEC_HR_GROUP,
3482 	MLXSW_REG_QEEC_HR_SUBGROUP,
3483 	MLXSW_REG_QEEC_HR_TC,
3484 };
3485 
3486 /* reg_qeec_element_hierarchy
3487  * 0 - Port
3488  * 1 - Group
3489  * 2 - Subgroup
3490  * 3 - Traffic Class
3491  * Access: Index
3492  */
3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3494 
3495 /* reg_qeec_element_index
3496  * The index of the element in the hierarchy.
3497  * Access: Index
3498  */
3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3500 
3501 /* reg_qeec_next_element_index
3502  * The index of the next (lower) element in the hierarchy.
3503  * Access: RW
3504  *
3505  * Note: Reserved for element_hierarchy 0.
3506  */
3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3508 
3509 /* reg_qeec_mise
3510  * Min shaper configuration enable. Enables configuration of the min
3511  * shaper on this ETS element
3512  * 0 - Disable
3513  * 1 - Enable
3514  * Access: RW
3515  */
3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3517 
3518 /* reg_qeec_ptps
3519  * PTP shaper
3520  * 0: regular shaper mode
3521  * 1: PTP oriented shaper
3522  * Allowed only for hierarchy 0
3523  * Not supported for CPU port
3524  * Note that ptps mode may affect the shaper rates of all hierarchies
3525  * Supported only on Spectrum-1
3526  * Access: RW
3527  */
3528 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3529 
3530 enum {
3531 	MLXSW_REG_QEEC_BYTES_MODE,
3532 	MLXSW_REG_QEEC_PACKETS_MODE,
3533 };
3534 
3535 /* reg_qeec_pb
3536  * Packets or bytes mode.
3537  * 0 - Bytes mode
3538  * 1 - Packets mode
3539  * Access: RW
3540  *
3541  * Note: Used for max shaper configuration. For Spectrum, packets mode
3542  * is supported only for traffic classes of CPU port.
3543  */
3544 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3545 
3546 /* The smallest permitted min shaper rate. */
3547 #define MLXSW_REG_QEEC_MIS_MIN	200000		/* Kbps */
3548 
3549 /* reg_qeec_min_shaper_rate
3550  * Min shaper information rate.
3551  * For CPU port, can only be configured for port hierarchy.
3552  * When in bytes mode, value is specified in units of 1000bps.
3553  * Access: RW
3554  */
3555 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3556 
3557 /* reg_qeec_mase
3558  * Max shaper configuration enable. Enables configuration of the max
3559  * shaper on this ETS element.
3560  * 0 - Disable
3561  * 1 - Enable
3562  * Access: RW
3563  */
3564 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3565 
3566 /* The largest max shaper value possible to disable the shaper. */
3567 #define MLXSW_REG_QEEC_MAS_DIS	((1u << 31) - 1)	/* Kbps */
3568 
3569 /* reg_qeec_max_shaper_rate
3570  * Max shaper information rate.
3571  * For CPU port, can only be configured for port hierarchy.
3572  * When in bytes mode, value is specified in units of 1000bps.
3573  * Access: RW
3574  */
3575 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
3576 
3577 /* reg_qeec_de
3578  * DWRR configuration enable. Enables configuration of the dwrr and
3579  * dwrr_weight.
3580  * 0 - Disable
3581  * 1 - Enable
3582  * Access: RW
3583  */
3584 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3585 
3586 /* reg_qeec_dwrr
3587  * Transmission selection algorithm to use on the link going down from
3588  * the ETS element.
3589  * 0 - Strict priority
3590  * 1 - DWRR
3591  * Access: RW
3592  */
3593 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3594 
3595 /* reg_qeec_dwrr_weight
3596  * DWRR weight on the link going down from the ETS element. The
3597  * percentage of bandwidth guaranteed to an ETS element within
3598  * its hierarchy. The sum of all weights across all ETS elements
3599  * within one hierarchy should be equal to 100. Reserved when
3600  * transmission selection algorithm is strict priority.
3601  * Access: RW
3602  */
3603 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3604 
3605 /* reg_qeec_max_shaper_bs
3606  * Max shaper burst size
3607  * Burst size is 2^max_shaper_bs * 512 bits
3608  * For Spectrum-1: Range is: 5..25
3609  * For Spectrum-2: Range is: 11..25
3610  * Reserved when ptps = 1
3611  * Access: RW
3612  */
3613 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
3614 
3615 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS	25
3616 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1	5
3617 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2	11
3618 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3	5
3619 
3620 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3621 				       enum mlxsw_reg_qeec_hr hr, u8 index,
3622 				       u8 next_index)
3623 {
3624 	MLXSW_REG_ZERO(qeec, payload);
3625 	mlxsw_reg_qeec_local_port_set(payload, local_port);
3626 	mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3627 	mlxsw_reg_qeec_element_index_set(payload, index);
3628 	mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3629 }
3630 
3631 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3632 					    bool ptps)
3633 {
3634 	MLXSW_REG_ZERO(qeec, payload);
3635 	mlxsw_reg_qeec_local_port_set(payload, local_port);
3636 	mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
3637 	mlxsw_reg_qeec_ptps_set(payload, ptps);
3638 }
3639 
3640 /* QRWE - QoS ReWrite Enable
3641  * -------------------------
3642  * This register configures the rewrite enable per receive port.
3643  */
3644 #define MLXSW_REG_QRWE_ID 0x400F
3645 #define MLXSW_REG_QRWE_LEN 0x08
3646 
3647 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3648 
3649 /* reg_qrwe_local_port
3650  * Local port number.
3651  * Access: Index
3652  *
3653  * Note: CPU port is supported. No support for router port.
3654  */
3655 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3656 
3657 /* reg_qrwe_dscp
3658  * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3659  * Access: RW
3660  */
3661 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3662 
3663 /* reg_qrwe_pcp
3664  * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3665  * Access: RW
3666  */
3667 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3668 
3669 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3670 				       bool rewrite_pcp, bool rewrite_dscp)
3671 {
3672 	MLXSW_REG_ZERO(qrwe, payload);
3673 	mlxsw_reg_qrwe_local_port_set(payload, local_port);
3674 	mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3675 	mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3676 }
3677 
3678 /* QPDSM - QoS Priority to DSCP Mapping
3679  * ------------------------------------
3680  * QoS Priority to DSCP Mapping Register
3681  */
3682 #define MLXSW_REG_QPDSM_ID 0x4011
3683 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3684 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3685 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3686 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +			\
3687 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *	\
3688 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3689 
3690 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3691 
3692 /* reg_qpdsm_local_port
3693  * Local Port. Supported for data packets from CPU port.
3694  * Access: Index
3695  */
3696 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3697 
3698 /* reg_qpdsm_prio_entry_color0_e
3699  * Enable update of the entry for color 0 and a given port.
3700  * Access: WO
3701  */
3702 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3703 		     MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3704 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3705 
3706 /* reg_qpdsm_prio_entry_color0_dscp
3707  * DSCP field in the outer label of the packet for color 0 and a given port.
3708  * Reserved when e=0.
3709  * Access: RW
3710  */
3711 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3712 		     MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3713 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3714 
3715 /* reg_qpdsm_prio_entry_color1_e
3716  * Enable update of the entry for color 1 and a given port.
3717  * Access: WO
3718  */
3719 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3720 		     MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3721 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3722 
3723 /* reg_qpdsm_prio_entry_color1_dscp
3724  * DSCP field in the outer label of the packet for color 1 and a given port.
3725  * Reserved when e=0.
3726  * Access: RW
3727  */
3728 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3729 		     MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3730 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3731 
3732 /* reg_qpdsm_prio_entry_color2_e
3733  * Enable update of the entry for color 2 and a given port.
3734  * Access: WO
3735  */
3736 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3737 		     MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3738 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3739 
3740 /* reg_qpdsm_prio_entry_color2_dscp
3741  * DSCP field in the outer label of the packet for color 2 and a given port.
3742  * Reserved when e=0.
3743  * Access: RW
3744  */
3745 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3746 		     MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3747 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3748 
3749 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3750 {
3751 	MLXSW_REG_ZERO(qpdsm, payload);
3752 	mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3753 }
3754 
3755 static inline void
3756 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3757 {
3758 	mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3759 	mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3760 	mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3761 	mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3762 	mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3763 	mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3764 }
3765 
3766 /* QPDP - QoS Port DSCP to Priority Mapping Register
3767  * -------------------------------------------------
3768  * This register controls the port default Switch Priority and Color. The
3769  * default Switch Priority and Color are used for frames where the trust state
3770  * uses default values. All member ports of a LAG should be configured with the
3771  * same default values.
3772  */
3773 #define MLXSW_REG_QPDP_ID 0x4007
3774 #define MLXSW_REG_QPDP_LEN 0x8
3775 
3776 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
3777 
3778 /* reg_qpdp_local_port
3779  * Local Port. Supported for data packets from CPU port.
3780  * Access: Index
3781  */
3782 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8);
3783 
3784 /* reg_qpdp_switch_prio
3785  * Default port Switch Priority (default 0)
3786  * Access: RW
3787  */
3788 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
3789 
3790 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port,
3791 				       u8 switch_prio)
3792 {
3793 	MLXSW_REG_ZERO(qpdp, payload);
3794 	mlxsw_reg_qpdp_local_port_set(payload, local_port);
3795 	mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
3796 }
3797 
3798 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3799  * --------------------------------------------------
3800  * This register controls the mapping from DSCP field to
3801  * Switch Priority for IP packets.
3802  */
3803 #define MLXSW_REG_QPDPM_ID 0x4013
3804 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3805 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3806 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3807 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +			\
3808 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *	\
3809 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3810 
3811 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3812 
3813 /* reg_qpdpm_local_port
3814  * Local Port. Supported for data packets from CPU port.
3815  * Access: Index
3816  */
3817 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3818 
3819 /* reg_qpdpm_dscp_e
3820  * Enable update of the specific entry. When cleared, the switch_prio and color
3821  * fields are ignored and the previous switch_prio and color values are
3822  * preserved.
3823  * Access: WO
3824  */
3825 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3826 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3827 
3828 /* reg_qpdpm_dscp_prio
3829  * The new Switch Priority value for the relevant DSCP value.
3830  * Access: RW
3831  */
3832 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3833 		     MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3834 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3835 
3836 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3837 {
3838 	MLXSW_REG_ZERO(qpdpm, payload);
3839 	mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3840 }
3841 
3842 static inline void
3843 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3844 {
3845 	mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3846 	mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3847 }
3848 
3849 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3850  * ------------------------------------------------------------------
3851  * This register configures if the Switch Priority to Traffic Class mapping is
3852  * based on Multicast packet indication. If so, then multicast packets will get
3853  * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3854  * QTCT.
3855  * By default, Switch Priority to Traffic Class mapping is not based on
3856  * Multicast packet indication.
3857  */
3858 #define MLXSW_REG_QTCTM_ID 0x401A
3859 #define MLXSW_REG_QTCTM_LEN 0x08
3860 
3861 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3862 
3863 /* reg_qtctm_local_port
3864  * Local port number.
3865  * No support for CPU port.
3866  * Access: Index
3867  */
3868 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3869 
3870 /* reg_qtctm_mc
3871  * Multicast Mode
3872  * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3873  * indication (default is 0, not based on Multicast packet indication).
3874  */
3875 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3876 
3877 static inline void
3878 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3879 {
3880 	MLXSW_REG_ZERO(qtctm, payload);
3881 	mlxsw_reg_qtctm_local_port_set(payload, local_port);
3882 	mlxsw_reg_qtctm_mc_set(payload, mc);
3883 }
3884 
3885 /* QPSC - QoS PTP Shaper Configuration Register
3886  * --------------------------------------------
3887  * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
3888  * Supported only on Spectrum-1.
3889  */
3890 #define MLXSW_REG_QPSC_ID 0x401B
3891 #define MLXSW_REG_QPSC_LEN 0x28
3892 
3893 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
3894 
3895 enum mlxsw_reg_qpsc_port_speed {
3896 	MLXSW_REG_QPSC_PORT_SPEED_100M,
3897 	MLXSW_REG_QPSC_PORT_SPEED_1G,
3898 	MLXSW_REG_QPSC_PORT_SPEED_10G,
3899 	MLXSW_REG_QPSC_PORT_SPEED_25G,
3900 };
3901 
3902 /* reg_qpsc_port_speed
3903  * Port speed.
3904  * Access: Index
3905  */
3906 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
3907 
3908 /* reg_qpsc_shaper_time_exp
3909  * The base-time-interval for updating the shapers tokens (for all hierarchies).
3910  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3911  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3912  * Access: RW
3913  */
3914 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
3915 
3916 /* reg_qpsc_shaper_time_mantissa
3917  * The base-time-interval for updating the shapers tokens (for all hierarchies).
3918  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3919  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3920  * Access: RW
3921  */
3922 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
3923 
3924 /* reg_qpsc_shaper_inc
3925  * Number of tokens added to shaper on each update.
3926  * Units of 8B.
3927  * Access: RW
3928  */
3929 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
3930 
3931 /* reg_qpsc_shaper_bs
3932  * Max shaper Burst size.
3933  * Burst size is 2 ^ max_shaper_bs * 512 [bits]
3934  * Range is: 5..25 (from 2KB..2GB)
3935  * Access: RW
3936  */
3937 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
3938 
3939 /* reg_qpsc_ptsc_we
3940  * Write enable to port_to_shaper_credits.
3941  * Access: WO
3942  */
3943 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
3944 
3945 /* reg_qpsc_port_to_shaper_credits
3946  * For split ports: range 1..57
3947  * For non-split ports: range 1..112
3948  * Written only when ptsc_we is set.
3949  * Access: RW
3950  */
3951 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
3952 
3953 /* reg_qpsc_ing_timestamp_inc
3954  * Ingress timestamp increment.
3955  * 2's complement.
3956  * The timestamp of MTPPTR at ingress will be incremented by this value. Global
3957  * value for all ports.
3958  * Same units as used by MTPPTR.
3959  * Access: RW
3960  */
3961 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
3962 
3963 /* reg_qpsc_egr_timestamp_inc
3964  * Egress timestamp increment.
3965  * 2's complement.
3966  * The timestamp of MTPPTR at egress will be incremented by this value. Global
3967  * value for all ports.
3968  * Same units as used by MTPPTR.
3969  * Access: RW
3970  */
3971 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
3972 
3973 static inline void
3974 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
3975 		    u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
3976 		    u8 shaper_bs, u8 port_to_shaper_credits,
3977 		    int ing_timestamp_inc, int egr_timestamp_inc)
3978 {
3979 	MLXSW_REG_ZERO(qpsc, payload);
3980 	mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
3981 	mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
3982 	mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
3983 	mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
3984 	mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
3985 	mlxsw_reg_qpsc_ptsc_we_set(payload, true);
3986 	mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
3987 	mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
3988 	mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
3989 }
3990 
3991 /* PMLP - Ports Module to Local Port Register
3992  * ------------------------------------------
3993  * Configures the assignment of modules to local ports.
3994  */
3995 #define MLXSW_REG_PMLP_ID 0x5002
3996 #define MLXSW_REG_PMLP_LEN 0x40
3997 
3998 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3999 
4000 /* reg_pmlp_rxtx
4001  * 0 - Tx value is used for both Tx and Rx.
4002  * 1 - Rx value is taken from a separte field.
4003  * Access: RW
4004  */
4005 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4006 
4007 /* reg_pmlp_local_port
4008  * Local port number.
4009  * Access: Index
4010  */
4011 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
4012 
4013 /* reg_pmlp_width
4014  * 0 - Unmap local port.
4015  * 1 - Lane 0 is used.
4016  * 2 - Lanes 0 and 1 are used.
4017  * 4 - Lanes 0, 1, 2 and 3 are used.
4018  * 8 - Lanes 0-7 are used.
4019  * Access: RW
4020  */
4021 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4022 
4023 /* reg_pmlp_module
4024  * Module number.
4025  * Access: RW
4026  */
4027 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4028 
4029 /* reg_pmlp_tx_lane
4030  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
4031  * Access: RW
4032  */
4033 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4034 
4035 /* reg_pmlp_rx_lane
4036  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
4037  * equal to Tx lane.
4038  * Access: RW
4039  */
4040 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4041 
4042 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
4043 {
4044 	MLXSW_REG_ZERO(pmlp, payload);
4045 	mlxsw_reg_pmlp_local_port_set(payload, local_port);
4046 }
4047 
4048 /* PMTU - Port MTU Register
4049  * ------------------------
4050  * Configures and reports the port MTU.
4051  */
4052 #define MLXSW_REG_PMTU_ID 0x5003
4053 #define MLXSW_REG_PMTU_LEN 0x10
4054 
4055 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4056 
4057 /* reg_pmtu_local_port
4058  * Local port number.
4059  * Access: Index
4060  */
4061 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
4062 
4063 /* reg_pmtu_max_mtu
4064  * Maximum MTU.
4065  * When port type (e.g. Ethernet) is configured, the relevant MTU is
4066  * reported, otherwise the minimum between the max_mtu of the different
4067  * types is reported.
4068  * Access: RO
4069  */
4070 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4071 
4072 /* reg_pmtu_admin_mtu
4073  * MTU value to set port to. Must be smaller or equal to max_mtu.
4074  * Note: If port type is Infiniband, then port must be disabled, when its
4075  * MTU is set.
4076  * Access: RW
4077  */
4078 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4079 
4080 /* reg_pmtu_oper_mtu
4081  * The actual MTU configured on the port. Packets exceeding this size
4082  * will be dropped.
4083  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4084  * oper_mtu might be smaller than admin_mtu.
4085  * Access: RO
4086  */
4087 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4088 
4089 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
4090 				       u16 new_mtu)
4091 {
4092 	MLXSW_REG_ZERO(pmtu, payload);
4093 	mlxsw_reg_pmtu_local_port_set(payload, local_port);
4094 	mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4095 	mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4096 	mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4097 }
4098 
4099 /* PTYS - Port Type and Speed Register
4100  * -----------------------------------
4101  * Configures and reports the port speed type.
4102  *
4103  * Note: When set while the link is up, the changes will not take effect
4104  * until the port transitions from down to up state.
4105  */
4106 #define MLXSW_REG_PTYS_ID 0x5004
4107 #define MLXSW_REG_PTYS_LEN 0x40
4108 
4109 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4110 
4111 /* an_disable_admin
4112  * Auto negotiation disable administrative configuration
4113  * 0 - Device doesn't support AN disable.
4114  * 1 - Device supports AN disable.
4115  * Access: RW
4116  */
4117 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4118 
4119 /* reg_ptys_local_port
4120  * Local port number.
4121  * Access: Index
4122  */
4123 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
4124 
4125 #define MLXSW_REG_PTYS_PROTO_MASK_IB	BIT(0)
4126 #define MLXSW_REG_PTYS_PROTO_MASK_ETH	BIT(2)
4127 
4128 /* reg_ptys_proto_mask
4129  * Protocol mask. Indicates which protocol is used.
4130  * 0 - Infiniband.
4131  * 1 - Fibre Channel.
4132  * 2 - Ethernet.
4133  * Access: Index
4134  */
4135 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4136 
4137 enum {
4138 	MLXSW_REG_PTYS_AN_STATUS_NA,
4139 	MLXSW_REG_PTYS_AN_STATUS_OK,
4140 	MLXSW_REG_PTYS_AN_STATUS_FAIL,
4141 };
4142 
4143 /* reg_ptys_an_status
4144  * Autonegotiation status.
4145  * Access: RO
4146  */
4147 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4148 
4149 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M				BIT(0)
4150 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII			BIT(1)
4151 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII			BIT(2)
4152 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R				BIT(3)
4153 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G			BIT(4)
4154 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G		BIT(5)
4155 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR		BIT(6)
4156 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2	BIT(7)
4157 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR	BIT(8)
4158 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)
4159 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)
4160 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)
4161 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)
4162 
4163 /* reg_ptys_ext_eth_proto_cap
4164  * Extended Ethernet port supported speeds and protocols.
4165  * Access: RO
4166  */
4167 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4168 
4169 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII			BIT(0)
4170 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX		BIT(1)
4171 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4		BIT(2)
4172 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4		BIT(3)
4173 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR		BIT(4)
4174 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2		BIT(5)
4175 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4		BIT(6)
4176 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4		BIT(7)
4177 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR		BIT(12)
4178 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR		BIT(13)
4179 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR		BIT(14)
4180 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4		BIT(15)
4181 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4	BIT(16)
4182 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2		BIT(18)
4183 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4		BIT(19)
4184 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)
4185 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)
4186 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)
4187 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)
4188 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX		BIT(24)
4189 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T		BIT(25)
4190 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T		BIT(26)
4191 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)
4192 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)
4193 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)
4194 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2		BIT(30)
4195 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2		BIT(31)
4196 
4197 /* reg_ptys_eth_proto_cap
4198  * Ethernet port supported speeds and protocols.
4199  * Access: RO
4200  */
4201 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4202 
4203 /* reg_ptys_ib_link_width_cap
4204  * IB port supported widths.
4205  * Access: RO
4206  */
4207 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4208 
4209 #define MLXSW_REG_PTYS_IB_SPEED_SDR	BIT(0)
4210 #define MLXSW_REG_PTYS_IB_SPEED_DDR	BIT(1)
4211 #define MLXSW_REG_PTYS_IB_SPEED_QDR	BIT(2)
4212 #define MLXSW_REG_PTYS_IB_SPEED_FDR10	BIT(3)
4213 #define MLXSW_REG_PTYS_IB_SPEED_FDR	BIT(4)
4214 #define MLXSW_REG_PTYS_IB_SPEED_EDR	BIT(5)
4215 
4216 /* reg_ptys_ib_proto_cap
4217  * IB port supported speeds and protocols.
4218  * Access: RO
4219  */
4220 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4221 
4222 /* reg_ptys_ext_eth_proto_admin
4223  * Extended speed and protocol to set port to.
4224  * Access: RW
4225  */
4226 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4227 
4228 /* reg_ptys_eth_proto_admin
4229  * Speed and protocol to set port to.
4230  * Access: RW
4231  */
4232 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4233 
4234 /* reg_ptys_ib_link_width_admin
4235  * IB width to set port to.
4236  * Access: RW
4237  */
4238 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4239 
4240 /* reg_ptys_ib_proto_admin
4241  * IB speeds and protocols to set port to.
4242  * Access: RW
4243  */
4244 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4245 
4246 /* reg_ptys_ext_eth_proto_oper
4247  * The extended current speed and protocol configured for the port.
4248  * Access: RO
4249  */
4250 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4251 
4252 /* reg_ptys_eth_proto_oper
4253  * The current speed and protocol configured for the port.
4254  * Access: RO
4255  */
4256 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4257 
4258 /* reg_ptys_ib_link_width_oper
4259  * The current IB width to set port to.
4260  * Access: RO
4261  */
4262 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4263 
4264 /* reg_ptys_ib_proto_oper
4265  * The current IB speed and protocol.
4266  * Access: RO
4267  */
4268 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4269 
4270 enum mlxsw_reg_ptys_connector_type {
4271 	MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4272 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4273 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4274 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4275 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4276 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4277 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4278 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4279 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4280 };
4281 
4282 /* reg_ptys_connector_type
4283  * Connector type indication.
4284  * Access: RO
4285  */
4286 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4287 
4288 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4289 					   u32 proto_admin, bool autoneg)
4290 {
4291 	MLXSW_REG_ZERO(ptys, payload);
4292 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4293 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4294 	mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4295 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4296 }
4297 
4298 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4299 					       u32 proto_admin, bool autoneg)
4300 {
4301 	MLXSW_REG_ZERO(ptys, payload);
4302 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4303 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4304 	mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4305 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4306 }
4307 
4308 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4309 					     u32 *p_eth_proto_cap,
4310 					     u32 *p_eth_proto_admin,
4311 					     u32 *p_eth_proto_oper)
4312 {
4313 	if (p_eth_proto_cap)
4314 		*p_eth_proto_cap =
4315 			mlxsw_reg_ptys_eth_proto_cap_get(payload);
4316 	if (p_eth_proto_admin)
4317 		*p_eth_proto_admin =
4318 			mlxsw_reg_ptys_eth_proto_admin_get(payload);
4319 	if (p_eth_proto_oper)
4320 		*p_eth_proto_oper =
4321 			mlxsw_reg_ptys_eth_proto_oper_get(payload);
4322 }
4323 
4324 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4325 						 u32 *p_eth_proto_cap,
4326 						 u32 *p_eth_proto_admin,
4327 						 u32 *p_eth_proto_oper)
4328 {
4329 	if (p_eth_proto_cap)
4330 		*p_eth_proto_cap =
4331 			mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4332 	if (p_eth_proto_admin)
4333 		*p_eth_proto_admin =
4334 			mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4335 	if (p_eth_proto_oper)
4336 		*p_eth_proto_oper =
4337 			mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4338 }
4339 
4340 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4341 					  u16 proto_admin, u16 link_width)
4342 {
4343 	MLXSW_REG_ZERO(ptys, payload);
4344 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4345 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4346 	mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4347 	mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4348 }
4349 
4350 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4351 					    u16 *p_ib_link_width_cap,
4352 					    u16 *p_ib_proto_oper,
4353 					    u16 *p_ib_link_width_oper)
4354 {
4355 	if (p_ib_proto_cap)
4356 		*p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4357 	if (p_ib_link_width_cap)
4358 		*p_ib_link_width_cap =
4359 			mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4360 	if (p_ib_proto_oper)
4361 		*p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4362 	if (p_ib_link_width_oper)
4363 		*p_ib_link_width_oper =
4364 			mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4365 }
4366 
4367 /* PPAD - Port Physical Address Register
4368  * -------------------------------------
4369  * The PPAD register configures the per port physical MAC address.
4370  */
4371 #define MLXSW_REG_PPAD_ID 0x5005
4372 #define MLXSW_REG_PPAD_LEN 0x10
4373 
4374 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4375 
4376 /* reg_ppad_single_base_mac
4377  * 0: base_mac, local port should be 0 and mac[7:0] is
4378  * reserved. HW will set incremental
4379  * 1: single_mac - mac of the local_port
4380  * Access: RW
4381  */
4382 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4383 
4384 /* reg_ppad_local_port
4385  * port number, if single_base_mac = 0 then local_port is reserved
4386  * Access: RW
4387  */
4388 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4389 
4390 /* reg_ppad_mac
4391  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4392  * If single_base_mac = 1 - the per port MAC address
4393  * Access: RW
4394  */
4395 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4396 
4397 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4398 				       u8 local_port)
4399 {
4400 	MLXSW_REG_ZERO(ppad, payload);
4401 	mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4402 	mlxsw_reg_ppad_local_port_set(payload, local_port);
4403 }
4404 
4405 /* PAOS - Ports Administrative and Operational Status Register
4406  * -----------------------------------------------------------
4407  * Configures and retrieves per port administrative and operational status.
4408  */
4409 #define MLXSW_REG_PAOS_ID 0x5006
4410 #define MLXSW_REG_PAOS_LEN 0x10
4411 
4412 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4413 
4414 /* reg_paos_swid
4415  * Switch partition ID with which to associate the port.
4416  * Note: while external ports uses unique local port numbers (and thus swid is
4417  * redundant), router ports use the same local port number where swid is the
4418  * only indication for the relevant port.
4419  * Access: Index
4420  */
4421 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4422 
4423 /* reg_paos_local_port
4424  * Local port number.
4425  * Access: Index
4426  */
4427 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4428 
4429 /* reg_paos_admin_status
4430  * Port administrative state (the desired state of the port):
4431  * 1 - Up.
4432  * 2 - Down.
4433  * 3 - Up once. This means that in case of link failure, the port won't go
4434  *     into polling mode, but will wait to be re-enabled by software.
4435  * 4 - Disabled by system. Can only be set by hardware.
4436  * Access: RW
4437  */
4438 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4439 
4440 /* reg_paos_oper_status
4441  * Port operational state (the current state):
4442  * 1 - Up.
4443  * 2 - Down.
4444  * 3 - Down by port failure. This means that the device will not let the
4445  *     port up again until explicitly specified by software.
4446  * Access: RO
4447  */
4448 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4449 
4450 /* reg_paos_ase
4451  * Admin state update enabled.
4452  * Access: WO
4453  */
4454 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4455 
4456 /* reg_paos_ee
4457  * Event update enable. If this bit is set, event generation will be
4458  * updated based on the e field.
4459  * Access: WO
4460  */
4461 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4462 
4463 /* reg_paos_e
4464  * Event generation on operational state change:
4465  * 0 - Do not generate event.
4466  * 1 - Generate Event.
4467  * 2 - Generate Single Event.
4468  * Access: RW
4469  */
4470 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4471 
4472 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4473 				       enum mlxsw_port_admin_status status)
4474 {
4475 	MLXSW_REG_ZERO(paos, payload);
4476 	mlxsw_reg_paos_swid_set(payload, 0);
4477 	mlxsw_reg_paos_local_port_set(payload, local_port);
4478 	mlxsw_reg_paos_admin_status_set(payload, status);
4479 	mlxsw_reg_paos_oper_status_set(payload, 0);
4480 	mlxsw_reg_paos_ase_set(payload, 1);
4481 	mlxsw_reg_paos_ee_set(payload, 1);
4482 	mlxsw_reg_paos_e_set(payload, 1);
4483 }
4484 
4485 /* PFCC - Ports Flow Control Configuration Register
4486  * ------------------------------------------------
4487  * Configures and retrieves the per port flow control configuration.
4488  */
4489 #define MLXSW_REG_PFCC_ID 0x5007
4490 #define MLXSW_REG_PFCC_LEN 0x20
4491 
4492 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4493 
4494 /* reg_pfcc_local_port
4495  * Local port number.
4496  * Access: Index
4497  */
4498 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4499 
4500 /* reg_pfcc_pnat
4501  * Port number access type. Determines the way local_port is interpreted:
4502  * 0 - Local port number.
4503  * 1 - IB / label port number.
4504  * Access: Index
4505  */
4506 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4507 
4508 /* reg_pfcc_shl_cap
4509  * Send to higher layers capabilities:
4510  * 0 - No capability of sending Pause and PFC frames to higher layers.
4511  * 1 - Device has capability of sending Pause and PFC frames to higher
4512  *     layers.
4513  * Access: RO
4514  */
4515 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4516 
4517 /* reg_pfcc_shl_opr
4518  * Send to higher layers operation:
4519  * 0 - Pause and PFC frames are handled by the port (default).
4520  * 1 - Pause and PFC frames are handled by the port and also sent to
4521  *     higher layers. Only valid if shl_cap = 1.
4522  * Access: RW
4523  */
4524 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4525 
4526 /* reg_pfcc_ppan
4527  * Pause policy auto negotiation.
4528  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4529  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4530  *     based on the auto-negotiation resolution.
4531  * Access: RW
4532  *
4533  * Note: The auto-negotiation advertisement is set according to pptx and
4534  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4535  */
4536 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4537 
4538 /* reg_pfcc_prio_mask_tx
4539  * Bit per priority indicating if Tx flow control policy should be
4540  * updated based on bit pfctx.
4541  * Access: WO
4542  */
4543 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4544 
4545 /* reg_pfcc_prio_mask_rx
4546  * Bit per priority indicating if Rx flow control policy should be
4547  * updated based on bit pfcrx.
4548  * Access: WO
4549  */
4550 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4551 
4552 /* reg_pfcc_pptx
4553  * Admin Pause policy on Tx.
4554  * 0 - Never generate Pause frames (default).
4555  * 1 - Generate Pause frames according to Rx buffer threshold.
4556  * Access: RW
4557  */
4558 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4559 
4560 /* reg_pfcc_aptx
4561  * Active (operational) Pause policy on Tx.
4562  * 0 - Never generate Pause frames.
4563  * 1 - Generate Pause frames according to Rx buffer threshold.
4564  * Access: RO
4565  */
4566 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4567 
4568 /* reg_pfcc_pfctx
4569  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4570  * 0 - Never generate priority Pause frames on the specified priority
4571  *     (default).
4572  * 1 - Generate priority Pause frames according to Rx buffer threshold on
4573  *     the specified priority.
4574  * Access: RW
4575  *
4576  * Note: pfctx and pptx must be mutually exclusive.
4577  */
4578 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4579 
4580 /* reg_pfcc_pprx
4581  * Admin Pause policy on Rx.
4582  * 0 - Ignore received Pause frames (default).
4583  * 1 - Respect received Pause frames.
4584  * Access: RW
4585  */
4586 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4587 
4588 /* reg_pfcc_aprx
4589  * Active (operational) Pause policy on Rx.
4590  * 0 - Ignore received Pause frames.
4591  * 1 - Respect received Pause frames.
4592  * Access: RO
4593  */
4594 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4595 
4596 /* reg_pfcc_pfcrx
4597  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4598  * 0 - Ignore incoming priority Pause frames on the specified priority
4599  *     (default).
4600  * 1 - Respect incoming priority Pause frames on the specified priority.
4601  * Access: RW
4602  */
4603 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4604 
4605 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4606 
4607 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4608 {
4609 	mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4610 	mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4611 	mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4612 	mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4613 }
4614 
4615 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4616 {
4617 	MLXSW_REG_ZERO(pfcc, payload);
4618 	mlxsw_reg_pfcc_local_port_set(payload, local_port);
4619 }
4620 
4621 /* PPCNT - Ports Performance Counters Register
4622  * -------------------------------------------
4623  * The PPCNT register retrieves per port performance counters.
4624  */
4625 #define MLXSW_REG_PPCNT_ID 0x5008
4626 #define MLXSW_REG_PPCNT_LEN 0x100
4627 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4628 
4629 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4630 
4631 /* reg_ppcnt_swid
4632  * For HCA: must be always 0.
4633  * Switch partition ID to associate port with.
4634  * Switch partitions are numbered from 0 to 7 inclusively.
4635  * Switch partition 254 indicates stacking ports.
4636  * Switch partition 255 indicates all switch partitions.
4637  * Only valid on Set() operation with local_port=255.
4638  * Access: Index
4639  */
4640 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4641 
4642 /* reg_ppcnt_local_port
4643  * Local port number.
4644  * 255 indicates all ports on the device, and is only allowed
4645  * for Set() operation.
4646  * Access: Index
4647  */
4648 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4649 
4650 /* reg_ppcnt_pnat
4651  * Port number access type:
4652  * 0 - Local port number
4653  * 1 - IB port number
4654  * Access: Index
4655  */
4656 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4657 
4658 enum mlxsw_reg_ppcnt_grp {
4659 	MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4660 	MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4661 	MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4662 	MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4663 	MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4664 	MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4665 	MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4666 	MLXSW_REG_PPCNT_TC_CNT = 0x11,
4667 	MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4668 };
4669 
4670 /* reg_ppcnt_grp
4671  * Performance counter group.
4672  * Group 63 indicates all groups. Only valid on Set() operation with
4673  * clr bit set.
4674  * 0x0: IEEE 802.3 Counters
4675  * 0x1: RFC 2863 Counters
4676  * 0x2: RFC 2819 Counters
4677  * 0x3: RFC 3635 Counters
4678  * 0x5: Ethernet Extended Counters
4679  * 0x6: Ethernet Discard Counters
4680  * 0x8: Link Level Retransmission Counters
4681  * 0x10: Per Priority Counters
4682  * 0x11: Per Traffic Class Counters
4683  * 0x12: Physical Layer Counters
4684  * 0x13: Per Traffic Class Congestion Counters
4685  * Access: Index
4686  */
4687 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4688 
4689 /* reg_ppcnt_clr
4690  * Clear counters. Setting the clr bit will reset the counter value
4691  * for all counters in the counter group. This bit can be set
4692  * for both Set() and Get() operation.
4693  * Access: OP
4694  */
4695 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4696 
4697 /* reg_ppcnt_prio_tc
4698  * Priority for counter set that support per priority, valid values: 0-7.
4699  * Traffic class for counter set that support per traffic class,
4700  * valid values: 0- cap_max_tclass-1 .
4701  * For HCA: cap_max_tclass is always 8.
4702  * Otherwise must be 0.
4703  * Access: Index
4704  */
4705 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4706 
4707 /* Ethernet IEEE 802.3 Counter Group */
4708 
4709 /* reg_ppcnt_a_frames_transmitted_ok
4710  * Access: RO
4711  */
4712 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4713 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4714 
4715 /* reg_ppcnt_a_frames_received_ok
4716  * Access: RO
4717  */
4718 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4719 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4720 
4721 /* reg_ppcnt_a_frame_check_sequence_errors
4722  * Access: RO
4723  */
4724 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4725 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4726 
4727 /* reg_ppcnt_a_alignment_errors
4728  * Access: RO
4729  */
4730 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4731 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4732 
4733 /* reg_ppcnt_a_octets_transmitted_ok
4734  * Access: RO
4735  */
4736 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4737 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4738 
4739 /* reg_ppcnt_a_octets_received_ok
4740  * Access: RO
4741  */
4742 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4743 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4744 
4745 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4746  * Access: RO
4747  */
4748 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4749 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4750 
4751 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4752  * Access: RO
4753  */
4754 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4755 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4756 
4757 /* reg_ppcnt_a_multicast_frames_received_ok
4758  * Access: RO
4759  */
4760 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4761 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4762 
4763 /* reg_ppcnt_a_broadcast_frames_received_ok
4764  * Access: RO
4765  */
4766 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4767 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4768 
4769 /* reg_ppcnt_a_in_range_length_errors
4770  * Access: RO
4771  */
4772 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4773 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4774 
4775 /* reg_ppcnt_a_out_of_range_length_field
4776  * Access: RO
4777  */
4778 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4779 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4780 
4781 /* reg_ppcnt_a_frame_too_long_errors
4782  * Access: RO
4783  */
4784 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4785 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4786 
4787 /* reg_ppcnt_a_symbol_error_during_carrier
4788  * Access: RO
4789  */
4790 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4791 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4792 
4793 /* reg_ppcnt_a_mac_control_frames_transmitted
4794  * Access: RO
4795  */
4796 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4797 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4798 
4799 /* reg_ppcnt_a_mac_control_frames_received
4800  * Access: RO
4801  */
4802 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4803 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4804 
4805 /* reg_ppcnt_a_unsupported_opcodes_received
4806  * Access: RO
4807  */
4808 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4809 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4810 
4811 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4812  * Access: RO
4813  */
4814 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4815 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4816 
4817 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4818  * Access: RO
4819  */
4820 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4821 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4822 
4823 /* Ethernet RFC 2863 Counter Group */
4824 
4825 /* reg_ppcnt_if_in_discards
4826  * Access: RO
4827  */
4828 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4829 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4830 
4831 /* reg_ppcnt_if_out_discards
4832  * Access: RO
4833  */
4834 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4835 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4836 
4837 /* reg_ppcnt_if_out_errors
4838  * Access: RO
4839  */
4840 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4841 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4842 
4843 /* Ethernet RFC 2819 Counter Group */
4844 
4845 /* reg_ppcnt_ether_stats_undersize_pkts
4846  * Access: RO
4847  */
4848 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4849 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4850 
4851 /* reg_ppcnt_ether_stats_oversize_pkts
4852  * Access: RO
4853  */
4854 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4855 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4856 
4857 /* reg_ppcnt_ether_stats_fragments
4858  * Access: RO
4859  */
4860 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4861 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4862 
4863 /* reg_ppcnt_ether_stats_pkts64octets
4864  * Access: RO
4865  */
4866 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4867 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4868 
4869 /* reg_ppcnt_ether_stats_pkts65to127octets
4870  * Access: RO
4871  */
4872 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4873 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4874 
4875 /* reg_ppcnt_ether_stats_pkts128to255octets
4876  * Access: RO
4877  */
4878 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4879 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4880 
4881 /* reg_ppcnt_ether_stats_pkts256to511octets
4882  * Access: RO
4883  */
4884 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4885 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4886 
4887 /* reg_ppcnt_ether_stats_pkts512to1023octets
4888  * Access: RO
4889  */
4890 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4891 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4892 
4893 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4894  * Access: RO
4895  */
4896 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4897 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4898 
4899 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4900  * Access: RO
4901  */
4902 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4903 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4904 
4905 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4906  * Access: RO
4907  */
4908 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4909 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4910 
4911 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4912  * Access: RO
4913  */
4914 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4915 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4916 
4917 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4918  * Access: RO
4919  */
4920 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4921 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4922 
4923 /* Ethernet RFC 3635 Counter Group */
4924 
4925 /* reg_ppcnt_dot3stats_fcs_errors
4926  * Access: RO
4927  */
4928 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4929 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4930 
4931 /* reg_ppcnt_dot3stats_symbol_errors
4932  * Access: RO
4933  */
4934 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
4935 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4936 
4937 /* reg_ppcnt_dot3control_in_unknown_opcodes
4938  * Access: RO
4939  */
4940 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
4941 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4942 
4943 /* reg_ppcnt_dot3in_pause_frames
4944  * Access: RO
4945  */
4946 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
4947 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4948 
4949 /* Ethernet Extended Counter Group Counters */
4950 
4951 /* reg_ppcnt_ecn_marked
4952  * Access: RO
4953  */
4954 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4955 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4956 
4957 /* Ethernet Discard Counter Group Counters */
4958 
4959 /* reg_ppcnt_ingress_general
4960  * Access: RO
4961  */
4962 MLXSW_ITEM64(reg, ppcnt, ingress_general,
4963 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4964 
4965 /* reg_ppcnt_ingress_policy_engine
4966  * Access: RO
4967  */
4968 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
4969 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4970 
4971 /* reg_ppcnt_ingress_vlan_membership
4972  * Access: RO
4973  */
4974 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
4975 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4976 
4977 /* reg_ppcnt_ingress_tag_frame_type
4978  * Access: RO
4979  */
4980 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
4981 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4982 
4983 /* reg_ppcnt_egress_vlan_membership
4984  * Access: RO
4985  */
4986 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
4987 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4988 
4989 /* reg_ppcnt_loopback_filter
4990  * Access: RO
4991  */
4992 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
4993 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4994 
4995 /* reg_ppcnt_egress_general
4996  * Access: RO
4997  */
4998 MLXSW_ITEM64(reg, ppcnt, egress_general,
4999 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5000 
5001 /* reg_ppcnt_egress_hoq
5002  * Access: RO
5003  */
5004 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
5005 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5006 
5007 /* reg_ppcnt_egress_policy_engine
5008  * Access: RO
5009  */
5010 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
5011 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5012 
5013 /* reg_ppcnt_ingress_tx_link_down
5014  * Access: RO
5015  */
5016 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
5017 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5018 
5019 /* reg_ppcnt_egress_stp_filter
5020  * Access: RO
5021  */
5022 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
5023 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5024 
5025 /* reg_ppcnt_egress_sll
5026  * Access: RO
5027  */
5028 MLXSW_ITEM64(reg, ppcnt, egress_sll,
5029 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5030 
5031 /* Ethernet Per Priority Group Counters */
5032 
5033 /* reg_ppcnt_rx_octets
5034  * Access: RO
5035  */
5036 MLXSW_ITEM64(reg, ppcnt, rx_octets,
5037 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5038 
5039 /* reg_ppcnt_rx_frames
5040  * Access: RO
5041  */
5042 MLXSW_ITEM64(reg, ppcnt, rx_frames,
5043 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5044 
5045 /* reg_ppcnt_tx_octets
5046  * Access: RO
5047  */
5048 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5049 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5050 
5051 /* reg_ppcnt_tx_frames
5052  * Access: RO
5053  */
5054 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5055 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5056 
5057 /* reg_ppcnt_rx_pause
5058  * Access: RO
5059  */
5060 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5061 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5062 
5063 /* reg_ppcnt_rx_pause_duration
5064  * Access: RO
5065  */
5066 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5067 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5068 
5069 /* reg_ppcnt_tx_pause
5070  * Access: RO
5071  */
5072 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5073 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5074 
5075 /* reg_ppcnt_tx_pause_duration
5076  * Access: RO
5077  */
5078 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5079 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5080 
5081 /* reg_ppcnt_rx_pause_transition
5082  * Access: RO
5083  */
5084 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5085 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5086 
5087 /* Ethernet Per Traffic Group Counters */
5088 
5089 /* reg_ppcnt_tc_transmit_queue
5090  * Contains the transmit queue depth in cells of traffic class
5091  * selected by prio_tc and the port selected by local_port.
5092  * The field cannot be cleared.
5093  * Access: RO
5094  */
5095 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5096 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5097 
5098 /* reg_ppcnt_tc_no_buffer_discard_uc
5099  * The number of unicast packets dropped due to lack of shared
5100  * buffer resources.
5101  * Access: RO
5102  */
5103 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5104 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5105 
5106 /* Ethernet Per Traffic Class Congestion Group Counters */
5107 
5108 /* reg_ppcnt_wred_discard
5109  * Access: RO
5110  */
5111 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5112 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5113 
5114 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
5115 					enum mlxsw_reg_ppcnt_grp grp,
5116 					u8 prio_tc)
5117 {
5118 	MLXSW_REG_ZERO(ppcnt, payload);
5119 	mlxsw_reg_ppcnt_swid_set(payload, 0);
5120 	mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5121 	mlxsw_reg_ppcnt_pnat_set(payload, 0);
5122 	mlxsw_reg_ppcnt_grp_set(payload, grp);
5123 	mlxsw_reg_ppcnt_clr_set(payload, 0);
5124 	mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5125 }
5126 
5127 /* PLIB - Port Local to InfiniBand Port
5128  * ------------------------------------
5129  * The PLIB register performs mapping from Local Port into InfiniBand Port.
5130  */
5131 #define MLXSW_REG_PLIB_ID 0x500A
5132 #define MLXSW_REG_PLIB_LEN 0x10
5133 
5134 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5135 
5136 /* reg_plib_local_port
5137  * Local port number.
5138  * Access: Index
5139  */
5140 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
5141 
5142 /* reg_plib_ib_port
5143  * InfiniBand port remapping for local_port.
5144  * Access: RW
5145  */
5146 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5147 
5148 /* PPTB - Port Prio To Buffer Register
5149  * -----------------------------------
5150  * Configures the switch priority to buffer table.
5151  */
5152 #define MLXSW_REG_PPTB_ID 0x500B
5153 #define MLXSW_REG_PPTB_LEN 0x10
5154 
5155 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5156 
5157 enum {
5158 	MLXSW_REG_PPTB_MM_UM,
5159 	MLXSW_REG_PPTB_MM_UNICAST,
5160 	MLXSW_REG_PPTB_MM_MULTICAST,
5161 };
5162 
5163 /* reg_pptb_mm
5164  * Mapping mode.
5165  * 0 - Map both unicast and multicast packets to the same buffer.
5166  * 1 - Map only unicast packets.
5167  * 2 - Map only multicast packets.
5168  * Access: Index
5169  *
5170  * Note: SwitchX-2 only supports the first option.
5171  */
5172 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5173 
5174 /* reg_pptb_local_port
5175  * Local port number.
5176  * Access: Index
5177  */
5178 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5179 
5180 /* reg_pptb_um
5181  * Enables the update of the untagged_buf field.
5182  * Access: RW
5183  */
5184 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5185 
5186 /* reg_pptb_pm
5187  * Enables the update of the prio_to_buff field.
5188  * Bit <i> is a flag for updating the mapping for switch priority <i>.
5189  * Access: RW
5190  */
5191 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5192 
5193 /* reg_pptb_prio_to_buff
5194  * Mapping of switch priority <i> to one of the allocated receive port
5195  * buffers.
5196  * Access: RW
5197  */
5198 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5199 
5200 /* reg_pptb_pm_msb
5201  * Enables the update of the prio_to_buff field.
5202  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5203  * Access: RW
5204  */
5205 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5206 
5207 /* reg_pptb_untagged_buff
5208  * Mapping of untagged frames to one of the allocated receive port buffers.
5209  * Access: RW
5210  *
5211  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5212  * Spectrum, as it maps untagged packets based on the default switch priority.
5213  */
5214 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5215 
5216 /* reg_pptb_prio_to_buff_msb
5217  * Mapping of switch priority <i+8> to one of the allocated receive port
5218  * buffers.
5219  * Access: RW
5220  */
5221 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5222 
5223 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5224 
5225 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5226 {
5227 	MLXSW_REG_ZERO(pptb, payload);
5228 	mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5229 	mlxsw_reg_pptb_local_port_set(payload, local_port);
5230 	mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5231 	mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5232 }
5233 
5234 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5235 						    u8 buff)
5236 {
5237 	mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5238 	mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5239 }
5240 
5241 /* PBMC - Port Buffer Management Control Register
5242  * ----------------------------------------------
5243  * The PBMC register configures and retrieves the port packet buffer
5244  * allocation for different Prios, and the Pause threshold management.
5245  */
5246 #define MLXSW_REG_PBMC_ID 0x500C
5247 #define MLXSW_REG_PBMC_LEN 0x6C
5248 
5249 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5250 
5251 /* reg_pbmc_local_port
5252  * Local port number.
5253  * Access: Index
5254  */
5255 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5256 
5257 /* reg_pbmc_xoff_timer_value
5258  * When device generates a pause frame, it uses this value as the pause
5259  * timer (time for the peer port to pause in quota-512 bit time).
5260  * Access: RW
5261  */
5262 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5263 
5264 /* reg_pbmc_xoff_refresh
5265  * The time before a new pause frame should be sent to refresh the pause RW
5266  * state. Using the same units as xoff_timer_value above (in quota-512 bit
5267  * time).
5268  * Access: RW
5269  */
5270 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5271 
5272 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5273 
5274 /* reg_pbmc_buf_lossy
5275  * The field indicates if the buffer is lossy.
5276  * 0 - Lossless
5277  * 1 - Lossy
5278  * Access: RW
5279  */
5280 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5281 
5282 /* reg_pbmc_buf_epsb
5283  * Eligible for Port Shared buffer.
5284  * If epsb is set, packets assigned to buffer are allowed to insert the port
5285  * shared buffer.
5286  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5287  * Access: RW
5288  */
5289 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5290 
5291 /* reg_pbmc_buf_size
5292  * The part of the packet buffer array is allocated for the specific buffer.
5293  * Units are represented in cells.
5294  * Access: RW
5295  */
5296 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5297 
5298 /* reg_pbmc_buf_xoff_threshold
5299  * Once the amount of data in the buffer goes above this value, device
5300  * starts sending PFC frames for all priorities associated with the
5301  * buffer. Units are represented in cells. Reserved in case of lossy
5302  * buffer.
5303  * Access: RW
5304  *
5305  * Note: In Spectrum, reserved for buffer[9].
5306  */
5307 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5308 		     0x08, 0x04, false);
5309 
5310 /* reg_pbmc_buf_xon_threshold
5311  * When the amount of data in the buffer goes below this value, device
5312  * stops sending PFC frames for the priorities associated with the
5313  * buffer. Units are represented in cells. Reserved in case of lossy
5314  * buffer.
5315  * Access: RW
5316  *
5317  * Note: In Spectrum, reserved for buffer[9].
5318  */
5319 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5320 		     0x08, 0x04, false);
5321 
5322 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5323 				       u16 xoff_timer_value, u16 xoff_refresh)
5324 {
5325 	MLXSW_REG_ZERO(pbmc, payload);
5326 	mlxsw_reg_pbmc_local_port_set(payload, local_port);
5327 	mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5328 	mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5329 }
5330 
5331 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5332 						    int buf_index,
5333 						    u16 size)
5334 {
5335 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5336 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5337 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5338 }
5339 
5340 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5341 						       int buf_index, u16 size,
5342 						       u16 threshold)
5343 {
5344 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5345 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5346 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5347 	mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5348 	mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5349 }
5350 
5351 /* PSPA - Port Switch Partition Allocation
5352  * ---------------------------------------
5353  * Controls the association of a port with a switch partition and enables
5354  * configuring ports as stacking ports.
5355  */
5356 #define MLXSW_REG_PSPA_ID 0x500D
5357 #define MLXSW_REG_PSPA_LEN 0x8
5358 
5359 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5360 
5361 /* reg_pspa_swid
5362  * Switch partition ID.
5363  * Access: RW
5364  */
5365 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5366 
5367 /* reg_pspa_local_port
5368  * Local port number.
5369  * Access: Index
5370  */
5371 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5372 
5373 /* reg_pspa_sub_port
5374  * Virtual port within the local port. Set to 0 when virtual ports are
5375  * disabled on the local port.
5376  * Access: Index
5377  */
5378 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5379 
5380 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5381 {
5382 	MLXSW_REG_ZERO(pspa, payload);
5383 	mlxsw_reg_pspa_swid_set(payload, swid);
5384 	mlxsw_reg_pspa_local_port_set(payload, local_port);
5385 	mlxsw_reg_pspa_sub_port_set(payload, 0);
5386 }
5387 
5388 /* PPLR - Port Physical Loopback Register
5389  * --------------------------------------
5390  * This register allows configuration of the port's loopback mode.
5391  */
5392 #define MLXSW_REG_PPLR_ID 0x5018
5393 #define MLXSW_REG_PPLR_LEN 0x8
5394 
5395 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5396 
5397 /* reg_pplr_local_port
5398  * Local port number.
5399  * Access: Index
5400  */
5401 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5402 
5403 /* Phy local loopback. When set the port's egress traffic is looped back
5404  * to the receiver and the port transmitter is disabled.
5405  */
5406 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5407 
5408 /* reg_pplr_lb_en
5409  * Loopback enable.
5410  * Access: RW
5411  */
5412 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5413 
5414 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5415 				       bool phy_local)
5416 {
5417 	MLXSW_REG_ZERO(pplr, payload);
5418 	mlxsw_reg_pplr_local_port_set(payload, local_port);
5419 	mlxsw_reg_pplr_lb_en_set(payload,
5420 				 phy_local ?
5421 				 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5422 }
5423 
5424 /* PMTM - Port Module Type Mapping Register
5425  * ----------------------------------------
5426  * The PMTM allows query or configuration of module types.
5427  */
5428 #define MLXSW_REG_PMTM_ID 0x5067
5429 #define MLXSW_REG_PMTM_LEN 0x10
5430 
5431 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);
5432 
5433 /* reg_pmtm_module
5434  * Module number.
5435  * Access: Index
5436  */
5437 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
5438 
5439 enum mlxsw_reg_pmtm_module_type {
5440 	/* Backplane with 4 lanes */
5441 	MLXSW_REG_PMTM_MODULE_TYPE_BP_4X,
5442 	/* QSFP */
5443 	MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP,
5444 	/* SFP */
5445 	MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP,
5446 	/* Backplane with single lane */
5447 	MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4,
5448 	/* Backplane with two lane */
5449 	MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8,
5450 	/* Chip2Chip */
5451 	MLXSW_REG_PMTM_MODULE_TYPE_C2C = 10,
5452 };
5453 
5454 /* reg_pmtm_module_type
5455  * Module type.
5456  * Access: RW
5457  */
5458 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4);
5459 
5460 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module)
5461 {
5462 	MLXSW_REG_ZERO(pmtm, payload);
5463 	mlxsw_reg_pmtm_module_set(payload, module);
5464 }
5465 
5466 static inline void
5467 mlxsw_reg_pmtm_unpack(char *payload,
5468 		      enum mlxsw_reg_pmtm_module_type *module_type)
5469 {
5470 	*module_type = mlxsw_reg_pmtm_module_type_get(payload);
5471 }
5472 
5473 /* HTGT - Host Trap Group Table
5474  * ----------------------------
5475  * Configures the properties for forwarding to CPU.
5476  */
5477 #define MLXSW_REG_HTGT_ID 0x7002
5478 #define MLXSW_REG_HTGT_LEN 0x20
5479 
5480 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5481 
5482 /* reg_htgt_swid
5483  * Switch partition ID.
5484  * Access: Index
5485  */
5486 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5487 
5488 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0	/* For locally attached CPU */
5489 
5490 /* reg_htgt_type
5491  * CPU path type.
5492  * Access: RW
5493  */
5494 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5495 
5496 enum mlxsw_reg_htgt_trap_group {
5497 	MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5498 	MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
5499 	MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
5500 	MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5501 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5502 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5503 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
5504 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5505 	MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5506 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5507 	MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5508 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
5509 	MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
5510 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5511 	MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
5512 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5513 	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5514 	MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
5515 	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5516 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
5517 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
5518 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5519 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
5520 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
5521 	MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
5522 
5523 	__MLXSW_REG_HTGT_TRAP_GROUP_MAX,
5524 	MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
5525 };
5526 
5527 enum mlxsw_reg_htgt_discard_trap_group {
5528 	MLXSW_REG_HTGT_DISCARD_TRAP_GROUP_BASE = MLXSW_REG_HTGT_TRAP_GROUP_MAX,
5529 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
5530 	MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,
5531 	MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,
5532 };
5533 
5534 /* reg_htgt_trap_group
5535  * Trap group number. User defined number specifying which trap groups
5536  * should be forwarded to the CPU. The mapping between trap IDs and trap
5537  * groups is configured using HPKT register.
5538  * Access: Index
5539  */
5540 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5541 
5542 enum {
5543 	MLXSW_REG_HTGT_POLICER_DISABLE,
5544 	MLXSW_REG_HTGT_POLICER_ENABLE,
5545 };
5546 
5547 /* reg_htgt_pide
5548  * Enable policer ID specified using 'pid' field.
5549  * Access: RW
5550  */
5551 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
5552 
5553 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
5554 
5555 /* reg_htgt_pid
5556  * Policer ID for the trap group.
5557  * Access: RW
5558  */
5559 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
5560 
5561 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
5562 
5563 /* reg_htgt_mirror_action
5564  * Mirror action to use.
5565  * 0 - Trap to CPU.
5566  * 1 - Trap to CPU and mirror to a mirroring agent.
5567  * 2 - Mirror to a mirroring agent and do not trap to CPU.
5568  * Access: RW
5569  *
5570  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
5571  */
5572 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
5573 
5574 /* reg_htgt_mirroring_agent
5575  * Mirroring agent.
5576  * Access: RW
5577  */
5578 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
5579 
5580 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
5581 
5582 /* reg_htgt_priority
5583  * Trap group priority.
5584  * In case a packet matches multiple classification rules, the packet will
5585  * only be trapped once, based on the trap ID associated with the group (via
5586  * register HPKT) with the highest priority.
5587  * Supported values are 0-7, with 7 represnting the highest priority.
5588  * Access: RW
5589  *
5590  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
5591  * by the 'trap_group' field.
5592  */
5593 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
5594 
5595 #define MLXSW_REG_HTGT_DEFAULT_TC 7
5596 
5597 /* reg_htgt_local_path_cpu_tclass
5598  * CPU ingress traffic class for the trap group.
5599  * Access: RW
5600  */
5601 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
5602 
5603 enum mlxsw_reg_htgt_local_path_rdq {
5604 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
5605 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
5606 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
5607 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
5608 };
5609 /* reg_htgt_local_path_rdq
5610  * Receive descriptor queue (RDQ) to use for the trap group.
5611  * Access: RW
5612  */
5613 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
5614 
5615 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
5616 				       u8 priority, u8 tc)
5617 {
5618 	MLXSW_REG_ZERO(htgt, payload);
5619 
5620 	if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
5621 		mlxsw_reg_htgt_pide_set(payload,
5622 					MLXSW_REG_HTGT_POLICER_DISABLE);
5623 	} else {
5624 		mlxsw_reg_htgt_pide_set(payload,
5625 					MLXSW_REG_HTGT_POLICER_ENABLE);
5626 		mlxsw_reg_htgt_pid_set(payload, policer_id);
5627 	}
5628 
5629 	mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
5630 	mlxsw_reg_htgt_trap_group_set(payload, group);
5631 	mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
5632 	mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
5633 	mlxsw_reg_htgt_priority_set(payload, priority);
5634 	mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
5635 	mlxsw_reg_htgt_local_path_rdq_set(payload, group);
5636 }
5637 
5638 /* HPKT - Host Packet Trap
5639  * -----------------------
5640  * Configures trap IDs inside trap groups.
5641  */
5642 #define MLXSW_REG_HPKT_ID 0x7003
5643 #define MLXSW_REG_HPKT_LEN 0x10
5644 
5645 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
5646 
5647 enum {
5648 	MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
5649 	MLXSW_REG_HPKT_ACK_REQUIRED,
5650 };
5651 
5652 /* reg_hpkt_ack
5653  * Require acknowledgements from the host for events.
5654  * If set, then the device will wait for the event it sent to be acknowledged
5655  * by the host. This option is only relevant for event trap IDs.
5656  * Access: RW
5657  *
5658  * Note: Currently not supported by firmware.
5659  */
5660 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
5661 
5662 enum mlxsw_reg_hpkt_action {
5663 	MLXSW_REG_HPKT_ACTION_FORWARD,
5664 	MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
5665 	MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
5666 	MLXSW_REG_HPKT_ACTION_DISCARD,
5667 	MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5668 	MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5669 	MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
5670 	MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
5671 };
5672 
5673 /* reg_hpkt_action
5674  * Action to perform on packet when trapped.
5675  * 0 - No action. Forward to CPU based on switching rules.
5676  * 1 - Trap to CPU (CPU receives sole copy).
5677  * 2 - Mirror to CPU (CPU receives a replica of the packet).
5678  * 3 - Discard.
5679  * 4 - Soft discard (allow other traps to act on the packet).
5680  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
5681  * 6 - Trap to CPU (CPU receives sole copy) and count it as error.
5682  * 15 - Restore the firmware's default action.
5683  * Access: RW
5684  *
5685  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
5686  * addressed to the CPU.
5687  */
5688 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5689 
5690 /* reg_hpkt_trap_group
5691  * Trap group to associate the trap with.
5692  * Access: RW
5693  */
5694 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5695 
5696 /* reg_hpkt_trap_id
5697  * Trap ID.
5698  * Access: Index
5699  *
5700  * Note: A trap ID can only be associated with a single trap group. The device
5701  * will associate the trap ID with the last trap group configured.
5702  */
5703 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5704 
5705 enum {
5706 	MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5707 	MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5708 	MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5709 };
5710 
5711 /* reg_hpkt_ctrl
5712  * Configure dedicated buffer resources for control packets.
5713  * Ignored by SwitchX-2.
5714  * 0 - Keep factory defaults.
5715  * 1 - Do not use control buffer for this trap ID.
5716  * 2 - Use control buffer for this trap ID.
5717  * Access: RW
5718  */
5719 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5720 
5721 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5722 				       enum mlxsw_reg_htgt_trap_group trap_group,
5723 				       bool is_ctrl)
5724 {
5725 	MLXSW_REG_ZERO(hpkt, payload);
5726 	mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5727 	mlxsw_reg_hpkt_action_set(payload, action);
5728 	mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5729 	mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5730 	mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5731 				MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5732 				MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5733 }
5734 
5735 /* RGCR - Router General Configuration Register
5736  * --------------------------------------------
5737  * The register is used for setting up the router configuration.
5738  */
5739 #define MLXSW_REG_RGCR_ID 0x8001
5740 #define MLXSW_REG_RGCR_LEN 0x28
5741 
5742 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5743 
5744 /* reg_rgcr_ipv4_en
5745  * IPv4 router enable.
5746  * Access: RW
5747  */
5748 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5749 
5750 /* reg_rgcr_ipv6_en
5751  * IPv6 router enable.
5752  * Access: RW
5753  */
5754 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5755 
5756 /* reg_rgcr_max_router_interfaces
5757  * Defines the maximum number of active router interfaces for all virtual
5758  * routers.
5759  * Access: RW
5760  */
5761 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5762 
5763 /* reg_rgcr_usp
5764  * Update switch priority and packet color.
5765  * 0 - Preserve the value of Switch Priority and packet color.
5766  * 1 - Recalculate the value of Switch Priority and packet color.
5767  * Access: RW
5768  *
5769  * Note: Not supported by SwitchX and SwitchX-2.
5770  */
5771 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5772 
5773 /* reg_rgcr_pcp_rw
5774  * Indicates how to handle the pcp_rewrite_en value:
5775  * 0 - Preserve the value of pcp_rewrite_en.
5776  * 2 - Disable PCP rewrite.
5777  * 3 - Enable PCP rewrite.
5778  * Access: RW
5779  *
5780  * Note: Not supported by SwitchX and SwitchX-2.
5781  */
5782 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5783 
5784 /* reg_rgcr_activity_dis
5785  * Activity disable:
5786  * 0 - Activity will be set when an entry is hit (default).
5787  * 1 - Activity will not be set when an entry is hit.
5788  *
5789  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5790  * (RALUE).
5791  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5792  * Entry (RAUHT).
5793  * Bits 2:7 are reserved.
5794  * Access: RW
5795  *
5796  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5797  */
5798 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5799 
5800 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5801 				       bool ipv6_en)
5802 {
5803 	MLXSW_REG_ZERO(rgcr, payload);
5804 	mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5805 	mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5806 }
5807 
5808 /* RITR - Router Interface Table Register
5809  * --------------------------------------
5810  * The register is used to configure the router interface table.
5811  */
5812 #define MLXSW_REG_RITR_ID 0x8002
5813 #define MLXSW_REG_RITR_LEN 0x40
5814 
5815 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5816 
5817 /* reg_ritr_enable
5818  * Enables routing on the router interface.
5819  * Access: RW
5820  */
5821 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5822 
5823 /* reg_ritr_ipv4
5824  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5825  * interface.
5826  * Access: RW
5827  */
5828 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5829 
5830 /* reg_ritr_ipv6
5831  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5832  * interface.
5833  * Access: RW
5834  */
5835 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5836 
5837 /* reg_ritr_ipv4_mc
5838  * IPv4 multicast routing enable.
5839  * Access: RW
5840  */
5841 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5842 
5843 /* reg_ritr_ipv6_mc
5844  * IPv6 multicast routing enable.
5845  * Access: RW
5846  */
5847 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5848 
5849 enum mlxsw_reg_ritr_if_type {
5850 	/* VLAN interface. */
5851 	MLXSW_REG_RITR_VLAN_IF,
5852 	/* FID interface. */
5853 	MLXSW_REG_RITR_FID_IF,
5854 	/* Sub-port interface. */
5855 	MLXSW_REG_RITR_SP_IF,
5856 	/* Loopback Interface. */
5857 	MLXSW_REG_RITR_LOOPBACK_IF,
5858 };
5859 
5860 /* reg_ritr_type
5861  * Router interface type as per enum mlxsw_reg_ritr_if_type.
5862  * Access: RW
5863  */
5864 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5865 
5866 enum {
5867 	MLXSW_REG_RITR_RIF_CREATE,
5868 	MLXSW_REG_RITR_RIF_DEL,
5869 };
5870 
5871 /* reg_ritr_op
5872  * Opcode:
5873  * 0 - Create or edit RIF.
5874  * 1 - Delete RIF.
5875  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5876  * is not supported. An interface must be deleted and re-created in order
5877  * to update properties.
5878  * Access: WO
5879  */
5880 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5881 
5882 /* reg_ritr_rif
5883  * Router interface index. A pointer to the Router Interface Table.
5884  * Access: Index
5885  */
5886 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5887 
5888 /* reg_ritr_ipv4_fe
5889  * IPv4 Forwarding Enable.
5890  * Enables routing of IPv4 traffic on the router interface. When disabled,
5891  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5892  * Not supported in SwitchX-2.
5893  * Access: RW
5894  */
5895 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5896 
5897 /* reg_ritr_ipv6_fe
5898  * IPv6 Forwarding Enable.
5899  * Enables routing of IPv6 traffic on the router interface. When disabled,
5900  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5901  * Not supported in SwitchX-2.
5902  * Access: RW
5903  */
5904 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5905 
5906 /* reg_ritr_ipv4_mc_fe
5907  * IPv4 Multicast Forwarding Enable.
5908  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5909  * will be enabled.
5910  * Access: RW
5911  */
5912 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5913 
5914 /* reg_ritr_ipv6_mc_fe
5915  * IPv6 Multicast Forwarding Enable.
5916  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5917  * will be enabled.
5918  * Access: RW
5919  */
5920 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5921 
5922 /* reg_ritr_lb_en
5923  * Loop-back filter enable for unicast packets.
5924  * If the flag is set then loop-back filter for unicast packets is
5925  * implemented on the RIF. Multicast packets are always subject to
5926  * loop-back filtering.
5927  * Access: RW
5928  */
5929 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5930 
5931 /* reg_ritr_virtual_router
5932  * Virtual router ID associated with the router interface.
5933  * Access: RW
5934  */
5935 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5936 
5937 /* reg_ritr_mtu
5938  * Router interface MTU.
5939  * Access: RW
5940  */
5941 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5942 
5943 /* reg_ritr_if_swid
5944  * Switch partition ID.
5945  * Access: RW
5946  */
5947 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5948 
5949 /* reg_ritr_if_mac
5950  * Router interface MAC address.
5951  * In Spectrum, all MAC addresses must have the same 38 MSBits.
5952  * Access: RW
5953  */
5954 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5955 
5956 /* reg_ritr_if_vrrp_id_ipv6
5957  * VRRP ID for IPv6
5958  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5959  * Access: RW
5960  */
5961 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5962 
5963 /* reg_ritr_if_vrrp_id_ipv4
5964  * VRRP ID for IPv4
5965  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5966  * Access: RW
5967  */
5968 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5969 
5970 /* VLAN Interface */
5971 
5972 /* reg_ritr_vlan_if_vid
5973  * VLAN ID.
5974  * Access: RW
5975  */
5976 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5977 
5978 /* FID Interface */
5979 
5980 /* reg_ritr_fid_if_fid
5981  * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5982  * the vFID range are supported.
5983  * Access: RW
5984  */
5985 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5986 
5987 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5988 					  enum mlxsw_reg_ritr_if_type rif_type,
5989 					  u16 fid)
5990 {
5991 	if (rif_type == MLXSW_REG_RITR_FID_IF)
5992 		mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5993 	else
5994 		mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5995 }
5996 
5997 /* Sub-port Interface */
5998 
5999 /* reg_ritr_sp_if_lag
6000  * LAG indication. When this bit is set the system_port field holds the
6001  * LAG identifier.
6002  * Access: RW
6003  */
6004 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
6005 
6006 /* reg_ritr_sp_system_port
6007  * Port unique indentifier. When lag bit is set, this field holds the
6008  * lag_id in bits 0:9.
6009  * Access: RW
6010  */
6011 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
6012 
6013 /* reg_ritr_sp_if_vid
6014  * VLAN ID.
6015  * Access: RW
6016  */
6017 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
6018 
6019 /* Loopback Interface */
6020 
6021 enum mlxsw_reg_ritr_loopback_protocol {
6022 	/* IPinIP IPv4 underlay Unicast */
6023 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
6024 	/* IPinIP IPv6 underlay Unicast */
6025 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
6026 	/* IPinIP generic - used for Spectrum-2 underlay RIF */
6027 	MLXSW_REG_RITR_LOOPBACK_GENERIC,
6028 };
6029 
6030 /* reg_ritr_loopback_protocol
6031  * Access: RW
6032  */
6033 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
6034 
6035 enum mlxsw_reg_ritr_loopback_ipip_type {
6036 	/* Tunnel is IPinIP. */
6037 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
6038 	/* Tunnel is GRE, no key. */
6039 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
6040 	/* Tunnel is GRE, with a key. */
6041 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
6042 };
6043 
6044 /* reg_ritr_loopback_ipip_type
6045  * Encapsulation type.
6046  * Access: RW
6047  */
6048 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
6049 
6050 enum mlxsw_reg_ritr_loopback_ipip_options {
6051 	/* The key is defined by gre_key. */
6052 	MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
6053 };
6054 
6055 /* reg_ritr_loopback_ipip_options
6056  * Access: RW
6057  */
6058 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
6059 
6060 /* reg_ritr_loopback_ipip_uvr
6061  * Underlay Virtual Router ID.
6062  * Range is 0..cap_max_virtual_routers-1.
6063  * Reserved for Spectrum-2.
6064  * Access: RW
6065  */
6066 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
6067 
6068 /* reg_ritr_loopback_ipip_underlay_rif
6069  * Underlay ingress router interface.
6070  * Reserved for Spectrum.
6071  * Access: RW
6072  */
6073 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
6074 
6075 /* reg_ritr_loopback_ipip_usip*
6076  * Encapsulation Underlay source IP.
6077  * Access: RW
6078  */
6079 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
6080 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
6081 
6082 /* reg_ritr_loopback_ipip_gre_key
6083  * GRE Key.
6084  * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
6085  * Access: RW
6086  */
6087 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
6088 
6089 /* Shared between ingress/egress */
6090 enum mlxsw_reg_ritr_counter_set_type {
6091 	/* No Count. */
6092 	MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
6093 	/* Basic. Used for router interfaces, counting the following:
6094 	 *	- Error and Discard counters.
6095 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
6096 	 *	  same set of counters for the different type of traffic
6097 	 *	  (IPv4, IPv6 and mpls).
6098 	 */
6099 	MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
6100 };
6101 
6102 /* reg_ritr_ingress_counter_index
6103  * Counter Index for flow counter.
6104  * Access: RW
6105  */
6106 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
6107 
6108 /* reg_ritr_ingress_counter_set_type
6109  * Igress Counter Set Type for router interface counter.
6110  * Access: RW
6111  */
6112 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6113 
6114 /* reg_ritr_egress_counter_index
6115  * Counter Index for flow counter.
6116  * Access: RW
6117  */
6118 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6119 
6120 /* reg_ritr_egress_counter_set_type
6121  * Egress Counter Set Type for router interface counter.
6122  * Access: RW
6123  */
6124 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6125 
6126 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6127 					       bool enable, bool egress)
6128 {
6129 	enum mlxsw_reg_ritr_counter_set_type set_type;
6130 
6131 	if (enable)
6132 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6133 	else
6134 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6135 	mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6136 
6137 	if (egress)
6138 		mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6139 	else
6140 		mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6141 }
6142 
6143 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6144 {
6145 	MLXSW_REG_ZERO(ritr, payload);
6146 	mlxsw_reg_ritr_rif_set(payload, rif);
6147 }
6148 
6149 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6150 					     u16 system_port, u16 vid)
6151 {
6152 	mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6153 	mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6154 	mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6155 }
6156 
6157 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6158 				       enum mlxsw_reg_ritr_if_type type,
6159 				       u16 rif, u16 vr_id, u16 mtu)
6160 {
6161 	bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6162 
6163 	MLXSW_REG_ZERO(ritr, payload);
6164 	mlxsw_reg_ritr_enable_set(payload, enable);
6165 	mlxsw_reg_ritr_ipv4_set(payload, 1);
6166 	mlxsw_reg_ritr_ipv6_set(payload, 1);
6167 	mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6168 	mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6169 	mlxsw_reg_ritr_type_set(payload, type);
6170 	mlxsw_reg_ritr_op_set(payload, op);
6171 	mlxsw_reg_ritr_rif_set(payload, rif);
6172 	mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6173 	mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6174 	mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6175 	mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6176 	mlxsw_reg_ritr_lb_en_set(payload, 1);
6177 	mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6178 	mlxsw_reg_ritr_mtu_set(payload, mtu);
6179 }
6180 
6181 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6182 {
6183 	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6184 }
6185 
6186 static inline void
6187 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6188 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6189 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
6190 			    u16 uvr_id, u16 underlay_rif, u32 gre_key)
6191 {
6192 	mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6193 	mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6194 	mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6195 	mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6196 	mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6197 }
6198 
6199 static inline void
6200 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6201 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6202 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
6203 			    u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6204 {
6205 	mlxsw_reg_ritr_loopback_protocol_set(payload,
6206 				    MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6207 	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6208 						 uvr_id, underlay_rif, gre_key);
6209 	mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6210 }
6211 
6212 /* RTAR - Router TCAM Allocation Register
6213  * --------------------------------------
6214  * This register is used for allocation of regions in the TCAM table.
6215  */
6216 #define MLXSW_REG_RTAR_ID 0x8004
6217 #define MLXSW_REG_RTAR_LEN 0x20
6218 
6219 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6220 
6221 enum mlxsw_reg_rtar_op {
6222 	MLXSW_REG_RTAR_OP_ALLOCATE,
6223 	MLXSW_REG_RTAR_OP_RESIZE,
6224 	MLXSW_REG_RTAR_OP_DEALLOCATE,
6225 };
6226 
6227 /* reg_rtar_op
6228  * Access: WO
6229  */
6230 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6231 
6232 enum mlxsw_reg_rtar_key_type {
6233 	MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6234 	MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6235 };
6236 
6237 /* reg_rtar_key_type
6238  * TCAM key type for the region.
6239  * Access: WO
6240  */
6241 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6242 
6243 /* reg_rtar_region_size
6244  * TCAM region size. When allocating/resizing this is the requested
6245  * size, the response is the actual size.
6246  * Note: Actual size may be larger than requested.
6247  * Reserved for op = Deallocate
6248  * Access: WO
6249  */
6250 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6251 
6252 static inline void mlxsw_reg_rtar_pack(char *payload,
6253 				       enum mlxsw_reg_rtar_op op,
6254 				       enum mlxsw_reg_rtar_key_type key_type,
6255 				       u16 region_size)
6256 {
6257 	MLXSW_REG_ZERO(rtar, payload);
6258 	mlxsw_reg_rtar_op_set(payload, op);
6259 	mlxsw_reg_rtar_key_type_set(payload, key_type);
6260 	mlxsw_reg_rtar_region_size_set(payload, region_size);
6261 }
6262 
6263 /* RATR - Router Adjacency Table Register
6264  * --------------------------------------
6265  * The RATR register is used to configure the Router Adjacency (next-hop)
6266  * Table.
6267  */
6268 #define MLXSW_REG_RATR_ID 0x8008
6269 #define MLXSW_REG_RATR_LEN 0x2C
6270 
6271 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6272 
6273 enum mlxsw_reg_ratr_op {
6274 	/* Read */
6275 	MLXSW_REG_RATR_OP_QUERY_READ = 0,
6276 	/* Read and clear activity */
6277 	MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6278 	/* Write Adjacency entry */
6279 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6280 	/* Write Adjacency entry only if the activity is cleared.
6281 	 * The write may not succeed if the activity is set. There is not
6282 	 * direct feedback if the write has succeeded or not, however
6283 	 * the get will reveal the actual entry (SW can compare the get
6284 	 * response to the set command).
6285 	 */
6286 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6287 };
6288 
6289 /* reg_ratr_op
6290  * Note that Write operation may also be used for updating
6291  * counter_set_type and counter_index. In this case all other
6292  * fields must not be updated.
6293  * Access: OP
6294  */
6295 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6296 
6297 /* reg_ratr_v
6298  * Valid bit. Indicates if the adjacency entry is valid.
6299  * Note: the device may need some time before reusing an invalidated
6300  * entry. During this time the entry can not be reused. It is
6301  * recommended to use another entry before reusing an invalidated
6302  * entry (e.g. software can put it at the end of the list for
6303  * reusing). Trying to access an invalidated entry not yet cleared
6304  * by the device results with failure indicating "Try Again" status.
6305  * When valid is '0' then egress_router_interface,trap_action,
6306  * adjacency_parameters and counters are reserved
6307  * Access: RW
6308  */
6309 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6310 
6311 /* reg_ratr_a
6312  * Activity. Set for new entries. Set if a packet lookup has hit on
6313  * the specific entry. To clear the a bit, use "clear activity".
6314  * Access: RO
6315  */
6316 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6317 
6318 enum mlxsw_reg_ratr_type {
6319 	/* Ethernet */
6320 	MLXSW_REG_RATR_TYPE_ETHERNET,
6321 	/* IPoIB Unicast without GRH.
6322 	 * Reserved for Spectrum.
6323 	 */
6324 	MLXSW_REG_RATR_TYPE_IPOIB_UC,
6325 	/* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
6326 	 * adjacency).
6327 	 * Reserved for Spectrum.
6328 	 */
6329 	MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6330 	/* IPoIB Multicast.
6331 	 * Reserved for Spectrum.
6332 	 */
6333 	MLXSW_REG_RATR_TYPE_IPOIB_MC,
6334 	/* MPLS.
6335 	 * Reserved for SwitchX/-2.
6336 	 */
6337 	MLXSW_REG_RATR_TYPE_MPLS,
6338 	/* IPinIP Encap.
6339 	 * Reserved for SwitchX/-2.
6340 	 */
6341 	MLXSW_REG_RATR_TYPE_IPIP,
6342 };
6343 
6344 /* reg_ratr_type
6345  * Adjacency entry type.
6346  * Access: RW
6347  */
6348 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6349 
6350 /* reg_ratr_adjacency_index_low
6351  * Bits 15:0 of index into the adjacency table.
6352  * For SwitchX and SwitchX-2, the adjacency table is linear and
6353  * used for adjacency entries only.
6354  * For Spectrum, the index is to the KVD linear.
6355  * Access: Index
6356  */
6357 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6358 
6359 /* reg_ratr_egress_router_interface
6360  * Range is 0 .. cap_max_router_interfaces - 1
6361  * Access: RW
6362  */
6363 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6364 
6365 enum mlxsw_reg_ratr_trap_action {
6366 	MLXSW_REG_RATR_TRAP_ACTION_NOP,
6367 	MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6368 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6369 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6370 	MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6371 };
6372 
6373 /* reg_ratr_trap_action
6374  * see mlxsw_reg_ratr_trap_action
6375  * Access: RW
6376  */
6377 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6378 
6379 /* reg_ratr_adjacency_index_high
6380  * Bits 23:16 of the adjacency_index.
6381  * Access: Index
6382  */
6383 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6384 
6385 enum mlxsw_reg_ratr_trap_id {
6386 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6387 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6388 };
6389 
6390 /* reg_ratr_trap_id
6391  * Trap ID to be reported to CPU.
6392  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6393  * For trap_action of NOP, MIRROR and DISCARD_ERROR
6394  * Access: RW
6395  */
6396 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6397 
6398 /* reg_ratr_eth_destination_mac
6399  * MAC address of the destination next-hop.
6400  * Access: RW
6401  */
6402 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6403 
6404 enum mlxsw_reg_ratr_ipip_type {
6405 	/* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
6406 	MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6407 	/* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
6408 	MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6409 };
6410 
6411 /* reg_ratr_ipip_type
6412  * Underlay destination ip type.
6413  * Note: the type field must match the protocol of the router interface.
6414  * Access: RW
6415  */
6416 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6417 
6418 /* reg_ratr_ipip_ipv4_udip
6419  * Underlay ipv4 dip.
6420  * Reserved when ipip_type is IPv6.
6421  * Access: RW
6422  */
6423 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6424 
6425 /* reg_ratr_ipip_ipv6_ptr
6426  * Pointer to IPv6 underlay destination ip address.
6427  * For Spectrum: Pointer to KVD linear space.
6428  * Access: RW
6429  */
6430 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6431 
6432 enum mlxsw_reg_flow_counter_set_type {
6433 	/* No count */
6434 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6435 	/* Count packets and bytes */
6436 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6437 	/* Count only packets */
6438 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6439 };
6440 
6441 /* reg_ratr_counter_set_type
6442  * Counter set type for flow counters
6443  * Access: RW
6444  */
6445 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6446 
6447 /* reg_ratr_counter_index
6448  * Counter index for flow counters
6449  * Access: RW
6450  */
6451 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6452 
6453 static inline void
6454 mlxsw_reg_ratr_pack(char *payload,
6455 		    enum mlxsw_reg_ratr_op op, bool valid,
6456 		    enum mlxsw_reg_ratr_type type,
6457 		    u32 adjacency_index, u16 egress_rif)
6458 {
6459 	MLXSW_REG_ZERO(ratr, payload);
6460 	mlxsw_reg_ratr_op_set(payload, op);
6461 	mlxsw_reg_ratr_v_set(payload, valid);
6462 	mlxsw_reg_ratr_type_set(payload, type);
6463 	mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6464 	mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6465 	mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6466 }
6467 
6468 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6469 						 const char *dest_mac)
6470 {
6471 	mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6472 }
6473 
6474 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6475 {
6476 	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6477 	mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6478 }
6479 
6480 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6481 					       bool counter_enable)
6482 {
6483 	enum mlxsw_reg_flow_counter_set_type set_type;
6484 
6485 	if (counter_enable)
6486 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6487 	else
6488 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6489 
6490 	mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6491 	mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6492 }
6493 
6494 /* RDPM - Router DSCP to Priority Mapping
6495  * --------------------------------------
6496  * Controls the mapping from DSCP field to switch priority on routed packets
6497  */
6498 #define MLXSW_REG_RDPM_ID 0x8009
6499 #define MLXSW_REG_RDPM_BASE_LEN 0x00
6500 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6501 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6502 #define MLXSW_REG_RDPM_LEN 0x40
6503 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6504 				   MLXSW_REG_RDPM_LEN - \
6505 				   MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6506 
6507 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6508 
6509 /* reg_dscp_entry_e
6510  * Enable update of the specific entry
6511  * Access: Index
6512  */
6513 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6514 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6515 
6516 /* reg_dscp_entry_prio
6517  * Switch Priority
6518  * Access: RW
6519  */
6520 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6521 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6522 
6523 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6524 				       u8 prio)
6525 {
6526 	mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6527 	mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6528 }
6529 
6530 /* RICNT - Router Interface Counter Register
6531  * -----------------------------------------
6532  * The RICNT register retrieves per port performance counters
6533  */
6534 #define MLXSW_REG_RICNT_ID 0x800B
6535 #define MLXSW_REG_RICNT_LEN 0x100
6536 
6537 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6538 
6539 /* reg_ricnt_counter_index
6540  * Counter index
6541  * Access: RW
6542  */
6543 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6544 
6545 enum mlxsw_reg_ricnt_counter_set_type {
6546 	/* No Count. */
6547 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6548 	/* Basic. Used for router interfaces, counting the following:
6549 	 *	- Error and Discard counters.
6550 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
6551 	 *	  same set of counters for the different type of traffic
6552 	 *	  (IPv4, IPv6 and mpls).
6553 	 */
6554 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
6555 };
6556 
6557 /* reg_ricnt_counter_set_type
6558  * Counter Set Type for router interface counter
6559  * Access: RW
6560  */
6561 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
6562 
6563 enum mlxsw_reg_ricnt_opcode {
6564 	/* Nop. Supported only for read access*/
6565 	MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
6566 	/* Clear. Setting the clr bit will reset the counter value for
6567 	 * all counters of the specified Router Interface.
6568 	 */
6569 	MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
6570 };
6571 
6572 /* reg_ricnt_opcode
6573  * Opcode
6574  * Access: RW
6575  */
6576 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
6577 
6578 /* reg_ricnt_good_unicast_packets
6579  * good unicast packets.
6580  * Access: RW
6581  */
6582 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
6583 
6584 /* reg_ricnt_good_multicast_packets
6585  * good multicast packets.
6586  * Access: RW
6587  */
6588 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
6589 
6590 /* reg_ricnt_good_broadcast_packets
6591  * good broadcast packets
6592  * Access: RW
6593  */
6594 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
6595 
6596 /* reg_ricnt_good_unicast_bytes
6597  * A count of L3 data and padding octets not including L2 headers
6598  * for good unicast frames.
6599  * Access: RW
6600  */
6601 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
6602 
6603 /* reg_ricnt_good_multicast_bytes
6604  * A count of L3 data and padding octets not including L2 headers
6605  * for good multicast frames.
6606  * Access: RW
6607  */
6608 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
6609 
6610 /* reg_ritr_good_broadcast_bytes
6611  * A count of L3 data and padding octets not including L2 headers
6612  * for good broadcast frames.
6613  * Access: RW
6614  */
6615 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
6616 
6617 /* reg_ricnt_error_packets
6618  * A count of errored frames that do not pass the router checks.
6619  * Access: RW
6620  */
6621 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
6622 
6623 /* reg_ricnt_discrad_packets
6624  * A count of non-errored frames that do not pass the router checks.
6625  * Access: RW
6626  */
6627 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
6628 
6629 /* reg_ricnt_error_bytes
6630  * A count of L3 data and padding octets not including L2 headers
6631  * for errored frames.
6632  * Access: RW
6633  */
6634 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
6635 
6636 /* reg_ricnt_discard_bytes
6637  * A count of L3 data and padding octets not including L2 headers
6638  * for non-errored frames that do not pass the router checks.
6639  * Access: RW
6640  */
6641 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
6642 
6643 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
6644 					enum mlxsw_reg_ricnt_opcode op)
6645 {
6646 	MLXSW_REG_ZERO(ricnt, payload);
6647 	mlxsw_reg_ricnt_op_set(payload, op);
6648 	mlxsw_reg_ricnt_counter_index_set(payload, index);
6649 	mlxsw_reg_ricnt_counter_set_type_set(payload,
6650 					     MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
6651 }
6652 
6653 /* RRCR - Router Rules Copy Register Layout
6654  * ----------------------------------------
6655  * This register is used for moving and copying route entry rules.
6656  */
6657 #define MLXSW_REG_RRCR_ID 0x800F
6658 #define MLXSW_REG_RRCR_LEN 0x24
6659 
6660 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
6661 
6662 enum mlxsw_reg_rrcr_op {
6663 	/* Move rules */
6664 	MLXSW_REG_RRCR_OP_MOVE,
6665 	/* Copy rules */
6666 	MLXSW_REG_RRCR_OP_COPY,
6667 };
6668 
6669 /* reg_rrcr_op
6670  * Access: WO
6671  */
6672 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
6673 
6674 /* reg_rrcr_offset
6675  * Offset within the region from which to copy/move.
6676  * Access: Index
6677  */
6678 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
6679 
6680 /* reg_rrcr_size
6681  * The number of rules to copy/move.
6682  * Access: WO
6683  */
6684 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6685 
6686 /* reg_rrcr_table_id
6687  * Identifier of the table on which to perform the operation. Encoding is the
6688  * same as in RTAR.key_type
6689  * Access: Index
6690  */
6691 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6692 
6693 /* reg_rrcr_dest_offset
6694  * Offset within the region to which to copy/move
6695  * Access: Index
6696  */
6697 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6698 
6699 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6700 				       u16 offset, u16 size,
6701 				       enum mlxsw_reg_rtar_key_type table_id,
6702 				       u16 dest_offset)
6703 {
6704 	MLXSW_REG_ZERO(rrcr, payload);
6705 	mlxsw_reg_rrcr_op_set(payload, op);
6706 	mlxsw_reg_rrcr_offset_set(payload, offset);
6707 	mlxsw_reg_rrcr_size_set(payload, size);
6708 	mlxsw_reg_rrcr_table_id_set(payload, table_id);
6709 	mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6710 }
6711 
6712 /* RALTA - Router Algorithmic LPM Tree Allocation Register
6713  * -------------------------------------------------------
6714  * RALTA is used to allocate the LPM trees of the SHSPM method.
6715  */
6716 #define MLXSW_REG_RALTA_ID 0x8010
6717 #define MLXSW_REG_RALTA_LEN 0x04
6718 
6719 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6720 
6721 /* reg_ralta_op
6722  * opcode (valid for Write, must be 0 on Read)
6723  * 0 - allocate a tree
6724  * 1 - deallocate a tree
6725  * Access: OP
6726  */
6727 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6728 
6729 enum mlxsw_reg_ralxx_protocol {
6730 	MLXSW_REG_RALXX_PROTOCOL_IPV4,
6731 	MLXSW_REG_RALXX_PROTOCOL_IPV6,
6732 };
6733 
6734 /* reg_ralta_protocol
6735  * Protocol.
6736  * Deallocation opcode: Reserved.
6737  * Access: RW
6738  */
6739 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6740 
6741 /* reg_ralta_tree_id
6742  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
6743  * the tree identifier (managed by software).
6744  * Note that tree_id 0 is allocated for a default-route tree.
6745  * Access: Index
6746  */
6747 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6748 
6749 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6750 					enum mlxsw_reg_ralxx_protocol protocol,
6751 					u8 tree_id)
6752 {
6753 	MLXSW_REG_ZERO(ralta, payload);
6754 	mlxsw_reg_ralta_op_set(payload, !alloc);
6755 	mlxsw_reg_ralta_protocol_set(payload, protocol);
6756 	mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6757 }
6758 
6759 /* RALST - Router Algorithmic LPM Structure Tree Register
6760  * ------------------------------------------------------
6761  * RALST is used to set and query the structure of an LPM tree.
6762  * The structure of the tree must be sorted as a sorted binary tree, while
6763  * each node is a bin that is tagged as the length of the prefixes the lookup
6764  * will refer to. Therefore, bin X refers to a set of entries with prefixes
6765  * of X bits to match with the destination address. The bin 0 indicates
6766  * the default action, when there is no match of any prefix.
6767  */
6768 #define MLXSW_REG_RALST_ID 0x8011
6769 #define MLXSW_REG_RALST_LEN 0x104
6770 
6771 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6772 
6773 /* reg_ralst_root_bin
6774  * The bin number of the root bin.
6775  * 0<root_bin=<(length of IP address)
6776  * For a default-route tree configure 0xff
6777  * Access: RW
6778  */
6779 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6780 
6781 /* reg_ralst_tree_id
6782  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6783  * Access: Index
6784  */
6785 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6786 
6787 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6788 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6789 #define MLXSW_REG_RALST_BIN_COUNT 128
6790 
6791 /* reg_ralst_left_child_bin
6792  * Holding the children of the bin according to the stored tree's structure.
6793  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6794  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6795  * Access: RW
6796  */
6797 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6798 
6799 /* reg_ralst_right_child_bin
6800  * Holding the children of the bin according to the stored tree's structure.
6801  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6802  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6803  * Access: RW
6804  */
6805 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6806 		     false);
6807 
6808 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6809 {
6810 	MLXSW_REG_ZERO(ralst, payload);
6811 
6812 	/* Initialize all bins to have no left or right child */
6813 	memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6814 	       MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6815 
6816 	mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6817 	mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6818 }
6819 
6820 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6821 					    u8 left_child_bin,
6822 					    u8 right_child_bin)
6823 {
6824 	int bin_index = bin_number - 1;
6825 
6826 	mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6827 	mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6828 					    right_child_bin);
6829 }
6830 
6831 /* RALTB - Router Algorithmic LPM Tree Binding Register
6832  * ----------------------------------------------------
6833  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6834  */
6835 #define MLXSW_REG_RALTB_ID 0x8012
6836 #define MLXSW_REG_RALTB_LEN 0x04
6837 
6838 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6839 
6840 /* reg_raltb_virtual_router
6841  * Virtual Router ID
6842  * Range is 0..cap_max_virtual_routers-1
6843  * Access: Index
6844  */
6845 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6846 
6847 /* reg_raltb_protocol
6848  * Protocol.
6849  * Access: Index
6850  */
6851 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6852 
6853 /* reg_raltb_tree_id
6854  * Tree to be used for the {virtual_router, protocol}
6855  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6856  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6857  * Access: RW
6858  */
6859 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6860 
6861 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6862 					enum mlxsw_reg_ralxx_protocol protocol,
6863 					u8 tree_id)
6864 {
6865 	MLXSW_REG_ZERO(raltb, payload);
6866 	mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6867 	mlxsw_reg_raltb_protocol_set(payload, protocol);
6868 	mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6869 }
6870 
6871 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6872  * -----------------------------------------------------
6873  * RALUE is used to configure and query LPM entries that serve
6874  * the Unicast protocols.
6875  */
6876 #define MLXSW_REG_RALUE_ID 0x8013
6877 #define MLXSW_REG_RALUE_LEN 0x38
6878 
6879 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6880 
6881 /* reg_ralue_protocol
6882  * Protocol.
6883  * Access: Index
6884  */
6885 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6886 
6887 enum mlxsw_reg_ralue_op {
6888 	/* Read operation. If entry doesn't exist, the operation fails. */
6889 	MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6890 	/* Clear on read operation. Used to read entry and
6891 	 * clear Activity bit.
6892 	 */
6893 	MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6894 	/* Write operation. Used to write a new entry to the table. All RW
6895 	 * fields are written for new entry. Activity bit is set
6896 	 * for new entries.
6897 	 */
6898 	MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6899 	/* Update operation. Used to update an existing route entry and
6900 	 * only update the RW fields that are detailed in the field
6901 	 * op_u_mask. If entry doesn't exist, the operation fails.
6902 	 */
6903 	MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6904 	/* Clear activity. The Activity bit (the field a) is cleared
6905 	 * for the entry.
6906 	 */
6907 	MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6908 	/* Delete operation. Used to delete an existing entry. If entry
6909 	 * doesn't exist, the operation fails.
6910 	 */
6911 	MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6912 };
6913 
6914 /* reg_ralue_op
6915  * Operation.
6916  * Access: OP
6917  */
6918 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6919 
6920 /* reg_ralue_a
6921  * Activity. Set for new entries. Set if a packet lookup has hit on the
6922  * specific entry, only if the entry is a route. To clear the a bit, use
6923  * "clear activity" op.
6924  * Enabled by activity_dis in RGCR
6925  * Access: RO
6926  */
6927 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6928 
6929 /* reg_ralue_virtual_router
6930  * Virtual Router ID
6931  * Range is 0..cap_max_virtual_routers-1
6932  * Access: Index
6933  */
6934 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6935 
6936 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE	BIT(0)
6937 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN	BIT(1)
6938 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION	BIT(2)
6939 
6940 /* reg_ralue_op_u_mask
6941  * opcode update mask.
6942  * On read operation, this field is reserved.
6943  * This field is valid for update opcode, otherwise - reserved.
6944  * This field is a bitmask of the fields that should be updated.
6945  * Access: WO
6946  */
6947 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6948 
6949 /* reg_ralue_prefix_len
6950  * Number of bits in the prefix of the LPM route.
6951  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6952  * two entries in the physical HW table.
6953  * Access: Index
6954  */
6955 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6956 
6957 /* reg_ralue_dip*
6958  * The prefix of the route or of the marker that the object of the LPM
6959  * is compared with. The most significant bits of the dip are the prefix.
6960  * The least significant bits must be '0' if the prefix_len is smaller
6961  * than 128 for IPv6 or smaller than 32 for IPv4.
6962  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6963  * Access: Index
6964  */
6965 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6966 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6967 
6968 enum mlxsw_reg_ralue_entry_type {
6969 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6970 	MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6971 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6972 };
6973 
6974 /* reg_ralue_entry_type
6975  * Entry type.
6976  * Note - for Marker entries, the action_type and action fields are reserved.
6977  * Access: RW
6978  */
6979 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6980 
6981 /* reg_ralue_bmp_len
6982  * The best match prefix length in the case that there is no match for
6983  * longer prefixes.
6984  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6985  * Note for any update operation with entry_type modification this
6986  * field must be set.
6987  * Access: RW
6988  */
6989 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6990 
6991 enum mlxsw_reg_ralue_action_type {
6992 	MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6993 	MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6994 	MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6995 };
6996 
6997 /* reg_ralue_action_type
6998  * Action Type
6999  * Indicates how the IP address is connected.
7000  * It can be connected to a local subnet through local_erif or can be
7001  * on a remote subnet connected through a next-hop router,
7002  * or transmitted to the CPU.
7003  * Reserved when entry_type = MARKER_ENTRY
7004  * Access: RW
7005  */
7006 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
7007 
7008 enum mlxsw_reg_ralue_trap_action {
7009 	MLXSW_REG_RALUE_TRAP_ACTION_NOP,
7010 	MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
7011 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
7012 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
7013 	MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
7014 };
7015 
7016 /* reg_ralue_trap_action
7017  * Trap action.
7018  * For IP2ME action, only NOP and MIRROR are possible.
7019  * Access: RW
7020  */
7021 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
7022 
7023 /* reg_ralue_trap_id
7024  * Trap ID to be reported to CPU.
7025  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
7026  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
7027  * Access: RW
7028  */
7029 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
7030 
7031 /* reg_ralue_adjacency_index
7032  * Points to the first entry of the group-based ECMP.
7033  * Only relevant in case of REMOTE action.
7034  * Access: RW
7035  */
7036 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
7037 
7038 /* reg_ralue_ecmp_size
7039  * Amount of sequential entries starting
7040  * from the adjacency_index (the number of ECMPs).
7041  * The valid range is 1-64, 512, 1024, 2048 and 4096.
7042  * Reserved when trap_action is TRAP or DISCARD_ERROR.
7043  * Only relevant in case of REMOTE action.
7044  * Access: RW
7045  */
7046 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
7047 
7048 /* reg_ralue_local_erif
7049  * Egress Router Interface.
7050  * Only relevant in case of LOCAL action.
7051  * Access: RW
7052  */
7053 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
7054 
7055 /* reg_ralue_ip2me_v
7056  * Valid bit for the tunnel_ptr field.
7057  * If valid = 0 then trap to CPU as IP2ME trap ID.
7058  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
7059  * decapsulation then tunnel decapsulation is done.
7060  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
7061  * decapsulation then trap as IP2ME trap ID.
7062  * Only relevant in case of IP2ME action.
7063  * Access: RW
7064  */
7065 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
7066 
7067 /* reg_ralue_ip2me_tunnel_ptr
7068  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
7069  * For Spectrum, pointer to KVD Linear.
7070  * Only relevant in case of IP2ME action.
7071  * Access: RW
7072  */
7073 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
7074 
7075 static inline void mlxsw_reg_ralue_pack(char *payload,
7076 					enum mlxsw_reg_ralxx_protocol protocol,
7077 					enum mlxsw_reg_ralue_op op,
7078 					u16 virtual_router, u8 prefix_len)
7079 {
7080 	MLXSW_REG_ZERO(ralue, payload);
7081 	mlxsw_reg_ralue_protocol_set(payload, protocol);
7082 	mlxsw_reg_ralue_op_set(payload, op);
7083 	mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
7084 	mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
7085 	mlxsw_reg_ralue_entry_type_set(payload,
7086 				       MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
7087 	mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
7088 }
7089 
7090 static inline void mlxsw_reg_ralue_pack4(char *payload,
7091 					 enum mlxsw_reg_ralxx_protocol protocol,
7092 					 enum mlxsw_reg_ralue_op op,
7093 					 u16 virtual_router, u8 prefix_len,
7094 					 u32 dip)
7095 {
7096 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7097 	mlxsw_reg_ralue_dip4_set(payload, dip);
7098 }
7099 
7100 static inline void mlxsw_reg_ralue_pack6(char *payload,
7101 					 enum mlxsw_reg_ralxx_protocol protocol,
7102 					 enum mlxsw_reg_ralue_op op,
7103 					 u16 virtual_router, u8 prefix_len,
7104 					 const void *dip)
7105 {
7106 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7107 	mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
7108 }
7109 
7110 static inline void
7111 mlxsw_reg_ralue_act_remote_pack(char *payload,
7112 				enum mlxsw_reg_ralue_trap_action trap_action,
7113 				u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7114 {
7115 	mlxsw_reg_ralue_action_type_set(payload,
7116 					MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7117 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7118 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7119 	mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7120 	mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7121 }
7122 
7123 static inline void
7124 mlxsw_reg_ralue_act_local_pack(char *payload,
7125 			       enum mlxsw_reg_ralue_trap_action trap_action,
7126 			       u16 trap_id, u16 local_erif)
7127 {
7128 	mlxsw_reg_ralue_action_type_set(payload,
7129 					MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7130 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7131 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7132 	mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7133 }
7134 
7135 static inline void
7136 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7137 {
7138 	mlxsw_reg_ralue_action_type_set(payload,
7139 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7140 }
7141 
7142 static inline void
7143 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7144 {
7145 	mlxsw_reg_ralue_action_type_set(payload,
7146 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7147 	mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7148 	mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7149 }
7150 
7151 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
7152  * ----------------------------------------------------------
7153  * The RAUHT register is used to configure and query the Unicast Host table in
7154  * devices that implement the Algorithmic LPM.
7155  */
7156 #define MLXSW_REG_RAUHT_ID 0x8014
7157 #define MLXSW_REG_RAUHT_LEN 0x74
7158 
7159 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7160 
7161 enum mlxsw_reg_rauht_type {
7162 	MLXSW_REG_RAUHT_TYPE_IPV4,
7163 	MLXSW_REG_RAUHT_TYPE_IPV6,
7164 };
7165 
7166 /* reg_rauht_type
7167  * Access: Index
7168  */
7169 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7170 
7171 enum mlxsw_reg_rauht_op {
7172 	MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7173 	/* Read operation */
7174 	MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7175 	/* Clear on read operation. Used to read entry and clear
7176 	 * activity bit.
7177 	 */
7178 	MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7179 	/* Add. Used to write a new entry to the table. All R/W fields are
7180 	 * relevant for new entry. Activity bit is set for new entries.
7181 	 */
7182 	MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7183 	/* Update action. Used to update an existing route entry and
7184 	 * only update the following fields:
7185 	 * trap_action, trap_id, mac, counter_set_type, counter_index
7186 	 */
7187 	MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7188 	/* Clear activity. A bit is cleared for the entry. */
7189 	MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7190 	/* Delete entry */
7191 	MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7192 	/* Delete all host entries on a RIF. In this command, dip
7193 	 * field is reserved.
7194 	 */
7195 };
7196 
7197 /* reg_rauht_op
7198  * Access: OP
7199  */
7200 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7201 
7202 /* reg_rauht_a
7203  * Activity. Set for new entries. Set if a packet lookup has hit on
7204  * the specific entry.
7205  * To clear the a bit, use "clear activity" op.
7206  * Enabled by activity_dis in RGCR
7207  * Access: RO
7208  */
7209 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7210 
7211 /* reg_rauht_rif
7212  * Router Interface
7213  * Access: Index
7214  */
7215 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7216 
7217 /* reg_rauht_dip*
7218  * Destination address.
7219  * Access: Index
7220  */
7221 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7222 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7223 
7224 enum mlxsw_reg_rauht_trap_action {
7225 	MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7226 	MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7227 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7228 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7229 	MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7230 };
7231 
7232 /* reg_rauht_trap_action
7233  * Access: RW
7234  */
7235 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7236 
7237 enum mlxsw_reg_rauht_trap_id {
7238 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7239 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7240 };
7241 
7242 /* reg_rauht_trap_id
7243  * Trap ID to be reported to CPU.
7244  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7245  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
7246  * trap_id is reserved.
7247  * Access: RW
7248  */
7249 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7250 
7251 /* reg_rauht_counter_set_type
7252  * Counter set type for flow counters
7253  * Access: RW
7254  */
7255 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7256 
7257 /* reg_rauht_counter_index
7258  * Counter index for flow counters
7259  * Access: RW
7260  */
7261 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7262 
7263 /* reg_rauht_mac
7264  * MAC address.
7265  * Access: RW
7266  */
7267 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7268 
7269 static inline void mlxsw_reg_rauht_pack(char *payload,
7270 					enum mlxsw_reg_rauht_op op, u16 rif,
7271 					const char *mac)
7272 {
7273 	MLXSW_REG_ZERO(rauht, payload);
7274 	mlxsw_reg_rauht_op_set(payload, op);
7275 	mlxsw_reg_rauht_rif_set(payload, rif);
7276 	mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7277 }
7278 
7279 static inline void mlxsw_reg_rauht_pack4(char *payload,
7280 					 enum mlxsw_reg_rauht_op op, u16 rif,
7281 					 const char *mac, u32 dip)
7282 {
7283 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
7284 	mlxsw_reg_rauht_dip4_set(payload, dip);
7285 }
7286 
7287 static inline void mlxsw_reg_rauht_pack6(char *payload,
7288 					 enum mlxsw_reg_rauht_op op, u16 rif,
7289 					 const char *mac, const char *dip)
7290 {
7291 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
7292 	mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7293 	mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7294 }
7295 
7296 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7297 						u64 counter_index)
7298 {
7299 	mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7300 	mlxsw_reg_rauht_counter_set_type_set(payload,
7301 					     MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7302 }
7303 
7304 /* RALEU - Router Algorithmic LPM ECMP Update Register
7305  * ---------------------------------------------------
7306  * The register enables updating the ECMP section in the action for multiple
7307  * LPM Unicast entries in a single operation. The update is executed to
7308  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
7309  */
7310 #define MLXSW_REG_RALEU_ID 0x8015
7311 #define MLXSW_REG_RALEU_LEN 0x28
7312 
7313 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7314 
7315 /* reg_raleu_protocol
7316  * Protocol.
7317  * Access: Index
7318  */
7319 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7320 
7321 /* reg_raleu_virtual_router
7322  * Virtual Router ID
7323  * Range is 0..cap_max_virtual_routers-1
7324  * Access: Index
7325  */
7326 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7327 
7328 /* reg_raleu_adjacency_index
7329  * Adjacency Index used for matching on the existing entries.
7330  * Access: Index
7331  */
7332 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7333 
7334 /* reg_raleu_ecmp_size
7335  * ECMP Size used for matching on the existing entries.
7336  * Access: Index
7337  */
7338 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7339 
7340 /* reg_raleu_new_adjacency_index
7341  * New Adjacency Index.
7342  * Access: WO
7343  */
7344 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7345 
7346 /* reg_raleu_new_ecmp_size
7347  * New ECMP Size.
7348  * Access: WO
7349  */
7350 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7351 
7352 static inline void mlxsw_reg_raleu_pack(char *payload,
7353 					enum mlxsw_reg_ralxx_protocol protocol,
7354 					u16 virtual_router,
7355 					u32 adjacency_index, u16 ecmp_size,
7356 					u32 new_adjacency_index,
7357 					u16 new_ecmp_size)
7358 {
7359 	MLXSW_REG_ZERO(raleu, payload);
7360 	mlxsw_reg_raleu_protocol_set(payload, protocol);
7361 	mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7362 	mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7363 	mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7364 	mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7365 	mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7366 }
7367 
7368 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
7369  * ----------------------------------------------------------------
7370  * The RAUHTD register allows dumping entries from the Router Unicast Host
7371  * Table. For a given session an entry is dumped no more than one time. The
7372  * first RAUHTD access after reset is a new session. A session ends when the
7373  * num_rec response is smaller than num_rec request or for IPv4 when the
7374  * num_entries is smaller than 4. The clear activity affect the current session
7375  * or the last session if a new session has not started.
7376  */
7377 #define MLXSW_REG_RAUHTD_ID 0x8018
7378 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7379 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
7380 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7381 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7382 		MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7383 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7384 
7385 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7386 
7387 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7388 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7389 
7390 /* reg_rauhtd_filter_fields
7391  * if a bit is '0' then the relevant field is ignored and dump is done
7392  * regardless of the field value
7393  * Bit0 - filter by activity: entry_a
7394  * Bit3 - filter by entry rip: entry_rif
7395  * Access: Index
7396  */
7397 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7398 
7399 enum mlxsw_reg_rauhtd_op {
7400 	MLXSW_REG_RAUHTD_OP_DUMP,
7401 	MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7402 };
7403 
7404 /* reg_rauhtd_op
7405  * Access: OP
7406  */
7407 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7408 
7409 /* reg_rauhtd_num_rec
7410  * At request: number of records requested
7411  * At response: number of records dumped
7412  * For IPv4, each record has 4 entries at request and up to 4 entries
7413  * at response
7414  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
7415  * Access: Index
7416  */
7417 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7418 
7419 /* reg_rauhtd_entry_a
7420  * Dump only if activity has value of entry_a
7421  * Reserved if filter_fields bit0 is '0'
7422  * Access: Index
7423  */
7424 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7425 
7426 enum mlxsw_reg_rauhtd_type {
7427 	MLXSW_REG_RAUHTD_TYPE_IPV4,
7428 	MLXSW_REG_RAUHTD_TYPE_IPV6,
7429 };
7430 
7431 /* reg_rauhtd_type
7432  * Dump only if record type is:
7433  * 0 - IPv4
7434  * 1 - IPv6
7435  * Access: Index
7436  */
7437 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7438 
7439 /* reg_rauhtd_entry_rif
7440  * Dump only if RIF has value of entry_rif
7441  * Reserved if filter_fields bit3 is '0'
7442  * Access: Index
7443  */
7444 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7445 
7446 static inline void mlxsw_reg_rauhtd_pack(char *payload,
7447 					 enum mlxsw_reg_rauhtd_type type)
7448 {
7449 	MLXSW_REG_ZERO(rauhtd, payload);
7450 	mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7451 	mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7452 	mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7453 	mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7454 	mlxsw_reg_rauhtd_type_set(payload, type);
7455 }
7456 
7457 /* reg_rauhtd_ipv4_rec_num_entries
7458  * Number of valid entries in this record:
7459  * 0 - 1 valid entry
7460  * 1 - 2 valid entries
7461  * 2 - 3 valid entries
7462  * 3 - 4 valid entries
7463  * Access: RO
7464  */
7465 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7466 		     MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7467 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7468 
7469 /* reg_rauhtd_rec_type
7470  * Record type.
7471  * 0 - IPv4
7472  * 1 - IPv6
7473  * Access: RO
7474  */
7475 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7476 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7477 
7478 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7479 
7480 /* reg_rauhtd_ipv4_ent_a
7481  * Activity. Set for new entries. Set if a packet lookup has hit on the
7482  * specific entry.
7483  * Access: RO
7484  */
7485 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7486 		     MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7487 
7488 /* reg_rauhtd_ipv4_ent_rif
7489  * Router interface.
7490  * Access: RO
7491  */
7492 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7493 		     16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7494 
7495 /* reg_rauhtd_ipv4_ent_dip
7496  * Destination IPv4 address.
7497  * Access: RO
7498  */
7499 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7500 		     32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7501 
7502 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7503 
7504 /* reg_rauhtd_ipv6_ent_a
7505  * Activity. Set for new entries. Set if a packet lookup has hit on the
7506  * specific entry.
7507  * Access: RO
7508  */
7509 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7510 		     MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7511 
7512 /* reg_rauhtd_ipv6_ent_rif
7513  * Router interface.
7514  * Access: RO
7515  */
7516 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7517 		     16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7518 
7519 /* reg_rauhtd_ipv6_ent_dip
7520  * Destination IPv6 address.
7521  * Access: RO
7522  */
7523 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7524 		       16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7525 
7526 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7527 						    int ent_index, u16 *p_rif,
7528 						    u32 *p_dip)
7529 {
7530 	*p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7531 	*p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7532 }
7533 
7534 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7535 						    int rec_index, u16 *p_rif,
7536 						    char *p_dip)
7537 {
7538 	*p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7539 	mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7540 }
7541 
7542 /* RTDP - Routing Tunnel Decap Properties Register
7543  * -----------------------------------------------
7544  * The RTDP register is used for configuring the tunnel decap properties of NVE
7545  * and IPinIP.
7546  */
7547 #define MLXSW_REG_RTDP_ID 0x8020
7548 #define MLXSW_REG_RTDP_LEN 0x44
7549 
7550 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
7551 
7552 enum mlxsw_reg_rtdp_type {
7553 	MLXSW_REG_RTDP_TYPE_NVE,
7554 	MLXSW_REG_RTDP_TYPE_IPIP,
7555 };
7556 
7557 /* reg_rtdp_type
7558  * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
7559  * Access: RW
7560  */
7561 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
7562 
7563 /* reg_rtdp_tunnel_index
7564  * Index to the Decap entry.
7565  * For Spectrum, Index to KVD Linear.
7566  * Access: Index
7567  */
7568 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
7569 
7570 /* reg_rtdp_egress_router_interface
7571  * Underlay egress router interface.
7572  * Valid range is from 0 to cap_max_router_interfaces - 1
7573  * Access: RW
7574  */
7575 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
7576 
7577 /* IPinIP */
7578 
7579 /* reg_rtdp_ipip_irif
7580  * Ingress Router Interface for the overlay router
7581  * Access: RW
7582  */
7583 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
7584 
7585 enum mlxsw_reg_rtdp_ipip_sip_check {
7586 	/* No sip checks. */
7587 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
7588 	/* Filter packet if underlay is not IPv4 or if underlay SIP does not
7589 	 * equal ipv4_usip.
7590 	 */
7591 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
7592 	/* Filter packet if underlay is not IPv6 or if underlay SIP does not
7593 	 * equal ipv6_usip.
7594 	 */
7595 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
7596 };
7597 
7598 /* reg_rtdp_ipip_sip_check
7599  * SIP check to perform. If decapsulation failed due to these configurations
7600  * then trap_id is IPIP_DECAP_ERROR.
7601  * Access: RW
7602  */
7603 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
7604 
7605 /* If set, allow decapsulation of IPinIP (without GRE). */
7606 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP	BIT(0)
7607 /* If set, allow decapsulation of IPinGREinIP without a key. */
7608 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE	BIT(1)
7609 /* If set, allow decapsulation of IPinGREinIP with a key. */
7610 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY	BIT(2)
7611 
7612 /* reg_rtdp_ipip_type_check
7613  * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
7614  * these configurations then trap_id is IPIP_DECAP_ERROR.
7615  * Access: RW
7616  */
7617 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
7618 
7619 /* reg_rtdp_ipip_gre_key_check
7620  * Whether GRE key should be checked. When check is enabled:
7621  * - A packet received as IPinIP (without GRE) will always pass.
7622  * - A packet received as IPinGREinIP without a key will not pass the check.
7623  * - A packet received as IPinGREinIP with a key will pass the check only if the
7624  *   key in the packet is equal to expected_gre_key.
7625  * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
7626  * Access: RW
7627  */
7628 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
7629 
7630 /* reg_rtdp_ipip_ipv4_usip
7631  * Underlay IPv4 address for ipv4 source address check.
7632  * Reserved when sip_check is not '1'.
7633  * Access: RW
7634  */
7635 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
7636 
7637 /* reg_rtdp_ipip_ipv6_usip_ptr
7638  * This field is valid when sip_check is "sipv6 check explicitly". This is a
7639  * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
7640  * is to the KVD linear.
7641  * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
7642  * Access: RW
7643  */
7644 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
7645 
7646 /* reg_rtdp_ipip_expected_gre_key
7647  * GRE key for checking.
7648  * Reserved when gre_key_check is '0'.
7649  * Access: RW
7650  */
7651 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
7652 
7653 static inline void mlxsw_reg_rtdp_pack(char *payload,
7654 				       enum mlxsw_reg_rtdp_type type,
7655 				       u32 tunnel_index)
7656 {
7657 	MLXSW_REG_ZERO(rtdp, payload);
7658 	mlxsw_reg_rtdp_type_set(payload, type);
7659 	mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
7660 }
7661 
7662 static inline void
7663 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
7664 			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
7665 			  unsigned int type_check, bool gre_key_check,
7666 			  u32 ipv4_usip, u32 expected_gre_key)
7667 {
7668 	mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
7669 	mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
7670 	mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
7671 	mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
7672 	mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
7673 	mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
7674 }
7675 
7676 /* RIGR-V2 - Router Interface Group Register Version 2
7677  * ---------------------------------------------------
7678  * The RIGR_V2 register is used to add, remove and query egress interface list
7679  * of a multicast forwarding entry.
7680  */
7681 #define MLXSW_REG_RIGR2_ID 0x8023
7682 #define MLXSW_REG_RIGR2_LEN 0xB0
7683 
7684 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
7685 
7686 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
7687 
7688 /* reg_rigr2_rigr_index
7689  * KVD Linear index.
7690  * Access: Index
7691  */
7692 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7693 
7694 /* reg_rigr2_vnext
7695  * Next RIGR Index is valid.
7696  * Access: RW
7697  */
7698 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7699 
7700 /* reg_rigr2_next_rigr_index
7701  * Next RIGR Index. The index is to the KVD linear.
7702  * Reserved when vnxet = '0'.
7703  * Access: RW
7704  */
7705 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7706 
7707 /* reg_rigr2_vrmid
7708  * RMID Index is valid.
7709  * Access: RW
7710  */
7711 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7712 
7713 /* reg_rigr2_rmid_index
7714  * RMID Index.
7715  * Range 0 .. max_mid - 1
7716  * Reserved when vrmid = '0'.
7717  * The index is to the Port Group Table (PGT)
7718  * Access: RW
7719  */
7720 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7721 
7722 /* reg_rigr2_erif_entry_v
7723  * Egress Router Interface is valid.
7724  * Note that low-entries must be set if high-entries are set. For
7725  * example: if erif_entry[2].v is set then erif_entry[1].v and
7726  * erif_entry[0].v must be set.
7727  * Index can be from 0 to cap_mc_erif_list_entries-1
7728  * Access: RW
7729  */
7730 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7731 
7732 /* reg_rigr2_erif_entry_erif
7733  * Egress Router Interface.
7734  * Valid range is from 0 to cap_max_router_interfaces - 1
7735  * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
7736  * Access: RW
7737  */
7738 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7739 
7740 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7741 					bool vnext, u32 next_rigr_index)
7742 {
7743 	MLXSW_REG_ZERO(rigr2, payload);
7744 	mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7745 	mlxsw_reg_rigr2_vnext_set(payload, vnext);
7746 	mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7747 	mlxsw_reg_rigr2_vrmid_set(payload, 0);
7748 	mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7749 }
7750 
7751 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7752 						   bool v, u16 erif)
7753 {
7754 	mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7755 	mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7756 }
7757 
7758 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7759  * ------------------------------------------------------
7760  */
7761 #define MLXSW_REG_RECR2_ID 0x8025
7762 #define MLXSW_REG_RECR2_LEN 0x38
7763 
7764 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7765 
7766 /* reg_recr2_pp
7767  * Per-port configuration
7768  * Access: Index
7769  */
7770 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7771 
7772 /* reg_recr2_sh
7773  * Symmetric hash
7774  * Access: RW
7775  */
7776 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7777 
7778 /* reg_recr2_seed
7779  * Seed
7780  * Access: RW
7781  */
7782 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7783 
7784 enum {
7785 	/* Enable IPv4 fields if packet is not TCP and not UDP */
7786 	MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP	= 3,
7787 	/* Enable IPv4 fields if packet is TCP or UDP */
7788 	MLXSW_REG_RECR2_IPV4_EN_TCP_UDP		= 4,
7789 	/* Enable IPv6 fields if packet is not TCP and not UDP */
7790 	MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP	= 5,
7791 	/* Enable IPv6 fields if packet is TCP or UDP */
7792 	MLXSW_REG_RECR2_IPV6_EN_TCP_UDP		= 6,
7793 	/* Enable TCP/UDP header fields if packet is IPv4 */
7794 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV4		= 7,
7795 	/* Enable TCP/UDP header fields if packet is IPv6 */
7796 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV6		= 8,
7797 };
7798 
7799 /* reg_recr2_outer_header_enables
7800  * Bit mask where each bit enables a specific layer to be included in
7801  * the hash calculation.
7802  * Access: RW
7803  */
7804 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7805 
7806 enum {
7807 	/* IPv4 Source IP */
7808 	MLXSW_REG_RECR2_IPV4_SIP0			= 9,
7809 	MLXSW_REG_RECR2_IPV4_SIP3			= 12,
7810 	/* IPv4 Destination IP */
7811 	MLXSW_REG_RECR2_IPV4_DIP0			= 13,
7812 	MLXSW_REG_RECR2_IPV4_DIP3			= 16,
7813 	/* IP Protocol */
7814 	MLXSW_REG_RECR2_IPV4_PROTOCOL			= 17,
7815 	/* IPv6 Source IP */
7816 	MLXSW_REG_RECR2_IPV6_SIP0_7			= 21,
7817 	MLXSW_REG_RECR2_IPV6_SIP8			= 29,
7818 	MLXSW_REG_RECR2_IPV6_SIP15			= 36,
7819 	/* IPv6 Destination IP */
7820 	MLXSW_REG_RECR2_IPV6_DIP0_7			= 37,
7821 	MLXSW_REG_RECR2_IPV6_DIP8			= 45,
7822 	MLXSW_REG_RECR2_IPV6_DIP15			= 52,
7823 	/* IPv6 Next Header */
7824 	MLXSW_REG_RECR2_IPV6_NEXT_HEADER		= 53,
7825 	/* IPv6 Flow Label */
7826 	MLXSW_REG_RECR2_IPV6_FLOW_LABEL			= 57,
7827 	/* TCP/UDP Source Port */
7828 	MLXSW_REG_RECR2_TCP_UDP_SPORT			= 74,
7829 	/* TCP/UDP Destination Port */
7830 	MLXSW_REG_RECR2_TCP_UDP_DPORT			= 75,
7831 };
7832 
7833 /* reg_recr2_outer_header_fields_enable
7834  * Packet fields to enable for ECMP hash subject to outer_header_enable.
7835  * Access: RW
7836  */
7837 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7838 
7839 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7840 {
7841 	int i;
7842 
7843 	for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7844 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7845 							       true);
7846 }
7847 
7848 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7849 {
7850 	int i;
7851 
7852 	for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7853 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7854 							       true);
7855 }
7856 
7857 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7858 {
7859 	int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7860 
7861 	mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7862 
7863 	i = MLXSW_REG_RECR2_IPV6_SIP8;
7864 	for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7865 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7866 							       true);
7867 }
7868 
7869 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7870 {
7871 	int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7872 
7873 	mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7874 
7875 	i = MLXSW_REG_RECR2_IPV6_DIP8;
7876 	for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7877 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7878 							       true);
7879 }
7880 
7881 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7882 {
7883 	MLXSW_REG_ZERO(recr2, payload);
7884 	mlxsw_reg_recr2_pp_set(payload, false);
7885 	mlxsw_reg_recr2_sh_set(payload, true);
7886 	mlxsw_reg_recr2_seed_set(payload, seed);
7887 }
7888 
7889 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7890  * --------------------------------------------------------------
7891  * The RMFT_V2 register is used to configure and query the multicast table.
7892  */
7893 #define MLXSW_REG_RMFT2_ID 0x8027
7894 #define MLXSW_REG_RMFT2_LEN 0x174
7895 
7896 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7897 
7898 /* reg_rmft2_v
7899  * Valid
7900  * Access: RW
7901  */
7902 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7903 
7904 enum mlxsw_reg_rmft2_type {
7905 	MLXSW_REG_RMFT2_TYPE_IPV4,
7906 	MLXSW_REG_RMFT2_TYPE_IPV6
7907 };
7908 
7909 /* reg_rmft2_type
7910  * Access: Index
7911  */
7912 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7913 
7914 enum mlxsw_sp_reg_rmft2_op {
7915 	/* For Write:
7916 	 * Write operation. Used to write a new entry to the table. All RW
7917 	 * fields are relevant for new entry. Activity bit is set for new
7918 	 * entries - Note write with v (Valid) 0 will delete the entry.
7919 	 * For Query:
7920 	 * Read operation
7921 	 */
7922 	MLXSW_REG_RMFT2_OP_READ_WRITE,
7923 };
7924 
7925 /* reg_rmft2_op
7926  * Operation.
7927  * Access: OP
7928  */
7929 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7930 
7931 /* reg_rmft2_a
7932  * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7933  * entry.
7934  * Access: RO
7935  */
7936 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7937 
7938 /* reg_rmft2_offset
7939  * Offset within the multicast forwarding table to write to.
7940  * Access: Index
7941  */
7942 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7943 
7944 /* reg_rmft2_virtual_router
7945  * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7946  * Access: RW
7947  */
7948 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7949 
7950 enum mlxsw_reg_rmft2_irif_mask {
7951 	MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7952 	MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7953 };
7954 
7955 /* reg_rmft2_irif_mask
7956  * Ingress RIF mask.
7957  * Access: RW
7958  */
7959 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7960 
7961 /* reg_rmft2_irif
7962  * Ingress RIF index.
7963  * Access: RW
7964  */
7965 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7966 
7967 /* reg_rmft2_dip{4,6}
7968  * Destination IPv4/6 address
7969  * Access: RW
7970  */
7971 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7972 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7973 
7974 /* reg_rmft2_dip{4,6}_mask
7975  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7976  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7977  * Access: RW
7978  */
7979 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7980 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7981 
7982 /* reg_rmft2_sip{4,6}
7983  * Source IPv4/6 address
7984  * Access: RW
7985  */
7986 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7987 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7988 
7989 /* reg_rmft2_sip{4,6}_mask
7990  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7991  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7992  * Access: RW
7993  */
7994 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7995 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7996 
7997 /* reg_rmft2_flexible_action_set
7998  * ACL action set. The only supported action types in this field and in any
7999  * action-set pointed from here are as follows:
8000  * 00h: ACTION_NULL
8001  * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
8002  * 03h: ACTION_TRAP
8003  * 06h: ACTION_QOS
8004  * 08h: ACTION_POLICING_MONITORING
8005  * 10h: ACTION_ROUTER_MC
8006  * Access: RW
8007  */
8008 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
8009 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
8010 
8011 static inline void
8012 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
8013 			    u16 virtual_router,
8014 			    enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8015 			    const char *flex_action_set)
8016 {
8017 	MLXSW_REG_ZERO(rmft2, payload);
8018 	mlxsw_reg_rmft2_v_set(payload, v);
8019 	mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
8020 	mlxsw_reg_rmft2_offset_set(payload, offset);
8021 	mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
8022 	mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
8023 	mlxsw_reg_rmft2_irif_set(payload, irif);
8024 	if (flex_action_set)
8025 		mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
8026 							      flex_action_set);
8027 }
8028 
8029 static inline void
8030 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8031 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8032 			  u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
8033 			  const char *flexible_action_set)
8034 {
8035 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8036 				    irif_mask, irif, flexible_action_set);
8037 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
8038 	mlxsw_reg_rmft2_dip4_set(payload, dip4);
8039 	mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
8040 	mlxsw_reg_rmft2_sip4_set(payload, sip4);
8041 	mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
8042 }
8043 
8044 static inline void
8045 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8046 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8047 			  struct in6_addr dip6, struct in6_addr dip6_mask,
8048 			  struct in6_addr sip6, struct in6_addr sip6_mask,
8049 			  const char *flexible_action_set)
8050 {
8051 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8052 				    irif_mask, irif, flexible_action_set);
8053 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
8054 	mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
8055 	mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
8056 	mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
8057 	mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
8058 }
8059 
8060 /* MFCR - Management Fan Control Register
8061  * --------------------------------------
8062  * This register controls the settings of the Fan Speed PWM mechanism.
8063  */
8064 #define MLXSW_REG_MFCR_ID 0x9001
8065 #define MLXSW_REG_MFCR_LEN 0x08
8066 
8067 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
8068 
8069 enum mlxsw_reg_mfcr_pwm_frequency {
8070 	MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
8071 	MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
8072 	MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
8073 	MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
8074 	MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
8075 	MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
8076 	MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
8077 	MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
8078 };
8079 
8080 /* reg_mfcr_pwm_frequency
8081  * Controls the frequency of the PWM signal.
8082  * Access: RW
8083  */
8084 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
8085 
8086 #define MLXSW_MFCR_TACHOS_MAX 10
8087 
8088 /* reg_mfcr_tacho_active
8089  * Indicates which of the tachometer is active (bit per tachometer).
8090  * Access: RO
8091  */
8092 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
8093 
8094 #define MLXSW_MFCR_PWMS_MAX 5
8095 
8096 /* reg_mfcr_pwm_active
8097  * Indicates which of the PWM control is active (bit per PWM).
8098  * Access: RO
8099  */
8100 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
8101 
8102 static inline void
8103 mlxsw_reg_mfcr_pack(char *payload,
8104 		    enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
8105 {
8106 	MLXSW_REG_ZERO(mfcr, payload);
8107 	mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
8108 }
8109 
8110 static inline void
8111 mlxsw_reg_mfcr_unpack(char *payload,
8112 		      enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
8113 		      u16 *p_tacho_active, u8 *p_pwm_active)
8114 {
8115 	*p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
8116 	*p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
8117 	*p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
8118 }
8119 
8120 /* MFSC - Management Fan Speed Control Register
8121  * --------------------------------------------
8122  * This register controls the settings of the Fan Speed PWM mechanism.
8123  */
8124 #define MLXSW_REG_MFSC_ID 0x9002
8125 #define MLXSW_REG_MFSC_LEN 0x08
8126 
8127 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
8128 
8129 /* reg_mfsc_pwm
8130  * Fan pwm to control / monitor.
8131  * Access: Index
8132  */
8133 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
8134 
8135 /* reg_mfsc_pwm_duty_cycle
8136  * Controls the duty cycle of the PWM. Value range from 0..255 to
8137  * represent duty cycle of 0%...100%.
8138  * Access: RW
8139  */
8140 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
8141 
8142 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
8143 				       u8 pwm_duty_cycle)
8144 {
8145 	MLXSW_REG_ZERO(mfsc, payload);
8146 	mlxsw_reg_mfsc_pwm_set(payload, pwm);
8147 	mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
8148 }
8149 
8150 /* MFSM - Management Fan Speed Measurement
8151  * ---------------------------------------
8152  * This register controls the settings of the Tacho measurements and
8153  * enables reading the Tachometer measurements.
8154  */
8155 #define MLXSW_REG_MFSM_ID 0x9003
8156 #define MLXSW_REG_MFSM_LEN 0x08
8157 
8158 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
8159 
8160 /* reg_mfsm_tacho
8161  * Fan tachometer index.
8162  * Access: Index
8163  */
8164 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
8165 
8166 /* reg_mfsm_rpm
8167  * Fan speed (round per minute).
8168  * Access: RO
8169  */
8170 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
8171 
8172 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
8173 {
8174 	MLXSW_REG_ZERO(mfsm, payload);
8175 	mlxsw_reg_mfsm_tacho_set(payload, tacho);
8176 }
8177 
8178 /* MFSL - Management Fan Speed Limit Register
8179  * ------------------------------------------
8180  * The Fan Speed Limit register is used to configure the fan speed
8181  * event / interrupt notification mechanism. Fan speed threshold are
8182  * defined for both under-speed and over-speed.
8183  */
8184 #define MLXSW_REG_MFSL_ID 0x9004
8185 #define MLXSW_REG_MFSL_LEN 0x0C
8186 
8187 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
8188 
8189 /* reg_mfsl_tacho
8190  * Fan tachometer index.
8191  * Access: Index
8192  */
8193 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
8194 
8195 /* reg_mfsl_tach_min
8196  * Tachometer minimum value (minimum RPM).
8197  * Access: RW
8198  */
8199 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
8200 
8201 /* reg_mfsl_tach_max
8202  * Tachometer maximum value (maximum RPM).
8203  * Access: RW
8204  */
8205 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
8206 
8207 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
8208 				       u16 tach_min, u16 tach_max)
8209 {
8210 	MLXSW_REG_ZERO(mfsl, payload);
8211 	mlxsw_reg_mfsl_tacho_set(payload, tacho);
8212 	mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
8213 	mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
8214 }
8215 
8216 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
8217 					 u16 *p_tach_min, u16 *p_tach_max)
8218 {
8219 	if (p_tach_min)
8220 		*p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
8221 
8222 	if (p_tach_max)
8223 		*p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
8224 }
8225 
8226 /* FORE - Fan Out of Range Event Register
8227  * --------------------------------------
8228  * This register reports the status of the controlled fans compared to the
8229  * range defined by the MFSL register.
8230  */
8231 #define MLXSW_REG_FORE_ID 0x9007
8232 #define MLXSW_REG_FORE_LEN 0x0C
8233 
8234 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
8235 
8236 /* fan_under_limit
8237  * Fan speed is below the low limit defined in MFSL register. Each bit relates
8238  * to a single tachometer and indicates the specific tachometer reading is
8239  * below the threshold.
8240  * Access: RO
8241  */
8242 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
8243 
8244 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
8245 					 bool *fault)
8246 {
8247 	u16 limit;
8248 
8249 	if (fault) {
8250 		limit = mlxsw_reg_fore_fan_under_limit_get(payload);
8251 		*fault = limit & BIT(tacho);
8252 	}
8253 }
8254 
8255 /* MTCAP - Management Temperature Capabilities
8256  * -------------------------------------------
8257  * This register exposes the capabilities of the device and
8258  * system temperature sensing.
8259  */
8260 #define MLXSW_REG_MTCAP_ID 0x9009
8261 #define MLXSW_REG_MTCAP_LEN 0x08
8262 
8263 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
8264 
8265 /* reg_mtcap_sensor_count
8266  * Number of sensors supported by the device.
8267  * This includes the QSFP module sensors (if exists in the QSFP module).
8268  * Access: RO
8269  */
8270 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
8271 
8272 /* MTMP - Management Temperature
8273  * -----------------------------
8274  * This register controls the settings of the temperature measurements
8275  * and enables reading the temperature measurements. Note that temperature
8276  * is in 0.125 degrees Celsius.
8277  */
8278 #define MLXSW_REG_MTMP_ID 0x900A
8279 #define MLXSW_REG_MTMP_LEN 0x20
8280 
8281 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
8282 
8283 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
8284 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
8285 /* reg_mtmp_sensor_index
8286  * Sensors index to access.
8287  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
8288  * (module 0 is mapped to sensor_index 64).
8289  * Access: Index
8290  */
8291 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
8292 
8293 /* Convert to milli degrees Celsius */
8294 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
8295 					  ((v_) >= 0) ? ((v_) * 125) : \
8296 					  ((s16)((GENMASK(15, 0) + (v_) + 1) \
8297 					   * 125)); })
8298 
8299 /* reg_mtmp_temperature
8300  * Temperature reading from the sensor. Reading is in 0.125 Celsius
8301  * degrees units.
8302  * Access: RO
8303  */
8304 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
8305 
8306 /* reg_mtmp_mte
8307  * Max Temperature Enable - enables measuring the max temperature on a sensor.
8308  * Access: RW
8309  */
8310 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
8311 
8312 /* reg_mtmp_mtr
8313  * Max Temperature Reset - clears the value of the max temperature register.
8314  * Access: WO
8315  */
8316 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
8317 
8318 /* reg_mtmp_max_temperature
8319  * The highest measured temperature from the sensor.
8320  * When the bit mte is cleared, the field max_temperature is reserved.
8321  * Access: RO
8322  */
8323 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
8324 
8325 /* reg_mtmp_tee
8326  * Temperature Event Enable.
8327  * 0 - Do not generate event
8328  * 1 - Generate event
8329  * 2 - Generate single event
8330  * Access: RW
8331  */
8332 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
8333 
8334 #define MLXSW_REG_MTMP_THRESH_HI 0x348	/* 105 Celsius */
8335 
8336 /* reg_mtmp_temperature_threshold_hi
8337  * High threshold for Temperature Warning Event. In 0.125 Celsius.
8338  * Access: RW
8339  */
8340 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
8341 
8342 /* reg_mtmp_temperature_threshold_lo
8343  * Low threshold for Temperature Warning Event. In 0.125 Celsius.
8344  * Access: RW
8345  */
8346 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
8347 
8348 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
8349 
8350 /* reg_mtmp_sensor_name
8351  * Sensor Name
8352  * Access: RO
8353  */
8354 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
8355 
8356 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
8357 				       bool max_temp_enable,
8358 				       bool max_temp_reset)
8359 {
8360 	MLXSW_REG_ZERO(mtmp, payload);
8361 	mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
8362 	mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
8363 	mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
8364 	mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
8365 						    MLXSW_REG_MTMP_THRESH_HI);
8366 }
8367 
8368 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
8369 					 int *p_max_temp, char *sensor_name)
8370 {
8371 	s16 temp;
8372 
8373 	if (p_temp) {
8374 		temp = mlxsw_reg_mtmp_temperature_get(payload);
8375 		*p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8376 	}
8377 	if (p_max_temp) {
8378 		temp = mlxsw_reg_mtmp_max_temperature_get(payload);
8379 		*p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8380 	}
8381 	if (sensor_name)
8382 		mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
8383 }
8384 
8385 /* MTBR - Management Temperature Bulk Register
8386  * -------------------------------------------
8387  * This register is used for bulk temperature reading.
8388  */
8389 #define MLXSW_REG_MTBR_ID 0x900F
8390 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
8391 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
8392 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
8393 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +	\
8394 			    MLXSW_REG_MTBR_REC_LEN *	\
8395 			    MLXSW_REG_MTBR_REC_MAX_COUNT)
8396 
8397 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
8398 
8399 /* reg_mtbr_base_sensor_index
8400  * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
8401  * 64-127 are mapped to the SFP+/QSFP modules sequentially).
8402  * Access: Index
8403  */
8404 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
8405 
8406 /* reg_mtbr_num_rec
8407  * Request: Number of records to read
8408  * Response: Number of records read
8409  * See above description for more details.
8410  * Range 1..255
8411  * Access: RW
8412  */
8413 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
8414 
8415 /* reg_mtbr_rec_max_temp
8416  * The highest measured temperature from the sensor.
8417  * When the bit mte is cleared, the field max_temperature is reserved.
8418  * Access: RO
8419  */
8420 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
8421 		     16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8422 
8423 /* reg_mtbr_rec_temp
8424  * Temperature reading from the sensor. Reading is in 0..125 Celsius
8425  * degrees units.
8426  * Access: RO
8427  */
8428 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
8429 		     MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8430 
8431 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
8432 				       u8 num_rec)
8433 {
8434 	MLXSW_REG_ZERO(mtbr, payload);
8435 	mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
8436 	mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
8437 }
8438 
8439 /* Error codes from temperatute reading */
8440 enum mlxsw_reg_mtbr_temp_status {
8441 	MLXSW_REG_MTBR_NO_CONN		= 0x8000,
8442 	MLXSW_REG_MTBR_NO_TEMP_SENS	= 0x8001,
8443 	MLXSW_REG_MTBR_INDEX_NA		= 0x8002,
8444 	MLXSW_REG_MTBR_BAD_SENS_INFO	= 0x8003,
8445 };
8446 
8447 /* Base index for reading modules temperature */
8448 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
8449 
8450 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
8451 					      u16 *p_temp, u16 *p_max_temp)
8452 {
8453 	if (p_temp)
8454 		*p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
8455 	if (p_max_temp)
8456 		*p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
8457 }
8458 
8459 /* MCIA - Management Cable Info Access
8460  * -----------------------------------
8461  * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
8462  */
8463 
8464 #define MLXSW_REG_MCIA_ID 0x9014
8465 #define MLXSW_REG_MCIA_LEN 0x40
8466 
8467 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
8468 
8469 /* reg_mcia_l
8470  * Lock bit. Setting this bit will lock the access to the specific
8471  * cable. Used for updating a full page in a cable EPROM. Any access
8472  * other then subsequence writes will fail while the port is locked.
8473  * Access: RW
8474  */
8475 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
8476 
8477 /* reg_mcia_module
8478  * Module number.
8479  * Access: Index
8480  */
8481 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
8482 
8483 /* reg_mcia_status
8484  * Module status.
8485  * Access: RO
8486  */
8487 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
8488 
8489 /* reg_mcia_i2c_device_address
8490  * I2C device address.
8491  * Access: RW
8492  */
8493 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
8494 
8495 /* reg_mcia_page_number
8496  * Page number.
8497  * Access: RW
8498  */
8499 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
8500 
8501 /* reg_mcia_device_address
8502  * Device address.
8503  * Access: RW
8504  */
8505 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
8506 
8507 /* reg_mcia_size
8508  * Number of bytes to read/write (up to 48 bytes).
8509  * Access: RW
8510  */
8511 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
8512 
8513 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH	256
8514 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH	128
8515 #define MLXSW_REG_MCIA_EEPROM_SIZE		48
8516 #define MLXSW_REG_MCIA_I2C_ADDR_LOW		0x50
8517 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH		0x51
8518 #define MLXSW_REG_MCIA_PAGE0_LO_OFF		0xa0
8519 #define MLXSW_REG_MCIA_TH_ITEM_SIZE		2
8520 #define MLXSW_REG_MCIA_TH_PAGE_NUM		3
8521 #define MLXSW_REG_MCIA_PAGE0_LO			0
8522 #define MLXSW_REG_MCIA_TH_PAGE_OFF		0x80
8523 
8524 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
8525 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC	= 0x00,
8526 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436	= 0x01,
8527 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636	= 0x03,
8528 };
8529 
8530 enum mlxsw_reg_mcia_eeprom_module_info_id {
8531 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP	= 0x03,
8532 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP	= 0x0C,
8533 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS	= 0x0D,
8534 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28	= 0x11,
8535 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD	= 0x18,
8536 };
8537 
8538 enum mlxsw_reg_mcia_eeprom_module_info {
8539 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
8540 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
8541 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
8542 };
8543 
8544 /* reg_mcia_eeprom
8545  * Bytes to read/write.
8546  * Access: RW
8547  */
8548 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
8549 
8550 /* This is used to access the optional upper pages (1-3) in the QSFP+
8551  * memory map. Page 1 is available on offset 256 through 383, page 2 -
8552  * on offset 384 through 511, page 3 - on offset 512 through 639.
8553  */
8554 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
8555 				MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
8556 				MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
8557 
8558 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
8559 				       u8 page_number, u16 device_addr,
8560 				       u8 size, u8 i2c_device_addr)
8561 {
8562 	MLXSW_REG_ZERO(mcia, payload);
8563 	mlxsw_reg_mcia_module_set(payload, module);
8564 	mlxsw_reg_mcia_l_set(payload, lock);
8565 	mlxsw_reg_mcia_page_number_set(payload, page_number);
8566 	mlxsw_reg_mcia_device_address_set(payload, device_addr);
8567 	mlxsw_reg_mcia_size_set(payload, size);
8568 	mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
8569 }
8570 
8571 /* MPAT - Monitoring Port Analyzer Table
8572  * -------------------------------------
8573  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
8574  * For an enabled analyzer, all fields except e (enable) cannot be modified.
8575  */
8576 #define MLXSW_REG_MPAT_ID 0x901A
8577 #define MLXSW_REG_MPAT_LEN 0x78
8578 
8579 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
8580 
8581 /* reg_mpat_pa_id
8582  * Port Analyzer ID.
8583  * Access: Index
8584  */
8585 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
8586 
8587 /* reg_mpat_system_port
8588  * A unique port identifier for the final destination of the packet.
8589  * Access: RW
8590  */
8591 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
8592 
8593 /* reg_mpat_e
8594  * Enable. Indicating the Port Analyzer is enabled.
8595  * Access: RW
8596  */
8597 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
8598 
8599 /* reg_mpat_qos
8600  * Quality Of Service Mode.
8601  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
8602  * PCP, DEI, DSCP or VL) are configured.
8603  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
8604  * same as in the original packet that has triggered the mirroring. For
8605  * SPAN also the pcp,dei are maintained.
8606  * Access: RW
8607  */
8608 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
8609 
8610 /* reg_mpat_be
8611  * Best effort mode. Indicates mirroring traffic should not cause packet
8612  * drop or back pressure, but will discard the mirrored packets. Mirrored
8613  * packets will be forwarded on a best effort manner.
8614  * 0: Do not discard mirrored packets
8615  * 1: Discard mirrored packets if causing congestion
8616  * Access: RW
8617  */
8618 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
8619 
8620 enum mlxsw_reg_mpat_span_type {
8621 	/* Local SPAN Ethernet.
8622 	 * The original packet is not encapsulated.
8623 	 */
8624 	MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
8625 
8626 	/* Remote SPAN Ethernet VLAN.
8627 	 * The packet is forwarded to the monitoring port on the monitoring
8628 	 * VLAN.
8629 	 */
8630 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
8631 
8632 	/* Encapsulated Remote SPAN Ethernet L3 GRE.
8633 	 * The packet is encapsulated with GRE header.
8634 	 */
8635 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
8636 };
8637 
8638 /* reg_mpat_span_type
8639  * SPAN type.
8640  * Access: RW
8641  */
8642 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
8643 
8644 /* Remote SPAN - Ethernet VLAN
8645  * - - - - - - - - - - - - - -
8646  */
8647 
8648 /* reg_mpat_eth_rspan_vid
8649  * Encapsulation header VLAN ID.
8650  * Access: RW
8651  */
8652 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
8653 
8654 /* Encapsulated Remote SPAN - Ethernet L2
8655  * - - - - - - - - - - - - - - - - - - -
8656  */
8657 
8658 enum mlxsw_reg_mpat_eth_rspan_version {
8659 	MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
8660 };
8661 
8662 /* reg_mpat_eth_rspan_version
8663  * RSPAN mirror header version.
8664  * Access: RW
8665  */
8666 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
8667 
8668 /* reg_mpat_eth_rspan_mac
8669  * Destination MAC address.
8670  * Access: RW
8671  */
8672 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
8673 
8674 /* reg_mpat_eth_rspan_tp
8675  * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
8676  * Access: RW
8677  */
8678 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
8679 
8680 /* Encapsulated Remote SPAN - Ethernet L3
8681  * - - - - - - - - - - - - - - - - - - -
8682  */
8683 
8684 enum mlxsw_reg_mpat_eth_rspan_protocol {
8685 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
8686 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
8687 };
8688 
8689 /* reg_mpat_eth_rspan_protocol
8690  * SPAN encapsulation protocol.
8691  * Access: RW
8692  */
8693 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
8694 
8695 /* reg_mpat_eth_rspan_ttl
8696  * Encapsulation header Time-to-Live/HopLimit.
8697  * Access: RW
8698  */
8699 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
8700 
8701 /* reg_mpat_eth_rspan_smac
8702  * Source MAC address
8703  * Access: RW
8704  */
8705 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
8706 
8707 /* reg_mpat_eth_rspan_dip*
8708  * Destination IP address. The IP version is configured by protocol.
8709  * Access: RW
8710  */
8711 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
8712 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
8713 
8714 /* reg_mpat_eth_rspan_sip*
8715  * Source IP address. The IP version is configured by protocol.
8716  * Access: RW
8717  */
8718 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
8719 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
8720 
8721 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
8722 				       u16 system_port, bool e,
8723 				       enum mlxsw_reg_mpat_span_type span_type)
8724 {
8725 	MLXSW_REG_ZERO(mpat, payload);
8726 	mlxsw_reg_mpat_pa_id_set(payload, pa_id);
8727 	mlxsw_reg_mpat_system_port_set(payload, system_port);
8728 	mlxsw_reg_mpat_e_set(payload, e);
8729 	mlxsw_reg_mpat_qos_set(payload, 1);
8730 	mlxsw_reg_mpat_be_set(payload, 1);
8731 	mlxsw_reg_mpat_span_type_set(payload, span_type);
8732 }
8733 
8734 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
8735 {
8736 	mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
8737 }
8738 
8739 static inline void
8740 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
8741 				 enum mlxsw_reg_mpat_eth_rspan_version version,
8742 				 const char *mac,
8743 				 bool tp)
8744 {
8745 	mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
8746 	mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
8747 	mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
8748 }
8749 
8750 static inline void
8751 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
8752 				      const char *smac,
8753 				      u32 sip, u32 dip)
8754 {
8755 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8756 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8757 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8758 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
8759 	mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
8760 	mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
8761 }
8762 
8763 static inline void
8764 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
8765 				      const char *smac,
8766 				      struct in6_addr sip, struct in6_addr dip)
8767 {
8768 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8769 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8770 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8771 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
8772 	mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
8773 	mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
8774 }
8775 
8776 /* MPAR - Monitoring Port Analyzer Register
8777  * ----------------------------------------
8778  * MPAR register is used to query and configure the port analyzer port mirroring
8779  * properties.
8780  */
8781 #define MLXSW_REG_MPAR_ID 0x901B
8782 #define MLXSW_REG_MPAR_LEN 0x0C
8783 
8784 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
8785 
8786 /* reg_mpar_local_port
8787  * The local port to mirror the packets from.
8788  * Access: Index
8789  */
8790 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
8791 
8792 enum mlxsw_reg_mpar_i_e {
8793 	MLXSW_REG_MPAR_TYPE_EGRESS,
8794 	MLXSW_REG_MPAR_TYPE_INGRESS,
8795 };
8796 
8797 /* reg_mpar_i_e
8798  * Ingress/Egress
8799  * Access: Index
8800  */
8801 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
8802 
8803 /* reg_mpar_enable
8804  * Enable mirroring
8805  * By default, port mirroring is disabled for all ports.
8806  * Access: RW
8807  */
8808 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
8809 
8810 /* reg_mpar_pa_id
8811  * Port Analyzer ID.
8812  * Access: RW
8813  */
8814 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
8815 
8816 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
8817 				       enum mlxsw_reg_mpar_i_e i_e,
8818 				       bool enable, u8 pa_id)
8819 {
8820 	MLXSW_REG_ZERO(mpar, payload);
8821 	mlxsw_reg_mpar_local_port_set(payload, local_port);
8822 	mlxsw_reg_mpar_enable_set(payload, enable);
8823 	mlxsw_reg_mpar_i_e_set(payload, i_e);
8824 	mlxsw_reg_mpar_pa_id_set(payload, pa_id);
8825 }
8826 
8827 /* MGIR - Management General Information Register
8828  * ----------------------------------------------
8829  * MGIR register allows software to query the hardware and firmware general
8830  * information.
8831  */
8832 #define MLXSW_REG_MGIR_ID 0x9020
8833 #define MLXSW_REG_MGIR_LEN 0x9C
8834 
8835 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
8836 
8837 /* reg_mgir_hw_info_device_hw_revision
8838  * Access: RO
8839  */
8840 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
8841 
8842 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
8843 
8844 /* reg_mgir_fw_info_psid
8845  * PSID (ASCII string).
8846  * Access: RO
8847  */
8848 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
8849 
8850 /* reg_mgir_fw_info_extended_major
8851  * Access: RO
8852  */
8853 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
8854 
8855 /* reg_mgir_fw_info_extended_minor
8856  * Access: RO
8857  */
8858 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
8859 
8860 /* reg_mgir_fw_info_extended_sub_minor
8861  * Access: RO
8862  */
8863 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
8864 
8865 static inline void mlxsw_reg_mgir_pack(char *payload)
8866 {
8867 	MLXSW_REG_ZERO(mgir, payload);
8868 }
8869 
8870 static inline void
8871 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
8872 		      u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
8873 {
8874 	*hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
8875 	mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
8876 	*fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
8877 	*fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
8878 	*fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
8879 }
8880 
8881 /* MRSR - Management Reset and Shutdown Register
8882  * ---------------------------------------------
8883  * MRSR register is used to reset or shutdown the switch or
8884  * the entire system (when applicable).
8885  */
8886 #define MLXSW_REG_MRSR_ID 0x9023
8887 #define MLXSW_REG_MRSR_LEN 0x08
8888 
8889 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8890 
8891 /* reg_mrsr_command
8892  * Reset/shutdown command
8893  * 0 - do nothing
8894  * 1 - software reset
8895  * Access: WO
8896  */
8897 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8898 
8899 static inline void mlxsw_reg_mrsr_pack(char *payload)
8900 {
8901 	MLXSW_REG_ZERO(mrsr, payload);
8902 	mlxsw_reg_mrsr_command_set(payload, 1);
8903 }
8904 
8905 /* MLCR - Management LED Control Register
8906  * --------------------------------------
8907  * Controls the system LEDs.
8908  */
8909 #define MLXSW_REG_MLCR_ID 0x902B
8910 #define MLXSW_REG_MLCR_LEN 0x0C
8911 
8912 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8913 
8914 /* reg_mlcr_local_port
8915  * Local port number.
8916  * Access: RW
8917  */
8918 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8919 
8920 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8921 
8922 /* reg_mlcr_beacon_duration
8923  * Duration of the beacon to be active, in seconds.
8924  * 0x0 - Will turn off the beacon.
8925  * 0xFFFF - Will turn on the beacon until explicitly turned off.
8926  * Access: RW
8927  */
8928 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8929 
8930 /* reg_mlcr_beacon_remain
8931  * Remaining duration of the beacon, in seconds.
8932  * 0xFFFF indicates an infinite amount of time.
8933  * Access: RO
8934  */
8935 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8936 
8937 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8938 				       bool active)
8939 {
8940 	MLXSW_REG_ZERO(mlcr, payload);
8941 	mlxsw_reg_mlcr_local_port_set(payload, local_port);
8942 	mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8943 					   MLXSW_REG_MLCR_DURATION_MAX : 0);
8944 }
8945 
8946 /* MTPPS - Management Pulse Per Second Register
8947  * --------------------------------------------
8948  * This register provides the device PPS capabilities, configure the PPS in and
8949  * out modules and holds the PPS in time stamp.
8950  */
8951 #define MLXSW_REG_MTPPS_ID 0x9053
8952 #define MLXSW_REG_MTPPS_LEN 0x3C
8953 
8954 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
8955 
8956 /* reg_mtpps_enable
8957  * Enables the PPS functionality the specific pin.
8958  * A boolean variable.
8959  * Access: RW
8960  */
8961 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
8962 
8963 enum mlxsw_reg_mtpps_pin_mode {
8964 	MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
8965 };
8966 
8967 /* reg_mtpps_pin_mode
8968  * Pin mode to be used. The mode must comply with the supported modes of the
8969  * requested pin.
8970  * Access: RW
8971  */
8972 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
8973 
8974 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN	7
8975 
8976 /* reg_mtpps_pin
8977  * Pin to be configured or queried out of the supported pins.
8978  * Access: Index
8979  */
8980 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
8981 
8982 /* reg_mtpps_time_stamp
8983  * When pin_mode = pps_in, the latched device time when it was triggered from
8984  * the external GPIO pin.
8985  * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
8986  * time to generate next output signal.
8987  * Time is in units of device clock.
8988  * Access: RW
8989  */
8990 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
8991 
8992 static inline void
8993 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
8994 {
8995 	MLXSW_REG_ZERO(mtpps, payload);
8996 	mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
8997 	mlxsw_reg_mtpps_pin_mode_set(payload,
8998 				     MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
8999 	mlxsw_reg_mtpps_enable_set(payload, true);
9000 	mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
9001 }
9002 
9003 /* MTUTC - Management UTC Register
9004  * -------------------------------
9005  * Configures the HW UTC counter.
9006  */
9007 #define MLXSW_REG_MTUTC_ID 0x9055
9008 #define MLXSW_REG_MTUTC_LEN 0x1C
9009 
9010 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
9011 
9012 enum mlxsw_reg_mtutc_operation {
9013 	MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
9014 	MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
9015 };
9016 
9017 /* reg_mtutc_operation
9018  * Operation.
9019  * Access: OP
9020  */
9021 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
9022 
9023 /* reg_mtutc_freq_adjustment
9024  * Frequency adjustment: Every PPS the HW frequency will be
9025  * adjusted by this value. Units of HW clock, where HW counts
9026  * 10^9 HW clocks for 1 HW second.
9027  * Access: RW
9028  */
9029 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
9030 
9031 /* reg_mtutc_utc_sec
9032  * UTC seconds.
9033  * Access: WO
9034  */
9035 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
9036 
9037 static inline void
9038 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
9039 		     u32 freq_adj, u32 utc_sec)
9040 {
9041 	MLXSW_REG_ZERO(mtutc, payload);
9042 	mlxsw_reg_mtutc_operation_set(payload, oper);
9043 	mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
9044 	mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
9045 }
9046 
9047 /* MCQI - Management Component Query Information
9048  * ---------------------------------------------
9049  * This register allows querying information about firmware components.
9050  */
9051 #define MLXSW_REG_MCQI_ID 0x9061
9052 #define MLXSW_REG_MCQI_BASE_LEN 0x18
9053 #define MLXSW_REG_MCQI_CAP_LEN 0x14
9054 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
9055 
9056 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
9057 
9058 /* reg_mcqi_component_index
9059  * Index of the accessed component.
9060  * Access: Index
9061  */
9062 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
9063 
9064 enum mlxfw_reg_mcqi_info_type {
9065 	MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
9066 };
9067 
9068 /* reg_mcqi_info_type
9069  * Component properties set.
9070  * Access: RW
9071  */
9072 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
9073 
9074 /* reg_mcqi_offset
9075  * The requested/returned data offset from the section start, given in bytes.
9076  * Must be DWORD aligned.
9077  * Access: RW
9078  */
9079 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
9080 
9081 /* reg_mcqi_data_size
9082  * The requested/returned data size, given in bytes. If data_size is not DWORD
9083  * aligned, the last bytes are zero padded.
9084  * Access: RW
9085  */
9086 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
9087 
9088 /* reg_mcqi_cap_max_component_size
9089  * Maximum size for this component, given in bytes.
9090  * Access: RO
9091  */
9092 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
9093 
9094 /* reg_mcqi_cap_log_mcda_word_size
9095  * Log 2 of the access word size in bytes. Read and write access must be aligned
9096  * to the word size. Write access must be done for an integer number of words.
9097  * Access: RO
9098  */
9099 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
9100 
9101 /* reg_mcqi_cap_mcda_max_write_size
9102  * Maximal write size for MCDA register
9103  * Access: RO
9104  */
9105 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
9106 
9107 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
9108 {
9109 	MLXSW_REG_ZERO(mcqi, payload);
9110 	mlxsw_reg_mcqi_component_index_set(payload, component_index);
9111 	mlxsw_reg_mcqi_info_type_set(payload,
9112 				     MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
9113 	mlxsw_reg_mcqi_offset_set(payload, 0);
9114 	mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
9115 }
9116 
9117 static inline void mlxsw_reg_mcqi_unpack(char *payload,
9118 					 u32 *p_cap_max_component_size,
9119 					 u8 *p_cap_log_mcda_word_size,
9120 					 u16 *p_cap_mcda_max_write_size)
9121 {
9122 	*p_cap_max_component_size =
9123 		mlxsw_reg_mcqi_cap_max_component_size_get(payload);
9124 	*p_cap_log_mcda_word_size =
9125 		mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
9126 	*p_cap_mcda_max_write_size =
9127 		mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
9128 }
9129 
9130 /* MCC - Management Component Control
9131  * ----------------------------------
9132  * Controls the firmware component and updates the FSM.
9133  */
9134 #define MLXSW_REG_MCC_ID 0x9062
9135 #define MLXSW_REG_MCC_LEN 0x1C
9136 
9137 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
9138 
9139 enum mlxsw_reg_mcc_instruction {
9140 	MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
9141 	MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
9142 	MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
9143 	MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
9144 	MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
9145 	MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
9146 };
9147 
9148 /* reg_mcc_instruction
9149  * Command to be executed by the FSM.
9150  * Applicable for write operation only.
9151  * Access: RW
9152  */
9153 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
9154 
9155 /* reg_mcc_component_index
9156  * Index of the accessed component. Applicable only for commands that
9157  * refer to components. Otherwise, this field is reserved.
9158  * Access: Index
9159  */
9160 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
9161 
9162 /* reg_mcc_update_handle
9163  * Token representing the current flow executed by the FSM.
9164  * Access: WO
9165  */
9166 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
9167 
9168 /* reg_mcc_error_code
9169  * Indicates the successful completion of the instruction, or the reason it
9170  * failed
9171  * Access: RO
9172  */
9173 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
9174 
9175 /* reg_mcc_control_state
9176  * Current FSM state
9177  * Access: RO
9178  */
9179 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
9180 
9181 /* reg_mcc_component_size
9182  * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
9183  * the size may shorten the update time. Value 0x0 means that size is
9184  * unspecified.
9185  * Access: WO
9186  */
9187 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
9188 
9189 static inline void mlxsw_reg_mcc_pack(char *payload,
9190 				      enum mlxsw_reg_mcc_instruction instr,
9191 				      u16 component_index, u32 update_handle,
9192 				      u32 component_size)
9193 {
9194 	MLXSW_REG_ZERO(mcc, payload);
9195 	mlxsw_reg_mcc_instruction_set(payload, instr);
9196 	mlxsw_reg_mcc_component_index_set(payload, component_index);
9197 	mlxsw_reg_mcc_update_handle_set(payload, update_handle);
9198 	mlxsw_reg_mcc_component_size_set(payload, component_size);
9199 }
9200 
9201 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
9202 					u8 *p_error_code, u8 *p_control_state)
9203 {
9204 	if (p_update_handle)
9205 		*p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
9206 	if (p_error_code)
9207 		*p_error_code = mlxsw_reg_mcc_error_code_get(payload);
9208 	if (p_control_state)
9209 		*p_control_state = mlxsw_reg_mcc_control_state_get(payload);
9210 }
9211 
9212 /* MCDA - Management Component Data Access
9213  * ---------------------------------------
9214  * This register allows reading and writing a firmware component.
9215  */
9216 #define MLXSW_REG_MCDA_ID 0x9063
9217 #define MLXSW_REG_MCDA_BASE_LEN 0x10
9218 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
9219 #define MLXSW_REG_MCDA_LEN \
9220 		(MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
9221 
9222 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
9223 
9224 /* reg_mcda_update_handle
9225  * Token representing the current flow executed by the FSM.
9226  * Access: RW
9227  */
9228 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
9229 
9230 /* reg_mcda_offset
9231  * Offset of accessed address relative to component start. Accesses must be in
9232  * accordance to log_mcda_word_size in MCQI reg.
9233  * Access: RW
9234  */
9235 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
9236 
9237 /* reg_mcda_size
9238  * Size of the data accessed, given in bytes.
9239  * Access: RW
9240  */
9241 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
9242 
9243 /* reg_mcda_data
9244  * Data block accessed.
9245  * Access: RW
9246  */
9247 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
9248 
9249 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
9250 				       u32 offset, u16 size, u8 *data)
9251 {
9252 	int i;
9253 
9254 	MLXSW_REG_ZERO(mcda, payload);
9255 	mlxsw_reg_mcda_update_handle_set(payload, update_handle);
9256 	mlxsw_reg_mcda_offset_set(payload, offset);
9257 	mlxsw_reg_mcda_size_set(payload, size);
9258 
9259 	for (i = 0; i < size / 4; i++)
9260 		mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
9261 }
9262 
9263 /* MPSC - Monitoring Packet Sampling Configuration Register
9264  * --------------------------------------------------------
9265  * MPSC Register is used to configure the Packet Sampling mechanism.
9266  */
9267 #define MLXSW_REG_MPSC_ID 0x9080
9268 #define MLXSW_REG_MPSC_LEN 0x1C
9269 
9270 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
9271 
9272 /* reg_mpsc_local_port
9273  * Local port number
9274  * Not supported for CPU port
9275  * Access: Index
9276  */
9277 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
9278 
9279 /* reg_mpsc_e
9280  * Enable sampling on port local_port
9281  * Access: RW
9282  */
9283 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
9284 
9285 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
9286 
9287 /* reg_mpsc_rate
9288  * Sampling rate = 1 out of rate packets (with randomization around
9289  * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
9290  * Access: RW
9291  */
9292 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
9293 
9294 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
9295 				       u32 rate)
9296 {
9297 	MLXSW_REG_ZERO(mpsc, payload);
9298 	mlxsw_reg_mpsc_local_port_set(payload, local_port);
9299 	mlxsw_reg_mpsc_e_set(payload, e);
9300 	mlxsw_reg_mpsc_rate_set(payload, rate);
9301 }
9302 
9303 /* MGPC - Monitoring General Purpose Counter Set Register
9304  * The MGPC register retrieves and sets the General Purpose Counter Set.
9305  */
9306 #define MLXSW_REG_MGPC_ID 0x9081
9307 #define MLXSW_REG_MGPC_LEN 0x18
9308 
9309 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
9310 
9311 /* reg_mgpc_counter_set_type
9312  * Counter set type.
9313  * Access: OP
9314  */
9315 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
9316 
9317 /* reg_mgpc_counter_index
9318  * Counter index.
9319  * Access: Index
9320  */
9321 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
9322 
9323 enum mlxsw_reg_mgpc_opcode {
9324 	/* Nop */
9325 	MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
9326 	/* Clear counters */
9327 	MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
9328 };
9329 
9330 /* reg_mgpc_opcode
9331  * Opcode.
9332  * Access: OP
9333  */
9334 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
9335 
9336 /* reg_mgpc_byte_counter
9337  * Byte counter value.
9338  * Access: RW
9339  */
9340 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
9341 
9342 /* reg_mgpc_packet_counter
9343  * Packet counter value.
9344  * Access: RW
9345  */
9346 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
9347 
9348 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
9349 				       enum mlxsw_reg_mgpc_opcode opcode,
9350 				       enum mlxsw_reg_flow_counter_set_type set_type)
9351 {
9352 	MLXSW_REG_ZERO(mgpc, payload);
9353 	mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
9354 	mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
9355 	mlxsw_reg_mgpc_opcode_set(payload, opcode);
9356 }
9357 
9358 /* MPRS - Monitoring Parsing State Register
9359  * ----------------------------------------
9360  * The MPRS register is used for setting up the parsing for hash,
9361  * policy-engine and routing.
9362  */
9363 #define MLXSW_REG_MPRS_ID 0x9083
9364 #define MLXSW_REG_MPRS_LEN 0x14
9365 
9366 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
9367 
9368 /* reg_mprs_parsing_depth
9369  * Minimum parsing depth.
9370  * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
9371  * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
9372  * Access: RW
9373  */
9374 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
9375 
9376 /* reg_mprs_parsing_en
9377  * Parsing enable.
9378  * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
9379  * NVGRE. Default is enabled. Reserved when SwitchX-2.
9380  * Access: RW
9381  */
9382 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
9383 
9384 /* reg_mprs_vxlan_udp_dport
9385  * VxLAN UDP destination port.
9386  * Used for identifying VxLAN packets and for dport field in
9387  * encapsulation. Default is 4789.
9388  * Access: RW
9389  */
9390 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
9391 
9392 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
9393 				       u16 vxlan_udp_dport)
9394 {
9395 	MLXSW_REG_ZERO(mprs, payload);
9396 	mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
9397 	mlxsw_reg_mprs_parsing_en_set(payload, true);
9398 	mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
9399 }
9400 
9401 /* MOGCR - Monitoring Global Configuration Register
9402  * ------------------------------------------------
9403  */
9404 #define MLXSW_REG_MOGCR_ID 0x9086
9405 #define MLXSW_REG_MOGCR_LEN 0x20
9406 
9407 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
9408 
9409 /* reg_mogcr_ptp_iftc
9410  * PTP Ingress FIFO Trap Clear
9411  * The PTP_ING_FIFO trap provides MTPPTR with clr according
9412  * to this value. Default 0.
9413  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9414  * Access: RW
9415  */
9416 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
9417 
9418 /* reg_mogcr_ptp_eftc
9419  * PTP Egress FIFO Trap Clear
9420  * The PTP_EGR_FIFO trap provides MTPPTR with clr according
9421  * to this value. Default 0.
9422  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9423  * Access: RW
9424  */
9425 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
9426 
9427 /* MTPPPC - Time Precision Packet Port Configuration
9428  * -------------------------------------------------
9429  * This register serves for configuration of which PTP messages should be
9430  * timestamped. This is a global configuration, despite the register name.
9431  *
9432  * Reserved when Spectrum-2.
9433  */
9434 #define MLXSW_REG_MTPPPC_ID 0x9090
9435 #define MLXSW_REG_MTPPPC_LEN 0x28
9436 
9437 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
9438 
9439 /* reg_mtpppc_ing_timestamp_message_type
9440  * Bitwise vector of PTP message types to timestamp at ingress.
9441  * MessageType field as defined by IEEE 1588
9442  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9443  * Default all 0
9444  * Access: RW
9445  */
9446 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
9447 
9448 /* reg_mtpppc_egr_timestamp_message_type
9449  * Bitwise vector of PTP message types to timestamp at egress.
9450  * MessageType field as defined by IEEE 1588
9451  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9452  * Default all 0
9453  * Access: RW
9454  */
9455 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
9456 
9457 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
9458 {
9459 	MLXSW_REG_ZERO(mtpppc, payload);
9460 	mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
9461 	mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
9462 }
9463 
9464 /* MTPPTR - Time Precision Packet Timestamping Reading
9465  * ---------------------------------------------------
9466  * The MTPPTR is used for reading the per port PTP timestamp FIFO.
9467  * There is a trap for packets which are latched to the timestamp FIFO, thus the
9468  * SW knows which FIFO to read. Note that packets enter the FIFO before been
9469  * trapped. The sequence number is used to synchronize the timestamp FIFO
9470  * entries and the trapped packets.
9471  * Reserved when Spectrum-2.
9472  */
9473 
9474 #define MLXSW_REG_MTPPTR_ID 0x9091
9475 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
9476 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
9477 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
9478 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN +		\
9479 		    MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
9480 
9481 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
9482 
9483 /* reg_mtpptr_local_port
9484  * Not supported for CPU port.
9485  * Access: Index
9486  */
9487 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
9488 
9489 enum mlxsw_reg_mtpptr_dir {
9490 	MLXSW_REG_MTPPTR_DIR_INGRESS,
9491 	MLXSW_REG_MTPPTR_DIR_EGRESS,
9492 };
9493 
9494 /* reg_mtpptr_dir
9495  * Direction.
9496  * Access: Index
9497  */
9498 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
9499 
9500 /* reg_mtpptr_clr
9501  * Clear the records.
9502  * Access: OP
9503  */
9504 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
9505 
9506 /* reg_mtpptr_num_rec
9507  * Number of valid records in the response
9508  * Range 0.. cap_ptp_timestamp_fifo
9509  * Access: RO
9510  */
9511 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
9512 
9513 /* reg_mtpptr_rec_message_type
9514  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
9515  * (e.g. Bit0: Sync, Bit1: Delay_Req)
9516  * Access: RO
9517  */
9518 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
9519 		     MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
9520 		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9521 
9522 /* reg_mtpptr_rec_domain_number
9523  * DomainNumber field as defined by IEEE 1588
9524  * Access: RO
9525  */
9526 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
9527 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
9528 		     MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9529 
9530 /* reg_mtpptr_rec_sequence_id
9531  * SequenceId field as defined by IEEE 1588
9532  * Access: RO
9533  */
9534 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
9535 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
9536 		     MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
9537 
9538 /* reg_mtpptr_rec_timestamp_high
9539  * Timestamp of when the PTP packet has passed through the port Units of PLL
9540  * clock time.
9541  * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
9542  * Access: RO
9543  */
9544 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
9545 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9546 		     MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
9547 
9548 /* reg_mtpptr_rec_timestamp_low
9549  * See rec_timestamp_high.
9550  * Access: RO
9551  */
9552 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
9553 		     MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9554 		     MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
9555 
9556 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
9557 					   unsigned int rec,
9558 					   u8 *p_message_type,
9559 					   u8 *p_domain_number,
9560 					   u16 *p_sequence_id,
9561 					   u64 *p_timestamp)
9562 {
9563 	u32 timestamp_high, timestamp_low;
9564 
9565 	*p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
9566 	*p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
9567 	*p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
9568 	timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
9569 	timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
9570 	*p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
9571 }
9572 
9573 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
9574  * ---------------------------------------------------------
9575  * This register is used for configuring under which trap to deliver PTP
9576  * packets depending on type of the packet.
9577  */
9578 #define MLXSW_REG_MTPTPT_ID 0x9092
9579 #define MLXSW_REG_MTPTPT_LEN 0x08
9580 
9581 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
9582 
9583 enum mlxsw_reg_mtptpt_trap_id {
9584 	MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
9585 	MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
9586 };
9587 
9588 /* reg_mtptpt_trap_id
9589  * Trap id.
9590  * Access: Index
9591  */
9592 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
9593 
9594 /* reg_mtptpt_message_type
9595  * Bitwise vector of PTP message types to trap. This is a necessary but
9596  * non-sufficient condition since need to enable also per port. See MTPPPC.
9597  * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
9598  * Bit0: Sync, Bit1: Delay_Req)
9599  */
9600 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
9601 
9602 static inline void mlxsw_reg_mtptptp_pack(char *payload,
9603 					  enum mlxsw_reg_mtptpt_trap_id trap_id,
9604 					  u16 message_type)
9605 {
9606 	MLXSW_REG_ZERO(mtptpt, payload);
9607 	mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
9608 	mlxsw_reg_mtptpt_message_type_set(payload, message_type);
9609 }
9610 
9611 /* MGPIR - Management General Peripheral Information Register
9612  * ----------------------------------------------------------
9613  * MGPIR register allows software to query the hardware and
9614  * firmware general information of peripheral entities.
9615  */
9616 #define MLXSW_REG_MGPIR_ID 0x9100
9617 #define MLXSW_REG_MGPIR_LEN 0xA0
9618 
9619 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
9620 
9621 enum mlxsw_reg_mgpir_device_type {
9622 	MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
9623 	MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
9624 };
9625 
9626 /* device_type
9627  * Access: RO
9628  */
9629 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
9630 
9631 /* devices_per_flash
9632  * Number of devices of device_type per flash (can be shared by few devices).
9633  * Access: RO
9634  */
9635 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
9636 
9637 /* num_of_devices
9638  * Number of devices of device_type.
9639  * Access: RO
9640  */
9641 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
9642 
9643 /* num_of_modules
9644  * Number of modules.
9645  * Access: RO
9646  */
9647 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
9648 
9649 static inline void mlxsw_reg_mgpir_pack(char *payload)
9650 {
9651 	MLXSW_REG_ZERO(mgpir, payload);
9652 }
9653 
9654 static inline void
9655 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
9656 		       enum mlxsw_reg_mgpir_device_type *device_type,
9657 		       u8 *devices_per_flash, u8 *num_of_modules)
9658 {
9659 	if (num_of_devices)
9660 		*num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
9661 	if (device_type)
9662 		*device_type = mlxsw_reg_mgpir_device_type_get(payload);
9663 	if (devices_per_flash)
9664 		*devices_per_flash =
9665 				mlxsw_reg_mgpir_devices_per_flash_get(payload);
9666 	if (num_of_modules)
9667 		*num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
9668 }
9669 
9670 /* TNGCR - Tunneling NVE General Configuration Register
9671  * ----------------------------------------------------
9672  * The TNGCR register is used for setting up the NVE Tunneling configuration.
9673  */
9674 #define MLXSW_REG_TNGCR_ID 0xA001
9675 #define MLXSW_REG_TNGCR_LEN 0x44
9676 
9677 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
9678 
9679 enum mlxsw_reg_tngcr_type {
9680 	MLXSW_REG_TNGCR_TYPE_VXLAN,
9681 	MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
9682 	MLXSW_REG_TNGCR_TYPE_GENEVE,
9683 	MLXSW_REG_TNGCR_TYPE_NVGRE,
9684 };
9685 
9686 /* reg_tngcr_type
9687  * Tunnel type for encapsulation and decapsulation. The types are mutually
9688  * exclusive.
9689  * Note: For Spectrum the NVE parsing must be enabled in MPRS.
9690  * Access: RW
9691  */
9692 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
9693 
9694 /* reg_tngcr_nve_valid
9695  * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
9696  * Access: RW
9697  */
9698 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
9699 
9700 /* reg_tngcr_nve_ttl_uc
9701  * The TTL for NVE tunnel encapsulation underlay unicast packets.
9702  * Access: RW
9703  */
9704 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
9705 
9706 /* reg_tngcr_nve_ttl_mc
9707  * The TTL for NVE tunnel encapsulation underlay multicast packets.
9708  * Access: RW
9709  */
9710 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
9711 
9712 enum {
9713 	/* Do not copy flow label. Calculate flow label using nve_flh. */
9714 	MLXSW_REG_TNGCR_FL_NO_COPY,
9715 	/* Copy flow label from inner packet if packet is IPv6 and
9716 	 * encapsulation is by IPv6. Otherwise, calculate flow label using
9717 	 * nve_flh.
9718 	 */
9719 	MLXSW_REG_TNGCR_FL_COPY,
9720 };
9721 
9722 /* reg_tngcr_nve_flc
9723  * For NVE tunnel encapsulation: Flow label copy from inner packet.
9724  * Access: RW
9725  */
9726 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
9727 
9728 enum {
9729 	/* Flow label is static. In Spectrum this means '0'. Spectrum-2
9730 	 * uses {nve_fl_prefix, nve_fl_suffix}.
9731 	 */
9732 	MLXSW_REG_TNGCR_FL_NO_HASH,
9733 	/* 8 LSBs of the flow label are calculated from ECMP hash of the
9734 	 * inner packet. 12 MSBs are configured by nve_fl_prefix.
9735 	 */
9736 	MLXSW_REG_TNGCR_FL_HASH,
9737 };
9738 
9739 /* reg_tngcr_nve_flh
9740  * NVE flow label hash.
9741  * Access: RW
9742  */
9743 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
9744 
9745 /* reg_tngcr_nve_fl_prefix
9746  * NVE flow label prefix. Constant 12 MSBs of the flow label.
9747  * Access: RW
9748  */
9749 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
9750 
9751 /* reg_tngcr_nve_fl_suffix
9752  * NVE flow label suffix. Constant 8 LSBs of the flow label.
9753  * Reserved when nve_flh=1 and for Spectrum.
9754  * Access: RW
9755  */
9756 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
9757 
9758 enum {
9759 	/* Source UDP port is fixed (default '0') */
9760 	MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
9761 	/* Source UDP port is calculated based on hash */
9762 	MLXSW_REG_TNGCR_UDP_SPORT_HASH,
9763 };
9764 
9765 /* reg_tngcr_nve_udp_sport_type
9766  * NVE UDP source port type.
9767  * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
9768  * When the source UDP port is calculated based on hash, then the 8 LSBs
9769  * are calculated from hash the 8 MSBs are configured by
9770  * nve_udp_sport_prefix.
9771  * Access: RW
9772  */
9773 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
9774 
9775 /* reg_tngcr_nve_udp_sport_prefix
9776  * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
9777  * Reserved when NVE type is NVGRE.
9778  * Access: RW
9779  */
9780 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
9781 
9782 /* reg_tngcr_nve_group_size_mc
9783  * The amount of sequential linked lists of MC entries. The first linked
9784  * list is configured by SFD.underlay_mc_ptr.
9785  * Valid values: 1, 2, 4, 8, 16, 32, 64
9786  * The linked list are configured by TNUMT.
9787  * The hash is set by LAG hash.
9788  * Access: RW
9789  */
9790 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
9791 
9792 /* reg_tngcr_nve_group_size_flood
9793  * The amount of sequential linked lists of flooding entries. The first
9794  * linked list is configured by SFMR.nve_tunnel_flood_ptr
9795  * Valid values: 1, 2, 4, 8, 16, 32, 64
9796  * The linked list are configured by TNUMT.
9797  * The hash is set by LAG hash.
9798  * Access: RW
9799  */
9800 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
9801 
9802 /* reg_tngcr_learn_enable
9803  * During decapsulation, whether to learn from NVE port.
9804  * Reserved when Spectrum-2. See TNPC.
9805  * Access: RW
9806  */
9807 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
9808 
9809 /* reg_tngcr_underlay_virtual_router
9810  * Underlay virtual router.
9811  * Reserved when Spectrum-2.
9812  * Access: RW
9813  */
9814 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
9815 
9816 /* reg_tngcr_underlay_rif
9817  * Underlay ingress router interface. RIF type should be loopback generic.
9818  * Reserved when Spectrum.
9819  * Access: RW
9820  */
9821 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
9822 
9823 /* reg_tngcr_usipv4
9824  * Underlay source IPv4 address of the NVE.
9825  * Access: RW
9826  */
9827 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
9828 
9829 /* reg_tngcr_usipv6
9830  * Underlay source IPv6 address of the NVE. For Spectrum, must not be
9831  * modified under traffic of NVE tunneling encapsulation.
9832  * Access: RW
9833  */
9834 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
9835 
9836 static inline void mlxsw_reg_tngcr_pack(char *payload,
9837 					enum mlxsw_reg_tngcr_type type,
9838 					bool valid, u8 ttl)
9839 {
9840 	MLXSW_REG_ZERO(tngcr, payload);
9841 	mlxsw_reg_tngcr_type_set(payload, type);
9842 	mlxsw_reg_tngcr_nve_valid_set(payload, valid);
9843 	mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
9844 	mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
9845 	mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
9846 	mlxsw_reg_tngcr_nve_flh_set(payload, 0);
9847 	mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
9848 					       MLXSW_REG_TNGCR_UDP_SPORT_HASH);
9849 	mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
9850 	mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
9851 	mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
9852 }
9853 
9854 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
9855  * -------------------------------------------------------
9856  * The TNUMT register is for building the underlay MC table. It is used
9857  * for MC, flooding and BC traffic into the NVE tunnel.
9858  */
9859 #define MLXSW_REG_TNUMT_ID 0xA003
9860 #define MLXSW_REG_TNUMT_LEN 0x20
9861 
9862 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
9863 
9864 enum mlxsw_reg_tnumt_record_type {
9865 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
9866 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
9867 	MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
9868 };
9869 
9870 /* reg_tnumt_record_type
9871  * Record type.
9872  * Access: RW
9873  */
9874 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
9875 
9876 enum mlxsw_reg_tnumt_tunnel_port {
9877 	MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
9878 	MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
9879 	MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
9880 	MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
9881 };
9882 
9883 /* reg_tnumt_tunnel_port
9884  * Tunnel port.
9885  * Access: RW
9886  */
9887 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
9888 
9889 /* reg_tnumt_underlay_mc_ptr
9890  * Index to the underlay multicast table.
9891  * For Spectrum the index is to the KVD linear.
9892  * Access: Index
9893  */
9894 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
9895 
9896 /* reg_tnumt_vnext
9897  * The next_underlay_mc_ptr is valid.
9898  * Access: RW
9899  */
9900 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
9901 
9902 /* reg_tnumt_next_underlay_mc_ptr
9903  * The next index to the underlay multicast table.
9904  * Access: RW
9905  */
9906 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
9907 
9908 /* reg_tnumt_record_size
9909  * Number of IP addresses in the record.
9910  * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
9911  * Access: RW
9912  */
9913 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
9914 
9915 /* reg_tnumt_udip
9916  * The underlay IPv4 addresses. udip[i] is reserved if i >= size
9917  * Access: RW
9918  */
9919 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
9920 
9921 /* reg_tnumt_udip_ptr
9922  * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
9923  * i >= size. The IPv6 addresses are configured by RIPS.
9924  * Access: RW
9925  */
9926 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
9927 
9928 static inline void mlxsw_reg_tnumt_pack(char *payload,
9929 					enum mlxsw_reg_tnumt_record_type type,
9930 					enum mlxsw_reg_tnumt_tunnel_port tport,
9931 					u32 underlay_mc_ptr, bool vnext,
9932 					u32 next_underlay_mc_ptr,
9933 					u8 record_size)
9934 {
9935 	MLXSW_REG_ZERO(tnumt, payload);
9936 	mlxsw_reg_tnumt_record_type_set(payload, type);
9937 	mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
9938 	mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
9939 	mlxsw_reg_tnumt_vnext_set(payload, vnext);
9940 	mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
9941 	mlxsw_reg_tnumt_record_size_set(payload, record_size);
9942 }
9943 
9944 /* TNQCR - Tunneling NVE QoS Configuration Register
9945  * ------------------------------------------------
9946  * The TNQCR register configures how QoS is set in encapsulation into the
9947  * underlay network.
9948  */
9949 #define MLXSW_REG_TNQCR_ID 0xA010
9950 #define MLXSW_REG_TNQCR_LEN 0x0C
9951 
9952 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
9953 
9954 /* reg_tnqcr_enc_set_dscp
9955  * For encapsulation: How to set DSCP field:
9956  * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
9957  * (outer) IP header. If there is no IP header, use TNQDR.dscp
9958  * 1 - Set the DSCP field as TNQDR.dscp
9959  * Access: RW
9960  */
9961 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
9962 
9963 static inline void mlxsw_reg_tnqcr_pack(char *payload)
9964 {
9965 	MLXSW_REG_ZERO(tnqcr, payload);
9966 	mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
9967 }
9968 
9969 /* TNQDR - Tunneling NVE QoS Default Register
9970  * ------------------------------------------
9971  * The TNQDR register configures the default QoS settings for NVE
9972  * encapsulation.
9973  */
9974 #define MLXSW_REG_TNQDR_ID 0xA011
9975 #define MLXSW_REG_TNQDR_LEN 0x08
9976 
9977 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
9978 
9979 /* reg_tnqdr_local_port
9980  * Local port number (receive port). CPU port is supported.
9981  * Access: Index
9982  */
9983 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
9984 
9985 /* reg_tnqdr_dscp
9986  * For encapsulation, the default DSCP.
9987  * Access: RW
9988  */
9989 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
9990 
9991 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
9992 {
9993 	MLXSW_REG_ZERO(tnqdr, payload);
9994 	mlxsw_reg_tnqdr_local_port_set(payload, local_port);
9995 	mlxsw_reg_tnqdr_dscp_set(payload, 0);
9996 }
9997 
9998 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
9999  * --------------------------------------------------------
10000  * The TNEEM register maps ECN of the IP header at the ingress to the
10001  * encapsulation to the ECN of the underlay network.
10002  */
10003 #define MLXSW_REG_TNEEM_ID 0xA012
10004 #define MLXSW_REG_TNEEM_LEN 0x0C
10005 
10006 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
10007 
10008 /* reg_tneem_overlay_ecn
10009  * ECN of the IP header in the overlay network.
10010  * Access: Index
10011  */
10012 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
10013 
10014 /* reg_tneem_underlay_ecn
10015  * ECN of the IP header in the underlay network.
10016  * Access: RW
10017  */
10018 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
10019 
10020 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
10021 					u8 underlay_ecn)
10022 {
10023 	MLXSW_REG_ZERO(tneem, payload);
10024 	mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
10025 	mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
10026 }
10027 
10028 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
10029  * --------------------------------------------------------
10030  * The TNDEM register configures the actions that are done in the
10031  * decapsulation.
10032  */
10033 #define MLXSW_REG_TNDEM_ID 0xA013
10034 #define MLXSW_REG_TNDEM_LEN 0x0C
10035 
10036 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
10037 
10038 /* reg_tndem_underlay_ecn
10039  * ECN field of the IP header in the underlay network.
10040  * Access: Index
10041  */
10042 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
10043 
10044 /* reg_tndem_overlay_ecn
10045  * ECN field of the IP header in the overlay network.
10046  * Access: Index
10047  */
10048 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
10049 
10050 /* reg_tndem_eip_ecn
10051  * Egress IP ECN. ECN field of the IP header of the packet which goes out
10052  * from the decapsulation.
10053  * Access: RW
10054  */
10055 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
10056 
10057 /* reg_tndem_trap_en
10058  * Trap enable:
10059  * 0 - No trap due to decap ECN
10060  * 1 - Trap enable with trap_id
10061  * Access: RW
10062  */
10063 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
10064 
10065 /* reg_tndem_trap_id
10066  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
10067  * Reserved when trap_en is '0'.
10068  * Access: RW
10069  */
10070 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
10071 
10072 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
10073 					u8 overlay_ecn, u8 ecn, bool trap_en,
10074 					u16 trap_id)
10075 {
10076 	MLXSW_REG_ZERO(tndem, payload);
10077 	mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
10078 	mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
10079 	mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
10080 	mlxsw_reg_tndem_trap_en_set(payload, trap_en);
10081 	mlxsw_reg_tndem_trap_id_set(payload, trap_id);
10082 }
10083 
10084 /* TNPC - Tunnel Port Configuration Register
10085  * -----------------------------------------
10086  * The TNPC register is used for tunnel port configuration.
10087  * Reserved when Spectrum.
10088  */
10089 #define MLXSW_REG_TNPC_ID 0xA020
10090 #define MLXSW_REG_TNPC_LEN 0x18
10091 
10092 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
10093 
10094 enum mlxsw_reg_tnpc_tunnel_port {
10095 	MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
10096 	MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
10097 	MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
10098 	MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
10099 };
10100 
10101 /* reg_tnpc_tunnel_port
10102  * Tunnel port.
10103  * Access: Index
10104  */
10105 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
10106 
10107 /* reg_tnpc_learn_enable_v6
10108  * During IPv6 underlay decapsulation, whether to learn from tunnel port.
10109  * Access: RW
10110  */
10111 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
10112 
10113 /* reg_tnpc_learn_enable_v4
10114  * During IPv4 underlay decapsulation, whether to learn from tunnel port.
10115  * Access: RW
10116  */
10117 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
10118 
10119 static inline void mlxsw_reg_tnpc_pack(char *payload,
10120 				       enum mlxsw_reg_tnpc_tunnel_port tport,
10121 				       bool learn_enable)
10122 {
10123 	MLXSW_REG_ZERO(tnpc, payload);
10124 	mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
10125 	mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
10126 	mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
10127 }
10128 
10129 /* TIGCR - Tunneling IPinIP General Configuration Register
10130  * -------------------------------------------------------
10131  * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
10132  */
10133 #define MLXSW_REG_TIGCR_ID 0xA801
10134 #define MLXSW_REG_TIGCR_LEN 0x10
10135 
10136 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
10137 
10138 /* reg_tigcr_ipip_ttlc
10139  * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
10140  * header.
10141  * Access: RW
10142  */
10143 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
10144 
10145 /* reg_tigcr_ipip_ttl_uc
10146  * The TTL for IPinIP Tunnel encapsulation of unicast packets if
10147  * reg_tigcr_ipip_ttlc is unset.
10148  * Access: RW
10149  */
10150 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
10151 
10152 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
10153 {
10154 	MLXSW_REG_ZERO(tigcr, payload);
10155 	mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
10156 	mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
10157 }
10158 
10159 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register
10160  * -----------------------------------------------------------
10161  * The TIEEM register maps ECN of the IP header at the ingress to the
10162  * encapsulation to the ECN of the underlay network.
10163  */
10164 #define MLXSW_REG_TIEEM_ID 0xA812
10165 #define MLXSW_REG_TIEEM_LEN 0x0C
10166 
10167 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);
10168 
10169 /* reg_tieem_overlay_ecn
10170  * ECN of the IP header in the overlay network.
10171  * Access: Index
10172  */
10173 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
10174 
10175 /* reg_tineem_underlay_ecn
10176  * ECN of the IP header in the underlay network.
10177  * Access: RW
10178  */
10179 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
10180 
10181 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,
10182 					u8 underlay_ecn)
10183 {
10184 	MLXSW_REG_ZERO(tieem, payload);
10185 	mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);
10186 	mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);
10187 }
10188 
10189 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register
10190  * -----------------------------------------------------------
10191  * The TIDEM register configures the actions that are done in the
10192  * decapsulation.
10193  */
10194 #define MLXSW_REG_TIDEM_ID 0xA813
10195 #define MLXSW_REG_TIDEM_LEN 0x0C
10196 
10197 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);
10198 
10199 /* reg_tidem_underlay_ecn
10200  * ECN field of the IP header in the underlay network.
10201  * Access: Index
10202  */
10203 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
10204 
10205 /* reg_tidem_overlay_ecn
10206  * ECN field of the IP header in the overlay network.
10207  * Access: Index
10208  */
10209 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
10210 
10211 /* reg_tidem_eip_ecn
10212  * Egress IP ECN. ECN field of the IP header of the packet which goes out
10213  * from the decapsulation.
10214  * Access: RW
10215  */
10216 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
10217 
10218 /* reg_tidem_trap_en
10219  * Trap enable:
10220  * 0 - No trap due to decap ECN
10221  * 1 - Trap enable with trap_id
10222  * Access: RW
10223  */
10224 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
10225 
10226 /* reg_tidem_trap_id
10227  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
10228  * Reserved when trap_en is '0'.
10229  * Access: RW
10230  */
10231 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
10232 
10233 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,
10234 					u8 overlay_ecn, u8 eip_ecn,
10235 					bool trap_en, u16 trap_id)
10236 {
10237 	MLXSW_REG_ZERO(tidem, payload);
10238 	mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);
10239 	mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);
10240 	mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);
10241 	mlxsw_reg_tidem_trap_en_set(payload, trap_en);
10242 	mlxsw_reg_tidem_trap_id_set(payload, trap_id);
10243 }
10244 
10245 /* SBPR - Shared Buffer Pools Register
10246  * -----------------------------------
10247  * The SBPR configures and retrieves the shared buffer pools and configuration.
10248  */
10249 #define MLXSW_REG_SBPR_ID 0xB001
10250 #define MLXSW_REG_SBPR_LEN 0x14
10251 
10252 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
10253 
10254 /* shared direstion enum for SBPR, SBCM, SBPM */
10255 enum mlxsw_reg_sbxx_dir {
10256 	MLXSW_REG_SBXX_DIR_INGRESS,
10257 	MLXSW_REG_SBXX_DIR_EGRESS,
10258 };
10259 
10260 /* reg_sbpr_dir
10261  * Direction.
10262  * Access: Index
10263  */
10264 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
10265 
10266 /* reg_sbpr_pool
10267  * Pool index.
10268  * Access: Index
10269  */
10270 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
10271 
10272 /* reg_sbpr_infi_size
10273  * Size is infinite.
10274  * Access: RW
10275  */
10276 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
10277 
10278 /* reg_sbpr_size
10279  * Pool size in buffer cells.
10280  * Reserved when infi_size = 1.
10281  * Access: RW
10282  */
10283 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
10284 
10285 enum mlxsw_reg_sbpr_mode {
10286 	MLXSW_REG_SBPR_MODE_STATIC,
10287 	MLXSW_REG_SBPR_MODE_DYNAMIC,
10288 };
10289 
10290 /* reg_sbpr_mode
10291  * Pool quota calculation mode.
10292  * Access: RW
10293  */
10294 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
10295 
10296 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
10297 				       enum mlxsw_reg_sbxx_dir dir,
10298 				       enum mlxsw_reg_sbpr_mode mode, u32 size,
10299 				       bool infi_size)
10300 {
10301 	MLXSW_REG_ZERO(sbpr, payload);
10302 	mlxsw_reg_sbpr_pool_set(payload, pool);
10303 	mlxsw_reg_sbpr_dir_set(payload, dir);
10304 	mlxsw_reg_sbpr_mode_set(payload, mode);
10305 	mlxsw_reg_sbpr_size_set(payload, size);
10306 	mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
10307 }
10308 
10309 /* SBCM - Shared Buffer Class Management Register
10310  * ----------------------------------------------
10311  * The SBCM register configures and retrieves the shared buffer allocation
10312  * and configuration according to Port-PG, including the binding to pool
10313  * and definition of the associated quota.
10314  */
10315 #define MLXSW_REG_SBCM_ID 0xB002
10316 #define MLXSW_REG_SBCM_LEN 0x28
10317 
10318 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
10319 
10320 /* reg_sbcm_local_port
10321  * Local port number.
10322  * For Ingress: excludes CPU port and Router port
10323  * For Egress: excludes IP Router
10324  * Access: Index
10325  */
10326 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
10327 
10328 /* reg_sbcm_pg_buff
10329  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
10330  * For PG buffer: range is 0..cap_max_pg_buffers - 1
10331  * For traffic class: range is 0..cap_max_tclass - 1
10332  * Note that when traffic class is in MC aware mode then the traffic
10333  * classes which are MC aware cannot be configured.
10334  * Access: Index
10335  */
10336 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
10337 
10338 /* reg_sbcm_dir
10339  * Direction.
10340  * Access: Index
10341  */
10342 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
10343 
10344 /* reg_sbcm_min_buff
10345  * Minimum buffer size for the limiter, in cells.
10346  * Access: RW
10347  */
10348 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
10349 
10350 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
10351 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
10352 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
10353 
10354 /* reg_sbcm_infi_max
10355  * Max buffer is infinite.
10356  * Access: RW
10357  */
10358 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
10359 
10360 /* reg_sbcm_max_buff
10361  * When the pool associated to the port-pg/tclass is configured to
10362  * static, Maximum buffer size for the limiter configured in cells.
10363  * When the pool associated to the port-pg/tclass is configured to
10364  * dynamic, the max_buff holds the "alpha" parameter, supporting
10365  * the following values:
10366  * 0: 0
10367  * i: (1/128)*2^(i-1), for i=1..14
10368  * 0xFF: Infinity
10369  * Reserved when infi_max = 1.
10370  * Access: RW
10371  */
10372 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
10373 
10374 /* reg_sbcm_pool
10375  * Association of the port-priority to a pool.
10376  * Access: RW
10377  */
10378 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
10379 
10380 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
10381 				       enum mlxsw_reg_sbxx_dir dir,
10382 				       u32 min_buff, u32 max_buff,
10383 				       bool infi_max, u8 pool)
10384 {
10385 	MLXSW_REG_ZERO(sbcm, payload);
10386 	mlxsw_reg_sbcm_local_port_set(payload, local_port);
10387 	mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
10388 	mlxsw_reg_sbcm_dir_set(payload, dir);
10389 	mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
10390 	mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
10391 	mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
10392 	mlxsw_reg_sbcm_pool_set(payload, pool);
10393 }
10394 
10395 /* SBPM - Shared Buffer Port Management Register
10396  * ---------------------------------------------
10397  * The SBPM register configures and retrieves the shared buffer allocation
10398  * and configuration according to Port-Pool, including the definition
10399  * of the associated quota.
10400  */
10401 #define MLXSW_REG_SBPM_ID 0xB003
10402 #define MLXSW_REG_SBPM_LEN 0x28
10403 
10404 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
10405 
10406 /* reg_sbpm_local_port
10407  * Local port number.
10408  * For Ingress: excludes CPU port and Router port
10409  * For Egress: excludes IP Router
10410  * Access: Index
10411  */
10412 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
10413 
10414 /* reg_sbpm_pool
10415  * The pool associated to quota counting on the local_port.
10416  * Access: Index
10417  */
10418 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
10419 
10420 /* reg_sbpm_dir
10421  * Direction.
10422  * Access: Index
10423  */
10424 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
10425 
10426 /* reg_sbpm_buff_occupancy
10427  * Current buffer occupancy in cells.
10428  * Access: RO
10429  */
10430 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
10431 
10432 /* reg_sbpm_clr
10433  * Clear Max Buffer Occupancy
10434  * When this bit is set, max_buff_occupancy field is cleared (and a
10435  * new max value is tracked from the time the clear was performed).
10436  * Access: OP
10437  */
10438 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
10439 
10440 /* reg_sbpm_max_buff_occupancy
10441  * Maximum value of buffer occupancy in cells monitored. Cleared by
10442  * writing to the clr field.
10443  * Access: RO
10444  */
10445 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
10446 
10447 /* reg_sbpm_min_buff
10448  * Minimum buffer size for the limiter, in cells.
10449  * Access: RW
10450  */
10451 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
10452 
10453 /* reg_sbpm_max_buff
10454  * When the pool associated to the port-pg/tclass is configured to
10455  * static, Maximum buffer size for the limiter configured in cells.
10456  * When the pool associated to the port-pg/tclass is configured to
10457  * dynamic, the max_buff holds the "alpha" parameter, supporting
10458  * the following values:
10459  * 0: 0
10460  * i: (1/128)*2^(i-1), for i=1..14
10461  * 0xFF: Infinity
10462  * Access: RW
10463  */
10464 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
10465 
10466 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
10467 				       enum mlxsw_reg_sbxx_dir dir, bool clr,
10468 				       u32 min_buff, u32 max_buff)
10469 {
10470 	MLXSW_REG_ZERO(sbpm, payload);
10471 	mlxsw_reg_sbpm_local_port_set(payload, local_port);
10472 	mlxsw_reg_sbpm_pool_set(payload, pool);
10473 	mlxsw_reg_sbpm_dir_set(payload, dir);
10474 	mlxsw_reg_sbpm_clr_set(payload, clr);
10475 	mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
10476 	mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
10477 }
10478 
10479 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
10480 					 u32 *p_max_buff_occupancy)
10481 {
10482 	*p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
10483 	*p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
10484 }
10485 
10486 /* SBMM - Shared Buffer Multicast Management Register
10487  * --------------------------------------------------
10488  * The SBMM register configures and retrieves the shared buffer allocation
10489  * and configuration for MC packets according to Switch-Priority, including
10490  * the binding to pool and definition of the associated quota.
10491  */
10492 #define MLXSW_REG_SBMM_ID 0xB004
10493 #define MLXSW_REG_SBMM_LEN 0x28
10494 
10495 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
10496 
10497 /* reg_sbmm_prio
10498  * Switch Priority.
10499  * Access: Index
10500  */
10501 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
10502 
10503 /* reg_sbmm_min_buff
10504  * Minimum buffer size for the limiter, in cells.
10505  * Access: RW
10506  */
10507 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
10508 
10509 /* reg_sbmm_max_buff
10510  * When the pool associated to the port-pg/tclass is configured to
10511  * static, Maximum buffer size for the limiter configured in cells.
10512  * When the pool associated to the port-pg/tclass is configured to
10513  * dynamic, the max_buff holds the "alpha" parameter, supporting
10514  * the following values:
10515  * 0: 0
10516  * i: (1/128)*2^(i-1), for i=1..14
10517  * 0xFF: Infinity
10518  * Access: RW
10519  */
10520 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
10521 
10522 /* reg_sbmm_pool
10523  * Association of the port-priority to a pool.
10524  * Access: RW
10525  */
10526 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
10527 
10528 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
10529 				       u32 max_buff, u8 pool)
10530 {
10531 	MLXSW_REG_ZERO(sbmm, payload);
10532 	mlxsw_reg_sbmm_prio_set(payload, prio);
10533 	mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
10534 	mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
10535 	mlxsw_reg_sbmm_pool_set(payload, pool);
10536 }
10537 
10538 /* SBSR - Shared Buffer Status Register
10539  * ------------------------------------
10540  * The SBSR register retrieves the shared buffer occupancy according to
10541  * Port-Pool. Note that this register enables reading a large amount of data.
10542  * It is the user's responsibility to limit the amount of data to ensure the
10543  * response can match the maximum transfer unit. In case the response exceeds
10544  * the maximum transport unit, it will be truncated with no special notice.
10545  */
10546 #define MLXSW_REG_SBSR_ID 0xB005
10547 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
10548 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
10549 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
10550 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +	\
10551 			    MLXSW_REG_SBSR_REC_LEN *	\
10552 			    MLXSW_REG_SBSR_REC_MAX_COUNT)
10553 
10554 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
10555 
10556 /* reg_sbsr_clr
10557  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
10558  * field is cleared (and a new max value is tracked from the time the clear
10559  * was performed).
10560  * Access: OP
10561  */
10562 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
10563 
10564 /* reg_sbsr_ingress_port_mask
10565  * Bit vector for all ingress network ports.
10566  * Indicates which of the ports (for which the relevant bit is set)
10567  * are affected by the set operation. Configuration of any other port
10568  * does not change.
10569  * Access: Index
10570  */
10571 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
10572 
10573 /* reg_sbsr_pg_buff_mask
10574  * Bit vector for all switch priority groups.
10575  * Indicates which of the priorities (for which the relevant bit is set)
10576  * are affected by the set operation. Configuration of any other priority
10577  * does not change.
10578  * Range is 0..cap_max_pg_buffers - 1
10579  * Access: Index
10580  */
10581 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
10582 
10583 /* reg_sbsr_egress_port_mask
10584  * Bit vector for all egress network ports.
10585  * Indicates which of the ports (for which the relevant bit is set)
10586  * are affected by the set operation. Configuration of any other port
10587  * does not change.
10588  * Access: Index
10589  */
10590 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
10591 
10592 /* reg_sbsr_tclass_mask
10593  * Bit vector for all traffic classes.
10594  * Indicates which of the traffic classes (for which the relevant bit is
10595  * set) are affected by the set operation. Configuration of any other
10596  * traffic class does not change.
10597  * Range is 0..cap_max_tclass - 1
10598  * Access: Index
10599  */
10600 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
10601 
10602 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
10603 {
10604 	MLXSW_REG_ZERO(sbsr, payload);
10605 	mlxsw_reg_sbsr_clr_set(payload, clr);
10606 }
10607 
10608 /* reg_sbsr_rec_buff_occupancy
10609  * Current buffer occupancy in cells.
10610  * Access: RO
10611  */
10612 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10613 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
10614 
10615 /* reg_sbsr_rec_max_buff_occupancy
10616  * Maximum value of buffer occupancy in cells monitored. Cleared by
10617  * writing to the clr field.
10618  * Access: RO
10619  */
10620 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10621 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
10622 
10623 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
10624 					     u32 *p_buff_occupancy,
10625 					     u32 *p_max_buff_occupancy)
10626 {
10627 	*p_buff_occupancy =
10628 		mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
10629 	*p_max_buff_occupancy =
10630 		mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
10631 }
10632 
10633 /* SBIB - Shared Buffer Internal Buffer Register
10634  * ---------------------------------------------
10635  * The SBIB register configures per port buffers for internal use. The internal
10636  * buffers consume memory on the port buffers (note that the port buffers are
10637  * used also by PBMC).
10638  *
10639  * For Spectrum this is used for egress mirroring.
10640  */
10641 #define MLXSW_REG_SBIB_ID 0xB006
10642 #define MLXSW_REG_SBIB_LEN 0x10
10643 
10644 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
10645 
10646 /* reg_sbib_local_port
10647  * Local port number
10648  * Not supported for CPU port and router port
10649  * Access: Index
10650  */
10651 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
10652 
10653 /* reg_sbib_buff_size
10654  * Units represented in cells
10655  * Allowed range is 0 to (cap_max_headroom_size - 1)
10656  * Default is 0
10657  * Access: RW
10658  */
10659 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
10660 
10661 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
10662 				       u32 buff_size)
10663 {
10664 	MLXSW_REG_ZERO(sbib, payload);
10665 	mlxsw_reg_sbib_local_port_set(payload, local_port);
10666 	mlxsw_reg_sbib_buff_size_set(payload, buff_size);
10667 }
10668 
10669 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
10670 	MLXSW_REG(sgcr),
10671 	MLXSW_REG(spad),
10672 	MLXSW_REG(smid),
10673 	MLXSW_REG(sspr),
10674 	MLXSW_REG(sfdat),
10675 	MLXSW_REG(sfd),
10676 	MLXSW_REG(sfn),
10677 	MLXSW_REG(spms),
10678 	MLXSW_REG(spvid),
10679 	MLXSW_REG(spvm),
10680 	MLXSW_REG(spaft),
10681 	MLXSW_REG(sfgc),
10682 	MLXSW_REG(sftr),
10683 	MLXSW_REG(sfdf),
10684 	MLXSW_REG(sldr),
10685 	MLXSW_REG(slcr),
10686 	MLXSW_REG(slcor),
10687 	MLXSW_REG(spmlr),
10688 	MLXSW_REG(svfa),
10689 	MLXSW_REG(svpe),
10690 	MLXSW_REG(sfmr),
10691 	MLXSW_REG(spvmlr),
10692 	MLXSW_REG(cwtp),
10693 	MLXSW_REG(cwtpm),
10694 	MLXSW_REG(pgcr),
10695 	MLXSW_REG(ppbt),
10696 	MLXSW_REG(pacl),
10697 	MLXSW_REG(pagt),
10698 	MLXSW_REG(ptar),
10699 	MLXSW_REG(ppbs),
10700 	MLXSW_REG(prcr),
10701 	MLXSW_REG(pefa),
10702 	MLXSW_REG(pemrbt),
10703 	MLXSW_REG(ptce2),
10704 	MLXSW_REG(perpt),
10705 	MLXSW_REG(peabfe),
10706 	MLXSW_REG(perar),
10707 	MLXSW_REG(ptce3),
10708 	MLXSW_REG(percr),
10709 	MLXSW_REG(pererp),
10710 	MLXSW_REG(iedr),
10711 	MLXSW_REG(qpts),
10712 	MLXSW_REG(qpcr),
10713 	MLXSW_REG(qtct),
10714 	MLXSW_REG(qeec),
10715 	MLXSW_REG(qrwe),
10716 	MLXSW_REG(qpdsm),
10717 	MLXSW_REG(qpdp),
10718 	MLXSW_REG(qpdpm),
10719 	MLXSW_REG(qtctm),
10720 	MLXSW_REG(qpsc),
10721 	MLXSW_REG(pmlp),
10722 	MLXSW_REG(pmtu),
10723 	MLXSW_REG(ptys),
10724 	MLXSW_REG(ppad),
10725 	MLXSW_REG(paos),
10726 	MLXSW_REG(pfcc),
10727 	MLXSW_REG(ppcnt),
10728 	MLXSW_REG(plib),
10729 	MLXSW_REG(pptb),
10730 	MLXSW_REG(pbmc),
10731 	MLXSW_REG(pspa),
10732 	MLXSW_REG(pplr),
10733 	MLXSW_REG(pmtm),
10734 	MLXSW_REG(htgt),
10735 	MLXSW_REG(hpkt),
10736 	MLXSW_REG(rgcr),
10737 	MLXSW_REG(ritr),
10738 	MLXSW_REG(rtar),
10739 	MLXSW_REG(ratr),
10740 	MLXSW_REG(rtdp),
10741 	MLXSW_REG(rdpm),
10742 	MLXSW_REG(ricnt),
10743 	MLXSW_REG(rrcr),
10744 	MLXSW_REG(ralta),
10745 	MLXSW_REG(ralst),
10746 	MLXSW_REG(raltb),
10747 	MLXSW_REG(ralue),
10748 	MLXSW_REG(rauht),
10749 	MLXSW_REG(raleu),
10750 	MLXSW_REG(rauhtd),
10751 	MLXSW_REG(rigr2),
10752 	MLXSW_REG(recr2),
10753 	MLXSW_REG(rmft2),
10754 	MLXSW_REG(mfcr),
10755 	MLXSW_REG(mfsc),
10756 	MLXSW_REG(mfsm),
10757 	MLXSW_REG(mfsl),
10758 	MLXSW_REG(fore),
10759 	MLXSW_REG(mtcap),
10760 	MLXSW_REG(mtmp),
10761 	MLXSW_REG(mtbr),
10762 	MLXSW_REG(mcia),
10763 	MLXSW_REG(mpat),
10764 	MLXSW_REG(mpar),
10765 	MLXSW_REG(mgir),
10766 	MLXSW_REG(mrsr),
10767 	MLXSW_REG(mlcr),
10768 	MLXSW_REG(mtpps),
10769 	MLXSW_REG(mtutc),
10770 	MLXSW_REG(mpsc),
10771 	MLXSW_REG(mcqi),
10772 	MLXSW_REG(mcc),
10773 	MLXSW_REG(mcda),
10774 	MLXSW_REG(mgpc),
10775 	MLXSW_REG(mprs),
10776 	MLXSW_REG(mogcr),
10777 	MLXSW_REG(mtpppc),
10778 	MLXSW_REG(mtpptr),
10779 	MLXSW_REG(mtptpt),
10780 	MLXSW_REG(mgpir),
10781 	MLXSW_REG(tngcr),
10782 	MLXSW_REG(tnumt),
10783 	MLXSW_REG(tnqcr),
10784 	MLXSW_REG(tnqdr),
10785 	MLXSW_REG(tneem),
10786 	MLXSW_REG(tndem),
10787 	MLXSW_REG(tnpc),
10788 	MLXSW_REG(tigcr),
10789 	MLXSW_REG(tieem),
10790 	MLXSW_REG(tidem),
10791 	MLXSW_REG(sbpr),
10792 	MLXSW_REG(sbcm),
10793 	MLXSW_REG(sbpm),
10794 	MLXSW_REG(sbmm),
10795 	MLXSW_REG(sbsr),
10796 	MLXSW_REG(sbib),
10797 };
10798 
10799 static inline const char *mlxsw_reg_id_str(u16 reg_id)
10800 {
10801 	const struct mlxsw_reg_info *reg_info;
10802 	int i;
10803 
10804 	for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
10805 		reg_info = mlxsw_reg_infos[i];
10806 		if (reg_info->id == reg_id)
10807 			return reg_info->name;
10808 	}
10809 	return "*UNKNOWN*";
10810 }
10811 
10812 /* PUDE - Port Up / Down Event
10813  * ---------------------------
10814  * Reports the operational state change of a port.
10815  */
10816 #define MLXSW_REG_PUDE_LEN 0x10
10817 
10818 /* reg_pude_swid
10819  * Switch partition ID with which to associate the port.
10820  * Access: Index
10821  */
10822 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
10823 
10824 /* reg_pude_local_port
10825  * Local port number.
10826  * Access: Index
10827  */
10828 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
10829 
10830 /* reg_pude_admin_status
10831  * Port administrative state (the desired state).
10832  * 1 - Up.
10833  * 2 - Down.
10834  * 3 - Up once. This means that in case of link failure, the port won't go
10835  *     into polling mode, but will wait to be re-enabled by software.
10836  * 4 - Disabled by system. Can only be set by hardware.
10837  * Access: RO
10838  */
10839 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
10840 
10841 /* reg_pude_oper_status
10842  * Port operatioanl state.
10843  * 1 - Up.
10844  * 2 - Down.
10845  * 3 - Down by port failure. This means that the device will not let the
10846  *     port up again until explicitly specified by software.
10847  * Access: RO
10848  */
10849 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
10850 
10851 #endif
10852